Method for manufacturing package substrate and package substrate

Abstract

A method for manufacturing a package substrate according to embodiments of the present invention comprises: a step of preparing a glass substrate; a step of forming a plurality of defects on one surface of the glass substrate by irradiating a laser at regular intervals along the perimeter of an area where a through hole is to be formed on one surface of the glass substrate; and a step of etching the glass substrate to form a through hole penetrating the glass substrate, wherein, when observed on one surface of the glass substrate, the spacing between the defects adjacent to each other along the perimeter is 2 μm to 8 μm.

Description

Technology Field

[0001] The present invention relates to a method for manufacturing a package substrate and a package substrate manufactured therefrom. Background Technology

[0003] The semiconductor packaging process generally involves a series of assembly steps in which a wafer on which a semiconductor chip is formed is cut, mounted onto various interposers or substrates, and electrically connected to external circuits. In this back-end technology, the package substrate can function as a transmission path for electrical signals and as a supporting structure for the semiconductor package.

[0004] Traditionally, ceramic substrates or organic substrates such as resins have been primarily used. However, ceramics generally have high dielectric constants, making them unsuitable for high-frequency package structures where high-speed signals are transmitted. Furthermore, their high mechanical rigidity can lead to defects such as cracks during microstructure processing or thinning processes. Additionally, resin substrates have high coefficients of thermal expansion and low thermal conductivity, which degrade dimensional stability in high-temperature environments and make it difficult to implement fine-pitch structures.

[0005] As an alternative, glass-based package substrates are attracting attention. Glass is evaluated as a next-generation package material suitable for high-speed and high-density systems because it has a coefficient of thermal expansion similar to silicon and possesses excellent insulation properties and dimensional stability.

[0006] In addition, Through-Glass Via (TGV) technology, which forms through holes within a glass substrate, can be advantageous in terms of high-speed signal transmission, package miniaturization, and improved thermal characteristics. For example, the TGV structure can provide effects such as short wiring distance, low signal delay, and excellent electromagnetic shielding compared to conventional materials by precisely machining micro-holes that penetrate the glass substrate vertically and filling them with a conductive material to form an electrical path. Prior art literature

[0008] Republic of Korea Registered Patent Publication No. 10-1067109 The problem to be solved

[0009] The problem to be solved by the present invention is to provide a method for manufacturing a package substrate that forms a through hole having a predetermined surface roughness by etching the glass substrate after forming a laser defect on the glass substrate.

[0010] Another problem to be solved by the present invention is to provide a package substrate manufactured by the manufacturing method described above. means of solving the problem

[0012] A method for manufacturing a package substrate according to an embodiment of the present invention comprises: a step of preparing a glass substrate; a step of forming a plurality of defects on one surface of the glass substrate by irradiating a laser at regular intervals along the perimeter of an area where a through hole is to be formed on one surface of the glass substrate; and a step of etching the glass substrate to form a through hole penetrating the glass substrate, wherein, when observed on one surface of the glass substrate, the spacing between the defects adjacent to each other along the perimeter is 2 μm to 8 μm. Effects of the invention

[0014] According to an embodiment of the present invention, a laser is irradiated at regular intervals along the perimeter of an area where a through hole is to be formed on at least one surface of a glass substrate to form defects, and the glass substrate is etched to form a through hole. The spacing between the laser defects is adjusted to a specific range so that the surface roughness of the inner wall of the through hole can be adjusted to a desired range while simultaneously forming the through hole during the etching process. Accordingly, additional processes such as a surface roughening process for the through hole are not required, and the degradation of the physical properties of the glass substrate caused by this can be prevented.

[0015] In addition, as the inner wall of the through hole manufactured by the above-described method has a surface roughness within a specific range, the adhesion between the glass substrate and the conductive material filled in the internal space of the through hole can be improved, and the delamination or voids between the glass substrate and the conductive material can be reduced, thereby improving electrical properties. Brief explanation of the drawing

[0017] FIG. 1 is a schematic process flow diagram showing a method for manufacturing a package substrate according to some embodiments. FIG. 2 is a schematic cross-sectional view illustrating the process of forming a through hole during the manufacturing process of a package substrate according to some embodiments. FIG. 3 is a schematic plan view illustrating the process of forming a through hole during the manufacturing process of a package substrate according to some embodiments. FIG. 4 is a schematic cross-sectional view showing a glass substrate in which laser defects are formed during the manufacturing process of a package substrate according to some embodiments. FIG. 5 is a schematic cross-sectional view of a package substrate according to some embodiments. FIG. 6 is a schematic plan view of a package substrate according to some embodiments. Figure 7 is an enlarged view of area A of Figure 1. FIG. 8 is a schematic cross-sectional view of a package substrate according to some embodiments. FIG. 9 is a schematic cross-sectional view illustrating the process of forming via electrodes during the manufacturing process of a package substrate according to some embodiments. FIG. 10 is a schematic cross-sectional view of a package substrate according to some embodiments. FIG. 11 is a schematic cross-sectional view of a package substrate according to some embodiments. FIG. 12 is a schematic cross-sectional view of a package substrate according to some embodiments. FIGS. 13a to 13e are images of through holes in package substrates manufactured in Manufacturing Examples 2, 4, 6, 8, and 10, respectively. FIGS. 14a to 14e are 3D images of through holes in package substrates prepared in Manufacturing Examples 2, 4, 6, 8, and 10, respectively. Specific details for implementing the invention

[0018] The present invention will be described in detail below through various embodiments. The embodiments are not limited to those disclosed below and may be modified in various forms as long as the essence of the invention is not altered.

[0019] In this specification, terms referring to each component are used to distinguish it from other components and are not intended to limit the embodiments. Additionally, singular expressions in this specification include singular or plural expressions unless the context clearly indicates otherwise.

[0020] In this specification, when a part is described as "comprising" a certain component, this means that, unless specifically stated otherwise, it does not exclude other components but may include additional components.

[0021] All numerical ranges representing physical property values, dimensions, etc. of the components described in this specification should be understood to be modified by the term "approximately" in all cases unless otherwise specified.

[0022] In this specification, terms such as "first," "second," etc. are used to describe various components, and said components are not limited by said terms. These terms are used for the purpose of distinguishing one component from another.

[0023] In this specification, the description that one component is formed or positioned above or below another component includes both direct formation or indirect placement between these components through the interposition of another component. Furthermore, it should be understood that the reference for the top and bottom of each component may vary depending on the direction in which the object is observed.

[0024] The description in this specification that one component is connected to another component includes both direct and indirect connections between these components through another component.

[0025] In numerical ranges defining the size, physical properties, etc., of components described in this specification, if a numerical range in which only the upper limit is defined and a numerical range in which only the lower limit is defined are separately exemplified, it should be understood that a numerical range combining these upper and lower limits is also included in the exemplary range.

[0026] Additionally, the dimensions of each component in the drawings may be exaggerated for illustrative purposes and do not imply their actual dimensions. Furthermore, throughout the specification, the same reference numerals refer to the same components.

[0028] Method for manufacturing a package substrate

[0029] A method for manufacturing a package substrate according to embodiments of the present invention comprises the steps of: preparing a glass substrate; irradiating a laser at regular intervals along the perimeter of an area on one surface of the glass substrate to form a plurality of defects on said surface of the glass substrate; and etching the glass substrate to form a through hole penetrating the glass substrate, wherein, when observed on said surface of the glass substrate, the spacing between the defects adjacent to each other along the perimeter is 2 μm to 8 μm.

[0030] FIG. 1 is a schematic process flow diagram showing a method for manufacturing a package substrate according to some embodiments.

[0031] Referring to step S10 of FIG. 1, a glass substrate can be prepared as a support substrate or core substrate of a package substrate.

[0032] The above package substrate includes a glass substrate, which can suppress the occurrence of parasitic elements within the core and power loss resulting from the application of high-frequency power. Additionally, since the glass material has a low coefficient of thermal expansion and high hardness, thermal deformation of the package substrate can be prevented during the manufacturing process and subsequent packaging process. Accordingly, the breakage and defect rates of the glass substrate can be reduced, and integration density can be improved by forming finer and more precise patterns.

[0033] In one embodiment, the glass substrate may include alkali borosilicate, alkali-free borosilicate, alkali aluminosilicate, alkali-free aluminosilicate, alkali-free aluminoborosilicate, etc., but any plate glass material applied as an electronic component may be used without limitation. For example, the glass substrate may be manufactured by Schott, AGC, Corning, etc., but is not limited thereto.

[0034] In one embodiment, the thickness of the glass substrate may be 50 μm or more. For example, the thickness of the glass substrate may be 100 μm or more, 150 μm or more, 200 μm or more, 250 μm or more, 300 μm or more, 400 μm or more, or 500 μm or more. Additionally, the thickness of the glass substrate may be 3,000 μm or less. For example, the thickness of the glass substrate may be 2,500 μm or less, 2,000 μm or less, 1,500 μm or less, or 1,000 μm or less. Within the thickness range of the glass substrate, as the spacing between defects formed by laser irradiation is controlled to a range of 2 μm to 8 μm, the surface roughness characteristics of the inner wall of the through hole formed in the glass substrate through a subsequent etching process can be more easily controlled to a desired level.

[0035] Referring to step S20 of FIG. 1, a defect can be formed by irradiating a laser at a predetermined location on one side of a glass substrate. The predetermined location is set along the perimeter of the area where a through hole is to be formed.

[0036] Generally, glass substrates have low chemical reactivity, making it difficult to initiate etching, and consequently, selective etching of localized areas may be difficult. Additionally, when through holes are formed by mechanical drilling or etching alone, thermal and mechanical stress on the glass substrate is intensified, which may result in cracks, burrs, and process deposits on the glass substrate.

[0037] According to embodiments of the present invention, defects generated by laser irradiation can function as etching initiation points, thereby inducing etching of a glass substrate at a predetermined point. Additionally, by performing an etching process after forming local defects on the glass substrate through laser irradiation, etching reactivity is improved, and damage caused by etching is minimized, allowing for the formation of high-quality through holes.

[0038] Figure 2 is a schematic cross-sectional view illustrating the process of forming through holes during the manufacturing process of a package substrate.

[0039] Referring to FIG. 2 (a) and (b), a laser can be irradiated at regular intervals along the perimeter of a region (VH) on one side of a glass substrate (110) to be formed through holes. Accordingly, a plurality of defects (50) can be formed spaced apart at regular intervals along the perimeter of the VH region.

[0040] FIG. 3 is a schematic plan view for explaining the process of forming a through hole during the manufacturing process of a package substrate. Specifically, FIG. 2(b) is a cross-sectional view of a glass substrate (110) cut along the BB' line of FIG. 3.

[0041] In a subsequent process of etching the glass substrate, the portion where the defect is formed can be removed, for example, by reacting with an etching solution. Accordingly, by forming a plurality of defects (50) along the perimeter of the region (VH) where a through hole is to be formed, the defect (50) may enlarge or expand during the etching process and meet with an adjacent defect (50), and accordingly, the VH region may be removed from the glass substrate (110). For example, the process of forming the through hole may be performed by a laser-assisted etching or laser-induced etching method.

[0042] According to embodiments of the present invention, when observed on one side of the glass substrate (110), the spacing (D) between adjacent defects (50) along the perimeter of the VH region is 2 μm to 8 μm. Within this range, the surface roughness of the inner wall of the through hole formed after the etching process is controlled to a desired range, thereby enabling the realization of a through hole having a structure with improved mechanical and electrical properties.

[0043] Meanwhile, when the package substrate is applied to semiconductor packages or the like, conductive materials such as metal may be filled into the through-holes to implement electrical signal transmission paths within the glass substrate. However, as conductive materials have low adhesion to glass, problems such as interfacial delamination between the glass substrate and the conductive material and degradation of plating quality may occur within the through-holes.

[0044] According to embodiments of the present invention, defects are first formed at regular intervals on one surface of a glass substrate using a laser, and then through holes are formed through an etching process, thereby forming an irregular structure with appropriately controlled irregularity on the inner wall of the through holes. Accordingly, a stable interlocking structure can be formed between the inner wall of the through holes and the conductive material due to a mechanical anchoring effect. Therefore, the conductive material can be adhered more uniformly to the glass substrate, and the peel resistance and electrical reliability of the vias can be improved.

[0045] For example, if the spacing (D) between defects (50) is less than 2 μm, the surface roughness of the inner wall of the through hole may increase excessively. For example, as the spacing between defects becomes excessively short, adjacent defects may meet quickly during a subsequent etching process. Consequently, the etching time until the through hole is formed may decrease, making it difficult to achieve uniform and even etching across the entire inner wall of the through hole. Additionally, if the etching time for the glass substrate is increased, non-uniform etching may occur in localized areas due to over-etching. In this case, the adhesion and bonding between the conductive material filled inside the through hole and the glass substrate may decrease, and the plating quality and electrical properties may deteriorate.

[0046] For example, if the spacing (D) between defects (50) is greater than 8 μm, the number of defects within the same area decreases, and the etching reaction is not sufficiently induced, which may result in a decrease in the etching rate or problems such as opening defects due to incomplete etching. Additionally, if etching is performed under harsher conditions to form an opening, damage due to over-etching may occur in the surrounding area outside the area where the through hole is formed, or surface characteristics and physical properties may change, which may lead to deterioration of electrical and thermal properties.

[0047] In one embodiment, the spacing (D) between adjacent defects (50) along the perimeter of the VH region may be greater than 2 μm or greater than 2.5 μm, and preferably greater than 3 μm, greater than 3.5 μm, or greater than 4 μm. Additionally, the spacing (D) between the defects (50) may be less than 6 μm, less than 6 μm, or less than 5.5 μm, and preferably less than 5 μm or less than 4.5 μm.

[0048] For example, the spacing (D) between adjacent defects (50) along the perimeter of the VH region may be 2 μm to 6 μm, greater than 2 μm and less than 6 μm, greater than 2 μm and less than 6 μm, 2.5 μm to 5.5 μm, 2.5 μm to 5 μm, 3 μm to 5 μm, 3 μm to 4.5 μm, 3.5 μm to 4.5 μm, or 4 μm to 4.5 μm.

[0049] Within the above range, the roughness of the inner wall of the through hole can be controlled to a desired range. For example, the centerline average roughness (Ra) of the inner wall of the through hole formed after the etching process may be greater than 0.2 μm and less than or equal to 2.0 μm. In addition, the 10-point average roughness (Rz) of the inner wall of the through hole may be less than or equal to 10 μm. Accordingly, the conductive material can be adhered to the glass substrate more uniformly and stably by means of a mechanical anchoring effect between the inner wall of the through hole and the conductive material, thereby improving stability and electrical reliability.

[0050] In one embodiment, by setting an appropriate defect spacing (D) by comprehensively considering the diameter of the VH region, the width of the through hole to be formed, or the thickness of the glass substrate, the surface roughness characteristics of the inner wall of the through hole after the etching process can be controlled more stably and reproducibly to a desired level. For example, the defect spacing (D) in the range described above may be a preferred spacing for forming a through hole having a width of 40 μm to 250 μm.

[0051] For example, in a process of forming a through hole having a width of 40 μm to 250 μm in a glass substrate (110) with a thickness of 50 μm to 3,000 μm, defects (50) are formed at a spacing (D) of the range described above by irradiation with a laser, and thus surface roughness characteristics described above can be obtained on the inner wall of the through hole. In one example, a preferred defect spacing (D) for forming a through hole having a width of 140 μm and specific surface roughness characteristics described below in a glass substrate (110) with a thickness of 0.53 t may be 2 μm to 8 μm.

[0052] In one embodiment, the diameter of the VH region may be 40 μm or more, 60 μm or more, 80 μm or more, or 100 μm or more, and may be 250 μm or less, 230 μm or less, 210 μm or less, 200 μm or less, 180 μm or less, 160 μm or less, or 140 μm or less.

[0053] For example, the diameter of the VH region may be 40 µm to 250 µm, 40 µm to 230 µm, 40 µm to 210 µm, 40 µm to 200 µm, 60 µm to 180 µm, 80 µm to 160 µm, or 100 µm to 140 µm. As defects (50) are formed along the perimeter of the VH region having the diameter of the above range at intervals (D) of the above range, the surface roughness characteristics of the inner wall of the through hole can be more easily adjusted to a desired range.

[0054] In one embodiment, the ratio (D / W) of the diameter (W) of the VH region and the spacing (D) between the defects (50) may be 0.014 to 0.2, 0.014 to 0.15, 0.014 to 0.125, 0.014 to 0.1, 0.014 to 0.06, or 0.014 to 0.045, 0.015 to 0.045, 0.02 to 0.04, 0.02 to 0.035, 0.02 to 0.032, 0.02 to 0.030, 0.025 to 0.030, or 0.025 to 0.029. As defects are formed at appropriate intervals relative to the perimeter length of the VH region within the above range, etching defects are suppressed during the subsequent etching process, and through holes having a uniform shape corresponding to the VH region can be formed, and furthermore, the surface roughness of the inner wall of the through hole can be easily adjusted to a desired range.

[0055] In one embodiment, the diameter of the VH region may be substantially the same as the diameter of the through hole to be formed in a subsequent process.

[0056] In some embodiments, the defect (50) may include cracks, microcracks, etc. formed by laser irradiation. Additionally, the defect (50) may include a region having a density or chemical bonding state different from other regions of the glass substrate that are not irradiated by laser irradiation, as the density or chemical bonding state changes due to laser irradiation.

[0057] FIG. 4 is a schematic cross-sectional view showing a glass substrate in which laser defects are formed during the manufacturing process of a package substrate according to some embodiments.

[0058] Referring to FIG. 4(a), the defect (50) may have a shape that is recessed inward from the surface of the glass substrate (110). For example, each of the defects (50) may have a groove shape that extends in a direction perpendicular to the surface of the glass substrate (110) through drilling by laser irradiation.

[0059] Referring to FIG. 4(b), the defect (50) can penetrate the glass substrate (110). For example, the defect (50) may have a pillar shape that penetrates from one side of the glass substrate (110) to the other side.

[0060] Referring to FIG. 4(c), a plurality of defects may be further formed on the other side of the glass substrate (110). For example, the step of irradiating a laser at regular intervals along the perimeter of the area (VH) where the through hole is to be formed on the other side of the glass substrate (110) may be further included.

[0061] As the defect (50) caused by the laser irradiation is formed on both sides of the glass substrate (110), the etching proceeds simultaneously on both sides of the glass substrate in the subsequent etching process, and as the etching reaction is concentrated locally, the etching speed is improved and the total etching time required to form through holes can be shortened.

[0062] In one embodiment, a plurality of defects (50) formed on one surface of the glass substrate (110) and a plurality of defects formed on the other surface of the glass substrate (110) may overlap each other in the thickness direction of the glass substrate (110). Accordingly, as the etching start point is precisely controlled on both sides of the glass substrate (110), the diameter variation of the through hole on both sides of the glass substrate can be reduced and the shape precision can be improved. In addition, substrate damage and quality degradation due to unnecessary over-etching can be prevented.

[0063] Meanwhile, if the defect (50) is formed on both sides of the glass substrate (110), a through hole with an hourglass-shaped cross section may be formed.

[0064] The laser can be irradiated perpendicularly to one surface of the glass substrate (110). Accordingly, a defect extending along the thickness direction from one surface of the glass substrate (110) can be formed. Thus, the diameter, perpendicularity, taper, etc. of the through hole can be easily controlled, and through a subsequent etching process, a through hole with high precision and dimensional stability can be formed.

[0065] In one embodiment, the wavelength of the laser may be 290 nm to 330 nm, and for example, a 308 nm XeCl excimer laser may be used, but is not limited thereto. Additionally, to form each defect (50), a laser having the above-described wavelength has an energy density of 1 J / cm² 2 up to 10 J / cm 2 It can be irradiated for 5 to 20 seconds under conditions of a pulse of 5 ns to 20 ns and a spot size of 5 µm to 30 µm.

[0066] Referring to step S30 of FIG. 1, the defective glass substrate can be etched to form a through hole penetrating the glass substrate. For example, the defective region has deteriorated chemical stability compared to the non-defective region, and reactivity to the etching solution may increase due to fine structural defects such as cracks, pores, and reduced density. Therefore, selective etching of the glass substrate occurs centered on the defective region, and a through hole can be formed to correspond to the VH region.

[0067] Referring to FIG. 2 (c) and (d), as the defect (50) formed along the perimeter of the VH region is etched into the glass substrate (110), a through hole (120) penetrating the glass substrate (110) can be formed to correspond to the VH region as the defect (50) is enlarged or expanded during the etching process.

[0068] The above etching can be performed by wet etching using an etchant. The etchant is not limited to any that can be conventionally applied to etch a glass substrate. For example, the etchant may include a sulfuric acid solution, a nitric acid solution, a hydrofluoric acid solution, etc.

[0069] In one embodiment, the wet etching may be performed by immersing a glass substrate in an etching solution containing hydrofluoric acid and / or nitric acid and applying ultrasonic treatment, etc. For example, the concentration of hydrofluoric acid in the etching solution may be 0.5 M or more, or 1.1 M or more, and 3 M or less, or 2 M or less. For example, the concentration of nitric acid in the etching solution may be 0.5 M or more, or 1 M or more, and 2 M or less. The ultrasonic treatment may be performed at a frequency of 40 Hz to 120 Hz, or 60 Hz to 100 Hz.

[0070] In the above etching process, a mask pattern can be applied to the remaining surface of the glass substrate (110), excluding the region (VH) where a through hole is to be formed, to prevent etching of the remaining surface. Additionally, etching can be performed without a mask pattern.

[0071] Generally, when through holes are formed in a thin glass substrate, localized stress concentration occurs during the processing of the glass substrate, which may weaken the mechanical properties of the glass substrate or cause microcracks. Consequently, processability and workability may be degraded during the manufacturing and packaging processes of the package substrate.

[0072] According to embodiments of the present invention, by irradiating a laser at regular intervals in an area where a through hole is to be formed to first form a defect, and then performing etching on the glass substrate, workability and processability can be improved while preventing the deterioration of the mechanical properties of the glass substrate.

[0073] According to some embodiments, an additional roughening process for the through hole may not be included after forming the through hole. The additional roughening process may refer to a mechanical or chemical process performed on the inner wall of the through hole after forming the through hole, such as a polishing process using sandpaper or abrasive paper, sandblasting, chemical etching, ion beam etching, laser etching, etc.

[0074] If additional processes, such as additional surface roughening on the sidewalls of the through-holes, are performed after forming through-holes in a glass substrate, the mechanical properties of the glass substrate may be weakened or the thermal properties may change. Furthermore, roughness may be imparted not only to the sidewalls of the through-holes but also to other surfaces of the glass substrate requiring flatness due to the surface roughening process; as the process becomes more complex for partial surface roughening, processability may be reduced.

[0075] According to embodiments of the present invention, the roughness of the inner wall of a through hole can be controlled by adjusting the laser irradiation interval during the process of forming a through hole in a glass substrate. Accordingly, the surface roughness of the inner wall of the through hole can be controlled to a desired range while simultaneously forming the through hole, thereby eliminating the need for additional processes such as a roughening process for the through hole, and preventing the degradation of the physical properties of the glass substrate caused by this.

[0076] FIG. 5 is a schematic cross-sectional view of a package substrate according to some embodiments. For example, FIG. 5 is a schematic drawing showing a glass substrate with through holes formed therein.

[0077] FIG. 6 is a schematic plan view of a package substrate according to some embodiments. For example, FIG. 5 is a cross-sectional view observed by cutting the package substrate along the C-C' line of FIG. 6.

[0078] Referring to FIG. 5, the glass substrate (110) includes a first surface (112) and a second surface (114) facing each other. The first surface (112) and the second surface (114) may face each other in the thickness direction of the glass substrate (110).

[0079] The glass substrate (110) may include a side formed in the thickness direction, which is connected to the first surface (112) and the second surface (114), respectively. The side may be a plane perpendicular to the first surface (112) and the second surface (114), or an inclined surface inclined at a predetermined angle with respect to the first surface (112) and the second surface (114). Additionally, the side may be a curved surface.

[0080] The first surface (112) and the second surface (114) of the glass substrate (110) may be parallel to each other. Accordingly, the glass substrate (110) may have a substantially constant thickness overall.

[0081] The through hole (120) can penetrate the glass substrate (110) in the thickness direction, that is, from the first surface (112) to the second surface (114). The through hole (120) is a via formed for electrical connection of the upper and lower parts of the package substrate, and may be referred to, for example, as a TGV (through glass via).

[0082] The through hole (120) includes an internal space (124) and an inner wall (122) surrounding the internal space (124). The internal space (124) of the through hole (120) refers to an empty space. The inner wall (122) of the through hole (120) refers to the side wall of the glass substrate (110) where the through hole (120) is defined, that is, the surface of the glass substrate (110) at the interface between the glass substrate (110) and the through hole (120).

[0083] Figure 7 is an enlarged view of area A of Figure 5.

[0084] Referring to FIG. 7, as the through hole (120) is formed by the manufacturing method described above, the cross-sectional profile of the inner wall (122) of the through hole (120) may have an irregular shape.

[0085] According to one embodiment, as the spacing between defects (50) formed along the perimeter of the VH region is adjusted to the range described above, the centerline average roughness (Ra) of the inner wall (122) of the through hole (120) can be controlled to be greater than 0.2 μm and less than or equal to 2.0 μm.

[0086] When the Ra of the inner wall of the through hole is 0.2 μm or less, the mechanical anchoring effect between the glass substrate and the conductive material within the through hole may not be substantially provided. Consequently, delamination or voids may increase at the interface between the glass substrate and the conductive material, and electrical reliability and stability may be reduced. Furthermore, as the bonding surface between the glass substrate and the conductive material becomes relatively flat and the bonding area decreases, it becomes difficult to disperse the stress accumulated on the bonding surface, which may lead to localized delamination or cracking during the subsequent packaging process.

[0087] In addition, if the Ra of the inner wall of the through hole exceeds 2.0 μm, the height variation of the inner wall of the through hole increases excessively, which may actually reduce the adhesion of the conductive material to the glass substrate. Furthermore, if the roughness of the inner wall of the through hole becomes excessively high, the cross-sectional profile of the conductive material formed on the inner wall may become rough. In this case, voids may be formed inside the conductive material or the flow of current may be distorted, causing the resistance to increase.

[0088] In some embodiments, Ra of the inner wall (122) of the through hole (120) may be greater than 0.2 μm and less than or equal to 1.8 μm, 0.25 μm to 1.6 μm, 0.25 μm to 1.4 μm, 0.25 μm to 1.3 μm, 0.25 μm to 1.2 μm, 0.3 μm to 1.0 μm, 0.3 μm to 0.8 μm, 0.3 μm to 0.6 μm, 0.3 μm to 0.55 μm, 0.4 μm to 0.55 μm, or 0.45 μm to 0.55 μm. Within the above range, a more stable bonding structure can be formed between the conductive material formed inside the through hole (120) and the glass substrate (110), and the area of ​​contact between the conductive material and the glass substrate (110) can be further increased, thereby further improving structural stability, electrical reliability, and low resistance characteristics.

[0089] The above centerline average roughness (Ra) was obtained using a laser microscope ISO 21920 Measurements can be taken according to the specifications. The above laser microscope may include the KEYENCE VK-X3000, but is not limited thereto.

[0090] The centerline average roughness (Ra) of the inner wall (122) of the through hole (120) may be measured for a glass substrate having a thickness of 50 μm to 3,000 μm and a through hole having a width of 40 μm to 250 μm. Specifically, the centerline average roughness (Ra) may be measured for a glass substrate with a thickness of 0.53t and a through hole with a width of 140 μm.

[0091] Meanwhile, considering the local deviation of the inner wall (122) of the through hole (120), the Ra value may be measured multiple times in different areas of the inner wall (122) of the through hole (120), and the average of the measured values ​​may be used as the Ra of the inner wall (122) of the through hole (120). For example, the inner wall (122) of the through hole (120) may include a plurality of arbitrarily selected measurement areas, and the Ra of the inner wall (122) may be obtained by averaging the Ra values ​​of each measurement area. Each of the above measurement areas may have a line shape extending in the thickness direction of the glass substrate (110).

[0092] In some embodiments, the inner wall (122) of the through hole (120) includes a total of three arbitrarily selected measurement areas, and when the Ra values ​​of each measurement area are measured, the standard deviation of the Ra values ​​may be 0.3 μm or less. The standard deviation may be the sample standard deviation.

[0093] The standard deviation of the above Ra values ​​may indicate the uniformity of roughness over the entire area of ​​the inner wall (122). For example, the smaller the standard deviation of the above Ra values, the more uniform the roughness value of the inner wall (122) of the through hole (120) may be, and the larger the standard deviation of the above Ra values, the greater the difference in roughness value in the local area of ​​the inner wall (122).

[0094] As the standard deviation of the Ra values ​​measured at the inner wall (122) of the through hole (120) is 0.3 μm or less, the thickness distribution and bonding characteristics of the plating layer can be uniform throughout the inner wall during the plating and filling process of the conductive material. In addition, the mechanical anchoring effect of the conductive material on the glass substrate (110) is formed similarly throughout the inside of the through hole (120), so that the stress acting on the interface can be more evenly distributed. Accordingly, stress concentration in localized areas can be relieved, thereby further suppressing peeling and cracking.

[0095] The standard deviation of the above Ra values ​​may be 0.15 μm or less. Accordingly, the uniformity of bonding of the conductive material to the inner wall (122) of the through hole (120) is further improved, and stress concentration is further relieved, thereby suppressing localized delamination and voids.

[0096] For example, the standard deviation of the above Ra values ​​may be 0.13 μm or less, 0.1 μm or less, 0.08 μm or less, 0.06 μm or less, or 0.05 μm or less. Additionally, the standard deviation of the above Ra values ​​may be 0.01 μm or more, or 0.02 μm or more.

[0097] In one embodiment, the 10-point average roughness (Rz) of the inner wall (122) of the through hole (120) may be 10 μm or less. Accordingly, a conductive material can be plated uniformly and stably along the inner wall (122) of the through hole (120), and a uniform bond between the glass substrate (110) and the conductive material can be ensured.

[0098] For example, the above 10-point average roughness (Rz) represents the average distance between the five highest peaks and the five deepest valleys in the cross-sectional roughness profile. If the Rz of the inner wall (122) of the through hole (120) is excessively large, plating non-uniformity and bonding defects may occur due to local deep or high irregularities, and long-term reliability may be reduced.

[0099] In some embodiments, the Rz of the inner wall (122) of the through hole (120) may be 0.5 μm to 10 μm, 0.5 μm to 9 μm, 0.5 μm to 8 μm, 0.5 μm to 7.5 μm, 0.5 μm to 6.5 μm, 0.5 μm to 5 μm, 0.5 μm to 4 μm, 0.5 μm to 3.5 μm, 0.5 μm to 3.5 μm, 1 μm to 3.5 μm, 1.5 μm to 3.5 μm, or 2 μm to 3.5 μm.

[0100] As irregularities of appropriate height and depth are formed on the inner wall (122) of the through hole (120) within the above range, mechanical anchoring of the conductive material to the glass substrate (110) is more stably secured, and the bonding strength can be further improved. In addition, due to structural stress distribution by peaks and valleys at the bonding interface, mechanical stability at the bonding interface is further enhanced, and cracks caused by thermal and electrical expansion can be further suppressed.

[0101] The 10-point average roughness (Rz) of the inner wall (122) of the through hole (120) may be measured for a glass substrate having a thickness of 50 μm to 3,000 μm and a through hole having a width of 40 μm to 250 μm. Specifically, the 10-point average roughness (Rz) may be measured for a glass substrate (110) with a thickness of 0.53t and a through hole with a width of 140 μm.

[0102] The above 10-point average roughness (Rz) was obtained using a laser microscope ISO 21920 Measurements can be taken according to the specifications, and the above laser microscope can be the KEYENCE VK-X3000, etc.

[0103] Specifically, the Rz value can be measured multiple times at the inner wall (122) of the through hole (120), and the average of the measured Rz values ​​can be used as the Rz of the inner wall (122). For example, the inner wall (122) of the through hole (120) may include a plurality of arbitrarily selected measurement areas, and the Rz of the inner wall (122) may be obtained by averaging the Rz values ​​of each measurement area. Each of the measurement areas may have a line shape extending in the thickness direction of the glass substrate (110).

[0104] In some embodiments, the inner wall (122) of the through hole (120) includes a total of three arbitrarily selected measurement areas, and when the Rz values ​​of each measurement area are measured, the standard deviation of the Rz values ​​may be 3 μm or less. Accordingly, a conductive material may be uniformly deposited or formed over the entire inner wall (122) of the through hole (120), and bonding strength and resistance characteristics may be evenly displayed. The standard deviation may be a sample standard deviation.

[0105] For example, the standard deviation of the above Rz values ​​may be 2.5 μm or less, 2 μm or less, 1.5 μm or less, 1 μm or less, 0.5 μm or less, 0.4 μm or less, or 0.3 μm or less. Additionally, the standard deviation of the above Rz values ​​may be 0.1 μm or more, or 0.2 μm or more. Within the above range, the height may be uniform overall on the inner wall (122) of the through hole (120) while providing irregularities of an appropriate size, thereby further improving the adhesion of the conductive material to the glass substrate (110).

[0106] In some embodiments, the ratio of Rz to Ra (Rz / Ra) of the inner wall (122) of the through hole (120) may be 5.0 or higher. The Rz / Ra can quantitatively indicate the uniformity of the roughness distribution of the through hole (120) and the size distribution of local irregularities. For example, the lower the Rz / Ra value, the more uniform and smooth the irregularity distribution of the inner wall (122) of the through hole (120) may be, and the higher the Rz / Ra value, the greater the variation in the size of the irregularities in local areas may be.

[0107] Preferably, the Rz / Ra of the inner wall (122) of the through hole (120) may be 5.5 or higher, 5.7 or higher, 5.9 or higher, 6 or higher, or 6.2 or higher, and may be 10 or lower, 8 or lower, 7.5 or lower, 7 or lower, or 6.6 or lower. Within the above range, as the uneven structure has an appropriate height variation, the bonding strength to the plating layer, etc. is further improved, and the uneven size can be uniform throughout the inner wall (122), thereby suppressing localized peeling, defects, and cracks, and further enhancing the uniformity of the plating layer.

[0108] The through hole (120) may include a first opening (126) in contact with a first surface (112) of the glass substrate (110), and a second opening (128) in contact with a second surface (114) of the glass substrate (110).

[0109] For example, the first opening (126) is a surface exposed through the first surface (112) of the glass substrate (110) and may be located on the same plane as the first surface (112). Additionally, the second opening (128) is a surface exposed through the second surface (114) of the glass substrate (110) and may be located on the same plane as the second surface (114).

[0110] The first opening (126) and the second opening (128) may have various shapes such as a circle, ellipse, rectangle, square, rhombus, parallelogram, triangle, etc. In one embodiment, the shape of the first opening (126) and the second opening (128) may be circular or elliptical, and specifically, may be circular.

[0111] In one embodiment, the first opening (126) and the second opening (128) may have the same shape as each other.

[0112] The width (W1) of the first opening (126) and the width (W2) of the second opening (128) may be substantially the same. Additionally, the width (W1) of the first opening (126) and the width (W2) of the second opening (128) may be substantially similar to the diameter of the VH region.

[0113] The width (W1) of the first opening (126) and the width (W2) of the second opening (128) may each be 40 μm to 250 μm, 40 μm to 230 μm, 40 μm to 210 μm, 40 μm to 200 μm, 60 μm to 180 μm, 80 μm to 160 μm, or 100 μm to 140 μm. Within the above range, the package substrate may be more highly integrated, and electrical characteristics and reliability may be further improved.

[0114] In one embodiment, the width or diameter of the through hole (120) in the thickness direction of the glass substrate (110) may be substantially constant. Specifically, the entire area of ​​the through hole (120) may have the same diameter as the diameter (W1) of the first opening (126) and the diameter (W2) of the second opening (128).

[0115] The through hole (120) may have a column shape, specifically a cylinder shape. For example, the cross-section of the through hole (120) may have a square or rectangular shape.

[0116] In one embodiment, the width or diameter of the through hole (120) may vary in the thickness direction of the glass substrate (110). For example, the width or diameter of the through hole (120) may gradually decrease and then increase again in the direction from the first opening (126) toward the second opening (128). In this case, the cross-section of the through hole (120) may have an hourglass shape.

[0117] In one embodiment, the first opening (126) and the second opening (128) may overlap each other in the thickness direction of the glass substrate (110). For example, the through hole (120) may extend parallel to the thickness direction of the glass substrate (110).

[0118] In one embodiment, the through hole (120) may be extended at a predetermined angle of inclination with respect to the thickness direction of the glass substrate (110), in which case the first opening (126) and the second opening (128) may partially overlap or not overlap in the thickness direction of the glass substrate (110).

[0119] Referring to step S40 of FIG. 1, a via electrode can be formed inside the through hole. For example, FIG. 8 is a schematic cross-sectional view showing a package substrate having a via electrode formed thereon.

[0120] Referring to FIG. 8, the package substrate may include a via electrode (130) that fills at least a portion of the internal space (124) of the through hole (120).

[0121] The via electrode (130) can cover the inner wall (122) of the through hole (120). For example, the via electrode (130) can come into direct contact with the inner wall (122) of the through hole (120). As the inner wall (122) of the through hole (120) satisfies the roughness described above, a mechanical anchoring effect between the inner wall (122) and the via electrode (130) can be provided, so that the via electrode (130) can be stably adhered or bonded to the glass substrate (110).

[0122] The upper and lower portions of the glass substrate (110) can be electrically connected through via electrodes (130). For example, the via electrodes (130) may be connection terminals for vertical electrical connection within the package substrate.

[0123] In some embodiments, the step of forming a via electrode (e.g., step S40) may include the step of forming a seed layer along the inner wall of the through hole, and the step of forming an electrically conductive layer inside the through hole using the seed layer. For example, the via electrode may include a seed layer and an electrically conductive layer formed on the seed layer.

[0124] FIG. 9 is a schematic cross-sectional view illustrating the process of forming via electrodes during the manufacturing process of a package substrate according to some embodiments.

[0125] Referring to FIG. 9(a), a seed layer (132) can be formed along the inner wall (122) of the through hole (120). For example, the seed layer (132) can be formed to uniformly cover the inner wall (122) of the through hole (120).

[0126] In the process of forming the through hole (e.g., step S20), a through hole having specific surface characteristics can be formed by forming defects at regular intervals by laser irradiation, and accordingly, the seed layer (132) can be stably adhered to the glass substrate (110) by an anchoring effect in which the surface irregularities of the inner wall (122) and the metal particles of the seed layer (132) interact with each other.

[0127] In one embodiment, the seed layer (132) may be formed in a dry manner. For example, the seed layer (132) may be formed through a deposition process such as Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), or Atomic Layer Deposition (ALD). For example, it may be formed by sputtering a metal element along the inner wall (122) of the through hole (120).

[0128] The seed layer (132) may include metals such as copper (Cu), aluminum (Al), chromium (Cr), nickel (Ni), tungsten (W), titanium (Ti), tantalum (Ta), indium (In), molybdenum (Mo), cobalt (Co), tin (Sn), magnesium (Mg), silver (Ag), and gold (Au), or alloys thereof, but is not limited thereto.

[0129] Referring to FIG. 9(c), an electrically conductive layer (134) can be formed on the seed layer (132). The electrically conductive layer (134) can be formed by a plating method using the seed layer (132). Although the seed layer (132) and the electrically conductive layer (134) are distinguished by solid lines in FIG. 9, the seed layer (132) and the electrically conductive layer (134) may be integrated with each other during the plating process to form a one-body shape without distinction between layers.

[0130] The electrically conductive layer (134) comprises a conductive material. For example, the electrically conductive layer (134) may comprise metals such as copper (Cu), aluminum (Al), chromium (Cr), nickel (Ni), tungsten (W), titanium (Ti), tantalum (Ta), indium (In), molybdenum (Mo), cobalt (Co), tin (Sn), magnesium (Mg), silver (Ag), gold (Au), or alloys thereof, but is not limited thereto.

[0131] The thickness of the electrically conductive layer (134) can be controlled by adjusting various process conditions, such as the concentration of the plating solution, the plating time, and the type of additive included in the plating solution, during the plating process.

[0132] In some embodiments, the seed layer (132) may include a metal element included in the electrically conductive layer (134). In some embodiments, the seed layer (132) may include an element different from the metal element included in the electrically conductive layer (134).

[0133] Meanwhile, referring to FIG. 9 (b) and (d), a mask pattern (135) may be formed in a portion where the formation of the electrically conductive layer (134) is unnecessary before the plating process. The mask pattern (135) may include an insulating material. In this case, the mask pattern (135) can be removed after the electrically conductive layer (134) is formed.

[0134] In some embodiments, the via electrode (130) may fill the entire internal space (124) of the through hole (120). For example, only the via electrode (130) may exist within the internal space (124) of the through hole (120).

[0135] FIG. 10 is a schematic cross-sectional view of a package substrate according to some embodiments.

[0136] Referring to FIG. 10, the via electrode (130) may fill only a portion of the internal space (124) of the through hole (120). For example, the via electrode (130) in the internal space (124) of the through hole (120) may have a hollow column shape formed along the inner wall (122) of the through hole (120). For example, when observed in a direction perpendicular to the thickness direction of the glass substrate (120), the cross-section of the via electrode (130) may have a circular, elliptical, or square ring shape.

[0137] When the via electrode (130) is formed only in a part of the internal space (124) of the through hole (120), an insulating layer may be disposed in the remaining space. For example, the via electrode (130) may be disposed adjacent to the inner wall (122) of the through hole (120), and an insulating layer may be disposed in the space surrounded by the via electrode (130).

[0138] FIG. 11 is a schematic cross-sectional view of a package substrate according to some embodiments.

[0139] Referring to FIG. 11, the through hole (130) may have a shape in which the width gradually decreases from the first opening to the second opening and then increases again. Additionally, the cross-section of the via electrode (130) filled in the through hole (130) may have an hourglass shape.

[0140] FIG. 12 is a schematic cross-sectional view of a package substrate according to some embodiments.

[0141] Referring to FIG. 12, the package substrate includes a core layer (100). The core layer (100) includes a glass substrate (110) and a through hole (120). The core layer (100) may include a via electrode (130) filled inside the through hole (120).

[0142] The core layer (100) can serve as an intermediate or intermediary connecting the upper and lower parts of the package substrate within the package substrate. For example, the via electrode (130) of the core layer (100) can function as a passage for transmitting electrical signals between the upper and lower parts within the package substrate.

[0143] The core layer (100) may further include via pads (140) connected to via electrodes (130) and disposed on one or both sides of the glass substrate (110). The via pads (140) may be formed to have a width longer or a wider area than the opening of the through hole (120). Thus, electrical connectivity and reliability may be further improved by the via pads (140).

[0144] The via pad (140) can be formed together with the via electrode (130). For example, the via electrode (130) and the via pad (140) can be formed together through electroplating using the same seed layer.

[0145] A method for manufacturing a package substrate according to embodiments of the present invention may further include a step of manufacturing an upper layer.

[0146] For example, the package substrate may include an upper layer (200) disposed on one side of the core layer (100).

[0147] The upper layer (200) may include an upper insulating layer (210) covering one side of the core layer (100). For example, the upper layer manufacturing step may include the step of forming an upper insulating layer on the core layer. The upper insulating layer may be formed by coating a resin composition on the core layer or by laminating an insulating film.

[0148] In one embodiment, the upper insulating layer (210) may include a build-up layer material such as an epoxy resin or an imide resin, but is not limited thereto, and any material that functions as an insulator for a semiconductor device or a package substrate may be applied as the upper insulating layer (210).

[0149] The upper layer (200) may further include an upper redistribution layer (220) that is at least partially embedded in the upper insulating layer (210). The upper redistribution layer (220) may be electrically connected to a via electrode (130).

[0150] For example, the upper layer manufacturing step can be formed by repeating the process of forming an electrically conductive layer in a predetermined pattern on the upper insulating layer and etching unnecessary parts to form an etched layer of the electrically conductive layer.

[0151] In one embodiment, upper redistribution layers arranged adjacent to each other with an upper insulating layer in between can be formed by forming via holes in the upper insulating layer and filling the via holes through a plating process. The via holes can be formed by dry methods such as laser etching or plasma etching, or wet methods using a mask pattern and an etching solution.

[0152] The upper redistribution layer (220) may be composed of a plurality of layers along the thickness direction of the package substrate. For example, the upper redistribution layer (220) may have a 2-layer structure, a 3-layer structure, a 4-layer structure, a 5-layer structure, or a multilayer structure of 6 layers or more.

[0153] For example, in the case of a four-layer structure, the upper redistribution layer (220) may include a first upper redistribution layer (220a), a second upper redistribution layer (220b), a third upper redistribution layer (220c), and a fourth upper redistribution layer (220d) that are sequentially stacked and connected from one side of the core layer (100).

[0154] In FIG. 12, the upper insulating layer (210) is depicted as a single layer, but the upper insulating layer (210) may be composed of multiple layers. When the upper insulating layer (210) is composed of multiple layers, multiple upper redistribution layers (220) may be disposed on at least one of the upper and lower surfaces of each layer of the upper insulating layer (210).

[0155] The outermost upper redistribution layer (220) in the thickness direction of the package substrate may be exposed from the upper surface of the upper layer (200). The outermost upper redistribution layer (220) may function as a connection electrode connected to a connection terminal of a semiconductor device, etc.

[0156] In one embodiment, the upper layer (200) may further include an upper cover layer (230). The upper cover layer (230) may protect the surface circuit of the package substrate from the external environment. The upper cover layer (230) may include an opening that exposes the outermost upper redistribution layer (220). Through the opening, the outermost upper redistribution layer (220) and a connection terminal of an external component may be connected.

[0157] The upper cover layer (230) may include an insulating film such as solder resist or polyimide film (PI).

[0158] A method for manufacturing a package substrate according to embodiments of the present invention may further include a step of manufacturing a lower layer. The lower layer may be formed in a manner similar to the upper layer.

[0159] For example, the package substrate may further include a lower layer (300) disposed on the other side of the core layer (100).

[0160] The lower layer (300) may include a lower insulating layer (310) covering the other side of the core layer (100).

[0161] The lower insulating layer (310) may include a build-up layer material such as an epoxy resin or an imide resin, but is not limited thereto, and any material that functions as an insulator for a semiconductor device or a package substrate may be applied as the lower insulating layer (310).

[0162] The lower layer (300) may further include a lower redistribution layer (320) that is at least partially embedded in the lower insulating layer (310). The lower redistribution layer (320) may be electrically connected to the via electrode (130).

[0163] The lower redistribution layer (320) may be composed of a plurality of layers along the thickness direction of the package substrate. For example, the lower redistribution layer (320) may have a 2-layer structure, a 3-layer structure, a 4-layer structure, a 5-layer structure, or a multilayer structure of 6 layers or more.

[0164] For example, in the case of a two-layer structure, the lower redistribution layer (320) may include a first lower redistribution layer (320a) and a second lower redistribution layer (320b) that are sequentially stacked and connected from the other side of the core layer (100).

[0165] In FIG. 12, the lower insulating layer (310) is depicted as a single layer, but the lower insulating layer (310) may be composed of multiple layers. When the lower insulating layer (310) is composed of multiple layers, multiple lower redistribution layers (320) may be disposed on at least one of the upper and lower surfaces of each layer of the lower insulating layer (310).

[0166] The outermost lower redistribution layer (320) in the thickness direction of the package substrate may be exposed to the outside from the lower surface of the lower layer (300). The outermost lower redistribution layer (320) may function as a connection electrode connected to a connection terminal of a semiconductor device, etc.

[0167] In one embodiment, the lower layer (200) may further include a lower cover layer (330). The lower cover layer (330) may protect the surface circuit of the package substrate from the external environment. The lower cover layer (330) may include an opening that exposes the outermost lower redistribution layer (320). Through the opening, the outermost lower redistribution layer (320) and a connection terminal of an external component may be connected.

[0168] The lower cover layer (330) may include an insulating film such as solder resist or polyimide film (PI).

[0169] According to some embodiments, a semiconductor package may be provided comprising a package substrate according to the above embodiments and a device mounted on said package substrate.

[0170] In one embodiment, a device may be mounted on the upper layer (200) and / or lower layer (300) of the package substrate. The device may be electrically connected to the package substrate. Examples of the device include a capacitor, a transistor, an impedance, a semiconductor, etc., but are not limited to any device mounted on a semiconductor device.

[0171] In some embodiments, the glass substrate (110) may further include a cavity formed by being indented internally. For example, the cavity may be formed by being indented in part on the first surface (112) side in the thickness direction of the glass substrate (110), or by being formed by being indented in part on the second surface (114) side. Additionally, the cavity may have a shape that penetrates the glass substrate (110) in the thickness direction.

[0172] A device may be mounted in the above cavity. The device may be electrically connected to a package substrate. Examples of the device include capacitors, transistors, impedance devices, semiconductor devices, etc., but are not limited to any device mounted on a semiconductor device.

[0173] The above semiconductor device may be a central processing unit (CPU) chip, a graphic processing unit (GPU) chip, an application processor (AP) chip, or a memory chip.

[0175] The above contents are explained in more detail by the following examples. However, the following examples are merely for illustrating the present invention, and the scope of the present invention is not limited to these examples.

[0177] [Example]

[0178] (1) Manufacturing of package substrate

[0179] A glass substrate with a thickness of 0.53t (Corning SG7.8) was prepared.

[0180] A virtual region (i.e., VH region) having a circular shape with a diameter of 140 μm was established on one surface of the glass substrate. A plurality of defects were formed by irradiating a laser at regular intervals along the perimeter of the VH region. The spacing between the defects formed by the laser irradiation was set as shown in Table 1 below.

[0181] Specifically, to form each defect, a laser with a wavelength of approximately 308 nm is used with a pulse of approximately 10 ns and an energy density of approximately 5 J / cm². 2 , and was irradiated for 10 seconds under conditions of a spot size of about 5 μm.

[0182] The glass substrate was etched to form a through hole penetrating the glass substrate in the thickness direction. The through hole was formed to have a cylindrical shape with a diameter of 140 μm.

[0183] The above etching was performed for 30 minutes, and was carried out by placing the glass substrate in a deionized water-based acidic etchant containing 2 M hydrofluoric acid (HF) and 1.1 M nitric acid (HNO3) and applying ultrasound at 80 Hz.

[0185] (2) Measurement of the roughness of the inner wall of the through hole

[0186] The roughness of the inner wall of the through hole manufactured above was measured. Specifically, a total of three measurement areas were arbitrarily selected on the inner wall of the through hole. Each measurement area was specified so as not to overlap with one another, and was set to have a line shape extending along the inner wall of the through hole in the thickness direction of the glass substrate. For example, each measurement area was set as the area indicated by the dotted line in FIG. 11a.

[0187] The above roughness was measured using a laser microscope (KEYENCE VK-X3000) according to ISO 21920 standards, with centerline average roughness (Ra) and 10-point average roughness (Rz).

[0188] The average value of the Ra values ​​in each measurement area was set as the Ra of the inner wall of the penetration hole, and the average value of the Rz values ​​in each measurement area was set as the Rz of the inner wall of the penetration hole. The ratio of Ra to Rz (Rz / Ra) was calculated. Meanwhile, among the measured values ​​in each measurement area, the maximum value was indicated as "max" in Table 1 below, and the minimum value was indicated as "min".

[0190] Package substrates were manufactured by changing the spacing between defects in the above laser processing process as shown in Table 1 below. At this time, package substrates were manufactured twice with the same defect spacing. For example, Manufacturing Examples 1 and 2 are for package substrates manufactured by setting the laser irradiation spacing to 2 μm, and Manufacturing Examples 3 and 4 are for package substrates manufactured by setting the laser irradiation spacing to 3 μm.

[0191] The roughness of the inner wall of the through hole of the above-manufactured package substrate was measured. The measurement results are shown in Table 1 below.

[0193] Preparation Example Defect spacing (㎛) Ra (㎛) Rz (㎛) Rz / Ra average Standard deviation max min average Standard deviation max min 1 2 1.513 0.149 1.619 1.302 8.082 0.769 8.949 7.079 5.342 2 2 1.652 0.211 1.915 1.398 8.674 1.098 9.614 7.134 5.251 3 3 1.267 0.267 1.529 0.9 7.495 2.101 9.855 4.752 5.916 4 3 1.153 0.128 1.268 0.974 6.624 0.471 7.141 6.001 5.745 5 4 0.519 0.055 0.586 0.451 3.278 0.348 3.676 2.829 6.316 6 4 0.481 0.03 0.521 0.449 3.157 0.272 3.441 2.79 6.563 7 5 0.598 0.11 0.751 0.498 3.979 1.036 5.421 3.035 6.654 8 5 0.570 0.11 0.726 0.487 3.675 0.638 4.448 2.925 6.447 9 6 0.596 0.128 0.776 0.484 3.612 0.5 4.206 2.984 6.060 10 6 0.599 0.049 0.647 0.531 3.737 0.438 4.168 3.135 6.239

[0195] Referring to Table 1 above, it was confirmed that the roughness of the inner wall of the through hole varies depending on the spacing between defects formed by laser irradiation. Specifically, referring to Manufacturing Examples 1 and 2, when the spacing between defects was 2 μm, the inner wall of the through hole had an Ra value of about 1.5 μm to about 1.7 μm and an Rz value of about 8 μm to about 9 μm.

[0196] In addition, referring to Manufacturing Examples 3 to 10, when the spacing between defects is 3 μm to 6 μm, the Ra value of the inner wall of the through hole is controlled to 1.3 μm or less, and the Rz value is controlled to 8 μm or less.

[0197] Meanwhile, as the number of defects per unit area decreases as the defect spacing increases, harsher etching conditions may be required to form through holes, or the etching time may increase. In this case, surface characteristics may change or physical properties may be altered by etching in other areas of the glass substrate besides the area where through holes are formed, and electrical and thermal properties may deteriorate.

[0199] FIGS. 13a to 13e are images of through holes in Preparation Examples 2, 4, 6, 8, and 10, respectively, taken using a laser microscope (KEYENCE VK-X3000). Specifically, FIG. 13a is an image of the through hole in Preparation Example 2, FIG. 13b is an image of the through hole in Preparation Example 4, FIG. 13c is an image of the through hole in Preparation Example 6, FIG. 13d is an image of the through hole in Preparation Example 8, and FIG. 13e is an image of the through hole in Preparation Example 10.

[0200] FIGS. 14a to 14e are 3D images of through holes in Preparation Examples 2, 4, 6, 8, and 10, respectively, obtained using a laser microscope (KEYENCE VK-X3000). Specifically, 3D images of the through holes were obtained using an image program (VK-X3000 Viewer Application) linked with the laser microscope. FIG. 14a is a 3D image of the through hole in Preparation Example 2, FIG. 14b is a 3D image of the through hole in Preparation Example 4, FIG. 14c is a 3D image of the through hole in Preparation Example 6, FIG. 14d is a 3D image of the through hole in Preparation Example 8, and FIG. 14e is a 3D image of the through hole in Preparation Example 10.

[0201] Referring to FIGS. 13a to 13e and FIGS. 14a to 14e, it was confirmed that the surface characteristics of the inner wall of the through hole change by adjusting the laser irradiation interval during the process of forming the through hole.

[0202] Referring to FIGS. 13c and FIGS. 14c, it can be seen that in the case of the through hole in Manufacturing Example 6, irregularities of an appropriate size are provided on the inner wall, thereby providing a mechanical anchoring effect with the metal layer structurally formed on the inner wall. In addition, it can be seen that as the irregularities are distributed in a uniform size throughout the inner wall of the through hole, stress concentration, peeling, and defects in localized areas are suppressed, and uniform plating can be provided. Explanation of the symbols

[0204] 100: Core layer 110: Glass substrate 112: Page 1 114: Page 2 120: Through hole 122: Inner wall 124: Interior space 130: via electrode 132: Seed Layer 134: Electrically conductive layer 140: Core wiring layer 200: Upper layer 210: Upper insulation layer 220: Upper redistribution layer 230: Cover layer 300: Lower floor 310: Lower insulation layer 320: Lower redistribution layer 50: Defect

Claims

Claim 1 A method for manufacturing a package substrate, comprising: a step of preparing a glass substrate; a step of forming a plurality of defects on one surface of the glass substrate by irradiating a laser at regular intervals along the perimeter of an area where a through hole is to be formed; and a step of etching the glass substrate to form a through hole penetrating the glass substrate, wherein, when observed on one surface of the glass substrate, the spacing between the defects adjacent to each other along the perimeter is 2 μm to 8 μm, the through hole includes an internal space and an inner wall surrounding the internal space, and the centerline average roughness (Ra) of the inner wall of the through hole is greater than 0.2 μm and less than or equal to 2.0 μm. Claim 2 A method for manufacturing a package substrate according to claim 1, wherein the spacing between the defects adjacent to each other along the perimeter is 2 μm to 6 μm. Claim 3 A method for manufacturing a package substrate according to claim 1, wherein the laser is irradiated perpendicularly to one surface of the glass substrate. Claim 4 A method for manufacturing a package substrate according to claim 1, wherein each of the defects has a groove shape extending in a direction perpendicular to one surface of the glass substrate. Claim 5 A method for manufacturing a package substrate, wherein each of the above defects penetrates the glass substrate in claim 4. Claim 6 A method for manufacturing a package substrate according to claim 1, further comprising the step of forming a plurality of defects on the other side of the glass substrate by irradiating a laser at regular intervals along the perimeter of the area where the through hole is to be formed on the other side of the glass substrate. Claim 7 A method for manufacturing a package substrate according to claim 6, wherein a plurality of defects formed on one surface of the glass substrate and a plurality of defects formed on the other surface of the glass substrate overlap each other in the thickness direction of the glass substrate. Claim 8 A method for manufacturing a package substrate according to claim 1, wherein the etching of the glass substrate is performed by wet etching. Claim 9 A method for manufacturing a package substrate according to claim 1, wherein the through hole has a cylindrical shape. Claim 10 delete Claim 11 A method for manufacturing a package substrate according to claim 1, further comprising: a step of forming a seed layer along the inner wall of the through hole; and a step of forming an electrically conductive layer inside the through hole using the seed layer. Claim 12 A package substrate manufactured by the method according to claim 1.

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