Electronic device, method, non-transitory computer readable storage medium, and ufs card including ufs storage device

Abstract

According to one embodiment, an electronic device comprises at least one processor, a universal flash storage (UFS) device controller operatively coupled with the at least one processor, a UFS interface including downstream lanes for transmitting data from the at least one processor to the UFS device controller and upstream lanes for transmitting data from the UFS device controller to the at least one processor, and storage including a plurality of non-volatile memories and a cache memory, wherein the at least one processor, in response to boot up of the at least one processor, transmits a first control signal to the UFS device controller to indicate that the temperature of the plurality of non-volatile memories is measured using a temperature sensor operatively coupled with the UFS device controller and that the measured temperature exceeds a threshold value, receives a status signal from the UFS device controller indicating that the temperature of the plurality of non-volatile memories measured through the temperature sensor exceeds the threshold value, and based on the status signal, through the UFS device controller, the plurality of downstream lanes A second control signal instructing to disable at least some of the above and at least some of the above multiple upstream lanes, and to disable the cache memory configured to store 1 bit per unit cell of the storage, can be transmitted to the UFS device controller. Various other embodiments are possible.

Description

Technology Field

[0001] The following descriptions relate to an electronic device including a universal flash storage (UFS) storage device, a method, a non-transitory computer readable storage medium, and a UFS card. Background Technology

[0003] Semiconductor memory devices can be classified into volatile memory devices, which lose stored data when the power supply is interrupted, and non-volatile memory devices, which do not lose stored data. Volatile memory devices offer fast read and write speeds, but the stored content may be lost if the external power supply is cut off. On the other hand, non-volatile memory devices have slower read and write speeds compared to volatile memory devices, but they can preserve their contents even if the external power supply is interrupted.

[0004] In particular, non-volatile memory such as flash memory can be widely used as storage devices in various fields due to advantages such as large capacity, low noise, and low power consumption. Specifically, solid-state drives (SSDs) based on flash memory can be used as high-capacity storage devices in various devices such as personal computers, laptops, workstations, and server systems. The problem to be solved

[0006] Universal Flash Storage (UFS) defines Temperature Event Notification in its standard. However, because it is extremely rare for UFS storage devices to exceed the temperature range that guarantees normal operation, there is no corresponding feature for temperature event notification within the UFS standard.

[0007] However, in the future, when the data rate is expected to double, UFS storage devices are expected to exceed the temperature range that guarantees normal operation. Accordingly, to ensure the temperature range that guarantees normal operation, a method to dissipate the temperature of the package containing the UFS storage device through hardware is being considered, but its effectiveness cannot be guaranteed. Therefore, additional measures are required to ensure the temperature range that guarantees the normal operation of the UFS storage device.

[0008] The technical problems to be solved in this document are not limited to those described above, and other technical problems not mentioned will be clearly understood by those skilled in the art to which this invention belongs from the description below. means of solving the problem

[0010] According to one embodiment, an electronic device comprises at least one processor, a universal flash storage (UFS) device controller operatively coupled with the at least one processor, a UFS interface including downstream lanes for transmitting data from the at least one processor to the UFS device controller and upstream lanes for transmitting data from the UFS device controller to the at least one processor, and storage including a plurality of non-volatile memories and a cache memory, wherein the at least one processor, in response to boot up of the at least one processor, transmits a first control signal to the UFS device controller to indicate that the temperature of the plurality of non-volatile memories is measured using a temperature sensor operatively coupled with the UFS device controller and that the measured temperature exceeds a threshold value, receives a status signal from the UFS device controller indicating that the temperature of the plurality of non-volatile memories measured through the temperature sensor exceeds the threshold value, and based on the status signal, through the UFS device controller, the plurality of downstream lanes A second control signal can be transmitted to the UFS device controller, which instructs to disable at least some of the above and at least some of the above multiple upstream lanes, and to disable the cache memory configured to store 1 bit per unit cell of the above storage.

[0011] According to one embodiment, an electronic device comprises at least one processor, a universal flash storage (UFS) device controller operatively coupled with the at least one processor, a UFS interface including downstream lanes for transmitting data from the at least one processor to the UFS device controller and upstream lanes for transmitting data from the UFS device controller to the at least one processor, and storage including a plurality of non-volatile memories and a cache memory, wherein the at least one processor transmits a first control signal to the UFS device controller instructing it to identify whether the temperature of the storage measured using a temperature sensor operatively coupled with the UFS device controller is less than a threshold value in response to the boot up of the at least one processor, receives a status signal from the UFS device controller for indicating that the temperature of the storage is less than the threshold value, and based on the status signal, activates a deactivated lane among the plurality of downstream lanes and the plurality of upstream lanes through the UFS device controller, and 1 bit per unit cell of the storage It may be configured to transmit a second control signal to the UFS device controller instructing it to activate the cache memory configured to store.

[0012] According to one embodiment, an electronic device comprises at least one processor, a universal flash storage (UFS) device controller operatively coupled with the at least one processor, a UFS interface including downstream lanes for transmitting data from the at least one processor to the UFS device controller and upstream lanes for transmitting data from the UFS device controller to the at least one processor, and storage including a plurality of non-volatile memories and a cache memory, wherein the at least one processor transmits a first control signal to the UFS device controller in response to the boot-up of the at least one processor, instructing to identify that the temperature of the storage measured using a temperature sensor operatively coupled with the UFS device controller exceeds a first threshold value or is less than a second threshold value which is smaller than the first threshold value, and transmits a second control signal to the UFS device controller in response to receiving a status signal from the UFS device controller indicating that the temperature of the storage exceeds the first threshold value, instructing a plurality of first events for reducing the current consumption of the UFS device controller. It may be configured to transmit, and in response to receiving a status signal from the UFS device controller indicating that the temperature of the storage is less than the second threshold value, to transmit a second control signal to the UFS device controller indicating a plurality of second events for increasing the current consumption of the UFS device controller.

[0013] According to one embodiment, a method of operation of an electronic device comprising at least one processor, a universal flash storage (UFS) device controller operatively coupled with the at least one processor, a UFS interface including downstream lanes for transmitting data from the at least one processor to the UFS device controller and upstream lanes for transmitting data from the UFS device controller to the at least one processor, and storage including a plurality of non-volatile memories and a cache memory, comprises: an operation of measuring the temperature of the plurality of non-volatile memories using a temperature sensor operatively coupled with the UFS device controller in response to the boot-up of the at least one processor; an operation of transmitting a first control signal to the UFS device controller to indicate that the measured temperature exceeds a threshold value; an operation of receiving a status signal from the UFS device controller indicating that the temperature of the plurality of non-volatile memories measured through the temperature sensor exceeds the threshold value; and, based on the status signal, through the UFS device controller, at least some of the plurality of downstream lanes and the plurality of upstream It may include the operation of transmitting a second control signal to the UFS device controller, which instructs to disable at least some of the lanes and disable the cache memory configured to store 1 bit per unit cell of the storage.

[0014] A method of operation of an electronic device according to one embodiment comprising at least one processor, a universal flash storage (UFS) device controller operatively coupled with the at least one processor, a UFS interface including downstream lanes for transmitting data from the at least one processor to the UFS device controller and upstream lanes for transmitting data from the UFS device controller to the at least one processor, and storage including a plurality of non-volatile memories and a cache memory, comprises: transmitting a first control signal to the UFS device controller in response to the boot-up of the at least one processor to instruct to identify whether the temperature of the storage measured using a temperature sensor operatively coupled with the UFS device controller is less than a threshold value; receiving a status signal from the UFS device controller to indicate that the temperature of the storage is less than the threshold value; and, based on the status signal, activating a deactivated lane among the plurality of downstream lanes and the plurality of upstream lanes through the UFS device controller and storing 1 bit per unit cell of the storage. It may include the operation of transmitting a second control signal to the UFS device controller instructing it to activate the configured cache memory.

[0015] A method of operation of an electronic device according to one embodiment comprising at least one processor, a universal flash storage (UFS) device controller operatively coupled with the at least one processor, a UFS interface including downstream lanes for transmitting data from the at least one processor to the UFS device controller and upstream lanes for transmitting data from the UFS device controller to the at least one processor, and storage including a plurality of non-volatile memories and a cache memory, comprises the operation of transmitting a first control signal to the UFS device controller in response to the boot-up of the at least one processor, instructing to identify that the temperature of the storage measured using a temperature sensor operatively coupled with the UFS device controller exceeds a first threshold value or is less than a second threshold value which is smaller than the first threshold value; and, in response to receiving a status signal from the UFS device controller indicating that the temperature of the storage exceeds the first threshold value, transmitting a second control signal to the UFS device controller instructing a plurality of first events for reducing the current consumption of the UFS device controller. The operation may include, in response to receiving a status signal from the UFS device controller indicating that the temperature of the storage is less than the second threshold value, transmitting a second control signal to the UFS device controller indicating a plurality of second events to increase the current consumption of the UFS device controller.

[0016] According to one embodiment, a non-transient computer-readable storage medium comprises, when executed by at least one processor of an electronic device including at least one processor, a universal flash storage (UFS) device controller operatively coupled with the at least one processor, a UFS interface comprising downstream lanes for transmitting data from the at least one processor to the UFS device controller and upstream lanes for transmitting data from the UFS device controller to the at least one processor, and storage comprising a plurality of non-volatile memories and a cache memory, in response to the boot-up of the at least one processor, a first control signal for instructing to measure the temperature of the plurality of non-volatile memories using a temperature sensor operatively coupled with the UFS device controller and to identify that the measured temperature exceeds a threshold value, and receiving a status signal from the UFS device controller indicating that the temperature of the plurality of non-volatile memories measured through the temperature sensor exceeds the threshold value, and based on the status signal, through the UFS device controller, the plurality of downstream One or more programs including instructions that cause the electronic device to transmit a second control signal to the UFS device controller, which instructs to disable at least some of the lanes and at least some of the plurality of upstream lanes, and to disable the cache memory configured to store 1 bit per unit cell of the storage.

[0017] According to one embodiment, a non-transient computer-readable storage medium comprises, when executed by at least one processor of an electronic device including at least one processor, a universal flash storage (UFS) device controller operatively coupled with the at least one processor, a UFS interface comprising downstream lanes for transmitting data from the at least one processor to the UFS device controller and upstream lanes for transmitting data from the UFS device controller to the at least one processor, and storage comprising a plurality of non-volatile memories and a cache memory, a first control signal for instructing to identify whether the temperature of the storage measured using a temperature sensor operatively coupled with the UFS device controller is less than a threshold value in response to the boot-up of the at least one processor, a status signal for instructing to identify whether the temperature of the storage is less than the threshold value is received from the UFS device controller, and based on the status signal, through the UFS device controller, a deactivated lane among the plurality of downstream lanes and the plurality of upstream lanes One or more programs including instructions that cause the electronic device to transmit a second control signal to the UFS device controller, which instructs the device to activate a cache memory configured to store 1 bit per unit cell of the storage.

[0018] According to one embodiment, a non-transient computer-readable storage medium comprises, when executed by at least one processor of an electronic device including at least one processor, a universal flash storage (UFS) device controller operatively coupled with the at least one processor, a UFS interface comprising downstream lanes for transmitting data from the at least one processor to the UFS device controller and upstream lanes for transmitting data from the UFS device controller to the at least one processor, and storage comprising a plurality of non-volatile memories and a cache memory, a first control signal for instructing to identify, in response to the boot-up of the at least one processor, that the temperature of the storage measured using a temperature sensor operatively coupled with the UFS device controller exceeds a first threshold value or is less than a second threshold value which is smaller than the first threshold value, and a plurality of first events for reducing the current consumption of the UFS device controller in response to receiving a status signal from the UFS device controller indicating that the temperature of the storage exceeds the first threshold value. One or more programs including instructions that cause the electronic device to transmit a second control signal to the UFS device controller, and in response to receiving a status signal from the UFS device controller indicating that the temperature of the storage is less than the second threshold value, transmit a second control signal to the UFS device controller indicating a plurality of second events to increase the current consumption of the UFS device controller. Effects of the invention

[0020] According to one embodiment, an electronic device including a UFS storage device, a method, a computer-readable storage medium, and a universal flash storage (UFS) card can change the magnitude of the current consumed when the UFS storage device operates in a specific temperature range to return the temperature of the UFS storage device to a reliable temperature range.

[0021] The effects obtainable from the present disclosure are not limited to those mentioned above, and other unmentioned effects will be clearly understood by those skilled in the art to which the present disclosure belongs from the description below. Brief explanation of the drawing

[0023] FIG. 1 is a block diagram of an electronic device in a network environment according to various embodiments. FIG. 2a illustrates a UFS system including a UFS host device and a UFS storage device according to various embodiments. FIG. 2b illustrates a block diagram of storage according to various embodiments. FIG. 3 is a flowchart illustrating the operation of an electronic device when the temperature of a UFS storage device exceeds a critical temperature according to various embodiments. FIG. 4 is a flowchart illustrating the operation of an electronic device for measuring the temperature of a UFS storage device according to various embodiments. FIGS. 5a to 5e are flowcharts illustrating the operations of an electronic device when the temperature of a UFS storage device according to various embodiments exceeds a critical temperature. FIG. 6 is a flowchart illustrating the operation of an electronic device when the temperature of a UFS storage device is below a critical temperature, according to various embodiments. FIG. 7 is a flowchart illustrating the operation of an electronic device when the temperature of a UFS storage device is below a critical temperature, according to various embodiments. FIGS. 8a to 8e are flowcharts illustrating the operation of an electronic device when the temperature of a UFS storage device according to various embodiments is below a critical temperature. FIG. 9 is a flowchart illustrating the operation of an electronic device when the temperature of a UFS storage device exceeds a critical temperature according to various embodiments. FIG. 10 illustrates a UFS card according to various embodiments. FIG. 11 is a flowchart illustrating the operation of an electronic device when the temperature of a UFS storage device exceeds a first threshold temperature or is less than a second threshold temperature, according to various embodiments. Specific details for implementing the invention

[0024] FIG. 1 is a block diagram of an electronic device (101) in a network environment (100) according to various embodiments.

[0025] Referring to FIG. 1, in a network environment (100), an electronic device (101) may communicate with an electronic device (102) through a first network (198) (e.g., a short-range wireless communication network) or with at least one of an electronic device (104) or a server (108) through a second network (199) (e.g., a long-range wireless communication network). According to one embodiment, the electronic device (101) may communicate with the electronic device (104) through a server (108). According to one embodiment, the electronic device (101) may include a processor (120), memory (130), input module (150), sound output module (155), display module (160), audio module (170), sensor module (176), interface (177), connection terminal (178), haptic module (179), camera module (180), power management module (188), battery (189), communication module (190), subscriber identification module (196), or antenna module (197). In some embodiments, at least one of these components (e.g., connection terminal (178)) may be omitted from the electronic device (101), or one or more other components may be added. In some embodiments, some of these components (e.g., sensor module (176), camera module (180), or antenna module (197)) may be integrated into a single component (e.g., display module (160)).

[0026] The processor (120) can control at least one other component (e.g., hardware or software component) of the electronic device (101) connected to the processor (120) by executing software (e.g., program (140)), and can perform various data processing or operations. According to one embodiment, as at least part of the data processing or operations, the processor (120) can store commands or data received from other components (e.g., sensor module (176) or communication module (190)) in volatile memory (132), process the commands or data stored in volatile memory (132), and store the resulting data in non-volatile memory (134). According to one embodiment, the processor (120) may include a main processor (121) (e.g., central processing unit or application processor) or an auxiliary processor (123) that can operate independently or together with it (e.g., graphics processing unit, neural processing unit (NPU), image signal processor, sensor hub processor, or communication processor). For example, if the electronic device (101) includes a main processor (121) and an auxiliary processor (123), the auxiliary processor (123) may be configured to use less power than the main processor (121) or to be specialized for a designated function. The auxiliary processor (123) may be implemented separately from the main processor (121) or as part thereof.

[0027] The auxiliary processor (123) may control at least some of the functions or states associated with at least one component of the electronic device (101) (e.g., display module (160), sensor module (176), or communication module (190)) on behalf of the main processor (121) while the main processor (121) is in an inactive (e.g., sleep) state, or together with the main processor (121) while the main processor (121) is in an active (e.g., application execution) state. According to one embodiment, the auxiliary processor (123) (e.g., image signal processor or communication processor) may be implemented as part of another functionally related component (e.g., camera module (180) or communication module (190)). According to one embodiment, the auxiliary processor (123) (e.g., neural network processing unit) may include a hardware structure specialized for processing an artificial intelligence model. The artificial intelligence model may be generated through machine learning. Such learning may be performed, for example, on the electronic device (101) itself where the artificial intelligence model is executed, or through a separate server (e.g., server (108)). The learning algorithm may include, for example, supervised learning, unsupervised learning, semi-supervised learning, or reinforcement learning, but is not limited to the examples described above. The artificial intelligence model may include a plurality of artificial neural network layers.An artificial neural network may be a deep neural network (DNN), a convolutional neural network (CNN), a recurrent neural network (RNN), a restricted Boltzmann machine (RBM), a deep belief network (DBN), a bidirectional recurrent deep neural network (BRDNN), a deep Q-network, or a combination of two or more of the above, but is not limited to the examples described above. In addition to the hardware structure, the artificial intelligence model may include a software structure, either additionally or substantially.

[0028] The memory (130) can store various data used by at least one component of the electronic device (101) (e.g., processor (120) or sensor module (176)). The data may include, for example, input data or output data for software (e.g., program (140)) and related commands. The memory (130) may include volatile memory (132) or non-volatile memory (134).

[0029] The program (140) may be stored as software in memory (130) and may include, for example, an operating system (142), middleware (144), or an application (146).

[0030] The input module (150) can receive commands or data to be used for a component of the electronic device (101) (e.g., processor (120)) from outside the electronic device (101) (e.g., user). The input module (150) may include, for example, a microphone, a mouse, a keyboard, a key (e.g., a button), or a digital pen (e.g., a stylus pen).

[0031] The sound output module (155) can output a sound signal to the outside of the electronic device (101). The sound output module (155) may include, for example, a speaker or a receiver. The speaker may be used for general purposes, such as multimedia playback or recording playback. The receiver may be used to receive incoming calls. According to one embodiment, the receiver may be implemented separately from the speaker or as part thereof.

[0032] The display module (160) can visually provide information to an external (e.g., user) of the electronic device (101). The display module (160) may include, for example, a display, a holographic device, or a projector and a control circuit for controlling said device. According to one embodiment, the display module (160) may include a touch sensor configured to detect a touch, or a pressure sensor configured to measure the intensity of the force generated by said touch.

[0033] The audio module (170) can convert sound into an electrical signal or, conversely, convert an electrical signal into sound. According to one embodiment, the audio module (170) can acquire sound through the input module (150) or output sound through the sound output module (155) or an external electronic device (e.g., electronic device (102)) (e.g., speaker or headphones) connected directly or wirelessly to the electronic device (101).

[0034] The sensor module (176) can detect the operating state of the electronic device (101) (e.g., power or temperature) or the external environmental state (e.g., user state) and generate an electrical signal or data value corresponding to the detected state. According to one embodiment, the sensor module (176) may include, for example, a gesture sensor, a gyroscope sensor, a barometric pressure sensor, a magnetic sensor, an accelerometer sensor, a grip sensor, a proximity sensor, a color sensor, an IR (infrared) sensor, a biosensor, a temperature sensor, a humidity sensor, or an illuminance sensor.

[0035] The interface (177) may support one or more specified protocols that can be used for the electronic device (101) to be connected directly or wirelessly to an external electronic device (e.g., electronic device (102)). According to one embodiment, the interface (177) may include, for example, a high definition multimedia interface (HDMI), a universal serial bus (USB) interface, an SD card interface, or an audio interface.

[0036] The connection terminal (178) may include a connector through which the electronic device (101) can be physically connected to an external electronic device (e.g., electronic device (102)). According to one embodiment, the connection terminal (178) may include, for example, an HDMI connector, a USB connector, an SD card connector, or an audio connector (e.g., a headphone connector).

[0037] The haptic module (179) can convert an electrical signal into a mechanical stimulus (e.g., vibration or movement) or an electrical stimulus that the user can perceive through tactile or kinesthetic senses. According to one embodiment, the haptic module (179) may include, for example, a motor, a piezoelectric element, or an electric stimulation device.

[0038] The camera module (180) can capture still images and video. According to one embodiment, the camera module (180) may include one or more lenses, image sensors, image signal processors, or flashes.

[0039] The power management module (188) can manage the power supplied to the electronic device (101). According to one embodiment, the power management module (188) can be implemented, for example, as at least part of a power management integrated circuit (PMIC).

[0040] The battery (189) can supply power to at least one component of the electronic device (101). According to one embodiment, the battery (189) may include, for example, a non-rechargeable primary battery, a rechargeable secondary battery, or a fuel cell.

[0041] The communication module (190) can support the establishment of a direct (e.g., wired) communication channel or a wireless communication channel between an electronic device (101) and an external electronic device (e.g., electronic device (102), electronic device (104), or server (108)), and the performance of communication through the established communication channel. The communication module (190) may include one or more communication processors that operate independently of the processor (120) (e.g., application processor) and support direct (e.g., wired) communication or wireless communication. According to one embodiment, the communication module (190) may include a wireless communication module (192) (e.g., cellular communication module, short-range wireless communication module, or GNSS (global navigation satellite system) communication module) or a wired communication module (194) (e.g., LAN (local area network) communication module, or power line communication module). The corresponding communication module among these communication modules can communicate with an external electronic device (104) through a first network (198) (e.g., a short-range communication network such as Bluetooth, WiFi (wireless fidelity) direct, or IrDA (infrared data association)) or a second network (199) (e.g., a legacy cellular network, a 5G network, a next-generation communication network, the Internet, or a computer network (e.g., a LAN or WAN). These various types of communication modules may be integrated into a single component (e.g., a single chip) or implemented as multiple separate components (e.g., multiple chips). The wireless communication module (192) can identify or authenticate the electronic device (101) within a communication network such as the first network (198) or the second network (199) using subscriber information (e.g., International Mobile Subscriber Identifier (IMSI)) stored in the subscriber identification module (196).

[0042] The wireless communication module (192) can support 5G networks and next-generation communication technologies following 4G networks, for example, new radio access technology. NR access technology can support high-speed transmission of high-capacity data (enhanced mobile broadband (eMBB)), minimization of terminal power and connection of multiple terminals (massive machine type communications (mMTC)), or high reliability and low latency (ultra-reliable and low-latency communications (URLLC)). The wireless communication module (192) can support a high-frequency band (e.g., mmWave band) to achieve a high data transmission rate, for example. The wireless communication module (192) can support various technologies for securing performance in the high-frequency band, such as beamforming, massive MIMO (multiple-input and multiple-output), full-dimensional MIMO (FD-MIMO), array antenna, analog beam-forming, or large-scale antenna. The wireless communication module (192) can support various requirements specified in the electronic device (101), external electronic device (e.g., electronic device (104)), or network system (e.g., second network (199)). According to one embodiment, the wireless communication module (192) can support a Peak data rate (e.g., 20 Gbps or more) for realizing eMBB, loss coverage (e.g., 164 dB or less) for realizing mMTC, or U-plane latency (e.g., downlink (DL) and uplink (UL) each 0.5 ms or less, or round trip 1 ms or less) for realizing URLLC.

[0043] An antenna module (197) can transmit a signal or power to or from an external source (e.g., an external electronic device). According to one embodiment, the antenna module (197) may include an antenna comprising a radiator made of a conductor or a conductive pattern formed on a substrate (e.g., a PCB (print circuitry board)). According to one embodiment, the antenna module (197) may include a plurality of antennas (e.g., an array antenna). In this case, at least one antenna suitable for a communication method used in a communication network, such as a first network (198) or a second network (199), may be selected from the plurality of antennas, for example, by a communication module (190). A signal or power may be transmitted or received between the communication module (190) and an external electronic device through the selected at least one antenna. According to some embodiments, in addition to the radiator, other components (e.g., a radio frequency integrated circuit (RFIC)) may be additionally formed as part of the antenna module (197).

[0044] According to various embodiments, the antenna module (197) may form a mmWave antenna module. According to one embodiment, the mmWave antenna module may include a printed circuit board, an RFIC disposed on or adjacent to a first surface (e.g., bottom surface) of the printed circuit board and capable of supporting a specified high frequency band (e.g., mmWave band), and a plurality of antennas (e.g., array antennas) disposed on or adjacent to a second surface (e.g., top surface or side surface) of the printed circuit board and capable of transmitting or receiving a signal of the specified high frequency band.

[0045] At least some of the above components can be connected to each other via a communication method between peripheral devices (e.g., bus, GPIO (general purpose input and output), SPI (serial peripheral interface), or MIPI (mobile industry processor interface)) and exchange signals (e.g., commands or data) with each other.

[0046] According to one embodiment, commands or data may be transmitted or received between the electronic device (101) and an external electronic device (104) through a server (108) connected to a second network (199). Each of the external electronic devices (102, or 104) may be the same or different type of device as the electronic device (101). According to one embodiment, all or part of the operations performed on the electronic device (101) may be performed on one or more of the external electronic devices (102, 104, or 108). For example, if the electronic device (101) needs to perform a function or service automatically or in response to a request from a user or another device, the electronic device (101) may request one or more external electronic devices to perform at least part of the function or service instead of performing the function or service itself or additionally. One or more external electronic devices that receive the above request may execute at least part of the requested function or service, or additional function or service related to the request, and transmit the result of the execution to the electronic device (101). The electronic device (101) may provide the result as is or additionally processed as at least part of the response to the request. For this purpose, for example, cloud computing, distributed computing, mobile edge computing (MEC), or client-server computing technology may be used. The electronic device (101) may provide ultra-low latency services using, for example, distributed computing or mobile edge computing. In another embodiment, the external electronic device (104) may include an Internet of Things (IoT) device. The server (108) may be an intelligent server using machine learning and / or neural networks. According to one embodiment, the external electronic device (104) or the server (108) may be included within the second network (199).The electronic device (101) can be applied to intelligent services (e.g., smart home, smart city, smart car, or healthcare) based on 5G communication technology and IoT-related technology.

[0048] FIG. 2a illustrates a UFS system (200) including a UFS host device (210) and a UFS storage device (220) according to various embodiments.

[0049] Referring to FIG. 2a, the UFS system (200) is a system that follows the UFS standard published by JEDEC (Joint Electron Device Engineering Council) and may include a UFS host device (210) and a UFS storage device (220). Referring to FIG. 1 and FIG. 2a together, the UFS host device (210) may be implemented as part of the processor (120) of FIG. 1, or the UFS storage device (220) may be implemented as part of the memory (130) of FIG. 1 (e.g., non-volatile memory (134)).

[0050] According to one embodiment, a UFS host device (210) and a UFS storage device (220) may be interconnected via a UFS interface. The UFS interface may include a lane transmitting a reference clock (Ref_CLK), a lane transmitting a hardware reset signal (Reset_n) for the UFS storage device (220), lanes transmitting a differential input signal pair (DIN_t, DIN_c), and lanes transmitting a differential output signal pair (DOUT_t, DOUT_c). The differential input signal pair (DIN_t, DIN_c) transmitting data from the UFS host device (210) to the UFS storage device (220) may be referred to as a downstream lane. The differential output signal pair (DOUT_t, DOUT_c) transmitting data from the UFS storage device (220) to the UFS host device (210) may be referred to as an upstream lane.

[0051] According to one embodiment, the UFS host device (210) may include a processor (212) and a UFS host controller (214). The processor (212) of the UFS host device (210) may correspond to the main processor (121) of FIG. 1 (e.g., an application processor). The processor (212) may execute a program (or software) that wishes to communicate with the UFS storage device (220). The processor (212) may control the UFS host controller (214) through the UFS-HCI (host controller interface). For example, an I / O request from the processor (212) may be converted into UFS commands specified in the UFS standard through a UFS driver (not shown), and said converted UFS commands may be transmitted to the UFS host controller (214). The UFS host controller (214) may transmit said converted UFS commands to the UFS storage device (220) through the UFS interface.

[0052] According to one embodiment, the UFS storage device (220) may include a UFS device controller (222), a memory (224), and a temperature sensor (226).

[0053] The UFS device controller (222) receives a command from the UFS host device (210) and, according to the received command, reads user data from the memory (224) and provides it to the UFS host device (210), or programs the user data provided from the UFS host device (210) into the memory (224).

[0054] According to various embodiments, the UFS device controller (222) may receive a temperature sensing value from a temperature sensor (226). The UFS device controller (222) may determine the internal temperature of the UFS storage device (220) based on the received temperature sensing value. The UFS device controller (222) may transmit a status signal to the UFS host device (210) indicating a comparison result when the determined internal temperature is compared with a predefined threshold temperature. Alternatively, the UFS device controller (222) may include the determined internal temperature value in a measurement signal and transmit it to the UFS host device (210).

[0055] The memory (224) may be a non-volatile storage device that stores data regardless of whether power is supplied. The memory (224) may include non-volatile memories that store data under the control of the UFS device controller (222). For example, the non-volatile memory may include NAND flash memory, but is not limited thereto. Depending on various embodiments, the memory (224) may include other types of non-volatile memory, such as phase-change random access memory (PRAM) and / or resistive random access memory (RRAM).

[0056] According to one embodiment, the temperature sensor (226) may sense the temperature of the UFS storage device (220). For example, the temperature sensor (226) may be a sensor for sensing the temperature (e.g., internal temperature, surface temperature) of the UFS storage device (220). For example, the temperature sensor (226) may sense the temperature of the memory (224) contained within the UFS storage device (220). The temperature sensor (2260) may sense the temperature of the UFS storage device (220) based on a predefined period and transmit the sensed temperature value to the UFS device controller (222). In the above-described embodiment, the temperature sensor (226) is described as a single sensor, but is not limited thereto. According to various embodiments, the temperature sensor (226) may include a plurality of sensors (not shown) for sensing the temperature of the UFS storage device (220). The UFS device controller (222) may average the temperature sensing values ​​received from the plurality of sensors (not shown) to identify the internal temperature of the UFS storage device (220).

[0058] FIG. 2b illustrates a block diagram of a memory (224) according to various embodiments.

[0059] Referring to FIG. 2b, the memory (224) may include a cache memory (230) and a plurality of NAND flash memories (232).

[0060] The cache memory (230) can temporarily store write data received from the UFS host device (210). The cache memory (230) may be a buffer memory for write boost as defined in the UFS standard. For example, the cache memory (230) may correspond to a single-level cell (SLC) flash memory. The SLC flash memory may be a flash memory configured to store 1 bit per unit cell.

[0061] Multiple NAND flash memories (232) are non-volatile storage devices that store data even when the power supply is cut off, and can have a relatively large storage capacity compared to the cache memory (230). Multiple NAND flash memories (232) may be flash memories configured to store at least 2 bits per unit cell. For example, multiple NAND flash memories (232) may correspond to any one of MLC (multi-level cell), TLC (triple-level cell), or QLC (quadruple-level cell).

[0062] According to various embodiments, the cache memory (230) may be enabled or disabled under the control of the UFS device controller (222). For example, the UFS device controller (222) may enable the cache memory (230) in response to receiving a control signal to increase current consumption from the UFS host device (210). The control signal to increase current consumption may be generated in response to identifying that the internal temperature of the UFS storage device (220) exceeds a predefined threshold temperature. In another example, the UFS device controller (222) may disable the cache memory (230) in response to receiving a control signal to decrease current consumption from the UFS host device (210). The control signal to decrease current consumption may be generated in response to identifying that the internal temperature of the UFS storage device (220) is below a predefined threshold temperature.

[0064] FIG. 3 is a flowchart illustrating the operation of an electronic device (101) when the temperature of a UFS storage device (220) exceeds a critical temperature according to various embodiments.

[0065] Referring to FIG. 3, in operation 310, the electronic device (101) (e.g., the processor (120) of FIG. 1) can set UFS initialization and default values ​​in response to boot up. The boot up may refer to a user turning on the electronic device (101) to load an operating system (142) stored in memory (130). In response to the boot up, the electronic device (101) can determine UFS initialization and default values. The UFS initialization may refer to supplying power to the UFS storage device (220). The default values ​​are values ​​transmitted to the UFS device controller (222) and may include at least one of the following: the frequency of the reference clock (Ref_CLK) for data transmission and reception with the UFS host device (210), and a value indicating which lane is activated among the first lane (Lane_1) and the second lane (Lane_2) of the UFS interface.

[0066] In operation 320, the electronic device (101) may transmit a first control signal that enables temperature measurement of the UFS storage device (220). For example, the UFS host device (210) may control the UFS storage device (220) to measure the internal temperature using a temperature sensor (226) by transmitting the first control signal to the UFS storage device (220). According to one embodiment, the first control signal may include a "wExceptionEventControl" attribute. For example, if bit 3 of the "wExceptionEventControl" attribute is "logic high" or "1", "TOO_HIGH_TEMP_EN" may be enabled. "TOO_HIGH_TEMP_EN" may refer to the activation of an event that monitors whether the internal temperature of the UFS storage device (220) is high. The UFS storage device (220) can decode the first control signal received from the UFS host device (210) and, if bit 3 of the “wExceptionEventControl” attribute is “logic high” or “1”, activate the temperature sensor (226).

[0067] In operation 330, the electronic device (101) can identify whether the value of the status signal changes to indicate that it exceeds a threshold temperature. The UFS device controller (222) can identify whether the temperature value sensed through the temperature sensor (226) exceeds the threshold temperature. The threshold temperature may be an upper limit of a predefined temperature. For example, the UFS storage device (220) may be required to operate within the predefined temperature range to ensure the reliability of data stored in memory (224). The predefined temperature range may be from -20°C to 85°C, and the threshold temperature may correspond to 85°C. The UFS device controller (222) may transmit a status signal to the UFS host device (210) at predefined intervals, the status signal including the result of comparing the temperature sensed through the temperature sensor (226) with the threshold temperature. The status signal may include the "wExceptionEventStatus" attribute. The UFS device controller (222) can indicate the result of comparing the temperature sensed through the temperature sensor (226) with the threshold temperature through bit 3 of "wExceptionEventStatus". For example, if the temperature sensed through the temperature sensor (226) is lower than the threshold temperature, the UFS device controller (222) can transmit a status signal to the UFS host device (210) including bit 3 of "wExceptionEventStatus" which is "logic low" or "0". As another example, if the temperature sensed through the temperature sensor (226) is higher than the threshold temperature, the UFS device controller (222) can transmit a status signal to the UFS host device (210) including bit 3 of "wExceptionEventStatus" which is "logic high" or "1".

[0068] The UFS host device (210) receives the status signal from the UFS device controller (222) and checks bit 3 of the “wExceptionEventStatus” attribute to determine whether the internal temperature of the UFS storage device (220) has exceeded the threshold temperature. According to one embodiment, if the internal temperature of the UFS storage device (220) has not exceeded the threshold temperature, operation 330 may be repeated until the value of the status signal is changed to indicate that the threshold temperature has been exceeded.

[0069] In operation 340, the electronic device (101) may transmit a second control signal to the UFS device controller (222) instructing to disable at least some of the multiple downstream lanes and at least some of the multiple upstream lanes, and to disable the cache memory (230) configured to store 1 bit per unit cell of the memory (224).

[0070] If the "wExceptionEventStatus" property of the above status signal indicates that the threshold temperature is exceeded, the electronic device (101) can control the UFS storage device (220) to reduce the temperature of the UFS storage device (220). The electronic device (101) can control the UFS storage device (220) to operate within the above-defined temperature range by lowering the temperature of the UFS storage device (220) by reducing the current consumption of the UFS storage device (220).

[0071] According to one embodiment, the UFS device controller (222) may disable at least some of the plurality of downstream lanes and at least some of the plurality of upstream lanes based on the second control signal. For example, the UFS device controller (222) may disable at least one of the first lane (Lane_1) and the second lane (Lane_2). When at least one of the first lane (Lane_1) and the second lane (Lane_2) is disabled, the current consumption of the UFS storage device (220) is reduced, and based on the reduction in current consumption, the temperature of the UFS storage device (220) may also be reduced.

[0072] According to another embodiment, the UFS device controller (222) may disable a cache memory (230) configured to store 1 bit per unit cell of the memory (224) based on the second control signal. The cache memory (230) may be a buffer memory for improving write operations to a plurality of NAND flash memories (232). The UFS device controller (222) may reduce the amount of current consumed by the UFS storage device (220) by disabling the cache memory (230).

[0073] In the above-described embodiment, the cache memory (230) is described as being implemented separately from the plurality of NAND flash memories (232), but is not limited thereto. According to various embodiments, the UFS device controller (222) may perform SLC caching for write acceleration by controlling at least some area of ​​the plurality of NAND flash memories (232) to store 1 bit per unit cell. In this case, the UFS device controller (222) may reduce the temperature of the UFS storage device (220) by not allocating the at least some area for SLC caching in response to the second control signal.

[0075] FIG. 4 is a flowchart illustrating the operation of an electronic device (101) for measuring the temperature of a UFS storage device (220) according to various embodiments.

[0076] Referring to FIG. 4, in operation 410, an electronic device (101) (e.g., the processor (120) of FIG. 1) may receive a measurement signal including a temperature sensing value from a UFS device controller (222). The measurement signal may include a "bDeviceCaseRoughTemperature" attribute. The "bDeviceCaseRoughTemperature" attribute may directly include a value sensing the internal temperature of the UFS storage device (220). For example, the "bDeviceCaseRoughTemperature" attribute may include a sensing value of -79°C to 170°C. When based on a status signal including the above "wExceptionEventStatus" attribute, the UFS host device (210) can identify only that the internal temperature of the UFS storage device (220) has exceeded a threshold temperature, whereas when based on the "bDeviceCaseRoughTemperature" attribute, the UFS host device (210) can identify what the specific internal temperature of the UFS storage device (220) is.

[0077] In operation 420, the electronic device (101) can identify that the temperature sensing value exceeds the threshold temperature. The UFS host device (210) can identify whether the temperature sensing value exceeds the threshold temperature by comparing the internal temperature of the identified UFS storage device (220) with the threshold temperature based on the "bDeviceCaseRoughTemperature" attribute included in the measurement signal. Based on the identification, the UFS host device (210) can transmit the second control signal of operation 340 to the UFS storage device (220).

[0079] FIGS. 5a to 5e are flowcharts illustrating the operations of an electronic device (101) when the temperature of a UFS storage device (220) according to various embodiments exceeds a critical temperature.

[0080] Referring to FIGS. 5a through 5e, operations 510 through 530 may correspond to operations 310 through 330 shown in FIG. 3.

[0081] Referring to FIG. 5a, in operation 541, the electronic device (101) (e.g., the processor (120) of FIG. 1) may transmit a second control signal to the UFS device controller (222) that sets the delay time, during which the UFS storage device (220) waits before entering sleep mode, from a first time to a second time shorter than the first time. In operation 530, the UFS host device (210) may generate the second control signal in response to identifying that the temperature of the UFS storage device (220) exceeds the threshold temperature based on a status signal. The sleep mode may be a mode that changes the UFS storage device (220) to an inactive state to reduce power consumption of the electronic device (101) when no new data input / output request is input during the delay time from the time when data input / output between the UFS storage device (220) and the UFS host device (210) is terminated. For example, the UFS host The device (210) can control the UFS storage device (220) to enter sleep mode more quickly by using a second control signal to change the length of the waiting time of the UFS storage device (220) from the first time to the second time, which is shorter than the first time. Since the time for the UFS storage device (220) to enter sleep mode is shortened, the magnitude of the current consumed by the UFS storage device (220) is also reduced, and based on this, the internal temperature of the UFS storage device (220) can also be reduced. The delay time is a host trigger signal and can be set to various time intervals depending on the manufacturer. According to one embodiment, the second time may be the shortest time among the time intervals that the delay time can have.

[0082] Referring to FIG. 5b, in operation 543, the electronic device (101) may transmit a second control signal to the UFS device controller (222) instructing it to stop operations running in the background of the UFS device controller (222). The background may refer to operations performed by the UFS device controller (222) independently of the UFS host device (210). For example, the UFS device controller (222) may perform garbage collection without receiving a separate command from the UFS host device (210). The garbage collection may be a memory management technique to delay as much as possible the time when the limit of the Program / Erase cycle, which is the durability of non-volatile memory, is reached. For example, the UFS device controller (222) may be configured to perform the garbage collection while no read / write operations occur from the UFS host device (210). The UFS host device (210) may identify that the temperature of the UFS storage device (220) exceeds the threshold temperature based on the status signal received in operation 530 and instruct to stop background operations. The UFS storage device (220) may reduce current consumption and lower the temperature of the UFS storage device (220) by stopping background operations, including garbage collection, in accordance with the second control signal.

[0083] Referring to FIG. 5c, in operation 545, the electronic device (101) can change the operating frequency of the UFS storage device (220) from a first frequency to a second frequency lower than the first frequency and transmit a second control signal to the UFS storage device (220) instructing it to reduce the gear speed of the lane.

[0084] The operating frequency of the above UFS storage device (220) may be the frequency of the reference clock (Ref_CLK) shown in FIG. 2a. For example, the reference clock (Ref_CLK) may be any one of 19.2 MHz, 26 MHz, and 38.4 MHz.

[0085] The above gear speed may refer to a data rate, which is the speed at which the first lane (Lane_1) and / or the second lane (Lane_2) of FIG. 2a transmit data. For example, the gear speed may be divided into a pulse width modulation (PWM) gear with a low data rate and a high speed (HS) gear with a high data rate. The PWM gear and the HS gear may each be divided into four gear speeds. For example, the HS gear may be divided into HS-GEAR 1 at 1248 Mbps, HS-GEAR 2 at 2496 Mbps, HS-GEAR 3 at 4992 Mbps, and HS-GEAR 4 at 9984 Mbps.

[0086] According to one embodiment, the UFS host device (210) can reduce the operating frequency of the UFS storage device (220) from the first frequency to the second frequency and reduce the gear speed of the first lane (Lane_1) and / or the second lane (Lane_2). As the frequency of the reference clock (Ref_CLK) and the gear speed of the lane are reduced, the magnitude of the current consumed by the UFS storage device (220) is reduced, and the temperature of the UFS storage device (220) can be lowered.

[0087] Referring to FIG. 5d, in operation 547, the electronic device (101) may transmit a second control signal to the UFS device controller (222) instructing to reduce the swap size between the DRAM (dynamic random access memory) (not shown) and the memory (224). The processor (120) of the electronic device (101) may identify data programmed in the DRAM that has been called less than a predetermined number of times or has not been called for a predetermined period and swap it to the memory (224). Additionally, the electronic device (101) may identify data programmed in the memory (224) that has been called more than a predetermined number of times or has been called for a predetermined period and swap it to the DRAM (not shown). The processor (120) of the electronic device (101) can reduce the amount of current consumed by the UFS storage device (220) and lower the temperature of the UFS storage device (220) by stopping the swap between the DRAM (not shown) and the memory (224).

[0088] Referring to FIG. 5e, in operation 549, the electronic device (101) may display a visual object to indicate that the operation speed of the electronic device (101) may be slowed down, or output an auditory notification. For example, the processor (120) may display a visual object containing the phrase "The temperature of the terminal is too high" or "The speed may be slowed down due to the high temperature of the terminal" on the screen via the display module (160). As another example, the processor (120) may output a text-to-speech (TTS) converted voice of the phrase via the sound output module (155).

[0090] FIG. 6 is a flowchart illustrating the operation of an electronic device (101) when the temperature of a UFS storage device (220) is below a critical temperature according to various embodiments.

[0091] Referring to FIG. 6, in operation 610, an electronic device (101) (e.g., the processor (120) of FIG. 1) may request the UFS storage device (220) to transmit a status signal at predefined intervals. For example, the UFS host device (210) of the electronic device (101) may transmit a signal requesting a status signal to the UFS device controller (222) of the UFS storage device (220) whenever a specific amount of time has elapsed. According to another embodiment, the UFS host device (210) may request the UFS device controller (222) to transmit the status signal whenever a read / write operation requested from the UFS storage device (220) is completed.

[0092] According to various embodiments, the predefined period may correspond to any one of a plurality of predetermined periods between the UFS host device (210) and the UFS storage device (220). In this case, the UFS host device (210) may include a value indicating any one of the plurality of periods in the first control signal and transmit it to the UFS device controller (222). The UFS device controller (222) may use the value indicating any one of the plurality of periods to identify at which period the status signal must be transmitted to the UFS device controller (222).

[0093] In operation 620, the electronic device (101) can identify whether the value of the status signal has changed to indicate less than the threshold temperature. For example, if bit 3 of the "wExceptionEventStatus" attribute included in the status signal is "logic high" or "1", it can identify that the internal temperature of the UFS storage device (220) still exceeds the threshold temperature and the reliability of the data cannot be guaranteed. As another example, if bit 3 of the "wExceptionEventStatus" attribute included in the status signal is "logic low" or "0", the UFS host device (210) can identify that the internal temperature of the UFS storage device (220) has dropped below the threshold temperature.

[0094] In operation 630, the electronic device (101) may transmit a third control signal to the UFS device controller (222) instructing it to change the setting value of the UFS device controller (222) to a default setting value. For example, if bit 3 of the "wExceptionEventStatus" attribute included in the status signal of operation 620 is "logic low" or "0", the UFS host device (210) can identify that the UFS storage device (220) is operating within a temperature range where data reliability is guaranteed. Accordingly, the UFS host device (210) can reconfigure the UFS storage device (220) according to the default setting value determined at the time of UFS initialization in response to the boot-up in operation 310 of FIG. 3.

[0095] According to various embodiments, the UFS host device (210) may not immediately transmit the third control signal even if the value of the status signal received in operation 620 is changed to indicate that it is less than the threshold temperature. For example, the UFS host device (210) may identify in operation 620 that the value of the status signal indicates that it is less than the threshold temperature and may request the measurement signal again from the UFS device controller (222). The UFS host device (210) may compare the temperature sensing value included in the measurement signal with an additional threshold temperature. The additional threshold temperature may be a temperature lower than the threshold temperature. For example, if the threshold temperature is 85°C, the additional threshold temperature may be 60°C. This may be because if the setting value of the UFS device controller (222) is changed to the default setting value via the third control signal immediately after the temperature of the UFS storage device (220) has fallen below the threshold temperature, the temperature of the UFS storage device (220) may exceed the threshold temperature in a short period of time.

[0096] In the above-described embodiment, it is described that a status signal is transmitted from the UFS device controller (222) to the UFS host device (210) at predetermined intervals, but is not limited thereto. According to various embodiments, the UFS device controller (222) may transmit a measurement signal including a temperature sensing value of the UFS storage device (220) at the predetermined intervals. When the UFS host device (210) receives the measurement signal, the UFS host device (210) may determine whether to transmit the third control signal to the UFS device controller (222) by comparing the temperature sensing value included in the received measurement signal with the threshold temperature.

[0098] FIG. 7 is a flowchart illustrating the operation of an electronic device (101) when the temperature of a UFS storage device (220) is below a critical temperature according to various embodiments.

[0099] Referring to FIG. 7, in operation 710, the electronic device (101) (e.g., the processor (120) of FIG. 1) may set UFS initialization and default values ​​in response to boot up. The boot up may refer to a user turning on the electronic device (101) to load an operating system (142) stored in memory (130). In response to the boot up, the electronic device (101) may determine UFS initialization and default values. The UFS initialization may refer to supplying power to the UFS storage device (220). The default values ​​are values ​​transmitted to the UFS device controller (222) and may include at least one of the following: the frequency of the reference clock (Ref_CLK) for data transmission and reception with the UFS host device (210), and a value indicating which lane is activated among the first lane (Lane_1) and the second lane (Lane_2) of the UFS interface.

[0100] In operation 720, the electronic device (101) may transmit a first control signal to enable temperature measurement of the UFS storage device (220). For example, the UFS host device (210) may control the UFS storage device (220) to measure the internal temperature using a temperature sensor (226) by transmitting the first control signal to the UFS storage device (220). According to one embodiment, the first control signal may include a "wExceptionEventControl" attribute. For example, if bit 4 of the "wExceptionEventControl" attribute is "logic high" or "1", "TOO_LOW_TEMP_EN" may be enabled. "TOO_LOW_TEMP_EN" may refer to the activation of an event that monitors whether the internal temperature of the UFS storage device (220) is low. The UFS storage device (220) can decode the first control signal received from the UFS host device (210) and, if bit 4 of the “wExceptionEventControl” attribute is “logic high” or “1”, activate the temperature sensor (226).

[0101] In operation 730, the electronic device (101) can identify whether the value of the status signal changes to indicate that it is less than a threshold temperature. The UFS device controller (222) can identify whether the temperature value sensed through the temperature sensor (226) exceeds the threshold temperature. The threshold temperature may be a lower limit value of a predefined temperature. For example, the UFS storage device (220) may be required to operate within the predefined temperature range to ensure the reliability of data stored in memory (224). The predefined temperature range may be from -20°C to 85°C, and the threshold temperature may correspond to -20°C. The UFS device controller (222) may transmit a status signal to the UFS host device (210) at predefined intervals, the result of comparing the temperature sensed through the temperature sensor (226) with the threshold temperature. The status signal may include the "wExceptionEventStatus" attribute. The UFS device controller (222) can indicate the result of comparing the temperature sensed through the temperature sensor (226) with the threshold temperature through bit 4 of "wExceptionEventStatus". For example, if the temperature sensed through the temperature sensor (226) is higher than the threshold temperature, the UFS device controller (222) can transmit a status signal to the UFS host device (210) including bit 4 of "wExceptionEventStatus" which is "logic low" or "0". As another example, if the temperature sensed through the temperature sensor (226) is lower than the threshold temperature, the UFS device controller (222) can transmit a status signal to the UFS host device (210) including bit 4 of "wExceptionEventStatus" which is "logic high" or "1".

[0102] The UFS host device (210) receives the status signal from the UFS device controller (222) and checks bit 4 of the “wExceptionEventStatus” attribute to determine whether the internal temperature of the UFS storage device (220) is less than the threshold temperature. According to one embodiment, if the internal temperature of the UFS storage device (220) is greater than or equal to the threshold temperature, operation 730 may be repeated until the value of the status signal is changed to indicate that it is less than the threshold temperature.

[0103] In operation 740, the electronic device (101) may transmit a second control signal to the UFS device controller (222) instructing to activate at least some of the inactive lanes among the plurality of downstream lanes and at least some of the inactive lanes among the plurality of upstream lanes, and to activate the cache memory (230) configured to store 1 bit per unit cell among the memory (224).

[0104] If the "wExceptionEventStatus" attribute of the above status signal indicates that the temperature of the UFS storage device (220) is below the threshold temperature, the electronic device (101) can control the UFS storage device (220) to raise the temperature of the UFS storage device (220). The electronic device (101) can control the UFS storage device (220) to operate within the above-defined temperature range by raising the temperature of the UFS storage device (220) by increasing the current consumption of the UFS storage device (220).

[0105] According to one embodiment, the UFS device controller (222) may disable at least some of the inactive lanes among the plurality of downstream lanes and at least some of the inactive lanes among the plurality of upstream lanes based on the second control signal. For example, the UFS device controller (222) may enable the disabled lanes among the first lane (Lane_1) and the second lane (Lane_2). When both the first lane (Lane_1) and the second lane (Lane_2) are enabled according to the activation, the current consumption of the UFS storage device (220) increases, and the temperature of the UFS storage device (220) may also increase based on the increase in current consumption.

[0106] According to another embodiment, the UFS device controller (222) may enable a cache memory (230) configured to store 1 bit per unit cell of the memory (224) based on the second control signal. The cache memory (230) may be a buffer memory for improving write operations to a plurality of NAND flash memories (232). The UFS device controller (222) may enable the cache memory (230) to increase the magnitude of the current consumption of the UFS storage device (220).

[0107] In the above-described embodiment, the cache memory (230) is described as being implemented separately from the plurality of NAND flash memories (232), but is not limited thereto. According to various embodiments, the UFS device controller (222) may perform SLC caching for write acceleration by controlling at least some area of ​​the plurality of NAND flash memories (232) to store 1 bit per unit cell. In this case, the UFS device controller (222) may increase the temperature of the UFS storage device (220) by increasing the size of the at least some area for SLC caching in response to the second control signal.

[0109] FIGS. 8a to 8e are flowcharts illustrating the operation of an electronic device (101) when the temperature of a UFS storage device (220) according to various embodiments is below a critical temperature.

[0110] Referring to FIGS. 8a through 8e, operations 810 through 830 may correspond to operations 710 through 730 shown in FIG. 7.

[0111] Referring to FIG. 8a, in operation 841, the electronic device (101) (e.g., the processor (120) of FIG. 1) may transmit a second control signal to the UFS device controller (222) to set the delay time, which the UFS storage device (220) waits for before entering sleep mode, from a first time to a second time longer than the first time. In operation 830, the UFS host device (210) may generate the second control signal in response to identifying that the temperature of the UFS storage device (220) is below the threshold temperature based on a status signal. The sleep mode may be a mode that changes the UFS storage device (220) to an inactive state to reduce power consumption of the electronic device (101) when no new data input / output request is input during the delay time from the time when data input / output between the UFS storage device (220) and the UFS host device (210) is terminated. For example, the UFS host device (210) can control the UFS storage device (220) to enter sleep mode more slowly by using a second control signal to change the length of the waiting time of the UFS storage device (220) from the first time to the second time, which is longer than the first time. Since the time for the UFS storage device (220) to start entering sleep mode is extended, the power consumption of the UFS storage device (220) before entry is also increased, and based on this, the internal temperature of the UFS storage device (220) may also increase. The delay time is a host trigger signal and can be set to various time intervals depending on the manufacturer. According to one embodiment, the second time may be the longest time among the time intervals that the delay time can have.

[0112] Referring to FIG. 8b, in operation 843, the electronic device (101) may transmit a second control signal to the UFS device controller (222) instructing it to perform tasks that are executed in the background of the UFS device controller (222). The background may refer to tasks performed by the UFS device controller (222) independently of the UFS host device (210). For example, the UFS device controller (222) may perform garbage collection without receiving a separate command from the UFS host device (210). The garbage collection may be a memory management technique to delay as much as possible the time when the limit of the program / erase cycle, which is the durability of non-volatile memory, is reached. For example, the UFS device controller (222) may be configured to perform the garbage collection while no read and / or write operations occur from the UFS host device (210).

[0113] The UFS host device (210) may identify, based on a status signal received from operation 830, that the temperature of the UFS storage device (220) is below the threshold temperature and instruct it to perform background operations. The UFS storage device (220) may increase the current consumption and increase the temperature of the UFS storage device (220) by performing background operations, including garbage collection, in accordance with the second control signal.

[0114] Referring to FIG. 8c, in operation 845, the electronic device (101) can change the operating frequency of the UFS storage device (220) from a first frequency to a second frequency higher than the first frequency and transmit a second control signal to the UFS storage device (220) instructing it to increase the gear speed of the lane.

[0115] The operating frequency of the above UFS storage device (220) may be the frequency of the reference clock (Ref_CLK) shown in FIG. 2a. For example, the reference clock (Ref_CLK) may be any one of 19.2 MHz, 26 MHz, and 38.4 MHz.

[0116] The above gear speed may refer to a data rate, which is the speed at which the first lane (Lane_1) and / or the second lane (Lane_2) of FIG. 2a transmit data. For example, the gear speed may be divided into a pulse width modulation (PWM) gear with a low data rate and a high speed (HS) gear with a high data rate. The PWM gear and the HS gear may each be divided into four gear speeds. For example, the HS gear may be divided into HS-GEAR 1 at 1248 Mbps, HS-GEAR 2 at 2496 Mbps, HS-GEAR 3 at 4992 Mbps, and HS-GEAR 4 at 9984 Mbps.

[0117] According to one embodiment, the UFS host device (210) can increase the operating frequency of the UFS storage device (220) from the first frequency to the second frequency and increase the gear speed of the first lane (Lane_1) and / or the second lane (Lane_2). As the frequency of the reference clock (Ref_CLK) and the gear speed of the lane decrease, the magnitude of the current consumed by the UFS storage device (220) increases, and the temperature of the UFS storage device (220) may increase.

[0118] Referring to FIG. 8d, in operation 847, the electronic device (101) may transmit a second control signal to the UFS device controller (222) instructing to increase the swap size between the DRAM (dynamic random access memory) (not shown) and the memory (224). The processor (120) of the electronic device (101) may identify data programmed in the DRAM that has been called less than a predetermined number of times or has not been called for a predetermined period and swap it to the memory (224). Additionally, the electronic device (101) may identify data programmed in the memory (224) that has been called more than a predetermined number of times or has been called for a predetermined period and swap it to the DRAM (not shown). The processor (120) of the electronic device (101) can increase the amount of current consumed by the UFS storage device (220) and increase the temperature of the UFS storage device (220) by increasing the size of the swap between the DRAM (not shown) and the memory (224).

[0119] Referring to FIG. 8e, in operation 849, the electronic device (101) may display a visual object to indicate that there is a possibility of malfunction of the electronic device (101) or output an auditory notification. For example, the processor (120) may display a visual object containing a warning phrase such as "The temperature of the terminal is too low" or "The temperature of the terminal is too low and an error may occur" on the screen via the display module (160). As another example, the processor (120) may output a text-to-speech (TTS) converted voice of the warning phrase via the sound output module (155).

[0121] FIG. 9 is a flowchart illustrating the operation of an electronic device (101) when the temperature of a UFS storage device (220) exceeds a critical temperature according to various embodiments.

[0122] Referring to FIG. 9, in operation 910, the electronic device (101) may request the UFS storage device (220) to transmit a status signal at predefined intervals. For example, the UFS host device (210) of the electronic device (101) may transmit a signal requesting a status signal to the UFS device controller (222) of the UFS storage device (220) whenever a specific time elapses. According to another embodiment, the UFS host device (210) may request the UFS device controller (222) to transmit the status signal whenever the read and / or write operation requested from the UFS storage device (220) is completed.

[0123] According to various embodiments, the predefined period may correspond to any one of a plurality of predetermined periods between the UFS host device (210) and the UFS storage device (220). In this case, the UFS host device (210) may include a value indicating any one of the plurality of periods in the first control signal and transmit it to the UFS device controller (222). The UFS device controller (222) may use the value indicating any one of the plurality of periods to identify at which period the status signal must be transmitted to the UFS device controller (222).

[0124] In operation 920, the electronic device (101) can identify whether the value of the status signal has changed to indicate that the threshold temperature has been exceeded. For example, if bit 4 of the "wExceptionEventStatus" attribute included in the status signal is "logic high" or "1", it can identify that the internal temperature of the UFS storage device (220) is still a low temperature below the threshold temperature and that the reliability of the data cannot be guaranteed. As another example, if bit 4 of the "wExceptionEventStatus" attribute included in the status signal is "logic low" or "0", the UFS host device (210) can identify that the internal temperature of the UFS storage device (220) has risen to exceed the threshold temperature.

[0125] In operation 930, the electronic device (101) may transmit a third control signal to the UFS device controller (222) instructing it to change the setting value of the UFS device controller (222) to a default setting value. For example, if bit 4 of the "wExceptionEventStatus" attribute included in the status signal of operation 620 is "logic low" or "0", the UFS host device (210) can identify that the UFS storage device (220) is operating within a temperature range where data reliability is guaranteed. Accordingly, the UFS host device (210) can reconfigure the UFS storage device (220) according to the default setting value determined at the time of UFS initialization in response to the boot-up in operation 310 of FIG. 3.

[0126] According to various embodiments, the UFS host device (210) may not immediately transmit the third control signal even if the value of the status signal received in operation 920 is changed to indicate that it is less than the threshold temperature. For example, the UFS host device (210) may identify in operation 620 that the value of the status signal indicates that it is less than the threshold temperature and may request the measurement signal again from the UFS device controller (222). The UFS host device (210) may compare the temperature sensing value included in the measurement signal with an additional threshold temperature. The additional threshold temperature may be a temperature higher than the threshold temperature. For example, if the threshold temperature is -20°C, the additional threshold temperature may be -10°C. This is because if the setting value of the UFS device controller (222) is changed to the default setting value via the third control signal immediately after the temperature of the UFS storage device (220) has dropped below the threshold temperature, the temperature of the UFS storage device (220) may drop below the threshold temperature in a short period of time.

[0127] In the above-described embodiment, it is described that a status signal is transmitted from the UFS device controller (222) to the UFS host device (210) at predetermined intervals, but is not limited thereto. According to various embodiments, the UFS device controller (222) may transmit a measurement signal including a temperature sensing value of the UFS storage device (220) at the predetermined intervals. When the UFS host device (210) receives the measurement signal, the UFS host device (210) may determine whether to transmit the third control signal to the UFS device controller (222) by comparing the temperature sensing value included in the received measurement signal with the threshold temperature.

[0129] FIG. 10 illustrates a UFS card (1000) according to various embodiments.

[0130] Referring to FIG. 10, the UFS card (1000) may include a UFS device controller (1010) and storage (1020). The UFS card (1000) may have a form similar to a memory card and may be coupled to other components of the electronic device (101) via a connection interface so as to be detachable and attachable. The UFS card (1000) may be a device to which a standard protocol such as Universal Flash Storage (UFS) applies.

[0131] According to one embodiment, the connection interface may provide a connection that allows data to be exchanged between an electronic device (101) and a UFS card (1000). The connection interface may be implemented in various interface methods such as ATA (Advanced Technology Attachment), SATA (Serial ATA), e-SATA (external SATA), SCSI (Small Computer Small Interface), SAS (Serial Attached SCSI), PCI (Peripheral Component Interconnection), PCIe (PCI express), NVMe (NVM express), IEEE 1394, USB (universal serial bus), SD (secure digital) card, MMC (multi-media card), eMMC (embedded multi-media card), UFS (Universal Flash Storage), eUFS (embedded Universal Flash Storage), and CF (compact flash) card interfaces.

[0132] A UFS card (1000) according to one embodiment receives a first control signal from an electronic device (101) connected through the connection interface, senses the temperature of the UFS card (1000), identifies whether the temperature sense value is outside a predefined temperature range that can guarantee data reliability, transmits a status signal to the electronic device (101), and receives a second control signal from the electronic device (101) to change at least one of the operating frequency of the UFS card (1000), the gear speed of the lane, the number of activated lanes, whether the SLC caching of the memory (224) is enabled, the length of the delay time waiting before entering sleep mode, whether tasks running in the background of the UFS card (1000) are stopped, and the swap size between the DRAM (not shown) of the electronic device (101) and the UFS card (1000).

[0134] FIG. 11 is a flowchart illustrating the operation of an electronic device (101) when the temperature of a UFS storage device (220) exceeds a first threshold temperature or is less than a second threshold temperature, according to various embodiments.

[0135] Referring to FIG. 11, in operation 1110, the electronic device (101) (e.g., the processor (120) of FIG. 1) can initialize the UFS and set default values ​​in response to boot up. The operation 1110 may correspond to operation 310 of FIG. 3.

[0136] In operation 1120, the electronic device (101) may transmit a first control signal that enables temperature measurement of the UFS storage device (220). The operation 1120 may correspond to operation 320 of FIG. 3.

[0137] In operation 1130, the electronic device (101) can identify whether the value of the status signal changes to indicate that it exceeds a first threshold temperature. The first threshold temperature may be the largest value among the temperature ranges for ensuring the reliability of data stored in memory (224). The UFS host device (210) receives a status signal from the UFS device controller (222) and, based on the status signal, can identify whether the temperature of the UFS storage device (220) exceeds the first threshold temperature.

[0138] In operation 1140, the electronic device (101) may transmit a second control signal to the UFS storage device (220) indicating a plurality of first events to reduce the current consumption. In operation 1130, since it is identified that the temperature of the UFS storage device (220) exceeds the first threshold temperature, the UFS host device (210) may control the UFS storage device (220) to operate within the temperature range for reliability assurance by reducing the temperature of the UFS storage device (220). Accordingly, the UFS host device (210) may transmit a plurality of first events to reduce the heat generation of the UFS storage device (220) by reducing the magnitude of the current consumption to the UFS device controller (222) of the UFS storage device (220) through the second control signal. The plurality of first events may include at least one of operation 340 of FIG. 3 and operations 541 to 549 of FIG. 5a to 5e.

[0139] In operation 1150, the electronic device (101) can identify whether the value of the status signal changes to indicate that it is less than the second threshold temperature. The second threshold temperature may be the smallest value among the temperature ranges for ensuring the reliability of data stored in memory (224). The UFS host device (210) receives a status signal from the UFS device controller (222) and, based on the status signal, can identify whether the temperature of the UFS storage device (220) is less than the second threshold temperature. If the temperature of the UFS storage device (220) is greater than the second threshold temperature, the UFS host device (210) can identify that the UFS storage device (220) is operating within the temperature range for ensuring reliability and can repeat operation 1130 to monitor the internal temperature.

[0140] In operation 1160, the electronic device (101) can transmit a second control signal to the UFS storage device (220) indicating a plurality of second events to increase the current consumption. In operation 1150, since it is identified that the temperature of the UFS storage device (220) is below the second threshold temperature, the UFS host device (210) can control the UFS storage device (220) to operate within the temperature range for reliability assurance by increasing the temperature of the UFS storage device (220). Accordingly, the UFS host device (210) can increase the magnitude of the current consumption to generate heat in the UFS storage device (220) and, accordingly, transmit a plurality of second events to increase the temperature of the UFS storage device (220) to the UFS device controller (222) of the UFS storage device (220) through the second control signal. The plurality of second events may include at least one of operation 740 of FIG. 7 and operations 841 to 849 of FIG. 8a to 8e.

[0142] According to one embodiment, an electronic device comprises at least one processor, a universal flash storage (UFS) device controller operatively coupled with the at least one processor, a UFS interface including downstream lanes for transmitting data from the at least one processor to the UFS device controller and upstream lanes for transmitting data from the UFS device controller to the at least one processor, and storage including a plurality of non-volatile memories and a cache memory, wherein the at least one processor, in response to boot up of the at least one processor, measures the temperature of the storage using a temperature sensor operatively coupled with the UFS device controller, transmits a first control signal to the UFS device controller to indicate identifying that the measured temperature exceeds a threshold value, receives a status signal from the UFS device controller indicating that the temperature of the storage measured through the temperature sensor exceeds the threshold value, and based on the status signal, disables at least some of the plurality of downstream lanes and at least some of the plurality of upstream lanes through the UFS device controller. A second control signal instructing the UFS device controller to disable the cache memory configured to store 1 bit per unit cell among the storage above may be configured to be transmitted.

[0143] According to one embodiment, the at least one processor may be configured to transmit the second control signal to the UFS device controller, based on the status signal, the second control signal which sets the delay time for the storage to wait before entering sleep mode from a first time to a second time shorter than the first time.

[0144] According to one embodiment, the second time may correspond to the minimum value among the time ranges in which the delay time can be set.

[0145] According to one embodiment, the at least one processor may be configured to transmit the second control signal to the UFS device controller, which instructs the UFS device controller to stop tasks running in the background based on the status signal.

[0146] According to one embodiment, the background operations may include garbage collection and wear leveling.

[0147] According to one embodiment, the at least one processor may be configured to transmit the second control signal to the UFS device controller, which instructs the UFS device controller to change the operating frequency of the UFS device controller from a first frequency to a second frequency lower than the first frequency, based on the status signal.

[0148] According to one embodiment, the second frequency may correspond to the smallest frequency among a plurality of frequency values ​​that the operating frequency of the UFS device controller may have.

[0149] According to one embodiment, the second frequency may be varied based on the size of the transmission and reception bandwidth between the UFS device controller and the at least one processor.

[0150] According to one embodiment, the first control signal corresponds to a signal including a wExceptionEventControl value, and the status signal may correspond to a signal including a wExceptionEventStatus value.

[0151] According to one embodiment, the electronic device further comprises a dynamic random access memory (DRAM) operatively coupled with the at least one processor, and the at least one processor may be configured to transmit the second control signal to the UFS device controller, which instructs to bypass a request to read at least some of the data stored in the plurality of nonvolatile memories in order to program at least some of the data stored in the DRAM into the plurality of nonvolatile memories or to write at least some of the data stored in the plurality of nonvolatile memories to the DRAM.

[0152] According to one embodiment, the at least one processor may be configured to display a visual object to indicate that the operating speed of the electronic device may be slowed down through a display operatively coupled to the at least one processor, or to output an auditory notification to indicate that the operating speed of the electronic device may be slowed down through an audio output module operatively coupled to the at least one processor, based on the status signal.

[0153] According to one embodiment, the cache memory corresponds to a single-level cell (SLC) flash memory, and the plurality of non-volatile memories may correspond to at least one of a multi-level cell (MLC) flash memory, a triple-level cell (TLC) flash memory, and a quadruple-level cell (QLC) flash memory, configured to store at least 2 bits per unit cell.

[0154] According to one embodiment, the at least one processor may be configured to receive a measurement signal indicating the temperature value of the storage, by requesting the temperature value of the storage measured by the UFS device controller using the temperature sensor in response to receiving the status signal.

[0155] According to one embodiment, the at least one processor may be configured to request the measurement signal from the UFS device controller at predetermined intervals and, in response to identifying that the temperature of the storage identified through the measurement signal is included within a predetermined temperature range, to transmit a third control signal to the UFS device controller instructing to reactivate at least some of the disabled downstream lanes and at least some of the disabled upstream lanes and to reactivate the disabled cache memory.

[0156] According to one embodiment, the at least one processor may be configured to request the UFS device controller to transmit the status signal to the at least one processor at predefined intervals, and, in response to identifying that the temperature of the storage is less than the threshold value based on the status signal, to reactivate at least some of the disabled downstream lanes and at least some of the disabled upstream lanes, and to transmit a third control signal to the UFS device controller instructing to reactivate the disabled cache memory.

[0158] According to one embodiment, an electronic device comprises at least one processor, a universal flash storage (UFS) device controller operatively coupled with the at least one processor, a UFS interface including downstream lanes for transmitting data from the at least one processor to the UFS device controller and upstream lanes for transmitting data from the UFS device controller to the at least one processor, and storage including a plurality of non-volatile memories and a cache memory, wherein the at least one processor transmits a first control signal to the UFS device controller in response to the boot-up of the at least one processor to instruct to identify whether the temperature of the storage measured using a temperature sensor operatively coupled with the UFS device controller is less than a threshold value, receives a status signal from the UFS device controller to indicate that the temperature of the storage is less than the threshold value, and based on the status signal, activates a deactivated lane among the plurality of downstream lanes and the plurality of upstream lanes through the UFS device controller, and 1 bit per unit cell of the storage It may be configured to transmit a second control signal to the UFS device controller instructing it to activate the cache memory configured to store.

[0159] According to one embodiment, the at least one processor may be configured to transmit the second control signal to the UFS device controller, based on the status signal, the second control signal which sets the delay time for the storage to wait before entering sleep mode from a first time to a second time longer than the first time.

[0160] According to one embodiment, the second time may correspond to the maximum value among the time ranges in which the delay time can be set.

[0161] According to one embodiment, the at least one processor may be configured to transmit the second control signal to the UFS device controller, which instructs the execution of tasks executed in the background of the UFS device controller based on the status signal.

[0162] According to one embodiment, the background operations may include garbage collection and wear leveling.

[0163] According to one embodiment, the at least one processor may be configured to transmit the second control signal to the UFS device controller, which instructs the UFS device controller to change the operating frequency of the UFS device controller from a first frequency to a second frequency higher than the first frequency, based on the status signal.

[0164] According to one embodiment, the second frequency may correspond to the highest frequency among a plurality of frequency values ​​that the operating frequency of the UFS device controller may have.

[0165] According to one embodiment, the second frequency may be varied based on the size of the transmission and reception bandwidth between the UFS device controller and the at least one processor.

[0166] According to one embodiment, the first control signal corresponds to a signal including a wExceptionEventControl value, and the status signal may correspond to a signal including a wExceptionEventStatus value.

[0167] According to one embodiment, the electronic device further comprises a dynamic random access memory (DRAM) operatively coupled with the at least one processor, and the at least one processor may be configured to transmit to the UFS device controller the second control signal instructing to increase the size of data for programming at least a portion of the data stored in the DRAM into the plurality of nonvolatile memories, or the size of data for requesting a read of at least a portion of the data stored in the plurality of nonvolatile memories in order to write at least a portion of the data stored in the plurality of nonvolatile memories to the DRAM.

[0168] According to one embodiment, the at least one processor may be configured to display a visual object to indicate the possibility of a malfunction of the electronic device through a display operatively coupled to the at least one processor, or to output an auditory notification to indicate the possibility of a malfunction of the electronic device through an audio output module operatively coupled to the at least one processor, based on the status signal.

[0169] According to one embodiment, the cache memory corresponds to a single-level cell (SLC) flash memory, and the plurality of non-volatile memories may correspond to at least one of a multi-level cell (MLC) flash memory, a triple-level cell (TLC) flash memory, and a quadruple-level cell (QLC) flash memory, configured to store at least 2 bits per unit cell.

[0170] According to one embodiment, the at least one processor may be configured to receive a measurement signal indicating the temperature value of the storage, by requesting the temperature value of the storage measured by the UFS device controller using the temperature sensor in response to receiving the status signal.

[0171] According to one embodiment, the at least one processor may be configured to request the measurement signal from the UFS device controller at predetermined intervals and, in response to identifying that the temperature of the storage identified through the measurement signal is included within a predetermined temperature range, to transmit a third control signal to the UFS device controller instructing to deactivate at least some of the activated downstream lanes and at least some of the activated upstream lanes again and to deactivate the activated cache memory again.

[0172] According to one embodiment, the at least one processor may be configured to request the UFS device controller to transmit the status signal to the at least one processor at predefined intervals, and, in response to identifying that the temperature of the storage is less than the threshold value based on the status signal, to transmit a third control signal to the UFS device controller instructing to deactivate at least some of the activated downstream lanes and at least some of the activated upstream lanes again and to deactivate the activated cache memory again.

[0174] According to one embodiment, an electronic device comprises at least one processor, a universal flash storage (UFS) device controller operatively coupled with the at least one processor, a UFS interface including downstream lanes for transmitting data from the at least one processor to the UFS device controller and upstream lanes for transmitting data from the UFS device controller to the at least one processor, and storage including a plurality of non-volatile memories and a cache memory, wherein the at least one processor transmits a first control signal to the UFS device controller in response to the boot-up of the at least one processor, instructing to identify that the temperature of the storage measured using a temperature sensor operatively coupled with the UFS device controller exceeds a first threshold value or is less than a second threshold value which is smaller than the first threshold value, and transmits a second control signal to the UFS device controller in response to receiving a status signal from the UFS device controller indicating that the temperature of the storage exceeds the first threshold value, instructing a plurality of first events for reducing the current consumption of the UFS device controller. It may be configured to transmit, and in response to receiving a status signal from the UFS device controller indicating that the temperature of the storage is less than the second threshold value, to transmit a second control signal to the UFS device controller indicating a plurality of second events for increasing the current consumption of the UFS device controller.

[0176] According to one embodiment, a method of operation of an electronic device comprising at least one processor, a universal flash storage (UFS) device controller operatively coupled with the at least one processor, a UFS interface including downstream lanes for transmitting data from the at least one processor to the UFS device controller and upstream lanes for transmitting data from the UFS device controller to the at least one processor, and storage including a plurality of non-volatile memories and a cache memory, comprises: an operation of measuring the temperature of the plurality of non-volatile memories using a temperature sensor operatively coupled with the UFS device controller in response to the boot-up of the at least one processor; an operation of transmitting a first control signal to the UFS device controller to indicate that the measured temperature exceeds a threshold value; an operation of receiving a status signal from the UFS device controller indicating that the temperature of the plurality of non-volatile memories measured through the temperature sensor exceeds the threshold value; and, based on the status signal, through the UFS device controller, at least some of the plurality of downstream lanes and the plurality of upstream It may include the operation of transmitting a second control signal to the UFS device controller, which instructs to disable at least some of the lanes and disable the cache memory configured to store 1 bit per unit cell of the storage.

[0178] A method of operation of an electronic device according to one embodiment comprising at least one processor, a universal flash storage (UFS) device controller operatively coupled with the at least one processor, a UFS interface including downstream lanes for transmitting data from the at least one processor to the UFS device controller and upstream lanes for transmitting data from the UFS device controller to the at least one processor, and storage including a plurality of non-volatile memories and a cache memory, comprises: transmitting a first control signal to the UFS device controller in response to the boot-up of the at least one processor to instruct to identify whether the temperature of the storage measured using a temperature sensor operatively coupled with the UFS device controller is less than a threshold value; receiving a status signal from the UFS device controller to indicate that the temperature of the storage is less than the threshold value; and, based on the status signal, activating a deactivated lane among the plurality of downstream lanes and the plurality of upstream lanes through the UFS device controller and storing 1 bit per unit cell of the storage. It may include the operation of transmitting a second control signal to the UFS device controller instructing it to activate the configured cache memory.

[0180] A method of operation of an electronic device according to one embodiment comprising at least one processor, a universal flash storage (UFS) device controller operatively coupled with the at least one processor, a UFS interface including downstream lanes for transmitting data from the at least one processor to the UFS device controller and upstream lanes for transmitting data from the UFS device controller to the at least one processor, and storage including a plurality of non-volatile memories and a cache memory, comprises the operation of transmitting a first control signal to the UFS device controller in response to the boot-up of the at least one processor, instructing to identify that the temperature of the storage measured using a temperature sensor operatively coupled with the UFS device controller exceeds a first threshold value or is less than a second threshold value which is smaller than the first threshold value; and, in response to receiving a status signal from the UFS device controller indicating that the temperature of the storage exceeds the first threshold value, transmitting a second control signal to the UFS device controller instructing a plurality of first events for reducing the current consumption of the UFS device controller. The operation may include, in response to receiving a status signal from the UFS device controller indicating that the temperature of the storage is less than the second threshold value, transmitting a second control signal to the UFS device controller indicating a plurality of second events to increase the current consumption of the UFS device controller.

[0182] According to one embodiment, a non-transient computer-readable storage medium comprises, when executed by at least one processor of an electronic device including at least one processor, a universal flash storage (UFS) device controller operatively coupled with the at least one processor, a UFS interface comprising downstream lanes for transmitting data from the at least one processor to the UFS device controller and upstream lanes for transmitting data from the UFS device controller to the at least one processor, and storage comprising a plurality of non-volatile memories and a cache memory, in response to the boot-up of the at least one processor, a first control signal for instructing to measure the temperature of the plurality of non-volatile memories using a temperature sensor operatively coupled with the UFS device controller and to identify that the measured temperature exceeds a threshold value, and receiving a status signal from the UFS device controller indicating that the temperature of the plurality of non-volatile memories measured through the temperature sensor exceeds the threshold value, and based on the status signal, through the UFS device controller, the plurality of downstream One or more programs including instructions that cause the electronic device to transmit a second control signal to the UFS device controller, which instructs to disable at least some of the lanes and at least some of the plurality of upstream lanes, and to disable the cache memory configured to store 1 bit per unit cell of the storage.

[0184] According to one embodiment, a non-transient computer-readable storage medium comprises, when executed by at least one processor of an electronic device including at least one processor, a universal flash storage (UFS) device controller operatively coupled with the at least one processor, a UFS interface comprising downstream lanes for transmitting data from the at least one processor to the UFS device controller and upstream lanes for transmitting data from the UFS device controller to the at least one processor, and storage comprising a plurality of non-volatile memories and a cache memory, a first control signal for instructing to identify whether the temperature of the storage measured using a temperature sensor operatively coupled with the UFS device controller is less than a threshold value in response to the boot-up of the at least one processor, a status signal for instructing to identify whether the temperature of the storage is less than the threshold value is received from the UFS device controller, and based on the status signal, through the UFS device controller, a deactivated lane among the plurality of downstream lanes and the plurality of upstream lanes One or more programs including instructions that cause the electronic device to transmit a second control signal to the UFS device controller, which instructs the device to activate a cache memory configured to store 1 bit per unit cell of the storage.

[0186] According to one embodiment, a non-transient computer-readable storage medium comprises, when executed by at least one processor of an electronic device including at least one processor, a universal flash storage (UFS) device controller operatively coupled with the at least one processor, a UFS interface comprising downstream lanes for transmitting data from the at least one processor to the UFS device controller and upstream lanes for transmitting data from the UFS device controller to the at least one processor, and storage comprising a plurality of non-volatile memories and a cache memory, a first control signal for instructing to identify, in response to the boot-up of the at least one processor, that the temperature of the storage measured using a temperature sensor operatively coupled with the UFS device controller exceeds a first threshold value or is less than a second threshold value which is smaller than the first threshold value, and a plurality of first events for reducing the current consumption of the UFS device controller in response to receiving a status signal from the UFS device controller indicating that the temperature of the storage exceeds the first threshold value. One or more programs including instructions that cause the electronic device to transmit a second control signal to the UFS device controller, and in response to receiving a status signal from the UFS device controller indicating that the temperature of the storage is less than the second threshold value, transmit a second control signal to the UFS device controller indicating a plurality of second events to increase the current consumption of the UFS device controller.

[0188] According to one embodiment, a universal flash storage (UFS) card comprises a UFS device controller, a UFS interface including downstream lanes for receiving data through the UFS device controller from an external device operatively coupled to the UFS card and upstream lanes for transmitting data from the UFS device controller to the external device, and a storage including a plurality of non-volatile memories and a cache memory. The UFS device controller may be configured to receive a first control signal from the external device instructing to identify whether the temperature of the storage measured using a temperature sensor operatively coupled to the UFS device controller exceeds a threshold value, transmit a status signal to the external device instructing that the temperature of the storage exceeds the threshold value, and receive a second control signal from the external device instructing to disable at least some of the plurality of downstream lanes and at least some of the plurality of upstream lanes, and to disable a cache memory configured to store 1 bit per unit cell in the storage.

[0190] As described above, according to one embodiment, a System on Chip comprises at least one processor, a storage controller controlling storage, and a UFS interface including downstream lanes and upstream lanes, and the at least one processor may be configured to transmit a first control signal to the storage controller in response to boot up of the at least one processor, to measure the temperature of the storage using a temperature sensor operatively coupled with the storage controller, and to identify that the measured temperature exceeds a threshold value, receive a status signal from the storage controller indicating that the temperature measured through the temperature sensor exceeds the threshold value, and based on the status signal, transmit a second control signal to the storage controller instructing to disable at least some of the downstream lanes and at least some of the upstream lanes, and to disable the cache memory configured to store 1 bit per unit cell of the storage.

[0192] According to one embodiment, an electronic device comprises at least one processor, a UFS host controller operatively coupled to the at least one processor, a UFS interface including downstream lanes for transmitting data from the UFS host controller to a UFS device controller and upstream lanes for transmitting data from the UFS device controller to the UFS host controller, and storage including a plurality of non-volatile memories and a cache memory, wherein the at least one processor may be configured to respond to a boot up of the at least one processor by transmitting a first control signal through the UFS host controller to the UFS device controller instructing the UFS device controller to measure the temperature of the storage using a temperature sensor operatively coupled to the storage, receive a status signal from the UFS device controller indicating that the measured temperature of the storage exceeds a threshold value, and reduce the size of data to be written to the plurality of non-volatile memories based on the status signal.

[0194] The electronic device according to the various embodiments disclosed in this document may be of various forms. The electronic device may include, for example, a portable communication device (e.g., a smartphone), a computer device, a portable multimedia device, a portable medical device, a camera, a wearable device, or a consumer electronics device. The electronic device according to the embodiments of this document is not limited to the devices described above.

[0195] The various embodiments of this document and the terms used therein are not intended to limit the technical features described in this document to specific embodiments, and should be understood to include various modifications, equivalents, or substitutions of said embodiments. In connection with the description of the drawings, similar reference numerals may be used for similar or related components. The singular form of a noun corresponding to an item may include one or more of said items unless the relevant context clearly indicates otherwise. In this document, phrases such as "A or B," "at least one of A and B," "at least one of A or B," "A, B or C," "at least one of A, B and C," and "at least one of A, B, or C" may each include any one of the items listed together in the corresponding phrase, or all possible combinations thereof. Terms such as "first," "second," or "first" or "second" may be used simply to distinguish said components from other said components and do not limit said components in any other aspect (e.g., importance or order). Where any (e.g., 1st) component is referred to as "coupled" or "connected" to another (e.g., 2nd) component, with or without the terms "functionally" or "communicationly," it means that said any component may be connected to said other component directly (e.g., via a wire), wirelessly, or through a third component.

[0196] The term “module” as used in the various embodiments of this document may include a unit implemented in hardware, software, or firmware, and may be used interchangeably with terms such as logic, logic block, component, or circuit, for example. A module may be a component formed integrally, or a minimum unit of said component or a part thereof that performs one or more functions. For example, according to one embodiment, a module may be implemented in the form of an application-specific integrated circuit (ASIC).

[0197] Various embodiments of the present document may be implemented as software (e.g., program (140)) comprising one or more instructions stored in a storage medium (e.g., internal memory (136) or external memory (138)) readable by a machine (e.g., electronic device (101)). For example, a processor (e.g., processor (120)) of the machine (e.g., electronic device (101)) may call at least one of the one or more instructions stored in the storage medium and execute it. This enables the machine to be operated to perform at least one function according to the at least one called instruction. The one or more instructions may include code generated by a compiler or code that can be executed by an interpreter. The storage medium readable by the machine may be provided in the form of a non-transitory storage medium. Here, 'non-temporary' simply means that the storage medium is a tangible device and does not contain a signal (e.g., electromagnetic waves), and the term does not distinguish between cases where data is stored semi-permanently and cases where it is stored temporarily.

[0198] According to one embodiment, the method according to the various embodiments disclosed herein may be provided as included in a computer program product. The computer program product may be traded between a seller and a buyer as a product. The computer program product may be distributed in the form of a device-readable storage medium (e.g., CD-ROM (compact disc read-only memory)), or distributed online (e.g., download or upload) through an application store (e.g., Play Store) or directly between two user devices (e.g., smartphones). In the case of online distribution, at least a portion of the computer program product may be temporarily stored or temporarily created on a device-readable storage medium, such as the memory of a manufacturer's server, an application store's server, or a relay server.

[0199] According to various embodiments, each component (e.g., module or program) of the components described above may include a singular or multiple entities, and some of the multiple entities may be separated and placed in other components. According to various embodiments, one or more of the components or operations of the aforementioned components may be omitted, or one or more other components or operations may be added. Generally or additionally, multiple components (e.g., module or program) may be integrated into a single component. In this case, the integrated component may perform one or more functions of each of the multiple components in the same or similar manner as those performed by the corresponding component among the multiple components prior to integration. According to various embodiments, operations performed by the module, program, or other components may be executed sequentially, in parallel, iteratively, or heuristically, or one or more of the operations may be executed in a different order, omitted, or one or more other operations may be added.

Claims

Claim 1 An electronic device comprises: at least one processor including a processing circuit; a universal flash storage (UFS) device including a controller and a storage medium including a non-volatile memory; a temperature sensor; and a UFS interface including downstream lanes for transmitting data from the at least one processor to the controller and upstream lanes for transmitting data from the controller to the at least one processor, wherein the at least one processor is configured to transmit a first control signal to the controller in response to a boot up of the at least one processor, for instructing the controller to identify whether the temperature of the UFS device exceeds a threshold value, and the controller receives the first control signal from the at least one processor; and based on receiving the first control signal, identifies the temperature of the UFS device through the temperature sensor; An electronic device configured to transmit a status signal to at least one processor indicating that the temperature of the UFS device exceeds the threshold value based on the temperature of the UFS device identified as exceeding the threshold value, wherein the at least one processor: receives the status signal from the controller; and, based on the status signal, transmits a second control signal to the controller through the controller that causes to disable some of the downstream lanes or some of the upstream lanes. Claim 2 An electronic device according to claim 1, wherein the at least one processor is configured to transmit to the controller a second control signal that sets the delay time for the UFS device to wait before entering sleep mode from a first time to a second time shorter than the first time, based on the status signal. Claim 3 An electronic device according to claim 1, wherein the at least one processor is configured to transmit the second control signal to the controller, which instructs the controller to stop operations running in the background of the controller based on the status signal. Claim 4 An electronic device according to claim 1, wherein the at least one processor is configured to transmit to the controller a second control signal instructing the controller to change the operating frequency of the controller from a first frequency to a second frequency lower than the first frequency based on the status signal. Claim 5 An electronic device according to claim 4, wherein the second frequency can be varied based on the size of the transmission and reception bandwidth between the controller and the at least one processor. Claim 6 The electronic device according to claim 1, wherein the electronic device further comprises a dynamic random access memory (DRAM), and the at least one processor is configured to transmit to the controller the second control signal instructing to bypass a request to read at least some of the data stored in the non-volatile memory in order to program at least some of the data stored in the DRAM into the non-volatile memory or to write at least some of the data stored in the non-volatile memory into the DRAM. Claim 7 An electronic device according to claim 1, wherein the at least one processor is configured to request the controller to transmit the status signal to the at least one processor at predetermined intervals, and, in response to identifying that the temperature of the UFS device is less than the threshold value based on the status signal, to reactivate some of the disabled downstream lanes or some of the upstream lanes, and to transmit a third control signal to the controller instructing to activate the disabled cache memory based on the second control signal. Claim 8 An electronic device comprises: at least one processor including a processing circuit; a universal flash storage (UFS) device including a controller and a storage medium including a non-volatile memory; a temperature sensor; and a UFS interface including downstream lanes for transmitting data from the at least one processor to the controller and upstream lanes for transmitting data from the controller to the at least one processor, wherein the at least one processor is configured to transmit a first control signal to the controller in response to a boot up of the at least one processor, for instructing the controller to identify whether the temperature of the UFS device is less than a threshold value, and the controller receives the first control signal from the at least one processor; and based on receiving the first control signal, identifies the temperature of the UFS device through the temperature sensor; An electronic device configured to transmit a status signal to at least one processor indicating that the temperature of the UFS device is less than the threshold value based on the temperature of the UFS device identified as being less than the threshold value, and the at least one processor configured to: receive the status signal from the controller, and based on the status signal, transmit a second control signal to the UFS device controller, through the controller, causing the deactivated lane among the downstream lanes and the upstream lanes to be activated. Claim 9 An electronic device according to claim 8, wherein the at least one processor is configured to transmit to the controller a second control signal that sets the delay time for the UFS device to wait before entering sleep mode from a first time to a second time longer than the first time, based on the status signal. Claim 10 An electronic device according to claim 8, wherein the at least one processor is configured to transmit the second control signal to the controller, which instructs the controller to execute tasks executed in the background of the controller based on the status signal. Claim 11 An electronic device according to claim 8, wherein the at least one processor is configured to transmit to the controller a second control signal instructing the controller to change the operating frequency of the controller from a first frequency to a second frequency higher than the first frequency, based on the status signal. Claim 12 An electronic device according to claim 11, wherein the second frequency can be varied based on the size of the transmission and reception bandwidth between the controller and the at least one processor. Claim 13 The electronic device according to claim 8, wherein the electronic device further comprises a dynamic random access memory (DRAM), and the at least one processor is configured to transmit to the controller the second control signal instructing to increase the size of data for programming at least a portion of the data stored in the DRAM into the non-volatile memory, or the size of data for requesting a read of at least a portion of the data stored in the non-volatile memory in order to write at least a portion of the data stored in the non-volatile memory to the DRAM. Claim 14 An electronic device according to claim 8, wherein the at least one processor requests the controller to transmit the status signal to the at least one processor at predefined intervals, and is configured to deactivate the activated lane among the downstream lanes and the upstream lanes in response to identifying that the temperature of the UFS device is below the threshold value based on the status signal. Claim 15 An electronic device comprises: at least one processor including a processing circuit; a universal flash storage (UFS) device including a controller and a storage medium including a non-volatile memory; a temperature sensor; and a UFS interface including downstream lanes for transmitting data from the at least one processor to the controller and upstream lanes for transmitting data from the controller to the at least one processor, wherein the at least one processor: transmits a first control signal to the controller in response to boot up of the at least one processor, instructing to identify whether the temperature of the UFS device exceeds a first threshold value or is less than a second threshold value which is smaller than the first threshold value; and transmits a second control signal to the controller in response to receiving a status signal from the controller indicating that the temperature of the UFS device exceeds the first threshold value, in order to cause some of the downstream lanes or some of the upstream lanes to be disabled; An electronic device configured to transmit a third control signal to the controller, which causes some of the downstream lanes or some of the upstream lanes to be activated, in response to receiving a status signal from the controller indicating that the temperature of the UFS device is less than the second threshold value. Claim 16 An electronic device according to claim 15, wherein the second control signal further comprises at least one of instructing to disable a cache memory configured to store 1 bit per unit cell of the UFS device, setting a delay time waiting before the UFS device enters sleep mode from a first time to a second time shorter than the first time, instructing to stop tasks running in the background of the controller, and changing the operating frequency of the controller from a first frequency to a second frequency lower than the first frequency. Claim 17 An electronic device according to claim 15, wherein the at least one processor: requests the controller to transmit the status signal to the at least one processor at predefined intervals; and is configured to transmit to the controller a fourth control signal instructing to reactivate some of the deactivated downstream lanes or some of the upstream lanes in response to identifying, based on the status signal, that the temperature of the UFS device is less than the first threshold value. Claim 18 An electronic device according to claim 15, wherein the third control signal further comprises at least one of instructing to activate a cache memory configured to store 1 bit per unit cell of the UFS device, setting a delay time waiting before the UFS device enters sleep mode from a first time to a second time longer than the first time, instructing to execute tasks executed in the background of the controller, and changing the operating frequency of the controller from a first frequency to a second frequency higher than the first frequency. Claim 19 An electronic device according to claim 15, wherein the at least one processor is configured to: request the controller to transmit the status signal to the at least one processor at predefined intervals; and, based on the status signal, transmit a fourth control signal to the controller instructing to deactivate some of the activated downstream lanes or some of the upstream lanes again in response to identifying that the temperature of the UFS device exceeds the second threshold value. Claim 20 In claim 15, the controller is an electronic device mounted in one package together with the UFS device.

Images