Apparatus and method for inserting synchronized data using inter-packet gap of ethernet packets

Abstract

The present invention relates to a technology for mutually exchanging asynchronous data including 1PPS signals, time information (time synchronization data), and user data between Ethernet devices or between wired and wireless devices having an Ethernet interface. More specifically, the invention relates to a device and method for inserting data synchronization using an Ethernet packet gap (IPG) that enables stable time and data synchronization between devices by synchronizing the asynchronous data and inserting it in real time into an Ethernet packet gap (IPG).

Description

Technology Field

[0001] The present invention relates to a technology for mutually exchanging asynchronous data including 1PPS signals, time information (time synchronization data), and user data between Ethernet devices or between wired and wireless devices having an Ethernet interface. More specifically, the invention relates to a device and method for inserting data synchronization using an Ethernet packet gap (IPG) that enables stable time and data synchronization between devices by synchronizing the asynchronous data and inserting it in real time into an Ethernet packet gap (IPG). Background Technology

[0002] In Ethernet systems, a widely used hardware-based method for time synchronization between devices involves connecting a GPS (Global Positioning System) receiver to each Ethernet device or wired / wireless device to receive 1 PPS (1 Pulse Per Second) signals and time information, and then synchronizing the clocks and times between Ethernet devices or between Ethernet and wired / wireless devices based on this information. Additionally, a method of maintaining time synchronization between devices by periodically inserting separate synchronization packets containing time information into the communication section where actual data transmission takes place, using software-based time synchronization protocols such as NTP (Network Time Protocol) and PTP (Precision Time Protocol), is also commonly utilized. In some methods, a technique has been proposed in which the Inter-Frame Gap (IFG), which is the interval between Ethernet frames, is reduced, the received raw Ethernet packet is decapsulated, user data corresponding to the reduced time is inserted into the Padding (PAD) area located after the MAC Client Data field, and then the packet is reconstructed and transmitted by encapsulating it again.

[0003] However, these conventional methods entail the following technical limitations.

[0004] First, GPS-based methods have a structural vulnerability in which maintaining clock and time synchronization between devices becomes impossible if GPS signal reception is blocked or becomes unstable due to external factors such as changes in the wireless environment, GPS jamming, receiver failure, and / or unstable signal strength.

[0005] Second, software-based NTP and PTP methods require periodic transmission and reception of synchronization packets, which reduces the effective bandwidth available for actual data transmission and may cause transmission delays for packets containing time-sensitive data.

[0006] Third, the method of inserting synchronization information by directly modifying the data field of Ethernet packets entails packet decapsulation and encapsulation processes, which increases memory usage and data processing time and can consequently lead to performance degradation in the form of transmission delay.

[0007] In addition, the PAD field used in this method is an area filled with '0' values ​​to satisfy the minimum transmission length of 64 bytes for an Ethernet frame when the length of MAC client data is less than 46 bytes. If arbitrary user data is inserted into this PAD field, the total length of the MAC client data may exceed the MTU (Maximum Transmission Unit) limit of 1,500 bytes; in this case, the Ethernet frame is interpreted as a higher-layer protocol, and the LENGTH / TYPE field must also be changed to the higher-layer protocol type.

[0008] The 'INSERTION' data inserted during this process is incorrectly recognized as a configuration field of the upper layer rather than the information intended by the user, which can cause communication errors. Furthermore, when attempting to transmit data to an upper layer, it is technically more feasible to utilize jumbo frames or upper-layer protocols rather than simply inserting data by shortening the IFG interval. However, this method requires protocol conversion to the upper layer within the OSI 7-layer model, and if the target device does not support the corresponding upper-layer protocol, the method itself cannot be applied. Prior art literature

[0009] (Patent Document 0001) KR 10-2005-0108932 A, 2005.11.17.(Patent Document 0002) KR 10-2006-0056275 A, 2006.05.23.US 2013 / 0051407 A1, 2013.02.28.WO 2008 / 12025 A1, 2008.10.23. The problem to be solved

[0010] Accordingly, the present invention is proposed to solve problems arising from the prior art, and aims to provide a data synchronization insertion device and method using gap intervals between Ethernet packets that resolve the limitations of the prior art that occur during time synchronization and information exchange between devices in an Ethernet system, and can secure real-time capability, efficiency, and structural stability.

[0011] First, the present invention aims to improve the overall synchronization reliability of the system by enabling the maintenance of clock and time synchronization between devices through the mutual exchange of asynchronous data, including 1PPS signals, time information (time synchronization data), and user data, between an Ethernet device and a wired / wireless device, even in situations where GPS signal reception is unstable or disconnected in a specific device due to changes in the wireless environment, GPS jamming, receiver failure, etc.

[0012] Second, unlike software-based methods such as NTP and PTP, the present invention does not periodically generate and transmit separate packets containing synchronization information; instead, it enables real-time information exchange without degradation of the transmission rate by hardware-wise synchronizing and inserting exchange data in real-time into the gap between Ethernet packets (Inter-Packet Gap, IPG), thereby effectively preventing transmission delays that may occur during software processing.

[0013] Third, the present invention operates by inserting 1PPS, time information, and user data in real time into the gap (IPG) between Ethernet packets without undergoing processes such as decapsulation, encapsulation, or modification, addition, or deletion of data fields of standard Ethernet raw packets, and thus aims to effectively resolve problems such as increased memory usage, delayed data processing time, and transmission delay caused by packet reconstruction that occurred in conventional methods. means of solving the problem

[0014] According to an embodiment of the present invention, a data synchronization insertion device utilizing a gap between Ethernet packets is provided, comprising: an IPG detection unit that detects an idle state after the termination of a received Ethernet packet and determines an IPG start point; an IPG window adjustment unit that generates IPG window candidates, which are insertable time intervals of various widths based on the IPG start point, and selects and outputs one of the IPG window candidates; an IPG synchronization unit that synchronizes user data and a reference time signal with the selected IPG window and the Ethernet clock to generate synchronized serial data; an IPG field mapping unit that aligns the serial data in byte units to form a map-field; and an IPG field insertion unit that aligns and inserts the map-field into an effective interval of the IPG window.

[0015] In addition, the IPG detection unit detects the idle state in which all bits in the received data remain '0' after the termination of the received Ethernet packet by monitoring the idle state in nibble units, determines the time when the idle state is first detected as the IPG start point, generates an IPG window detection signal based on the IPG start point, and can output the generated IPG window edge signal as a reference timing signal by detecting the rising edge of the IPG window detection signal.

[0016] In addition, the IPG window control unit receives a reference timing signal output from the IPG detection unit as a trigger input, generates a plurality of timing signals delayed relative to the reference timing signal using a multi-stage D-flip-flop chain, generates a plurality of IPG window candidates with different widths based on the plurality of delayed timing signals, and then selects and outputs an IPG window suitable for inserting actual user data among the generated IPG window candidates.

[0017] In addition, the IPG synchronization unit can synchronize the user data input from the outside and the reference time signal with the Ethernet clock based on the buffered IPG window detection signal provided from the IPG detection unit and the IPG window selected by the IPG window adjustment unit to align them in a parallel form, and output a synchronized serial data stream converted into a serial bit sequence that can be inserted into an Ethernet packet.

[0018] In addition, the IPG field mapping unit can align the synchronized serial data stream output from the IPG synchronization unit in predetermined byte units to form one or more map fields, and can process the map fields into a form that can be inserted into the blank interval between Ethernet packets by including a distinguishing bit pattern for identifying the user data and reference time signal in the map fields.

[0019] In addition, the IPG field insertion unit receives an IPG window detection signal provided by the IPG detection unit and a map-field provided by the IPG field mapping unit, aligns and inserts the map-field into the valid interval of the IPG window selected by the IPG window adjustment unit, and thereby transmits information including the user data and reference time signal into the blank interval between Ethernet packets.

[0020] Additionally, the IPG detection unit includes a nibble detector that detects an idle state in which all bits remain '0' by monitoring nibble unit input of the received data after the termination of the received Ethernet packet; and an edge detector that detects a change in the output of the nibble detector. The nibble detector detects the point in time when the received data becomes '0' to determine the IPG start point and generates an IPG window detection signal based on the IPG start point. The edge detector detects the rising edge of the IPG window detection signal and outputs an IPG window edge signal for generating an IPG window as a reference timing signal.

[0021] Additionally, the IPG window control unit may include: a trigger input unit that receives the IPG window edge signal provided from the edge detector as a reference timing signal and generates a plurality of delayed timing signals together with the Ethernet clock; a window generation unit that combines the plurality of delayed timing signals to generate a plurality of IPG window candidates having different widths; and a window selection unit that selects one of the IPG window candidates and outputs it as the final IPG window.

[0022] Additionally, the IPG synchronization unit may include: a plurality of D-flip-flops that align the user data and reference time signals in a parallel form; a clock selector that selects a clock serving as an operation reference for the D-flip-flops and provides it to the plurality of D-flip-flops; an AND gate that controls the output timing of the parallel data aligned through the D-flip-flops by using the IPG window signal selected by the IPG window control unit as an enable signal; a serial mapper that configures the data aligned through the D-flip-flops into a predefined map-field format; and a shift register that converts the map-field into a serial bit sequence and outputs a synchronized serial data stream.

[0023] Additionally, the IPG field mapping unit includes a plurality of D-flip-flops that receive a synchronized serial data stream output from the IPG synchronization unit by synchronizing it with the Ethernet clock and the IPG window signal, and the D-flip-flops of the IPG field mapping unit use the Ethernet clock as a clock input and the IPG window signal as an enable signal to sequentially store the synchronized serial data stream only in the corresponding valid timing interval, reconstruct the sequentially stored bits into 8-bit byte fields based on the bits, and the reconstructed byte fields can form a map-field including the user data and the reference time signal.

[0024] Additionally, the IPG field insertion unit includes a plurality of D-flip-flops that receive a map-field provided by the IPG field mapping unit and process it in synchronization with the Ethernet clock and the buffered IPG window signal. The D-flip-flops of the IPG field insertion unit use the Ethernet clock as a clock input and the buffered IPG window signal as an enable signal to sequentially store the map-field only in the corresponding valid timing interval to generate a gated field. The gated field is output in response to the valid insertion timing through an AND logic operation with the buffered IPG window detection signal provided by the IPG detection unit. The gated field output in response to the valid insertion timing is inserted into the blank interval between Ethernet packets, and the inserted gated field can be merged with the existing Ethernet packet through an OR circuit to be output as a new Ethernet packet containing a new IPG that includes synchronization information.

[0025] In addition, according to an embodiment of the present invention, a data synchronization insertion method using a data synchronization insertion device utilizing a gap between Ethernet packets is provided, comprising: (a) a step of determining an IPG start point by detecting an idle state after the termination of a received Ethernet packet; (b) a step of generating IPG window candidates, which are insertable time intervals of various widths based on the IPG start point, and selecting and outputting one of the IPG window candidates; (c) a step of generating synchronized serial data by synchronizing user data and a reference time signal with the selected IPG window and the Ethernet clock; (d) a step of configuring a map-field by aligning the serial data in byte units; and (e) a step of aligning and inserting the map-field into the valid interval of the IPG window.

[0026] In addition, the above process (a) can detect the idle state in nibble units by monitoring the idle state in which all bits in the received data remain '0' after the termination of the received Ethernet packet, determine the time when the idle state is first detected as the IPG start point, generate an IPG window detection signal based on the IPG start point, and detect the rising edge of the IPG window detection signal to output the generated IPG window edge signal as a reference timing signal.

[0027] Additionally, the above process (b) can receive the reference timing signal as a trigger input, generate a plurality of timing signals delayed relative to the reference timing signal, generate a plurality of IPG window candidates with different widths based on the plurality of delayed timing signals, and then select and output an IPG window suitable for inserting actual user data from among the generated IPG window candidates.

[0028] Additionally, the above process (c) can synchronize the user data and reference time signals with the Ethernet clock based on the buffered IPG window detection signal and the selected IPG window to align them in parallel, and output a synchronized serial data stream converted into a serial bit sequence that can be inserted into an Ethernet packet.

[0029] In addition, the above process (d) can align the synchronized serial data stream in predetermined byte units to form one or more map fields, and include a distinguishing bit pattern for identifying the user data and reference time signal in the map field, thereby processing the map field into a form that can be inserted into the blank interval between Ethernet packets.

[0030] In addition, the above process (e) receives the IPG window detection signal and the map-field, aligns and inserts the map-field into the valid interval of the selected IPG window, and thereby enables real-time transmission of information including the user data and reference time signal into the blank interval between Ethernet packets. Effects of the invention

[0031] According to an embodiment of the present invention, a hardware-based technology is provided that enables real-time synchronization and insertion of asynchronous data, including a 1 PPS reference time signal, time information, and user data, into an Ethernet packet gap (IPG) between wired and wireless devices using a standard Ethernet packet (frame) interface, without decapsulating or encapsulating the raw packet, or changing, adding, or deleting data fields. This allows for high-precision time synchronization and real-time data insertion while maintaining the structure of the MAC frame during data transmission between devices, thereby improving the overall data transmission rate of the system and realizing reliable bidirectional information exchange without transmission delay. Accordingly, according to an embodiment of the present invention, by utilizing an FPGA-based hardware structure, a standard Ethernet PHY interface, and PCIe, a high-speed serial connection method, it can be effectively applied to environments requiring real-time performance and precision in Ethernet-based communication devices in various application fields, such as defense and civilian sectors. Brief explanation of the drawing

[0032] FIG. 1 is a diagram showing the configuration of a data synchronization insertion device according to an embodiment of the present invention. FIG. 2 is a diagram showing the configuration of the IPG detector shown in FIG. 1. FIG. 3 is a diagram showing the configuration of the IPG window control unit shown in FIG. 1. FIG. 4 is a diagram showing the configuration of the IPG synchronization unit shown in FIG. 1. FIG. 5 is a diagram showing the configuration of the IPG field mapping unit shown in FIG. 1. FIG. 6 is a diagram showing the configuration of the IPG field insertion part shown in FIG. 1. FIG. 7 is a diagram showing an Ethernet packet structure in which user data is inserted through a data synchronization insertion device according to an embodiment of the present invention. FIG. 8 is a diagram showing the configuration of an Ethernet-based synchronization transmission system according to an embodiment of the present invention. FIG. 9 is a diagram illustrating a data synchronization insertion method according to an embodiment of the present invention. Specific details for implementing the invention

[0033] Hereinafter, embodiments of the present invention will be described in detail with reference to the attached drawings. However, the present invention is not limited to the embodiments disclosed below but may be implemented in various different forms, and the embodiments of the present invention are provided merely to ensure that the disclosure of the present invention is complete and to fully inform those skilled in the art of the scope of the invention. In the drawings, like reference numerals refer to like elements.

[0034] FIG. 1 is a schematic diagram showing the configuration of a data synchronization insertion device according to an embodiment of the present invention.

[0035] Referring to FIG. 1, a data synchronization insertion device (10) according to an embodiment of the present invention includes five data processing units that receive and process Ethernet packets. The five data processing units include a gap section between Ethernet packets (hereinafter referred to as 'IPG') detection unit (11), an IPG window adjustment unit (12), an IPG synchronization unit (13), an IPG field mapping unit (14), and an IPG field insertion unit (15).

[0036] The IPG detection unit (11) is a core module that accurately detects the gap between Ethernet packets, i.e., the IPG, and prepares the corresponding section to be used as a window for data insertion.

[0037] Figure 2 is a schematic diagram showing the configuration of the IPG detection unit shown in Figure 1.

[0038] Referring to FIGS. 1 and 2, an IPG detection unit (11) according to an example of the present invention analyzes the flow of a received Ethernet packet (Ethernet Packet, 1) to detect the start bit time and valid time interval of the IPG in real time, and uses this to generate an IPG window that can reliably insert synchronization information and user data. Here, the term 'valid time interval' refers to a time range among the IPGs existing between Ethernet packets that is allowed for the system to actually insert synchronization information or user data.

[0039] As shown in FIG. 2, the IPG detection unit (11) operates centered on a bit time searcher (111), which includes a nibble detector (112) and an edge detector (113), and the operation characteristics (IPG detection method) are as follows.

[0040] First, the IPG start point (Start Bit Time) is detected based on the idle pattern that appears in the Ethernet packet reception path after the end of the received Ethernet packet (1). After the Ethernet packet transmission is completed, an idle state occurs in the Ethernet packet reception path where all bits remain '0' for a certain period of time, and this idle state is considered as a physical signal condition indicating the start of the IPG section. At this time, the nibble detector (112) continuously monitors the 4-bit parallel received data signal (RXD[3:0]) input through the Ethernet reception path and detects in real time the section where all bits of the data remain '0'. To detect an idle state, as shown in FIG. 2, the nibble detector (112) connects each bit of RXD[3:0] (receive data bus that transmits Ethernet packet (1) data) to the inverter (114), and then inputs the inverted output value to an AND operator (AND) to output a nibble detection signal (NIBBLE_DETECTION) only when all 4 bits are '0'. The nibble detection signal (NIBBLE_DETECTION) output at this time considers the point in time when the corresponding idle state is detected as the IPG start point. Subsequently, the IPG start point is used as a reference timing for creating an IPG window. In addition, the input RXD[3:0] signal is sequentially sampled through a 2-stage D-flip-flop (DFF) structure. This is intended to prevent false detection caused by disturbances (noise) or momentary signal anomalies through clock synchronization, and to increase signal stability and detection reliability. That is, through a dual sampling structure leading from RXD1 to RXD2, signal changes or transient states under critical conditions are filtered out, and detection is performed based only on the filtered stable idle state.This nibble-based IPG start point detection structure can operate in real-time at the hardware level and offers technical advantages such as faster and more stable time information synchronization and data insertion timing compared to conventional software-based packet interpretation methods.

[0041] Next, an IPG window is generated (detected). In the process of generating the IPG window, a section of N bit time of a pre-set length is defined as the IPG window based on the previously detected IPG start point. Here, 'N ​​bit time' is a unit of time defined according to the system Ethernet clock speed (e.g., approximately 8ns / bit based on 125MHz) and is precisely counted by a hardware timing control circuit. The generated IPG window is used as an IPG window signal (Detected-IPG WINDOW) (hereinafter referred to as 'IPG window detection signal') and serves as an effective section where actual data insertion is possible. As shown in FIG. 2, this section is output in a 'high' state of the signal waveform and provides reference timing information for synchronization with subsequent insertion modules. At this time, an edge detector (EDGE DETECTOR, 113) detects the rising and falling edges of the IPG window detection signal (Detected-IPG WINDOW) to generate an IPG window edge signal (WINDOW EDGE). This serves as a criterion for clearly distinguishing the start and end of a reference timing pulse and is essential information for precisely specifying the data insertion time and end time. The edge detector (113) may include a circuit based on an XOR operation of the previous state and the current state or a digital Schmitt trigger to detect the rising and falling edges of the IPG window detection signal (Detected-IPG WINDOW), respectively.

[0042] Next, the timing is adjusted. The IPG window detection signal (Detected-IPG WINDOW) is temporarily stored through a bit buffer, and the timing can be fine-tuned to correct synchronization errors or latency with the system's Ethernet clock. This timing adjustment is essential for the subsequent IPG synchronization unit (13) and IPG field insertion unit (15) to accurately determine the timing at which data will actually be inserted. Additionally, by providing the IPG window edge signal (IPG WINDOW EDGE) in parallel, the insertion start and end points can also be clearly distinguished.

[0043] Figure 3 is a schematic diagram showing the configuration of the IPG window control unit shown in Figure 1.

[0044] Referring to FIG. 3, the IPG window control unit (12) generates and selects an IPG window of an appropriate size based on the number of bits of user data, based on the IPG window edge signal (IPG WINDOW EDGE) received from the IPG detection unit (11), and outputs it. This IPG window control unit (12) may include a link detection unit (121), a phase synchronization circuit unit (122), a clock selection unit (123), a trigger input unit (124), a window generation unit (125), a window selection unit (126), and an up / down control unit (127).

[0045] The link detection unit (121) detects the physical connection status and link speed information between network devices in real time and provides reference information necessary for subsequent clock selection. This link detection unit (121) receives a link status signal input from the Ethernet PHY layer, determines the link speed at which the network is currently operating (e.g., 10 Mbps, 100 Mbps, 1000 Mbps), and converts the information into a digital signal that can be processed by an internal control circuit. Additionally, the link detection unit (121) receives an external reference clock (e.g., 25 MHz) and the PHY link status signal as inputs and transmits a control signal to the clock selection unit (123) so that an appropriate clock can be selected according to the detected link speed. This process serves as the basis for selecting a frequency optimized for system operation from among the clocks generated through the phase synchronization circuit unit (122). The link detection unit (121) can be designed to be structured to respond dynamically to changes in the network environment through interaction with an external PHY, and this link detection function plays a key role in automatically adjusting the clock setting and IPG window timing control path of the entire system.

[0046] The phase synchronization circuit (122) generates a multi-frequency clock suitable for the system by processing a reference clock input from the outside (e.g., 25 MHz) using a high-precision phase-locked loop (PLL) method based on reference information received from the link detection unit (121). For example, a 125 MHz clock is output when high-speed operation is required, and a 25 MHz basic clock is output in low-speed mode. The multi-frequency clock output from the PLL unit (122) is transmitted to the clock selection unit (123), and an appropriate operation clock is selected according to the Ethernet link environment. The generated clock subsequently becomes an important element that serves as the time reference for the entire IPG window adjustment unit (12).

[0047] The clock selection unit (123) automatically selects a clock of an appropriate frequency based on reference information (link speed information) transmitted from the link detection unit (121). For example, if the network is connected at 1000 Mbps, a 125 MHz high-speed clock is selected, and if it operates at 100 Mbps or less, a 25 MHz basic clock is selected and supplied. The clock selected in this way is subsequently used as a reference clock supplied to the entire synchronization insertion timing structure, such as the trigger input unit (124), window creation unit (125), and window selection unit (126), within the IPG window adjustment unit (12).

[0048] The trigger input unit (124) generates multi-stage time delay timing signals based on the IPG window edge signal transmitted from the IPG detection unit (11). The trigger input unit (124) consists of N D-flip-flops (DFF) serially connected in a daisy chain manner. Each D-flip-flop is synchronized with the same reference clock and sequentially outputs precise delay timing based on the timing of the input signal. This trigger input unit (124) uses the Ethernet operation clock (e.g., 25 MHz or 125 MHz) determined by the clock selection unit (123) as the reference clock to maintain precise time resolution of the entire delay circuit. When the input signal, the IPG window edge signal, is applied to the first flip-flop of the D-flip-flop chain in the form of a rising edge, the reference timing T0 is set. Subsequently, the outputs of each stage, T1, T2, ..., T N(Here, N is a natural number) are signals delayed in units of Ethernet clock cycles and are used as timing standards for configuring windows of various lengths in the IPG window generation unit (125). These trigger input units (124) operate based on a precise reference clock input through the PLL unit (122) and the clock selection unit (123). Accordingly, timing consistency and stability of the data insertion time can be simultaneously guaranteed within the system even under disturbance conditions such as changes in network link speed or external electrical noise.

[0049] The window generation unit (125) receives delay signals (T0~T for each step) from the trigger input unit (124). N IPG window candidate signals (W1~W) having various time widths based on ) N It generates ). This window generation unit (125) can be implemented based on an OR operation logic network and generates a variable-length time interval by combining sequentially delayed signals. First, T0, T1, ..., T output from the D-flip-flop chain of the trigger input unit (124) N These are signals that are each time-delayed by a clock cycle, and the relative timing difference between them represents the minimum unit of the time interval where IPG can be inserted. These signals are input to the window generation unit (125) and are sequentially accumulated through OR logic gates. This method is implemented as a time-accumulated OR chaining method to create a window area that gradually expands based on T0. As a result, the generated W1~W N Each of these functions as a candidate window with a different time width, serving as a valid time interval (candidate IPG windows) into which user data of various lengths can be inserted.

[0050] The window selection unit (126) is a plurality of window candidate signals (W1~W) output from the window creation unit (125). N It receives ) as input and selects one of them in real time to produce the final output. This window selection unit (126) includes a multiplexer (MUX), and the multiplexer (MUX) uses a window selection signal (Window SEL), which is a control signal from the up / down control unit (127), to select multiple window candidate signals (W1~W N Select and output one of the ). Each window candidate (W1~W N ) represents time intervals of different lengths generated previously through the trigger input unit (124) and the window generation unit (125), each representing an effective IPG insertion interval containing a certain number of Ethernet clock cycles. Among these various window widths, the timing interval most suitable for the bit length of the actual user data and the insertion conditions is selected according to the window selection signal (Window SEL). The window selection signal (Window SEL) is dynamically calculated by the up / down control unit (127) according to the real-time system situation, that is, the number of bits of user data to be inserted or the payload size of the synchronization information, and the window selection unit (126) selects the correct timing signal among multiple inputs based on this. The window selected by the window selection unit (126) is output under the name 'Controlled-IPG WINDOW' (hereinafter referred to as 'IPG window selection signal'), which is then transmitted to the subsequent IPG synchronization unit (13) and / or IPG field insertion unit (15) to allow user data or time synchronization information to be inserted into the IPG at the correct timing.

[0051] The core function of the window selection unit (126) is to select window candidates of various lengths (W1~W NThe purpose is to coordinate timing so that data can be inserted without difficulty within the IPG interval by accurately and quickly selecting one of them. Based on a multiplexer (MUX), it implements stable selection operation in hardware and operates in precise synchronization with clock-based system operation. It is dynamically driven by a window selection signal (Window SEL) to respond flexibly according to the external environment (link speed) and internal data state (insertion amount).

[0052] Meanwhile, a glitch removal circuit (128) may be additionally configured between the window generation unit (125) and the window selection unit (126). During the process of accumulating multiple delay signals using an OR operation between the window generation unit (125) and the window selection unit (126), instantaneous unnecessary pulses, i.e., glitches, may occur. This glitch phenomenon means that some of the IPG window candidate signals (W1~WN) are unintentionally activated in a short interval, which may cause malfunctions or timing discrepancies during the subsequent data insertion process. To prevent this, the added glitch removal circuit (128) operates in a structure that allows only signals of a certain length or longer to pass through the generated window candidate signals (W1~WN) after undergoing clock-based sampling and pulse width verification processes. Specifically, the input window candidate signals are latched to the reference clock to remove glitch pulses, and then only the stabilized signals are transmitted to the window selection unit (126). This ensures the timing accuracy of IPG window candidates and improves the reliability of system operation.

[0053] Additionally, the final IPG window signal selected by the window selection unit (126) is output as an IPG window selection signal according to the window selection signal (Window SEL) determined in real time by the up / down control unit (127). However, during the selection operation based on the multiplexer (MUX), there may be cases where the final output is not accurately aligned with the reference clock due to internal propagation delay or clock boundary issues. To resolve this, a precision synchronization circuit unit (129) may be additionally configured. The precision synchronization circuit unit (129) realigns the selected IPG window selection signal to the reference clock supplied by the PLL unit (122) and the clock selection unit (123). For example, the output signal is passed through a clock synchronization flip-flop chain one more time to be precisely aligned with the clock boundary, thereby ensuring that no timing error occurs when it is subsequently transmitted to the IPG synchronization unit (13) and the IPG field insertion unit (15). As a result, the precision synchronization circuit (129) stabilizes the timing of the IPG window and ensures that user data or synchronization information can always be inserted in a state that is exactly aligned with the reference clock.

[0054] Figure 4 is a schematic diagram showing the configuration of the IPG synchronization unit shown in Figure 1.

[0055] Referring to FIG. 4, the IPG synchronization unit (13) synchronizes the 1PPS signal and user data with the Ethernet clock based on the buffered-detected IPG window signal transmitted from the IPG detection unit (1), and performs bit serialization to generate a final output suitable for real-time data insertion through a serial process, namely a serial mapper and a shift register, thereby outputting a synchronized serial data stream (Bit-Shifted).

[0056] The operation characteristics (IPG synchronization method) of the IPG synchronization unit (13) are explained.

[0057] The IPG window signal and the clock signal are synchronized. The buffered-detected IPG window signal output from the IPG detection unit (11) is stabilized through a buffer, and the stabilized signal, the IPG window signal, is input to the enable input terminal of each D-flip-flop (131) within the IPG synchronization unit (13) to control subsequent data so that it is processed only within that interval. The stabilized IPG window signal indicates the time interval during which data can be inserted and is synchronized with the Ethernet clock to be used as a timing reference signal that accurately defines the insertion time of user data.

[0058] User data and a 1PPS signal (1PPS Pulse) are processed by being precisely synchronized with the Ethernet clock within the system. User data is input in the form of, for example, 16-bit parallel data (DATA[15:0]) and is applied to each independent D-flip-flop (131) circuit along with the 1PPS signal. A clock selector (132) is a circuit that performs selection control between input signals; an externally provided 1PPS signal is connected to the select signal input terminal (SEL), and the Ethernet clock serving as the system's reference is input to the clock signal input terminal (CLK). The clock selector (132) operates according to the state of the input 1PPS signal. For example, if the 1PPS signal is 'Low (GND)', the clock selector (132) selects the Ethernet clock as the output and transmits it to the downstream end. Conversely, if the 1PPS signal is 'High', it outputs a fixed 'High' state (VCC).

[0059] The output signal of the clock selector (132) is used as the clock (or trigger) signal of the D-flip-flop (131) and serves as the timing reference for the user data and 1PPS signal. An IPG window signal is input to the enable input terminal (Enable) of each D-flip-flop (131). The D-flip-flop (131) generates an output only when the clock signal output from the clock selector (132) is input to the clock signal input terminal (CLK) and the IPG window signal (IPG WINDOW), which is the enable signal of the D-flip-flop (131), is in a High state. That is, the user data and 1PPS signal are output as gated signals (Gated-1PPS, Gated-DATA[15:0]) through the D-flip-flop (131) only within the IPG valid interval where these two conditions are simultaneously satisfied. The gated field signal output in this way is then logically operated with the IPG window signal (IPG WINDOW) through the AND gate (133) to output a synchronized signal (Synced-1PPS, Synced-DATA[15:0]).

[0060] User data can be flexibly configured according to the system's operational purpose and application environment, and can be an expandable data field capable of including various forms of signals. For example, a 1PPS signal is used as a reference pulse based on a GPS receiver or a high-precision oscillator (OCXO), and can be utilized as a reference time in systems requiring precise time synchronization. Additionally, segmented time information is configured by dividing PPS-based precise time data into fixed time slots, and can be used for time alignment on a network or real-time reference signal distribution. A Pseudo-Random Binary Sequence (PRBS) is utilized as a test sequence to evaluate transmission quality in wired and wireless environments, and can serve as data for the system to measure the Bit Error Rate (BER) or analyze channel conditions. Furthermore, user data may take the form of serial communication data containing control and configuration commands; in this case, it is configured in the form of simple serial commands or control codes between devices. Additionally, user data may include bit-level information used for distinguishing roles with counterpart devices, authentication processes, and equipment identification. For example, authentication keys, device IDs, module status bits, etc., can all be transmitted as single-bit or low-bit information of a signal nature. As such, user data can be configured not only by a single transmission method but also by a segmented transmission method in which data is divided into segments and transmitted sequentially at regular intervals.

[0061] The signal synchronized with the IPG window (Synced-1PPS, Synced-DATA[15:0]) is passed to the subsequent stage, the Serial Mapper (134). The Serial Mapper (134) performs the role of reconstructing the input parallel data into a transmission format suitable for inserting into an Ethernet frame, and the entire data includes, for example, a Reserved field (7 bits) (set to a fixed value of '0'), Synced-1PPS (1 bit) (a single bit representing reference time information), Synced-DATA[15:0] (user data field), and a lower Reserved field (8 bits) (set to a fixed value of '0'). This parallel data, consisting of a total of 32 bits, is then passed to the Shift Register (135). The Shift Register (135) sequentially shifts this parallel data one bit at a time based on the system's Ethernet clock and outputs it, thereby finally generating a synchronized serial data stream (Bit_Shifted[0]), which is a bit-unit serial signal. The synchronized serial data stream (Bit_Shifted[0]) generated in this way is transmitted to the destination device via the Ethernet channel aligned within the valid interval of the IPG window, and this is processed using a real-time insertion method. This structure ensures that the synchronized data is accurately inserted within the IPG.

[0062] Figure 5 is a schematic diagram showing the configuration of the IPG field mapping unit shown in Figure 1.

[0063] Referring to FIG. 5, the IPG field mapping unit (14) receives a synchronized serial data stream (Bit_Shifted[0]) output from the IPG synchronization unit (13) and includes a bit stream that encodes user data serially. This bit stream is sequentially input to a series of D-flip-flops that operate in sync with the Ethernet transmission clock. The circuit is configured in a daisy-chain structure. The output of the first DFF[0] is passed as the input to the next stage, DFF[1], and such a connection is continuously maintained up to the final DFF

[31] . This structure effectively physically implements the function of a shift register and performs sequential bit shift operations.

[0064] The output of each D-flip-flop (DFF) is shifted in real time according to the Ethernet clock, and the corresponding output value is mapped to a designated position according to the insertion timing within the IPG interval. This mapping is performed based on a predefined byte-unit field structure. For example, the output bits of the D-flip-flop correspond to a byte field. The outputs of DFF[0] through DFF[7] are inserted into the BYTE1[0] field, the outputs of DFF[8] through DFF

[15] are inserted into the BYTE2[7] field, the outputs of DFF

[16] through DFF

[23] are inserted into the BYTE3[7] field, and the outputs of DFF

[24] through DFF

[31] are mapped to the BYTE4[7] field. The byte fields configured in this way are logically separated into lower_DATA[7:0] and upper_DATA[15:8], and are finally inserted in real time within the IPG window detection signal (Detected-IPG WINDOW) interval. This structure ensures that user data is accurately inserted into the IPG without collisions by precisely specifying the insertion position of each bit in alignment with the timing of the IPG interval. As a result, the entire system can achieve stable real-time data communication without distortion of data timing.

[0065] This mapping operation operates in synchronization with the system's Ethernet clock and the IPG window signal. The Ethernet transmit clock serves as the reference for the entire D-flip-flop (DFF) shift operation, and the IPG window signal defines the valid time interval of the IPG window detection signal (Detected-IPG WINDOW) during which data insertion is permitted, while simultaneously aligning the data to match the insertion conditions of the IPG window selection signal (Controlled-IPG WINDOW). In other words, the data is not simply shifted, but is precisely controlled to be inserted into the corresponding field only at a specified timing, synchronized with the IPG interval.

[0066] Figure 6 is a schematic diagram showing the configuration of the IPG field insertion part shown in Figure 1.

[0067] Referring to FIG. 6, the IPG field insertion unit (15) performs the function of inserting data into the actual IPG based on the serial bit sequence, i.e., the mapped field, output from the series of D-flip-flops (DFF[0]~DFF

[31] ) of the IPG field mapping unit (14). That is, the mapped field is the result of sequentially shifting the serial output signal 'Bit_Shifted[0]' generated by the IPG synchronization unit (13) through a plurality of D-flip-flops (DFF[0]~DFF

[31] ), and the data is provided in a real-time aligned state. This IPG field insertion unit (15) performs logical calculations based on the IPG window detection signal (Detected-IPG WINDOW) detected by the IPG detection unit (11) and the mapped field output from the IPG field mapping unit (14) to finally output a synchronized Ethernet packet (Synced-Packet). For example, by performing a logical AND operation between each bit of the Mapped-field and the Detected-IPG WINDOW signal, data can be controlled to be inserted only into valid time slots within the IPG interval. Through this method, user data can be transmitted in real time with the data aligned within the standard IPG interval (96-bit time) without exceeding the Ethernet transmission structure.

[0068] FIG. 7 is a schematic diagram showing the structure of an Ethernet packet in which user data is inserted in real time, as a result generated through a data synchronization insertion device according to an embodiment of the present invention.

[0069] The Ethernet packet with user data inserted shown in Fig. 7 is a visual representation of the final output result corresponding to the synchronized packet signal (Synced-Packet) among the outputs of the IPG field insertion unit (15) shown in Fig. 6, in which user data that is precisely synchronized is inserted into the IPG section.

[0070] Ethernet packets with user data inserted have a sequence such as "IPG→PREAMBLE→SFD→DA→SA→LENGTH / TYPE→CLIENT DATA→FCS→IPG→PREAMBLE→SFD" based on packet flow. There is a fixed IPG interval (96-bit time) between packets. The system detects and synchronizes this IPG interval to enable data insertion, and real-time data is inserted through the IPG field insertion section (15). The user data inserted within the IPG interval is 32 bits and includes 1PPS (1 bit) (reference time information), LOWER_DATA[7:0](8 bits) (lower byte of user data), UPPER_DATA[15:8](8 bits) (upper byte of user data), and Reserved / Padding (remaining bit) (0 value for insertion timing alignment). This has the form in which the Bit_Shifted[0] serial bit generated in the IPG synchronization unit (13) is shifted and stored as 32 bits through a D-flip-flop (DFF) series in the IPG field mapping unit (14), and inserted into an actual transmittable timing slot through a logical AND operation with the IPG window in the IPG field insertion unit (15).

[0071] FIG. 8 is a schematic diagram showing the configuration of an Ethernet-based synchronous transmission system according to an embodiment of the present invention.

[0072] Referring to FIG. 8, an Ethernet-based synchronous transmission system (100) according to an embodiment of the present invention includes a data synchronous insertion device (10) implemented based on a Field-Programmable Gate Array (FPGA). This data synchronous insertion device (10) performs the function of inserting user data in real time by utilizing the IPG interval between Ethernet packets, identical to the configuration shown in FIGS. 1 to 7. The data synchronous insertion device (10) receives and processes user data 1, user data 2, and a reference time signal 1PPS input from the outside. The input signals are converted into an insertable serial bit sequence, i.e., a map-field, and this map-field is aligned and inserted into the IPG interval, which is the idle time between Ethernet packets. This inserted data is transmitted through a PHY (Physical Layer) block mounted inside the FPGA.

[0073] In the Ethernet-based synchronous transmission system (100), there are two main transmission and reception paths. Among these, the P1-TX / RX path is responsible for interoperability with a PCIe-based upper control device or an Ethernet device (e.g., a server, a router, etc.), and the P2-TX / RX path is connected to an actual wired or wireless transmission device to perform real-time data transmission. Additionally, the data synchronization insertion device (10) can detect an IPG section existing in the Ethernet frame flow in real time and generate an IPG window signal based on that section to precisely control the timing of user data insertion. This enables stable insertion of user data without changing the structure of the existing MAC frame. High-speed interoperability with the upper host system can be achieved through a high-speed serial interface called PCIe (Peripheral Component Interconnect Express). The data synchronization insertion device (10) can process control commands, setting parameters, status information, etc., in real time through this interface. Along with this, the P2 port is connected to an Ethernet device (wired or wireless transmission device) to perform bidirectional communication based on Ethernet, allowing for flexible response to various network environments.

[0074] The operation flow of the Ethernet-based synchronous transmission system (100) is as follows. When user data and a 1PPS signal are input to the data synchronization insertion device (10), these signals are converted into serial bit sequences and prepared as insertion data. Subsequently, when an IPG section is detected in the flow between Ethernet frames, an IPG window is created based on this, and user data is inserted within that section at the correct timing. The inserted data is contained within the standard IPG length (96-bit time) and is stably transmitted to the other side without collision or frame damage during transmission. The frame transmitted in this way is sent to the other device via the P2-TX path, and the receiving side detects the inserted IPG area based on the same structure and can accurately receive user data by restoring the map-field in that section. Since the synchronization devices on both sides are configured with the same structure, bidirectional time synchronization and user data exchange based on the 1PPS reference signal are possible, and it can be applied to various applications such as high-precision time distribution, real-time status reporting, and distributed control communication. As a result, the Ethernet-based synchronization transmission system (100) of the present invention can function as a highly reliable, high-precision synchronization data transmission system capable of inserting and transmitting user data in real time without affecting MAC frames while maintaining the physical structure of the existing Ethernet protocol.

[0075] FIG. 9 is a schematic diagram illustrating a data synchronization insertion method according to an embodiment of the present invention.

[0076] Referring to FIGS. 1, 8, and 9, when an Ethernet-based synchronous transmission system (100) receives an Ethernet packet transmitted from the outside, it receives it through a PHY block located inside (or outside) the FPGA. The PHY block is a circuit corresponding to the Ethernet physical layer and restores the received analog or electrical signal into a digital Ethernet signal (RX data). The restored digital signal is a pure data stream with encoding (e.g., 8b / 10b, 64b / 66b) decoded according to the Ethernet standard, and is transmitted to the FPGA logic area through the RX data bus (RXD[3:0] or RXD[7:0]) inside the FPGA. At this time, the IPG detection unit (11) is a module implemented inside the FPGA and directly receives and processes the received data (RX data) transmitted in digital form from the PHY block as input. That is, the IPG detection unit (11) monitors the idle state that appears after the termination of the Ethernet packet inside the FPGA, and if the period lasts for a certain period of time, determines it as the starting point of the IPG and sets it as the reference timing for creating an IPG window where data can be inserted.

[0077] Next, an IPG is detected (S2). The IPG detection unit (11) monitors the received data (RXD[3:0]) received from the PHY block in real time and detects the start time of the IPG section based on the idle state that appears immediately after the transmission of the Ethernet packet is completed, that is, the period in which all bits remain '0' (S2). This process is performed through a bit time searcher (111) inside the IPG detection unit (11), as shown in FIG. 2, and the bit type searcher (111) is composed of a nibble detector (112) and an edge detector (113). The nibble detector (112) continuously monitors the 4-bit received data bus (RXD[3:0]) and detects the point in time when all input bits simultaneously become '0'. To do this, each RXD bit is inverted by an inverter, and then a nibble detection signal (NIBBLE_DETECTION) is output only when all bits are '0' through a logical AND operation. The '0000' state detected in this manner signifies the start of an idle section on the physical layer, and based on this, the starting point of the IPG section is determined as the IPG starting point. Subsequently, the IPG detection unit (11) outputs an IPG window detection signal (Detected-IPG WINDOW), which is a timing signal that serves as a criterion for creating an IPG window, based on the IPG starting point, and this signal is subsequently used as a synchronization signal for the data insertion window.

[0078] Next, the IPG window is adjusted (S3). When an idle state is detected through the IPG detection unit (11) and the starting point of the IPG interval is set, the IPG window adjustment unit (12) generates a time interval in which actual data can be inserted based on this IPG starting point. As shown in FIG. 3, the trigger input unit (124) of the IPG window adjustment unit (12) divides the time flow from the IPG starting point into clock cycle units using a multi-stage D-flip-flop (DFF) chain and delay signals (T0~T NThese signals are converted into ). These signals are precisely time-resolved based on a reference clock (e.g., 125 MHz or 25 MHz) selected according to the network link speed, and subsequently serve as the basis for generating time intervals. The window generation unit (125) converts these delay signals (T0~T N By logically combining ) to obtain multiple IPG window candidates (W1~W) with different time widths N It generates a window. This configuration is implemented as a sequential network based on OR operations, and is accumulated such that, for example, the combination of T0 to T7 generates an 8-bit window, and the combination of T0 to T15 generates a 16-bit window. The window selection unit (126) selects a window candidate in real time from among the previously generated IPG window candidates that has a time width suitable for the number of bits of user data to be inserted or the insertion conditions. This selection is controlled through a MUX structure and an internal control signal, the window selection signal (Window SEL), and the selected final window is output as the IPG window selection signal (Controlled-IPG WINDOW). This signal is then transmitted to the IPG synchronization unit (13) and the IPG field insertion unit (15) to serve as a reference for controlling the synchronization of user data and the reference time signal 1PPS, as well as the actual data insertion timing. Consequently, this process is a core process for generating and controlling a timing window that can actually stably insert user data within the IPG interval, and plays a decisive role in ensuring the real-time capability and precision of the system.

[0079] Next, the IPG is synchronized (S4). When an IPG window selection signal (Controlled-IPG WINDOW) is generated (selected) from the IPG window control unit (12), the IPG synchronization unit (13) synchronizes the parallel data (DATA[15:0]) input from the user and the reference time signal 1PPS with the IPG window selection signal (Controlled-IPG WINDOW) and the system reference Ethernet clock. At this time, the user data and the 1PPS signal are each applied to independent D-flip-flops (131). The IPG window selection signal (Controlled-IPG WINDOW) is input to the enable input terminal (Enable) of the D-flip-flop (131), which is a timing control signal indicating an insertable valid time interval, allowing data to be processed only within that interval. A clock selector (132) is connected to the clock input terminal (CLK) of the D-flip-flop (131), and this clock selector (132) determines the operating mode according to the state of the input 1PPS signal. When 1PPS is 'Low', the clock selector (132) outputs a reference Ethernet clock to perform synchronization, and when 1PPS is 'High', the clock selector (132) outputs a fixed 'High' signal to maintain the data in a constant state. Through this structure, the parallel input data and reference time signal are output in the form of Gated Data (Gated-DATA) and Gated 1PPS (Gated-1PPS) only within the IPG valid interval and precisely aligned with the Ethernet clock. Subsequently, these outputs pass through an AND gate (133) to be finally refined into synchronized 'Synced-DATA[15:0]' and 'Synced-1PPS', which are aligned to match the IPG window selection signal (Controlled-IPG WINDOW). The parallel data synchronized in this way is transmitted to the serial mapper (134) and combined into a 32-bit data format.This format facilitates the structuring of inserted data and restoration at the receiving end, and is optimized for protocol-independent hardware-based data synchronization implementation. The generated 32-bit parallel data is then transmitted to a shift register (135) and sequentially shifted one bit at a time along the system reference Ethernet clock. Through this process, it is finally converted into a single serial bit stream called a synchronized serial data stream (Bit_Shifted[0]), which is used as a data stream to be inserted in real-time during the IPG interval.

[0080] Next, the IPG field is mapped (S5). 'Bit_Shifted[0]', a synchronized serial data stream generated by the IPG synchronization unit (13), is passed to the IPG field mapping unit (14) and aligned into a byte-unit field structure suitable for Ethernet packet insertion. For example, the IPG field mapping unit (14) can be composed of a structure substantially identical to a shift register (e.g., composed of a series of 32 D-flip-flops (DFF[0]~DFF

[31] )). 'Bit_Shifted[0]' is shifted sequentially through the series of D-flip-flops according to the Ethernet clock, and as a result, the 32-bit serial data is aligned into 4 bytes (BYTE1~BYTE4) as shown in [Table 1] below.

[0081] Serial data DFF[0]~DFF[7] DFF[8]~DFF

[15] DFF

[16] ~DFF

[23] DFF

[24] ~DFF

[31] byte BYTE1 BYTE2 BYTE3 BYTE4

[0082] These byte fields are logically separated and can be composed of LOWER_DATA[7:0](BYTE1), UPPER_DATA[15:8](BYTE2), reference time information (1PPS) / Reserved fields (BYTE3~BYTE4), etc., and are used as alignment reference units when inserting an IPG section. All mapping operations are performed in precise synchronization with the system reference Ethernet clock and the IPG window indicating the insertion time, i.e., the IPG window detection signal (Detected-IPG WINDOW) timing. Through this, the serial bit sequence is stably accumulated in byte units and configured into logical data blocks to enable precise positional insertion in the next process, the IPG field insertion process (S6).

[0083] Next, an IPG field is inserted (S6). User data, i.e., the map-field, aligned in 32-bit units in the IPG field mapping unit (14) is transmitted to the IPG field insertion unit (15). The IPG field insertion unit (15) inserts this map-field data by aligning it to the insertion valid interval detected in real time. The IPG field insertion unit (15) outputs data only within the time slot where insertion is allowed through an AND operation between the IPG window detection signal (Detected-IPG WINDOW) and the map-field. That is, each shifted data bit is transmitted only when the IPG interval is open in a 'High' state, and is not output otherwise, thereby precisely controlling the data insertion timing. This method provides the following technical effects. Since data is inserted only within the IPG between Ethernet packets, the original structure of the MAC frame, data field, FCS, etc., are not altered at all, and real-time user data transmission is possible without conflicts or interpretation errors in network protocols. In particular, it is designed to enable clock-based insertion that is precisely adjusted within a 96-bit time (Inter-Packet Gap, IEEE 802.3 standard), so that communication can continue while maintaining the existing frame specifications without the MAC layer or upper layer protocol recognizing whether data has been inserted. Accordingly, the IPG field insertion unit (15) aligns map-field data in real-time with the timing within the IPG interval to transparently include user data, thereby completing a hardware-based stable real-time communication structure that simultaneously satisfies high-precision time synchronization and data insertion.

[0084] Next, an Ethernet packet is transmitted (S7). Serial data precisely inserted within the IPG section in the IPG field insertion section (15) is converted into a physical layer signal suitable for actual Ethernet transmission through a PHY block mounted inside the FPGA. The converted electrical signal is transmitted in real time to a counterpart terminal or network device on the Ethernet channel through the P2-TX port. An important point in this process is that since user data is inserted only within the IPG section without changing the existing Ethernet MAC frame structure, the validity of the frame (FCS, length, structure, etc.) is maintained, and it can be routed and processed normally even through general network equipment. On the counterpart terminal side, the IPG section in the received packet flow is detected in real time through an IPG-based data synchronization receiving module having the same structure as the data synchronization device (10) according to the embodiment of the present invention, and the map-field inserted in that section can be accurately restored. The restored serial data is again parallelized and divided into a 1PPS time signal and user data, thereby enabling stable precise time synchronization and data exchange between the two terminals.

[0085] In the foregoing, preferred embodiments of the present invention have been described and illustrated using specific terms, but such terms are intended solely to clarify the invention, and it is obvious that various modifications and changes may be made to the embodiments and described terms of the present invention without departing from the technical spirit and scope of the following claims. Such modified embodiments should not be understood separately from the spirit and scope of the present invention, but should be considered to fall within the scope of the claims of the present invention. Explanation of the symbols

[0086] 1 : Ethernet packet 10 : Data synchronization insertion device 11: IPG detection unit 12: IPG window adjustment unit 13: IPG Synchronization Section 14: IPG Field Mapping Section 15 : IPG field insertion section 111 : Bit type searcher 112 : Nibble detector 113 : Edge detector 121: Link detection unit 122: Phase synchronization circuit unit 123: Clock selection unit 124: Trigger input unit 125 : Window creation section 126 : Window selection section 127 : Up / Down Control Unit 128 : Clutch Removal Circuit Unit 129: Precision synchronization circuit 131: D-flip-flop 132: Clock selector 133: AND gate 134: Serial Mapper 135: Shift Register 100: Ethernet-based synchronous transmission system Detected-IPG WINDOW: IPG window detection signal IPG WINDOW EDGE : IPG Window Edge signal Controlled-IPG WINDOW : IPG Window Selection Signal Buffered-Detect IPG WINDOW: Buffered IPG window detection signal IPG WINDOW : IPG Window Signal Bit_Shifted[0] : Synchronized serial data stream Gated field: A gated field Synced-New IPG: Synchronized new IPG Synced-Packet: New Ethernet packet NIBBLE_DETECTION : Nibble detection signal Window SEL: Window selection signal

Claims

Claim 1 A data synchronization insertion device using a gap between Ethernet packets, comprising: an IPG detection unit that detects an idle state after the termination of a received Ethernet packet and determines an IPG start point; an IPG window control unit that generates IPG window candidates, which are insertable time intervals of various widths based on the IPG start point, and selects and outputs one of the IPG window candidates; an IPG synchronization unit that generates synchronized serial data by synchronizing user data and a reference time signal with the selected IPG window and the Ethernet clock; an IPG field mapping unit that forms a map-field by aligning the serial data in byte units; and an IPG field insertion unit that inserts the map-field by aligning it to an effective interval of the IPG window; wherein the IPG window control unit receives a reference timing signal output from the IPG detection unit as a trigger input, generates a plurality of timing signals delayed relative to the reference timing signal using a multi-stage D-flip-flop chain, generates a plurality of IPG window candidates of different widths based on the plurality of delayed timing signals, and then selects and outputs an IPG window capable of inserting actual user data among the generated IPG window candidates. Claim 2 A data synchronization insertion device using a gap between Ethernet packets, wherein the IPG detection unit detects an idle state in which all bits in the received data are maintained as '0' in nibble units after the termination of a received Ethernet packet, determines the time at which the idle state is first detected as the IPG start point, generates an IPG window detection signal based on the IPG start point, and outputs an IPG window edge signal generated by detecting the rising edge of the IPG window detection signal as a reference timing signal. Claim 3 delete Claim 4 A data synchronization insertion device using a gap between Ethernet packets, wherein the IPG synchronization unit synchronizes the user data input from the outside and the reference time signal with the Ethernet clock based on the buffered IPG window detection signal provided from the IPG detection unit and the IPG window selected by the IPG window adjustment unit to align them in a parallel form, and outputs a synchronized serial data stream converted into a serial bit sequence that can be inserted into an Ethernet packet, wherein the aligned parallel data is output. Claim 5 A data synchronization insertion device using a gap between Ethernet packets, wherein the IPG field mapping unit aligns a synchronized serial data stream output from the IPG synchronization unit in predetermined byte units to form one or more map-fields, and includes a distinguishing bit pattern for identifying the user data and reference time signal in the map-field to process the map-field into a form that can be inserted into a gap between Ethernet packets. Claim 6 A data synchronization insertion device using a gap between Ethernet packets, wherein the IPG field insertion unit receives an IPG window detection signal provided from the IPG detection unit and a map-field provided from the IPG field mapping unit, aligns and inserts the map-field into an effective section of the IPG window selected by the IPG window adjustment unit, and thereby transmits information including the user data and reference time signal into the gap between Ethernet packets. Claim 7 A data synchronization insertion device using a gap between Ethernet packets, wherein the IPG detection unit includes: a nibble detector that detects an idle state in which all bits are maintained as '0' by monitoring nibble unit input of received data after the termination of a received Ethernet packet; and an edge detector that detects a change in the output of the nibble detector; wherein the nibble detector detects the point in time when the received data becomes '0' to determine the IPG start point and generates an IPG window detection signal based on the IPG start point, and the edge detector detects the rising edge of the IPG window detection signal and outputs an IPG window edge signal for generating an IPG window as a reference timing signal. Claim 8 In claim 7, the IPG window control unit comprises: a trigger input unit that receives the IPG window edge signal provided from the edge detector as a reference timing signal and generates a plurality of delayed timing signals together with the Ethernet clock; a window generation unit that combines the plurality of delayed timing signals to generate a plurality of IPG window candidates having different widths; and a window selection unit that selects one of the IPG window candidates and outputs it as a final IPG window; a data synchronization insertion device using a gap between Ethernet packets. Claim 9 In claim 8, the IPG synchronization unit comprises: a plurality of D-flip-flops that align the user data and reference time signals in a parallel form; a clock selector that selects a clock serving as an operation reference for the D-flip-flops and provides it to the plurality of D-flip-flops; an AND gate that controls the output timing of the parallel data aligned through the D-flip-flops by using an IPG window signal selected by the IPG window control unit as an enable signal; a serial mapper that configures the data aligned through the D-flip-flops into a predefined map-field format; and a shift register that converts the map-field into a serial bit sequence and outputs a synchronized serial data stream; a data synchronization insertion device using a gap between Ethernet packets. Claim 10 In claim 9, the IPG field mapping unit comprises a plurality of D-flip-flops that receive a synchronized serial data stream output from the IPG synchronization unit by synchronizing it with the Ethernet clock and the IPG window signal, and the D-flip-flops of the IPG field mapping unit use the Ethernet clock as a clock input and the IPG window signal as an enable signal to sequentially store the synchronized serial data stream only in the corresponding valid timing interval, reconstruct the sequentially stored bits into 8-bit byte fields based on the bits, and the reconstructed byte fields form a map-field including the user data and the reference time signal, a data synchronization insertion device using a gap interval between Ethernet packets. Claim 11 In claim 10, the IPG field insertion unit comprises a plurality of D-flip-flops that receive a map-field provided by the IPG field mapping unit and process it in synchronization with the Ethernet clock and a buffered IPG window signal, and the D-flip-flops of the IPG field insertion unit take the Ethernet clock as a clock input and the buffered IPG window signal as an enable signal to sequentially store the map-field only in the corresponding effective timing interval to generate a gated field, the gated field is output in correspondence with the effective insertion timing through an AND logic operation with the buffered IPG window detection signal provided by the IPG detection unit, the gated field output in correspondence with the effective insertion timing is inserted into the gap between Ethernet packets, and the inserted gated field is merged with the existing Ethernet packet through an OR circuit and output as a new Ethernet packet containing a new IPG containing synchronization information, a data synchronization insertion device using a gap between Ethernet packets. Claim 12 A method for inserting data using a data synchronization insertion device utilizing a gap between Ethernet packets, comprising: (a) a process of determining an IPG start point by detecting an idle state after the termination of a received Ethernet packet; (b) a process of generating IPG window candidates, which are insertable time intervals of various widths based on the IPG start point, and selecting and outputting one of the IPG window candidates; (c) a process of generating synchronized serial data by synchronizing user data and a reference time signal with the selected IPG window and the Ethernet clock; (d) a process of configuring a map-field by aligning the serial data in byte units; and (e) a process of inserting the map-field by aligning it into the valid interval of the IPG window. A method for inserting data synchronization using a gap between Ethernet packets, comprising: (a) detecting an idle state in which all bits in the received data are maintained as '0' by monitoring the idle state in nibble units after the termination of the received Ethernet packet, determining the time when the idle state is first detected as the IPG start point, generating an IPG window detection signal based on the IPG start point, and outputting the generated IPG window edge signal by detecting the rising edge of the IPG window detection signal as a reference timing signal; and (b) receiving the reference timing signal as a trigger input, generating a plurality of timing signals delayed with respect to the reference timing signal, generating a plurality of IPG window candidates with different widths based on the plurality of delayed timing signals, and then selecting and outputting an IPG window among the generated IPG window candidates that allows for the insertion of actual user data. Claim 13 delete Claim 14 delete Claim 15 In claim 12, the above process (c) aligns the user data and reference time signal in parallel by synchronizing them with the Ethernet clock based on the buffered IPG window detection signal and the selected IPG window, and outputs a synchronized serial data stream converted into a serial bit sequence that can be inserted into an Ethernet packet, using a gap between Ethernet packets for data synchronization insertion. Claim 16 In claim 15, the above process (d) aligns the synchronized serial data stream into one or more map fields by a predetermined byte unit, and processes the map fields into a form that can be inserted into the gap between Ethernet packets by including a distinguishing bit pattern for identifying the user data and reference time signal in the map fields. This is a method for inserting data synchronization using a gap between Ethernet packets. Claim 17 In claim 16, the above process (e) receives the IPG window detection signal and the map-field, aligns and inserts the map-field into the valid interval of the selected IPG window, and thereby transmits information including the user data and reference time signal in real time to the gap interval between Ethernet packets, a method for inserting data synchronization using a gap interval between Ethernet packets.

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