Nonvolatile memory device including selection transistors and operation method thereof

Abstract

A method of operating a memory device according to an embodiment of the present invention comprises: simultaneously programming selection transistors included in a plurality of cell strings, each comprising a plurality of selection transistors and a plurality of memory cells, which are serially connected between a common source line and a plurality of bit lines; and sequentially verifying a group of selection transistors connected to a selected selection line among a plurality of selection lines, and sequentially storing the verification results for each group in a plurality of data latch circuits of each page buffer connected to the bit lines.

Description

Technology Field

[0001] The present invention relates to semiconductor design technology, and specifically, the present invention relates to a method for programming and verifying select transistors of a non-volatile memory device. Background Technology

[0003] Memory devices can be classified into volatile memory devices and nonvolatile memory devices.

[0004] Among these, non-volatile memory devices have relatively slower write and read speeds compared to volatile memory devices, but they can retain stored data even if the power supply is cut off. Therefore, non-volatile memory devices are widely used in portable electronic devices to store data that must be maintained regardless of power supply.

[0005] Non-volatile memory devices can be classified into ROM (Read Only Memory), MROM (Mask ROM), PROM (Programmable ROM), EPROM (Erasable Programmable ROM), EEPROM (Electrically Erasable Programmable ROM), Flash memory, PRAM (Phase change Random Access Memory), MRAM (Magnetic RAM), RRAM (Resistive RAM), FRAM (Ferroelectric RAM), etc., depending on how data is stored.

[0006] Recently, in order to improve the integration density of semiconductor memory devices, semiconductor memory devices having a three-dimensional array structure are being studied.

[0007] delete Prior art literature

[65535] Registered Patent Publication No. 10-2333743 | Published Patent Publication No. 10-2018-0018923 The problem to be solved

[0008] Embodiments of the present invention provide a memory device having a threshold voltage distribution of improved select transistors. means of solving the problem

[0010] According to one embodiment of the present invention, a method of operating a memory device may include: simultaneously programming selection transistors included in a plurality of cell strings, each comprising a plurality of selection transistors and a plurality of memory cells, which are serially connected between a common source line and a plurality of bit lines; and sequentially verifying a group of selection transistors connected to a selected selection line among a plurality of selection lines, and sequentially storing the verification results for each group in a plurality of data latch circuits of each page buffer connected to the bit lines.

[0011] According to one embodiment of the present invention, a memory device may include: a plurality of cell strings each comprising a plurality of source select transistors and a plurality of memory cells, connected between a common source line and a plurality of bit lines; a peripheral circuit including a plurality of page buffers connected to the cell strings through the bit lines and connected to the source select transistors and the memory cells through source select lines and a plurality of word lines; and a control logic for controlling the peripheral circuit to simultaneously program the source select transistors of the cell strings, sequentially verify a group of source select transistors connected to a selected source select line among the source select lines, and sequentially store the verification results of the group in a plurality of data latch circuits of each page buffer. Effects of the invention

[0013] The memory device according to the proposed embodiment has the effect of reducing the execution time of the programming operation of source selection transistors and minimizing damage to the drain selection line during programming by programming the source selection transistors at once and then verifying them by group of source selection transistors connected to the same source selection line.

[0014] In addition, there is an effect of improving the operating characteristics of the memory device by individually adjusting the voltages of the source select lines based on the verification results stored for each group of source select transistors. Brief explanation of the drawing

[0016] FIG. 1 is a drawing for explaining a memory device according to an embodiment of the present invention. Figure 2 is a diagram for explaining the structure of one of the memory blocks of Figure 1. FIG. 3 is a diagram showing an exemplary embodiment of cell strings connected to the same bit line in the memory block of FIG. 2. FIG. 4 is a block diagram for explaining the structure of one of the page buffers of FIG. 1. Figure 5 is a circuit diagram illustrating a part of the page buffer configuration of Figure 4 in more detail. FIG. 6 is a flowchart illustrating a programming method for source selection transistors according to an embodiment of the present invention. FIGS. 7a to 9b are diagrams to help understand the programming operation of the source selection transistors of FIG. 6. FIGS. 10a to 14b are diagrams to help understand the verification operation of the source select transistors of FIG. 6. FIG. 15 is a flowchart illustrating the operation of setting the operating voltage according to an embodiment of the present invention. Specific details for implementing the invention

[0017] Hereinafter, in order to explain in detail enough so that a person skilled in the art to which the present invention pertains can easily implement the technical concept of the present invention, embodiments of the present invention will be described with reference to the accompanying drawings.

[0018] Furthermore, throughout the specification, when a part is described as being "connected" to another part, this includes not only cases where they are "directly connected" but also cases where they are "electrically connected" with an intermediate circuit in between. Additionally, when a part is described as "including" or "equipped" with a certain component, this means that, unless specifically stated otherwise, it does not exclude other components but may include or be equipped with additional components. Moreover, it will be understood that the invention is not limited to the singular form simply because some components are described in the singular form throughout the specification, and that such components may be composed of multiple units.

[0020] FIG. 1 is a drawing for explaining a memory device (100) according to an embodiment of the present invention.

[0021] Referring to FIG. 1, the memory device (100) may include a memory cell array (110), peripheral circuits (120), and control logic (130).

[0022] A memory cell array (110) may include a plurality of memory blocks (BLK1 to BLKz). Each memory block may have a three-dimensional structure. Each memory block may include a plurality of memory cells stacked on a substrate. The plurality of memory blocks (BLK1 to BLKz) may be connected to a peripheral circuit (120) through row lines (RL) and bit lines (BL1 to BLm). The plurality of memory blocks (BLK1 to BLKz) may be commonly connected to the first to m bit lines (BL1 to BLm).

[0023] According to an embodiment, a plurality of memory cells may be non-volatile memory cells. Row lines (RL) may include a common source line, at least one source selection line, a plurality of word lines, and at least one drain selection line. Memory cells connected to the same word line may be defined as a single page. Thus, a single memory block may include a plurality of pages.

[0024] The memory cells included in the memory cell array (110) can each be configured as a single-level cell (SLC) that stores one data bit, a multi-level cell (MLC) that stores two data bits, a triple-level cell (TLC) that stores three data bits, or a quad-level cell (QLC) that can store four data bits.

[0025] The peripheral circuit (120) may be configured to perform a program operation, a read operation, or an erase operation on a selected area of ​​the memory cell array (110) under the control of the control logic (130). The peripheral circuit (120) may drive the memory cell array (110). For example, the peripheral circuit (120) may apply various operating voltages to the row lines (RL) and the first to m-bit lines (BL1 to BLm) or discharge the applied voltages under the control of the control logic (130). The program operation may include at least one program loop. Each program loop may include a program voltage application operation that applies a program voltage and a verification operation that verifies the program result using a verification voltage. The peripheral circuit (120) may perform a program loop including a program voltage application operation and a verification operation at least once on memory cells connected to a selected row line among a plurality of row lines (RL).

[0026] More specifically, the peripheral circuit (120) may include a row decoder (121), a voltage generator (122), a page buffer group (123), a column decoder (124), a data input / output circuit (125), and a sensing circuit (126).

[0027] The row decoder (121) can be connected to the memory cell array (110) via row lines (RL). The row decoder (121) can operate in response to the control of the control logic (130). The row decoder (121) can receive a row address (RADD) from the control logic (130). The row decoder (121) can decode the row address (RADD) to select one of a plurality of memory blocks (BLK1~BLKz). The row decoder (121) can decode the row address (RADD) to select at least one row line among the selected memory blocks and apply voltages (Vop) generated by the voltage generator (122) to the row line.

[0028] For example, the row decoder (121) may apply a program voltage to a selected word line and apply a program pass voltage at a level lower than the program voltage to unselected word lines during a program voltage application operation. The row decoder (121) may apply a verification voltage to a selected word line and apply a verification pass voltage higher than the verification voltage to unselected word lines during a verification operation. The row decoder (121) may apply a read voltage to a selected word line and apply a read pass voltage higher than the read voltage to unselected word lines during a read operation. The erase operation of the memory device (100) may be performed in units of memory blocks. During the erase operation, the row decoder (121) may select one memory block according to the decoded address. During the erase operation, the row decoder (121) may apply a ground voltage to the word lines connected to the selected memory block.

[0029] According to the embodiment, the row decoder (121) may further include an address buffer, a block decoder, and a row decoder, etc.

[0030] The voltage generation unit (122) can operate in response to the control of the control logic (130). The voltage generation unit (122) can generate multiple voltages using the external power supply voltage supplied to the memory device (100). Specifically, the voltage generation unit (122) can generate various operating voltages (Vop) used for program, read, and erase operations in response to an operation signal (OPSIG) provided by the control logic (130). For example, the voltage generation unit (122) can generate a program voltage, a verification voltage, a pass voltage, a read voltage, and an erase voltage.

[0031] According to an embodiment, the voltage generation unit (122) can generate an internal power supply voltage by regulating an external power supply voltage. The internal power supply voltage generated by the voltage generation unit (122) can be used as an operating voltage of the memory device (100). According to an embodiment, the voltage generation unit (122) can generate a plurality of voltages using the external power supply voltage or the internal power supply voltage. For example, the voltage generation unit (122) includes a plurality of pumping capacitors that receive the internal power supply voltage, and can generate a plurality of voltages by selectively activating the plurality of pumping capacitors in response to the control of the control logic (130). The generated plurality of voltages can be supplied to the memory cell array (110) by the row decoder (121).

[0032] The page buffer group (123) may include first to m page buffers (PB1 to PBm). The first to m page buffers (PB1 to PBm) may operate in response to control by the control logic (130). The first to m page buffers (PB1 to PBm) may each be connected to the memory cell array (110) through the first to m bit lines (BL1 to BLm). Specifically, the first to m page buffers (PB1 to PBm) may operate in response to page buffer control signals (PBSIGNALS) provided by the control logic (130). For example, the first to m page buffers (PB1 to PBm) may temporarily store data received through the first to m bit lines (BL1 to BLm) or sense the voltage or current of the bit lines (BL1 to BLm).

[0033] For example, the first to m page buffers (PB1 to PBm) can transmit data (DATA) received from the data input / output circuit (125) through the data line (DL) to the selected memory cells through the first to m bit lines (BL1 to BLm) when a program voltage is applied to a selected word line during a program voltage application operation. The memory cells of the selected pages can be programmed according to the transmitted data (DATA). A memory cell connected to a bit line to which a program allow voltage (e.g., ground voltage) is applied has an elevated threshold voltage, and a memory cell connected to a bit line to which a program prohibit voltage (e.g., power supply voltage) is applied can maintain its threshold voltage.

[0034] The first to m-th page buffers (PB1 to PBm) can read page data from selected memory cells through the first to m-th bit lines (BL1 to BLm) during a verification operation. The first to m-th page buffers (PB1 to PBm) can precharge all bit lines with a precharge voltage during a verification operation.

[0035] The first to m-th page buffers (PB1~PBm) can read data (DATA) from the memory cells of the selected page through the first to m-th bit lines (BL1~BLm) during a read operation, and output the read data (DATA) to the data input / output circuit (125) under the control of the column decoder (124). During an erase operation, the first to m-th page buffers (PB1~PBm) can float the first to m-th bit lines (BL1~BLm).

[0036] The column decoder (124) can operate in response to the control of the control logic (130). The column decoder (124) can transfer data between the data input / output circuit (125) and the page buffer group (123) in response to the column address (CADD) provided by the control logic (130). For example, the column decoder (124) can exchange data with the first to m page buffers (PB1 to PBm) through data lines (DL) or exchange data with the data input / output circuit (125) through data lines (CL).

[0037] The data input / output circuit (125) can exchange data (DATA) with an external device (e.g., a memory controller). The data input / output circuit (125) can operate in response to the control of the control logic (130). According to an embodiment, the data input / output circuit (125) may include a plurality of input / output buffers (not shown) that receive data (DATA) in response to an input / output control signal (DIO). The data input / output circuit (125) can receive data (DATA) to be stored from the memory controller during a program operation, and output data transferred from the first to m-th page buffers (PB1~PBm) to the memory controller during a read operation.

[0038] The sensing circuit (126) can generate a reference current in response to an allow bit signal (VRYBIT) generated by the control logic (130) during a read operation or a verification operation, and output a pass signal (PASS) or a fail signal (FAIL) by comparing the sensing voltage (VPB) received from the page buffer group (123) with the reference voltage generated by the reference current.

[0039] The control logic (130) is configured to control the overall operation of the memory device (100). The control logic (130) can receive a command (CMD) and an address (ADDR) from the memory controller. The control logic (130) can control the peripheral circuit (120) by outputting an operation signal (OPSIG), a row address (RADD), page buffer control signals (PBSIGNALS), an input / output control signal (DIO), and an allow bit (VRYBIT) in response to the command (CMD) and the address (ADDR). Additionally, the control logic (130) can determine whether the verification operation has passed or failed in response to a pass signal (PASS) or fail signal (FAIL) transmitted from the sensing circuit (126).

[0041] FIG. 2 is a diagram for explaining the structure of one of the multiple memory blocks (BLK1~BLKz) of FIG. 1. FIG. 3 is a diagram showing an exemplary embodiment of cell strings (ST) connected to the same bit line in the memory block (BLKi) of FIG. 2.

[0042] Referring to FIGS. 2 and 3, a memory block (BLKi) may include a plurality of cell strings (ST) connected between bit lines (BL1 to BLm) and a common source line (CSL). Bit lines (BL1 to BLm) may each be connected to a predetermined number of cell strings (ST), and the common source line (CSL) may be connected in common to the cell strings (ST). Each cell string (ST) may include a source select transistor (SST), a plurality of memory cells (MC1 to MCn), and a drain select transistor (DST).

[0043] The gates of source select transistors (SST) included in different memory strings (ST) connected to different bit lines (BL1~BLm) can be connected to a first source select line (SSL1) and can be connected to a second source select line (SSL2). For example, source select transistors (SST) that are adjacent to each other in the second direction (Y) can be connected to the same source select line.

[0044] For example, assuming that source select transistors (SST) are arranged sequentially along the second direction (Y), the gates of source select transistors (SST) arranged in the first direction (X) from the first source select transistor (SST) and included in other strings (ST), and the gates of source select transistors (SST) arranged in the first direction (X) from the second source select transistor (SST) and included in other strings (ST) can be connected to the first source select line (SSL1). Additionally, the gates of source select transistors (SST) arranged in the first direction (X) from the third source select transistor (SST) and included in other strings (ST), and the gates of source select transistors (SST) arranged in the first direction (X) from the fourth source select transistor (SST) and included in other strings (ST) can be connected to the second source select line (SSL2).

[0045] The gates of memory cells (MC1 to MCn) can be connected to word lines (WL1 to WLn), respectively, and the gates of drain select transistors (DST) can be connected to any one of the first to fourth drain select lines (DSL1 to DSL4). Among the drain select transistors (DST), the gates of transistors arranged in the first direction (X) are commonly connected to the same drain select line (e.g., DSL1), but transistors arranged in the second direction (Y) can be connected to different drain select lines (DSL1 to DSL4).

[0046] For example, assuming that drain select transistors (DST) are arranged sequentially along the second direction (Y), the gates of the drain select transistors (DST) arranged in the first direction (X) from the first drain select transistor (DST) and included in other strings (ST) can be connected to the first drain select line (DSL1). The drain select transistors (DST) arranged in the second direction (Y) from the drain select transistors (DST) connected to the first drain select line (DSL1) can be sequentially connected to the second to fourth drain select lines (DSL2 to DSL4). Thus, within the selected memory block, memory strings (ST) connected to the selected drain select line can be selected, and memory strings (ST) connected to the remaining non-selected drain select lines can be non-selected.

[0047] Memory cells connected to the same word line can form a single page (PG). Here, a page refers to a physical page. For example, among strings (ST) connected to the first to m-bit lines (BL1~BLm), a group of memory cells connected in the first direction (X) in the same word line is called a page (PG). For example, among the first memory cells (MC1) connected to the first word line (WL1), memory cells arranged along the first direction (X) can form a single page (PG). Among the first memory cells (MC1) commonly connected to the first word line (WL1), cells arranged in the second direction (Y) can be distinguished as different pages. Accordingly, when the first drain selection line (DSL1) is the selected drain selection line and the first word line (WL1) is the selected word line, among the multiple pages (PG) connected to the first word line (WL1), the page connected to the first drain selection line (DSL1) becomes the selected page. Pages connected to the second to fourth drain selection lines (DSL2~DSL4) that are commonly connected to the first word line (WL1) but are not selected become the unselected pages.

[0048] In the case where a single memory cell is a single-level cell (SLC) that stores 1 bit of data, one physical page (PG) can store one logical page (LPG) of data. Also, in the case where a single memory cell is a cell that stores 2 bits or more of data, one physical page (PG) can store 2 or more logical pages (LPG) of data.

[0049] In the drawing, it is shown that one source select transistor (SST) and one drain select transistor (DST) are each included within a single string (ST); however, depending on the memory device, multiple source select transistors (SST) and drain select transistors (DST) may be included within a single string (ST). Additionally, depending on the memory device, dummy cells may be included between the source select transistor (SST), memory cells (MC1~MCn), and drain select transistor (DST). Dummy cells do not store user data like general memory cells (MC1~MCn), but they may be used to improve the electrical characteristics of each string (ST). However, since dummy cells are not a critical component in this embodiment, a detailed description is omitted.

[0050] In FIG. 2, the common source line (CSL), source selection lines (SSL1, SSL2), word lines (WL1~WLn) and drain selection lines (DSL1~DSL4) may correspond to the row lines (RL) of FIG. 1. That is, the common source line (CSL), source selection lines (SSL1, SSL2), word lines (WL1~WLn) and drain selection lines (DSL1~DSL4) may be controlled by a row decoder (121).

[0052] Meanwhile, in a memory device having a three-dimensional array structure, a configuration is proposed in which source select transistors (SST) and / or drain select transistors (DST) are arranged in the same structure as the memory cells. The memory device (100) can electrically connect or electrically disconnect memory cells from a common source line by controlling the source select transistors (SST). If the threshold voltages of the source select transistors (SST) differ significantly from the desired voltage distribution, the source select transistors (SST) cannot be effectively controlled.

[0053] It is assumed that the source select transistors (SST) have threshold voltages higher than the desired voltage distribution. When performing any operation while turning on the source select transistors (SST), the current flowing through the source select transistors (SST) to the common source line (CSL) may be unintentionally reduced. That is, the amount of current flowing through the cell string to the common source line (CSL) may be lowered. It is assumed that the source select transistors (SST) have threshold voltages lower than the desired threshold voltage. When performing any operation while turning off the source select transistors (SST), current may unintentionally leak into the common source line (CSL) through the source select transistors (SST). Therefore, effectively setting the threshold voltages of the source select transistors (SST) is an important factor in improving the reliability of the semiconductor memory device (100).

[0054] Accordingly, the control logic (130) can control the peripheral circuit (120) to perform programming and verification operations of the source select transistors so that the threshold voltages of the source select transistors (SST) can be included in a desired voltage range. The programming operation for the source select transistors can be performed prior to programming the memory cells of each page.

[0055] According to an embodiment of the present invention, the control logic (130) can control the peripheral circuit (120) to simultaneously program all select transistors (SST) included in a plurality of cell strings (ST). During the programming operation for the source select transistors (SST), the voltage generator (122) and the row decoder (121) can provide a program voltage to the source select lines (SSL1, SSL2) and apply a ground voltage to the common source line (CSL) in response to the control of the control logic (130). During the programming operation for the source select transistors (SST), the first to m-page buffers (PB1~PBm) can apply a ground voltage to the bit lines (BL1~BLm) in response to the control of the control logic (130).

[0056] Additionally, the control logic (130) can control the peripheral circuit (120) to select a group of select transistors (SST) connected to the same select line and sequentially store the verification results of the selected group in multiple data latch circuits within each page buffer connected to the bit lines (BL1~BLm). During the verification operation for the source select transistors source select lines (SST), the first to m page buffers (PB1~PBm) can sequentially store the verification results for each group of source select transistors connected to the same source select line in their internal data latch circuits in response to the control of the control logic (130). The control logic (130) can set the operating voltage for each group of source select transistors based on the verification results stored in the data latch circuits. According to an embodiment, the sensing circuit (126) generates a pass signal (PASS) or a fail signal (FAIL) based on the verification results stored in the data latch circuits, and the control logic (130) can set an operating voltage for each group of source select transistors in response to the pass signal (PASS) or fail signal (FAIL). Accordingly, the reliability of the memory device (100) can be improved.

[0058] FIG. 4 is a diagram for explaining the structure of the first page buffer (PB1) among the first to m page buffers (PB1~PBm) of FIG. 1.

[0059] Referring to FIG. 4, the first page buffer (PB1) may include a bit line connection circuit (310), a precharge circuit (312), a sensing latch circuit (320), a plurality of data latch circuits (330), and a cache latch circuit (340). Before description, the first page buffer (PB1) may be controlled based on page buffer control signals (PBSIGNALS) generated in the control logic (130) of FIG. 1. That is, signals controlling the first page buffer (PB1) may be included in the page buffer control signals (PBSIGNALS).

[0060] The bit line connection circuit (310) selectively connects the first bit line (BL1) according to the connection control signal (BL_CTRL), and can transmit input data transmitted through the sensing node (SO) to the first bit line (BL1) during a program operation, and can sense data transmitted through the first bit line (BL1) and transmit it to the sensing node (SO) during a read operation. Additionally, the bit line connection circuit (310) can discharge the first bit line (BL1) according to the connection control signal (BL_CTRL) and the bit line discharge signal (BLDIS).

[0061] A bit line connection circuit (310) according to one embodiment of the present invention can discharge the first bit line (BL1) to a ground voltage level during the programming operation of the source select transistor (SST). A detailed explanation thereof will be provided in FIG. 8.

[0062] The precharge circuit (312) can precharge the sensing node (SO) to the core voltage level based on the precharge signal (PRECHSO_N).

[0063] The sensing latch circuit (320) can store sensing data by sensing a voltage change of the sensing node (SO) according to the sensing latch control signal (S_CTRL). The sensing data has a preset logic level as an initial value, and the logic level may be maintained or the logic level may be inverted according to the output data transmitted through the first bit line (BL1) during a read operation or verification operation. The sensing latch circuit (320) can dump the sensing data to the cache latch circuit (340) during a read operation according to the sensing latch control signal (S_CTRL). During a read operation or verification operation, the sensing latch circuit (320) can provide the voltage of the stored sensing data to the sensing circuit (126 in FIG. 1) as a sensing voltage (VPB).

[0064] Meanwhile, the sensing latch circuit (320) according to one embodiment of the present invention can discharge the first bit line (BL1) by setting the sensing data to a specific logic level (e.g., logic high level) during the programming operation of the source select transistor (SST). A detailed explanation thereof will be provided in FIGS. 9a and 9b. In addition, the sensing latch circuit (320) according to one embodiment of the present invention can sequentially dump the sensing data to a plurality of data latch circuits (330) during the verification operation of the source select transistor (SST). A detailed explanation thereof will be provided in FIGS. 11 and 13b.

[0065] The cache latch circuit (340) can output dumped data to the outside through the data input / output circuit (125 in FIG. 1) according to the cache latch control signal (C_CTRL). According to an embodiment, the cache latch circuit (340) can transmit data input through the data input / output circuit (125) to a plurality of data latch circuits (330).

[0066] A plurality of data latch circuits (330) can store input data during program operation according to a plurality of data control signals (D1_CTRL, D2_CTRL, etc.) and transmit the stored data to a sensing node (SO). The number of a plurality of data latch circuits (330) can be designed differently depending on the number of data distributions stored in the memory cell, and can be provided in a number corresponding to a single-level cell, a multi-level cell, or a triple-level cell. For example, assuming that data corresponding to a triple-level cell is input, first to third data latch circuits are provided, the first data latch circuit can receive data corresponding to the MSB (Most Significant Bit), the second data latch circuit can receive data corresponding to the CSB (Central Significant Bit), and the third data latch circuit can receive data corresponding to the LSB (Least Significant Bit).

[0067] A plurality of data latch circuits (330) according to an embodiment of the present invention can receive and sequentially store the verification results of each group of source select transistors transmitted from the first bit line (BL1) through the sensing latch circuit (320) during the verification operation of the source select transistor (SST). According to an embodiment of the present invention, the sensing circuit (126) can receive the voltage of the data stored in the data latch circuits (330) as the sensing voltage (VPB) during the verification operation of the source select transistor (SST).

[0068] Meanwhile, the first page buffer (PB1) may include one or more verification latch circuits in addition to the above configuration, but the description of the remaining configurations will be omitted in order to faithfully explain the gist of the invention.

[0070] FIG. 5 is a circuit diagram showing a part of the configuration of the first page buffer (PB1) of FIG. 4 in more detail.

[0071] Referring to FIG. 5, the detailed configuration of the bit line connection circuit (310), precharge circuit (312), and sensing latch circuit (320) is shown.

[0072] The bit line connection circuit (310) may include first to seventh NMOS transistors (N1-N8) and first and second PMOS transistors (P1, P2). The first NMOS transistor (N1) and the second NMOS transistor (N2) are connected in series between the first bit line (BL1) and the ground voltage (VSS) terminal, and can receive a bit line select signal (SEL_BL) and a bit line discharge signal (BLDIS) as inputs to their respective gates. The third NMOS transistor (N3) is connected between the common node (BLCM) of the first NMOS transistor (N1) and the second NMOS transistor (N2) and the current sensing node (CSO), and can receive a bit line sensing signal (PB_SENSE) as input to its gate. The first and second PMOS transistors (P1, P2) and the fourth NMOS transistor (N4) are connected in series between the core voltage (VCORE) terminal and the current sensing node (CSO), and can receive the signal of the positive sensing node (QS), the precharge control signal (SA_PRECH_N), and the sensing control signal (SA_SENSE) as inputs to their respective gates. The fifth NMOS transistor (N5) is connected between the common node of the first and second PMOS transistors (P1, P2) and the current sensing node (CSO), and can receive the sense amplifier connection signal (SA_CSOC) as input to its gate. The sixth and seventh NMOS transistors (N6, N7) are connected between the current sensing node (CSO) and the ground voltage (VSS) terminal, and can receive the sense amplifier discharge signal (SA_DISCH) and the signal of the positive sensing node (QS) as inputs to their respective gates.

[0073] With the above configuration, the bit line connection circuit (310) can transmit input data transmitted through the sensing node (SO) to the first bit line (BL1) based on the bit line selection signal (SEL_BL), the bit line sensing signal (PB_SENSE), and the sensing control signal (SA_SENSE), or sense data transmitted through the first bit line (BL1) and transmit it to the sensing node (SO). Additionally, the bit line connection circuit (310) can discharge the first bit line (BL1) to the ground voltage (VSS) level according to the bit line selection signal (SEL_BL) and the bit line discharge signal (BLDIS). For reference, the bit line selection signal (SEL_BL), the bit line sensing signal (PB_SENSE), and the sensing control signal (SA_SENSE) may correspond to the connection control signal (BL_CTRL) of FIG. 4.

[0074] The precharge circuit (312) may include a third PMOS transistor (P3). The third PMOS transistor (P3) is connected between the core voltage (VCORE) terminal and the sensing node (SO) and can receive a precharge signal (PRECHSO_N) as input to its gate. The precharge circuit (312) can precharge the sensing node (SO) to the core voltage (VCORE) level based on the precharge signal (PRECHSO_N).

[0075] The sensing latch circuit (320) can store sensing data for a sensing operation of data transmitted through the first bit line (BL1) based on a sensing reset signal (SRST) and a sensing set signal (SSET). The sensing latch circuit (320) may include a sensing latch (322) and eighth to eleventh NMOS transistors (N8-N11). The sensing latch (322) may be composed of two cross-coupled inverters connected between a positive sensing node (QS) and a negative sensing node (QS_N). The eighth NMOS transistor (N8) and the ninth NMOS transistor (N9) are connected in series between the positive sensing node (QS) and the ground voltage (VSS) terminal, and can receive the sensing reset signal (SRST) and the page reset signal (PBRST) as inputs to their respective gates. The 10th NMOS transistor (N10) is connected between the sub-sensing node (QS_N) and the common node (COM1) between the 8th and 9th NMOS transistors (N8, N9), and can receive a sensing set signal (SSET) as input to its gate. The 11th NMOS transistor (N11) is connected between the 1st common node (COM1) and the ground voltage (VSS) terminal, and can receive a signal from the sensing node (SO) as input to its gate, and can form a current path connected to the ground power terminal (VSS) based on the voltage level of the sensing node (SO).

[0076] With the above configuration, the sensing latch circuit (320) can store sensing data based on the sensing reset signal (SRST) and the sensing set signal (SSET) during a read operation or a verification operation. For reference, the sensing reset signal (SRST), the sensing set signal (SSET), and the page reset signal (PBRST) may correspond to the sensing latch control signal (S_CTRL) of FIG. 4.

[0078] Hereinafter, a programming method for source selection transistors according to an embodiment of the present invention will be described with reference to FIGS. 1 to 15.

[0079] FIG. 6 is a flowchart illustrating a method for programming source select transistors according to an embodiment of the present invention. FIGS. 7a to 9b are diagrams to aid in understanding the programming operation (S110) of the source select transistors of FIG. 6. FIGS. 10a and 14b are diagrams to aid in understanding the verification operation (S130) of the source select transistors of FIG. 6.

[0080] Referring to FIG. 6, the control logic (130) can control the peripheral circuit (120) to program source select transistors of a plurality of cell strings. For example, referring to FIG. 1 and FIG. 3, the peripheral circuit (120) can simultaneously program source select transistors (SST) included in a plurality of cell strings (ST) connected between bit lines (BL1~BLm) and a common source line (CSL) (S110). That is, the peripheral circuit (120) can perform a programming operation for all source select transistors (SST) connected to the first source select line (SSL1) and the second source select line (SSL2). The programming operation can be performed using a programming voltage having a fixed voltage level.

[0081] Referring to FIGS. 7a and 7b, during program operation, the control logic (130) can control the voltage generator (122) and the row decoder (121) so that a ground voltage is applied to the common source line (CSL), a pass voltage (VPASS) is applied to a plurality of word lines (WL1~WLn), and a program voltage (VPGM) is applied to the first source select line (SSL1) and the second source select line (SSL2). The pass voltage (VPASS) has a voltage level capable of turning on memory cells (MC1~MCn) connected to the word lines (WL1~WLn), and may be a power supply voltage or high voltages similar to or higher than the power supply voltage. The program voltage (VPGM) may be a high voltage higher than the pass voltage (VPASS). At this time, the control logic (130) selects the first to fourth drains The voltage generator (122) and row decoder (121) can be controlled so that a ground voltage (VSS) or a drain select voltage (VDSL) is applied to the lines (DSL1~DSL4). The drain select voltage (VDSL) may be a voltage level capable of turning on the drain select transistors (DST).

[0082] Additionally, the control logic (130) can control the first to m page buffers (PB1 to PBm) so that a ground voltage (VSS) can be applied to the bit lines (BL1 to BLm).

[0083] According to one embodiment, with reference to FIG. 8, the control logic (130) can provide a logic high-level bit line select signal (SEL_BL) and a bit line discharge signal (BLDIS) to the first page buffer (PB1). Accordingly, the first NMOS transistor (N1) and the second NMOS transistor (N2) of the first page buffer (PB1) can be turned on to drive the first bit line (BL1) to the ground voltage (VSS) level.

[0084] According to another embodiment, with reference to FIGS. 9a and 9b, the control logic (130) may provide a logic low level precharge signal (PRECHSO_N) and a logic high level sensing set signal (SSET) to the first page buffer (PB1). Accordingly, the third PMOS transistor (P3) of the first page buffer (PB1) is turned on so that the sensing node (SO) is precharged to the core voltage (VCORE) level, and the tenth NMOS transistor (N10) and the eleventh NMOS transistor (N11) are turned on so that the negative sensing node (QS_N) is initialized to a logic low level and the positive sensing node (QS) is initialized to a logic high level. Accordingly, the seventh NMOS transistor (N7) remains turned on. Afterward, the control logic (130) can provide a logic high-level bit line select signal (SEL_BL), a bit line sensing signal (PB_SENSE), and a sense amplifier discharge signal (SA_DISCH) to the first page buffer (PB1). Accordingly, the first NMOS transistor (N1), the third NMOS transistor (N3), and the sixth NMOS transistor (N6) of the first page buffer (PB1) can be additionally turned on to drive the first bit line (BL1) to the ground voltage (VSS) level.

[0085] As described above, during a program operation, a ground voltage is applied to the common source line (CSL), a pass voltage (VPASS) is applied to multiple word lines (WL1~WLn), a ground voltage (VSS) is applied to the first bit line (BL1), and a program voltage (VPGM) is applied to the first source select line (SSL1) and the second source select line (SSL2), thereby maintaining the threshold voltages of the memory cells (MC1~MCn) while increasing the threshold voltages of the source select transistors (SST). Accordingly, the source select transistors (SST) can be programmed. At this time, the drain select transistors (DST) can be maintained in a turned-on state or a turned-off state. That is, the source select transistors (SST) can be programmed regardless of the state of the drain select transistors (DST).

[0086] Meanwhile, the programming operation for the source select transistors (SST) can be performed before data is stored in the memory cells (MC1 to MCn). In this case, the threshold voltages of the memory cells (MC1 to MCn) will be lower than the ground voltage during the programming operation for the source select transistors (SST). Therefore, even if the ground voltage is applied to the word lines (WL1 to WLn), the memory cells (MC1 to MCn) can be turned on.

[0087] Referring again to FIG. 6, the control logic (130) can control the peripheral circuit (120) to sequentially select a first source selection line (SSL1) and a second source selection line (SSL2) (S120). For example, a row decoder (121) can select the first source selection line (SSL1) by decoding a row address (RADD) provided by the control logic (130). The control logic (130) can control the peripheral circuit (120) to perform a verification operation on a group of source selection transistors (SST) connected to the selected first source selection line (SSL1) and to store the verification result in one of the multiple data latch circuits (330) of the first to m-th page buffers (PB1 to PBm) (for example, the first data latch circuit (330_1)) (S130).

[0088] Referring to FIGS. 10a and 10b, during a verification operation, the control logic (130) can control the first to m page buffers (PB1 to PBm) to provide a predetermined voltage or current (e.g., a sensing voltage (VSENSE)) to the bit lines (BL1 to BLm). For reference, the sensing voltage (VSENSE) may have a level reduced by the threshold voltage of the transistors in the page buffer from the core voltage (VCORE) level. Additionally, the control logic (130) can control the voltage generator (122) and the row decoder (121) to apply a read voltage (VREAD) to the selected first source select line (SSL1), while applying a ground voltage (VSS) to the unselected second source select line (SSL2). The read voltage (VREAD) may be a voltage level greater than the ground voltage (VSS) level but lower than the pass voltage (VPASS) level. The control logic (130) can control the voltage generator (122) and row decoder (121) so that a ground voltage is applied to the common source line (CSL) and a pass voltage (VPASS) is applied to a plurality of word lines (WL1~WLn).

[0089] Additionally, the control logic (130) can control the voltage generator (122) and the row decoder (121) so that a pass voltage (VPASS) is applied to the first and second drain selection lines (DSL1, DSL2) of the cell strings (SEL_ST in FIG. 10b) connected to the selected first source selection line (SSL1), while a ground voltage (VSS) is applied to the third and fourth drain selection lines (DSL3, DSL4) of the cell strings (UNSEL_ST in FIG. 10b) connected to the unselected second source selection line (SSL2). Accordingly, the drain selection transistors (DST), memory cells (MC1~MCn), and source selection transistors (SST) of the cell strings (SEL_ST) connected to the selected first source selection line (SSL1) can be turned on. On the other hand, the drain select transistors (DST) and source select transistors (SST) of the cell strings (UNSEL_ST) connected to the unselected second source select line (SSL2) can be turned off.

[0090] The control logic (130) can control the first to m page buffers (PB1 to PBm) to store voltage or current changes output through the first bit line (BL1) from cell strings (SEL_ST) connected to the selected first source select line (SSL1) in the first data latch circuit (330_1). Referring to FIG. 11, the bit line connection circuit (310) can sense data transmitted through the first bit line (BL1) and transmit it to a sensing node (SO). The sensing latch circuit (320) can store sensing data according to the output data transmitted through the first bit line (BL1) and dump (D1) the stored sensing data to the first data latch circuit (330_1). Accordingly, the verification result for the group of source select transistors (SST) connected to the first source select line (SSL1) can be stored in the first data latch circuit (330_1).

[0091] According to another embodiment, during a verification operation, the control logic (130) can control the voltage generator (122) and the row decoder (121) to sequentially select cell strings connected to the selected first source selection line (SSL1). For example, referring to FIG. 12a, the voltage generator (122) and the row decoder (121) can select a cell string (SEL_ST) by applying a pass voltage (VPASS) only to the first drain selection line (DSL1). The sensing latch circuit (320) can store sensing data according to the output data transmitted through the first bit line (BL1). Subsequently, referring to FIG. 12b, the voltage generator (122) and the row decoder (121) can be controlled to select a cell string (SEL_ST) by applying a pass voltage (VPASS) only to the second drain selection line (DSL2). The sensing latch circuit (320) can store sensing data according to output data transmitted through the first bit line (BL1). At this time, if either the selected cell string (SEL_ST) of FIG. 12a or the selected cell string (SEL_ST) of FIG. 12b is programmed normally, the sensing data stored in the sensing latch circuit (320) can be stored according to the case where the program is finally passed. As described in FIG. 11, the control logic (130) can control the first to m-page buffers (PB1~PBm) to dump (D1) the sensing data stored in the sensing latch circuit (320) to the first data latch circuit (330_1). Accordingly, the verification result for the group of source select transistors (SST) connected to the first source select line (SSL1) can be stored in the first data latch circuit (330_1).

[0092] Referring again to FIG. 6, the control logic (130) can control the peripheral circuit (120) to select the next source selection line, a second source selection line (SSL2) (S120), perform a verification operation on a group of source selection transistors (SST) connected to the selected second source selection line (SSL2), and store the verification result in one of the multiple data latch circuits (330) of the first to m-th page buffers (PB1 to PBm) (e.g., a second data latch circuit (330_2)) (S130).

[0093] Referring to FIG. 13a, the control logic (130) can control the peripheral circuit (120) to perform a verification operation in a manner similar to that described in FIG. 10a and FIG. 10b. Accordingly, the drain select transistors (DST), memory cells (MC1–MCn), and source select transistors (SST) of the cell strings (SEL_ST in FIG. 13a) connected to the selected second source select line (SSL2) can be turned on. On the other hand, the drain select transistors (DST) and source select transistors (SST) of the cell strings (UNSEL_ST in FIG. 13a) connected to the unselected first source select line (SSL1) can be turned off. The control logic (130) can control the first to m page buffers (PB1 to PBm) to store voltage or current changes output through the first bit line (BL1) from cell strings (SEL_ST) connected to the selected second source select line (SSL2) in the second data latch circuit (330_2). Referring to FIG. 13b, the bit line connection circuit (310) can sense data transmitted through the first bit line (BL1) and transmit it to a sensing node (SO). The sensing latch circuit (320) can store the sensing data according to the output data transmitted through the first bit line (BL1) and dump (D2) the stored sensing data to the second data latch circuit (330_2). Accordingly, the verification result for the group of source select transistors (SST) connected to the second source select line (SSL2) can be stored in the second data latch circuit (330_2).

[0094] According to another embodiment, during a verification operation, the control logic (130) can control the voltage generator (122) and the row decoder (121) to sequentially select cell strings connected to the selected second source selection line (SSL2). For example, referring to FIG. 14a, the voltage generator (122) and the row decoder (121) can select a cell string (SEL_ST) by applying a pass voltage (VPASS) only to the third drain selection line (DSL3). The sensing latch circuit (320) can store sensing data according to the output data transmitted through the first bit line (BL1). Then, referring to FIG. 14b, the voltage generator (122) and the row decoder (121) can select a cell string (SEL_ST) by applying a pass voltage (VPASS) only to the fourth drain selection line (DSL4). The sensing latch circuit (320) can store sensing data according to output data transmitted through the first bit line (BL1). At this time, if either the selected cell string (SEL_ST) of FIG. 14a or the selected cell string (SEL_ST) of FIG. 14b is programmed normally, the sensing data stored in the sensing latch circuit (320) can be stored according to the case where the program is finally passed. Accordingly, the verification result for the group of source select transistors (SST) connected to the second source select line (SSL2) can be stored in the second data latch circuit (330_2). As described in FIG. 13b, the control logic (130) can control the first to m-page buffers (PB1~PBm) to dump (D2) the sensing data stored in the sensing latch circuit (320) to the second data latch circuit (330_2). Accordingly, the verification result for the group of source select transistors (SST) connected to the second source select line (SSL2) can be stored in the second data latch circuit (330_2).

[0095] Referring again to FIG. 6, when the verification results for all source selection lines are stored in the data latch circuits (“YES”) of S140, the control logic (130) can set the operating voltage for each group of source selection transistors (SST) using the verification results stored in the first and second data latch circuits (330_1, 330_2) (S150). At this time, the operating voltage may be a voltage for turning on the source selection transistors (SST) during the program or read operation for the memory cells of each subsequent page.

[0097] FIG. 15 is a flowchart for explaining the setting operation (S150) of the operating voltage according to an embodiment of the present invention.

[0098] Referring to FIG. 15, the control logic (130) can set the group-specific operating voltage of the source select transistors (SST) using the verification results stored in the first and second data latch circuits (330_1, 330_2). First, the control logic (130) can determine whether the program of the source select transistors (SST) connected to the first source select line (SSL1) is a pass based on the verification result (hereinafter, the first verification result) stored in the first data latch circuit (330_1) (S210). Additionally, the control logic (130) can determine whether the program of the source select transistors (SST) connected to the second source select line (SSL2) is a pass based on the verification result (hereinafter, the second verification result) stored in the second data latch circuit (330_2) (S220).

[0099] According to an embodiment, the sensing circuit (126) of the peripheral circuit (120) can output a pass / fail signal (PASS / FAIL) by comparing a sensing voltage (VPB) corresponding to a first verification result with a reference voltage in response to an allow bit signal (VRYBIT) provided from the control logic (130), and output a pass / fail signal (PASS / FAIL) by comparing a sensing voltage (VPB) corresponding to a second verification result with a reference voltage.

[0100] If both the first verification result and the second verification result are confirmed to be a failure (“YES”) of S230, the control logic (130) determines that the program of the source select transistors (SST) has failed and can control the peripheral circuit (120) to re-perform the program operation and verification operation described in FIGS. 6 to 14b (S240). At this time, the program voltage (VPGM) applied to the source select transistors (SST) can be increased or decreased.

[0101] If either the first verification result or the second verification result is confirmed as a pass ("NO" of S230), the control logic (130) can set the operating voltage for each group of source select transistors (SST) according to the verification result confirmed as a pass (S250). For example, if the first verification result is a pass and the second verification result is confirmed as a fail, the control logic (130) can set the operating voltage of the source select transistors (SST) connected to the first source select line (SSL1) to a voltage level corresponding to the program voltage (VPGM), and the operating voltage of the source select transistors (SST) connected to the second source select line (SSL2) to a level lower than the set operating voltage. Conversely, if the first verification result is a fail and the second verification result is confirmed to be a pass, the control logic (130) can set the operating voltage of the source select transistors (SST) connected to the second source select line (SSL2) to a voltage level corresponding to the program voltage (VPGM), and the operating voltage of the source select transistors (SST) connected to the first source select line (SSL1) to a level lower than the set operating voltage (VPGM). That is, the control logic (130) can set the operating voltage (SST) of the source select transistors whose verification result is a fail lower than the operating voltage (SST) of the group of source select transistors whose verification result is a pass.

[0102] As described above, in an embodiment of the proposed invention, source select transistors (SSTs) connected to all source select lines can be programmed at once, and then verified by group of source select transistors (SSTs) connected to the same source select line. Accordingly, the execution time of the programming operation of the source select transistors (SSTs) can be reduced, while damage to the drain select line during programming can be minimized. In addition, operating characteristics can be improved by individually adjusting the voltages of the source select lines based on the verification results stored for each group of source select transistors (SSTs).

[0103] Meanwhile, although the above embodiments described a method for programming source select transistors connected to source select lines, the proposed invention is not limited thereto and can also be applied when programming drain select transistors connected to drain select lines. That is, drain select transistors connected to all drain select lines can be programmed at once, and then verified by group of drain select transistors connected to the same drain select line.

[0105] Although the technical concept of the present invention has been specifically described according to the preferred embodiments above, it should be noted that the above-described embodiments are for illustrative purposes only and are not intended to be limiting. Furthermore, a person skilled in the art will understand that various embodiments are possible within the scope of the technical concept of the present invention.

[0106] For example, the logic gates and transistors exemplified in the above-described embodiment must be implemented with different positions and types depending on the polarity of the input signal.

Claims

Claim 1 A method of operation of a non-volatile memory device comprising: a step of simultaneously programming the selection transistors included in a plurality of cell strings, each comprising a plurality of selection transistors and a plurality of memory cells, which are serially connected between a common source line and a plurality of bit lines; and a step of sequentially verifying a group of selection transistors connected to a selected selection line among a plurality of selection lines, and sequentially storing the verification results for each group in a plurality of data latch circuits of each page buffer connected to the bit lines. Claim 2 A method of operation of a non-volatile memory device according to claim 1, further comprising the step of setting an operating voltage for turning on the selection transistors for each group using verification results stored in the data latch circuits. Claim 3 In claim 2, the step of setting the operating voltage is a method of operating a non-volatile memory device in which the operating voltage of select transistors whose verification result is a fail is set lower than the operating voltage of select transistors whose verification result is a pass among the verification results. Claim 4 A method of operation of a non-volatile memory device according to claim 1, wherein if the verification results of all groups fail, the step of simultaneously programming, the step of sequentially verifying, and the step of sequentially storing the verification results for each group in the data latch circuits are repeated. Claim 5 A method of operation of a non-volatile memory device according to claim 4, wherein the level of the program voltage applied to the selection transistors is adjusted before the above re-execution. Claim 6 A method of operation of a non-volatile memory device according to claim 1, wherein the programming step comprises applying a ground voltage to the bit lines and the common source line, applying a pass voltage higher than the ground voltage to the word lines connected to the memory cells, and applying a program voltage higher than the pass voltage to the select lines connected to the select transistors. Claim 7 A method of operation of a non-volatile memory device according to claim 1, wherein the verification step comprises providing a sensing voltage to the bit lines, applying a ground voltage to the common source line, applying a read voltage higher than the ground voltage to the selected select lines, and applying the ground voltage to the unselected source select lines. Claim 8 A non-volatile memory device comprising: a plurality of cell strings each including a plurality of source select transistors and a plurality of memory cells, connected between a common source line and a plurality of bit lines; a plurality of page buffers connected to the cell strings through the bit lines, and a peripheral circuit connected to the source select transistors and the memory cells through source select lines and a plurality of word lines; and a control logic for controlling the peripheral circuit to simultaneously program the source select transistors of the cell strings, sequentially verify a group of source select transistors connected to a selected source select line among the source select lines, and sequentially store the verification results of the group in a plurality of data latch circuits of each page buffer. Claim 9 In claim 8, the control logic is a non-volatile memory device that sets an operating voltage for turning on source select transistors for each group of source select transistors using verification results stored in the data latch circuits. Claim 10 In claim 9, the control logic sets the operating voltage of the select transistors in which the verification result is a fail lower than the operating voltage of the select transistors in the group in which the verification result is a pass among the verification results. Claim 11 A non-volatile memory device according to claim 8, wherein the control logic controls the peripheral circuit to apply a ground voltage to the bit lines and the common source line during programming, apply a pass voltage higher than the ground voltage to the word lines, and apply a program voltage higher than the pass voltage to the source select lines. Claim 12 A non-volatile memory device according to claim 8, wherein the control logic controls the peripheral circuit to provide a sensing voltage to the bit lines, apply a ground voltage to the common source line, apply a read voltage higher than the ground voltage to the selected source select lines, apply the ground voltage to the unselected source select lines, and apply a pass voltage higher than the read voltage to the word lines during verification. Claim 13 In claim 8, each cell string further comprises at least one drain select transistor connected between a corresponding bit line and the highest memory cell among the memory cells, in a non-volatile memory device. Claim 14 In claim 13, the control logic controls the peripheral circuit to apply a drain selection voltage of a ground voltage or turn-on voltage level to a drain selection line connected to the drain selection transistor during programming. Claim 15 In claim 8, each page buffer comprises: a bit line connection circuit that transmits data transmitted through a corresponding bit line to a sensing node according to a connection control signal; a sensing latch circuit that senses a voltage change of the sensing node according to a sensing latch control signal and stores the sensing data; and the plurality of data latch circuits that sequentially store the sensing data according to a plurality of data control signals, wherein the connection control signal, the sensing latch control signal, and the data control signals are provided from the control logic, in a non-volatile memory device. Claim 16 In claim 15, the bit line connection circuit is a non-volatile memory device that precharges the corresponding bit line to ground voltage during programming. Claim 17 In claim 15, the sensing latch circuit is a non-volatile memory device that, during programming, sets the sensing data to a specific logic level and precharges the corresponding bit line to ground voltage.

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