Method and Apparatus for Dynamically Allocating SRAM Array for Cache Mode and SPM Mode

Abstract

The present disclosure relates to a method and apparatus for dynamically allocating an SRAM array to a Cache mode and an SPM mode. According to one aspect of the present disclosure, a method for dynamic allocation of an SRAM array is provided, comprising: a process for receiving an SPM request message; a process for acquiring a cache line usable as a SPM (scratched pad memory) among a plurality of cache lines of n cache ways constituting an n-way set-associative cache according to the SPM request message, and setting the first cache line as the first SPM line; a process for recording access information related to the access occurrence message when an access occurrence message for the first SPM line is received; and a process for restoring the first SPM line as a cache line when it is confirmed that the use of the first SPM line is completed based on the access information.

Description

Technology Field

[0001] The present disclosure relates to a method and apparatus for dynamically allocating a Static Random Access Memory (SRAM) array to a Cache mode and an SPM mode. Background Technology

[0002] The following description merely provides background information related to the present embodiment and does not constitute prior art.

[0003] Conventionally, while a kernel is running, on-chip SRAM (Static Random Access Memory) is statically divided into a cache area and a SPM (scratched pad memory) area. In other words, before the kernel starts, the SRAM array area that can be used as shared memory can be divided into a cache area and an SPM area, and the smallest configuration unit for dividing these areas can be viewed as the kernel level.

[0004] If a portion of the cache area within the RAM array can be dynamically changed to an SPM area as needed even within the operation of the kernel, the cache area can be used efficiently. U.S. Patent Publication US 2019-0197015 (June 27, 2019) discloses matters related to the background technology of the present invention. The problem to be solved

[0005] The main purpose of the present disclosure is to provide a method and apparatus for dynamically allocating an SRAM array to Cache mode and SPM mode.

[0006] The problems that the present invention aims to solve are not limited to those mentioned above, and other unmentioned problems will be clearly understood by a person skilled in the art from the description below. means of solving the problem

[0007] According to one aspect of the present disclosure, a method for dynamic allocation of an SRAM array is provided, comprising: a process for receiving an SPM request message; a process for acquiring a cache line usable as a SPM (scratched pad memory) among a plurality of cache lines of n cache ways constituting an n-way set-associative cache according to the SPM request message, and setting the first cache line as the first SPM line; a process for recording access information related to the access occurrence message when an access occurrence message for the first SPM line is received; and a process for restoring the first SPM line as a cache line when it is confirmed that the use of the first SPM line is completed based on the access information.

[0008] A computer program stored on a computer-readable recording medium is provided to execute each process included in the above-described SRAM array dynamic allocation method.

[0009] According to another aspect of the present disclosure, an SRAM array dynamic allocation device is provided, comprising: an SPM request receiving unit for receiving an SPM request message; an SPM area acquiring unit for acquiring a cache line usable as a SPM (scratched pad memory) among a plurality of cache lines of n cache ways constituting an n-way set-associative cache according to the SPM request message, and setting the first cache line as the first SPM line; an access information recording unit for recording access information related to the access occurrence message when an access occurrence message for the first SPM line is received; and a cache line restoration unit for restoring the first SPM line as a cache line when it is confirmed that the use of the first SPM line is completed based on the access information. Effects of the invention

[0010] According to an embodiment of the present disclosure, the cache area is efficiently utilized by dynamically changing a portion of the cache area within the RAM array into an SPM area as needed, even in an operating kernel.

[0011] The effects of the present disclosure are not limited to those mentioned above, and other unmentioned effects will be clearly understood by a person skilled in the art from the description below. Brief explanation of the drawing

[0012] FIG. 1 is a block diagram illustrating the configuration of an SRAM array dynamic allocation device (100) according to one embodiment of the present disclosure. Figure 2 is a diagram illustrating n cache ways that constitute an n-way set associative cache. Figure 3 is a diagram illustrating an example of an SPM information table. FIG. 4 is a flowchart illustrating a dynamic allocation method for an SRAM array according to one embodiment of the present disclosure. Specific details for implementing the invention

[0013] Some embodiments of the present disclosure are described in detail below with reference to exemplary drawings. It should be noted that in assigning reference numerals to the components of each drawing, the same components are given the same reference numeral whenever possible, even if they are shown in different drawings. Furthermore, in describing the present disclosure, if it is determined that a detailed description of related known components or functions could obscure the essence of the present disclosure, such detailed description is omitted.

[0014] In describing the components of the embodiments according to the present disclosure, symbols such as first, second, i), ii), a), b), etc., may be used. These symbols are intended only to distinguish the components from other components, and the essence, order, or sequence of the components is not limited by the symbols. When a part in the specification is described as 'comprising' or 'having' a component, this means that, unless explicitly stated otherwise, it does not exclude other components but may include additional components.

[0015] The detailed description set forth below, together with the accompanying drawings, is intended to describe exemplary embodiments of the present disclosure and is not intended to represent the only embodiment in which the present disclosure can be practiced.

[0016] FIG. 1 is a block diagram illustrating the configuration of an SRAM array dynamic allocation device (100) according to one embodiment of the present disclosure.

[0017] As illustrated in FIG. 1, the SRAM array dynamic allocation device (100) according to the present embodiment may be implemented by including an SPM request receiving unit (110), an SPM area obtaining unit (120), an access information recording unit (130), and a cache line restoring unit (140). The SRAM array dynamic allocation device (100) according to the present embodiment may be implemented by omitting some of the components of FIG. 1 or by adding other components not illustrated in FIG. 1.

[0018] An SRAM array dynamic allocation device (100) according to one embodiment of the present disclosure operates the SRAM array dynamic allocation device (100) according to the present embodiment during the operation of a first kernel (hereinafter referred to as the first kernel) that executes a program in an execution environment including an n-way set-associative cache.

[0019] The SRAM array dynamic allocation device (100) may be implemented as a component of the first kernel, but according to the embodiment, the SRAM array dynamic allocation device (100) may be implemented as a separate component from the first kernel.

[0020] In the following description, the SRAM array dynamic allocation device (100) is described as being implemented as a component separate from the first kernel and is configured to exchange necessary messages with the first kernel during operation.

[0021] Figure 2 is a diagram illustrating n cache ways that constitute an n-way set associative cache.

[0022] The n-way set association cache (200) consists of n cache ways, namely way 0 (210), way 1 (220), ..., way (n-2) (230), way (n-1) (240), and each cache way contains m cache lines (set 0, set 1, ..., set (m-1)).

[0023] Here, each cache line has a fixed capacity, for example, 64 bytes.

[0024] The SPM request receiving unit (110) receives an SPM request message from the additional SPM area securing function of the first kernel. The additional SPM area securing function of the first kernel is a function for additionally securing an SPM area required during program execution in the first kernel. Since details regarding the additional SPM area securing function are outside the scope of the present invention, a detailed description thereof is omitted.

[0025] The SPM request message may include the number of required cache lines needed for SPM. Although there may be multiple cache lines required for SPM, the following description assumes that there is only one required cache line.

[0026] In n cache ways (210, 220, 230, 240), each cache way can be pre-set to have the same maximum number of cache lines available for use as an SPM (i.e., the same capacity).

[0027] The SPM area acquisition unit (120), in accordance with the SPM request message, acquires a cache line that can be used as an SPM from among a plurality of cache lines of n cache ways (210, 220, 230, 240) constituting the n-way set association cache (200) as the first cache line.

[0028] The SPM area acquisition unit (120) acquires a first cache line from the first cache way that has the largest capacity used as an SPM area among n cache ways (210, 220, 230, 240). For example, when way n (240) has the largest capacity used as an SPM area, the SPM area acquisition unit (120) sets way n (240) as the first cache way and acquires a first cache line from the first cache way, that is, way n (240).

[0029] The SPM area acquisition unit (120) sets the acquired first cache line as the SPM area.

[0030] In the following description, unless otherwise noted, the SPM area set from the first cache line is named the first SPM line, and the SPM area obtained from one cache line is named the one SPM line.

[0031] When the SPM area acquisition unit (120) acquires a first cache line, it transmits address information corresponding to the first cache line to the SPM management function (not shown) of the first kernel to indicate that the first cache line has been allocated as the first SPM line.

[0032] Details regarding the SPM management function (not shown) are outside the scope of the present invention, so a detailed description thereof is omitted.

[0033] Figure 3 is a diagram illustrating an example of an SPM information table.

[0034] The SPM information table (300) includes SPM line information corresponding to each SPM line in use, and each SPM line information includes information such as a corresponding SPM line address field and a remaining access count field.

[0035] The SPM information table (300) is stored corresponding to each of the n cache ways (210, 220, 230, 240), and thus a total of n SPM information tables are stored.

[0036] The SPM area acquisition unit (120) can check each SPM information table (300) corresponding to n cache ways (210, 220, 230, 240) to determine how many cache lines are allocated as SPM lines for each of the n cache ways (210, 220, 230, 240).

[0037] For example, since four SPM line information is stored in the SPM information table (300), the SPM area acquisition unit (120) can know that there are four SPM lines in the cache way corresponding to the SPM information table (300).

[0038] The SPM area acquisition unit (120) checks each SPM information table (300) and sets the cache way with the largest capacity used as an SPM line (e.g., way n (240)) as the first cache way.

[0039] In this embodiment, it is assumed that the number of SPM lines for each cache way (210, 220, 230, 240) is determined by checking the SPM information table (300) for each of the n cache ways (210, 220, 230, 240), but the present invention is not limited thereto.

[0040] Additionally, the SPM area acquisition unit (120) may be implemented to determine the first cache way based on the sum of the values ​​of the remaining access count fields of the SPM line information stored in each SPM information table (300).

[0041] In other words, the SPM area acquisition unit (120) may be implemented to determine the cache way with the largest sum of the values ​​of the remaining access count fields of each SPM line information stored in the SPM information table (300) as the first cache way.

[0042] For example, if the number of SPM line information in way 0 (210) is 3, the number of SPM line information in way 1 (220) is 0, the number of SPM line information in way (n-2) (230) is 0, and the number of SPM line information in way n (240) is 4, the SPM area acquisition unit (120) compares cache ways with one or more SPM line information for each SPM information table (300).

[0043] At this time, if the values ​​of the remaining access count fields in the three SPM line information of way 0 (210) are 3, 2, and 4 respectively, the sum of the values ​​of the remaining access count fields becomes 9. Also, if the values ​​of the remaining access count fields in the four SPM line information of way n (240) are 1, 2, 1, and 1 respectively, the sum of the values ​​of the remaining access count fields becomes 5. In this case, the SPM area acquisition unit (120) can determine way 0 (210), which has the largest sum of the values ​​of the remaining access count fields of the SPM line information among way 0 (210) and way n (240), as the first cache way.

[0044] The reason the cache way with the largest sum of values ​​in the remaining access count field of the SPM line information is determined as the first cache way is that cache ways with a smaller sum of values ​​in the remaining access count field complete access to the SPM line more quickly, increasing the likelihood that the corresponding SPM line will be deleted.

[0045] When way n (240) is determined to be the first cache way, the SPM area acquisition unit (120) acquires the cache line having the largest address in the first cache way as the first cache line. That is, the SPM area acquisition unit (120) acquires the cache line corresponding to the last address among the cache lines not set as SPM lines in the first cache way as the first cache line. That is, as shown in FIG. 2, the first cache line is acquired from the last address of way n (240). By acquiring the first cache line from the last address of way n (240) in this way, fragmentation of the SPM area can be minimized.

[0046] The SPM area acquisition unit (120) stores information indicating that the first cache line is in SPM mode to set the first cache line as the first SPM line, and stores usage count information related to the first SPM line in the SPM information table (300).

[0047] The SPM area acquisition unit (120) sets a mode field in the tag area of ​​the first cache line and stores information indicating that it is an SPM mode in the mode field. For example, if the mode field is 0, it indicates that the first cache line is in cache mode, and if the mode field is 1, it indicates that the first cache line is in SPM mode.

[0048] The SPM area acquisition unit (120) generates one SPM line information corresponding to the first SPM line in the SPM information table (300), stores the address of the first cache line in the SPM line address field of the corresponding SPM line information, and stores usage count information in the remaining access count field.

[0049] Meanwhile, although the present embodiment was described assuming that the number of cache lines required for use as SPM in the SPM request message is one, if the SPM request message received by the SPM request receiving unit (110) indicates that the number of cache lines required for use as SPM is multiple (e.g., k), the SPM area acquisition unit (120) may be implemented to repeat the operation of determining the first cache way one by one k times corresponding to the number of required cache lines, or it may be implemented to determine the first cache way once according to the SPM request message and acquire k first cache lines from the determined first cache way.

[0050] In the case where k first cache lines are acquired from one cache way according to an SPM request message, the SPM area acquisition unit (120) acquires all k first cache lines that need to be used as SPM from the first cache way after determining the first cache way.

[0051] The access information recording unit (130) receives and records an access occurrence message for the first SPM line.

[0052] An access occurrence message for the first SPM line is a message indicating that the first SPM line has been accessed once. That the first SPM line has been accessed once means that the access operation has been completed after performing an access, such as reading, writing, or updating the first SPM line, once.

[0053] The access information recorder (130) receives an access occurrence message for the first SPM line from the first kernel or a program running in the first kernel.

[0054] When the access information recorder (130) receives an access occurrence message, it finds a first SPM line corresponding to the access occurrence message within the SPM information table (300), and updates the remaining access count field by decreasing the value of the remaining access count field of the corresponding first SPM line by 1.

[0055] The cache line restoration unit (140) restores the first SPM line to a cache line when it confirms that the use of the first SPM line is completed based on the access information of the first SPM line, that is, the value of the remaining access count field corresponding to the first SPM line.

[0056] The cache line restoration unit (140) restores the first SPM line to the cache area when the remaining access count information corresponding to the first SPM line in the SPM information table (300) is 0.

[0057] At this time, the cache line restoration unit (140) obtains the SPM line address field of the SPM line information corresponding to the first SPM line from the SPM information table (300), stores information indicating that it is in cache mode in the mode field of the first SPM line area corresponding to the address location corresponding to the SPM line address field, and deletes the SPM line information corresponding to the first SPM line from the SPM information table (300), thereby restoring the first SPM line to the cache area.

[0058] FIG. 4 is a flowchart illustrating a dynamic allocation method for an SRAM array according to one embodiment of the present disclosure.

[0059] A dynamic allocation method for an SRAM array according to one embodiment of the present disclosure is performed by an SRAM array dynamic allocation device (100).

[0060] The SPM request receiving unit (110) performs an SPM request receiving process to receive an SPM request message (S410).

[0061] The SPM area acquisition unit (120) performs an SPM area acquisition process according to an SPM request message, acquiring a cache line that can be used as an SPM among a plurality of cache lines of n cache ways constituting an n-way set association cache as a first cache line and setting the first cache line as a first SPM line (S420).

[0062] The access information recording unit (130) performs an access information recording process to record access information related to the access occurrence message when it receives an access occurrence message for the first SPM line (S430).

[0063] The cache line restoration unit (140) performs a cache line restoration process to restore the first SPM line to a cache line when it confirms that the use of the first SPM line is completed based on access information (S440).

[0064] Each component of the device or method according to the present invention may be implemented in hardware or software, or in a combination of hardware and software. Additionally, the function of each component may be implemented in software, and a microprocessor may be implemented to execute the function of the software corresponding to each component.

[0065] Various embodiments of the systems and techniques described herein may be realized as digital electronic circuits, integrated circuits, field programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), computer hardware, firmware, software, and / or combinations thereof. These various embodiments may include being implemented as one or more computer programs executable on a programmable system. A programmable system comprises a storage system, at least one input device, and at least one programmable processor (which may be a special-purpose processor or a general-purpose processor) coupled to receive data and instructions from and transmit data and instructions to at least one output device. Computer programs (which are also known as programs, software, software applications, or code) include instructions for the programmable processor and are stored on a "computer-readable recording medium."

[0066] Computer-readable recording media include all types of recording devices in which data that can be read by a computer system is stored. Such computer-readable recording media may be non-volatile or non-transitory media such as ROM, CD-ROM, magnetic tape, floppy disk, memory card, hard disk, magneto-optical disk, and storage device, and may also include transitory media such as data transmission media. Additionally, computer-readable recording media may be distributed across networked computer systems, and computer-readable code may be stored and executed in a distributed manner.

[0067] Although the flowcharts and timing diagrams in this specification describe each process as being executed sequentially, this is merely an illustrative explanation of the technical concept of one embodiment of the present disclosure. In other words, a person skilled in the art to which one embodiment of the present disclosure belongs may modify and adapt the flowcharts and timing diagrams in various ways, such as changing the order described in the flowcharts and timing diagrams or executing one or more of the processes in parallel, without departing from the essential characteristics of one embodiment of the present disclosure; therefore, the flowcharts and timing diagrams are not limited to a chronological order.

[0068] The above description is merely an illustrative explanation of the technical concept of the present embodiment, and a person skilled in the art to which the present embodiment belongs would be able to make various modifications and variations within the scope of the essential characteristics of the present embodiment. Accordingly, the present embodiments are intended to explain, not limit, the technical concept of the present embodiment, and the scope of the technical concept of the present embodiment is not limited by these embodiments. The scope of protection of the present embodiment shall be interpreted by the claims below, and all technical concepts within an equivalent scope shall be interpreted as being included within the scope of rights of the present embodiment. Explanation of the symbols

[0069] 100: SRAM array dynamic allocation unit 110: SPM request receiver 120: SPM Area Acquisition Unit 130: Access Information Recording Unit 140: Cache line restoration section 200: n-way set associative cache 300: SPM Information Table

Claims

Claim 1 A method for dynamic allocation of an SRAM array by an SRAM array dynamic allocation device comprising an SPM request receiving unit, an SPM area acquisition unit, an access information recording unit, and a cache line restoration unit, wherein the SPM request receiving unit receives an SPM request message in an SPM request receiving process; wherein the SPM area acquisition unit acquires a cache line usable as a SPM (scratched pad memory) among a plurality of cache lines of n cache ways constituting an n-way set-associative cache according to the SPM request message as a first cache line and sets the first cache line as a first SPM line in an SPM area acquisition process; wherein the access information recording unit records access information related to an access occurrence message when it receives an access occurrence message for the first SPM line in an access information recording process; A method for dynamic allocation of an SRAM array, wherein the cache line restoration unit includes a cache line restoration process in which the first SPM line is restored as a cache line when it is confirmed that the use of the first SPM line is completed based on the access information, and the SPM area acquisition process is characterized by acquiring the first cache line from the first cache way that has the largest capacity used as an SPM line among the n cache ways. Claim 2 A method for dynamic allocation of an SRAM array according to claim 1, wherein the SPM request reception process is characterized by receiving the SPM request message during the operation of the kernel from a kernel that executes a program in an execution environment including the n-way set associative cache. Claim 3 delete Claim 4 A method for dynamic allocation of an SRAM array according to claim 1, wherein the process of acquiring the SPM area is characterized by acquiring the cache line corresponding to the last address among the cache lines not set as SPM lines in the first cache way as the first cache line. Claim 5 A method for dynamic allocation of an SRAM array according to claim 1, wherein the process of acquiring the SPM area is characterized by storing information indicating that the first cache line is in SPM mode in a mode field included in the tag area of ​​the first cache line to set the first cache line as the first SPM line. Claim 6 A method for dynamic allocation of an SRAM array according to claim 1, wherein the process of acquiring the SPM area is characterized by storing information regarding the number of remaining accesses associated with the first SPM line in the remaining accesses field of the SPM information table. Claim 7 In claim 6, the cache line restoration process is characterized by restoring the first SPM line to a cache area when the remaining access count information of the first SPM line is 0. Claim 8 In claim 6, the cache line restoration process is characterized by restoring the first SPM line to a cache line by storing information indicating that the first SPM line is in cache mode in a mode field of an area corresponding to the address of the first SPM line. Claim 9 A computer program stored on a computer-readable recording medium to execute each process included in the SRAM array dynamic allocation method according to any one of claims 1, 2, and 4 through 8. Claim 10 An SRAM array dynamic allocation device comprising: an SPM request receiving unit for receiving an SPM request message; an SPM area acquiring unit for acquiring a cache line usable as a SPM (scratched pad memory) among a plurality of cache lines of n cache ways constituting an n-way set-associative cache according to the SPM request message and setting the first cache line as the first SPM line; an access information recording unit for recording access information related to the access occurrence message when an access occurrence message for the first SPM line is received; and a cache line restoration unit for restoring the first SPM line as a cache line when it is confirmed that the use of the first SPM line is completed based on the access information, wherein the SPM area acquiring unit acquires the first cache line from the first cache way having the largest capacity used as an SPM line among the n cache ways. Claim 11 delete Claim 12 In claim 10, the SPM area acquisition unit is characterized by storing information on the number of remaining accesses associated with the first SPM line. Claim 13 In claim 12, the cache line restoration process is characterized by restoring the first SPM line to a cache area when the remaining access count information of the first SPM line is 0.

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