Semiconductor device

Abstract

According to the concept of the present invention, a semiconductor device comprises a substrate including a logic cell region and a test region, wherein the logic cell region includes a first active region and a second active region spaced apart from each other, and the test region includes dummy regions spaced apart from each other; a first active pattern and a second active pattern provided respectively on the first and second active regions; a dummy pattern provided on each of the dummy regions; a device isolation film disposed in trenches formed between the first and second active patterns and the dummy pattern; a contact pattern provided on the dummy pattern and in contact with the dummy pattern; a first gate electrode extending in a first direction across the dummy regions; a gate contact connected to the first gate electrode; and a first metal layer on the gate contact, wherein the first metal layer includes a first test wiring connected to the contact pattern on the test region and a second test wiring connected to the gate contact, and the lowest level of the upper surface of the first active pattern may be lower than the lowest level of the upper surface of the dummy pattern.

Description

Technology Field

[0001] The present invention relates to a semiconductor device, and more specifically, to a semiconductor device including a field-effect transistor. Background Technology

[0002] Due to characteristics such as miniaturization, multifunctionality, and / or low manufacturing costs, semiconductor devices are gaining prominence as important elements in the electronics industry. Semiconductor devices can be classified into semiconductor memory devices that store logic data, semiconductor logic devices that process logic data, and hybrid semiconductor devices that include both memory and logic elements. As the electronics industry develops to a high degree, the demands for the characteristics of semiconductor devices are increasing. For example, there is a growing demand for high reliability, high speed, and / or multifunctionality of semiconductor devices. To meet these required characteristics, the structures within semiconductor devices are becoming increasingly complex, and semiconductor devices are becoming increasingly highly integrated. Relevant prior art includes U.S. Patent No. 10,177,038 (January 8, 2019) and U.S. Patent No. 8,138,497 (October 9, 2008). The problem to be solved

[0003] The problem that the present invention aims to solve is to provide a semiconductor device that facilitates defect detection. means of solving the problem

[0004] According to the concept of the present invention, a semiconductor device comprises a substrate including a logic cell region and a test region, wherein the logic cell region includes a first active region and a second active region spaced apart from each other, and the test region includes dummy regions spaced apart from each other; a first active pattern and a second active pattern provided respectively on the first and second active regions; a dummy pattern provided on each of the dummy regions; a device isolation film disposed in trenches formed between the first and second active patterns and the dummy pattern; a contact pattern provided on the dummy pattern and in contact with the dummy pattern; a first gate electrode extending in a first direction across the dummy regions; a gate contact connected to the first gate electrode; and a first metal layer on the gate contact, wherein the first metal layer includes a first test wiring connected to the contact pattern on the test region and a second test wiring connected to the gate contact, and the lowest level of the upper surface of the first active pattern may be lower than the lowest level of the upper surface of the dummy pattern.

[0005] According to another concept of the present invention, a semiconductor device comprises a substrate including a test area, wherein the test area includes dummy areas spaced apart from each other in a first direction; a dummy pattern provided on each of the dummy areas; a device isolation layer disposed in trenches formed between the dummy patterns; a gate electrode extending in the first direction across the dummy areas; a contact pattern extending in the first direction on the dummy pattern adjacent to the gate electrode; a gate contact provided on the gate electrode; and a first metal layer provided on the gate contact, wherein the first metal layer comprises: a first test wiring connected to the contact pattern and a second test wiring connected to the gate contact; and a first via between the first test wiring and the contact pattern, wherein the gate contact is vertically superimposed with the device isolation layer between the dummy areas, and the contact pattern may be in contact with the upper surface of the dummy pattern.

[0006] According to another concept of the present invention, a semiconductor device comprises a substrate including a logic cell region and a test region, wherein the logic cell region includes a first active region and a second active region spaced apart from each other, and the test region includes dummy regions spaced apart from each other; a first active pattern and a second active pattern provided respectively on the first and second active regions; a dummy pattern provided on each of the dummy regions; trenches formed between the first and second active patterns and the dummy pattern; a device isolation layer disposed within the trenches, wherein the upper portions of the first and second active patterns and the dummy pattern protrude over the device isolation layer; a first gate electrode crossing the first and second active patterns; a second gate electrode crossing the dummy pattern; a first source / drain pattern and a second source / drain pattern provided respectively on the first and second active patterns; a gate spacer provided on the sidewall of each of the first and second gate electrodes; a gate capping pattern provided on the upper surface of each of the first and second gate electrodes; and an interlayer insulating film on the gate capping pattern. An active contact penetrating the interlayer insulating film and connected to either of the first and second source / drain patterns; a contact pattern penetrating the interlayer insulating film and contacting the dummy pattern; a silicide pattern interposed between the active contact and the first and second source / drain patterns, respectively; a first gate contact connected to the first gate electrode and a second gate contact connected to the second gate electrode, penetrating the interlayer insulating film and the gate capping pattern; a first metal layer on the interlayer insulating film, the first metal layer comprising power wiring provided on the logic cell region, and first test wiring and second test wiring provided on the test region;and a second metal layer on the first metal layer, wherein the power wiring is electrically connected to the active contact, the first test wiring is electrically connected to the contact pattern, the second test wiring is electrically connected to the second gate contact, and the lowest level of the upper surface of the first active pattern may be lower than the lowest level of the upper surface of the dummy pattern.; Effects of the invention

[0007] According to the present invention, short-circuit defects can be detected in a non-destructive manner by using a voltage ramping method in which different voltages are applied to each of the first test wiring and the second test wiring to gradually increase the difference. Accordingly, the time required to detect short-circuit defects caused by voids in the device isolation film is reduced, and costs can be reduced by preventing wafer loss due to destructive analysis. As a result, defect detection in semiconductor devices can be made easier. Brief explanation of the drawing

[0008] FIG. 1 is a plan view for illustrating a semiconductor device according to embodiments of the present invention. FIGS. 2a to 2h are cross-sectional views along the lines A-A', B-B', C-C', D-D', E-E', F-F', G-G', and H-H' of FIG. 1, respectively. FIGS. 3 and FIGS. 5 are plan views for explaining a method for manufacturing a semiconductor device according to embodiments of the present invention. FIGS. 4a to 4g are cross-sectional views along the lines A-A', B-B', C-C', D-D', E-E', F-F', and G-G' of FIG. 3, respectively. FIGS. 6a to 6g are cross-sectional views along the lines A-A', B-B', C-C', D-D', E-E', F-F', and G-G' of FIG. 5, respectively. FIG. 7 is a plan view for illustrating a semiconductor device according to embodiments of the present invention. FIGS. 8a and FIGS. 8b are cross-sectional views along the lines A-A' and B-B' of FIGS. 7, respectively. FIGS. 9a to 9d are cross-sectional views along the lines A-A', B-B', D-D', and E-E' of FIG. 1, respectively, for illustrating semiconductor devices according to embodiments of the present invention. Specific details for implementing the invention

[0009] FIG. 1 is a plan view for illustrating a semiconductor device according to embodiments of the present invention. FIGS. 2a to 2h are cross-sectional views along the lines A-A', B-B', C-C', D-D', E-E', F-F', G-G', and H-H' of FIG. 1, respectively.

[0010] Referring to FIG. 1, a substrate (100) including a logic cell region (LCR) and a test region (TSR) may be provided. The substrate (100) may be a semiconductor substrate including silicon, germanium, silicon-germanium, etc., or a compound semiconductor substrate. In one example, the substrate (100) may be a silicon substrate. The logic cell region (LCR) may be an area where standard cells constituting a logic circuit are placed. In one example, the test region (TSR) may be an area on the substrate (100) where standard cells constituting a logic circuit are not placed. In another example, the test region (TSR) may be an area where a scribe line is formed. Hereinafter, the logic cell region (LCR) will first be described in detail with reference to FIG. 1 and FIG. 2a to 2e.

[0011] Referring to FIGS. 1 and FIGS. 2a through 2e, a first logic cell (LC1) and a second logic cell (LC2) may be provided on a logic cell region (LCR) of a substrate (100). Logic transistors constituting a logic circuit may be disposed on each of the first and second logic cells (LC1, LC2).

[0012] The substrate (100) may have active regions (PR1, PR2, NR1, NR2) on a logic cell region (LCR). The active regions (PR1, PR2, NR1, NR2) may include a first PMOSFET region (PR1), a second PMOSFET region (PR2), a first NMOSFET region (NR1), and a second NMOSFET region (NR2). Each of the first PMOSFET region (PR1), the second PMOSFET region (PR2), the first NMOSFET region (NR1), and the second NMOSFET region (NR2) may extend in a second direction (D2).

[0013] A first PMOSFET region (PR1), a second PMOSFET region (PR2), a first NMOSFET region (NR1), and a second NMOSFET region (NR2) can be defined by a second trench (TR2) formed on the upper surface of the substrate (100). For example, the second trench (TR2) may be located between the first NMOSFET region (NR1) and the first PMOSFET region (PR1). The second trench (TR2) may be located between the second PMOSFET region (PR2) and the second NMOSFET region (NR2). The second trench (TR2) may be located between the first PMOSFET region (PR1) and the second PMOSFET region (PR2).

[0014] A first PMOSFET region (PR1), a second PMOSFET region (PR2), a first NMOSFET region (NR1), and a second NMOSFET region (NR2) can be defined by a second trench (TR2) formed on the upper surface of the substrate (100). For example, the second trench (TR2) may be located between the first NMOSFET region (NR1) and the first PMOSFET region (PR1). The second trench (TR2) may be located between the first PMOSFET region (PR1) and the second PMOSFET region (PR2). The second trench (TR2) may be located between the second PMOSFET region (PR2) and the second NMOSFET region (NR2).

[0015] First active patterns (AP1) may be provided on each of the first and second PMOSFET regions (PR1, PR2). Second active patterns (AP2) may be provided on each of the first and second NMOSFET regions (NR1, NR2).

[0016] The first and second active patterns (AP1, AP2) may extend parallel to each other in a second direction (D2). The first and second active patterns (AP1, AP2) may be parts of the substrate (100) that protrude vertically. A first trench (TR1) may be defined between adjacent first active patterns (AP1) and between adjacent second active patterns (AP2). The first trench (TR1) may be shallower than the second trench (TR2). The second trench (TR2) may be a deep trench.

[0017] A device isolation layer (ST) can fill the first and second trenches (TR1, TR2). The device isolation layer (ST) may include a silicon oxide film. The upper portion of each of the first and second active patterns (AP1, AP2) may protrude vertically over the device isolation layer (ST) (see FIG. 2e). The upper portion of each of the first and second active patterns (AP1, AP2) may have a fin shape. The device isolation layer (ST) may not cover the upper portion of each of the first and second active patterns (AP1, AP2). The device isolation layer (ST) may cover the lower sidewall of each of the first and second active patterns (AP1, AP2).

[0018] First source / drain patterns (SD1) may be provided on each of the first and second PMOSFET regions (PR1, PR2). First source / drain patterns (SD1) may be provided on each of the first active patterns (AP1). The first source / drain patterns (SD1) may be impurity regions of a first conductivity type (e.g., p-type). A first channel pattern (CH1) may be interposed between a pair of first source / drain patterns (SD1) adjacent in a second direction (D2).

[0019] Second source / drain patterns (SD2) may be provided on each of the first and second NMOSFET regions (NR1, NR2). Second source / drain patterns (SD2) may be provided on each of the second active patterns (AP2). The second source / drain patterns (SD2) may be impurity regions of a second conductivity type (e.g., n-type). A second channel pattern (CH2) may be interposed between a pair of second source / drain patterns (SD2) adjacent in the second direction (D2).

[0020] The first and second source / drain patterns (SD1, SD2) may be epitaxial patterns formed by an optional epitaxial growth process. For example, the upper surfaces of the first and second source / drain patterns (SD1, SD2) may co-plane with the upper surfaces of the first and second channel patterns (CH1, CH2). For another example, the upper surfaces of the first and second source / drain patterns (SD1, SD2) may be higher than the upper surfaces of the first and second channel patterns (CH1, CH2).

[0021] The first source / drain pattern (SD1) may include a semiconductor element (e.g., SiGe) having a lattice constant greater than that of the semiconductor element of the substrate (100). Thus, a pair of first source / drain patterns (SD1) can provide compressive stress to the first channel pattern (CH1) between them. As an example, the second source / drain pattern (SD2) may include the same semiconductor element (e.g., Si) as the substrate (100).

[0022] First gate electrodes (GE1) may be provided extending in a first direction (D1) across the first and second active patterns (AP1, AP2). The first gate electrodes (GE1) may be arranged along a second direction (D2) with a first pitch. The first gate electrodes (GE1) may be vertically overlapped with the first and second channel patterns (CH1, CH2). Each of the first gate electrodes (GE1) may surround the top surface and both side walls of each of the first and second channel patterns (CH1, CH2).

[0023] Referring again to FIG. 2e, the first gate electrode (GE1) may be provided on the first upper surface (TS1) of the first channel pattern (CH1) and on at least one first sidewall (SW1) of the first channel pattern (CH1). The first gate electrode (GE1) may be provided on the second upper surface (TS2) of the second channel pattern (CH2) and on at least one second sidewall (SW2) of the second channel pattern (CH2). In other words, the transistor according to the present embodiment may be a three-dimensional field-effect transistor (e.g., FinFET) in which the first gate electrode (GE1) surrounds the channels (CH1, CH2) in three dimensions.

[0024] Typically, the first logic cell (LC1) may have a first boundary (BD1) and a second boundary (BD2) facing each other in the second direction (D2). The first and second boundaries (BD1, BD2) may extend in the first direction (D1). The first logic cell (LC1) may have a third boundary (BD3) and a fourth boundary (BD4) facing each other in the first direction (D1). The third and fourth boundaries (BD3, BD4) may extend in the second direction (D2).

[0025] Gate cutting patterns (CT) may be placed on the third and fourth boundaries (BD3, BD4) of the first logic cell (LC1). Gate cutting patterns (CT) may be placed on the boundary toward the first direction (D1) of each of the first and second logic cells (LC1, LC2). Gate cutting patterns (CT) may be arranged along the third boundary (BD3) at the first pitch. Gate cutting patterns (CT) may be arranged along the fourth boundary (BD4) at the first pitch. In a planar view, the gate cutting patterns (CT) on the third and fourth boundaries (BD3, BD4) may be placed so as to overlap each of the first gate electrodes (GE1). The gate cutting patterns (CT) may include an insulating material such as a silicon oxide film or a silicon nitride film.

[0026] A first gate electrode (GE1) on a first logic cell (LC1) can be separated from a first gate electrode (GE1) on a second logic cell (LC2) by a gate cutting pattern (CT). A gate cutting pattern (CT) may be interposed between the first gate electrode (GE1) on the first logic cell (LC1) and the first gate electrode (GE1) on the second logic cell (LC2) aligned with it in a first direction (D1). In other words, a first gate electrode (GE1) extending in the first direction (D1) can be separated into a plurality of first gate electrodes (GE1) by gate cutting patterns (CT).

[0027] A pair of gate spacers (GS) may be disposed on both sidewalls of each of the first gate electrodes (GE1). The gate spacers (GS) may extend along the first gate electrodes (GE1) in a first direction (D1). The upper surfaces of the gate spacers (GS) may be higher than the upper surfaces of the first gate electrodes (GE1). The upper surfaces of the gate spacers (GS) may co-plane with the upper surface of the first interlayer insulating film (110) to be described later. The gate spacers (GS) may include at least one of SiCN, SiCON, and SiN. As another example, the gate spacers (GS) may include a multi-layer composed of at least two of SiCN, SiCON, and SiN.

[0028] A gate dielectric pattern (GI) may be interposed between the first gate electrode (GE1) and the first active pattern (AP1), and between the first gate electrode (GE1) and the second active pattern (AP2). The gate dielectric pattern (GI) may extend along the bottom surface of the first gate electrode (GE1) above it. For example, the gate dielectric pattern (GI) may cover the first upper surface (TS1) and the first sidewall (SW1) of the first channel pattern (CH1). The gate dielectric pattern (GI) may cover the second upper surface (TS2) and the second sidewall (SW2) of the second channel pattern (CH2). The gate dielectric pattern (GI) may cover the upper surface of the device isolation film (ST) below the first gate electrode (GE1) (see FIG. 2e).

[0029] In one embodiment of the present invention, the gate dielectric pattern (GI) may include a high dielectric constant material having a dielectric constant higher than that of a silicon oxide film. As an example, the high dielectric constant material may include at least one of hafnium oxide, hafnium silicon oxide, hafnium zirconium oxide, hafnium tantalum oxide, lanthanum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, lithium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate.

[0030] In another embodiment, the semiconductor device of the present invention may include a negative capacitance (NC) FET using a negative capacitor. For example, the gate dielectric pattern (GI) may include a ferroelectric material film having ferroelectric properties and a paraelectric material film having paraelectric properties.

[0031] Ferroelectric material films can have negative capacitance. Paraelectric material films can have positive capacitance. For example, if two or more capacitors are connected in series and the capacitance of each capacitor is positive, the total capacitance decreases compared to the capacitance of each individual capacitor. Conversely, if at least one of the capacitances of the two or more capacitors connected in series has a negative value, the total capacitance can have a positive value and be greater than the absolute value of each individual capacitance.

[0032] When a ferroelectric material film with negative capacitance and a paraelectric material film with positive capacitance are connected in series, the total capacitance value of the series-connected ferroelectric material film and paraelectric material film can increase. By utilizing the increase in the total capacitance value, a transistor containing a ferroelectric material film can have a subthreshold swing (SS) of less than 60 mV / decade at room temperature.

[0033] Ferroelectric material films may have ferroelectric properties. Ferroelectric material films may include, for example, at least one of hafnium oxide, hafnium zirconium oxide, barium strontium titanium oxide, barium titanium oxide, and lead zirconium titanium oxide. Here, as an example, hafnium zirconium oxide may be a material in which zirconium (Zr) is doped into hafnium oxide. As another example, hafnium zirconium oxide may be a compound of hafnium (Hf), zirconium (Zr), and oxygen (O).

[0034] The ferroelectric material film may further include a doped dopant. For example, the dopant may include at least one of aluminum (Al), titanium (Ti), niobium (Nb), lanthanum (La), yttrium (Y), magnesium (Mg), silicon (Si), calcium (Ca), cerium (Ce), dysprosium (Dy), erbium (Er), gadolinium (Gd), germanium (Ge), scandium (Sc), strontium (Sr), and tin (Sn). Depending on which ferroelectric material the ferroelectric material film contains, the type of dopant included in the ferroelectric material film may vary.

[0035] When the ferroelectric material film contains hafnium oxide, the dopant included in the ferroelectric material film may include, for example, at least one of gadolinium (Gd), silicon (Si), zirconium (Zr), aluminum (Al), and yttrium (Y).

[0036] When the dopant is aluminum (Al), the ferroelectric material film may contain 3 to 8 at% (atomic %) of aluminum. Here, the ratio of the dopant may be the ratio of aluminum to the sum of hafnium and aluminum.

[0037] When the dopant is silicon (Si), the ferroelectric material film may contain 2 to 10 at% silicon. When the dopant is yttrium (Y), the ferroelectric material film may contain 2 to 10 at% yttrium. When the dopant is gadolinium (Gd), the ferroelectric material film may contain 1 to 7 at% gadolinium. When the dopant is zirconium (Zr), the ferroelectric material film may contain 50 to 80 at% zirconium.

[0038] The paraelectric material film may have paraelectric properties. The paraelectric material film may include, for example, at least one of silicon oxide and a metal oxide having a high dielectric constant. The metal oxide included in the paraelectric material film may include, for example, at least one of hafnium oxide, zirconium oxide, and aluminum oxide, but is not limited thereto.

[0039] Ferroelectric and paraelectric film layers may contain the same material. Ferroelectric film layers possess ferroelectric properties, whereas paraelectric film layers may not. For example, if both ferroelectric and paraelectric film layers contain hafnium oxide, the crystal structure of the hafnium oxide contained in the ferroelectric film layer is different from the crystal structure of the hafnium oxide contained in the paraelectric film layer.

[0040] The ferroelectric material film may have a thickness that exhibits ferroelectric properties. The thickness of the ferroelectric material film may be, for example, 0.5 to 10 nm, but is not limited thereto. Since the critical thickness at which ferroelectric properties are exhibited may vary for each ferroelectric material, the thickness of the ferroelectric material film may vary depending on the ferroelectric material.

[0041] For example, the gate dielectric pattern (GI) may include a single ferroelectric material film. For another example, the gate dielectric pattern (GI) may include a plurality of ferroelectric material films spaced apart from each other. The gate dielectric pattern (GI) may have a stacked film structure in which a plurality of ferroelectric material films and a plurality of paraelectric material films are alternately stacked.

[0042] The first gate electrode (GE1) may include a first metal pattern and a second metal pattern on the first metal pattern. The first metal pattern may be provided on the gate dielectric pattern (GI) and adjacent to the first and second channel patterns (CH1, CH2). The first metal pattern may include a work function metal that controls the threshold voltage of the transistor. A desired threshold voltage can be achieved by controlling the thickness and composition of the first metal pattern.

[0043] The first metal pattern may include a metal nitride film. For example, the first metal pattern may include at least one metal selected from the group consisting of titanium (Ti), tantalum (Ta), aluminum (Al), tungsten (W), and molybdenum (Mo), and nitrogen (N). The first metal pattern may further include carbon (C). The first metal pattern may include a plurality of stacked work function metal films.

[0044] The second metal pattern may include a metal having lower resistance than the first metal pattern. For example, the second metal pattern may include at least one metal selected from the group consisting of tungsten (W), aluminum (Al), titanium (Ti), and tantalum (Ta).

[0045] A first interlayer insulating film (110) may be provided on a substrate (100). The first interlayer insulating film (110) may cover gate spacers (GS) and first and second source / drain patterns (SD1, SD2). The upper surface of the first interlayer insulating film (110) may substantially co-plane with the upper surfaces of gate capping patterns (GP) and the upper surfaces of gate spacers (GS). A second interlayer insulating film (120) covering the gate capping patterns (GP) may be provided on the first interlayer insulating film (110). A third interlayer insulating film (130) may be provided on the second interlayer insulating film (120). A fourth interlayer insulating film (140) may be provided on the third interlayer insulating film (130). For example, the first to fourth interlayer insulating films (110-140) may include a silicon oxide film.

[0046] A pair of separation structures (DB) facing each other in a second direction (D2) may be provided on both sides of each of the first and second logic cells (LC1, LC2). For example, a pair of separation structures (DB) may be provided on the first and second boundaries (BD1, BD2) of the first logic cell (LC1), respectively. The separation structure (DB) may extend parallel to the first gate electrodes (GE1) in a first direction (D1). The pitch between the separation structure (DB) and the adjacent first gate electrode (GE1) may be the same as the first pitch.

[0047] The isolation structure (DB) can penetrate the first and second interlayer insulating films (110, 120) and extend into the first and second active patterns (AP1, AP2). The isolation structure (DB) can penetrate the top of each of the first and second active patterns (AP1, AP2). The isolation structure (DB) can electrically isolate the active region of each of the first and second logic cells (LC1, LC2) from the active region of an adjacent cell.

[0048] Active contacts (AC) may be provided that are electrically connected to the first and second source / drain patterns (SD1, SD2), respectively, by penetrating the first and second interlayer insulating films (110, 120). Each active contact (AC) may be provided between a pair of first gate electrodes (GE1). In a planar view, each active contact (AC) may have a bar shape or a line shape extending in a first direction (D1).

[0049] The active contact (AC) may be a self-aligned contact. In other words, the active contact (AC) may be formed self-aligned using the gate capping pattern (GP) and the gate spacer (GS). For example, the active contact (AC) may cover at least a portion of the sidewall of the gate spacer (GS). Although not illustrated, the active contact (AC) may cover a portion of the top surface of the gate capping pattern (GP).

[0050] Silicide patterns (SC) may be interposed between active contacts (AC) and first and second source / drain patterns (SD1, SD2), respectively. The active contacts (AC) may be electrically connected to the first and second source / drain patterns (SD1, SD2), respectively, through the silicide patterns (SC). The silicide pattern (SC) may include metal-silicide, and may include, for example, at least one of titanium-silicide, tantalum-silicide, tungsten-silicide, nickel-silicide, and cobalt-silicide.

[0051] The active contacts (AC) may include a first active contact (AC1), a second active contact (AC2), and a third active contact (AC3). The first active contact (AC1) on the first logic cell (LC1) may electrically connect the first source / drain pattern (SD1) of the first PMOSFET region (PR1) and the second source / drain pattern (SD2) of the first NMOSFET region (NR1) to each other. The first active contact (AC1) may extend in a first direction (D1) from the second source / drain pattern (SD2) of the first NMOSFET region (NR1) to the first source / drain pattern (SD1) of the first PMOSFET region (PR1).

[0052] The second active contact (AC2) can electrically connect the first source / drain pattern (SD1) of the first PMOSFET region (PR1) and the first source / drain pattern (SD1) of the second PMOSFET region (PR2) to each other. The second active contact (AC2) can extend in a first direction (D1) from the first source / drain pattern (SD1) of the first PMOSFET region (PR1) to the first source / drain pattern (SD1) of the second PMOSFET region (PR2). The second active contact (AC2) crosses the boundary (e.g., a third boundary (BD3)) between the first and second logic cells (LC1, LC2) and can be commonly connected to the first PMOSFET region (PR1) of the first logic cell (LC1) and the second PMOSFET region (PR2) of the second logic cell (LC2).

[0053] A third active contact (AC3) on the second logic cell (LC2) may be provided only on the first source / drain pattern (SD1) of the second PMOSFET region (PR2) or the second source / drain pattern (SD2) of the second NMOSFET region (NR2). Unlike the first and second active contacts (AC1, AC2) mentioned above, the third active contact (AC3) is limited to only one active region and may not connect adjacent active regions to each other.

[0054] From a planar perspective, the length of the third active contact (AC3) in the first direction (D1) may be shorter than the length of each of the first and second active contacts (AC1, AC2) in the first direction (D1). For example, the length of the third active contact (AC3) may be less than half the length of each of the first and second active contacts (AC1, AC2).

[0055] Gate contacts (GC) that are electrically connected to the first gate electrodes (GE1) through the second interlayer insulating film (120) and the gate capping pattern (GP) may be provided. In a planar view, the gate contacts (GC) on the first logic cell (LC1) may be arranged to overlap vertically with the first PMOSFET region (PR1). In other words, the gate contacts (GC) on the first logic cell (LC1) may be provided on the first active pattern (AP1) (see FIG. 1).

[0056] Meanwhile, the gate contact (GC) can be freely placed on the first gate electrode (GE1) without positional restrictions. For example, the gate contacts (GC) on the second logic cell (LC2) can be placed on the device isolation film (ST) filling the second PMOSFET region (PR2) and the second trench (TR2), respectively. Although not illustrated, the gate contacts (GC) on the second logic cell (LC2) can be placed on the second NMOSFET region (NR2).

[0057] Referring again to FIGS. 2a, 2c, and 2d, the upper surface of each active contact (AC) adjacent to the gate contact (GC) can be filled with an upper insulating pattern (UIP). The bottom surface of the upper insulating pattern (UIP) may be lower than the bottom surface of the gate contact (GC). In other words, the upper surface of the active contact (AC) adjacent to the gate contact (GC) may be lower than the bottom surface of the gate contact (GC) by the upper insulating pattern (UIP) (see FIG. 2a). This prevents the problem of a short circuit occurring when the gate contact (GC) comes into contact with the active contact (AC) adjacent to it.

[0058] Each of the active contact (AC) and the gate contact (GC) may include a conductive pattern (FM) and a barrier pattern (BM) surrounding the conductive pattern (FM). For example, the conductive pattern (FM) may include at least one metal selected from aluminum, copper, tungsten, molybdenum, and cobalt. The barrier pattern (BM) may cover the sidewalls and bottom surface of the conductive pattern (FM). The barrier pattern (BM) may include a metal film / metal nitride film. The metal film may include at least one selected from titanium, tantalum, tungsten, nickel, cobalt, and platinum. The metal nitride film may include at least one selected from titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), nickel nitride (NiN), cobalt nitride (CoN), and platinum nitride (PtN).

[0059] A first metal layer (M1) may be provided within the third interlayer insulating film (130). For example, the first metal layer (M1) may include a first power wiring (M1_R1), a second power wiring (M1_R2), a third power wiring (M1_R3), and first wirings (M1_I). Each of the wirings (M1_R1, M1_R2, M1_R3, M1_I) of the first metal layer (M1) may extend parallel to each other in a second direction (D2).

[0060] Specifically, the first and second power lines (M1_R1, M1_R2) may be provided on the third and fourth boundaries (BD3, BD4) of the first logic cell (LC1), respectively. The first power line (M1_R1) may extend in a second direction (D2) along the third boundary (BD3). The second power line (M1_R2) may extend in a second direction (D2) along the fourth boundary (BD4).

[0061] The first wires (M1_I) of the first metal layer (M1) may be arranged along the first direction (D1) at a second pitch. The second pitch may be smaller than the first pitch. The line width of each of the first wires (M1_I) may be smaller than the line width of each of the first to third power wires (M1_R1, M1_R2, M1_R3).

[0062] The first power wiring (M1_R1) may be a path where a drain voltage (VDD), for example, a power voltage is provided. The second power wiring (M1_R2) may be a path where a source voltage (VSS), for example, a ground voltage is provided. The first power wiring (M1_R1) may be placed between the second power wiring (M1_R2) and the third power wiring (M1_R3). The third power wiring (M1_R3) may be a path where a source voltage (VSS), for example, a ground voltage is provided.

[0063] The first NMOSFET region (NR1) may be adjacent to the second power line (M1_R2). The second NMOSFET region (NR2) may be adjacent to the third power line (M1_R3). The first and second PMOSFET regions (PR1, PR2) may be adjacent to the first power line (M1_R1). In a planar view, the first power line (M1_R1) may be positioned between the first and second PMOSFET regions (PR1, PR2).

[0064] The first metal layer (M1) may further include first vias (VI1). The first vias (VI1) may each be provided under the wirings (M1_R1, M1_R2, M1_R3, M1_I) of the first metal layer (M1). Through the first vias (VI1), the active contact (AC) and the wiring of the first metal layer (M1) may be electrically connected to each other. Through the first vias (VI1), the gate contact (GC) and the wiring of the first metal layer (M1) may be electrically connected to each other.

[0065] The wiring of the first metal layer (M1) and the first via (VI1) below it can each be formed by a separate process. In other words, the wiring of the first metal layer (M1) and the first via (VI1) can each be formed by a single damascene process. The semiconductor device according to the present embodiment may be formed using a process of less than 20 nm.

[0066] A second metal layer (M2) may be provided within the fourth interlayer insulating film (140). The second metal layer (M2) may include a plurality of second wires (M2_I). Each of the second wires (M2_I) of the second metal layer (M2) may have a line shape or a bar shape extending in a first direction (D1). In other words, the second wires (M2_I) may extend parallel to each other in the first direction (D1).

[0067] The second metal layer (M2) may further include second vias (VI2) provided below each of the second wirings (M2_I). Through the second vias (VI2), the wiring of the first metal layer (M1) and the wiring of the second metal layer (M2) can be electrically connected to each other. The wiring of the second metal layer (M2) and the second vias (VI2) below it can be formed together by a dual damascene process.

[0068] The wiring of the first metal layer (M1) and the wiring of the second metal layer (M2) may include the same or different conductive materials. For example, the wiring of the first metal layer (M1) and the wiring of the second metal layer (M2) may include at least one metal material selected from aluminum, copper, tungsten, molybdenum, and cobalt. Although not illustrated, metal layers (e.g., M3, M4, M5…) stacked on the fourth interlayer insulating film (140) may be additionally disposed. Each of the stacked metal layers may include wiring for routing between cells.

[0069] With reference again to FIG. 2c and FIG. 2d, the active contact (AC) of the present invention will be described in more detail. The first active contact (AC1) may include a first body portion (BP1) on a first source / drain pattern (SD1) and a second body portion (BP2) on a second source / drain pattern (SD2). The first body portion (BP1) of the first active contact (AC1) may be connected to the upper surface of the first source / drain pattern (SD1) through a silicide pattern (SC), and the second body portion (BP2) of the first active contact (AC1) may be connected to the upper surface of the second source / drain pattern (SD2) through a silicide pattern (SC). The second active contact (AC2) may include a first body portion (BP1) on the first source / drain pattern (SD1) of the second logic cell (LC2) and a second body portion (BP2) on the first source / drain pattern (SD1) of the first logic cell (LC1). Each of the first body portion (BP1) and the second body portion (BP2) of the second active contact (AC2) may be connected to the upper surface of the first source / drain pattern (SD1) through a silicide pattern (SC).

[0070] Each of the first active contact (AC1) and the second active contact (AC2) may include a protrusion (PT) between the first body portion (BP1) and the second body portion (BP2). The protrusion (PT) of the first active contact (AC1) may be provided on the device isolation layer (ST) between the first PMOSFET region (PR1) and the first NMOSFET region (NR1). The protrusion (PT) of the second active contact (AC2) may be provided on the device isolation layer (ST) between the first PMOSFET region (PR1) and the second PMOSFET region (PR2). The protrusion (PT) may be a portion that protrudes toward the device isolation layer (ST). For example, the protrusion (PT) of the first active contact (AC1) may be in contact with the device isolation layer (ST) between the first PMOSFET region (PR1) and the first NMOSFET region (NR1). The protrusion (PT) of the second active contact (AC2) can contact the device isolation film (ST) between the first PMOSFET region (PR1) and the second PMOSFET region (PR2).

[0071] The protrusion (PT) may extend along the inclined sidewall of the first source / drain pattern (SD1) or the second source / drain pattern (SD2) toward the device isolation layer (ST). The bottom surface (BS3) of the protrusion (PT) may be lower than the bottom surface (BS1) of the first body part (BP1) and the bottom surface (BS2) of the second body part (BP2). The bottom surface (BS3) of the protrusion (PT) may come into contact with the device isolation layer (ST). As another example, the bottom surface (BS3) of the protrusion (PT) may be spaced apart from the device isolation layer (ST).

[0072] The first active contact (AC1) and the second active contact (AC2) can be connected to the inclined sidewall of the first source / drain pattern (SD1) or the second source / drain pattern (SD2) through a protrusion (PT). In other words, the protrusion (PT) can increase the contact area between the active contact (AC) and the source / drain patterns (SD1, SD2). Thus, the resistance between the active contact (AC) and the source / drain patterns (SD1, SD2) can be reduced.

[0073] The upper surface of the device isolation layer (ST) may include a recess region (RSR) that is recessed toward either of the second trenches (TR2). The recess region (RSR) may be formed only on the logic cell region (LCR) where the first and second source / drain patterns (SD1, SD2) are formed. Each of the protrusions (PT) of the first active contact (AC1) and the protrusions (PT) of the second active contact (AC2) may extend into the recess region (RSR).

[0074] The device isolation layer (ST) may include a void (VD) extending vertically into any one of the second trenches (TR2). In a planar view, the void (VD) may extend in a second direction (D2). The void (VD) may be an empty space extending from the upper surface of the device isolation layer (ST) toward the bottom surface of the second trench (TR2). The void (VD) may be provided within the second trench (TR2). The void (VD) may be formed by the device isolation layer (ST) failing to completely fill the second trench (TR2), which is a deep trench. As another example, the void (VD) may not be provided within the second trench (TR2) (see FIG. 1).

[0075] A filled pattern (FP) may be provided within the void (VD). The filled pattern (FP) may completely fill the void (VD). As another example, the filled pattern (FP) may partially fill the void (VD). As will be described later, the filled pattern (FP) may be formed by a metallic material filling the void (VD) during the process of forming the first gate electrode (GE1) or active contacts (AC).

[0076] The buried pattern (FP) may include a metallic material. For example, the buried pattern (FP) may include a metal nitride film. For example, the buried pattern (FP) may include at least one metal selected from the group consisting of titanium (Ti), tantalum (Ta), aluminum (Al), tungsten (W), and molybdenum (Mo), and nitrogen (N). The buried pattern (FP) may further include carbon (C). As another example, the buried pattern (FP) may include at least one metal selected from the group consisting of tungsten (W), aluminum (Al), titanium (Ti), and tantalum (Ta).

[0077] A portion of the first gate electrode (GE1) may extend into the void (VD). The buried pattern (FP) may include a portion of the first gate electrode (GE1). Although not illustrated, a portion of the gate dielectric pattern (GI) may extend into the void (VD). As another example, the buried pattern (FP) may include the same material as the barrier pattern (BM) or the conductive pattern (FM). The protrusion (PT) of the first active contact (AC1) may come into contact with the buried pattern (FP). In this case, a short circuit may occur between the first active contact (AC1) and the adjacent first gate electrode (GE1) due to the buried pattern (FP). Whether a short circuit defect occurs may be determined by the width of the void (VD) in the second direction (D2), the distance between the active contact (AC) and the adjacent first gate electrode (GE1), the presence or absence of the buried pattern (FP), etc. As another example, the protrusion (PT) of the first active contact (AC1) can be spaced apart from the buried pattern (FP).

[0078] Hereinafter, the test area (TSR) will be described in detail with reference to FIGS. 1 and FIGS. 2f through 2h. With reference to FIGS. 1 and FIGS. 2f through 2h, the substrate (100) may have dummy areas (DR) on the test area (TSR). The dummy areas (DR) may be defined by a second trench (TR2) formed on the upper part of the substrate (100). Each of the dummy areas (DR) may be spaced apart from each other in a first direction (D1). A second trench (TR2) may be located between dummy areas (DR) that are adjacent to each other in the first direction (D1). Each of the dummy areas (DR) may extend in a second direction (D2).

[0079] Dummy patterns (DP) may be provided on each dummy region (DR). The dummy patterns (DP) may extend parallel to each other in a second direction (D2). The dummy patterns (DP) may be parts of the substrate (100) that protrude vertically. A first trench (TR1) may be defined between adjacent dummy patterns (DP). The first trench (TR1) may be shallower than the second trench (TR2). Unlike the first and second active patterns (AP1, AP2), the first and second source / drain patterns (SD1, SD2) may not be formed on the dummy patterns (DP). Since the first and second source / drain patterns (SD1, SD2) are not formed on the test region (TSR), a short circuit between the first and second source / drain patterns (SD1, SD2) and the adjacent second gate electrode (GE2) can be prevented. By doing so, it is possible to prevent errors from occurring when detecting short circuit defects, which will be described later.

[0080] The device isolation layer (ST) can fill the first and second trenches (TR1, TR2). The top of each dummy pattern (DP) can protrude vertically over the device isolation layer (ST) (see FIG. 2h). The top of each dummy pattern (DP) can have a fin shape. The device isolation layer (ST) may not cover the top of each dummy pattern (DP). The device isolation layer (ST) can cover the bottom sidewall of each dummy pattern (DP).

[0081] Second gate electrodes (GE2) may be provided extending in a first direction (D1) across dummy patterns (DP). The second gate electrodes (GE2) may be arranged along the second direction (D2). Referring again to FIG. 2h, the second gate electrodes (GE2) may be provided on the top surface (TS) of the dummy pattern (DP) and on at least one sidewall (SW) of the dummy pattern (DP). Unlike the logic cell region (LCR), a gate cutting pattern (CT) may not be provided on the test region (TSR). The second gate electrodes (GE2) may extend in a first direction (D1) across a plurality of dummy regions (DR) (see FIG. 1). The second gate electrodes (GE2) may have substantially the same structure as the first gate electrode (GE1).

[0082] A pair of gate spacers (GS) may be disposed on both sidewalls of each of the second gate electrodes (GE2). The gate spacers (GS) may extend along the second gate electrodes (GE2) in a first direction (D1). A gate capping pattern (GP) may be provided on each of the second gate electrodes (GE2). The gate capping pattern (GP) may extend along the second gate electrode (GE2) in a first direction (D1). A gate dielectric pattern (GI) may be interposed between the second gate electrode (GE2) and the dummy pattern (DP).

[0083] Contact patterns (CP) that penetrate the first and second interlayer insulating films (110, 120) and contact the dummy patterns (DP) may be provided. Each of the contact patterns (CP) may contact the upper surface of the dummy patterns (DP). Each contact pattern (CP) may be provided between a pair of second gate electrodes (GE2). In a planar view, each contact pattern (CP) may have a bar shape or a line shape extending in a first direction (D1).

[0084] The contact pattern (CP) may be a self-aligned contact. In other words, the contact pattern (CP) may be formed self-aligned using the gate capping pattern (GP) and the gate spacer (GS). For example, the contact pattern (CP) may cover at least a portion of the sidewall of the gate spacer (GS). Although not illustrated, the contact pattern (CP) may cover a portion of the top surface of the gate capping pattern (GP).

[0085] The contact pattern (CP) may extend in a first direction (D1) across a plurality of dummy regions (DR). The contact pattern (CP) may include body portions (BP) provided on the dummy patterns (DP) and a protrusion (PT) between the body portions (BP). The protrusion (PT) may be a portion that protrudes toward one of the second trenches (TR2) between adjacent dummy regions (DR).

[0086] A gate contact (GC) may be provided that penetrates the second interlayer insulating film (120) and the gate capping pattern (GP) and is electrically connected to any one of the second gate electrodes (GE2). The gate contact (GC) on the test area (TSR) may be vertically superimposed with the device isolation film (ST) between the dummy areas (DR) in a planar view. Each of the contact pattern (CP) and the gate contact (GC) may include a conduction pattern (FM) and a barrier pattern (BM) surrounding the conduction pattern (FM).

[0087] Referring again to FIG. 2f and FIG. 2g, the upper portion of each of the contact patterns (CP) adjacent to the second gate electrode (GE2) can be filled with an upper insulating pattern (UIP). This prevents the problem of a short circuit occurring when a contact pattern (CP) comes into contact with the adjacent second gate electrode (GE2).

[0088] The first metal layer (M1) may include a first test wire (M1_T1) and a second test wire (M1_T2) on a test area (TSR). Each of the first test wire (M1_T1) and the second test wire (M1_T2) may extend in a second direction (D2) parallel to each other. The second test wire (M1_T2) may be connected to a gate contact (GC) on the test area (TSR). The first test wire (M1_T1) may be connected to a contact pattern (CP) adjacent to a second gate electrode (GE2) that is electrically connected to the gate contact (GC).

[0089] The upper surface of the device isolation film (ST) on the test area (TSR) may have a flat profile. That is, on the test area (TSR), a recess area (RSR) in the logic cell area (LCR) may not be formed on the upper surface of the device isolation film (ST).

[0090] The device isolation layer (ST) may include a void (VD) extending vertically into any one of the second trenches (TR2). In a planar view, the void (VD) may extend in a second direction (D2). The void (VD) may be an empty space extending from the upper surface of the device isolation layer (ST) toward the bottom surface of the second trench (TR2). The void (VD) may be provided within the second trench (TR2). Unlike what is illustrated, the void (VD) may not be provided within the second trench (TR2) (see FIG. 1).

[0091] A filled pattern (FP) may be provided within the void (VD). The filled pattern (FP) may completely fill the void (VD). As another example, the filled pattern (FP) may partially fill the void (VD). As will be described later, the filled pattern (FP) may be formed by a metallic material filling the void (VD) during the process of forming the second gate electrode (GE2) or contact patterns (CP).

[0092] The buried pattern (FP) may include a metallic material. For example, the buried pattern (FP) may include a metal nitride film. For example, the buried pattern (FP) may include at least one metal selected from the group consisting of titanium (Ti), tantalum (Ta), aluminum (Al), tungsten (W), and molybdenum (Mo), and nitrogen (N). The buried pattern (FP) may further include carbon (C). As another example, the buried pattern (FP) may include at least one metal selected from the group consisting of tungsten (W), aluminum (Al), titanium (Ti), and tantalum (Ta).

[0093] A portion of the second gate electrode (GE2) may extend into the void (VD). The buried pattern (FP) may include a portion of the second gate electrode (GE2). Although not illustrated, a portion of the gate dielectric pattern (GI) may extend into the void (VD). As another example, the buried pattern (FP) may include the same material as the barrier pattern (BM) or the conductive pattern (FM). As an example, a protrusion (PT) of the contact pattern (CP) may come into contact with the buried pattern (FP). In this case, a short circuit may occur between the contact pattern (CP) and the adjacent second gate electrode (GE2) due to the buried pattern (FP). As another example, the protrusion (PT) of the contact pattern (CP) may be spaced apart from the buried pattern (FP). In this case, a short circuit may not occur between the contact pattern (CP) and the adjacent second gate electrode (GE2).

[0094] A first via (VI1) may be interposed between the first test wire (M1_T1) and the contact pattern (CP), and between the second test wire (M1_T2) and the second gate electrode (GE2). The first via (VI1) between the first test wire (M1_T1) and the contact pattern (CP) may be vertically overlapped with any one of the dummy regions (DR).

[0095] The second metal layer (M2) may be spaced apart from the first test wiring (M1_T1) and the second test wiring (M1_T2). The second metal layer (M2) may be provided only on the logic cell region (LCR) and not on the test region (TSR).

[0096] The lowest level on the upper surface of each of the first and second active patterns (AP1, AP2) may be the first level (LV1). The lowest level on the lower surface of the first interlayer insulating film (110) on the logic cell area (LCR) may be the third level (LV3) (see FIG. 2c and FIG. 2d). The lowest level on the upper surface of each of the dummy patterns (DP) may be the second level (LV2). The lowest level on the lower surface of the first interlayer insulating film (110) on the test area (TSR) may be the fourth level (LV4) (see FIG. 2g). The first level (LV1) may be lower than the second level (LV2). The third level (LV3) may be lower than the fourth level (LV4). This is because, as will be described later, the first and second source / drain patterns (SD1, SD2) are not formed on the test area (TSR).

[0097] Different voltages can be applied to the first test wire (M1_T1) and the second test wire (M1_T2). By gradually increasing the difference between the voltage applied to the first test wire (M1_T1) and the voltage applied to the second test wire (M1_T2), the breakdown of the insulating material between the contact pattern (CP) and the adjacent second gate electrode (GE2) can be induced, thereby allowing the breakdown voltage to be measured. The distance between the contact pattern (CP) and the adjacent second gate electrode (GE2) can be quantified based on the magnitude of the measured breakdown voltage. If a short circuit occurs between the contact pattern (CP) and the adjacent second gate electrode (GE2) as illustrated, the breakdown voltage can be measured as 0. If, unlike illustrated, no short circuit occurs between the contact pattern (CP) and the adjacent second gate electrode (GE2), the breakdown voltage can be measured and the distance between them can be quantified. Accordingly, short-circuit defects caused by voids (VD) and embedded patterns (FP) in the logic cell region (LCR), which has a structure substantially identical to that of the test region (TSR), can be detected in a non-destructive manner.

[0098] Conventionally, to identify short circuit defects between a gate electrode and an active contact, electron beam inspection and nano probing were used to locate the short circuit area, and the area was cut to perform destructive analysis. According to embodiments of the present invention, short circuit defects can be detected in a non-destructive manner by using a voltage ramping method in which different voltages are applied to each of the first test wiring (M1_T1) and the second test wiring (M1_T2) to gradually increase the difference. Accordingly, the time required to detect short circuit defects caused by voids in the device isolation film is reduced, and costs can be reduced by preventing wafer loss due to destructive analysis. As a result, defect detection in semiconductor devices can be made easier.

[0100] FIGS. 3 and 5 are plan views for explaining a method for manufacturing a semiconductor device according to embodiments of the present invention. FIGS. 4a to 4g are cross-sectional views along lines A-A', B-B', C-C', D-D', E-E', F-F', and G-G' of FIG. 3, respectively. FIGS. 6a to 6g are cross-sectional views along lines A-A', B-B', C-C', D-D', E-E', F-F', and G-G' of FIG. 5, respectively.

[0101] Referring to FIGS. 3 and FIGS. 4a through 4g, a substrate (100) having a logic cell region (LCR) and a test region (TSR) may be provided. The logic cell region (LCR) may include active regions (PR1, PR2, NR1, NR2). The active regions (PR1, PR2, NR1, NR2) may include a first PMOSFET region (PR1), a second PMOSFET region (PR2), a first NMOSFET region (NR1), and a second NMOSFET region (NR2). The test region (TSR) may include dummy regions (DR). The active regions (PR1, PR2, NR1, NR2) and the dummy regions (DR) may be defined by second trenches (TR2).

[0102] A substrate (100) can be patterned to form first and second active patterns (AP1, AP2). First active patterns (AP1) can be formed on each of the first and second PMOSFET regions (PR1, PR2). Second active patterns (AP2) can be formed on each of the first and second NMOSFET regions (NR1, NR2). Dummy patterns (DP) can be formed on each of the dummy regions (DR). The first and second active patterns (AP1, AP2) and the dummy patterns (DP) can be defined by first trenches (TR1).

[0103] A device isolation layer (ST) may be formed on a substrate (100). The device isolation layer (ST) may include an insulating material such as a silicon oxide film. The device isolation layer (ST) may fill first and second trenches (TR1, TR2). A void (VD) may be formed within the device isolation layer (ST). The void (VD) may be formed within the second trenches (TR2), which are deep trenches. This is because the width of the second trench (TR2) is smaller than its depth, so the device isolation layer (ST) cannot completely fill the second trench (TR2).

[0104] The device isolation layer (ST) can be recessed until the upper portions of each of the first and second active patterns (AP1, AP2) and dummy patterns (DP) are exposed. Thus, the upper portions of each of the first and second active patterns (AP1, AP2) and dummy patterns (DP) can protrude vertically over the device isolation layer (ST).

[0105] Sacrificial patterns (PP) can be formed across the first and second active patterns (AP1, AP2) and dummy patterns (DP). The sacrificial patterns (PP) can be formed in a line shape or a bar shape extending in the first direction (D1). The sacrificial patterns (PP) can fill the void (VD). Unlike what is illustrated, the sacrificial patterns (PP) may partially fill the void (VD) or not fill it at all.

[0106] Specifically, forming sacrificial patterns (PP) may include forming a sacrificial film on the front surface of a substrate (100), forming mask patterns (MA) on the sacrificial film, and patterning the sacrificial film using the mask patterns (MA) as an etching mask. The sacrificial film may include polysilicon.

[0107] A pair of gate spacers (GS) may be formed on both sidewalls of each of the sacrifice patterns (PP). Forming the gate spacers (GS) may include conformally forming a gate spacer film on the front surface of the substrate (100) and anisotropically etching the gate spacer film. The gate spacer film may include at least one of SiCN, SiCON, and SiN. As another example, the gate spacer film may be a multi-layer film including at least two of SiCN, SiCON, and SiN.

[0108] First source / drain patterns (SD1) may be formed on top of each of the first active patterns (AP1). A pair of first source / drain patterns (SD1) may be formed on both sides of each of the sacrifice patterns (PP).

[0109] Specifically, the upper portion of the first active pattern (AP1) can be etched using mask patterns (MA) and gate spacers (GS) as an etching mask to form first recesses (RS1). While etching the upper portion of the first active pattern (AP1), the device isolation film (ST) between the first active patterns (AP1) can be recessed (see FIG. 4c). Accordingly, a recess region (RSR) can be formed that is recessed from the upper surface of the device isolation film (ST) on the logic cell region (LCR) toward one of the second trenches (TR2).

[0110] A first source / drain pattern (SD1) can be formed by performing an optional epitaxial growth process in which the inner wall of the first recess (RS1) of the first active pattern (AP1) serves as a seed layer. As the first source / drain patterns (SD1) are formed, a first channel pattern (CH1) can be defined between a pair of first source / drain patterns (SD1). For example, the optional epitaxial growth process may include a Chemical Vapor Deposition (CVD) process or a Molecular Beam Epitaxy (MBE) process. The first source / drain patterns (SD1) may include a semiconductor element (e.g., SiGe) having a lattice constant greater than the lattice constant of the semiconductor element of the substrate (100). Each of the first source / drain patterns (SD1) may be formed of multiple semiconductor layers.

[0111] For example, impurities may be injected in-situ during a selective epitaxial growth process to form first source / drain patterns (SD1). For another example, after the first source / drain patterns (SD1) are formed, impurities may be injected into the first source / drain patterns (SD1). The first source / drain patterns (SD1) may be doped to have a first conductivity type (e.g., p-type).

[0112] Second source / drain patterns (SD2) may be formed on top of the second active pattern (AP2). A pair of second source / drain patterns (SD2) may be formed on both sides of each of the sacrifice patterns (PP).

[0113] Specifically, the upper portion of the second active pattern (AP2) can be etched using mask patterns (MA) and gate spacers (GS) as an etching mask to form second recesses (RS2). A second source / drain pattern (SD2) can be formed by performing an optional epitaxial growth process in which the inner wall of the second recess (RS2) of the second active pattern (AP2) serves as a seed layer. As the second source / drain patterns (SD2) are formed, a second channel pattern (CH2) can be defined between a pair of second source / drain patterns (SD2). For example, the second source / drain patterns (SD2) may contain the same semiconductor element (e.g., Si) as the substrate (100). The second source / drain patterns (SD2) may be doped to have a second conductivity type (e.g., n-type).

[0114] The first source / drain patterns (SD1) and the second source / drain patterns (SD2) can be formed sequentially through different processes. In other words, the first source / drain patterns (SD1) and the second source / drain patterns (SD2) may not be formed simultaneously.

[0115] Before proceeding with the process of forming the first source / drain pattern (SD1) and the second source / drain pattern (SD2), a mask film (not shown) covering the test area (TSR) may be provided. Accordingly, the first and second source / drain patterns (SD1, SD2) may not be formed on the test area (TSR). Since the process of recessing the upper part of the dummy pattern (DP) is not performed, the upper surface of the device isolation film (ST) on the test area (TSR) may have a flat profile.

[0116] Referring to FIGS. 5 and FIGS. 6a through 6g, a first interlayer insulating film (110) covering first and second source / drain patterns (SD1, SD2), mask patterns (MA), and gate spacers (GS) may be formed. As an example, the first interlayer insulating film (110) may include a silicon oxide film.

[0117] The first interlayer insulating film (110) can be flattened until the upper surfaces of the sacrificial patterns (PP) are exposed. The flattening of the first interlayer insulating film (110) can be performed using an etch back or chemical mechanical polishing (CMP) process. During the flattening process, all mask patterns (MA) can be removed. Consequently, the upper surface of the first interlayer insulating film (110) can be co-planar with the upper surfaces of the sacrificial patterns (PP) and the upper surfaces of the gate spacers (GS).

[0118] Sacrificial patterns (PP) can be replaced with first and second gate electrodes (GE1, GE2), respectively. Specifically, the exposed sacrificial patterns (PP) can be selectively removed. Empty spaces can be formed by removing the sacrificial patterns (PP). Within each of the empty spaces, a gate dielectric pattern (GI), first and second gate electrodes (GE1, GE2), and a gate capping pattern (GP) can be formed. Each of the first and second gate electrodes (GE1, GE2) may include a first metal pattern and a second metal pattern on the first metal pattern. The first metal pattern may be formed of a work function metal capable of controlling the threshold voltage of the transistor, and the second metal pattern may be formed of a low-resistance metal.

[0119] While replacing the sacrifice pattern (PP) with the first gate electrode (GE1), gate cutting patterns (CT) may be formed on the first gate electrode (GE1). The gate cutting patterns (CT) may separate a single first gate electrode (GE1) into multiple first gate electrodes (GE1). Gate cutting patterns (CT) may not be formed on the test area (TSR).

[0120] While replacing the sacrificial pattern (PP) with the first and second gate electrodes (GE1, GE2), a buried pattern (FP) may be formed within the void (VD). That is, the metal material forming the first and second gate electrodes (GE1, GE2) may be partially buried within the void (VD).

[0121] A second interlayer insulating film (120) may be formed on the first interlayer insulating film (110). The second interlayer insulating film (120) may include a silicon oxide film. A pair of separation structures (DB) may be formed on each side of the first logic cell (LC1). The separation structures (DB) may be formed to overlap with the first gate electrodes (GE1) formed on each side of the first logic cell (LC1). Specifically, forming the separation structures (DB) may include forming a hole that penetrates the first and second interlayer insulating films (110, 120) and the first gate electrode (GE1) and extends into the first and second active patterns (AP1, AP2), and filling the hole with an insulating film.

[0122] Referring again to FIGS. 1 and FIGS. 2a through 2h, a first hard mask pattern (not shown) may be formed on a second interlayer insulating film (120). A plurality of openings may be formed in the first hard mask pattern through a photolithography process. A first etching process may be performed on a substrate (100). The first etching process may be an anisotropic etching process. Through the first etching process, the second interlayer insulating film (120) exposed by the openings may be etched. Through the first etching process, the first interlayer insulating film (110) exposed by the openings may be etched. The first etching process may be performed until first and second source / drain patterns (SD1, SD2) are exposed on a logic cell region (LCR). During the first etching process, the top of each of the first and second source / drain patterns (SD1, SD2) may be removed. The first etching process may be performed until dummy patterns (DP) are exposed on the test area (TSR). During the first etching process, the top of each of the dummy patterns (DP) and a portion of the device isolation film (ST) may be removed.

[0123] In the first etching process above, the first interlayer insulating film (110) between the first and second source / drain patterns (SD1, SD2) and the first interlayer insulating film (110) between the dummy patterns (DP) can be deeply recessed.

[0124] Active contacts (AC) and contact patterns (CP) can be formed by filling a recessed area of ​​the first and second interlayer insulating films (110, 120) with a conductive material. For example, the first and second active contacts (AC1, AC2) may include a first body portion (BP1), a second body portion (BP2), and a protrusion (PT) between the first and second body portions (BP1, BP2). The contact pattern (CP) may also include body portions (BP) and a protrusion (PT) between them. For example, when forming the active contacts (AC) and contact patterns (CP), a portion of the barrier pattern (BM) and conductive pattern (FM) constituting them may be embedded within a void (VD) to form a portion of the embedded pattern (FP).

[0125] A second hard mask pattern (not shown) may be formed on the second interlayer insulating film (120). A second etching process may be performed on the substrate (100). Through the second etching process, the upper portion of the active contact (AC) and contact pattern (CP) exposed by the second hard mask pattern may be etched. An insulating material may be filled on the upper portion of the active contact (AC) and contact pattern (CP) to form upper insulating patterns (UIP).

[0126] Gate contacts (GC) that are electrically connected to the first and second gate electrodes (GE), respectively, can be formed by penetrating the second interlayer insulating film (120) and the gate capping pattern (GP).

[0127] A third interlayer insulating film (130) may be formed on the second interlayer insulating film (120). A first metal layer (M1) may be formed within the third interlayer insulating film (130). Forming the first metal layer (M1) may include forming a first power wiring (M1_R1), a second power wiring (M1_R2), a third power wiring (M1_R3), and first wirings (M1_I) on a logic cell region (LCR), and forming a first test wiring (M1_T1) and a second test wiring (M1_T2) on a test region (TSR).

[0128] A fourth interlayer insulating film (140) may be formed on a first metal layer (M1). A second metal layer (M2) may be formed within the fourth interlayer insulating film (140). Forming the second metal layer (M2) may include forming second wirings (M2_I). For example, the second wirings (M2_I) may be formed through a dual damascene process.

[0130] FIG. 7 is a plan view illustrating a semiconductor device according to embodiments of the present invention. FIG. 8a and FIG. 8b are cross-sectional views along the lines A-A' and B-B' of FIG. 7, respectively. In this embodiment, details that overlap with those described with reference to FIG. 1 and FIG. 2a through 2h are omitted, and the differences are described in detail.

[0131] Referring to FIGS. 7, 8a, and 8b, a second trench (TR2) may be formed between adjacent first active patterns (AP1) and second active patterns (AP2). A third trench (TR3) may be formed between adjacent first active patterns (AP1). The first trench (TR1) may be shallower than the second trench (TR2). The second trench (TR2) may be shallower than the third trench (TR3). The third trench (TR3) may be a deep trench.

[0132] A void (VD) may be formed within the third trench (TR3) but not within the second trench (TR2). This is because the width of the third trench (TR3) is smaller than its depth, so the device isolation layer (ST) cannot completely fill the third trench (TR3).

[0134] FIGS. 9a to 9d are for illustrating semiconductor devices according to embodiments of the present invention and are cross-sectional views along lines A-A', B-B', D-D', and E-E' of FIG. 1, respectively. In this embodiment, details that overlap with those described with reference to FIGS. 1 and FIGS. 2a to 2h are omitted, and the differences are described in detail.

[0135] Referring to FIGS. 1 and FIGS. 9a through 9d, a substrate (100) comprising a logic cell region (LCR) and a test region (TSR) may be provided. The logic cell region (LCR) may include a first PMOSFET region (PR1), a second PMOSFET region (PR2), a first NMOSFET region (NR1), and a second NMOSFET region (NR2). The test region (TSR) may include dummy regions (DR).

[0136] A device isolation layer (ST) may be provided on a substrate (100). The device isolation layer (ST) may define a first active pattern (AP1) and a second active pattern (AP2) on the upper surface of the substrate (100). The first active pattern (AP1) may be defined on each of the first PMOSFET region (PR1) and the second PMOSFET region (PR2), and the second active pattern (AP2) may be defined on each of the first NMOSFET region (NR1) and the second NMOSFET region (NR2).

[0137] The first active pattern (AP1) may include first channel patterns (CH1) that are vertically stacked. The stacked first channel patterns (CH1) may be spaced apart from each other in a third direction (D3). The stacked first channel patterns (CH1) may be vertically overlapped with each other. The second active pattern (AP2) may include second channel patterns (CH2) that are vertically stacked. The stacked second channel patterns (CH2) may be spaced apart from each other in a third direction (D3). The stacked second channel patterns (CH2) may be vertically overlapped with each other. The first and second channel patterns (CH1, CH2) may include at least one of silicon (Si), germanium (Ge), and silicon-germanium (SiGe).

[0138] The first active pattern (AP1) may further include first source / drain patterns (SD1). Stacked first channel patterns (CH1) may be interposed between a pair of adjacent first source / drain patterns (SD1). The stacked first channel patterns (CH1) may connect a pair of adjacent first source / drain patterns (SD1).

[0139] The second active pattern (AP2) may further include second source / drain patterns (SD2). Stacked second channel patterns (CH2) may be interposed between a pair of adjacent second source / drain patterns (SD2). The stacked second channel patterns (CH2) may connect a pair of adjacent second source / drain patterns (SD2).

[0140] First gate electrodes (GE1) may be provided extending in a first direction (D1) across first and second channel patterns (CH1, CH2). The first gate electrodes (GE1) may be vertically overlapped with the first and second channel patterns (CH1, CH2). A pair of gate spacers (GS) may be disposed on both sidewalls of the first gate electrodes (GE1). A gate capping pattern (GP) may be provided on the first gate electrodes (GE1).

[0141] The first gate electrode (GE1) may surround each of the first and second channel patterns (CH1, CH2) (see FIG. 9d). The first gate electrode (GE1) may be provided on the top surface (TS), at least one sidewall (SW), and bottom surface (BS) of each of the first and second channel patterns (CH1, CH2). In other words, the first gate electrode (GE1) may surround the top surface (TS), bottom surface (BS), and both sidewalls (SW) of each of the first and second channel patterns (CH1, CH2). The transistor according to the present embodiment may be a three-dimensional field effect transistor (e.g., a Multi-Bridge Channel Field Effect Transistor (MBCFET)) in which the first gate electrode (GE1) surrounds the channels (CH1, CH2) in three dimensions. A first gate electrode (GE1) extending in a first direction (D1) can be separated into multiple first gate electrodes (GE1) by gate cutting patterns (CT).

[0142] A gate dielectric pattern (GI) may be provided between each of the first and second channel patterns (CH1, CH2) and the first gate electrode (GE1). The gate dielectric pattern (GI) may surround each of the first and second channel patterns (CH1, CH2).

[0143] On the first and second NMOSFET regions (NR1, NR2), an insulating pattern (IP) may be interposed between the gate dielectric pattern (GI) and the second source / drain pattern (SD2). The gate electrode (GE) may be separated from the second source / drain pattern (SD2) by the gate dielectric pattern (GI) and the insulating pattern (IP). On the other hand, on the first and second PMOSFET regions (PR1, PR2), the insulating pattern (IP) may be omitted.

[0144] A first interlayer insulating film (110) and a second interlayer insulating film (120) may be provided on the front surface of the substrate (100). Active contacts (AC) connected to first and second source / drain patterns (SD1, SD2), respectively, through the first and second interlayer insulating films (110, 120) may be provided. Gate contacts (GC) connected to first gate electrodes (GE1), respectively, through the second interlayer insulating film (120) and a gate capping pattern (GP) may be provided.

[0145] The detailed description of the active contacts (AC) and gate contacts (GC) may be substantially the same as that described earlier with reference to FIGS. 1 and FIGS. 2a through 2h.

[0146] A third interlayer insulating film (130) may be provided on the second interlayer insulating film (120). A fourth interlayer insulating film (140) may be provided on the third interlayer insulating film (130). A first metal layer (M1) may be provided within the third interlayer insulating film (130). A second metal layer (M2) may be provided within the fourth interlayer insulating film (140). A detailed description of the first metal layer (M1) and the second metal layer (M2) may be substantially the same as that described above with reference to FIGS. 1 and FIGS. 2a through 2h.

[0148] Although embodiments of the present invention have been described above with reference to the attached drawings, those skilled in the art will understand that the present invention may be implemented in other specific forms without changing its technical concept or essential features. Therefore, the embodiments described above should be understood as illustrative in all respects and not restrictive.

Claims

Claim 1 A semiconductor device comprising a logic cell region and a test region, wherein the logic cell region includes a first active region and a second active region spaced apart from each other, and the test region includes dummy regions spaced apart from each other; a first active pattern and a second active pattern provided respectively on the first and second active regions; a dummy pattern provided on each of the dummy regions; a device isolation film disposed in trenches formed between the first and second active patterns and the dummy pattern; a contact pattern provided on the dummy pattern and in contact with the dummy pattern; a first gate electrode extending in a first direction across the dummy regions; a gate contact connected to the first gate electrode; and a first metal layer on the gate contact, wherein the first metal layer includes a first test wiring connected to the contact pattern on the test region and a second test wiring connected to the gate contact, and the lowest level of the upper surface of the first active pattern is lower than the lowest level of the upper surface of the dummy pattern. Claim 2 In claim 1, from a planar perspective, the gate contact is provided between the dummy regions, and the contact pattern is adjacent to the first gate electrode and extends in the first direction. Claim 3 In claim 1, the first metal layer further comprises a first via between the contact pattern and the first test wiring, wherein, in a planar view, the first via is a semiconductor device that overlaps vertically with any one of the dummy regions. Claim 4 In claim 1, the semiconductor device further comprises a second metal layer on the first metal layer, wherein the second metal layer is spaced apart from the first test wiring and the second test wiring. Claim 5 A semiconductor device according to claim 1, further comprising: a first source / drain pattern on the first active pattern; an active contact connected to the first source / drain pattern; and a silicide pattern between the active contact and the first source / drain pattern, wherein the active contact contacts the silicide pattern and the contact pattern contacts the upper surface of the dummy pattern. Claim 6 A semiconductor device according to claim 1, further comprising a second gate electrode crossing the first active pattern and a third gate electrode crossing the second active pattern, wherein a gate cutting pattern is interposed between the second gate electrode and the third gate electrode. Claim 7 A semiconductor device according to claim 1, wherein the device isolation layer comprises a void extending into any one of the trenches between the dummy regions, and at least a portion of the gate contact overlaps vertically with the void. Claim 8 In claim 7, a buried pattern is provided within the void, and the buried pattern comprises a metal material. Claim 9 A semiconductor device according to claim 1, further comprising a third active pattern disposed on the logic cell region and adjacent to the first active pattern, wherein the trenches include a first trench between the first active pattern and the second active pattern and a second trench between the first active pattern and the third active pattern, and the first trench is deeper than the second trench. Claim 10 In claim 1, the voltage applied to the first test wiring and the voltage applied to the second test wiring are different from each other.

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