Semiconductor device

Abstract

A semiconductor device is provided. The semiconductor device includes a first conductive plate on a substrate, a first capacitor block including a plurality of first lower electrodes on the first conductive plate, a second conductive plate spaced apart from the first conductive plate, a second capacitor block including a plurality of second lower electrodes on the second conductive plate, a separating insulating film between the first conductive plate and the second conductive plate, a separating block including a plurality of dummy lower electrodes on the separating insulating film, and a first electrode support supporting a plurality of first lower electrodes, a plurality of second lower electrodes, and a plurality of dummy lower electrodes.

Description

Technology Field

[0001] The present invention relates to a semiconductor device. Background Technology

[0002] In electrical and electronic devices, capacitors are used for various purposes. For example, capacitors are used as memory elements in semiconductor memory devices such as DRAM. As another example, in semiconductor devices, since capacitors function as energy reservoirs that locally store electrical energy, they can be used to implement decoupling circuits that block noise generated in one part of the semiconductor device from affecting other parts of the device.

[0003] Meanwhile, as the aspect ratio of the capacitor increases, bending of the capacitor may occur in the edge regions of the semiconductor device. As a result, insulation characteristics may deteriorate, and leakage current may occur when voltage is applied to the capacitor. The problem to be solved

[0004] The technical problem that the present invention aims to solve is to provide a semiconductor device with improved product reliability.

[0005] The technical problems of the present invention are not limited to those mentioned above, and other unmentioned technical problems will be clearly understood by those skilled in the art from the description below. means of solving the problem

[0006] A semiconductor device according to some embodiments of the present invention for achieving the above technical problem comprises: a first capacitor block including a first conductive plate on a substrate and a plurality of first lower electrodes on the first conductive plate; a second capacitor block including a second conductive plate spaced apart from the first conductive plate and a plurality of second lower electrodes on the second conductive plate; a separation insulating film between the first conductive plate and the second conductive plate; a separation block including a plurality of dummy lower electrodes on the separation insulating film; and a first electrode support that supports a plurality of first lower electrodes, a plurality of second lower electrodes, and a plurality of dummy lower electrodes.

[0007] A semiconductor device according to some embodiments of the present invention for achieving the above technical problem comprises: a first capacitor block including a first conductive plate on a substrate and a plurality of first lower electrodes on the first conductive plate; a second capacitor block including a second conductive plate spaced apart from the first conductive plate and a plurality of second lower electrodes on the second conductive plate; a first edge capacitor block including a plurality of first edge electrodes on the first conductive plate and surrounding the first capacitor block; a second edge capacitor block including a plurality of second edge electrodes on the second conductive plate and surrounding the second capacitor block; and a first electrode support that supports a plurality of first lower electrodes, a plurality of second lower electrodes, a plurality of first edge electrodes, and a plurality of second edge electrodes. The first electrode support comprises a first penetration pattern penetrating the first electrode support, wherein the first penetration pattern is formed across a plurality of first lower electrodes and a plurality of second lower electrodes and is not formed across a plurality of first edge electrodes and a plurality of second edge electrodes.

[0008] A semiconductor device according to some embodiments of the present invention for achieving the above technical problem comprises: a first capacitor block including a first conductive plate on a substrate and a plurality of first lower electrodes on the first conductive plate; a second capacitor block including a second conductive plate spaced apart from the first conductive plate and a plurality of second lower electrodes on the second conductive plate; a first edge capacitor block including a plurality of first edge electrodes on the first conductive plate and surrounding the first capacitor block; a second edge capacitor block including a plurality of second edge electrodes on the second conductive plate and surrounding the second capacitor block; a separation block including a separation insulating film between the first conductive plate and the second conductive plate and a plurality of dummy lower electrodes on the separation insulating film; a first electrode support including a first through pattern that supports a plurality of first lower electrodes, a plurality of second lower electrodes, a plurality of first edge electrodes, a plurality of second edge electrodes, and a plurality of dummy lower electrodes; and a first through pattern that supports a plurality of first lower electrodes, a plurality of second lower electrodes, a plurality of first edge electrodes, a plurality of second edge electrodes, and a plurality of dummy lower electrodes. It includes a second through-pattern that completely overlaps with the pattern, and a second electrode support disposed between the substrate and the first electrode support, wherein the first through-pattern is formed across a plurality of first lower electrodes and a plurality of second lower electrodes, and is not formed across a plurality of first edge electrodes, a plurality of second edge electrodes, and a plurality of dummy lower electrodes.

[0009] Specific details of other embodiments are included in the detailed description and drawings. Brief explanation of the drawing

[0010] FIG. 1 is an exemplary layout diagram for illustrating a semiconductor device according to some embodiments of the present invention. FIG. 2 is a cross-sectional view for illustrating a semiconductor device according to some embodiments of the present invention. FIG. 3 is an exemplary plan view for illustrating a capacitor structure according to some embodiments of the present invention. FIG. 4 is an exemplary cross-sectional view taken along AA of FIG. 3. Figure 5 is an enlarged view showing the R region of Figure 4. FIG. 6 is an exemplary cross-sectional view taken along BB of FIG. 3. FIGS. 7 to 14 are drawings of intermediate steps to explain a method for manufacturing the semiconductor device of FIG. 4. FIG. 15 is an exemplary plan view for illustrating a capacitor structure according to some other embodiments of the present invention. FIG. 16 is an exemplary cross-sectional view taken along AA of FIG. 15. FIGS. 17 to 21 are drawings of intermediate steps to explain a method for manufacturing the semiconductor device of FIG. 15. FIG. 22 is an exemplary plan view for illustrating a capacitor structure according to another embodiment of the present invention. FIG. 23 is an exemplary cross-sectional view taken along AA of FIG. 22. FIGS. 24 and FIGS. 25 are intermediate step drawings to explain a method for manufacturing the semiconductor device of FIG. 23. FIG. 26 is an exemplary plan view for illustrating a capacitor structure according to some other embodiments of the present invention. FIG. 27 is an exemplary cross-sectional view taken along BB of FIG. 26. FIG. 28 is a drawing for illustrating an electrode support according to some other embodiments of the present invention. FIG. 29 is a layout diagram for illustrating a semiconductor device according to some embodiments. FIG. 30 is a perspective view illustrating a semiconductor device according to some embodiments. FIG. 31 is a cross-sectional view taken along DD and EE of FIG. 29. FIG. 32 is a layout diagram for illustrating a semiconductor device according to some embodiments. FIG. 33 is a perspective view illustrating a semiconductor device according to some embodiments. Specific details for implementing the invention

[0011] Hereinafter, embodiments according to the technical concept of the present invention will be described with reference to the attached drawings.

[0012] FIG. 1 is an exemplary layout diagram for illustrating a semiconductor device according to some embodiment of the present invention. FIG. 2 is a cross-sectional view for illustrating a semiconductor device according to some embodiment of the present invention. FIG. 3 is an exemplary plan view for illustrating a capacitor structure according to some embodiment of the present invention. FIG. 4 is an exemplary cross-sectional view cut along AA of FIG. 3. FIG. 5 is an enlarged view showing region R of FIG. 4. FIG. 6 is an exemplary cross-sectional view cut along BB of FIG. 3.

[0013] Referring to FIGS. 1 and 2, a semiconductor device according to some embodiments may include a substrate (100), a first conductive plate (110), a second conductive plate (120), a separating insulating film (101), a capacitor structure (CS), a first contact (181), a second contact (182), and an interlayer insulating film (190).

[0014] The capacitor structure (CS) may include a first capacitor block (CB1), a second capacitor block (CB2), a separation block (SB), a first edge capacitor block (EB1), and a second edge capacitor block (EB2).

[0015] The substrate (100) may be, for example, a silicon single crystal substrate or an SOI (Silicon on Insulator) substrate. Alternatively, the substrate (100) may include silicon germanium, SGOI (silicon germanium on insulator), indium antimonide, lead telluride compound, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide, but is not limited thereto.

[0016] The first conductive plate (110) and the second conductive plate (120) may be disposed on a substrate (100). The first conductive plate (110) and the second conductive plate (120) may extend in the first direction (D1) and the second direction (D2) in a plane in which the first direction (D1) and the second direction (D2) are extended. The first conductive plate (110) and the second conductive plate (120) may include a conductive material.

[0017] The first conductive plate (110) and the second conductive plate (120) can be electrically connected to the capacitor structure (CS). Specifically, the first conductive plate (110) can be electrically connected to the first capacitor block (CB1) and the first edge capacitor block (EB1) of the capacitor structure (CS). The second conductive plate (120) can be electrically connected to the second capacitor block (CB2) and the second edge capacitor block (EB2) of the capacitor structure (CS).

[0018] The first conductive plate (110) and the second conductive plate (120) may be single films, but are not limited thereto. The first conductive plate (110) and the second conductive plate (120) may be multiple films. The first conductive plate (110) and the second conductive plate (120) may include, for example, polysilicon, TiSiN, tungsten (W), and combinations thereof, but are not limited thereto.

[0019] A separating insulating film (101) may be disposed on a substrate (100). The separating insulating film (101) may be disposed between a first conductive plate (110) and a second conductive plate (120). Each separating insulating film (101) may include an insulating material. For example, the separating insulating film (101) may include at least one of a silicon nitride film, a silicon oxynitride film, a silicon oxide film, and a combination thereof.

[0020] The first contact (181) and the second contact (182) may extend in a third direction (D3) perpendicular to the substrate (100) within the interlayer insulating film (190). The interlayer insulating film (190) may surround the first contact (181) and the second contact (182). The interlayer insulating film (190) may be placed on the substrate (100), the first conductive plate (110), the second conductive plate (120), and the isolation insulating film (101). The interlayer insulating film (190) may cover the capacitor structure (CS).

[0021] The first contact (181) can extend in a third direction (D3) on the first conductive plate (110). The first contact (181) can be electrically connected to the first capacitor block (CB1) and the first edge capacitor block (EB1) through the first conductive plate (110). That is, the first contact (181) can apply voltage to the first capacitor block (CB1) and the first edge capacitor block (EB1) through the first conductive plate (110).

[0022] The second contact (182) can extend in a third direction (D3) on the second conductive plate (120). The second contact (182) can be electrically connected to the second capacitor block (CB2) and the second edge capacitor block (EB2) through the second conductive plate (120). That is, the second contact (182) can apply voltage to the second capacitor block (CB2) and the second edge capacitor block (EB2) through the second conductive plate (120).

[0023] A capacitor structure (CS) can be placed on a substrate (100). The capacitor structure (CS) can be placed on a first conductive plate (110), a second conductive plate (120), and a separating insulating film (101).

[0024] Specifically, the first capacitor block (CB1) may be placed on the first conductive plate (110). The first edge capacitor block (EB1) may be placed on the first conductive plate (110). The second capacitor block (CB2) may be placed on the second conductive plate (120). The second edge capacitor block (EB2) may be placed on the second conductive plate (120). The separation block (SB) may be placed on the separation insulating film (101).

[0025] A capacitor structure (CS) may be positioned between the first contact (181) and the second contact (182). The capacitor structure (CS) may be positioned spaced apart from the first contact (181) and the second contact (182) in the first direction (D1).

[0026] The first edge capacitor block (EB1) can surround the first capacitor block (CB1). The second edge capacitor block (EB2) can surround the second capacitor block (CB2).

[0027] The first edge capacitor block (EB1) and the second edge capacitor block (EB2) may be spaced apart in a first direction (D1). In the first direction (D1), a separation block (SB) may be placed between the first edge capacitor block (EB1) and the second edge capacitor block (EB2).

[0028] The first edge capacitor block (EB1) and the second edge capacitor block (EB2) may be spaced apart with a separation block (SB) in between. That is, the separation block (SB) may be placed between the first edge capacitor block (EB1) and the second edge capacitor block (EB2).

[0029] The first capacitor block (CB1) and the second capacitor block (CB2) may be spaced apart in a first direction (D1). In the first direction (D1), a separation block (SB) may be placed between the first capacitor block (CB1) and the second capacitor block (CB2).

[0030] The first capacitor block (CB1) and the second capacitor block (CB2) may be spaced apart with a separation block (SB) in between. That is, the separation block (SB) may be placed between the first capacitor block (CB1) and the second capacitor block (CB2).

[0031] Referring to FIG. 3, the capacitor structure (CS) may include a plurality of lower electrodes (270). The plurality of lower electrodes (270) may include a plurality of first lower electrodes (211), a plurality of second lower electrodes (212), a plurality of first edge electrodes (221), a plurality of second edge electrodes (222), and a plurality of dummy lower electrodes (230). The plurality of lower electrodes (270) may be aligned in a first direction (D1) and a second direction (D2).

[0032] The first capacitor block (CB1) may include a plurality of first lower electrodes (211). The second capacitor block (CB2) may include a plurality of second lower electrodes (212). The first edge capacitor block (EB1) may include a plurality of first edge electrodes (221). The second edge capacitor block (EB2) may include a plurality of second edge electrodes (222). The separation block (SB) may include a plurality of dummy lower electrodes (230).

[0033] A plurality of lower electrodes (270) may include, for example, a doped semiconductor material, a conductive metal nitride (e.g., titanium nitride, tantalum nitride, niobium nitride or tungsten nitride, etc.), a metal (e.g., ruthenium, iridium, titanium or tantalum, etc.), and a conductive metal oxide (e.g., iridium oxide or niobium oxide, etc.), but are not limited thereto.

[0034] The capacitor structure (CS) may include a support structure (300). Specifically, the first capacitor block (CB1), the second capacitor block (CB2), the first edge capacitor block (EB1), the second edge capacitor block (EB2), and the separation block (SB) may overlap with the support structure (300).

[0035] The support structure (300) may include a through pattern (OP). The through pattern (OP) may be formed in the first capacitor block (CB1), the second capacitor block (CB2), the first edge capacitor block (EB1), the second edge capacitor block (EB2), and the separation block (SB).

[0036] The through-pattern (OP) can overlap with at least a portion of multiple electrodes. That is, the through-pattern (OP) can be formed across multiple electrodes.

[0037] For example, in the first capacitor block (CB1), a through pattern (OP) can be formed across four first lower electrodes (211). In the second capacitor block (CB2), a through pattern (OP) can be formed across four second lower electrodes (212). In the first edge capacitor block (EB1), a through pattern (OP) can be formed across four first edge electrodes (221). In the second edge capacitor block (EB2), a through pattern (OP) can be formed across four second edge electrodes (222). In the separation block (SB), a through pattern (OP) can be formed across four dummy lower electrodes (230).

[0038] In FIG. 3, the through pattern (OP) is shown as being formed across four lower electrodes, but the embodiment is not limited thereto. For example, the through pattern (OP) may be formed across three lower electrodes. As another example, the through pattern (OP) may be formed across six lower electrodes.

[0039] Referring to FIGS. 3 to 6, a semiconductor device according to some embodiments may be divided into a first capacitor block (CB1) region, a first edge capacitor block (EB1) region, a separation block (SB) region, a second edge capacitor block (EB2) region, and a second capacitor block (CB2) region from the perspective of a cross-sectional view.

[0040] A semiconductor device according to some embodiments may include a plurality of lower electrodes (270), upper electrodes (240), and a support structure (300).

[0041] A plurality of first lower electrodes (211) may be disposed on the first conductive plate (110) in the first capacitor block (CB1) region. A plurality of first lower electrodes (211) may extend on the first conductive plate (110) in a third direction (D3) perpendicular to the substrate (100). A plurality of second lower electrodes (212) may be disposed on the second conductive plate (120) in the second capacitor block (CB2) region. A plurality of second lower electrodes (212) may extend on the second conductive plate (120) in a third direction (D3) perpendicular to the substrate (100).

[0042] A plurality of first edge electrodes (221) may be disposed on the first conductive plate (110) in the first edge capacitor block (EB1) region. A plurality of second edge electrodes (222) may be disposed on the second conductive plate (120) in the second edge capacitor block (EB2) region. Likewise, a plurality of first edge electrodes (221) and a plurality of second edge electrodes (222) may extend in a third direction (D3) perpendicular to the substrate (100).

[0043] A plurality of dummy lower electrodes (230) may be placed on the separation insulating film (101) in the separation block (SB) region. A plurality of dummy lower electrodes (230) may extend in a third direction (D3) perpendicular to the substrate (100).

[0044] A plurality of dummy lower electrodes (230) can fill the space between the first edge capacitor block (EB1) and the second edge capacitor block (EB2) on the separating insulating film (101). The plurality of dummy lower electrodes (230) are not electrically connected to the first conductive plate (110) and the second conductive plate (120).

[0045] The first lower electrode (211) and the first dummy lower electrode (231) closest to the separation block (SB) may be spaced apart by a first gap (W1). The second lower electrode (212) and the second dummy lower electrode (232) closest to the separation block (SB) may be spaced apart by a second gap (W2). At this time, the first gap (W1) and the second gap (W2) may be the same.

[0046] The adjacent first edge electrode (221) and the first dummy lower electrode (231) may be spaced apart by a fourth gap (W4). The adjacent second edge electrode (222) and the second dummy lower electrode (232) may be spaced apart by a fifth gap (W5). At this time, the fourth gap (W4) and the fifth gap (W5) may be the same.

[0047] The first dummy lower electrode (231) and the second dummy lower electrode (232) adjacent to each other can be spaced apart by a third gap (W3).

[0048] The support structure (300) may include a first electrode support (310) and a second electrode support (320). The first electrode support (310) may have a plate-like shape extending in a direction parallel to the upper surface of the substrate (100). For example, the first electrode support (310) may be an electrode support positioned at the top of the electrode supports included in the first capacitor structure (CS).

[0049] The first electrode support (310) can be in contact with the side walls of a plurality of lower electrodes (270). The first electrode support (310) can support a plurality of lower electrodes (270).

[0050] The first electrode support (310) can prevent the plurality of lower electrodes (270), which are extended in the third direction (D3), from tilting and falling over. The plurality of lower electrodes (270) extend in the thickness direction of the first electrode support (310).

[0051] The first electrode support (310) may include an insulating material. The first electrode support (310) may include, for example, at least one of silicon nitride (SiN), silicon carbonitride (SiCN), silicon boron nitride (SiBN), silicon oxycarbonate (SiOC), silicon oxynitride (SiON), silicon oxide (SiO), and silicon oxycarbonate (SiOCN).

[0052] The first electrode support (310) may include a plurality of first penetration patterns (OP1) that penetrate the first electrode support (310).

[0053] The uppermost surface of a plurality of lower electrodes (270) may be placed in the same plane as the uppermost surface (310_US) of the first electrode support (310). The uppermost surface (211_US) of the first lower electrode (211) may be placed in the same plane as the uppermost surface (310_US) of the first electrode support (310). The uppermost surface (212_US) of a plurality of second lower electrodes (212) may be placed in the same plane as the uppermost surface (310_US) of the first electrode support (310). The uppermost surface (211_US) of a plurality of first edge electrodes (221) may be placed in the same plane as the uppermost surface (310_US) of the first electrode support (310). The uppermost surface (222_US) of a plurality of second edge electrodes (222) may be placed in the same plane as the uppermost surface (310_US) of the first electrode support (310). The uppermost surface (230_US) of the plurality of dummy lower electrodes (230) can be placed in the same plane as the uppermost surface (310_US) of the first electrode support (310).

[0054] The second electrode support (320) may be positioned between the substrate (100) and the first electrode support (310). The second electrode support (320) may have a plate-like shape extending in a direction parallel to the upper surface of the substrate (100).

[0055] The second electrode support (320) can come into contact with the side walls of the plurality of lower electrodes (270). The second electrode support (320) can support the plurality of lower electrodes (270).

[0056] The second electrode support (320) may include a plurality of second penetration patterns (OP2) that penetrate the second electrode support (320). The second penetration patterns (OP2) may be formed at a position corresponding to the first penetration pattern (OP1). The second penetration patterns (OP2) may overlap with the first penetration pattern (OP1) in a third direction (D3).

[0057] The second electrode support (320) may include, for example, at least one of silicon nitride (SiN), silicon carbonitride (SiCN), silicon boron nitride (SiBN), silicon oxycarbonate (SiOC), silicon oxynitride (SiON), silicon oxide (SiO), and silicon oxycarbonate (SiOCN).

[0058] Unlike what is illustrated, for example, the capacitor structure (CS) may not include a second electrode support (320). For another example, the capacitor structure (CS) may further include an additional electrode support between the substrate (100) and the first electrode support (310).

[0059] The through pattern (OP) can be spaced apart at equal intervals in the first capacitor block (CB1), the first edge capacitor block (EB1), the separation block (SB), the second edge capacitor block (EB2), and the second capacitor block (CB2).

[0060] A capacitor dielectric film (250) may be formed on a plurality of lower electrodes (270), a first electrode support (310), and a second electrode support (320). The capacitor dielectric film (250) may extend along the profile of the plurality of lower electrodes (270), the upper surface (310_US) of the first electrode support and the lower surface of the first electrode support (310), and the upper surface and lower surface of the second electrode support (320). The capacitor dielectric film (250) may include, for example, silicon oxide, silicon nitride, silicon oxynitride, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, lead zinc niobate and combinations thereof, but is not limited thereto. Although the capacitor dielectric film (250) is depicted as a single film, this is for convenience of explanation only and is not limited thereto.

[0061] In a semiconductor device according to some embodiments, the capacitor dielectric film (250) may include a stacked film structure in which zirconium oxide, aluminum oxide, and zirconium oxide are sequentially stacked.

[0062] In a semiconductor device according to some embodiments, the capacitor dielectric film (250) may include a dielectric film containing hafnium (Hf). In a semiconductor device according to some embodiments, the capacitor dielectric film (250) may have a stacked film structure of a ferroelectric material film and a paraelectric material film.

[0063] Ferroelectric material films can possess ferroelectric properties. Ferroelectric material films can have a thickness sufficient to exhibit ferroelectric properties. The thickness range of ferroelectric material films exhibiting ferroelectric properties may vary depending on the ferroelectric material.

[0064] For example, the ferroelectric material film may comprise a monometal oxide. The ferroelectric material film may comprise a monometal oxide film. Here, the monometal oxide may be a binary compound composed of one metal and oxygen. The ferroelectric material film comprising the monometal oxide may have an orthorhombic crystal system.

[0065] For example, the metal contained in a single metal oxide film may be hafnium (Hf). The single metal oxide film may be a hafnium oxide film (HfO). Here, the hafnium oxide film may have a stoichiometric chemical formula or a non-stoichiometric chemical formula.

[0066] As another example, the metal included in the single metal oxide film may be one of the rare earth metals belonging to the lanthanoids. The single metal oxide film may be a rare earth metal oxide film belonging to the lanthanoids. Here, the rare earth metal oxide film belonging to the lanthanoids may have a stoichiometric chemical formula or a non-stoichiometric chemical formula. When the ferroelectric material film includes a single metal oxide film, the ferroelectric material film may have a thickness of, for example, 1 nm or more and 10 nm or less.

[0067] For example, the ferroelectric material film may include a bimetal oxide. The ferroelectric material film may include a bimetal oxide film. Here, the bimetal oxide may be a ternary compound composed of two metals and oxygen. The ferroelectric material film containing the bimetal oxide may have an orthorhombic crystal system.

[0068] The metals included in the binary metal oxide film may be, for example, hafnium (Hf) and zirconium (Zr). The binary metal oxide film is a hafnium zirconium oxide film (Hf x Zr (1-x) O) may be. In a binary metal oxide film, x may be 0.2 or more and 0.8 or less. Here, hafnium zirconium oxide film (Hf x Zr (1-x) O) may have a chemical formula that conforms to stoichiometry, or a chemical formula that does not conform to stoichiometry.

[0069] When the ferroelectric material film includes a binary metal oxide film, the ferroelectric material film (132) may have a thickness of, for example, 1 nm or more and 20 nm or less.

[0070] For example, a paraelectric material film may be a dielectric film containing zirconium (Zr) or a stacked film containing zirconium (Zr), but is not limited thereto. Even if the chemical formula is the same, depending on the crystal structure of the dielectric material, it may exhibit ferroelectric properties or paraelectric properties.

[0071] Paraelectric materials have a positive dielectric constant, while ferroelectric materials can have a negative dielectric constant over a certain range. In other words, paraelectric materials have positive capacitance, and ferroelectric materials can have negative capacitance.

[0072] Generally, when two or more capacitors with positive capacitance are connected in series, the total capacitance decreases. However, when a negative capacitor with negative capacitance and a positive capacitor with positive capacitance are connected in series, the total capacitance increases.

[0073] The upper electrode (240) may be formed on the capacitor dielectric film (250). The upper electrode (240) may include, for example, a doped semiconductor material, a conductive metal nitride (e.g., titanium nitride, tantalum nitride, niobium nitride, or tungsten nitride), a metal (e.g., ruthenium, iridium, titanium, or tantalum), and a conductive metal oxide (e.g., iridium oxide or niobium oxide), but is not limited thereto. Although the upper electrode (240) is depicted as a single film, this is for convenience of explanation only and is not limited thereto.

[0074] The upper electrode (240) can extend in a third direction (D3) toward the substrate (100) from the uppermost surface (250_US) of the capacitor dielectric film (250) in the first capacitor block (CB1), the second capacitor block (CB2), the first edge capacitor block (EB1), the second edge capacitor block (EB2), and the separation block (SB).

[0075] Specifically, in the first capacitor block (CB1), the upper electrode (240) may extend from the uppermost surface (250_US) of the capacitor dielectric film (250) between the plurality of first lower electrodes (211) and on the capacitor dielectric film (250) toward the substrate (100). In the second capacitor block (CB2), the upper electrode (240) may extend from the uppermost surface (250_US) of the capacitor dielectric film (250) between the plurality of second lower electrodes (212) and on the capacitor dielectric film (250) toward the substrate (100).

[0076] In the first edge capacitor block (EB1), the upper electrode (240) may extend from the uppermost surface (250_US) of the capacitor dielectric film (250) between the plurality of first edge electrodes (221) and on the capacitor dielectric film (250) toward the substrate (100). In the second edge capacitor block (EB2), the upper electrode (240) may extend from the uppermost surface (250_US) of the capacitor dielectric film (250) between the plurality of second edge electrodes (222) and on the capacitor dielectric film (250) toward the substrate (100).

[0077] In the separation block (SB), the upper electrode (240) can extend from the uppermost surface (250_US) of the capacitor dielectric film (250) toward the substrate (100) between the plurality of dummy lower electrodes (230) and on the capacitor dielectric film (250).

[0078] A semiconductor device according to some embodiments may further include an etch stop layer (260). The etch stop layer (260) may be disposed on a first conductive plate (110), a second conductive plate (120), and a separating insulating layer (101) between a plurality of lower electrodes (270). The etch stop layer (160) may include at least one of a silicon nitride film, a silicon carbonitride film, a silicon boron nitride film (SiBN), a silicon oxynitride film, and a silicon oxycarbonate film.

[0079] FIGS. 7 to 14 are drawings of intermediate steps to explain a method for manufacturing the semiconductor device of FIG. 4.

[0080] Referring to FIG. 7, a first conductive plate (110), a separating insulating film (101), and a second conductive plate (120) are formed on a substrate (100).

[0081] On the first conductive plate (110), the separation insulating film (101), and the second conductive plate (120), a pre-etch stop layer (260P), a first mold layer (ML1), a second pre-support layer (320P), a second mold layer (ML2), and a first pre-support layer (310P) are sequentially formed.

[0082] Referring to FIG. 8, a first mask pattern (Mask1) is formed on a first free support layer (310P). The first mask pattern (Mask1) includes a first mask hole (MH1). The first mask hole (MH1) is formed at equal intervals on the separating insulating film (101), the first conductive plate (110), and the second conductive plate (120). The first mask hole (MH1) exposes a portion of the first free support layer (310P).

[0083] Referring to FIG. 9, an etching stop layer (260), a first mold layer (ML1), a second electrode support (320), a second mold layer (ML2), and a first electrode support (310) are formed by patterning along the first mask hole (MH1). A first trench (T1) is formed between the stack of the etching stop layer (260), the first mold layer (ML1), the second electrode support (320), the second mold layer (ML2), and the first electrode support (310).

[0084] Referring to FIG. 10, a plurality of lower electrodes (270) are formed within the first trench (T1). A plurality of dummy lower electrodes (230) are formed on the separating insulating film (101).

[0086] Referring to FIG. 11, a second mask pattern (Mask2) is formed on a first electrode support (130) and a plurality of lower electrodes (270).

[0087] The second mask pattern (Mask2) includes a second mask hole (MH2). The second mask pattern (Mask2) may partially overlap with a plurality of lower electrodes (270). The second mask hole (MH2) may expose a portion of the first electrode support (310). The second mask hole (MH2) may correspond to the above-described through pattern (OP).

[0088] Referring to FIG. 12, the first electrode support (310) exposed by the second mask hole (MH2) is removed. That is, the first electrode support (310) overlapping with the second mask hole (MH2) is removed to form the second trench (T2).

[0089] Additionally, the first mold layer (ML1) and the second mold layer (ML2) are removed. Accordingly, a void space is formed between the plurality of lower electrodes (270), the first electrode support (310), and the second electrode support (320). Likewise, a void space is formed between the plurality of lower electrodes (270), the second electrode support (320), and the etch stop film (260).

[0090] Referring to FIG. 13, a capacitor dielectric film (250) is formed along the profiles of a plurality of lower electrodes (270) on the etching stop layer (260), the upper and lower surfaces of the first electrode support (310), and the upper and lower surfaces of the second electrode support (320). A capacitor dielectric film (250) is formed in the second trench (T2) to form a third trench (T3).

[0091] Referring to FIG. 14, an upper electrode (240) is formed on the capacitor dielectric film (250).

[0092] An upper electrode (240) is formed within the third trench (T3). The upper electrode (240) can extend toward the substrate (100) in the space where the first electrode support (310) is removed by the mask hole (MH) of FIG. 11.

[0093] FIG. 15 is an exemplary plan view illustrating a capacitor structure according to several other embodiments of the present invention. FIG. 16 is an exemplary cross-sectional view taken along AA of FIG. 15. For convenience of explanation, the description will focus on the differences from the description made with reference to FIG. 3 through 6.

[0094] Referring to FIG. 15, the separation block (SB) does not include a dummy lower electrode (230 in FIG. 3). The first edge capacitor block (EB1) and the second edge capacitor block (EB2) do not include a through pattern (OP). That is, the through pattern (OP) is not formed in the first edge capacitor block (EB1) and the second edge capacitor block (EB2).

[0095] Referring to FIG. 16, an etching stop layer (260), an upper electrode (240), a first electrode support (310), and a second electrode support (320) are disposed on the separation insulating film (101) in the separation block (SB) region.

[0096] A through pattern (OP) is formed in the first capacitor block (CB1) and the second capacitor block (CB2). On the other hand, a through pattern (OP) is not formed in the first edge capacitor block (EB1) and the second edge capacitor block (EB2).

[0097] In the first capacitor block (CB1), the upper electrode (240) may extend from the uppermost surface (250_US) of the capacitor dielectric film (250) between the plurality of first lower electrodes (211) and on the capacitor dielectric film (250) toward the substrate (100). On the other hand, in the first edge capacitor block (EB1), the upper electrode (240) does not extend from the uppermost surface (250_US) of the capacitor dielectric film (250) between the plurality of first edge electrodes (221) and on the capacitor dielectric film (250) toward the substrate (100).

[0098] In the second capacitor block (CB2), the upper electrode (240) may extend from the uppermost surface (250_US) of the capacitor dielectric film (250) between the plurality of second lower electrodes (212) and on the capacitor dielectric film (250) toward the substrate (100). On the other hand, in the second edge capacitor block (EB2), the upper electrode (240) does not extend from the uppermost surface (250_US) of the capacitor dielectric film (250) between the plurality of second edge electrodes (222) and on the capacitor dielectric film (250) toward the substrate (100).

[0099] FIGS. 17 to 21 are drawings of intermediate steps for explaining a method of manufacturing the semiconductor device of FIG. 15. For convenience of explanation, the explanation will focus on the differences from the explanation with reference to FIGS. 7 to 14.

[0100] Referring to FIG. 17, a first free support layer (310P) is formed sequentially. A third mask pattern (Mask3) is formed. The third mask pattern (Mask3) includes a third mask hole (MH3). The third mask hole (MH3) exposes a portion of the first free support layer (310P). The third mask hole (MH3) is formed on the first conductive plate (110) and the second conductive plate (120). The third mask hole (MH3) is not formed on the separating insulating film (101).

[0101] Referring to FIG. 18, an etching stop layer (260), a first mold layer (ML1), a second electrode support (320), a second mold layer (ML2), and a first electrode support (310) are formed by patterning along the third mask hole (MH3). A fourth trench (T4) is formed between the stack of the etching stop layer (260), the first mold layer (ML1), the second electrode support (320), the second mold layer (ML2), and the first electrode support (310).

[0102] Since the third mask hole (MH3) is not formed on the separating insulating film (101), the fourth trench (T4) is not formed on the separating insulating film (101).

[0103] Referring to FIG. 19, a plurality of lower electrodes (270) are formed within the fourth trench (T4). No lower electrodes are formed on the separating insulating film (101).

[0104] Referring to FIG. 20, a fourth mask pattern (Mask4) is formed on a first electrode support (130) and a plurality of lower electrodes (270). The fourth mask pattern (Mask4) includes a fourth mask hole (MH4).

[0105] The fourth mask hole (MH4) is formed only in the regions of the first capacitor block (CB1) and the second capacitor block (CB2). The fourth mask hole (MH4) is not formed in the regions of the first edge capacitor block (EB1), the second edge capacitor block (EB2), and the separation block (SB).

[0106] The fourth mask hole (MH4) can expose a portion of the first electrode support (310). Specifically, it exposes a portion of the first electrode support (310) in the area of ​​the first capacitor block (CB1) and the second capacitor block (CB2).

[0107] Referring to FIG. 21, the first electrode support (310) exposed by the fourth mask hole (MH4) is removed. The first electrode support (310) is removed to form the fifth trench (T5).

[0108] The fifth trench (T5) is formed only in the regions of the first capacitor block (CB1) and the second capacitor block (CB2).

[0109] Additionally, the first mold layer (ML1) and the second mold layer (ML2) are removed. Accordingly, a void space is formed between the plurality of lower electrodes (270), the first electrode support (310), and the second electrode support (320). Likewise, a void space is formed between the plurality of lower electrodes (270), the second electrode support (320), and the etch stop film (260).

[0110] Next, as described with reference to FIGS. 13 and 14, a capacitor dielectric film (250) and an upper electrode (240) are formed sequentially.

[0111] Since the fifth trench (T5) is formed only in the first capacitor block (CB1) and second capacitor block (CB2) regions, the upper electrode (240) extending from the uppermost surface of the capacitor dielectric film (250) toward the substrate (100) is also formed only in the first capacitor block (CB1) and second capacitor block (CB2) regions.

[0112] FIG. 22 is an exemplary plan view illustrating a capacitor structure according to another embodiment of the present invention. FIG. 23 is an exemplary cross-sectional view taken along AA of FIG. 22. For convenience of explanation, the description will focus on the differences from the description made with reference to FIG. 3 and 4 and FIG. 15 and 16.

[0113] Referring to FIG. 22, the separation block (SB) may include a plurality of dummy lower electrodes (230). A through pattern (OP) is not formed in the separation block (SB), the first edge capacitor block (EB1), and the second edge capacitor block (EB2).

[0114] Referring to FIG. 23, a plurality of dummy lower electrodes (230) are placed on the separation insulating film (101) in the separation block (SB) region.

[0115] A through pattern (OP) is formed in the first capacitor block (CB1) and the second capacitor block (CB2). On the other hand, a through pattern (OP) is not formed in the separation block (SB), the first edge capacitor block (EB1), and the second edge capacitor block (EB2).

[0116] In the first capacitor block (CB1), the upper electrode (240) may extend from the uppermost surface (250_US) of the capacitor dielectric film (250) between the plurality of first lower electrodes (211) and on the capacitor dielectric film (250) toward the substrate (100). In the second capacitor block (CB2), the upper electrode (240) may extend from the uppermost surface (250_US) of the capacitor dielectric film (250) between the plurality of second lower electrodes (212) and on the capacitor dielectric film (250) toward the substrate (100).

[0117] On the other hand, in the separation block (SB), the upper electrode (240) does not extend from the uppermost surface (250_US) of the capacitor dielectric film (250) toward the substrate (100) between the plurality of dummy electrodes (230) and on the capacitor dielectric film (250).

[0118] In the first edge capacitor block (EB1), the upper electrode (240) does not extend from the uppermost surface (250_US) of the capacitor dielectric film (250) between the plurality of first edge electrodes (221) and on the capacitor dielectric film (250) toward the substrate (100). In the second edge capacitor block (EB2), the upper electrode (240) does not extend from the uppermost surface (250_US) of the capacitor dielectric film (250) between the plurality of second edge electrodes (222) and on the capacitor dielectric film (250) toward the substrate (100).

[0119] FIGS. 24 and 25 are drawings of intermediate steps for explaining a method of manufacturing the semiconductor device of FIG. 23. For convenience of explanation, the explanation will focus on the differences from the explanation described with reference to FIGS. 7 through 14 and FIGS. 17 through 21.

[0120] Referring to FIG. 24, as in FIG. 10, a fifth mask pattern (Mask5) including a fifth mask hole (MH5) is formed on the plurality of lower electrodes (270) and the first electrode support (310).

[0121] The fifth mask hole (MH5) is formed only in the regions of the first capacitor block (CB1) and the second capacitor block (CB2). The fifth mask hole (MH5) is not formed in the regions of the first edge capacitor block (EB1), the second edge capacitor block (EB2), and the separation block (SB).

[0122] Referring to FIG. 25, the first electrode support (310) exposed by the fifth mask hole (MH5) is removed. The first electrode support (310) is removed to form a sixth trench (T6). The sixth trench (T6) is formed only in the regions of the first capacitor block (CB1) and the second capacitor block (CB2). Additionally, the first mold layer (ML1) and the second mold layer (ML2) are removed. Accordingly, a void space is formed between the plurality of lower electrodes (270), the first electrode support (310), and the second electrode support (320). Likewise, a void space is formed between the plurality of lower electrodes (270), the second electrode support (320), and the etch stop layer (260).

[0123] Next, as described with reference to FIGS. 13 and 14, a capacitor dielectric film (250) and an upper electrode (240) are formed sequentially.

[0124] Since the sixth trench (T6) is formed only in the first capacitor block (CB1) and second capacitor block (CB2) regions, the upper electrode (240) extending from the uppermost surface of the capacitor dielectric film (250) toward the substrate (100) is also formed only in the first capacitor block (CB1) and second capacitor block (CB2) regions.

[0125] As a result, a plurality of dummy lower electrodes (230) are formed on the separation insulating film (101) of the separation block (SB). Meanwhile, unlike FIG. 12, the sixth trench (T6) is not formed in the separation block (SB), so the upper electrode (240) extending from the uppermost surface of the capacitor dielectric film (250) toward the substrate (100) between the plurality of dummy lower electrodes (230) of the separation block (SB) is not formed in the separation block (SB).

[0126] FIG. 26 is an exemplary plan view illustrating a capacitor structure according to another embodiment of the present invention. FIG. 27 is an exemplary cross-sectional view taken along BB of FIG. 26. For convenience of explanation, the description will focus on the differences from the description made with reference to FIG. 3 through 6 and FIG. 22 and 23.

[0127] Referring to FIG. 26, the separation block (SB) may include a plurality of dummy lower electrodes (230). The separation block (SB) may include a through pattern (OP). The first edge capacitor block (EB1) and the second edge capacitor block (EB2) may include a through pattern (OP).

[0128] Specifically, a portion of the first edge capacitor block (EB1), the separation block (SB), and the second edge capacitor block (EB2) that overlap with the first capacitor block (CB1) and the second capacitor block (CB2) in the first direction (D1) may include a through pattern (OP).

[0129] The first capacitor block (CB1) may include a first surface (S1) facing the separation block (SB). The second capacitor block (CB2) may include a second surface (S2) facing the separation block (SB).

[0130] A through pattern (OP) may be formed in a portion of the first edge capacitor block (EB1) between the first surface (S1) and the second surface (S2). That is, a through pattern (OP) may be formed in a portion of the first edge capacitor block (EB1) between the first surface (S1) of the first capacitor block (CB1) and the separation block (SB).

[0131] In a portion of the first edge capacitor block (EB1) that overlaps the first surface (S1) and the second surface (S2) in the first direction (D1), a through pattern (OP) can be formed across a plurality of first edge electrodes (221).

[0132] A through pattern (OP) is not formed in the area of ​​the first edge capacitor block (EB1) surrounding the other surface excluding the first surface (S1) of the first capacitor block (CB1). That is, a through pattern (OP) is not formed in the area of ​​the first edge capacitor block (EB1) in a 'C' shape that partially surrounds the first capacitor block (CB1).

[0133] A through pattern (OP) may be formed in a portion of the second edge capacitor block (EB2) between the first surface (S1) and the second surface (S2). That is, a through pattern (OP) may be formed in a portion of the second edge capacitor block (EB2) between the second surface (S2) of the second capacitor block (CB2) and the separation block (SB).

[0134] In a portion of the second edge capacitor block (EB2) that overlaps the first surface (S1) and the second surface (S2) in the first direction (D1), a through pattern (OP) can be formed across a plurality of second edge electrodes (222).

[0135] A through pattern (OP) is not formed in the area of ​​the second edge capacitor block (EB2) surrounding the other side excluding the second side (S2) of the second capacitor block (CB2). That is, a through pattern (OP) is not formed in the area of ​​the second edge capacitor block (EB2) which is a left-right inverted 'C' shape that partially surrounds the second capacitor block (CB2).

[0136] A through pattern (OP) may be formed in a portion of the separation block (SB) between the first surface (S1) and the second surface (S2). In a portion of the separation block (SB) that overlaps the first surface (S1) and the second surface (S2) in the first direction (D1), a through pattern (OP) may be formed across a plurality of dummy lower electrodes (230).

[0137] The cross-section cut along AA in Fig. 26 is the same as the cross-section described with reference to Fig. 4.

[0138] Referring to FIG. 27 in comparison with FIG. 6, a through pattern (OP) is formed in a part of the separation block (SB) and a through pattern (OP) is not formed in the remaining part, so the area where the first electrode support (310) is formed on the separation insulating film (101) is larger.

[0139] In a portion of the separation block (SB) where the through-pattern (OP) is not formed, the upper electrode (240) does not extend from the uppermost surface of the capacitor dielectric film (250) toward the substrate (100).

[0140] FIG. 28 is a drawing illustrating an electrode support according to several other embodiments of the present invention. For convenience of explanation, the differences from the description with reference to FIG. 3 will be explained in detail.

[0141] Referring to FIG. 28, the support structure (300) may include a through pattern (OP) of a different shape. The through pattern (OP) may be formed across three lower electrodes. However, the embodiment is not limited thereto, and the shape of the through pattern (OP) may be varied according to the embodiment.

[0142] FIG. 29 is a layout diagram illustrating a semiconductor device according to some embodiments. FIG. 30 is a perspective view illustrating a semiconductor device according to some embodiments. FIG. 31 is a cross-sectional view taken along DD and EE of FIG. 29.

[0143] Referring to FIGS. 29 to 31, the semiconductor device may include a substrate (100), a plurality of first conductive lines (420), a channel layer (430), a gate electrode (440), a gate insulating layer (450), and a capacitor structure (480). The semiconductor device of FIGS. 29 to 31 may be a memory device including a vertical channel transistor (VCT). The vertical channel transistor may refer to a structure in which the channel length of the channel layer (430) extends along a vertical direction from the substrate (100).

[0144] The capacitor structure (480) of FIGS. 29 to 31 may be identical to the capacitor structure (CS) described using FIGS. 1 to 3.

[0145] A lower insulating layer (412) may be disposed on the substrate (100), and a plurality of first conductive lines (420) may be spaced apart from each other in a first direction (D1) and extended in a second direction (D2) on the lower insulating layer (412). A plurality of first insulating patterns (422) may be disposed on the lower insulating layer (412) to fill the space between the plurality of first conductive lines (420). The plurality of first insulating patterns (422) may be extended in the second direction (D2), and the upper surface of the plurality of first insulating patterns (422) may be disposed at the same level as the upper surface of the plurality of first conductive lines (420). The plurality of first conductive lines (420) may function as bit lines of a semiconductor device.

[0146] In some embodiments, a plurality of first conductive lines (420) may comprise doped polysilicon, metal, conductive metal nitride, conductive metal silicide, conductive metal oxide, or a combination thereof. For example, a plurality of first conductive lines (420) may comprise doped polysilicon, Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, Co, TiN, TaN, WN, NbN, TiAl, TiAlN, TiSi, TiSiN, TaSi, TaSiN, RuTiN, NiSi, CoSi, IrO x , RuO x It may be composed of, or a combination thereof, but is not limited thereto. A plurality of first conductive lines (420) may comprise a single layer or a multilayer of the aforementioned materials. In some embodiments, a plurality of first conductive lines (420) may comprise a two-dimensional semiconductor material, for example, the two-dimensional semiconductor material may comprise graphene, carbon nanotubes, or a combination thereof.

[0147] The channel layer (430) may be arranged in a matrix form spaced apart in a first direction (D1) and a second direction (D2) on a plurality of first conductive lines (420). The channel layer (430) may have a first width according to the first direction (D1) and a first height according to the third direction (D3), and the first height may be greater than the first width. For example, the first height may be about 2 to 10 times the first width, but is not limited thereto. The bottom portion of the channel layer (430) functions as a first source / drain region (not shown), the upper portion of the channel layer (430) functions as a second source / drain region (not shown), and a portion of the channel layer (430) between the first and second source / drain regions may function as a channel region (not shown).

[0148] In some embodiments, the channel layer (430) may include an oxide semiconductor, for example, the oxide semiconductor is In x Ga y Zn z O, In x Ga y Si z O, In x Sn y Zn z O, In x Zn y O, Zn x O, Zn x Sn y O, Zn x O y N, Zr x Zn y Sn z O, Sn x O, Hf x In y Zn z O, Ga x Zn y Sn z O, Al x Zn y Sn z O, Yb x Gay Zn z O, In x Ga y It may include O or a combination thereof. The channel layer (430) may include a single layer or a multilayer of the oxide semiconductor. In some embodiments, the channel layer (430) may have a bandgap energy greater than the bandgap energy of silicon. For example, the channel layer (430) may have a bandgap energy of about 1.5 eV to 5.6 eV. For example, the channel layer (430) may have optimal channel performance when it has a bandgap energy of about 2.0 eV to 4.0 eV. For example, the channel layer (430) may be polycrystalline or amorphous, but is not limited thereto. In some embodiments, the channel layer (430) may include a two-dimensional semiconductor material, for example, the two-dimensional semiconductor material may include graphene, carbon nanotubes, or a combination thereof.

[0149] The gate electrode (440) may extend in a first direction (D1) on both sidewalls of the channel layer (430). The gate electrode (440) may include a first sub-gate electrode (440P1) facing the first sidewall of the channel layer (430) and a second sub-gate electrode (440P2) facing the second sidewall opposite the first sidewall of the channel layer (430). As one channel layer (430) is disposed between the first sub-gate electrode (440P1) and the second sub-gate electrode (440P2), the semiconductor device may have a dual-gate transistor structure. However, the technical concept of the present invention is not limited thereto, and a single-gate transistor structure may be realized by omitting the second sub-gate electrode (440P2) and forming only the first sub-gate electrode (440P1) facing the first sidewall of the channel layer (430).

[0150] The gate electrode (440) may comprise doped polysilicon, a metal, a conductive metal nitride, a conductive metal silicide, a conductive metal oxide, or a combination thereof. For example, the gate electrode (440) may comprise doped polysilicon, Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, Co, TiN, TaN, WN, NbN, TiAl, TiAlN, TiSi, TiSiN, TaSi, TaSiN, RuTiN, NiSi, CoSi, IrO x , RuO x It may be composed of , or a combination thereof, but is not limited to these.

[0151] The gate insulating layer (450) surrounds the sidewalls of the channel layer (430) and may be interposed between the channel layer (430) and the gate electrode (440). For example, as shown in FIG. 29, the entire sidewall of the channel layer (430) may be surrounded by the gate insulating layer (450), and a portion of the sidewall of the gate electrode (440) may be in contact with the gate insulating layer (450). In other embodiments, the gate insulating layer (450) may be extended in the extension direction of the gate electrode (440) (i.e., the first direction (D1)), and only two sidewalls of the channel layer (430) facing the gate electrode (440) may be in contact with the gate insulating layer (450).

[0152] In some embodiments, the gate insulating layer (450) may be made of a silicon oxide film, a silicon oxynitride film, a high dielectric film having a dielectric constant higher than that of a silicon oxide film, or a combination thereof. The high dielectric film may be made of a metal oxide or a metal oxynitride. For example, a high dielectric film that can be used as the gate insulating layer (450) may be made of HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, ZrO2, Al2O3, or a combination thereof, but is not limited thereto.

[0153] A plurality of second insulation patterns (432) may be extended along a second direction (D2) on a plurality of first insulation patterns (422), and a channel layer (430) may be disposed between two adjacent second insulation patterns (432). Additionally, between two adjacent second insulation patterns (432), a first filling layer (434) and a second filling layer (436) may be disposed in the space between two adjacent channel layers (430). The first filling layer (434) may be disposed at the bottom of the space between two adjacent channel layers (430), and the second filling layer (436) may be formed on the first filling layer (434) to fill the remainder of the space between two adjacent channel layers (430). The upper surface of the second buried layer (436) is positioned at the same level as the upper surface of the channel layer (430), and the second buried layer (436) can cover the upper surface of the gate electrode (440). Alternatively, a plurality of second insulating patterns (432) may be formed as a material layer continuous with a plurality of first insulating patterns (422), or the second buried layer (436) may be formed as a material layer continuous with the first buried layer (434).

[0154] A capacitor contact (460) may be disposed on the channel layer (430). The capacitor contact (460) may be arranged in a matrix form that is vertically overlapped with the channel layer (430) and spaced apart in a first direction (D1) and a second direction (D2). The capacitor contact (460) may be made of doped polysilicon, Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, Co, TiN, TaN, WN, NbN, TiAl, TiAlN, TiSi, TiSiN, TaSi, TaSiN, RuTiN, NiSi, CoSi, IrO x , RuO x , or a combination thereof, but is not limited thereto. The upper insulating layer (462) may surround the sidewall of the capacitor contact (460) on a plurality of second insulating patterns (432) and a second embedded layer (436).

[0155] An etch stop layer (470) is disposed on the upper insulating layer (462), and a capacitor structure (480) may be disposed on the etch stop layer (470). The capacitor structure (480) may include a lower electrode (270), a capacitor dielectric film (250), and an upper electrode (240).

[0156] The lower electrode (270) can be electrically connected to the upper surface of the capacitor contact (460) by penetrating the etch stop layer (470). The lower electrode (270) may be formed as a pillar type extending in the third direction (D3), but is not limited thereto. In some embodiments, the lower electrode (270) may be arranged in a matrix form that is positioned to overlap vertically with the capacitor contact (460) and spaced apart in the first direction (D1) and the second direction (D2). Alternatively, a landing pad (not shown) may be further positioned between the capacitor contact (460) and the lower electrode (270), so that the lower electrode (270) may be arranged in a hexagonal shape.

[0157] FIG. 32 is a layout diagram for illustrating a semiconductor device according to some embodiments. FIG. 33 is a perspective view for illustrating a semiconductor device according to some embodiments.

[0158] Referring to FIGS. 32 and 33, the semiconductor device may include a substrate (100), a plurality of first conductive lines (420A), a channel structure (430A), a contact gate electrode (440A), a plurality of second conductive lines (442A), and a capacitor structure (480). The semiconductor device may be a memory device including a vertical channel transistor (VCT).

[0159] A plurality of active regions (ACs) may be defined in the substrate (100) by a first device isolation layer (412A) and a second device isolation layer (414A). A channel structure (430A) may be disposed within each active region (AC), and the channel structure (430A) may include a first active pillar (430A1) and a second active pillar (430A2) extending in a vertical direction, and a connecting portion (430L) connected to the bottom portion of the first active pillar (430A1) and the bottom portion of the second active pillar (430A2). A first source / drain region (SD1) may be disposed within the connecting portion (430L), and a second source / drain region (SD2) may be disposed above the first and second active pillars (430A1, 430A2). The first active pillar (430A1) and the second active pillar (430A2) can each form an independent unit memory cell.

[0160] A plurality of first conductive lines (420A) may extend in a direction intersecting each of the plurality of active regions (AC), for example, in a second direction (D2). One of the plurality of first conductive lines (420A) may be placed on a connection (430L) between a first active pillar (430A1) and a second active pillar (430A2), and said one first conductive line (420A) may be placed on a first source / drain region (SD1). Another first conductive line (420A) adjacent to said one first conductive line (420A) may be placed between two channel structures (430A). One of the plurality of first conductive lines (420A) can function as a common bit line included in two unit memory cells formed by a first active pillar (430A1) and a second active pillar (430A2) disposed on both sides of the first conductive line (420A).

[0161] A contact gate electrode (440A) may be disposed between two adjacent channel structures (430A) in the second direction (D2). For example, a contact gate electrode (440A) may be disposed between a first active pillar (430A1) included in one channel structure (430A) and a second active pillar (430A2) of the adjacent channel structure (430A), and a contact gate electrode (440) may be shared by the first active pillar (430A1) and the second active pillar (430A2) disposed on both side walls. A gate insulating layer (450A) may be disposed between the contact gate electrode (440A) and the first active pillar (430A1) and between the contact gate electrode (440A) and the second active pillar (430A2). A plurality of second conductive lines (442A) may extend in a first direction (D1) on the upper surface of the contact gate electrode (440A). A plurality of second conductive lines (442A) may function as word lines of a semiconductor device.

[0162] A capacitor contact (460A) may be disposed on the channel structure (430A). The capacitor contact (460A) may be disposed on the second source / drain region (SD2), and a capacitor structure (480) may be disposed on the capacitor contact (460A).

[0163] Although embodiments of the present invention have been described above with reference to the attached drawings, the present invention is not limited to the above embodiments and can be manufactured in various different forms, and those skilled in the art will understand that the present invention can be implemented in other specific forms without changing the technical concept or essential features of the present invention. Therefore, the embodiments described above should be understood as illustrative in all respects and not restrictive. Explanation of the symbols

[0164] 100: Substrate 101: Separating insulating film CB1: 1st capacitor block CB2: 2nd capacitor block EB1: 1st edge capacitor block EB2: 2nd edge capacitor block SB: Separation Block OP: Penetration Pattern 230: Dummy lower electrode 310: First electrode support 320: Second electrode support 110: First conductive plate 120: 2nd Challenge Edition

Claims

Claim 1 A semiconductor device comprising: a first capacitor block including a first conductive plate on a substrate and a plurality of first lower electrodes on the first conductive plate; a second capacitor block including a second conductive plate spaced apart from the first conductive plate and a plurality of second lower electrodes on the second conductive plate; a separation block including a separation insulating film between the first conductive plate and the second conductive plate and a plurality of dummy lower electrodes on the separation insulating film; and a first electrode support supporting the plurality of first lower electrodes, the plurality of second lower electrodes, and the plurality of dummy lower electrodes, wherein the first conductive plate is connected to each of the plurality of first lower electrodes and the second conductive plate is connected to each of the plurality of second lower electrodes. Claim 2 A semiconductor device according to claim 1, comprising a plurality of first edge electrodes on the first conductive plate and further comprising a first edge capacitor block surrounding the first capacitor block, wherein the first electrode support comprises a first penetration pattern penetrating the first electrode support, and the first penetration pattern is formed across the first lower electrode and not formed across the first edge electrode. Claim 3 A semiconductor device according to claim 1, wherein the first electrode support penetrates the first electrode support and includes a first penetration pattern formed across the plurality of first lower electrodes and the plurality of second lower electrodes, and the first penetration pattern is not formed across the plurality of dummy lower electrodes. Claim 4 In claim 1, a first edge capacitor block comprising a plurality of first edge electrodes on the first conductive plate and surrounding the first capacitor block; A semiconductor device comprising a plurality of second edge electrodes on the second conductive plate and further comprising a second edge capacitor block surrounding the second capacitor block, wherein the first electrode support penetrates the first electrode support and includes a first penetration pattern formed across the plurality of first lower electrodes and the plurality of second lower electrodes, wherein the first capacitor block includes a first surface facing the separation block and the second capacitor block includes a second surface facing the separation block, and the first penetration pattern is formed across the plurality of first edge electrodes, the plurality of second edge electrodes, and the plurality of dummy lower electrodes between the first surface and the second surface, and is not formed across the plurality of first edge electrodes located in the first edge capacitor block surrounding a surface other than the first surface of the first capacitor block, and the plurality of second edge electrodes located in the second edge capacitor block surrounding a surface other than the second surface of the second capacitor block. Claim 5 A semiconductor device according to claim 1, wherein the gap between the first lower electrode and the dummy lower electrode closest to the separation block and the gap between the second lower electrode and the dummy lower electrode closest to the separation block are the same. Claim 6 A semiconductor device comprising: a first capacitor block including a first conductive plate on a substrate and a plurality of first lower electrodes on the first conductive plate; a second capacitor block including a second conductive plate spaced apart from the first conductive plate and a plurality of second lower electrodes on the second conductive plate; a first edge capacitor block including a plurality of first edge electrodes on the first conductive plate and surrounding the first capacitor block; a second edge capacitor block including a plurality of second edge electrodes on the second conductive plate and surrounding the second capacitor block; and a first electrode support supporting the plurality of first lower electrodes, the plurality of second lower electrodes, the plurality of first edge electrodes, and the plurality of second edge electrodes, wherein the first electrode support includes a first penetration pattern penetrating the first electrode support, and the first penetration pattern is formed across the plurality of first lower electrodes and the plurality of second lower electrodes and is not formed across the plurality of first edge electrodes and the plurality of second edge electrodes. Claim 7 A semiconductor device according to claim 6, further comprising a separation block disposed between the first capacitor block and the second capacitor block, the separation insulating film between the first conductive plate and the second conductive plate, and a plurality of dummy lower electrodes on the separation insulating film. Claim 8 A semiconductor device according to claim 7, wherein the first penetration pattern is not formed across the plurality of dummy lower electrodes. Claim 9 A first capacitor block comprising a first conductive plate on a substrate and a plurality of first lower electrodes on the first conductive plate; a second capacitor block comprising a second conductive plate spaced apart from the first conductive plate and a plurality of second lower electrodes on the second conductive plate; a first edge capacitor block comprising a plurality of first edge electrodes on the first conductive plate and surrounding the first capacitor block; a second edge capacitor block comprising a plurality of second edge electrodes on the second conductive plate and surrounding the second capacitor block; a separation block comprising a separation insulating film between the first conductive plate and the second conductive plate and a plurality of dummy lower electrodes on the separation insulating film; and a first electrode support comprising a first through-pattern, which supports the plurality of first lower electrodes, the plurality of second lower electrodes, the plurality of first edge electrodes, the plurality of second edge electrodes, and the plurality of dummy lower electrodes. A semiconductor device comprising a plurality of first lower electrodes, a plurality of second lower electrodes, a plurality of first edge electrodes, a plurality of second edge electrodes, and a plurality of dummy lower electrodes, and a second electrode support disposed between the substrate and the first electrode support, wherein the first through-pattern is formed across the plurality of first lower electrodes and the plurality of second lower electrodes, and is not formed across the plurality of first edge electrodes, the plurality of second edge electrodes, and the plurality of dummy lower electrodes. Claim 10 A semiconductor device according to claim 9, comprising: an etch stop film disposed between the plurality of first lower electrodes, the plurality of second lower electrodes, the plurality of first edge electrodes, the plurality of second edge electrodes, and the plurality of dummy lower electrodes on the first conductive plate, the second conductive plate, and the separating insulating film; a capacitor dielectric film extending along the profiles of the plurality of first lower electrodes, the plurality of second lower electrodes, the plurality of first edge electrodes, the plurality of second edge electrodes, and the plurality of dummy lower electrodes on the etch stop film, the upper and lower surfaces of the first electrode support, and the upper and lower surfaces of the second electrode support; and an upper electrode on the capacitor dielectric film, wherein the upper electrode extends toward the substrate from the uppermost surface of the capacitor dielectric film in the first capacitor block and the second capacitor block, and does not extend toward the substrate from the uppermost surface of the capacitor dielectric film in the first edge capacitor block and the second edge capacitor block.

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