Display device

Abstract

A display device is provided. The display device includes a first electrode arranged extending in a first direction from a subpixel, a second electrode arranged extending in the first direction and spaced apart from the first electrode in a second direction intersecting the first direction, a bank layer arranged extending in the second direction and surrounding a plurality of the subpixels, and a light-emitting element arranged on the first electrode and the second electrode, wherein at least one of the first electrode and the second electrode includes an electrode extension portion extended in the first direction and an electrode body portion connected to the electrode extension portion and having a width greater than that of the electrode extension portion, and the bank layer is arranged overlapping the electrode body portion by a first width and includes an organic insulating material.

Description

Technology Field

[0001] The present invention relates to a display device. Background Technology

[0002] As the information society develops, the demand for display devices for displaying images is increasing in various forms. The display device may be a flat panel display device such as a Liquid Crystal Display, a Field Emission Display, or a Light Emitting Display. The light emitting display device may include an organic light emitting display device comprising an organic light emitting diode as a light emitting element, an inorganic light emitting display device comprising an inorganic semiconductor as a light emitting element, or a micro light emitting diode (or micro light emitting diode) as a light emitting element. The problem to be solved

[0003] The problem that the present invention aims to solve is to provide a display device that can prevent light-emitting elements from being clustered and arranged in areas other than the alignment area.

[0004] The problems of the present invention are not limited to those mentioned above, and other unmentioned technical problems will be clearly understood by those skilled in the art from the description below. means of solving the problem

[0005] A display device according to one embodiment for solving the above problem comprises a first electrode extending in a first direction from a subpixel, a second electrode spaced apart from the first electrode in a second direction intersecting the first direction and extending in the first direction, a bank layer extending in the second direction and surrounding a plurality of the subpixels, and a light-emitting element disposed on the first electrode and the second electrode, wherein at least one of the first electrode and the second electrode comprises an electrode extension portion extending in the first direction and an electrode body portion connected to the electrode extension portion and having a width greater than that of the electrode extension portion, and the bank layer overlaps the electrode body portion by a first width and comprises an organic insulating material.

[0006] A display device according to one embodiment for solving the above other problems comprises a first electrode extended in a first direction and disposed therein, a second electrode spaced apart from the first electrode in a second direction intersecting the first direction and disposed therein extending in the first direction, a bank layer extending in the second direction and surrounding a plurality of the subpixels, and a light-emitting element disposed on the first electrode and the second electrode, wherein the first electrode comprises a first electrode extension portion extended in the first direction and a first electrode body portion connected to the first electrode extension portion and having a width greater than that of the first electrode extension portion, and the second electrode comprises a second electrode extension portion extended in the first direction and a second electrode body portion connected to the second electrode extension portion and having a width greater than that of the second electrode extension portion, and the first electrode extension portion has a shape bent in a diagonal direction inclined from the first direction toward the second electrode body portion. Effects of the invention

[0007] According to the display device of the embodiments, the bank layer may be disposed on electrodes receiving different voltages in a region other than the alignment region within the light-emitting region where light-emitting elements are aligned. Accordingly, the display device can prevent an electric field that interferes with the electric field of the alignment region of the light-emitting elements from being formed between the electrodes receiving different voltages.

[0008] The effects according to the embodiments are not limited to those exemplified above, and a wider variety of effects are included in this specification. Brief explanation of the drawing

[0009] FIG. 1 is a schematic plan view of a display device according to one embodiment. FIG. 2 is a circuit diagram of a pixel of a display device according to one embodiment. FIG. 3 is a plan view showing the arrangement of electrodes, bank patterns, and bank layers placed in a pixel of a display device according to one embodiment. FIG. 4 is a plan view showing the arrangement of connecting electrodes and light-emitting elements placed in one pixel in addition to FIG. 3. Figure 5 is a cross-sectional view taken along the line E1-E1' of Figure 4. Figure 6 is a cross-sectional view taken along the lines E2-E2' and E3-E3' of Figure 4. FIG. 7 is a schematic diagram of a light-emitting element according to one embodiment. Figure 8 is an enlarged plan view of A in Figure 3. Figure 9 is a cross-sectional view taken along the line E4-E4' of Figure 8. Figure 10 is an enlarged plan view of B in Figure 3. Figure 11 is a cross-sectional view taken along the line E5-E5' of Figure 10. Figure 12 is a cross-sectional view taken along the line X1-X1' of Figure 8. FIG. 13 is a graph showing the electric field strength in the first direction according to the length of the first width of FIG. 8 and FIG. 12. FIG. 14 is a graph showing the electric field strength in the first direction according to the first thickness of the bank layer of FIG. 8 and FIG. 12. FIG. 15 is a plan view of a display device according to another embodiment. FIG. 16 is a plan view showing the arrangement of connecting electrodes, a bank layer, and light-emitting elements placed in one pixel of FIG. 15. Figure 17 is a cross-sectional view taken along the line E6-E6' of Figures 15 and 16. Specific details for implementing the invention

[0010] The advantages and features of the present invention and the methods for achieving them will become clear by referring to the embodiments described below in detail together with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below but may be implemented in various different forms. These embodiments are provided merely to ensure that the disclosure of the present invention is complete and to fully inform those skilled in the art of the scope of the invention, and the present invention is defined only by the scope of the claims.

[0011] When elements or layers are referred to as being "on" another element or layer, this includes cases where another layer or element is interposed directly on or in the middle of another element. Throughout the specification, the same reference numerals refer to the same components. Shapes, sizes, ratios, angles, numbers, etc., disclosed in the drawings for describing embodiments are exemplary and therefore the invention is not limited to the depicted details.

[0012] Although terms such as "first," "second," etc., are used to describe various components, it goes without saying that these components are not limited by these terms. These terms are used merely to distinguish one component from another. Therefore, it goes without saying that the first component mentioned below may also be the second component within the technical scope of the present invention.

[0013] The features of each of the various embodiments of the present invention may be combined or combined with one another, either partially or wholly, and may technically enable various interlocking and operation. Each embodiment may be implemented independently of one another or may be implemented together in an associated relationship.

[0014] Specific embodiments will be described below with reference to the attached drawings.

[0015] FIG. 1 is a schematic plan view of a display device according to one embodiment.

[0016] Referring to FIG. 1, the display device (10) displays a video or a still image. The display device (10) may refer to any electronic device that provides a display screen. For example, a television, laptop, monitor, billboard, Internet of Things, mobile phone, smartphone, tablet PC (Personal Computer), electronic watch, smart watch, watch phone, head-mounted display, mobile communication terminal, electronic notebook, electronic book, PMP (Portable Multimedia Player), navigation, game console, digital camera, camcorder, etc. that provide a display screen may be included in the display device (10).

[0017] The display device (10) includes a display panel that provides a display screen. Examples of display panels include an inorganic light-emitting diode display panel, an organic light-emitting diode display panel, a quantum dot light-emitting diode display panel, a plasma display panel, a field emission display panel, etc. In the following examples, an inorganic light-emitting diode display panel is used as an example of a display panel, but it is not limited thereto, and if the same technical concept is applicable, it can be applied to other display panels.

[0018] The shape of the display device (10) can be varied in many ways. For example, the display device (10) may have a shape such as a horizontally elongated rectangle, a vertically elongated rectangle, a square, a rectangle with rounded corners (vertices), other polygons, or a circle. The shape of the display area (DPA) of the display device (10) may also be similar to the overall shape of the display device (10). In FIG. 1, a display device (10) in the shape of a rectangle with a long length in the second direction (DR2) is illustrated.

[0019] The display device (10) may include a display area (DPA) and a non-display area (NDA). The display area (DPA) is an area where the screen can be displayed, and the non-display area (NDA) is an area where the screen is not displayed. The display area (DPA) may also be referred to as an active area, and the non-display area (NDA) as an inactive area. The display area (DPA) may generally occupy the center of the display device (10).

[0020] The display area (DPA) may include a plurality of pixels (PX). The plurality of pixels (PX) may be arranged in a matrix direction. The shape of each pixel (PX) may be a planar rectangle or a square, but is not limited thereto, and may be a rhombus shape with each side tilted toward one direction. Each pixel (PX) may be arranged in a stripe type or an island type. Additionally, each of the pixels (PX) may include one or more light-emitting elements that emit light of a specific wavelength range to display a specific color.

[0021] A non-display area (NDA) may be placed around a display area (DPA). The non-display area (NDA) may surround the display area (DPA) in whole or in part. The display area (DPA) is rectangular in shape, and the non-display area (NDA) may be placed adjacent to the four sides of the display area (DPA). The non-display area (NDA) may form the bezel of the display device (10). In each non-display area (NDA), wiring or circuit drivers included in the display device (10) may be placed, or external devices may be mounted.

[0022] FIG. 2 is a circuit diagram of a pixel of a display device according to one embodiment.

[0023] Referring to FIG. 2, each subpixel (SPXn) of a display device (10) according to one embodiment includes, in addition to a light-emitting diode (EL), three transistors (T1, T2, T3) and one storage capacitor (Cst).

[0024] A light-emitting diode (EL) emits light according to the current supplied through a first transistor (T1). The light-emitting diode (EL) includes a first electrode, a second electrode, and at least one light-emitting element disposed between them. The light-emitting element can emit light of a specific wavelength range by means of an electrical signal transmitted from the first electrode and the second electrode.

[0025] One end of the light-emitting diode (EL) is connected to the source electrode of the first transistor (T1), and the other end can be connected to a second voltage wiring (VL2) to which a low potential voltage (hereinafter referred to as the second power supply voltage) lower than the high potential voltage (hereinafter referred to as the first power supply voltage) of the first voltage wiring (VL1) is supplied.

[0026] The first transistor (T1) determines the current flowing from the first voltage wiring (VL1), to which the first power supply voltage is supplied, to the light-emitting diode (EL) according to the voltage difference between the gate electrode and the source electrode. For example, the first transistor (T1) may be a driving transistor for driving the light-emitting diode (EL). The gate electrode of the first transistor (T1) may be connected to the source electrode of the second transistor (T2), the source electrode may be connected to the first electrode of the light-emitting diode (EL), and the drain electrode may be connected to the first voltage wiring (VL1), to which the first power supply voltage is applied.

[0027] The second transistor (T2) is turned on by a scan signal of the first scan line (SL1) to connect the data line (DTL) to the gate electrode of the first transistor (T1). The gate electrode of the second transistor (T2) is connected to the first scan line (SL1), the source electrode is connected to the gate electrode of the first transistor (T1), and the drain electrode can be connected to the data line (DTL).

[0028] The third transistor (T3) is turned on by a scan signal of the second scan line (SL2) to connect the initial voltage wire (VIL) to one end of the light-emitting diode (EL). The gate electrode of the third transistor (T3) is connected to the second scan line (SL2), the drain electrode is connected to the initial voltage wire (VIL), and the source electrode can be connected to one end of the light-emitting diode (EL) or the source electrode of the first transistor (T1).

[0029] In one embodiment, the source electrode and drain electrode of each transistor (T1, T2, T3) are not limited to those described above, and may be the opposite. Each of the transistors (T1, T2, T3) may be formed as a thin film transistor. Although FIG. 3 describes each transistor (T1, T2, T3) as being formed as an N-type MOSFET (Metal Oxide Semiconductor Field Effect Transistor), it is not limited thereto. That is, each transistor (T1, T2, T3) may be formed as a P-type MOSFET, or some may be formed as an N-type MOSFET and others as a P-type MOSFET.

[0030] A storage capacitor (Cst) is formed between the gate electrode and the source electrode of the first transistor (T1). The storage capacitor (Cst) stores the difference voltage between the gate voltage and the source voltage of the first transistor (T1).

[0031] FIG. 3 is a plan view showing the arrangement of electrodes, bank patterns, and bank layers placed in a pixel of a display device according to one embodiment. FIG. 4 is a plan view showing the arrangement of connecting electrodes and light-emitting elements placed in a pixel in addition to FIG. 3.

[0032] FIGS. 3 and 4 illustrate the planar arrangement of electrodes (RME: RME1, RME2), bank patterns (BP1, BP2), bank layer (BNL), a plurality of light-emitting elements (ED: ED1, ED2) and connecting electrodes (CNE: CNE1, CNE2) placed in one pixel (PX) of a display device (10).

[0033] Each of the pixels (PX) of the display device (10) may include a plurality of subpixels (SPXn). For example, one pixel (PX) may include a first subpixel (SPX1), a second subpixel (SPX2), and a third subpixel (SPX3). The first subpixel (SPX1) may emit light of a first color, the second subpixel (SPX2) may emit light of a second color, and the third subpixel (SPX3) may emit light of a third color. As an example, the first color may be blue, the second color may be green, and the third color may be red. However, not limited thereto, each subpixel (SPXn) may emit light of the same color. In one embodiment, each subpixel (SPXn) may emit blue light. In the drawing, one pixel (PX) is illustrated as containing three subpixels (SPXn), but is not limited thereto, and the pixel (PX) may contain a larger number of subpixels (SPXn).

[0034] Each subpixel (SPXn) of the display device (10) may include a light-emitting region (EMA) and a non-light-emitting region. The light-emitting region (EMA) may be an area where a light-emitting element (ED) is placed and light of a specific wavelength range is emitted. The non-light-emitting region may be an area where a light-emitting element (ED) is not placed and light emitted from the light-emitting element (ED) does not reach and is not emitted.

[0035] The light-emitting region (EMA) may include an area where a light-emitting element (ED) is placed and an area adjacent to the light-emitting element (ED) through which light emitted from the light-emitting element (ED) is emitted. For example, the light-emitting region (EMA) may also include an area where light emitted from the light-emitting element (ED) is reflected or refracted by another component and emitted. A plurality of light-emitting elements (ED) are placed in each subpixel (SPXn), and a light-emitting region may be formed by including the area where they are placed and an area adjacent thereto.

[0036] Each sub-pixel (SPXn) may further include sub-regions (SA1, SA2) disposed in a non-emissive region. The sub-regions (SA1, SA2) may include a first sub-region (SA1) disposed on the upper side, which is one side of the first direction (DR1) of the emitting region (EMA), and a second sub-region (SA2) disposed on the lower side, which is the other side of the first direction (DR1) of the emitting region (EMA). The emitting region (EMA) and the sub-regions (SA1, SA2) may be alternately arranged in the first direction (DR1) according to the arrangement of pixels (PX) and sub-pixels (SPXn). For example, a plurality of emitting regions (EMA) may be repeatedly arranged in the first direction (DR1) with the first sub-region (SA1) or the second sub-region (SA2) in between. The light-emitting regions (EMA) are arranged repeatedly in the second direction (DR2), and the first sub-region (SA1) and the second sub-region (SA2) may extend in the second direction (DR2) within the display area (DPA). However, not limited thereto, the light-emitting regions (EMA) and sub-regions (SA1, SA2) in a plurality of pixels (PX) may have an arrangement different from that of FIGS. 2 and FIGS. 3.

[0037] The first sub-region (SA1) and the second sub-region (SA2) may be areas shared by sub-pixels (SPXn) adjacent in the first direction (DR1). For example, the second sub-region (SA2) may be an area shared by the i-th sub-pixel (e.g., the sub-pixel (SPXn) shown in FIG. 3 and FIG. 4) and the i+1-th sub-pixel adjacent in the first direction (DR1) that is not shown in the drawings. The first sub-region (SA1) may be positioned above the light-emitting area (EMA) of the i-th sub-pixel, and the second sub-region (SA2) may be positioned above the light-emitting area of ​​the i+1-th sub-pixel.

[0038] In the sub-regions (SA1, SA2), light-emitting elements (ED) are not placed so light is not emitted, but a portion of the electrodes (RME) placed in each sub-pixel (SPXn) may be placed. The electrodes (RME) placed in different sub-pixels (SPXn) may be extended and placed in a first direction (DR1).

[0039] A display device (10) according to one embodiment may include a plurality of electrodes (RME: RME1, RME2), bank patterns (BP1, BP2), a bank layer (BNL), light-emitting elements (ED), and connecting electrodes (CNE: CNE1, CNE2).

[0040] Multiple bank patterns (BP1, BP2) can be placed in the light-emitting region (EMA) of each subpixel (SPXn). The bank patterns (BP1, BP2) may have a shape that has a certain width in the second direction (DR2) and extends in the first direction (DR1).

[0041] For example, bank patterns (BP1, BP2) may include a first bank pattern (BP1) and a second bank pattern (BP2) spaced apart from each other in a second direction (DR2) within the light-emitting region (EMA) of each subpixel (SPXn). The first bank pattern (BP1) is positioned at the center of the light-emitting region (EMA), and the second bank patterns (BP2) are positioned spaced apart from the first bank pattern (BP1). The first bank pattern (BP1) and the second bank pattern (BP2) are positioned alternately along the second direction (DR2) and may be arranged in an island pattern in the display region (DPA). A plurality of light-emitting elements (ED) may be positioned between the first bank pattern (BP1) and the second bank pattern (BP2).

[0042] The widths of the second direction (DR2) of the first bank pattern (BP1) and the second bank pattern (BP2) may differ from each other. The width of the second direction (DR2) of the first bank pattern (BP1) may be smaller than the width of the second direction (DR2) of the second bank pattern (BP2). While the first bank pattern (BP1) is placed in the light-emitting region (EMA) of each subpixel (SPXn), the second bank pattern (BP2) may be placed across the light-emitting region (EMA) of two subpixels (SPXn) adjacent to each other in the second direction (DR2). The second bank pattern (BP2) is placed across the boundary of subpixels (SPXn) adjacent in the second direction (DR2) and may overlap with the portion of the bank layer (BNL) described later that extends in the first direction (DR1). However, this is not limited thereto, and the first bank pattern (BP1) and the second bank pattern (BP2) may have the same width.

[0043] The first bank pattern (BP1) and the second bank pattern (BP2) have the same length in the first direction (DR1) as each other and may be longer than the length in the first direction (DR1) of the light-emitting region (EMA) surrounded by the bank layer (BNL). The first bank pattern (BP1) and the second bank pattern (BP2) may overlap with the portion of the bank layer (BNL) that extends in the second direction (DR2). However, they are not limited thereto, and the bank patterns (BP1, BP2) may be integrated with the bank layer (BNL) or separated from the portion of the bank layer (BNL) that extends in the second direction (DR2). In this case, the length in the first direction (DR1) of the bank patterns (BP1, BP2) may be the same as or smaller than the length in the first direction (DR1) of the light-emitting region (EMA) surrounded by the bank layer (BNL).

[0044] In the drawing, one first bank pattern (BP1) and two different second bank patterns (BP2) are arranged for each subpixel (SPXn), but this is not limited thereto. The number and shape of the bank patterns (BP1, BP2) may vary depending on the number or arrangement structure of the electrodes (RME).

[0045] Multiple electrodes (RME: RME1, RME2) are arranged in a shape extending in one direction for each subpixel (SPXn). The multiple electrodes (RME1, RME2) may extend in a first direction (DR1) and be placed in the light-emitting region (EMA) of the subpixel (SPXn), and may be arranged spaced apart from each other in a second direction (DR2). The multiple electrodes (RME) may be electrically connected to a light-emitting element (ED). However, they are not limited thereto, and the electrodes (RME) may not be electrically connected to the light-emitting element (ED).

[0046] The display device (10) may include a first electrode (RME1) disposed in each subpixel (SPXn) and a second electrode (RME2) disposed across different subpixels (SPXn). The first electrode (RME1) may be disposed adjacent to the center of the subpixel (SPXn) and may be disposed across the light-emitting region (EMA) and sub-regions (SA1, SA2). The second electrode (RME2) may be spaced apart from the first electrode (RME1) in the light-emitting region (EMA) in the second direction (DR2) and may be disposed across a plurality of subpixels (SPXn). The first electrode (RME1) and the second electrode (RME2) generally have a shape extending in the first direction (DR1), but the length extended in the first direction (DR1) and the shape of the portion disposed in the light-emitting region (EMA) may be different from each other. The first electrode (RME1) is positioned at the center of the subpixel (SXPn), and the portion positioned in the light-emitting region (EMA) can be positioned on the first bank pattern (BP1). The second electrode (RME2) is positioned on both sides of the second direction (DR2) from the center of the subpixel (SPXn), and the portion positioned in the light-emitting region (EMA) can be positioned on the second bank pattern (BP2).

[0047] According to one embodiment, the electrodes (RME1, RME2) may include a portion extending in a first direction (DR1) and a portion that widens around the radiating region (EMA). The electrodes (RME1, RME2) may include an electrode extension portion (RMS1, RMS2) extending in the first direction (DR1) and an electrode body portion (RMB1, RMB2) connected from the electrode extension portion (RMS1, RMS2) and having a width in the second direction (DR2) that is wider than that of the electrode extension portion (RMS1, RMS2).

[0048] The first electrode (RME1) may include a first electrode extension portion (RMS1) extended in a first direction (DR1) and a first electrode body portion (RMB1) with a wide width in a second direction (DR2). The second electrode (RME2) may include a second electrode extension portion (RMS2) extended in a first direction (DR1) and a second electrode body portion (RMB2) with a wide width in a second direction (DR2).

[0049] The electrode extensions (RMS1, RMS2) are positioned to overlap with the portion extending in the second direction (DR2) of the bank layer (BNL) and may be positioned in the sub-regions (SA1, SA2). The electrode extensions (RMS1, RMS2) may not be positioned in the light-emitting region (EMA). The electrode extensions (RMS1, RMS2) extend from the electrode body portion (RMB1, RMB2) into the first direction (DR1) and may have a shape that is at least partially bent. The electrode extensions (RMS1, RMS2) may extend into the first direction (DR1) from one side offset from the center of the electrode body portion (RMB1, RMB2). For example, the first electrode extension portion (RMS1) may extend into the first direction (DR1) by protruding to the right or left of the center of the first electrode body portion (RMB1). The second electrode extension (RMS2) may be extended in a first direction (DR1) by protruding to the right or left of the center of the second electrode body (RMB2). The electrode extensions (RMS1, RMS2) may have a partially bent shape or be extended at an angle from one direction to secure electrode contact holes (CTD, CTS) in a certain space.

[0050] The electrode body portions (RMB1, RMB2) are positioned to partially overlap with the bank layer (BNL) and may be positioned in the light-emitting region (EMA). The electrode body portions (RMB1, RMB2) may have a shape that has a constant width in the second direction (DR2) and extends in the first direction (DR1). The first electrode body portion (RMB1) is positioned at the center of the subpixel (SPXn) and may be positioned on the first bank pattern (BP1). Both ends of the first electrode body portion (RMB1) may overlap with the portion of the bank layer (BNL) that extends in the second direction (DR2). The second electrode body portion (RMB2) is positioned on both sides of the second direction (DR2) at the center of the subpixel (SPXn) and may be positioned on the second bank pattern (BP2). The second electrode body portion (RMB2) can overlap simultaneously with the portion extending in the first direction (DR1) and the portion extending in the second direction (DR2) of the bank layer (BNL). Both ends of the second electrode body portion (RMB2) can overlap with the portion extending in the second direction (DR2) of the bank layer (BNL). Since the second electrode body portion (RMB2) is positioned across subpixels (SPXn) adjacent in the second direction (DR2), it can overlap with the portion extending in the first direction (DR1) of the bank layer (BNL) positioned between the light-emitting regions (EMA) of the subpixels (SPXn).

[0051] The second electrodes (RME2) generally extend in the first direction (DR1) and can be positioned between adjacent subpixels (SPXn) in the second direction (DR2). The second electrodes (RME2) can be distinguished into different electrode lines (RML1, RML2) positioned on both sides of the second direction (DR2) relative to the first electrode (RME1). A plurality of second electrodes (RME2) may include different first electrode lines (RML1) and second electrode lines (RML2), and these may be positioned alternately in the second direction (DR2). For example, relative to the first subpixel (SPX1), the second electrode (RME2) positioned to the left of the first electrode (RME1) may be the first electrode line (RML1), and the second electrode (RME2) positioned to the right of the first electrode (RME1) may be the second electrode line (RML2). In the second subpixel (SPX2), the second electrode (RME2) positioned to the left of the first electrode (RME1) may be the second electrode line (RML2), and the second electrode (RME2) positioned to the right may be the first electrode line (RML1). In the third subpixel (SPX3), the second electrode (RME2) positioned to the left of the first electrode (RME1) may be the first electrode line (RML1), and the second electrode (RME2) positioned to the right may be the second electrode line (RML2).

[0052] The width of the second direction (DR2) of the first electrode body portion (RMB1) may be greater than the width of the second direction (DR2) of the second electrode body portion (RMB2). The width of the second direction (DR2) of the first electrode extension portion (RMS1) may be the same as or different from the width of the second direction (DR2) of the second electrode extension portion (RMS2). The widths of the first electrode extension portion (RMS1) and the second electrode extension portion (RMS2) may be relatively small so that they can be placed between sub-regions (SA1, SA2), whereas the widths of the first electrode body portion (RMB1) and the second electrode body portion (RMB2) may be relatively large. The first electrode body portion (RMB1) and the second electrode body portion (RMB2) may each have a width greater than that of the first bank pattern (BP1) and the second bank pattern (BP2), and may be arranged to cover both sides of the first direction (DR1) and the second direction (DR2) of the first bank pattern (BP1) and the second bank pattern (BP2). The gap between the first bank pattern (BP1) and the second bank pattern (BP2) may be greater than the gap between the first electrode (RME1) and the second electrode (RME2). According to one embodiment, the maximum width of the electrode body portions (RMB1, RMB2) may be greater than the width of the bank pattern (BP1, BP2). The second electrode body portion (RBM2) may have a width greater than the portion extending in the first direction (DR1) of the bank layer (BNL).

[0053] While the first electrode (RME1) is positioned corresponding to one subpixel (SPXn), the second electrode (RME2) may have its second electrode body (RMB2) positioned across adjacent subpixels (SPXn). Subpixels (SPXn) adjacent in the second direction (DR2) may share the second electrode body (RMB2) of the second electrode (RME2).

[0054] In one embodiment, the second electrode body portion (RMB2) of the second electrode (RME2) may be positioned to cover the light-emitting regions (EMA) of adjacent subpixels (SPXn). A plurality of light-emitting elements (EDs) are positioned in each light-emitting region (EMA), and the light-emitting elements (EDs) may be positioned between the first bank pattern (BP1) and the second bank pattern (BP2). As described below, the light-emitting elements (EDs) may be positioned such that both ends are placed on the electrodes (RME1, RME2) by an electric field generated on the first electrode (RME1) and the second electrode (RME2) between the first bank pattern (BP1) and the second bank pattern (BP2).

[0055] The first electrode extension (RMS1) of the first electrode (RME1) can contact the first conductive pattern (CDP1) of the third conductive layer through the first electrode contact hole (CTD) in the first sub-region (SA1). The first electrode contact hole (CTD) can be non-overlapping with the bank layer (BNL). The second electrode extension (RMS2) of the second electrode (RME2) can contact the second conductive pattern (CDP2) of the third conductive layer through the second electrode contact hole (CTD) in the second sub-region (SA2). Although not illustrated, the first electrode (RME1) and the second electrode (RME2) may further include a contact portion connected to the connecting electrode (CNE) in the sub-regions (SA1, SA2).

[0056] The electrode extension portions (RMS1, RMS2) can connect electrode body portions (RMB1, RMB2) spaced apart in the first direction (DR1) so that the electrodes (RME1, RME2) extend in the first direction (DR1) across the display area (DPA). For example, the electrode extension portions (RMS1, RMS2) can extend the electrode body portion (RMB1, RMB2) of the i-th subpixel and the electrode body portion of the i+1-th subpixel. Accordingly, the first electrode (RME1) and the second electrode (RME2) can be extended across the first direction (DR1).

[0057] In the drawing, it is illustrated that one first electrode (RME1) is disposed for each subpixel (SPXn) and different second electrodes (RME2) are disposed, but is not limited thereto. For example, the display device (10) may have a larger number of electrodes (RME) disposed in one subpixel (SPXn), or the arrangement and shape of the electrodes (RME) may vary.

[0058] A bank layer (BNL) may be arranged to surround a plurality of subpixels (SPXn), a light-emitting region (EMA), and sub-regions (SA1, SA2). The bank layer (BNL) may be arranged between subpixels (SPXn) adjacent in a first direction (DR1) and a second direction (DR2), and may also be arranged between light-emitting regions (EMA). The bank layer (BNL) may be arranged between a first sub-region (SA1) and a light-emitting region (EMA), and between a second sub-region (SA2) and a light-emitting region (EMA). The subpixels (SPXn), the light-emitting region (EMA), and the sub-regions (SA1, SA2) of the display device (10) are regions separated by the arrangement of the bank layer (BNL), and may be regions opened by the bank layer (BNL). The spacing between multiple subpixels (SPXn), light-emitting regions (EMA), and sub-regions (SA1, SA2) may vary depending on the width of the bank layer (BNL).

[0059] The bank layer (BNL) may include a portion extending in a first direction (DR1) and a second direction (DR2) on a plane. The bank layer (BNL) includes a portion extending in the second direction (DR2) from the front of the display area (DPA), but the portion of the bank layer (BNL) extending in the first direction (DR1) may be spaced apart in the second direction (DR2) for each subpixel (SPXn). The bank layer (BNL) may be positioned across the boundary of the subpixels (SPXn) extended in the second direction (DR2) to distinguish neighboring subpixels (SPXn) in the second direction (DR2). The bank layer (BNL) may be spaced apart in the second direction (DR2) with the sub-regions (SA1, SA2) in between. The bank layer (BNL) may be positioned to surround the light-emitting area (EMA) placed for each subpixel (SPXn) to distinguish them. The bank layer (BNL) is positioned to surround sub-regions (SA1, SA2) that extend in a second direction (DR2) from the front of the display area (DPA) so as to distinguish them.

[0060] Light-emitting elements (EDs) may be placed in a light-emitting region (EMA). Light-emitting elements (EDs) may be placed between bank patterns (BP1, BP2) and arranged spaced apart from each other in a first direction (DR1). In one embodiment, the light-emitting elements (EDs) may have a shape that extends in one direction, and both ends may be placed on different electrodes (RMEs). The length of the light-emitting elements (EDs) may be longer than the spacing between the electrodes (RMEs) spaced apart in a second direction (DR2). The light-emitting elements (EDs) may generally be arranged such that their extended direction is perpendicular to the first direction (DR1) in which the electrodes (RMEs) extend. However, they are not limited thereto, and the extended direction of the light-emitting elements (EDs) may be arranged to face the second direction (DR2) or a direction inclined obliquely thereto.

[0061] A light-emitting element (ED) may include a first light-emitting element (ED1) with both ends disposed on either a first electrode (RME1) or a second electrode (RME2), and a second light-emitting element (ED2) with both ends disposed on the first electrode (RME1) and the other second electrode (RME2). With respect to a first subpixel (SPX1), the first light-emitting element (ED1) may be disposed on the second electrode (RME2) of the second electrode line (RML2), and the second light-emitting element (ED2) may be disposed on the second electrode (RME2) of the first electrode line (RML1). The first light-emitting elements (ED1) may be disposed to the right of the first electrode (RME1), and the second light-emitting elements (ED2) may be disposed to the left of the first electrode (RME1). The first light-emitting elements (ED1) and the second light-emitting elements (ED) are each placed on the first electrode (RME1) and the second electrode (RME2), respectively, and the second electrode (RME2) on which they are placed may be different from each other.

[0062] As the second electrode (RME2) is disposed in different subpixels (SPXn) including the second electrode body portion (RMB2), some of the light-emitting elements (ED) disposed in different subpixels (SPXn) may be disposed on the same second electrode (RME2). For example, one end of the first light-emitting element (ED1) of the first subpixel (SPX1) may be disposed on the second electrode (RME2) of the second electrode line (RM2), and one end of the second light-emitting element (ED2) of the second subpixel (SPX2) may also be disposed on the second electrode (RME2) of the second electrode line (RM2).

[0063] Connecting electrodes (CNE; CNE1, CNE2) can be placed on electrodes (RME) and bank patterns (BP1, BP2). Each connecting electrode (CNE) has a shape extending in one direction and can be spaced apart from each other. The connecting electrodes (CNE) can be in contact with a light-emitting element (ED) and can be electrically connected to an electrode (RME) or a conductive layer underneath it.

[0064] The connection electrodes (CNE) may include a first connection electrode (CNE1) and a second connection electrode (CNE2) placed in each subpixel (SPXn).

[0065] The first connecting electrode (CNE1) has a shape extending in a first direction (DR1) and can be disposed on the first electrode body portion (RMB1) of the first electrode (RME1). The first connecting electrode (CNE1) may include a first sub-connecting electrode (CNE11) and a second sub-connecting electrode (CNE12) disposed to overlap with the first bank pattern (BP1) and the first electrode (RME1). The first sub-connecting electrode (CNE11) may be disposed to the right of the first electrode (RME1), and the second sub-connecting electrode (CNE12) may be disposed to the left of the first electrode (RME1).

[0066] The second connecting electrode (CNE2) may be spaced apart from the first connecting electrode (CNE1) in the second direction (DR2) and may have a shape extending in the first direction (DR1) and may be disposed on the second electrode body portion (RMB2) of the second electrode (RME2). The second connecting electrode (CNE2) may include a third sub-connecting electrode (CNE21) and a fourth sub-connecting electrode (CNE22) disposed to overlap with the second bank pattern (BP2) and the second electrode (RME2). The third sub-connecting electrode (CNE21) is the second electrode (RME2) disposed to the right of the first electrode (RME1) and may be disposed on the second electrode line (RML2) with respect to the first sub-pixel (SPX1). The fourth sub-connecting electrode (CNE22) is a second electrode (RME2) positioned to the left of the first electrode (RME1), and can be positioned on the first electrode line (RML1) with respect to the first sub-pixel (SPX1).

[0067] Although not illustrated, the first sub-connecting electrode (CNE11) and the second sub-connecting electrode (CNE12) each further include a contact portion disposed in the sub-regions (SA1, SA2), and through the contact portion, they can contact the first electrode (RME1) or directly contact the lower conductive layer, the first conductive pattern (CDP1). Additionally, the third sub-connecting electrode (CNE21) and the fourth sub-connecting electrode (CNE22) each further include a contact portion disposed in the sub-regions (SA1, SA2), and through the contact portion, they can contact the second electrode (RME2) or directly contact the lower conductive layer, the second conductive pattern (CDP2).

[0068] FIG. 5 is a cross-sectional view taken along the line E1-E1' of FIG. 4. FIG. 6 is a cross-sectional view taken along the lines E2-E2' and E3-E3' of FIG. 4.

[0069] Referring to FIGS. 5 and 6 in addition to FIGS. 3 and 4, the display device (10) may include a first substrate (SUB) and a semiconductor layer disposed thereon, a plurality of conductive layers, and a plurality of insulating layers. Additionally, the display device (10) may include a plurality of electrodes (RME: RME1, RME2), a light-emitting element (ED: ED1, ED2), and a connecting electrode (CNE: CNE1, CNE2). The semiconductor layer, the conductive layer, and the insulating layer may each constitute a circuit layer of the display device (10).

[0070] The first substrate (SUB) may be an insulating substrate. The first substrate (SUB) may be made of an insulating material such as glass, quartz, or a polymer resin. Additionally, the first substrate (SUB) may be a rigid substrate, but may also be a flexible substrate capable of bending, folding, rolling, etc. The first substrate (SUB) includes a display area (DPA) and a non-display area (NDA) surrounding it, and the display area (DPA) may include a light-emitting area (EMA) and sub-areas (SA1, SA2) that are part of the non-light-emitting area.

[0071] The first conductive layer may be disposed on the first substrate (SUB). The first conductive layer may include a lower metal layer (BML), a first voltage line (VL1), and a second voltage line (VL2). The lower metal layer (BML) is disposed to overlap with the first active layer (ACT1) of the first transistor (T1). The lower metal layer (BML) may perform the function of preventing light from being incident on the first active layer (ACT1) of the first transistor, or electrically connecting to the first active layer (ACT1) to stabilize the electrical characteristics of the first transistor (T1). However, the lower metal layer (BML) may be omitted.

[0072] A high potential voltage (or a first power supply voltage) delivered to the first electrode (RME1) may be applied to the first voltage wiring (VL1), and a low potential voltage (or a second power supply voltage) delivered to the second electrode (RME2) may be applied to the second voltage wiring (VL2). The first voltage wiring (VL1) may be electrically connected to the first transistor (T1) through a conductive pattern of the third conductive layer (e.g., a third conductive pattern (CDP3)). The second voltage wiring (VL2) may be electrically connected to the second electrode (RME2) through a conductive pattern of the third conductive layer (e.g., a second conductive pattern (CDP2)).

[0073] In the drawings, the first voltage line (VL1) and the second voltage line (VL2) are illustrated as being disposed in the first conductive layer, but are not limited thereto. In some embodiments, the first voltage line (VL1) and the second voltage line (VL2) may be disposed in the third conductive layer and directly electrically connected to the first transistor (T1) and the second electrode (RME2), respectively.

[0074] A buffer layer (BL) may be disposed on a first conductive layer and a first substrate (SUB). The buffer layer (BL) is formed on the first substrate (SUB) to protect the transistors of the pixel (PX) from moisture penetrating through the first substrate (SUB), which is susceptible to moisture permeability, and can perform a surface planarization function.

[0075] The semiconductor layer is disposed on the buffer layer (BL). The semiconductor layer may include a first active layer (ACT1) of the first transistor (T1) and a second active layer (ACT2) of the second transistor (T2). The first active layer (ACT1) and the second active layer (ACT2) may be disposed to partially overlap with the first gate electrode (G1) and the second gate electrode (G2) of the second conductive layer, respectively, which will be described later.

[0076] The semiconductor layer may include polycrystalline silicon, single-crystal silicon, oxide semiconductors, etc. In another embodiment, the semiconductor layer may include polycrystalline silicon. The oxide semiconductor may be an oxide semiconductor containing indium (In). For example, the oxide semiconductor may be at least one of indium tin oxide (ITO), indium zinc oxide (IZO), indium gallium oxide (IGO), indium zinc tin oxide (IZTO), indium gallium tin oxide (IGTO), indium gallium zinc oxide (IGZO), and indium gallium zinc tin oxide (IGZTO).

[0077] In the drawing, a first transistor (T1) is illustrated in the subpixel (SPXn) of the display device (10), but the display device (10) is not limited thereto and may include a larger number of transistors.

[0078] The first gate insulating layer (GI) is disposed on the semiconductor layer in the display area (DPA). The first gate insulating layer (GI) can serve as the gate insulating film for each transistor (T1, T2). In the drawings, the first gate insulating layer (GI) is illustrated as being patterned together with the gate electrodes (G1, G2) of the second conductive layer described later and partially disposed between the second conductive layer and the active layer (ACT1, ACT2) of the semiconductor layer, but is not limited thereto. In some embodiments, the first gate insulating layer (GI) may be disposed entirely on the buffer layer (BL).

[0079] The second conductive layer is disposed on the first gate insulating layer (GI). The second conductive layer may include a first gate electrode (G1) of the first transistor (T1) and a second gate electrode (G2) of the second transistor (T2). The first gate electrode (G1) may be disposed to overlap the channel region of the first active layer (ACT1) in the third direction (DR3), which is the thickness direction, and the second gate electrode (G2) may be disposed to overlap the channel region of the second active layer (ACT2) in the third direction (DR3), which is the thickness direction. Although not shown in the drawing, the second conductive layer may further include one electrode of the storage capacitor.

[0080] The first interlayer insulating layer (IL1) is disposed on the second conductive layer. The first interlayer insulating layer (IL1) functions as an insulating film between the second conductive layer and other layers disposed thereon, and can protect the second conductive layer.

[0081] A third conductive layer is disposed on the first interlayer insulating layer (IL1). The third conductive layer may include a plurality of conductive patterns (CDP1, CDP2, CDP3) and source electrodes (S1, S2) and drain electrodes (D1, D2) of each transistor (T1, T2). Some of the conductive patterns (CDP1, CDP2, CDP3) electrically connect conductive layers or semiconductor layers of different layers to each other and may serve as source / drain electrodes of transistors (T1, T2).

[0082] The first conductive pattern (CDP1) can contact the first active layer (ACT1) of the first transistor (T1) through a contact hole penetrating the first interlayer insulating layer (IL1). The first conductive pattern (CDP1) can contact the lower metal layer (BML) through a contact hole penetrating the first interlayer insulating layer (IL1) and the buffer layer (BL). The first conductive pattern (CDP1) can serve as the first source electrode (S1) of the first transistor (T1). The first conductive pattern (CDP1) can be electrically connected to the first electrode (RME1) or the first connection electrode (CNE1). The first transistor (T1) can transmit the first power supply voltage applied from the first voltage wiring (VL1) to the first electrode (RME1) or the first connection electrode (CNE1).

[0083] The second conductive pattern (CDP2) can contact the second voltage wiring (VL2) through a contact hole penetrating the first interlayer insulating layer (IL1) and the buffer layer (BL). The second conductive pattern (CDP2) can be electrically connected to the first electrode (RME1) or the first connecting electrode (CNE1). The second voltage wiring (VL2) can transmit the second power supply voltage to the second electrode (RME2) or the second connecting electrode (CNE2).

[0084] The third conductive pattern (CDP3) can contact the first voltage wiring (VL1) through a contact hole penetrating the first interlayer insulating layer (IL1) and the buffer layer (BL). Additionally, the third conductive pattern (CDP3) can contact the first active layer (ACT1) of the first transistor (T1) through a contact hole penetrating the first interlayer insulating layer (IL1). The third conductive pattern (CDP3) electrically connects the first voltage wiring (VL1) to the first transistor (T1) and can serve as the first drain electrode (D1) of the first transistor (T1).

[0085] The second source electrode (S2) and the second drain electrode (D2) can each contact the second active layer (ACT2) of the second transistor (T2) through a contact hole penetrating the first interlayer insulating layer (IL1). The second transistor (T2) can transmit a data signal to the first transistor (T1) or transmit an initialization signal.

[0086] The first protective layer (PV1) is disposed on the third conductive layer. The first protective layer (PV1) functions as an insulating film between the third conductive layer and other layers and can protect the third conductive layer.

[0087] The above-described buffer layer (BL), first gate insulating layer (GI), first interlayer insulating layer (IL1), and first protective layer (PV1) may be composed of a plurality of inorganic layers stacked alternately. For example, the buffer layer (BL), first gate insulating layer (GI), first interlayer insulating layer (IL1), and first protective layer (PV1) may be silicon oxide (SiO₂). x ), Silicon Nitride (SiN x ), Silicon Oxynitride (SiO₂ x N y It may be formed into a double layer in which an inorganic layer comprising at least one of ) is stacked, or a multilayer in which the same is stacked alternately. However, it is not limited thereto, and the buffer layer (BL), the first gate insulating layer (GI), the first interlayer insulating layer (IL1), and the first protective layer (PV1) may be formed into a single inorganic layer including the insulating material described above. In addition, in some embodiments, the first interlayer insulating layer (IL1) may be made of an organic insulating material such as polyimide (PI).

[0088] A via layer (VIA) is disposed on a third conductive layer in a display area (DPA). The via layer (VIA) may comprise an organic insulating material, such as polyimide (PI), to compensate for the step difference caused by the underlying conductive layers and to form a flat upper surface. However, in some embodiments, the via layer (VIA) may be omitted.

[0089] A display device (10) may include a display element layer disposed on a via layer (VIA), bank patterns (BP1, BP2), a plurality of electrodes (RME: RME1, RME2), a bank layer (BNL), a plurality of light-emitting elements (ED), and a plurality of connecting electrodes (CNE: CNE1, CNE2). Additionally, the display device (10) may include insulating layers (PAS1, PAS2, PAS3) disposed on the via layer (VIA).

[0090] Multiple bank patterns (BP1, BP2) may be disposed on a via layer (VIA). For example, bank patterns (BP1, BP2) may be disposed directly on the via layer (VIA) and may have a structure in which at least a portion protrudes with respect to the upper surface of the via layer (VIA). The protruding portion of the bank patterns (BP1, BP2) may have a side that is inclined or bent with a certain curvature, and light emitted from the light-emitting element (ED) may be reflected from the electrode (RME) disposed on the bank patterns (BP1, BP2) and emitted in the direction of the upper side of the via layer (VIA). Unlike as illustrated in the drawings, the bank patterns (BP1, BP2) may have a shape in which the outer surface in the cross-sectional view is bent with a certain curvature, such as a semicircle or a semi-ellipse. The bank patterns (BP1, BP2) may include an organic insulating material such as polyimide (PI), but are not limited thereto.

[0091] A plurality of electrodes (RME: RME1, RME2) may be disposed on bank patterns (BP1, BP2) and via layers (VIA). The first electrode (RME1) and the second electrode (RME2) may be disposed on at least the inclined sides of the bank patterns (BP1, BP2). For example, the width of the first electrode (RME1) and the second electrode (RME2), each measured in the second direction (DR2), may be greater than that of the first bank pattern (BP1) and the second bank pattern (BP2), and the first electrode (RME1) and the second electrode (RME2) may cover the inclined sides of the first bank pattern (BP1) and the second bank pattern (BP2). In the drawing, the second electrode (RME2) is illustrated as covering one side of the second bank pattern (BP2) that is placed within the light-emitting region (EMA), but the second electrode (RME2) may also cover another side of the second bank pattern (BP2) that is placed in the light-emitting region (EMA) of an adjacent subpixel (SPXn). The first electrode (RME1) placed on the first bank pattern (BP1) may be the first electrode body (RMB1), and the second electrode (RME2) placed on the second bank pattern (BP2) may be the second electrode body (RMB2).

[0092] The spacing between the first electrode (RME1) and the second electrode (RME2) in the second direction (DR2) may be narrower than the spacing between bank patterns (BP1, BP2). At least some regions of the first electrode (RME1) and the second electrode (RME2) may be placed directly on the via layer (VIA) so that they can be placed on the same plane.

[0093] A light-emitting element (ED) disposed between bank patterns (BP1, BP2) emits light in both end directions, and the emitted light can be directed toward an electrode (RME) disposed on the bank patterns (BP1, BP2). Each electrode (RME) may have a structure in which a portion disposed on the bank patterns (BP1, BP2) can reflect the light emitted from the light-emitting element (ED). The first electrode (RME1) and the second electrode (RME2) are disposed to cover at least one side of the bank patterns (BP1, BP2) so as to reflect the light emitted from the light-emitting element (ED).

[0094] Each electrode (RME) can contact a third conductive layer through electrode contact holes (CTD, CTS) in sub-regions (SA1, SAA2). A first electrode contact hole (CTD) may be formed in a first sub-region (SA1), and a second electrode contact hole (CTS) may be formed in a second sub-region (SA2). A first electrode (RME1) placed in the first electrode contact hole (CTD) may be a first electrode extension (RMS1), and a second electrode (RME2) placed in the second electrode contact hole (CTS) may be a second electrode extension (RMS2).

[0095] The first electrode (RME1) can be in contact with the first conductive pattern (CDP1) through a first electrode contact hole (CTD) penetrating the via layer (VIA) and the first protective layer (PV1). The second electrode (RME2) can be in contact with the second conductive pattern (CDP2) through a second electrode contact hole (CTS) penetrating the via layer (VIA) and the first protective layer (PV1). The first electrode (RME1) can be electrically connected to the first transistor (T1) through the first conductive pattern (CDP1) to apply the first power supply voltage, and the second electrode (RME2) can be electrically connected to the second voltage wiring (VL2) through the second conductive pattern (CDP2) to apply the second power supply voltage. However, it is not limited thereto. In another embodiment, each electrode (RME1, RME2) may not be electrically connected to the voltage wiring (VL1, VL2) of the third conductive layer, and the connecting electrode (CNE) described below may be directly connected to the third conductive layer.

[0096] Multiple electrodes (RMEs) may include a highly reflective conductive material. For example, the electrodes (RMEs) may include a metal such as silver (Ag), copper (Cu), aluminum (Al), an alloy such as aluminum (Al), nickel (Ni), lanthanum (La), or a structure in which a metal layer such as titanium (Ti), molybdenum (Mo), and niobium (Nb) is stacked with said alloy. In some embodiments, the electrodes (RMEs) may be composed of a double layer or a multilayer structure in which an alloy containing aluminum (Al) and at least one metal layer consisting of titanium (Ti), molybdenum (Mo), and niobium (Nb) are stacked.

[0097] Each electrode (RME) may further include a transparent conductive material, without being limited thereto. For example, each electrode (RME) may include a material such as ITO, IZO, ITZO, etc. In some embodiments, each electrode (RME) may have a structure in which a transparent conductive material and a highly reflective metal layer are each stacked one or more times, or may be formed as a single layer including these. For example, each electrode (RME) may have a stacked structure such as ITO / Ag / ITO / , ITO / Ag / IZO, or ITO / Ag / ITZO / IZO. The electrodes (RME) are electrically connected to a light-emitting element (ED) and may reflect some of the light emitted from the light-emitting element (ED) toward the upper direction of the first substrate (SUB).

[0098] The first insulating layer (PAS1) may be disposed on a via layer (VIA) and a plurality of electrodes (RME). The first insulating layer (PAS1) may include an insulating material to protect the plurality of electrodes (RME) while simultaneously insulating different electrodes (RME) from each other. Since the first insulating layer (PAS1) is disposed to cover the electrodes (RME) before the bank layer (BNL) is formed, the electrodes (RME) may be prevented from being damaged during the process of forming the bank layer (BNL). Additionally, the first insulating layer (PAS1) may prevent a light-emitting element (ED) disposed thereon from being damaged by direct contact with other components.

[0099] In an exemplary embodiment, the first insulating layer (PAS1) may have a step formed such that a portion of its upper surface is recessed between electrodes (RME) spaced apart in the second direction (DR2). A light-emitting element (ED) is disposed on the upper surface of the first insulating layer (PAS1) where the step is formed, and a space may be formed between the light-emitting element (ED) and the first insulating layer (PAS1).

[0100] A bank layer (BNL) may be disposed on a first insulating layer (PAS1). The bank layer (BNL) may include a portion extending in a first direction (DR1) and a second direction (DR2) and may surround each subpixel (SPXn). The bank layer (BNL) may surround and distinguish the light-emitting region (EMA) and sub-region (SA) of each subpixel (SPXn), and may surround the outermost edge of the display region (DPA) and distinguish the display region (DPA) from the non-display region (NDA).

[0101] The bank layer (BNL) may have a certain height similar to the bank pattern (BP1, BP2). A portion of the bank layer (BNL) may include a portion that overlaps with the bank pattern (BP1, BP2) and the electrode (RME1, RME2). In some embodiments, the height of the upper surface of the bank layer (BNL) may be higher than that of the bank pattern (BP1, BP2), and its thickness may be equal to, greater than, or smaller than that of the bank pattern (BP1, BP2). The bank layer (BNL) can prevent ink from overflowing into adjacent subpixels (SPXn) during the inkjet printing process in the manufacturing process of the display device (10). The bank layer (BNL) may include an organic insulating material such as polyimide or polyamide.

[0102] Light-emitting elements (EDs) may be placed in a light-emitting region (EMA). Light-emitting elements (EDs) may be placed on a first insulating layer (PAS1) between bank patterns (BP1, BP2). Light-emitting elements (EDs) may be placed such that one extended direction is parallel to the upper surface of the first substrate (SUB). As described below, the light-emitting elements (EDs) may include a plurality of semiconductor layers arranged along the one extended direction, and the plurality of semiconductor layers may be arranged sequentially along a direction parallel to the upper surface of the first substrate (SUB). However, not limited thereto, if the light-emitting elements (EDs) have a different structure, the plurality of semiconductor layers may be arranged in a direction perpendicular to the first substrate (SUB).

[0103] The light-emitting elements (EDs) placed in each subpixel (SPXn) can emit light of different wavelengths depending on the material of the semiconductor layer described above. However, not limited thereto, the light-emitting elements (EDs) placed in each subpixel (SPXn) may include a semiconductor layer of the same material and emit light of the same color.

[0104] Light-emitting elements (EDs) can be placed on different electrodes (RMEs) between different bank patterns (BP1, BP2). A first light-emitting element (ED1) can be placed between the first bank pattern (BP1) and the second bank pattern (BP2), with both ends placed on the first electrode body portion (RMB1) of the first electrode (RME1) and the second electrode body portion (RMB2) of the second electrode (RME2). With respect to the first subpixel (SPX1), the first light-emitting element (ED1) can be placed on the second electrode line (RML2) of the second electrode (RME2) and placed to the right of the first bank pattern (BP1) in the light-emitting region (EMA). The second light-emitting element (ED2) is positioned between the second bank pattern (BP2) and the first bank pattern (BP1), and both ends may be positioned on the first electrode body portion (RMB1) of the first electrode (RME1) and the second electrode body portion (RMB2) of the second electrode (RME2). Based on the first subpixel (SPX1), the second light-emitting element (ED2) is positioned on the first electrode line (RML1) of the second electrode (RME2) and may be positioned to the left of the first bank pattern (BP1) in the light-emitting region (EMA).

[0105] The light-emitting elements (EDs) can be electrically connected to the conductive layers under the electrode (RME) and via layer (VIA) by contacting the connecting electrodes (CNE: CNE1, CNE2, CNE3), and can emit light of a specific wavelength range when an electrical signal is applied.

[0106] A second insulating layer (PAS2) may be disposed on a plurality of light-emitting elements (ED), a first insulating layer (PAS1), and a bank layer (BNL). The second insulating layer (PAS2) includes a pattern portion that extends in a first direction (DR1) between bank patterns (BP1, BP2) and is disposed on a plurality of light-emitting elements (ED). The pattern portion is disposed to partially cover the outer surface of the light-emitting element (ED), and may not cover both sides or both ends of the light-emitting element (ED). The pattern portion may form a linear or island pattern within each subpixel (SPXn) in a planar view. The pattern portion of the second insulating layer (PAS2) can protect the light-emitting element (ED) and, at the same time, fix the light-emitting elements (ED) during the manufacturing process of the display device (10). Additionally, the second insulating layer (PAS2) may be disposed to fill the space between the light-emitting element (ED) and the first insulating layer (PAS1) below it. Additionally, a portion of the second insulating layer (PAS2) may be placed on the upper part of the bank layer (BNL) and in the sub-regions (SA1, SA2).

[0107] Multiple connecting electrodes (CNE: CNE1, CNE2) can be placed on electrodes (RME) and bank patterns (BP1, BP2).

[0108] The first connecting electrode (CNE1) may be placed on the first electrode (RME1) and the first bank pattern (BP1). The first sub-connecting electrode (CNE11) of the first connecting electrode (CNE1) may be placed on the upper right side of the first electrode (RME1) and the first bank pattern (BP1). The second sub-connecting electrode (CNE12) may be placed on the upper left side of the first electrode (RME1) and the first bank pattern (BP1).

[0109] The second connecting electrode (CNE2) may be placed on the second electrode (RME2) and the second bank pattern (BP2). The third sub-connecting electrode (CNE21) of the second connecting electrode (CNE2) may be placed on the second electrode line (RML2) and the second bank pattern (BP2) as the second electrode (RME2) placed to the right of the first electrode (RME1). The fourth sub-connecting electrode (CNE22) may be placed on the first electrode line (RML1) and the second bank pattern (BP2) as the second electrode (RME2) placed to the left of the first electrode (RME1).

[0110] The first connecting electrode (CNE1) and the second connecting electrode (CNE2) are each disposed on the second insulating layer (PAS2) and can come into contact with light-emitting elements (ED). The first connecting electrode (CNE1) can come into contact with the first end of the light-emitting elements (ED1, ED2). The first sub-connecting electrode (CNE11) can come into contact with the first end of the first light-emitting elements (ED1), and the second sub-connecting electrode (CNE12) can come into contact with the first end of the second light-emitting elements (ED2). The second connecting electrode (CNE2) can come into contact with the second end of the light-emitting elements (ED1, ED2). The third sub-connecting electrode (CNE21) can come into contact with the second end of the first light-emitting elements (ED1), and the fourth sub-connecting electrode (CNE22) can come into contact with the second end of the second light-emitting elements (ED2).

[0111] Connecting electrodes (CNEs) may include a conductive material. For example, they may include ITO, IZO, ITZO, aluminum (Al), etc. As an example, the connecting electrode (CNE) may include a transparent conductive material, and light emitted from the light-emitting element (ED) may pass through the connecting electrode (CNE) and be emitted.

[0112] A third insulating layer (PAS3) is disposed on the connecting electrodes (CNE1, CNE2) and the second insulating layer (PAS2). The third insulating layer (PAS3) can insulate the first connecting electrode (CNE1) and the second connecting electrode (CNE2) from each other so that they do not come into direct contact.

[0113] The first insulating layer (PAS1), the second insulating layer (PAS2), and the third insulating layer (PAS3) described above may each comprise an inorganic insulating material or an organic insulating material. For example, the first insulating layer (PAS1), the second insulating layer (PAS2), and the third insulating layer (PAS3) may each comprise an inorganic insulating material, or the first insulating layer (PAS1) and the third insulating layer (PAS3) may comprise an inorganic insulating material, while the second insulating layer (PAS2) may comprise an organic insulating material. The first insulating layer (PAS1), the second insulating layer (PAS2), and the third insulating layer (PAS3) may each, or at least one of them, be formed in a structure in which a plurality of insulating layers are stacked alternately or repeatedly. In an exemplary embodiment, when the first insulating layer (PAS1), the second insulating layer (PAS2), and the third insulating layer (PAS3) comprise an inorganic insulating material, they may each be silicon oxide (SiO₂). x ), silicon nitride (SiN x ), silicon oxynitride (SiO₂ x N y ), and hafnium oxide (HfO₂) x It may be any one of the following. When the first insulating layer (PAS1), the second insulating layer (PAS2), and the third insulating layer (PAS3) include an organic insulating material, they may each be an acrylic resin, a urethane resin, an epoxy resin, or a polyimide resin.

[0114] The first insulating layer (PAS1), the second insulating layer (PAS2), and the third insulating layer (PAS3) may be made of the same material, or part of them may be made of the same material and part of them may be made of different material, or each may be made of different material.

[0115] FIG. 7 is a schematic diagram of a light-emitting element according to one embodiment.

[0116] Referring to FIG. 7, the light-emitting element (ED) may be a light-emitting diode, and specifically, the light-emitting element (ED) may be an inorganic light-emitting diode made of inorganic material having a size in the nanometer to micrometer range. The light-emitting element (ED) may be aligned between two electrodes that form polarity when an electric field is formed in a specific direction between the two electrodes facing each other.

[0117] A light-emitting element (ED) according to one embodiment may have a shape that extends in one direction. The light-emitting element (ED) may have a shape such as a cylinder, a rod, a wire, or a tube. However, the shape of the light-emitting element (ED) is not limited thereto, and the light-emitting element (ED) may have various shapes, such as a polygonal prism shape like a cube, a rectangular prism, or a hexagonal prism, or a shape that extends in one direction but has a partially inclined outer surface.

[0118] The light-emitting element (ED) may include a semiconductor layer doped with any conductivity type (e.g., p-type or n-type) dopant. The semiconductor layer may emit light of a specific wavelength range when an electrical signal applied from an external power source is transmitted. The light-emitting element (ED) may include a first semiconductor layer (31), a second semiconductor layer (32), a light-emitting layer (36), an electrode layer (37), and an insulating film (38).

[0119] The first semiconductor layer (31) may be an n-type semiconductor. The first semiconductor layer (31) is Al x Ga y In 1-x-yIt may include a semiconductor material having the chemical formula N (0≤x≤1, 0≤y≤1, 0≤x+y≤1). For example, the first semiconductor layer (31) may be one or more of AlGaInN, GaN, AlGaN, InGaN, AlN, and InN doped with an n-type dopant. The n-type dopant doped in the first semiconductor layer (31) may be Si, Ge, Sn, Se, etc.

[0120] The second semiconductor layer (32) is disposed on the first semiconductor layer (31) with the light-emitting layer (36) in between. The second semiconductor layer (32) may be a p-type semiconductor, and the second semiconductor layer (32) is Al x Ga y In 1-x-y It may include a semiconductor material having the chemical formula N (0≤x≤1, 0≤y≤1, 0≤x+y≤1). For example, the second semiconductor layer (32) may be one or more of AlGaInN, GaN, AlGaN, InGaN, AlN, and InN doped with a p-type dopant. The p-type dopant doped in the second semiconductor layer (32) may be Mg, Zn, Ca, Ba, etc.

[0121] Meanwhile, the drawing shows the first semiconductor layer (31) and the second semiconductor layer (32) as being composed of a single layer, but is not limited thereto. Depending on the material of the light-emitting layer (36), the first semiconductor layer (31) and the second semiconductor layer (32) may further include a greater number of layers, such as a clad layer or a TSBR (Tensile strain barrier reducing) layer. For example, the light-emitting device (ED) may further include other semiconductor layers disposed between the first semiconductor layer (31) and the light-emitting layer (36), or between the second semiconductor layer (32) and the light-emitting layer (36). The semiconductor layer disposed between the first semiconductor layer (31) and the light-emitting layer (36) may be one or more of AlGaInN, GaN, AlGaN, InGaN, AlN, InN and SLs doped with an n-type dopant, and the semiconductor layer disposed between the second semiconductor layer (32) and the light-emitting layer (36) may be one or more of AlGaInN, GaN, AlGaN, InGaN, AlN and InN doped with a p-type dopant.

[0122] The light-emitting layer (36) is disposed between the first semiconductor layer (31) and the second semiconductor layer (32). The light-emitting layer (36) may include a material having a single or multiple quantum well structure. If the light-emitting layer (36) includes a material having a multiple quantum well structure, it may have a structure in which a quantum layer and a well layer are alternately stacked in multiple layers. The light-emitting layer (36) can emit light by the coupling of electron-hole pairs according to an electric signal applied through the first semiconductor layer (31) and the second semiconductor layer (32). The light-emitting layer (36) may include materials such as AlGaN, AlGaInN, InGaN, etc. In particular, if the light-emitting layer (36) has a structure in which quantum layers and well layers are alternately stacked in a multiple quantum well structure, the quantum layer may include a material such as AlGaN or AlGaInN, and the well layer may include a material such as GaN or AlInN.

[0123] The light-emitting layer (36) may have a structure in which semiconductor materials with large band gap energy and semiconductor materials with small band gap energy are alternately stacked, and may include different group 3 to group 5 semiconductor materials depending on the wavelength range of the light emitted. The light emitted by the light-emitting layer (36) is not limited to light in the blue wavelength range, and may emit light in the red or green wavelength range depending on the case.

[0124] The electrode layer (37) may be an ohmic connection electrode. However, it is not limited thereto and may be a Schottky connection electrode. The light-emitting element (ED) may include at least one electrode layer (37). The light-emitting element (ED) may include one or more electrode layers (37), but is not limited thereto and the electrode layer (37) may be omitted.

[0125] The electrode layer (37) can reduce the resistance between the light-emitting element (ED) and the electrode or connecting electrode when the light-emitting element (ED) in the display device (10) is electrically connected to the electrode or connecting electrode. The electrode layer (37) may include a conductive metal. For example, the electrode layer (37) may include at least one of aluminum (Al), titanium (Ti), indium (In), gold (Au), silver (Ag), ITO, IZO, and ITZO.

[0126] The insulating film (38) is arranged to surround the outer surface of the plurality of semiconductor layers and electrode layers described above. For example, the insulating film (38) may be arranged to surround the outer surface of at least the light-emitting layer (36), but may be formed so that both ends in the longitudinal direction of the light-emitting element (ED) are exposed. Additionally, the insulating film (38) may be formed with a rounded upper surface in cross-section in an area adjacent to at least one end of the light-emitting element (ED).

[0127] The insulating film (38) is made of materials having insulating properties, for example, silicon oxide (SiO₂). x ), silicon nitride (SiN x), silicon oxynitride (SiO₂ x N y ), aluminum nitride (AlN x ), aluminum oxide (AlO x ), zirconium oxide (ZrO x ), hafnium oxide (HfO x ), and titanium oxide (TiO₂ x It may include at least one of ). In the drawings, the insulating film (38) is illustrated as being formed as a single layer, but is not limited thereto, and in some embodiments, the insulating film (38) may be formed as a multilayer structure in which a plurality of layers are stacked.

[0128] The insulating film (38) can perform the function of protecting the semiconductor layers and electrode layers of the light-emitting element (ED). The insulating film (38) can prevent an electrical short circuit that may occur in the light-emitting layer (36) when in direct contact with the electrode through which an electrical signal is transmitted to the light-emitting element (ED). In addition, the insulating film (38) can prevent a decrease in the light-emitting efficiency of the light-emitting element (ED).

[0129] Additionally, the outer surface of the insulating film (38) may be surface-treated. The light-emitting element (ED) may be sprayed onto the electrode and aligned in a dispersed state within a predetermined ink. Here, in order for the light-emitting element (ED) to remain dispersed without aggregating with other adjacent light-emitting elements (ED) within the ink, the surface of the insulating film (38) may be treated to be hydrophobic or hydrophilic.

[0130] FIG. 8 is an enlarged plan view of A in FIG. 3. FIG. 9 is a cross-sectional view taken along the line E4-E4' in FIG. 8. FIG. 10 is an enlarged plan view of B in FIG. 3. FIG. 11 is a cross-sectional view taken along the line E5-E5' in FIG. 10.

[0131] Referring to FIGS. 8 to 11, a bank layer (BNL) of a display device (10) according to one embodiment may overlap with electrode body portions (RMB1, RMB2) in a third direction (DR3) by a first width (W1). FIGS. 8 and 9 illustrate a bank layer (BNL) arranged to cover a second electrode body portion (RMB2) and a first electrode extension portion (RMS1), and FIGS. 10 and 11 illustrate a bank layer (BNL) arranged to cover a first electrode body portion (RBM1) and a second electrode extension portion (RMS2).

[0132] The bank layer (BNL) can overlap with the electrode extension portions (RMS1, RMS2) and can be arranged to overlap with the electrode body portions (RMB1, RMB2) by a first width (W1). For example, the first width (W1) may be 7 µm or more. By being arranged to cover the electrode body portions (RMB1, RMB2) by the first width (W1), the bank layer (BNL) can reduce the electric field (IEI) generated at one end of the electrode body portions (RMB1, RMB2) and one end of the electrode extension portions (RMS1, RMS2).

[0133] According to one embodiment, in a sub-region (SA1, SA2) comprising contact holes (e.g., electrode contact holes (CTS, CTD)) that transmit electrical signals to a plurality of sub-pixels (SPXn), electrode extension portions (RMS1, RMS2) may be disposed having at least a portion that is bent or extends diagonally in a tilted direction from a first direction (DR1) or a second direction (DR2). One end of the electrode extension portion (RMS1, RMS2) and one end of the electrode body portion (RMB1, RMB2) may be disposed in close proximity to the upper or lower part of the light-emitting region (EMA). When an electric field (IEI) is formed between the first electrode (RME1) and the second electrode (RME2), to which different signals are applied at the upper or lower part of the light-emitting region (EMA) where one end of the electrode extension portion (RMS1, RMS2) and one end of the electrode body portion (RMB1, RMB2) come close together, the light-emitting elements (ED) can be arranged clustered in the upper and lower parts of the light-emitting region (EMA). That is, the light-emitting elements (ED) can be arranged outside the alignment region (LP) where the light-emitting elements (ED) are aligned. Here, the alignment region (LP) is an area or path where the light-emitting elements (ED) are aligned, and may be an area included in the light-emitting region (EMA) partitioned by the bank layer (BNL). The alignment region (LP) may correspond to the area between the first electrode (RME1) and the second electrode (RME2) within the light-emitting region (EMA).

[0134] The bank layer (BNL) can be overlapped to cover one end of the electrode body portion (RMB1, RMB2) and one end of the electrode extension portion (RMS1, RMS2). Accordingly, the bank layer (BNL) can reduce the electric field generated at one end of the electrode body portion (RMB1, RMB2) and one end of the electrode extension portion (RMS1, RMS2).

[0135] The bank layer (BNL) may include an organic insulating material as described above. The bank layer (BNL) may include an organic insulating material with a dielectric constant of 2 to 4, for example, polyimide (PI) or polyamide (PA). By including an organic material with a high dielectric constant, the bank layer (BNL) can act as a dielectric that reduces the electric field (IEI) generated from the electrode body portion (RMB1, RMB2) and the electrode extension portion (RMS1, RMS2). The bank layer (BNL) can prevent light-emitting elements (ED) from being clustered and arranged on the upper or lower part of the light-emitting region (EMA) outside the alignment region (LP) of the light-emitting region (EMA).

[0136] For example, referring to FIGS. 8 and 9, the first electrode extension (RMS1) may include a portion that bends diagonally from the first direction (DR1) toward the second electrode body (RMB2). When a bank layer (BNL) overlapping with one end of the first electrode extension (RMS1) and one end of the second electrode body (RMB2) are disposed in close proximity to each other, it is possible to prevent an electric field (IEI) from being formed between the one end of the first electrode extension (RMS1) receiving the first power supply voltage and the one end of the second electrode body (RMB2) receiving the second power supply voltage. Accordingly, the bank layer (BNL) can prevent the light-emitting elements (ED) from moving out of the alignment area (LP) due to the electric field (IEI) and being clustered in the upper and lower parts of the light-emitting area (EMA). Accordingly, the dark spot of the display device (10) can be improved.

[0137] Additionally, referring to FIGS. 10 and FIGS. 11, the second electrode extension (RMS2) may include a portion that bends diagonally from the first direction (DR1) toward the first electrode body (RMB1). When a bank layer (BNL) that overlaps with one end of the second electrode extension (RMS2) and one end of the first electrode body (RMB1) are disposed in close proximity to each other, it is possible to prevent an electric field (IEI) from being formed between the second electrode extension (RMS2) and the first electrode body (RMB1) which receive different voltages. Accordingly, the bank layer (BNL) can prevent the light-emitting elements (ED) from moving out of the alignment region (LP) due to the electric field (IEI) and being clustered in the upper and lower parts of the light-emitting region (EMA).

[0138] A bank layer (BNL) may be disposed on electrodes (RME1, RME2), a first insulating layer (PAS1), and bank patterns (BP1, BP2) with a predetermined thickness. The bank layer (BNL) may have a certain height. The bank layer (BNL) may include a first region that does not overlap with the bank patterns (BP1, BP2) and a second region that overlaps with the bank patterns (BP1, BP2). Since the upper surface of the bank layer (BNL) is generally flat, the thickness may differ between the first region and the second region. The bank layer (BNL) may have a first thickness (TH1) in the first region and a second thickness in the second region. The first thickness (TH1) may be the maximum thickness of the bank layer (BNL), and the second thickness may be the minimum thickness of the bank layer (BNL), but is not limited thereto. The first thickness (TH1) of the bank layer (BNL) may be 1 µm or more, and in particular, if it is 2 µm or more, the electric field (IEI) between the electrodes (RME1, RME2) can be effectively reduced. This is explained in detail with reference to FIG. 14. The second thickness of the bank layer (BNL) may be smaller than the first thickness (TH1). For example, the second thickness of the bank layer (BNL) may be 2 µm or less. The bank layer (BNL) may have different thicknesses to compensate for the step difference between the first region and the second region. However, it is not limited thereto, and the thickness of the bank layer (BNL) may be the same in the first region and the second region, and the upper surface of the first region may be higher than the upper surface of the second region.

[0139] Meanwhile, the first thickness (TH1) or the second thickness of the bank layer (BNL) may be thicker than the thickness of the insulating layers containing an inorganic insulating material. For example, if the first insulating layer (PAS1) contains an inorganic insulating material, the first thickness (TH1) or the second thickness of the bank layer (BNL) may be thicker than the thickness of the first insulating layer (PAS1).

[0140] Hereinafter, with reference to FIGS. 12 and 13, the change in the strength of the electric field (E_DR1) in the first direction (DR1) according to the length of the first width (W1) of the bank layer (BNL) is explained. Additionally, with reference to FIGS. 12 and 14, the change in the strength of the electric field (E_DR1) in the first direction (DR1) according to the first thickness (TH1) of the bank layer (BNL) is explained.

[0141] FIG. 12 is a cross-sectional view taken along the line X1-X1' of FIG. 8. FIG. 13 is a graph showing the electric field strength in the first direction according to the length of the first width of FIG. 8 and FIG. 12. FIG. 12 illustrates a part of the alignment region (LP), which is an area in FIG. 8 where the first electrode (RME1) and the second electrode (RME2) are not placed within the light-emitting region (EMA), the boundary between the light-emitting region (EMA) and the bank layer (BNL) (i.e., the upper part of the light-emitting region (EMA)), and both ends of the bank layer (BNL). The first width (W1) of the bank layer (BNL) refers to the length of the area where the electrodes (RME1, RME2) and the bank layer (BNL) overlap in FIG. 8. The first thickness (TH1) of the bank layer (BNL) refers to the maximum thickness in the first area where the bank layer (BNL) does not overlap with the bank patterns (BP1, BP2). When FIG. 13 is combined with FIG. 8 and FIG. 12, the bank layer (BNL) can be arranged to overlap the electrode body portions (RMB1, RMB2) by a first width (W1). The X-axis represents the relative position from X1 to X1' in FIG. 8 and FIG. 12, and the Y-axis represents the strength of the electric field (E_DR1) in the first direction (DR1) between the electrode extension portions (RMS1, RMS2) and the electrode body portions (RMB1, RMB2) to which different signals are applied. The graph in FIG. 13 shows the strength (Y-axis) of the electric field (E_DR1) according to the position (X-axis) when the first width (W1) is 0 µm, 3 µm, 5 µm, 7 µm, 9 µm, and 11 µm, respectively. Based on the X-axis being 17, X1 to 17 represent the electric field (E_DR1) of the alignment region (LP) inside the emission region (EMA), and X1' to 17 represent the electric field (E_DR1) of the bank layer (BNL) outside the emission region (EMA). In FIG. 12, the electric field (E_DR1) strength when the X-axis is 17 represents the electric field strength at the boundary between the emission region (EMA) (or alignment region (LP)) and the bank layer (BNL).In other words, since the electric field (E_DR1) strength when the X-axis is 17 refers to the electric field strength of the upper or lower part of the emission region (EMA), we will focus on explaining the change in the electric field (E_DR1) when the X-axis is 17.

[0142] When the first width (W1) is 0 µm, that is, when the bank layer (BNL) does not overlap with the electrode body portions (RMB1, RMB2), the electric field (E_DR1) strength above and below the light-emitting region (EMA) is approximately 1.8 × 10⁻⁶ 6 It can be V / m.

[0143] When the first width (W1) increases from 3 µm to 11 µm, the electric field (E_DR1) at the upper part and the electric field (E_DR1) at the lower part of the light-emitting region (EMA) (hereinafter used interchangeably with the term upper and lower electric field (E_DR1)) may decrease. In particular, when the first width (W1) is 7 µm or more, the electric field (E_DR1) is 4×10 5 It can decrease to V / m. The electric field (E_DR1) is 4×10 5 When V / m or less, the influence of the electric field above and below the emission region (EMA) on the alignment region (LP) may be small enough to be negligible. That is, the electric field formed within the alignment region (LP) is 4×10 6 Since it is approximately V / m, it can be about 10 times higher than the electric field (E_DR1) at the top and bottom of the light-emitting region (EMA). In this case, during the alignment process of the light-emitting element (ED), the light-emitting element (ED) can be stably aligned within the alignment region (LP) without being affected by the electric field (E_DR1) at the top and bottom of the light-emitting region (EMA), thus preventing the light-emitting element (ED) from being clustered together at the top and bottom of the light-emitting region (EMA). Therefore, when the bank layer (BNL) is overlapped to cover the electrode body portion (RMB1, RMB2) by more than 7 μm, the light-emitting element (ED) can be stably aligned within the alignment region (LP) without being affected by the electric field (E_DR1) at the top and bottom of the light-emitting region (EMA).

[0144] FIG. 14 is a graph showing the electric field strength in the first direction according to the first thickness of the bank layer of FIG. 8 and FIG. 12.

[0145] When FIG. 14 is combined with FIG. 8 and FIG. 12, the bank layer (BNL) may have a first thickness (TH1) in a first region that does not overlap with the bank patterns (BP1, BP2). The X-axis represents the relative position from X1 to X1' in FIG. 8 and FIG. 12, and the Y-axis represents the strength of the electric field (E_DR1) in the first direction (DR1) between the electrode extension portions (RMS1, RMS2) and the electrode body portions (RMB1, RMB2) to which different signals are applied. The graph in FIG. 14 shows the strength (Y-axis) of the electric field (E_DR1) according to the position (X-axis) when the first thickness (TH1) is 1 µm, 2 µm, 3 µm, and 4 µm, respectively. When the X-axis is 17, the electric field (E_DR1) strength refers to the electric field strength at the upper part of the emission region (EMA), which is the boundary between the alignment region (LP) and the bank layer (BNL), so we will explain based on this.

[0146] As the first thickness (TH1) of the bank layer (BNL) increases, the electric field generated at one end of the electrode (RME1, RME2) may be reduced. As the first thickness (TH1) of the bank layer (BNL) increases, the electric field (E_DR1) generated at one end of the electrode body (RMB1, RMB2) and one end of the electrode extension (RMS1, RMS2) may be reduced. For example, in FIG. 9, as the first thickness (TH1) of the bank layer (BNL) increases, the electric field generated at one end of the second electrode body (RMB2) and one end of the first electrode extension (RMS1) may be reduced. As another example, in FIG. 11, the thicker the first thickness (TH1) of the bank layer (BNL), the more the electric field generated at one end of the first electrode body part (RMB1) and one end of the second electrode extension part (RMS2) can be reduced.

[0147] Referring to FIG. 13, the first thickness (TH1) of the bank layer (BNL) may be 1 µm or more, and in particular, if it is 2 µm or more, the reduction range of the electric field (E_DR1) between the electrodes (RME1, RME2) may increase. The bank layer (BNL) may have a thick thickness within a range where the electric field of the alignment region (LP) for aligning the light-emitting element (ED) is not reduced.

[0148] Meanwhile, since the graphs in FIGS. 13 and 14 can be similarly applied to the electric field strength of the light-emitting region (EMA) (or alignment region (LP)) and bank layer (BNL) in FIGS. 10 and 11, the explanation thereof will be omitted.

[0149] Hereinafter, a display device (10_1) according to another embodiment will be described with reference to FIGS. 15 to 17.

[0150] FIG. 15 is a plan view of a display device according to another embodiment. FIG. 16 is a plan view showing the arrangement of connecting electrodes, a bank layer, and light-emitting elements placed in one pixel of FIG. 15. FIG. 17 is a cross-sectional view taken along the line E6-E6' of FIG. 15 and FIG. 16.

[0151] Referring to FIGS. 15 to 17, the first connecting electrode (CNE1) and the second connecting electrode (CNE2) of the connecting electrode (CNE) are connected to the lower conductive patterns through the first contact portion (CT1) and the second contact portion (CT2), and the invention is different from the previous embodiment in that it further includes a third connecting electrode (CNE3).

[0152] The first connecting electrode (CNE1) has a shape extending in the first direction (DR1) and can be placed on the first electrode body portion (RMB1) of the first electrode (RME1). The first connecting electrode (CNE1) can be placed to the right of the first electrode (RME1) and the first bank pattern (BP1), as in the first sub-connecting electrode ('CNE11' in FIG. 4) of the previous embodiment. The second connecting electrode (CNE2) has a shape extending in the first direction (DR1) and can be placed on the second electrode body portion (RMB2) of the second electrode (RME2). The second connecting electrode (CNE2) can be placed to the right of the second electrode (RME2) and the second bank pattern (BP2), as in the fourth sub-connecting electrode ('CNE22' in FIG. 4) of the previous embodiment.

[0153] The first connecting electrode (CNE1) and the second connecting electrode (CNE2) can be positioned extending from the light-emitting region (EMA) in a first direction (DR1) to a first sub-region (SA1) located above the light-emitting region (EMA). The first connecting electrode (CNE1) can contact the first conductive pattern (CDP1) through a first contact portion (CT1) formed on the first electrode (RME1) in the first sub-region (SA1). The second connecting electrode (CNE2) can contact the second conductive pattern (CDP2) through a second contact portion (CT2) formed on the second electrode (RME2) in the first sub-region (SA1).

[0154] Referring to FIG. 17, the via layer (VIA), the first insulating layer (PAS1), and the second insulating layer (PAS2) may include contact portions (CT1, CT2) disposed in a sub-region (SA). The contact portions (CT1, CT2) may each be disposed to overlap with a conductive pattern (CDP1, CDP2). For example, the contact portions (CT1, CT2) may include first contact portions (CT1) disposed to overlap with a first conductive pattern (CDP1), and second contact portions (CT2) disposed to overlap with a second conductive pattern (CDP2). The first contact portions (CT1) and the second contact portions (CT2) may penetrate the via layer (VIA), the first insulating layer (PAS1), and the second insulating layer (PAS2) to expose a portion of the upper surface of the first conductive pattern (CDP1) or the second conductive pattern (CDP2) below. The conductive patterns (CDP1, CDP2) exposed by each contact portion (CT1, CT2) can come into contact with the connecting electrode (CNE). The first conductive pattern (CDP1) exposed by the first contact portion (CT1) can come into contact with the first connecting electrode (CNE1). The second conductive pattern (CDP2) exposed by the second contact portion (CT2) can come into contact with the second connecting electrode (CNE2).

[0155] Referring again to FIGS. 15 and 16, the third connecting electrode (CNE3) may include extension portions (CN_E1, CN_E2) extending in a first direction (DR1), and a first connecting portion (CN_B1) connecting the extension portions (CN_E1, CN_E2). The first extension portion (CN_E1) ​​may be positioned on the second electrode (RME2) facing the first connecting electrode (CNE1) within the light-emitting region (EMA). With respect to the first subpixel (SPX1), the first extension portion (CN_E1) ​​may be positioned on the second electrode body portion (RMB2) of the second electrode (RME2) of the second electrode line (RML2). The second extension portion (CN_E2) may be positioned on the first electrode (RME1) facing the second connecting electrode (CNE2) within the light-emitting region (EMA). The first connection portion (CN_B1) can be extended in a second direction (DR2) on a bank layer (BNL) located below the light-emitting region (EMA) to connect the first extension portion (CN_E1) ​​and the second extension portion (CN_E2). The third connection electrode (CNE3) is placed on the light-emitting region (EMA) and the bank layer (BNL) and may not be directly connected to the electrode (RME) or the conductive pattern (CDP1, CDP2). The second electrode (RME2) located below the first extension portion (CN_E1) ​​is electrically connected to the second voltage wiring (VL2), but the second power supply voltage applied to the second electrode (RME2) may not be transmitted to the third connection electrode (CNE3).

[0156] Although embodiments of the present invention have been described above with reference to the attached drawings, those skilled in the art will understand that the present invention may be implemented in other specific forms without changing the technical concept or essential features thereof. Therefore, the embodiments described above should be understood as illustrative in all respects and not restrictive. Explanation of the symbols

[0159] 10: Display device ED: Light-emitting element SPXn: Subpixel RME1, RME2: Electrode RMS1, RMS2: Electrode extension part RMB1, RMB2: Electrode body part RML1, RML2: Electrode lines BP1, BP2: Bank pattern CNE1, CNE2: Connecting electrodes CTD, CTS: Electrode contact holes EMA: Emission region LP: Alignment region IEI: Electric field

Claims

Claim 1 A display device comprising: a first electrode disposed extending in a first direction from a subpixel; a second electrode disposed extending in the first direction and spaced apart from the first electrode in a second direction intersecting the first direction; a bank layer extending in the second direction and surrounding a plurality of the subpixels; and a light-emitting element disposed on the first electrode and the second electrode, wherein at least one of the first electrode and the second electrode comprises: an electrode extension portion extending in the first direction; and an electrode body portion connected to the electrode extension portion and having a width greater than that of the electrode extension portion, wherein the bank layer is disposed overlapping the electrode body portion by a first width and comprises an organic insulating material, wherein the second electrode comprises the electrode body portion, and the electrode body portion is disposed across different subpixels. Claim 2 A display device according to claim 1, wherein the first width is 7 µm or more. Claim 3 A display device according to claim 1, wherein the maximum thickness of the bank layer is 2 µm or more. Claim 4 A display device according to claim 1, wherein the dielectric constant of the bank layer is 2 to 4. Claim 5 In claim 1, the bank layer is a display device spaced apart in the first direction. Claim 6 A display device according to claim 1, wherein the first electrode comprises a first electrode extension portion extending in the first direction and a first electrode body portion connected to the first electrode extension portion, and the electrode body portion of the second electrode comprises a second electrode extension portion extending in the first direction and a second electrode body portion connected to the second electrode extension portion, and the first electrode extension portion has a shape bent in a diagonal direction inclined from the first direction toward the second electrode body portion. Claim 7 In claim 6, the second electrode extension is a display device having a shape that is bent diagonally, inclined from the first direction toward the first electrode body. Claim 8 A display device according to claim 1, wherein the second electrode comprises a first electrode line and a second electrode line spaced apart from each other with the first electrode in between, a first light-emitting element disposed between the first electrode and the first electrode line, and a second light-emitting element disposed between the first electrode and the second electrode line. Claim 9 delete Claim 10 A display device according to claim 1, wherein the width of the second direction of the electrode body portion is greater than the width of the second direction of the bank layer. Claim 11 In claim 1, the electrode body portion is a display device that overlaps with the bank layer disposed between the different subpixels. Claim 12 A display device according to claim 8, comprising: a first connecting electrode disposed on the first electrode and in contact with the first light-emitting element; and a second connecting electrode disposed on the second electrode and in contact with the second light-emitting element, wherein the first connecting electrode and the second connecting electrode are disposed on the electrode body portion. Claim 13 A display device according to claim 1, further comprising: a first bank pattern extending in the second direction from the subpixel and overlapping with the first electrode; and a second bank pattern spaced apart from the first electrode in the first direction, extending in the second direction, and overlapping with the second electrode, wherein the electrode body portion overlaps with either the first bank pattern and the second bank pattern, and the electrode extension portion does not overlap with the first bank pattern and the second bank pattern. Claim 14 In claim 13, the bank layer is a display device that overlaps the first bank pattern and the second bank pattern. Claim 15 A display device comprising: a first electrode extending in a first direction and disposed in a subpixel; a second electrode spaced apart from the first electrode in a second direction intersecting the first direction and extending in the first direction; a bank layer extending in the second direction and surrounding a plurality of the subpixels; and a light-emitting element disposed on the first electrode and the second electrode, wherein the first electrode includes a first electrode extension portion extending in the first direction and a first electrode body portion connected to the first electrode extension portion and having a width greater than that of the first electrode extension portion, and the second electrode includes a second electrode extension portion extending in the first direction and a second electrode body portion connected to the second electrode extension portion and having a width greater than that of the second electrode extension portion, wherein the first electrode extension portion has a shape bent in a diagonal direction inclined from the first direction toward the second electrode body portion, and the second electrode body portion is disposed across different subpixels. Claim 16 In claim 15, the bank layer is a display device that overlaps the first electrode body portion and the second electrode body portion. Claim 17 In claim 15, the bank layer is a display device that overlaps the first electrode body part and the second electrode body part by 7 μm or more. Claim 18 In claim 15, a display device in which the width of the second direction of the first electrode extension part is the same as the width of the second direction of the second electrode extension part. Claim 19 In claim 15, a display device in which the width of the first electrode body portion in the second direction is smaller than the width of the second electrode body portion in the second direction. Claim 20 In claim 19, the first electrode extension is connected to a conductive layer through a first electrode contact hole, the second electrode extension is connected to a conductive layer through a second electrode contact hole, and the first electrode contact hole and the second electrode contact hole are non-overlapping with the bank layer, forming a display device.

Images