Display panel and display apparatus having the same

Abstract

The display panel includes two or more gate layers extending in a first direction and one or more source-drain layers extending in a second direction intersecting the first direction. The two or more gate layers have a shape that is bent or folded along a hole periphery area corresponding to the periphery of a hole formed in an active region. The one or more source-drain layers have a shape that is bent or folded along the hole periphery area. At least one of the gate layers and at least one of the source-drain layers overlap in a vertical direction in the hole periphery area.

Description

Technology Field

[0001] The present invention relates to a display panel and a display device including the same, and more specifically, to a display panel in which a hole is formed within the display panel and a display device including the same. Background Technology

[0002] A display panel with a hole formed therein is being developed for the arrangement relationship with components such as a camera. In the area around the hole of the display panel, gate lines and data lines may be formed by bending or twisting to bypass the hole, and a dead space caused by the gate lines and data lines may be formed in the area around the hole. The problem to be solved

[0003] The objective of the present invention is to provide a display panel capable of reducing the dead space around the hole of the display panel.

[0004] Another objective of the present invention is to provide a display device including the display panel. means of solving the problem

[0005] A display panel according to one embodiment for realizing the above-described objective of the present invention includes two or more gate layers extending in a first direction and one or more source-drain layers extending in a second direction intersecting the first direction. The two or more gate layers have a shape that is bent or folded along a hole-periphery region corresponding to the periphery of a hole formed in an active region. The one or more source-drain layers have a shape that is bent or folded along the hole-periphery region. At least one of the gate layers and at least one of the source-drain layers overlap in a vertical direction in the hole-periphery region.

[0006] In one embodiment of the present invention, the two or more gate layers may include a first gate layer disposed on a first gate insulating layer, a second gate insulating layer disposed on the first gate layer, a second gate layer disposed on the second gate insulating layer, a first passivation layer formed on the second gate layer, and a third gate layer disposed on the first passivation layer.

[0007] In one embodiment of the present invention, the second gate layer and the third gate layer are superimposed in a vertical direction in a general area other than the hole surrounding area, and the first gate layer may not be superimposed in a vertical direction with the second gate layer and the third gate layer.

[0008] In one embodiment of the present invention, the first gate layer, the second gate layer, and the third gate layer may be superimposed in a vertical direction in the hole periphery region.

[0009] In one embodiment of the present invention, an organic insulating layer disposed in the hole peripheral region and disposed between the second gate insulating layer and the second gate layer may be further included.

[0010] In one embodiment of the present invention, the second gate layer and the third gate layer are vertically overlapped in the hole periphery region, and the first gate layer may not be vertically overlapped with the second gate layer and the third gate layer.

[0011] In one embodiment of the present invention, the display panel may further include a pixel comprising a P-type transistor and an N-type transistor.

[0012] In one embodiment of the present invention, the first gate layer may include a P-type gate line that outputs a P-type gate signal to the P-type transistor. The second gate layer may include a back gate electrode of the P-type transistor or the N-type transistor. The third gate layer may include an N-type gate line that outputs an N-type gate signal to the N-type transistor.

[0013] In one embodiment of the present invention, the one or more source drain layers may include a first source drain layer, a first organic insulating layer disposed on the first source drain layer, a second source drain layer disposed on the first organic insulating layer, and a second organic insulating layer disposed on the second source drain layer.

[0014] In one embodiment of the present invention, the first source drain layer and the second source drain layer may not overlap in the vertical direction in a general area other than the area around the hole.

[0015] In one embodiment of the present invention, the first source drain layer and the second source drain layer may be superimposed in a vertical direction in the area surrounding the hole.

[0016] In one embodiment of the present invention, the display panel may further include a plurality of pixels arranged in a matrix form. Pixels within a pixel column may be alternately connected to odd data lines and even data lines.

[0017] In one embodiment of the present invention, the first source drain layer may include the odd data line. The second source drain layer may include the even data line.

[0018] In one embodiment of the present invention, the display panel may include a first gate layer disposed on a first gate insulating layer, a second gate insulating layer disposed on the first gate layer, a second gate layer disposed on the second gate insulating layer, a first passivation layer formed on the second gate layer, a third gate layer disposed on the first passivation layer, a second passivation layer disposed on the third gate layer, a first source drain layer disposed on the second passivation layer, a first organic insulating layer disposed on the first source drain layer, a second source drain layer disposed on the first organic insulating layer, and a second organic insulating layer disposed on the second source drain layer.

[0019] In one embodiment of the present invention, the first gate layer, the second gate layer, the third gate layer, the first source drain layer, and the second source drain layer may be superimposed in a vertical direction in the hole periphery region.

[0020] In one embodiment of the present invention, the display panel may further include a third organic insulating layer disposed between the second gate insulating layer and the second gate layer, which is disposed in the area surrounding the hole.

[0021] In one embodiment of the present invention, the second gate layer, the third gate layer, the first source drain layer, and the second source drain layer are superimposed in a vertical direction in the hole periphery region, and the first gate layer may not be superimposed in a vertical direction with the second gate layer.

[0022] In one embodiment of the present invention, the display panel may include a first gate layer disposed on a first gate insulating layer, a second gate insulating layer disposed on the first gate layer, a second gate layer disposed on the second gate insulating layer, a first passivation layer formed on the second gate layer, a third gate layer disposed on the first passivation layer, a second passivation layer disposed on the third gate layer, a source drain layer disposed on the second passivation layer, and an organic insulating layer disposed on the source drain layer.

[0023] In one embodiment of the present invention, the first gate layer, the second gate layer, the third gate layer, and the source drain layer may be superimposed in a vertical direction in the hole periphery region.

[0024] A display device according to one embodiment for realizing the purpose of the present invention described above includes a display panel, a gate driver, a data driver, and an emission driver. The display panel includes two or more gate layers extending in a first direction, one or more source-drain layers extending in a second direction intersecting the first direction, and pixels connected to the two or more gate layers and the one or more source-drain layers. The two or more gate layers may have a shape that bends or folds along a hole-periphery region corresponding to the periphery of a hole formed in an active region. The one or more source-drain layers may have a shape that bends or folds along the hole-periphery region. At least one of the gate layers and at least one of the source-drain layers may overlap in a vertical direction in the hole-periphery region. Effects of the invention

[0025] According to such a display panel and a display device including said display panel, a hole is formed within the active area of ​​the display panel, and in a hole-periphery area where a gate layer and a source drain layer bypass said hole, said gate layer and the source drain layer are arranged in a vertically overlapping direction so as to reduce the dead space in the hole-periphery area. Brief explanation of the drawing

[0026] FIG. 1 is a block diagram showing a display device according to one embodiment of the present invention. Figure 2 is a circuit diagram showing the pixels of the display panel of Figure 1. Figure 3 is a timing diagram showing input signals applied to the pixels of Figure 2. Figure 4 is a conceptual diagram showing the pixel structure of the display panel of Figure 1. FIG. 5 is a plan view showing the hole, gate layer, and source drain layer of the display panel of FIG. 1. Figure 6 is a plan view showing the hole, the area around the hole, and the general area of ​​Figure 5. Figure 7 is a cross-sectional view of a display panel cut along the AA' line of Figure 6. Figure 8 is a cross-sectional view of a display panel cut along the BB' line of Figure 6. Figure 9 is a cross-sectional view of a display panel cut along the CC' line of Figure 6. FIG. 10 is a plan view showing a hole, a hole surrounding area, and a general area of ​​a display panel according to one embodiment of the present invention. Figure 11 is a cross-sectional view of a display panel cut along the CC' line of Figure 10. FIG. 12 is a cross-sectional view of the area around a hole of a display panel according to one embodiment of the present invention. FIG. 13 is a conceptual diagram showing the pixel structure of a display panel according to one embodiment of the present invention. Figure 14 is a cross-sectional view of the area around the hole of the display panel of Figure 13. Specific details for implementing the invention

[0027] Hereinafter, the present invention will be described in more detail with reference to the attached drawings.

[0028] FIG. 1 is a block diagram showing a display device according to one embodiment of the present invention.

[0029] Referring to FIG. 1, the display device includes a display panel (100) and a display panel driver. The display panel driver includes a drive control unit (200), a gate driver (300), a gamma reference voltage generator (400), a data driver (500), and an emission driver (600).

[0030] The above display panel (100) includes a display portion for displaying an image and a peripheral portion arranged adjacent to the display portion.

[0031] The display panel (100) comprises a plurality of gate lines (GWPL, GWNL, GIL, GBL), a plurality of data lines (DL), a plurality of emission lines (EL), and a plurality of pixels electrically connected to each of the gate lines (GWPL, GWNL, GIL, GBL), the data lines (DL), and the emission lines (EL). The gate lines (GWPL, GWNL, GIL, GBL) extend in a first direction (D1), the data lines (DL) extend in a second direction (D2) that intersects the first direction (D1), and the emission lines (EL) extend in the first direction (D1).

[0032] The above-described drive control unit (200) receives input image data (IMG) and an input control signal (CONT) from an external device (not shown). For example, the input image data (IMG) may include red image data, green image data, and blue image data. The input image data (IMG) may include white image data. The input image data (IMG) may include magenta image data, yellow image data, and cyan image data. The input control signal (CONT) may include a master clock signal and a data enable signal. The input control signal (CONT) may further include a vertical synchronization signal and a horizontal synchronization signal.

[0033] The above driving control unit (200) generates a first control signal (CONT1), a second control signal (CONT2), a third control signal (CONT3), a fourth control signal (CONT4), and a data signal (DATA) based on the input image data (IMG) and the input control signal (CONT).

[0034] The above drive control unit (200) generates the first control signal (CONT1) to control the operation of the gate drive unit (300) based on the input control signal (CONT) and outputs it to the gate drive unit (300). The first control signal (CONT1) may include a vertical start signal and a gate clock signal.

[0035] The above drive control unit (200) generates the second control signal (CONT2) to control the operation of the data drive unit (500) based on the input control signal (CONT) and outputs it to the data drive unit (500). The second control signal (CONT2) may include a horizontal start signal and a load signal.

[0036] The above drive control unit (200) generates a data signal (DATA) based on the input image data (IMG). The above drive control unit (200) outputs the data signal (DATA) to the data drive unit (500).

[0037] The above driving control unit (200) generates the third control signal (CONT3) to control the operation of the gamma reference voltage generation unit (400) based on the input control signal (CONT) and outputs it to the gamma reference voltage generation unit (400).

[0038] The above drive control unit (200) generates the fourth control signal (CONT4) to control the operation of the emission drive unit (600) based on the input control signal (CONT) and outputs it to the emission drive unit (600).

[0039] The gate driving unit (300) generates gate signals for driving the gate lines (GWPL, GWNL, GIL, GBL) in response to the first control signal (CONT1) received from the driving control unit (200). The gate driving unit (300) can output the gate signals to the gate lines (GWPL, GWNL, GIL, GBL).

[0040] The gamma reference voltage generation unit (400) generates a gamma reference voltage (VGREF) in response to the third control signal (CONT3) received from the driving control unit (200). The gamma reference voltage generation unit (400) provides the gamma reference voltage (VGREF) to the data driving unit (500). The gamma reference voltage (VGREF) has a value corresponding to each data signal (DATA).

[0041] For example, the gamma reference voltage generation unit (400) may be placed within the drive control unit (200) or within the data drive unit (500).

[0042] The data driving unit (500) receives the second control signal (CONT2) and the data signal (DATA) from the driving control unit (200), and receives the gamma reference voltage (VGREF) from the gamma reference voltage generation unit (400). The data driving unit (500) converts the data signal (DATA) into an analog data voltage using the gamma reference voltage (VGREF). The data driving unit (500) outputs the data voltage to the data line (DL).

[0043] The emission driving unit (600) generates emission signals to drive the emission lines (EL) in response to the fourth control signal (CONT4) received from the driving control unit (200). The emission driving unit (600) can output the emission signals to the emission lines (EL).

[0044] FIG. 2 is a circuit diagram showing a pixel of the display panel (100) of FIG. 1. FIG. 3 is a timing diagram showing input signals applied to the pixel of FIG. 2.

[0045] Referring to FIGS. 1 to 3, the display panel (100) includes a plurality of pixels, and each of the pixels includes an organic light-emitting diode (OLED).

[0046] The pixels receive a data write gate signal (GWP, GWN), a data initialization gate signal (GI), an organic light-emitting diode initialization gate signal (GB), the data voltage (VDATA), and the emission signal (EM), and display the image by emitting light from the organic light-emitting diode (OLED) according to the level of the data voltage (VDATA).

[0047] In this embodiment, the pixel may include a first type of switching element and a second type of switching element different from the first type. For example, the first type of switching element may be a polysilicon thin-film transistor. For example, the first type of switching element may be a low-temperature polysilicon (LTPS) thin-film transistor. For example, the second type of switching element may be an oxide thin-film transistor. For example, the first type of switching element may be a P-type transistor, and the second type of switching element may be an N-type transistor.

[0048] For example, the data write gate signal may include a first data write gate signal (GWP) and a second data write gate signal (GWN). The first data write gate signal (GWP) is applied to the P-type transistor and has a low-level activation signal at the data write timing. The second data write gate signal (GWN) is applied to the N-type transistor and has a high-level activation signal at the data write timing.

[0049] At least one of the above pixels may include a first to seventh pixel switching element (T1 to T7), a storage capacitor (CST), and an organic light-emitting diode (OLED).

[0050] The first pixel switching element (T1) includes a control electrode connected to a first node (N1), an input electrode connected to a second node (N2), and an output electrode connected to a third node (N3).

[0051] For example, the first pixel switching element (T1) may be a polysilicon thin-film transistor. The first pixel switching element (T1) may be a P-type thin-film transistor. The control electrode of the first pixel switching element (T1) may be a gate electrode, the input electrode of the first pixel switching element (T1) may be a source electrode, and the output electrode of the first pixel switching element (T1) may be a drain electrode.

[0052] The second pixel switching element (T2) includes a control electrode to which the first data write gate signal (GWP) is applied, an input electrode to which the data voltage (VDATA) is applied, and an output electrode connected to the second node (N2).

[0053] For example, the second pixel switching element (T2) may be a polysilicon thin-film transistor. The second pixel switching element (T2) may be a P-type thin-film transistor. The control electrode of the second pixel switching element (T2) may be a gate electrode, the input electrode of the second pixel switching element (T2) may be a source electrode, and the output electrode of the second pixel switching element (T2) may be a drain electrode.

[0054] The third pixel switching element (T3) includes a control electrode to which the second data writing gate signal (GWN) is applied, an input electrode connected to the first node (N1), and an output electrode connected to the third node (N3).

[0055] For example, the third pixel switching element (T3) may be an oxide thin-film transistor. The third pixel switching element (T3) may be an N-type thin-film transistor. The control electrode of the third pixel switching element (T3) may be a gate electrode, the input electrode of the third pixel switching element (T3) may be a source electrode, and the output electrode of the third pixel switching element (T3) may be a drain electrode.

[0056] The fourth pixel switching element (T4) includes a control electrode to which the data initialization gate signal (GI) is applied, an input electrode to which the initialization voltage (VI) is applied, and an output electrode connected to the first node (N1).

[0057] For example, the fourth pixel switching element (T4) may be an oxide thin-film transistor. The fourth pixel switching element (T4) may be an N-type thin-film transistor. The control electrode of the fourth pixel switching element (T4) may be a gate electrode, the input electrode of the fourth pixel switching element (T4) may be a source electrode, and the output electrode of the fourth pixel switching element (T4) may be a drain electrode.

[0058] The fifth pixel switching element (T5) includes a control electrode to which the emission signal (EM) is applied, an input electrode to which a high power supply voltage (ELVDD) is applied, and an output electrode connected to the second node (N2).

[0059] For example, the fifth pixel switching element (T5) may be a polysilicon thin-film transistor. The fifth pixel switching element (T5) may be a P-type thin-film transistor. The control electrode of the fifth pixel switching element (T5) may be a gate electrode, the input electrode of the fifth pixel switching element (T5) may be a source electrode, and the output electrode of the fifth pixel switching element (T5) may be a drain electrode.

[0060] The sixth pixel switching element (T6) includes a control electrode to which the emission signal (EM) is applied, an input electrode connected to the third node (N3), and an output electrode connected to the anode electrode of the organic light-emitting diode (OLED).

[0061] For example, the sixth pixel switching element (T6) may be a polysilicon thin-film transistor. The sixth pixel switching element (T6) may be a P-type thin-film transistor. The control electrode of the sixth pixel switching element (T6) may be a gate electrode, the input electrode of the sixth pixel switching element (T6) may be a source electrode, and the output electrode of the sixth pixel switching element (T6) may be a drain electrode.

[0062] The seventh pixel switching element (T7) includes a control electrode to which the organic light-emitting element initialization gate signal (GB) is applied, an input electrode to which the initialization voltage (VI) is applied, and an output electrode connected to the anode electrode of the organic light-emitting element.

[0063] For example, the seventh pixel switching element (T7) may be an oxide thin-film transistor. The seventh pixel switching element (T7) may be an N-type thin-film transistor. The control electrode of the seventh pixel switching element (T7) may be a gate electrode, the input electrode of the seventh pixel switching element (T7) may be a source electrode, and the output electrode of the seventh pixel switching element (T7) may be a drain electrode.

[0064] In this embodiment, the seventh pixel switching element (T7) is exemplified as an oxide thin-film transistor, but the seventh pixel switching element (T7) may be a polysilicon thin-film transistor. In this embodiment, the seventh pixel switching element (T7) is exemplified as an N-type thin-film transistor, but the seventh pixel switching element (T7) may be a P-type thin-film transistor.

[0065] The storage capacitor (CST) includes a first electrode to which the high power supply voltage (ELVDD) is applied and a second electrode connected to the first node (N1).

[0066] The above organic light-emitting diode (OLED) includes the anode electrode and the cathode electrode to which a low power supply voltage (ELVSS) is applied.

[0067] Referring to FIG. 3, during the first interval (DU1), the first node (N1) and the storage capacitor (CST) are initialized by the data initialization gate signal (GI). During the second interval (DU2), the threshold voltage (|VTH|) of the first pixel switching element (T1) is compensated by the first and second data write gate signals (GWP, GWN), and the data voltage (VDATA) compensated by the threshold voltage (|VTH|) is written to the first node (N1). During the third interval (DU3), the anode electrode of the organic light-emitting element (OLED) is initialized by the organic light-emitting element initialization gate signal (GB). During the fourth interval (DU4), the organic light-emitting element (OLED) emits light by the emission signal (EM), and the display panel (100) displays an image.

[0068] In this embodiment, the off-period of the emission signal (EM) is exemplified as the first to third periods (DU1, DU2, DU3), but the present invention is not limited thereto. The off-period of the emission signal (EM) may include the data writing period (DU2), and the off-period of the emission signal (EM) may be longer than the first to third periods (DU1, DU2, DU3).

[0069] In the first section (DU1), the data initialization gate signal (GI) may have an activation level. For example, the activation level of the data initialization gate signal (GI) may be a high level. When the data initialization gate signal (GI) has the activation level, the fourth pixel switching element (T4) is turned on, and the initialization voltage (VI) may be applied to the first node (N1). The data initialization gate signal (GI[N]) of the current stage may be generated based on the scan signal (SCAN[N-1]) of the previous stage.

[0070] In the second section (DU2), the first data write gate signal (GWP) and the second data write gate signal (GWN) may have an activation level. For example, the activation level of the first data write gate signal (GWP) may be a low level, and the activation level of the second data write gate signal (GWN) may be a high level. When the first data write gate signal (GWP) and the second data write gate signal (GWN) have the activation level, the second pixel switching element (T2) and the third pixel switching element (T3) are turned on. Additionally, the first pixel switching element (T1) is also turned on by the initialization voltage (VI). The first data write gate signal (GWP[N]) of the current stage may be generated based on the scan signal (SCAN[N]) of the current stage. The second data write gate signal (GWN[N]) may be generated based on the scan signal (SCAN[N]) of the current stage.

[0071] Along the path formed by the first to third pixel switching elements (T1, T2, T3) turned on, the first node (N1) is set with a voltage that is the absolute value (|VTH|) of the threshold voltage of the first pixel switching element (T1) subtracted from the data voltage (VDATA).

[0072] In the third section (DU3), the organic light-emitting diode initialization gate signal (GB) may have an activation level. For example, the activation level of the organic light-emitting diode initialization gate signal (GB) may be a high level. When the organic light-emitting diode initialization gate signal (GB) has the activation level, the seventh pixel switching element (T7) is turned on, and the initialization voltage (VI) may be applied to the anode electrode of the organic light-emitting diode (OLED). The organic light-emitting diode initialization gate signal (GB[N]) of the current stage may be generated based on the scan signal (SCAN[N+1]) of the next stage.

[0073] In the fourth section (DU4), the emission signal (EM) may have an activation level. For example, the activation level of the emission signal (EM) may be a low level. When the emission signal (EM) has the activation level, the fifth pixel switching element (T5) and the sixth pixel switching element (T6) are turned on. Additionally, the first pixel switching element (T1) is also turned on by the data voltage (VDATA).

[0074] The driving current can drive the organic light-emitting diode (OLED) by flowing in the order of the fifth pixel switching element (T5), the first pixel switching element (T1), and the sixth pixel switching element (T6). The intensity of the driving current can be determined by the level of the data voltage (VDATA). The brightness of the organic light-emitting diode (OLED) can be determined by the intensity of the driving current.

[0075] In this embodiment, when the image displayed on the display panel (100) is a still image or when the display panel (100) operates in an always-on mode, the driving frequency of the display panel (100) may be reduced to reduce power consumption. If all of the switching elements of the display panel (100) are polysilicon, flicker may occur due to leakage current of the switching elements in a low-frequency driving mode. Therefore, some of the switching elements of the pixels may be composed of oxide thin-film transistors. In this embodiment, the third pixel switching element (T3), the fourth pixel switching element (T4), and the seventh pixel switching element (T7) may be oxide thin-film transistors. The first pixel switching element (T1), the second pixel switching element (T2), the fifth pixel switching element (T5), and the sixth pixel switching element (T6) may be polysilicon thin-film transistors.

[0076] In this embodiment, the second data writing gate signal (GWN) is applied to the control electrode of the third pixel switching element (T3), and the organic light-emitting diode initialization gate signal (GB) is applied to the control electrode of the seventh pixel switching element (T7); however, the control electrode of the third pixel switching element (T3) may be connected to the control electrode of the seventh pixel switching element (T7). At this time, the second data writing gate signal (GWN) may be applied to the control electrode of the third pixel switching element (T3) and the control electrode of the seventh pixel switching element (T7).

[0077] FIG. 4 is a conceptual diagram showing the pixel structure of the display panel (100) of FIG. 1.

[0078] Referring to FIGS. 1 to 4, the display panel (100) may include a plurality of pixels arranged in a matrix form.

[0079] In this embodiment, pixels within a pixel column may be alternately connected to two adjacent data lines. Pixels within a pixel column may be alternately connected to odd data lines and even data lines.

[0080] For example, among the pixels placed in the first pixel column of the display panel (100), the first pixel (P11) and the third pixel (P31) may be connected to the first data line (DL1), and the second pixel (P21) and the fourth pixel (P41) may be connected to the second data line (DL2). For example, among the pixels placed in the second pixel column of the display panel (100), the first pixel (P12) and the third pixel (P32) may be connected to the third data line (DL3), and the second pixel (P22) and the fourth pixel (P42) may be connected to the fourth data line (DL4). For example, among the pixels placed in the third pixel column of the display panel (100), the first pixel (P13) and the third pixel (P33) may be connected to the fifth data line (DL5), and the second pixel (P23) and the fourth pixel (P43) may be connected to the sixth data line (DL6). For example, among the pixels placed in the fourth pixel column of the display panel (100), the first pixel (P14) and the third pixel (P34) may be connected to the seventh data line (DL7), and the second pixel (P24) and the fourth pixel (P44) may be connected to the eighth data line (DL8).

[0081] FIG. 5 is a plan view showing the hole (HL), gate layers (GAT1, GAT2, GAT3), and source drain layers (SD1, SD2) of the display panel (100) of FIG. 1. FIG. 6 is a plan view showing the hole (HL), the hole surrounding area, and the general area of ​​FIG. 5.

[0082] Referring to FIGS. 1 to 6, the display panel (100) includes an active area (AA) for displaying images and a peripheral area (PA) surrounding the active area (AA).

[0083] A hole (HL) may be formed within the active area (AA). The hole (HL) may be formed corresponding to the location of the camera module of the display device. The hole (HL) means that the base substrate of the display panel (100) is directly pierced, and only a transparent material may be placed within the hole (HL).

[0084] The above display panel (100) may include a plurality of gate layers (GAT1, GAT2, GAT3) extending in the first direction (D1) and a plurality of source drain layers (SD1, SD2) extending in the second direction (D2).

[0085] The gate layers (GAT1, GAT2, GAT3) that do not pass through the region where the hole (HL) is formed extend only in a straight line along the first direction (D1). On the other hand, the gate layers (GAT1, GAT2, GAT3) that pass through the region where the hole (HL) is formed extend in a straight line along the first direction (D1) in the general region where the hole (HL) is not formed, and have a shape that bends or curves along the circumference of the hole in the region around the hole where the hole (HL) is formed.

[0086] The source drain layer (SD1, SD2) that does not pass through the area where the hole (HL) is formed extends only in a straight line along the second direction (D2). On the other hand, the source drain layer (SD1, SD2) that passes through the area where the hole (HL) is formed extends in a straight line along the second direction (D2) in the general area where the hole (HL) is not formed, and has a shape that bends or curves along the perimeter of the hole in the area around the hole where the hole (HL) is formed.

[0087] That is, the portion of the gate layer (GAT1, GAT2, GAT3) or the source drain layer (SD1, SD2) that has a shape that is bent or broken due to the influence of the hole (HL) can be defined as the hole surrounding region.

[0088] FIG. 7 is a cross-sectional view of a display panel (100) cut along the AA' line of FIG. 6. FIG. 8 is a cross-sectional view of a display panel (100) cut along the BB' line of FIG. 6. FIG. 9 is a cross-sectional view of a display panel (100) cut along the CC' line of FIG. 6.

[0089] The AA' line represents the cross-sectional structure of the source drain layer (SD1, SD2) in the general region where the hole is not formed, the BB' line represents the cross-sectional structure of the gate layer (GAT1, GAT2, GAT3) in the general region, and the CC' line represents the cross-sectional structure of the gate layer (GAT1, GAT2, GAT3) and the source drain layer (SD1, SD2) in the region around the hole.

[0090] Referring to FIGS. 1 to 9, the display panel (100) comprises a base layer (PI), a barrier layer (BR) disposed on the base layer (PI), a first gate insulating layer (GI1) disposed on the barrier layer (BR), a first gate layer (GAT1) disposed on the first gate insulating layer (GI1), a second gate insulating layer (GI2) disposed on the first gate layer (GAT1), a second gate layer (GAT2) disposed on the second gate insulating layer (GI2), a first passivation layer (ILD1) formed on the second gate layer (GAT2), a third gate layer (GAT3) disposed on the first passivation layer (ILD1), a second passivation layer (ILD2) disposed on the third gate layer (GAT3), a first source drain layer (SD1) disposed on the second passivation layer (ILD2), and a first organic layer disposed on the first source drain layer (SD1). It may include an insulating layer (VIA1), a second source drain layer (SD2) disposed on the first organic insulating layer (VIA1), and a second organic insulating layer (VIA2) disposed on the second source drain layer (SD2).

[0091] The base layer (PI) may include polyimide. The barrier layer (BR) may include inorganic material. The thickness of the barrier layer (BR) may be about 800 nm to 900 nm.

[0092] The gate insulating layer (GI1, GI2) may include an inorganic material. The thickness of the gate insulating layer (GI1, GI2) may be about 150 nm.

[0093] The passivation layer (ILD1, ILD2) may include an inorganic material. The thickness of the passivation layer (ILD1, ILD2) may be thicker than the thickness of the gate insulation layer (GI1, GI2). The thickness of the passivation layer (ILD1, ILD2) may be about 400 nm to 500 nm.

[0094] The organic insulating layer (VIA1, VIA2) may include an organic insulating material. The thickness of the organic insulating layer (VIA1, VIA2) may be thicker than the thickness of the gate insulating layer (GI1, GI2) and the thickness of the passivation layer (ILD1, ILD2). The thickness of the organic insulating layer (VIA1, VIA2) may be about 1.5 μm to 2 μm.

[0095] In one embodiment of the present invention, the first passivation layer (ILD1) may be replaced with a third gate insulating layer (GI3), wherein the third gate insulating layer (GI3) may include an inorganic material and may be formed with a thickness of about 150 nm.

[0096] As shown in FIG. 7, in a general area other than the area around the hole, the first source drain layer (SD1) and the second source drain layer (SD2) may not overlap in the vertical direction.

[0097] The first source drain layer (SD1) may include the odd data lines (DL1, DL3, DL5, DL7) in the pixel structure of FIG. 4, and the second source drain layer (SD2) may include the even data lines (DL2, DL4, DL6, DL8) in the pixel structure of FIG. 4. Since the odd data lines and the even data lines do not overlap in the general area, the first source drain layer (SD1) and the second source drain layer (SD2) may not overlap in the vertical direction in the general area.

[0098] On the other hand, as shown in FIG. 9, the first source drain layer (SD1) and the second source drain layer (SD2) may be superimposed in a vertical direction in the area surrounding the hole. In the area surrounding the hole, the first source drain layer (SD1) and the second source drain layer (SD2) are not connected to the pixels and have a bent or curved shape to bypass the hole (HL).

[0099] In the area surrounding the hole, the first source drain layer (SD1) and the second source drain layer (SD2) can be overlapped in a vertical direction to reduce the dead space caused by the hole (HL).

[0100] In the area surrounding the hole, the horizontal spacing between adjacent data lines of the first source drain layer (SD1) is smaller than the horizontal spacing between adjacent data lines of the first source drain layer (SD1) in the general area, and the horizontal spacing between adjacent data lines of the second source drain layer (SD2) may be smaller than the horizontal spacing between adjacent data lines of the second source drain layer (SD2) in the general area. Accordingly, the dead space caused by the hole (HL) in the area surrounding the hole can be further reduced.

[0101] As shown in FIG. 8, in a general area other than the area around the hole, the second gate layer (GAT2) and the third gate layer (GAT3) overlap in a vertical direction, and the first gate layer (GAT1) may not overlap in a vertical direction with the second gate layer (GAT2) and the third gate layer (GAT3).

[0102] The first gate layer (GAT1) may include a P-type gate line (GWPL) that outputs a P-type gate signal (GWP) to the P-type transistor of FIG. 2. The second gate layer (GAT2) may include a back gate electrode of the P-type transistor or the N-type transistor and a connection line of the back gate electrode. The third gate layer may include an N-type gate line (GWNL) that outputs an N-type gate signal (GWN) to the N-type transistor of FIG. 2. Additionally, although not illustrated, the second gate layer (GAT2) may include a storage electrode that overlaps with the first gate layer (GAT1).

[0103] In the above general region, the first gate layer (GAT1) and the second gate layer (GAT2) output gate signals of different waveforms, so they may not overlap in the vertical direction to prevent coupling phenomena.

[0104] On the other hand, as shown in FIG. 9, the first gate layer (GAT1), the second gate layer (GAT2), and the third gate layer (GAT3) may be superimposed in a vertical direction in the area surrounding the hole. In the area surrounding the hole, the first gate layer (GAT1), the second gate layer (GAT2), and the third gate layer (GAT3) have a bent or curved shape to bypass the hole (HL).

[0106] The first gate layer (GAT1), the second gate layer (GAT2), and the third gate layer (GAT3) can be overlapped in a vertical direction in the area surrounding the hole to reduce the dead space caused by the hole (HL).

[0107] In the hole-periphery region, the horizontal spacing between adjacent gate lines of the first gate layer (GAT1) is smaller than the horizontal spacing between adjacent gate lines of the first gate layer (GAT1) in the general region, the horizontal spacing between adjacent backgate signal transmission lines of the second gate layer (GAT2) in the hole-periphery region is smaller than the horizontal spacing between adjacent backgate signal transmission lines of the second gate layer (GAT2) in the general region, and the horizontal spacing between adjacent gate lines of the third gate layer (GAT3) in the hole-periphery region may be smaller than the horizontal spacing between adjacent gate lines of the third gate layer (GAT1) in the general region. Accordingly, the dead space caused by the hole (HL) in the hole-periphery region can be further reduced.

[0108] In addition, in the present embodiment, the first gate layer (GAT1), the second gate layer (GAT2), the third gate layer (GAT3), the first source drain layer (SD1), and the second source drain layer (SD2) may be overlapped in a vertical direction in the area surrounding the hole. Accordingly, the dead space caused by the hole (HL) in the area surrounding the hole can be further reduced.

[0109] According to the present embodiment, a hole (HL) is formed within an active area (AA) of a display panel (100), and in a hole-periphery area where a gate layer (GAT1, GAT2, GAT3) and a source-drain layer (SD1, SD2) bypass the hole (HL), the gate layer (GAT1, GAT2, GAT3) and the source-drain layer (SD1, SD2) are arranged in a vertically overlapping direction to reduce the dead space in the hole-periphery area.

[0110] FIG. 10 is a plan view showing a hole, a hole surrounding area, and a general area of ​​a display panel according to one embodiment of the present invention. FIG. 11 is a cross-sectional view of a display panel cut along the CC' line of FIG. 10.

[0111] Since the display panel and display device according to the present embodiment are substantially identical to the display panel and display device of FIGS. 1 to 9 except for the layer structure of the area around the hole of the display panel, the same reference numbers are used for identical or similar components, and redundant descriptions are omitted.

[0112] Referring to FIGS. 1 to 5, FIGS. 7, FIGS. 8, FIGS. 10 and FIGS. 11, the display device includes a display panel (100) and a display panel driving unit. The display panel driving unit includes a driving control unit (200), a gate driving unit (300), a gamma reference voltage generating unit (400), a data driving unit (500), and an emission driving unit (600).

[0113] The above display panel (100) includes an active area (AA) for displaying images and a peripheral area (PA) surrounding the active area (AA). A hole (HL) may be formed within the active area (AA). The hole (HL) may be formed corresponding to the location of the camera module of the display device.

[0114] The above display panel (100) may include a plurality of gate layers (GAT1, GAT2, GAT3) extending in the first direction (D1) and a plurality of source drain layers (SD1, SD2) extending in the second direction (D2).

[0115] The above display panel (100) comprises a base layer (PI), a barrier layer (BR) disposed on the base layer (PI), a first gate insulating layer (GI1) disposed on the barrier layer (BR), a first gate layer (GAT1) disposed on the first gate insulating layer (GI1), a second gate insulating layer (GI2) disposed on the first gate layer (GAT1), a second gate layer (GAT2) disposed on the second gate insulating layer (GI2), a first passivation layer (ILD1) formed on the second gate layer (GAT2), a third gate layer (GAT3) disposed on the first passivation layer (ILD1), a second passivation layer (ILD2) disposed on the third gate layer (GAT3), a first source drain layer (SD1) disposed on the second passivation layer (ILD2), a first organic insulating layer (VIA1) disposed on the first source drain layer (SD1), and the first organic It may include a second source drain layer (SD2) disposed on an insulating layer (VIA1) and a second organic insulating layer (VIA2) disposed on the second source drain layer (SD2).

[0116] The above display panel (100) may further include a third organic insulating layer (VIA3) which is selectively disposed only in the area around the hole and is disposed between the second gate insulating layer (GI2) and the second gate layer (GAT2).

[0117] The organic insulating layers (VIA1, VIA2, VIA3) may include an organic insulating material. The thickness of the organic insulating layers (VIA1, VIA2, VIA3) may be thicker than the thickness of the gate insulating layers (GI1, GI2) and the thickness of the passivation layers (ILD1, ILD2). The thickness of the organic insulating layers (VIA1, VIA2, VIA3) may be about 1.5 μm to 2 μm.

[0118] In this embodiment, the first gate layer (GAT1), the second gate layer (GAT2), the third gate layer (GAT3), the first source drain layer (SD1), and the second source drain layer (SD2) may be superimposed in a vertical direction in the area surrounding the hole. Accordingly, the dead space caused by the hole (HL) in the area surrounding the hole can be reduced.

[0119] Since signals of different waveforms are applied to the first gate layer (GAT1) and the second gate layer (GAT2), it is necessary to prevent coupling. Since a structure in which the first gate layer (GAT1) and the second gate layer (GAT2) are vertically overlapped may be vulnerable to the coupling phenomenon, the third organic insulating layer (VIA3) may be further formed between the first gate layer (GAT1) and the second gate layer (GAT2). Accordingly, the coupling phenomenon between the first gate layer (GAT1) and the second gate layer (GAT2) can be prevented.

[0120] According to the present embodiment, a hole (HL) is formed within an active area (AA) of a display panel (100), and in a hole-periphery area where a gate layer (GAT1, GAT2, GAT3) and a source-drain layer (SD1, SD2) bypass the hole (HL), the gate layer (GAT1, GAT2, GAT3) and the source-drain layer (SD1, SD2) are arranged in a vertically overlapping direction to reduce the dead space in the hole-periphery area.

[0121] FIG. 12 is a cross-sectional view of the area around a hole of a display panel according to one embodiment of the present invention.

[0122] Since the display panel and display device according to the present embodiment are substantially identical to the display panel and display device of FIGS. 1 to 9 except for the layer structure of the area around the hole of the display panel, the same reference numbers are used for identical or similar components, and redundant descriptions are omitted.

[0123] Referring to FIGS. 1 to 8 and FIG. 12, the display device includes a display panel (100) and a display panel driver. The display panel driver includes a drive control unit (200), a gate driver (300), a gamma reference voltage generator (400), a data driver (500), and an emission driver (600).

[0124] The above display panel (100) includes an active area (AA) for displaying images and a peripheral area (PA) surrounding the active area (AA). A hole (HL) may be formed within the active area (AA). The hole (HL) may be formed corresponding to the location of the camera module of the display device.

[0125] The above display panel (100) may include a plurality of gate layers (GAT1, GAT2, GAT3) extending in the first direction (D1) and a plurality of source drain layers (SD1, SD2) extending in the second direction (D2).

[0126] The above display panel (100) comprises a base layer (PI), a barrier layer (BR) disposed on the base layer (PI), a first gate insulating layer (GI1) disposed on the barrier layer (BR), a first gate layer (GAT1) disposed on the first gate insulating layer (GI1), a second gate insulating layer (GI2) disposed on the first gate layer (GAT1), a second gate layer (GAT2) disposed on the second gate insulating layer (GI2), a first passivation layer (ILD1) formed on the second gate layer (GAT2), a third gate layer (GAT3) disposed on the first passivation layer (ILD1), a second passivation layer (ILD2) disposed on the third gate layer (GAT3), a first source drain layer (SD1) disposed on the second passivation layer (ILD2), a first organic insulating layer (VIA1) disposed on the first source drain layer (SD1), and the first organic It may include a second source drain layer (SD2) disposed on an insulating layer (VIA1) and a second organic insulating layer (VIA2) disposed on the second source drain layer (SD2).

[0127] As shown in FIG. 8, in a general area other than the area around the hole, the second gate layer (GAT2) and the third gate layer (GAT3) overlap in a vertical direction, and the first gate layer (GAT1) may not overlap in a vertical direction with the second gate layer (GAT2) and the third gate layer (GAT3).

[0128] As shown in FIG. 12, the second gate layer (GAT2) and the third gate layer (GAT3) overlap in the vertical direction even in the area around the hole, and the first gate layer (GAT1) may not overlap in the vertical direction with the second gate layer (GAT2) and the third gate layer (GAT3).

[0129] In this embodiment, the second gate layer (GAT2), the third gate layer (GAT3), the first source drain layer (SD1), and the second source drain layer (SD2) may be superimposed in a vertical direction in the area surrounding the hole. Accordingly, the dead space caused by the hole (HL) in the area surrounding the hole can be reduced.

[0130] Since the first gate layer (GAT1) and the second gate layer (GAT2) are to which signals of different waveforms are applied, it is necessary to prevent coupling. Therefore, the first gate layer (GAT1) and the second gate layer (GAT2) are arranged in an alternating manner, so that the distance between the first gate layer (GAT1) and the second gate layer (GAT2) can be increased compared to a structure in which the first gate layer (GAT1) and the second gate layer (GAT2) are vertically overlapped. Accordingly, the coupling phenomenon between the first gate layer (GAT1) and the second gate layer (GAT2) can be prevented.

[0131] According to the present embodiment, a hole (HL) is formed within an active area (AA) of a display panel (100), and in a hole-periphery area where a gate layer (GAT1, GAT2, GAT3) and a source-drain layer (SD1, SD2) bypass the hole (HL), a portion of the gate layer and the source-drain layer (GAT2, GAT3, SD1, SD2) is arranged in a vertically overlapping direction to reduce the dead space in the hole-periphery area.

[0132] FIG. 13 is a conceptual diagram showing the pixel structure of a display panel according to one embodiment of the present invention. FIG. 14 is a cross-sectional view of the area around the hole of the display panel of FIG. 13.

[0133] Since the display panel and display device according to the present embodiment are substantially identical to the display panel and display device of FIGS. 1 to 9, except for the pixel structure of the display panel and the layer structure of the hole surrounding area of ​​the display panel, the same reference numbers are used for identical or similar components, and redundant descriptions are omitted.

[0134] Referring to FIGS. 1 to 3, FIGS. 5, FIGS. 8, FIGS. 13 and FIGS. 14, the display device includes a display panel (100) and a display panel driving unit. The display panel driving unit includes a driving control unit (200), a gate driving unit (300), a gamma reference voltage generating unit (400), a data driving unit (500), and an emission driving unit (600).

[0135] The above display panel (100) includes an active area (AA) for displaying images and a peripheral area (PA) surrounding the active area (AA). A hole (HL) may be formed within the active area (AA). The hole (HL) may be formed corresponding to the location of the camera module of the display device.

[0136] The above display panel (100) may include a plurality of gate layers (GAT1, GAT2, GAT3) extending in the first direction (D1) and a source drain layer (SD1) extending in the second direction (D2).

[0137] The above display panel (100) may include a base layer (PI), a barrier layer (BR) disposed on the base layer (PI), a first gate insulating layer (GI1) disposed on the barrier layer (BR), a first gate layer (GAT1) disposed on the first gate insulating layer (GI1), a second gate insulating layer (GI2) disposed on the first gate layer (GAT1), a second gate layer (GAT2) disposed on the second gate insulating layer (GI2), a first passivation layer (ILD1) formed on the second gate layer (GAT2), a third gate layer (GAT3) disposed on the first passivation layer (ILD1), a second passivation layer (ILD2) disposed on the third gate layer (GAT3), a source drain layer (SD1) disposed on the second passivation layer (ILD2), and an organic insulating layer (VIA1) disposed on the source drain layer (SD1).

[0138] As shown in FIG. 13, the display panel (100) may include a plurality of pixels arranged in a matrix form.

[0139] In this embodiment, pixels within a pixel column can be connected to adjacent data lines.

[0140] For example, pixels (P11, P21, P31, P41) placed in the first pixel column of the display panel (100) may be connected to the first data line (DL1), pixels (P12, P22, P32, P42) placed in the second pixel column of the display panel (100) may be connected to the second data line (DL2), pixels (P13, P23, P33, P43) placed in the third pixel column of the display panel (100) may be connected to the third data line (DL3), and pixels (P14, P24, P34, P44) placed in the fourth pixel column of the display panel (100) may be connected to the fourth data line (DL4).

[0141] The source drain layer (SD1) of FIG. 14 may include the first to fourth data lines (DL1 to DL4).

[0142] In this embodiment, the first gate layer (GAT1), the second gate layer (GAT2), the third gate layer (GAT3), and the first source drain layer (SD1) may be superimposed in a vertical direction in the hole periphery region. Accordingly, the dead space caused by the hole (HL) in the hole periphery region can be reduced.

[0143] According to the present embodiment, a hole (HL) is formed within an active area (AA) of a display panel (100), and in a hole-periphery area where a gate layer (GAT1, GAT2, GAT3) and a source-drain layer (SD1) bypass the hole (HL), the gate layer (GAT1, GAT2, GAT3) and the source-drain layer (SD1) are arranged in a vertically overlapping direction to reduce the dead space in the hole-periphery area. Industrial applicability

[0144] According to the display panel and display device of the present invention described above, the dead space around the hole within the active area of ​​the display panel can be reduced.

[0145] Although the invention has been described with reference to the above embodiments, those skilled in the art will understand that various modifications and changes can be made to the invention without departing from the spirit and scope of the invention as described in the following claims. Explanation of the symbols

[0146] 100: Display panel 200: Drive control unit 300: Gate driver 400: Gamma reference voltage generator 500: Data driver 600: Emission driver

Claims

Claim 1 A display panel comprising: a first metal layer disposed on a first plane; a second metal layer disposed on a second plane different from the first plane; and a third metal layer disposed on a third plane different from the first plane and the second plane, wherein the first pattern of the first metal layer has a portion that bends or folds along a hole periphery area corresponding to the periphery of a hole formed in an active area, the second pattern of the second metal layer has a portion that bends or folds along the hole periphery area, and the third pattern of the third metal layer has a portion that bends or folds along the hole periphery area, and the bending or folded portion of the first pattern, the bending or folded portion of the second pattern, and the bending or folded portion of the third pattern overlap in the thickness direction of the display panel in the hole periphery area. Claim 2 A display panel according to claim 1, characterized in that the first metal layer is a first gate layer, the second metal layer is a second gate layer, and the third metal layer is a source drain layer. Claim 3 A display panel according to claim 2, characterized in that a first gate signal is applied to the first gate layer, and a second gate signal different from the first gate signal is applied to the second gate layer. Claim 4 A display panel characterized by further including pixels comprising a P-type transistor and an N-type transistor in paragraph 2. Claim 5 A display panel according to claim 4, wherein the first gate layer includes a P-type gate line that outputs a P-type gate signal to the P-type transistor, and the second gate layer includes a back gate electrode of the P-type transistor or the N-type transistor and a connection line of the back gate electrode. Claim 6 A display panel according to claim 4, wherein the first gate layer includes a P-type gate line that outputs a P-type gate signal to the P-type transistor, and the second gate layer includes an N-type gate line that outputs an N-type gate signal to the N-type transistor. Claim 7 A display panel according to claim 2, further comprising: a second gate insulating layer disposed on the first gate layer; and a first passivation layer disposed on the second gate layer. Claim 8 A display panel according to claim 7, further comprising: a third gate layer disposed on the first passivation layer; and a second passivation layer disposed on the third gate layer, wherein the source drain layer is disposed on the second passivation layer. Claim 9 A display panel according to claim 8, wherein the fourth pattern of the third gate layer has a portion that bends or folds along the area around the hole, and the bending or folded portion of the first pattern, the bending or folded portion of the second pattern, the bending or folded portion of the third pattern, and the bending or folded portion of the fourth pattern overlap in the thickness direction of the display panel in the area around the hole. Claim 10 A display panel characterized by further including pixels comprising a P-type transistor and an N-type transistor in claim 8. Claim 11 A display panel according to claim 10, wherein the first gate layer comprises a P-type gate line that outputs a P-type gate signal to the P-type transistor, the second gate layer comprises a back gate electrode of the P-type transistor or the N-type transistor and a connection line of the back gate electrode, and the third gate layer comprises an N-type gate line that outputs an N-type gate signal to the N-type transistor. Claim 12 A display panel according to paragraph 2, characterized in that the first gate layer does not overlap with the second gate layer in the thickness direction of the display panel in a general area other than the hole surrounding area. Claim 13 A display panel according to claim 2, further comprising: a first organic insulating layer disposed on the source drain layer; a second source drain layer disposed on the first organic insulating layer; and a second organic insulating layer disposed on the second source drain layer. Claim 14 A display panel according to claim 13, characterized in that the source drain layer does not overlap with the second source drain layer and the general area other than the hole periphery area in the thickness direction of the display panel. Claim 15 A display panel according to claim 14, characterized in that the source drain layer overlaps the second source drain layer and the hole periphery region in the thickness direction of the display panel.

Images