Display apparatus and method of driving the same

Abstract

The display device includes a light-emitting element, a driving switching element, a first compensation switching element, and a second compensation switching element. The driving switching element applies a driving current to the light-emitting element. The first compensation switching element and the second compensation switching element are positioned between the control electrode and the output electrode of the driving switching element and are connected in series with each other. A compensation gate signal is applied to the control electrode of the first compensation switching element and the control electrode of the second compensation switching element. The falling waveform of the compensation gate signal and the rising waveform of the compensation gate signal are set asymmetrically.

Description

Technology Field

[0001] The present invention relates to a display device and a driving method for the display device, and more specifically, to a display device and a driving method for the display device that improves display quality by controlling the voltage level of a node between a first compensation transistor and a second compensation transistor. Background Technology

[0002] Generally, a display device includes a display panel and a display panel driver. The display panel includes a plurality of gate lines, a plurality of data lines, a plurality of emission lines, and a plurality of pixels. The display panel driver includes a gate driver that provides a gate signal to the plurality of gate lines, a data driver that provides a data voltage to the data lines, an emission driver that provides an emission signal to the emission lines, and a driving control unit that controls the gate driver, the data driver, and the emission driver.

[0003] When the image displayed on the display panel is a still image or when the display panel operates in an always-on mode, the driving frequency of the display panel can be reduced to reduce power consumption.

[0004] If the driving frequency of the above display panel is reduced, the display quality of the display panel may deteriorate due to current leakage. The problem to be solved

[0005] The objective of the present invention is to provide a display device capable of improving the display quality of a display panel.

[0006] Another objective of the present invention is to provide a method for driving the display device. means of solving the problem

[0007] A display device according to one embodiment for realizing the purpose of the present invention described above includes a light-emitting element, a driving switching element, a first compensation switching element, and a second compensation switching element. The driving switching element applies a driving current to the light-emitting element. The first compensation switching element and the second compensation switching element are disposed between the control electrode and the output electrode of the driving switching element and are connected in series with each other. A compensation gate signal is applied to the control electrode of the first compensation switching element and the control electrode of the second compensation switching element. The falling waveform of the compensation gate signal and the rising waveform of the compensation gate signal are set asymmetrically.

[0008] In one embodiment of the present invention, the compensation gate signal may be polled from a high level to a low level, rise from the low level to an intermediate high level, and rise from the intermediate high level to the high level.

[0009] In one embodiment of the present invention, the compensation gate signal may be maintained for the first half of the light emission period by rising from the low level to the intermediate high level, and may be maintained for the second half of the light emission period by rising from the intermediate high level to the high level.

[0010] In one embodiment of the present invention, the compensation gate signal may be polled from a high level to a low level and rise from the low level to the high level. When the compensation gate signal rises from the low level to the high level, it may have a first rising slew rate and a second rising slew rate smaller than the first rising slew rate in sequence.

[0011] In one embodiment of the present invention, the compensation gate signal may be polled from a high level to a low level and rise from the low level to the high level. The rising slew rate of the compensation gate signal may be smaller than the falling slew rate of the compensation gate signal.

[0012] In one embodiment of the present invention, for a first grayscale greater than or equal to a reference grayscale, the compensation gate signal may have a first rising slew rate. For a second grayscale smaller than the reference grayscale, the compensation gate signal may have a second rising slew rate greater than the first rising slew rate.

[0013] In one embodiment of the present invention, for the first grayscale, the compensation gate signal may have a first on time. For the second grayscale, the compensation gate signal may have a second on time longer than the first on time.

[0014] In one embodiment of the present invention, the display device may further include a data writing switching element comprising a control electrode to which a data writing gate signal is applied, an input electrode to which a data voltage is applied, and an output electrode connected to the input electrode of the driving switching element.

[0015] In one embodiment of the present invention, when the data writing gate signal is polled, the compensation gate signal may be polled.

[0016] In one embodiment of the present invention, the display device may further include a first initialization switching element and a second initialization switching element connected in series with each other, which are disposed between the control electrode of the driving switching element and the application node of the initialization voltage.

[0017] In one embodiment of the present invention, a data initialization gate signal may be applied to the control electrode of the first initialization switching element and the control electrode of the second initialization switching element. When the data initialization gate signal rises, the compensation gate signal may be polled.

[0018] In one embodiment of the present invention, the pixel of the display device comprises: a first pixel switching element including a control electrode connected to a first node, an input electrode connected to a second node, and an output electrode connected to a third node; a second pixel switching element including a control electrode to which a data write gate signal is applied, an input electrode to which a data voltage is applied, and an output electrode connected to the second node; a third-1 pixel switching element including a control electrode to which a compensation gate signal is applied, an input electrode connected to the first node, and an output electrode connected to a fourth node; a third-2 pixel switching element including a control electrode to which the compensation gate signal is applied, an input electrode connected to the fourth node, and an output electrode connected to the third node; a fourth-1 pixel switching element including a control electrode to which a data initialization gate signal is applied, an input electrode connected to a fifth node, and an output electrode connected to the first node; a fourth-2 pixel switching element including a control electrode to which the data initialization gate signal is applied, an input electrode to which a first initialization voltage is applied, and an output electrode connected to the fifth node; a control electrode to which an emission signal is applied; and a first power supply. A fifth pixel switching element comprising an input electrode to which a voltage is applied and an output electrode connected to the second node; a sixth pixel switching element comprising a control electrode to which an emission signal is applied, an input electrode connected to the third node, and an output electrode connected to the anode electrode of the light-emitting element; a seventh pixel switching element comprising a control electrode to which a light-emitting element initialization gate signal is applied, an input electrode to which a second initialization voltage is applied, and an output electrode connected to the anode electrode of the light-emitting element; an eighth pixel switching element comprising a control electrode to which the light-emitting element initialization gate signal is applied, an input electrode to which a bias voltage is applied, and an output electrode connected to the second node.It may include a storage capacitor comprising a first electrode to which the first power supply voltage is applied and a second electrode connected to the first node, and the light-emitting element comprising the anode electrode and a cathode electrode to which the second power supply voltage is applied. The driving switching element may be the first pixel switching element, the first compensation switching element may be the third-1 pixel switching element, and the second compensation switching element may be the third-2 pixel switching element.

[0019] In one embodiment of the present invention, the pixel of the display device comprises: a first pixel switching element including a control electrode connected to a first node, an input electrode connected to a second node, and an output electrode connected to a third node; a second pixel switching element including a control electrode to which a data write gate signal is applied, an input electrode to which a data voltage is applied, and an output electrode connected to the second node; a third-1 pixel switching element including a control electrode to which a compensation gate signal is applied, an input electrode connected to the first node, and an output electrode connected to a fourth node; a third-2 pixel switching element including a control electrode to which the compensation gate signal is applied, an input electrode connected to the fourth node, and an output electrode connected to the third node; a fourth-1 pixel switching element including a control electrode to which a data initialization gate signal is applied, an input electrode connected to a fifth node, and an output electrode connected to the first node; a fourth-2 pixel switching element including a control electrode to which the data initialization gate signal is applied, an input electrode to which a first initialization voltage is applied, and an output electrode connected to the fifth node; a control electrode to which an emission signal is applied; and a first power supply. A fifth pixel switching element comprising an input electrode to which a voltage is applied and an output electrode connected to the second node; a sixth pixel switching element comprising a control electrode to which an emission signal is applied, an input electrode connected to the third node, and an output electrode connected to the anode electrode of the light-emitting element; a seventh pixel switching element comprising a control electrode to which a light-emitting element initialization gate signal is applied, an input electrode to which a first initialization voltage is applied, and an output electrode connected to the anode electrode of the light-emitting element; an eighth pixel switching element comprising a control electrode to which a light-emitting element initialization gate signal is applied, an input electrode to which a bias voltage is applied, and an output electrode connected to the second node.It may include a storage capacitor comprising a first electrode to which the first power supply voltage is applied and a second electrode connected to the first node, and the light-emitting element comprising the anode electrode and a cathode electrode to which the second power supply voltage is applied. The driving switching element may be the first pixel switching element, the first compensation switching element may be the third-1 pixel switching element, and the second compensation switching element may be the third-2 pixel switching element.

[0020] In one embodiment of the present invention, the pixel of the display device comprises: a first pixel switching element including a control electrode connected to a first node, an input electrode connected to a second node, and an output electrode connected to a third node; a second pixel switching element including a control electrode to which a data write gate signal is applied, an input electrode to which a data voltage is applied, and an output electrode connected to the second node; a third-1 pixel switching element including a control electrode to which a compensation gate signal is applied, an input electrode connected to the first node, and an output electrode connected to a fourth node; a third-2 pixel switching element including a control electrode to which the compensation gate signal is applied, an input electrode connected to the fourth node, and an output electrode connected to the third node; a fourth-1 pixel switching element including a control electrode to which a data initialization gate signal is applied, an input electrode connected to a fifth node, and an output electrode connected to the first node; a fourth-2 pixel switching element including a control electrode to which the data initialization gate signal is applied, an input electrode to which a first initialization voltage is applied, and an output electrode connected to the fifth node; a control electrode to which an emission signal is applied; and a first power supply. It may include a fifth pixel switching element comprising an input electrode to which a voltage is applied and an output electrode connected to the second node; a sixth pixel switching element comprising a control electrode to which an emission signal is applied, an input electrode connected to the third node and an output electrode connected to the anode electrode of the light-emitting element; a seventh pixel switching element comprising a control electrode to which a light-emitting element initialization gate signal is applied, an input electrode to which a second initialization voltage is applied, and an output electrode connected to the anode electrode of the light-emitting element; a storage capacitor comprising a first electrode to which the first power supply voltage is applied and a second electrode connected to the first node; and the light-emitting element comprising the anode electrode and a cathode electrode to which the second power supply voltage is applied.The driving switching element is the first pixel switching element, the first compensation switching element is the third-1 pixel switching element, and the second compensation switching element may be the third-2 pixel switching element.

[0021] In one embodiment of the present invention, the pixel of the display device comprises: a first pixel switching element including a control electrode connected to a first node, an input electrode connected to a second node, and an output electrode connected to a third node; a second pixel switching element including a control electrode to which a data write gate signal is applied, an input electrode to which a data voltage is applied, and an output electrode connected to the second node; a third-1 pixel switching element including a control electrode to which a compensation gate signal is applied, an input electrode connected to the first node, and an output electrode connected to a fourth node; a third-2 pixel switching element including a control electrode to which the compensation gate signal is applied, an input electrode connected to the fourth node, and an output electrode connected to the third node; a fourth-1 pixel switching element including a control electrode to which a data initialization gate signal is applied, an input electrode connected to a fifth node, and an output electrode connected to the first node; a fourth-2 pixel switching element including a control electrode to which the data initialization gate signal is applied, an input electrode to which a first initialization voltage is applied, and an output electrode connected to the fifth node; a control electrode to which an emission signal is applied; and a first power supply. It may include a fifth pixel switching element comprising an input electrode to which a voltage is applied and an output electrode connected to the second node; a sixth pixel switching element comprising a control electrode to which an emission signal is applied, an input electrode connected to the third node and an output electrode connected to the anode electrode of the light-emitting element; a seventh pixel switching element comprising a control electrode to which a light-emitting element initialization gate signal is applied, an input electrode to which a first initialization voltage is applied and an output electrode connected to the anode electrode of the light-emitting element; a storage capacitor comprising a first electrode to which a first power supply voltage is applied and a second electrode connected to the first node; and the light-emitting element comprising the anode electrode and a cathode electrode to which a second power supply voltage is applied.The driving switching element is the first pixel switching element, the first compensation switching element is the third-1 pixel switching element, and the second compensation switching element may be the third-2 pixel switching element.

[0022] A display device according to one embodiment for realizing the purpose of the present invention described above includes a light-emitting element, a driving switching element, a first compensation switching element, and a second compensation switching element. The driving switching element applies a driving current to the light-emitting element. The first compensation switching element and the second compensation switching element are disposed between the control electrode and the output electrode of the driving switching element and are connected in series with each other. A compensation gate signal is applied to the control electrode of the first compensation switching element and the control electrode of the second compensation switching element. When the driving frequency is smaller than the reference frequency, the falling waveform of the compensation gate signal and the rising waveform of the compensation gate signal are set asymmetrically. When the driving frequency is greater than or equal to the reference frequency, the falling waveform of the compensation gate signal and the rising waveform of the compensation gate signal are set symmetrically.

[0023] In one embodiment of the present invention, when the driving frequency is smaller than the reference frequency, the compensation gate signal may be polled from a high level to a low level, rise from the low level to an intermediate high level, and rise from the intermediate high level to the high level.

[0024] In one embodiment of the present invention, when the driving frequency is smaller than the reference frequency, the compensation gate signal may be polled from a high level to a low level and rise from the low level to the high level. When the driving frequency is smaller than the reference frequency and the compensation gate signal rises from the low level to the high level, a first rising slew rate and a second rising slew rate smaller than the first rising slew rate may be successively provided.

[0025] In one embodiment of the present invention, when the driving frequency is smaller than the reference frequency, the compensation gate signal may be fell from a high level to a low level and rise from the low level to the high level. When the driving frequency is smaller than the reference frequency, the rising slew rate of the compensation gate signal may be smaller than the falling slew rate of the compensation gate signal.

[0026] In one embodiment of the present invention, when the driving frequency is smaller than the reference frequency, the compensation gate signal may have a first rising slew rate for a first grayscale that is greater than or equal to the reference grayscale. When the driving frequency is smaller than the reference frequency, the compensation gate signal may have a second rising slew rate greater than the first rising slew rate for a second grayscale that is smaller than the reference grayscale.

[0027] A driving method for a display device according to an embodiment for realizing the above-described objective of the present invention includes the steps of providing a data write gate signal and a compensation gate signal to a pixel, providing a data voltage to the pixel, and providing an emission signal to the pixel. The pixel includes a light-emitting element, a driving switching element that applies a driving current to the light-emitting element, and a first compensation switching element and a second compensation switching element that are disposed between the control electrode and the output electrode of the driving switching element and are connected in series with each other. The compensation gate signal is applied to the control electrode of the first compensation switching element and the control electrode of the second compensation switching element. The falling waveform of the compensation gate signal and the rising waveform of the compensation gate signal are set asymmetrically. Effects of the invention

[0028] According to such a display device and a driving method of the display device, when the image displayed on the display panel is a still image or when the display panel operates in a continuous display mode, the driving frequency of the display panel can be reduced to reduce the power consumption of the display device.

[0029] By setting the falling waveform and rising waveform of the compensation switching signal applied to the control electrodes of the first compensation switching element and the second compensation switching element asymmetrically, an increase in the voltage of the node between the first compensation switching element and the second compensation switching element can be prevented.

[0030] By preventing an increase in the voltage at the node between the first compensation switching element and the second compensation switching element, current leakage of the first compensation switching element and the second compensation switching element is prevented during low-frequency driving, thereby preventing a decrease in brightness and flicker of the display panel in low-frequency driving mode and improving display quality. Brief explanation of the drawing

[0031] FIG. 1 is a block diagram showing a display device according to one embodiment of the present invention. Figure 2 is a circuit diagram showing the pixels of the display panel of Figure 1. Figure 3 is a timing diagram showing an example of input signals and node voltages applied to the pixel of Figure 2. Figure 4 is a timing diagram showing an example of input signals and node voltages applied to the pixel of Figure 2. Figure 5 is a timing diagram showing an example of input signals and node voltages applied to the pixel of Figure 2. FIG. 6a is a timing diagram showing an example of input signals and node voltages applied to the pixel of FIG. 2 in high grayscale. FIG. 6b is a timing diagram showing an example of input signals and node voltages applied to the pixels of FIG. 2 in low grayscale. Figure 7 is a timing diagram showing an example of input signals and node voltages applied to the pixel of Figure 2. FIG. 8a is a timing diagram showing an example of input signals and node voltages applied to the pixel of FIG. 2 in a low-frequency driving mode. FIG. 8b is a timing diagram showing an example of input signals and node voltages applied to the pixel of FIG. 2 in high-frequency driving mode. FIG. 9a is a timing diagram showing an example of input signals and node voltages applied to the pixel of FIG. 2 in a low-frequency driving mode. FIG. 9b is a timing diagram showing an example of input signals and node voltages applied to the pixel of FIG. 2 in high-frequency driving mode. FIG. 10a is a timing diagram showing an example of input signals and node voltages applied to the pixel of FIG. 2 in a low-frequency driving mode. FIG. 10b is a timing diagram showing an example of input signals and node voltages applied to the pixel of FIG. 2 in high-frequency driving mode. FIG. 11a is a timing diagram showing an example of input signals and node voltages applied to the pixels of FIG. 2 in a low-frequency driving mode and high grayscale. FIG. 11b is a timing diagram showing an example of input signals and node voltages applied to the pixels of FIG. 2 in a low-frequency driving mode and low grayscale. FIG. 11c is a timing diagram showing an example of input signals and node voltages applied to the pixel of FIG. 2 in high-frequency driving mode. FIG. 12a is a timing diagram showing an example of input signals and node voltages applied to the pixel of FIG. 2 in a low-frequency driving mode. FIG. 12b is a timing diagram showing an example of input signals and node voltages applied to the pixel of FIG. 2 in high-frequency driving mode. FIG. 13 is a circuit diagram showing a pixel of a display panel of a display device according to one embodiment of the present invention. FIG. 14 is a circuit diagram showing a pixel of a display panel of a display device according to one embodiment of the present invention. FIG. 15 is a circuit diagram showing a pixel of a display panel of a display device according to one embodiment of the present invention. Specific details for implementing the invention

[0032] Hereinafter, the present invention will be described in more detail with reference to the attached drawings.

[0033] FIG. 1 is a block diagram showing a display device according to one embodiment of the present invention.

[0034] Referring to FIG. 1, the display device includes a display panel (100) and a display panel driver. The display panel driver includes a drive control unit (200), a gate driver (300), a gamma reference voltage generator (400), a data driver (500), and an emission driver (600).

[0035] The above display panel (100) includes a display portion for displaying an image and a peripheral portion arranged adjacent to the display portion.

[0036] The display panel (100) comprises a plurality of gate lines (GWL, GCL, GIL, EBL), a plurality of data lines (DL), a plurality of emission lines (EL), and a plurality of pixels electrically connected to each of the gate lines (GWL, GCL, GIL, EBL), the data lines (DL), and the emission lines (EL). The gate lines (GWL, GCL, GIL, EBL) extend in a first direction (D1), the data lines (DL) extend in a second direction (D2) that intersects the first direction (D1), and the emission lines (EL) extend in the first direction (D1).

[0037] The drive control unit (200) receives input image data (IMG) and an input control signal (CONT) from an external device. For example, the input image data (IMG) may include red image data, green image data, and blue image data. The input image data (IMG) may include white image data. The input image data (IMG) may include magenta image data, yellow image data, and cyan image data. The input control signal (CONT) may include a master clock signal and a data enable signal. The input control signal (CONT) may further include a vertical synchronization signal and a horizontal synchronization signal.

[0038] The above driving control unit (200) generates a first control signal (CONT1), a second control signal (CONT2), a third control signal (CONT3), a fourth control signal (CONT4), and a data signal (DATA) based on the input image data (IMG) and the input control signal (CONT).

[0039] The above drive control unit (200) generates the first control signal (CONT1) to control the operation of the gate drive unit (300) based on the input control signal (CONT) and outputs it to the gate drive unit (300). The first control signal (CONT1) may include a vertical start signal and a gate clock signal.

[0040] The above drive control unit (200) generates the second control signal (CONT2) to control the operation of the data drive unit (500) based on the input control signal (CONT) and outputs it to the data drive unit (500). The second control signal (CONT2) may include a horizontal start signal and a load signal.

[0041] The above drive control unit (200) generates a data signal (DATA) based on the input image data (IMG). The above drive control unit (200) outputs the data signal (DATA) to the data drive unit (500).

[0042] The above driving control unit (200) generates the third control signal (CONT3) to control the operation of the gamma reference voltage generation unit (400) based on the input control signal (CONT) and outputs it to the gamma reference voltage generation unit (400).

[0043] The above drive control unit (200) generates the fourth control signal (CONT4) to control the operation of the emission drive unit (600) based on the input control signal (CONT) and outputs it to the emission drive unit (600).

[0044] The gate driving unit (300) generates gate signals for driving the gate lines (GWL, GCL, GIL, EBL) in response to the first control signal (CONT1) received from the driving control unit (200). The gate driving unit (300) can output the gate signals to the gate lines (GWL, GCL, GIL, EBL).

[0045] The gamma reference voltage generation unit (400) generates a gamma reference voltage (VGREF) in response to the third control signal (CONT3) received from the driving control unit (200). The gamma reference voltage generation unit (400) provides the gamma reference voltage (VGREF) to the data driving unit (500). The gamma reference voltage (VGREF) has a value corresponding to each data signal (DATA).

[0046] For example, the gamma reference voltage generation unit (400) may be placed within the drive control unit (200) or within the data drive unit (500).

[0047] The data driving unit (500) receives the second control signal (CONT2) and the data signal (DATA) from the driving control unit (200), and receives the gamma reference voltage (VGREF) from the gamma reference voltage generation unit (400). The data driving unit (500) converts the data signal (DATA) into an analog data voltage using the gamma reference voltage (VGREF). The data driving unit (500) outputs the data voltage to the data line (DL).

[0048] The emission driving unit (600) generates emission signals to drive the emission lines (EL) in response to the fourth control signal (CONT4) received from the driving control unit (200). The emission driving unit (600) can output the emission signals to the emission lines (EL).

[0049] In FIG. 1, for convenience of explanation, the gate driving unit (300) is shown as being positioned on the first side of the display panel (100) and the emission driving unit (600) is shown as being positioned on the second side of the display panel (100), but the present invention is not limited thereto. For example, both the gate driving unit (300) and the emission driving unit (600) may be positioned on the first side of the display panel (100). For example, the gate driving unit (300) and the emission driving unit (600) may be formed integrally.

[0050] FIG. 2 is a circuit diagram showing a pixel of the display panel (100) of FIG. 1. FIG. 3 is a timing diagram showing an example of input signals and node voltages applied to the pixel of FIG. 2.

[0051] Referring to FIGS. 1 to 3, the display panel (100) includes a plurality of pixels, and each of the pixels includes a light-emitting element (EE).

[0052] The pixels receive a data write gate signal (GW), a compensation gate signal (GC), a data initialization gate signal (GI), a light-emitting element initialization gate signal (EB), the data voltage (VDATA), and the emission signal (EM), and emit light from the light-emitting element (EE) according to the level of the data voltage (VDATA) to display the image.

[0053] The pixel may include a light-emitting element (EE), a driving switching element (T1) that applies a driving current to the light-emitting element (EE), and a first compensation switching element (T3-1) and a second compensation switching element (T3-2) that are disposed between the control electrode and the output electrode of the driving switching element (T1) and are connected in series with each other.

[0054] The pixel may further include a data writing switching element (T2) comprising a control electrode to which a data writing gate signal (GW) is applied, an input electrode to which a data voltage (VDATA) is applied, and an output electrode connected to the input electrode of the driving switching element (T1).

[0055] The pixel may further include a first initialization switching element (T4-1) and a second initialization switching element (T4-2) connected in series with each other, which are positioned between the control electrode of the driving switching element (T1) and the application node of the first initialization voltage (VINT).

[0056] More specifically, the pixel may include first, second, third-1, third-2, fourth-1, fourth-2, fifth, sixth, seventh, and eighth pixel switching elements (T1, T2, T3-1, T3-2, T4-1, T4-2, T5, T6, T7, and T8), a storage capacitor (CST), and the light-emitting element (EE).

[0057] The first pixel switching element (T1) includes a control electrode connected to a first node (N1), an input electrode connected to a second node (N2), and an output electrode connected to a third node (N3). The first pixel switching element (T1) may be the driving switching element.

[0058] The second pixel switching element (T2) includes a control electrode to which the data write gate signal (GW) is applied, an input electrode to which the data voltage (VDATA) is applied, and an output electrode connected to the second node (N2). The second pixel switching element (T2) may be the data write switching element.

[0059] The above 3-1 pixel switching element (T3-1) includes a control electrode to which the compensation gate signal (GC) is applied, an input electrode connected to the first node (N1), and an output electrode connected to the fourth node (N4). The above 3-1 pixel switching element (T3-1) may be the first compensation switching element.

[0060] The above third-2 pixel switching element (T3-2) includes a control electrode to which the compensation gate signal (GC) is applied, an input electrode connected to the fourth node (N4), and an output electrode connected to the third node (N3). The above third-2 pixel switching element (T3-2) may be the second compensation switching element.

[0061] The above 4-1 pixel switching element (T4-1) includes a control electrode to which the data initialization gate signal (GI) is applied, an input electrode connected to the 5th node (N5), and an output electrode connected to the 1st node (N1). The above 4-1 pixel switching element (T4-1) may be the 1st initialization switching element.

[0062] The above 4-2 pixel switching element (T4-2) includes a control electrode to which the data initialization gate signal (GI) is applied, an input electrode to which the first initialization voltage (VINT) is applied, and an output electrode connected to the fifth node (N5). The above 4-2 pixel switching element (T4-2) may be the second initialization switching element.

[0063] The fifth pixel switching element (T5) includes a control electrode to which the emission signal (EM) is applied, an input electrode to which the first power supply voltage (ELVDD) is applied, and an output electrode connected to the second node (N2).

[0064] The sixth pixel switching element (T6) includes a control electrode to which the emission signal (EM) is applied, an input electrode connected to the third node (N3), and an output electrode connected to the anode electrode of the light-emitting element (EE).

[0065] The seventh pixel switching element (T7) includes a control electrode to which the light-emitting element initialization gate signal (EB) is applied, an input electrode to which the second initialization voltage (VAINT) is applied, and an output electrode connected to the anode electrode of the light-emitting element (EE).

[0066] The seventh pixel switching element (T7) includes a control electrode to which the light-emitting element initialization gate signal (EB) is applied, an input electrode to which a bias voltage (VBIAS) is applied, and an output electrode connected to the second node (N2).

[0067] For example, the first, second, third-1, third-2, fourth-1, fourth-2, fifth, sixth, seventh, and eighth pixel switching elements (T1, T2, T3-1, T3-2, T4-1, T4-2, T5, T6, T7, and T8) may be polysilicon thin-film transistors. The first, second, third-1, third-2, fourth-1, fourth-2, fifth, sixth, seventh, and eighth pixel switching elements (T1, T2, T3-1, T3-2, T4-1, T4-2, T5, T6, T7, and T8) may be P-type thin-film transistors. The control electrode of the first, second, third-1, third-2, fourth-1, fourth-2, fifth, sixth, seventh, and eighth pixel switching elements (T1, T2, T3-1, T3-2, T4-1, T4-2, T5, T6, T7, and T8) is a gate electrode, the input electrode of the first, second, third-1, third-2, fourth-1, fourth-2, fifth, sixth, seventh, and eighth pixel switching elements (T1, T2, T3-1, T3-2, T4-1, T4-2, T5, T6, T7, and T8) is a source electrode, and the first, second, third-1, third-2, fourth-1, fourth-2, fifth, sixth, seventh, and eighth pixel switching elements (T1, T2, T3-1, T3-2, T4-1, T4-2, T5, The output electrodes of T6, T7, and T8 may be drain electrodes. Here, the input electrode and the output electrode may be referred to interchangeably. Likewise, the source electrode and the drain electrode may be referred to interchangeably.

[0068] The storage capacitor (CST) includes a first electrode to which the first power supply voltage (ELVDD) is applied and a second electrode connected to the first node (N1).

[0069] The light-emitting element (EE) includes the anode electrode and the cathode electrode to which the second power supply voltage (ELVSS) is applied.

[0070] A compensation gate signal (GC) may be applied to the control electrode of the first compensation switching element (e.g., T3-1) and the control electrode of the second compensation switching element (e.g., T3-2).

[0071] Referring to FIG. 3, in this embodiment, the falling waveform of the compensation gate signal (GC) and the rising waveform of the compensation gate signal (GC) can be set asymmetrically. For example, the compensation gate signal (GC) can be fallen from a high level to a low level, rise from the low level to an intermediate high level, and rise from the intermediate high level to the high level.

[0072] Specifically, during the first interval (DU1), the emission signal (EM), the data initialization gate signal (GI), the data write gate signal (GW), and the compensation gate signal (GC) may have an inactive level.

[0073] During the second section (DU2) following the first section (DU1), the emission signal (EM) may have an inactive level, the data initialization gate signal (GI) may have an active level, the data write gate signal (GW) may have an inactive level, and the compensation gate signal (GC) may have an inactive level.

[0074] During the third section (DU3) following the second section (DU2), the emission signal (EM) may have an inactive level, the data initialization gate signal (GI) may have an inactive level, the data write gate signal (GW) may have an active level, and the compensation gate signal (GC) may have an active level.

[0075] During the fourth section (DU4) and the fifth section (DU5) following the third section (DU3), the emission signal (EM) may have an inactive level, the data initialization gate signal (GI) may have an inactive level, the data write gate signal (GW) may have an inactive level, and the compensation gate signal (GC) may have an inactive level (intermediate high level).

[0076] During the 6-1 section (DU6-1) following the 5th section (DU5), the emission signal (EM) has an active level, the data initialization gate signal (GI) has an inactive level, the data write gate signal (GW) has an inactive level, and the compensation gate signal (GC) may have an inactive level (intermediate high level).

[0077] During the 6-2 section (DU6-2) following the 6-1 section (DU6-1), the emission signal (EM) may have an active level, the data initialization gate signal (GI) may have an inactive level, the data write gate signal (GW) may have an inactive level, and the compensation gate signal (GC) may have an inactive level (high level).

[0078] For example, during the second interval (DU2), the first node (N1) and the storage capacitor (CST) may be initialized by the data initialization gate signal (GI). During the third interval (DU3), the threshold voltage (|VTH|) of the first pixel switching element (T1) is compensated by the data write gate signal (GW) and the compensation gate signal (GC), and the data voltage (VDATA) with the threshold voltage (|VTH|) compensated may be written to the first node (N1). During the 6-1 interval (DU6-1) and the 6-2 interval (DU6-2), the light-emitting element (EE) emits light by the emission signal (EM), and the display panel (100) displays an image.

[0079] In this embodiment, when the data write gate signal (GW) is polled (at the boundary between DU2 and DU3), the compensation gate signal (GC) may be polled. Additionally, when the data initialization gate signal (GI) rises (at the boundary between DU2 and DU3), the compensation gate signal (GC) may be polled.

[0080] In this embodiment, when the image displayed on the display panel (100) is a still image or when the display panel (100) operates in an always-on mode, the driving frequency of the display panel (100) can be reduced to reduce power consumption.

[0081] Additionally, the display panel (100) may be driven at a variable frequency. For example, a first frame having a first frequency may include a first active section and a first blank section. A second frame having a second frequency different from the first frequency may include a second active section and a second blank section. A third frame having a third frequency different from the first frequency and the second frequency may include a third active section (AC3) and a third blank section.

[0082] Here, the first active section has the same length as the second active section, and the first blank section may have a different length from the second active section. The second active section has the same length as the third active section, and the second blank section may have a different length from the third active section.

[0083] A display device supporting variable frequency may include a data writing section in which data voltage is written to a pixel and a self-scan section in which data voltage is not written to a pixel and only light is emitted. The data writing section may be placed within the active section. The self-scan section may be placed within the blank section.

[0084] When the above display panel (100) operates in a low-frequency driving mode, current leakage occurs in the 3-1 and 3-2 pixel switching elements (T3-1, T3-2), causing the brightness of the display panel (100) to decrease undesirably. After the brightness of the display panel (100) decreases undesirably in this way, when a data voltage (VDATA) is applied to the pixel, the brightness of the display panel (100) becomes brighter and is visible as flicker.

[0085] In particular, when the voltage at the fourth node (N4) of FIG. 2 varies, there is a problem that the voltage at the first node (N1) varies as a result, causing unwanted changes in brightness. When the compensation gate signal (GC) rises, the voltage at the fourth node (N4) rises together. The high peak level (VP) of the voltage at the fourth node (N4) is proportional to the rising slew rate of the compensation gate signal (GC) and may be proportional to the difference between the high level and the low level of the compensation gate signal (GC).

[0086] To solve this problem, as described above, in this embodiment, the falling waveform of the compensation gate signal (GC) and the rising waveform of the compensation gate signal (GC) can be set asymmetrically.

[0087] In particular, in FIG. 3, the compensation gate signal (GC) may be polled from a high level to a low level, rise from the low level to an intermediate high level, and rise from the intermediate high level to the high level. That is, in the rising step, instead of rising directly from the low level to the high level, it rises in two stages via the intermediate high level, so the high peak level (VP) of the voltage of the fourth node (N4) can be reduced.

[0088] In FIG. 3, the compensation gate signal (GC) may rise from the low level to the intermediate high level and be maintained for the first half (DU6-1) of the emission interval, and rise from the intermediate high level to the high level and be maintained for the second half (DU6-2) of the emission interval. In FIG. 3, the emission interval may be defined from the end point of the fifth interval (DU5) to the start point of the first interval (DU1) of the next frame. However, the time during which the compensation gate signal (GC) maintains the intermediate high level is not necessarily limited to the first half (DU6-1) of the emission interval, but may include a part of the emission interval.

[0089] According to the present embodiment, when the image displayed on the display panel (100) is a still image or when the display panel (100) operates in a continuous display mode, the driving frequency of the display panel (100) can be reduced to reduce the power consumption of the display device.

[0090] By setting the falling waveform and rising waveform of the compensation switching signal (GC) applied to the control electrodes of the first compensation switching element (T3-1) and the second compensation switching element (T3-2) asymmetrically, it is possible to prevent an increase in the voltage of the node (N4) between the first compensation switching element (T3-1) and the second compensation switching element (T3-2).

[0091] By preventing an increase in the voltage of the node (N4) between the first compensation switching element (T3-1) and the second compensation switching element (T3-2), current leakage of the first compensation switching element (T3-1) and the second compensation switching element (T3-2) during low-frequency driving is prevented, thereby preventing a decrease in brightness and flicker of the display panel (100) in low-frequency driving mode and improving display quality.

[0092] Figure 4 is a timing diagram showing an example of input signals and node voltages applied to the pixel of Figure 2.

[0093] Since the display device according to the present embodiment is substantially the same as the display device of FIGS. 1 to 3 except for the waveform of the compensation gate signal (GC), the same reference numbers are used for identical or similar components, and redundant descriptions are omitted.

[0094] Referring to FIG. 4, in this embodiment, the falling waveform of the compensation gate signal (GC) and the rising waveform of the compensation gate signal (GC) can be set asymmetrically. For example, the compensation gate signal (GC) can be fallen from a high level to a low level and rise from the low level to the high level.

[0095] When the compensation gate signal (GC) rises from the low level to the high level, it may have a first rising slew rate and a second rising slew rate smaller than the first rising slew rate in sequence.

[0096] Here, the rising slew rate of the compensation gate signal (GC) indicates the degree to which the compensation gate signal (GC) increases over a predetermined short period of time; in the waveform diagram, a large rising slope of the compensation gate signal (GC) indicates a large rising slew rate, and a small rising slope of the compensation gate signal (GC) indicates a small rising slew rate.

[0097] Here, the falling slew rate of the compensation gate signal (GC) indicates the degree to which the compensation gate signal (GC) decreases over a predetermined short period of time; in the waveform diagram, a large absolute value of the slope of decrease of the compensation gate signal (GC) indicates a large falling slew rate, while a small absolute value of the slope of decrease of the compensation gate signal (GC) indicates a small falling slew rate.

[0098] Specifically, during the first interval (DU1), the emission signal (EM), the data initialization gate signal (GI), the data write gate signal (GW), and the compensation gate signal (GC) may have an inactive level.

[0099] During the second section (DU2) following the first section (DU1), the emission signal (EM) may have an inactive level, the data initialization gate signal (GI) may have an active level, the data write gate signal (GW) may have an inactive level, and the compensation gate signal (GC) may have an inactive level.

[0100] During the third section (DU3) following the second section (DU2), the emission signal (EM) may have an inactive level, the data initialization gate signal (GI) may have an inactive level, the data write gate signal (GW) may have an active level, and the compensation gate signal (GC) may have an active level.

[0101] During the fourth section (DU4) and the fifth section (DU5) following the third section (DU3), the emission signal (EM) may have an inactive level, the data initialization gate signal (GI) may have an inactive level, the data write gate signal (GW) may have an inactive level, and the compensation gate signal (GC) may have an inactive level.

[0102] During the sixth section (DU6) following the fifth section (DU5), the emission signal (EM) may have an active level, the data initialization gate signal (GI) may have an inactive level, the data write gate signal (GW) may have an inactive level, and the compensation gate signal (GC) may have an inactive level.

[0103] When the above display panel (100) operates in a low-frequency driving mode, current leakage occurs in the 3-1 and 3-2 pixel switching elements (T3-1, T3-2), causing the brightness of the display panel (100) to decrease undesirably. After the brightness of the display panel (100) decreases undesirably in this way, when a data voltage (VDATA) is applied to the pixel, the brightness of the display panel (100) becomes brighter and is visible as flicker.

[0104] In particular, when the voltage at the fourth node (N4) of FIG. 2 varies, there is a problem that the voltage at the first node (N1) varies as a result, causing unwanted changes in brightness. When the compensation gate signal (GC) rises, the voltage at the fourth node (N4) rises together. The high peak level (VP) of the voltage at the fourth node (N4) is proportional to the rising slew rate of the compensation gate signal (GC) and may be proportional to the difference between the high level and the low level of the compensation gate signal (GC).

[0105] To solve this problem, as described above, in this embodiment, the falling waveform of the compensation gate signal (GC) and the rising waveform of the compensation gate signal (GC) can be set asymmetrically.

[0106] In particular, in FIG. 4, the compensation gate signal (GC) is polled from a high level to a low level and rises from the low level to a high level, and when the compensation gate signal rises from the low level to the high level, it may sequentially have a first rising slew rate and a second rising slew rate smaller than the first rising slew rate. That is, in the rising stage of the compensation gate signal (GC), the compensation gate signal (GC) may have two rising slew rates, and due to the relatively small slew rate, the high peak level (VP) of the voltage of the fourth node (N4) can be reduced.

[0107] According to the present embodiment, when the image displayed on the display panel (100) is a still image or when the display panel (100) operates in a continuous display mode, the driving frequency of the display panel (100) can be reduced to reduce the power consumption of the display device.

[0108] By setting the falling waveform and rising waveform of the compensation switching signal (GC) applied to the control electrodes of the first compensation switching element (T3-1) and the second compensation switching element (T3-2) asymmetrically, it is possible to prevent an increase in the voltage of the node (N4) between the first compensation switching element (T3-1) and the second compensation switching element (T3-2).

[0109] By preventing an increase in the voltage of the node (N4) between the first compensation switching element (T3-1) and the second compensation switching element (T3-2), current leakage of the first compensation switching element (T3-1) and the second compensation switching element (T3-2) during low-frequency driving is prevented, thereby preventing a decrease in brightness and flicker of the display panel (100) in low-frequency driving mode and improving display quality.

[0110] Figure 5 is a timing diagram showing an example of input signals and node voltages applied to the pixel of Figure 2.

[0111] Since the display device according to the present embodiment is substantially the same as the display device of FIGS. 1 to 3 except for the waveform of the compensation gate signal (GC), the same reference numbers are used for identical or similar components, and redundant descriptions are omitted.

[0112] Referring to FIG. 5, in this embodiment, the falling waveform of the compensation gate signal (GC) and the rising waveform of the compensation gate signal (GC) can be set asymmetrically. For example, the compensation gate signal (GC) can be fallen from a high level to a low level and rise from the low level to the high level.

[0113] The rising slew rate of the compensation gate signal (GC) may be smaller than the falling slew rate of the compensation gate signal (GC). Due to the relatively small rising slew rate, the high peak level (VP) of the voltage of the fourth node (N4) can be reduced.

[0114] According to the present embodiment, when the image displayed on the display panel (100) is a still image or when the display panel (100) operates in a continuous display mode, the driving frequency of the display panel (100) can be reduced to reduce the power consumption of the display device.

[0115] By setting the falling waveform and rising waveform of the compensation switching signal (GC) applied to the control electrodes of the first compensation switching element (T3-1) and the second compensation switching element (T3-2) asymmetrically, it is possible to prevent an increase in the voltage of the node (N4) between the first compensation switching element (T3-1) and the second compensation switching element (T3-2).

[0116] By preventing an increase in the voltage of the node (N4) between the first compensation switching element (T3-1) and the second compensation switching element (T3-2), current leakage of the first compensation switching element (T3-1) and the second compensation switching element (T3-2) during low-frequency driving is prevented, thereby preventing a decrease in brightness and flicker of the display panel (100) in low-frequency driving mode and improving display quality.

[0117] FIG. 6a is a timing diagram showing an example of input signals and node voltages applied to a pixel of FIG. 2 in high grayscale. FIG. 6b is a timing diagram showing an example of input signals and node voltages applied to a pixel of FIG. 2 in low grayscale.

[0118] Since the display device according to the present embodiment is substantially the same as the display device of FIGS. 1 to 3 except for the waveform of the compensation gate signal (GC), the same reference numbers are used for identical or similar components, and redundant descriptions are omitted.

[0119] The change in brightness caused by the increase in voltage of the fourth node (N4) may be more severe in high grayscale than in low grayscale. This is because the level of the gate voltage of the driving switching element (T1) is relatively high in high grayscale.

[0120] FIG. 6a illustrates a situation where the display image of the display panel (100) is high grayscale, and FIG. 6b illustrates a situation where the display image of the display panel (100) is low grayscale.

[0121] Looking at FIG. 6a, for a first grayscale (high grayscale) that is greater than or equal to the reference grayscale, the compensation gate signal (GC) may have a first rising slew rate.

[0122] On the other hand, looking at FIG. 6b, for a second gradation (low gradation) smaller than the reference gradation, the compensation gate signal (GC) may have a second rising slew rate greater than the first rising slew rate.

[0123] Also, looking at FIG. 6a, for the first grayscale, the compensation gate signal (GC) may have a first on time (OT1).

[0124] On the other hand, looking at FIG. 6b, for the second grayscale, the compensation gate signal (GC) may have a second on time (OT2) longer than the first on time (OT1). The first on time (OT1) and the second on time (OT2) may represent the time during which the compensation gate signal (GC) maintains a minimum level.

[0125] In the above high-gradation, the first rising slew rate of the compensation gate signal (GC) may be smaller than the second rising slew rate of the compensation gate signal (GC) in the above high-gradation. Due to the relatively small rising slew rate, the high peak level (VP) of the voltage of the fourth node (N4) in the above high-gradation may be reduced.

[0126] According to the present embodiment, when the image displayed on the display panel (100) is a still image or when the display panel (100) operates in a continuous display mode, the driving frequency of the display panel (100) can be reduced to reduce the power consumption of the display device.

[0127] By setting the falling waveform and rising waveform of the compensation switching signal (GC) applied to the control electrodes of the first compensation switching element (T3-1) and the second compensation switching element (T3-2) asymmetrically, it is possible to prevent an increase in the voltage of the node (N4) between the first compensation switching element (T3-1) and the second compensation switching element (T3-2).

[0128] By preventing an increase in the voltage of the node (N4) between the first compensation switching element (T3-1) and the second compensation switching element (T3-2), current leakage of the first compensation switching element (T3-1) and the second compensation switching element (T3-2) during low-frequency driving is prevented, thereby preventing a decrease in brightness and flicker of the display panel (100) in low-frequency driving mode and improving display quality.

[0129] Figure 7 is a timing diagram showing an example of input signals and node voltages applied to the pixel of Figure 2.

[0130] Since the display device according to the present embodiment is substantially the same as the display device of FIGS. 1 to 3 except for the waveform of the compensation gate signal (GC), the same reference numbers are used for identical or similar components, and redundant descriptions are omitted.

[0131] Referring to FIG. 7, in this embodiment, the falling waveform of the compensation gate signal (GC) and the rising waveform of the compensation gate signal (GC) can be set asymmetrically. For example, the compensation gate signal (GC) can be fallen from a high level to a low level, rise from the low level to an intermediate high level, and rise from the intermediate high level to the high level.

[0132] In FIG. 7, in the rising step, the voltage is not raised directly from the low level to the high level, but rises in two stages by passing through an intermediate high level, so the high peak level (VP) of the voltage of the fourth node (N4) can be reduced.

[0133] According to the present embodiment, when the image displayed on the display panel (100) is a still image or when the display panel (100) operates in a continuous display mode, the driving frequency of the display panel (100) can be reduced to reduce the power consumption of the display device.

[0134] By setting the falling waveform and rising waveform of the compensation switching signal (GC) applied to the control electrodes of the first compensation switching element (T3-1) and the second compensation switching element (T3-2) asymmetrically, it is possible to prevent an increase in the voltage of the node (N4) between the first compensation switching element (T3-1) and the second compensation switching element (T3-2).

[0135] By preventing an increase in the voltage of the node (N4) between the first compensation switching element (T3-1) and the second compensation switching element (T3-2), current leakage of the first compensation switching element (T3-1) and the second compensation switching element (T3-2) during low-frequency driving is prevented, thereby preventing a decrease in brightness and flicker of the display panel (100) in low-frequency driving mode and improving display quality.

[0136] FIG. 8a is a timing diagram showing an example of input signals and node voltages applied to a pixel of FIG. 2 in a low-frequency driving mode. FIG. 8b is a timing diagram showing an example of input signals and node voltages applied to a pixel of FIG. 2 in a high-frequency driving mode.

[0137] Since the display device according to the present embodiment is substantially the same as the display device of FIGS. 1 to 3 except for the waveform of the compensation gate signal (GC), the same reference numbers are used for identical or similar components, and redundant descriptions are omitted.

[0138] In FIGS. 8a and 8b, the waveform setting of the compensation gate signal (GC) can be set differently in the low-frequency driving mode and the high-frequency driving mode.

[0139] When the driving frequency is lower than the reference frequency, the falling waveform of the compensation gate signal (GC) and the rising waveform of the compensation gate signal (GC) are set asymmetrically, and when the driving frequency is greater than or equal to the reference frequency, the falling waveform of the compensation gate signal (GC) and the rising waveform of the compensation gate signal (GC) can be set symmetrically. When the falling waveform of the compensation gate signal (GC) and the rising waveform of the compensation gate signal (GC) are set symmetrically, the absolute value of the falling slew rate of the compensation gate signal (GC) can be the same as the absolute value of the rising slew rate of the compensation gate signal (GC).

[0140] The waveform of the compensation gate signal (GC) when the driving frequency is smaller than the reference frequency is as shown in FIG. 3. That is, when the driving frequency is smaller than the reference frequency, the compensation gate signal (GC) may be polled from a high level to a low level, rise from the low level to an intermediate high level, and rise from the intermediate high level to a high level.

[0141] According to the present embodiment, when the image displayed on the display panel (100) is a still image or when the display panel (100) operates in a continuous display mode, the driving frequency of the display panel (100) can be reduced to reduce the power consumption of the display device.

[0142] By setting the falling waveform and rising waveform of the compensation switching signal (GC) applied to the control electrodes of the first compensation switching element (T3-1) and the second compensation switching element (T3-2) asymmetrically, it is possible to prevent an increase in the voltage of the node (N4) between the first compensation switching element (T3-1) and the second compensation switching element (T3-2).

[0143] By preventing an increase in the voltage of the node (N4) between the first compensation switching element (T3-1) and the second compensation switching element (T3-2), current leakage of the first compensation switching element (T3-1) and the second compensation switching element (T3-2) during low-frequency driving is prevented, thereby preventing a decrease in brightness and flicker of the display panel (100) in low-frequency driving mode and improving display quality.

[0144] FIG. 9a is a timing diagram showing an example of input signals and node voltages applied to a pixel of FIG. 2 in a low-frequency driving mode. FIG. 9b is a timing diagram showing an example of input signals and node voltages applied to a pixel of FIG. 2 in a high-frequency driving mode.

[0145] Since the display device according to the present embodiment is substantially the same as the display device of FIGS. 1, FIG. 2 and FIG. 4 except for the waveform of the compensation gate signal (GC), the same reference numbers are used for identical or similar components, and redundant descriptions are omitted.

[0146] In FIGS. 9a and 9b, the waveform setting of the compensation gate signal (GC) can be set differently in the low-frequency driving mode and the high-frequency driving mode.

[0147] When the driving frequency is lower than the reference frequency, the falling waveform of the compensation gate signal (GC) and the rising waveform of the compensation gate signal (GC) are set asymmetrically, and when the driving frequency is greater than or equal to the reference frequency, the falling waveform of the compensation gate signal (GC) and the rising waveform of the compensation gate signal (GC) can be set symmetrically. When the falling waveform of the compensation gate signal (GC) and the rising waveform of the compensation gate signal (GC) are set symmetrically, the absolute value of the falling slew rate of the compensation gate signal (GC) can be the same as the absolute value of the rising slew rate of the compensation gate signal (GC).

[0148] The waveform of the compensation gate signal (GC) when the driving frequency is smaller than the reference frequency is as shown in FIG. 4. That is, when the driving frequency is smaller than the reference frequency, the compensation gate signal (GC) may fall from a high level to a low level and rise from the low level to the high level. When the driving frequency is smaller than the reference frequency and the compensation gate signal (GC) rises from the low level to the high level, it may have a first rising slew rate and a second rising slew rate smaller than the first rising slew rate in sequence.

[0149] According to the present embodiment, when the image displayed on the display panel (100) is a still image or when the display panel (100) operates in a continuous display mode, the driving frequency of the display panel (100) can be reduced to reduce the power consumption of the display device.

[0150] By setting the falling waveform and rising waveform of the compensation switching signal (GC) applied to the control electrodes of the first compensation switching element (T3-1) and the second compensation switching element (T3-2) asymmetrically, it is possible to prevent an increase in the voltage of the node (N4) between the first compensation switching element (T3-1) and the second compensation switching element (T3-2).

[0151] By preventing an increase in the voltage of the node (N4) between the first compensation switching element (T3-1) and the second compensation switching element (T3-2), current leakage of the first compensation switching element (T3-1) and the second compensation switching element (T3-2) during low-frequency driving is prevented, thereby preventing a decrease in brightness and flicker of the display panel (100) in low-frequency driving mode and improving display quality.

[0152] FIG. 10a is a timing diagram showing an example of input signals and node voltages applied to a pixel of FIG. 2 in a low-frequency driving mode. FIG. 10b is a timing diagram showing an example of input signals and node voltages applied to a pixel of FIG. 2 in a high-frequency driving mode.

[0153] Since the display device according to the present embodiment is substantially the same as the display device of FIGS. 1, FIG. 2 and FIG. 5 except for the waveform of the compensation gate signal (GC), the same reference numbers are used for identical or similar components, and redundant descriptions are omitted.

[0154] In FIG. 10a and FIG. 10b, the waveform setting of the compensation gate signal (GC) can be set differently in the low-frequency driving mode and the high-frequency driving mode.

[0155] When the driving frequency is lower than the reference frequency, the falling waveform of the compensation gate signal (GC) and the rising waveform of the compensation gate signal (GC) are set asymmetrically, and when the driving frequency is greater than or equal to the reference frequency, the falling waveform of the compensation gate signal (GC) and the rising waveform of the compensation gate signal (GC) can be set symmetrically. When the falling waveform of the compensation gate signal (GC) and the rising waveform of the compensation gate signal (GC) are set symmetrically, the absolute value of the falling slew rate of the compensation gate signal (GC) can be the same as the absolute value of the rising slew rate of the compensation gate signal (GC).

[0156] The waveform of the compensation gate signal (GC) when the driving frequency is smaller than the reference frequency is as shown in FIG. 5. That is, when the driving frequency is smaller than the reference frequency, the compensation gate signal (GC) may fall from a high level to a low level and rise from the low level to the high level. When the driving frequency is smaller than the reference frequency, the rising slew rate of the compensation gate signal (GC) may be smaller than the falling slew rate of the compensation gate signal (GC).

[0157] According to the present embodiment, when the image displayed on the display panel (100) is a still image or when the display panel (100) operates in a continuous display mode, the driving frequency of the display panel (100) can be reduced to reduce the power consumption of the display device.

[0158] By setting the falling waveform and rising waveform of the compensation switching signal (GC) applied to the control electrodes of the first compensation switching element (T3-1) and the second compensation switching element (T3-2) asymmetrically, it is possible to prevent an increase in the voltage of the node (N4) between the first compensation switching element (T3-1) and the second compensation switching element (T3-2).

[0159] By preventing an increase in the voltage of the node (N4) between the first compensation switching element (T3-1) and the second compensation switching element (T3-2), current leakage of the first compensation switching element (T3-1) and the second compensation switching element (T3-2) during low-frequency driving is prevented, thereby preventing a decrease in brightness and flicker of the display panel (100) in low-frequency driving mode and improving display quality.

[0160] FIG. 11a is a timing diagram showing an example of input signals and node voltages applied to a pixel of FIG. 2 in a low-frequency driving mode and high grayscale. FIG. 11b is a timing diagram showing an example of input signals and node voltages applied to a pixel of FIG. 2 in a low-frequency driving mode and low grayscale. FIG. 11c is a timing diagram showing an example of input signals and node voltages applied to a pixel of FIG. 2 in a high-frequency driving mode.

[0161] Since the display device according to the present embodiment is substantially the same as the display device of FIG. 1, FIG. 2, FIG. 6a, and FIG. 6b except for the waveform of the compensation gate signal (GC), the same reference numbers are used for identical or similar components, and redundant descriptions are omitted.

[0162] In FIGS. 11a, 11b, and 11c, the waveform setting of the compensation gate signal (GC) can be set differently in the low-frequency driving mode and the high-frequency driving mode.

[0163] When the driving frequency is lower than the reference frequency, the falling waveform of the compensation gate signal (GC) and the rising waveform of the compensation gate signal (GC) are set asymmetrically, and when the driving frequency is greater than or equal to the reference frequency, the falling waveform of the compensation gate signal (GC) and the rising waveform of the compensation gate signal (GC) can be set symmetrically. When the falling waveform of the compensation gate signal (GC) and the rising waveform of the compensation gate signal (GC) are set symmetrically, the absolute value of the falling slew rate of the compensation gate signal (GC) can be the same as the absolute value of the rising slew rate of the compensation gate signal (GC).

[0164] The waveform of the compensation gate signal (GC) when the driving frequency is smaller than the reference frequency is as illustrated in FIGS. 6a and 6b. That is, when the driving frequency is smaller than the reference frequency, the compensation gate signal (GC) has a first rising slew rate for a first grayscale that is greater than or equal to the reference grayscale, and when the driving frequency is smaller than the reference frequency, the compensation gate signal (GC) may have a second rising slew rate greater than the first rising slew rate for a second grayscale that is smaller than the reference grayscale.

[0165] According to the present embodiment, when the image displayed on the display panel (100) is a still image or when the display panel (100) operates in a continuous display mode, the driving frequency of the display panel (100) can be reduced to reduce the power consumption of the display device.

[0166] By setting the falling waveform and rising waveform of the compensation switching signal (GC) applied to the control electrodes of the first compensation switching element (T3-1) and the second compensation switching element (T3-2) asymmetrically, it is possible to prevent an increase in the voltage of the node (N4) between the first compensation switching element (T3-1) and the second compensation switching element (T3-2).

[0167] By preventing an increase in the voltage of the node (N4) between the first compensation switching element (T3-1) and the second compensation switching element (T3-2), current leakage of the first compensation switching element (T3-1) and the second compensation switching element (T3-2) during low-frequency driving is prevented, thereby preventing a decrease in brightness and flicker of the display panel (100) in low-frequency driving mode and improving display quality.

[0168] FIG. 12a is a timing diagram showing an example of input signals and node voltages applied to a pixel of FIG. 2 in a low-frequency driving mode. FIG. 12b is a timing diagram showing an example of input signals and node voltages applied to a pixel of FIG. 2 in a high-frequency driving mode.

[0169] Since the display device according to the present embodiment is substantially the same as the display device of FIGS. 1, FIG. 2 and FIG. 7 except for the waveform of the compensation gate signal (GC), the same reference numbers are used for identical or similar components, and redundant descriptions are omitted.

[0170] In FIG. 10a and FIG. 10b, the waveform setting of the compensation gate signal (GC) can be set differently in the low-frequency driving mode and the high-frequency driving mode.

[0171] When the driving frequency is lower than the reference frequency, the falling waveform of the compensation gate signal (GC) and the rising waveform of the compensation gate signal (GC) are set asymmetrically, and when the driving frequency is greater than or equal to the reference frequency, the falling waveform of the compensation gate signal (GC) and the rising waveform of the compensation gate signal (GC) can be set symmetrically. When the falling waveform of the compensation gate signal (GC) and the rising waveform of the compensation gate signal (GC) are set symmetrically, the absolute value of the falling slew rate of the compensation gate signal (GC) can be the same as the absolute value of the rising slew rate of the compensation gate signal (GC).

[0172] The waveform of the compensation gate signal (GC) when the driving frequency is smaller than the reference frequency is as shown in FIG. 7. That is, when the driving frequency is smaller than the reference frequency, the compensation gate signal (GC) may be polled from a high level to a low level, rise from the low level to an intermediate high level, and rise from the intermediate high level to a high level.

[0173] According to the present embodiment, when the image displayed on the display panel (100) is a still image or when the display panel (100) operates in a continuous display mode, the driving frequency of the display panel (100) can be reduced to reduce the power consumption of the display device.

[0174] By setting the falling waveform and rising waveform of the compensation switching signal (GC) applied to the control electrodes of the first compensation switching element (T3-1) and the second compensation switching element (T3-2) asymmetrically, it is possible to prevent an increase in the voltage of the node (N4) between the first compensation switching element (T3-1) and the second compensation switching element (T3-2).

[0175] By preventing an increase in the voltage of the node (N4) between the first compensation switching element (T3-1) and the second compensation switching element (T3-2), current leakage of the first compensation switching element (T3-1) and the second compensation switching element (T3-2) during low-frequency driving is prevented, thereby preventing a decrease in brightness and flicker of the display panel (100) in low-frequency driving mode and improving display quality.

[0176] FIG. 13 is a circuit diagram showing a pixel of a display panel of a display device according to one embodiment of the present invention.

[0177] Since the display device according to the present embodiment is substantially the same as the display device of FIGS. 1 to 3 except for the structure of the pixel, the same reference numbers are used for identical or similar components, and redundant descriptions are omitted. The pixel of FIG. 13 is identical to the pixel of FIG. 2 except that a first initialization voltage (VINT), rather than a second initialization voltage, is applied to the input electrode of the seventh pixel switching element (T7).

[0178] Referring to FIGS. 1, FIGS. 3 and FIGS. 13, the display panel (100) includes a plurality of pixels, and each of the pixels includes a light-emitting element (EE).

[0179] The pixels receive a data write gate signal (GW), a compensation gate signal (GC), a data initialization gate signal (GI), a light-emitting element initialization gate signal (EB), the data voltage (VDATA), and the emission signal (EM), and emit light from the light-emitting element (EE) according to the level of the data voltage (VDATA) to display the image.

[0180] The pixel may include a light-emitting element (EE), a driving switching element (T1) that applies a driving current to the light-emitting element (EE), and a first compensation switching element (T3-1) and a second compensation switching element (T3-2) that are disposed between the control electrode and the output electrode of the driving switching element (T1) and are connected in series with each other.

[0181] Specifically, the pixel of the display device comprises: a first pixel switching element (T1) including a control electrode connected to a first node (N1), an input electrode connected to a second node (N2), and an output electrode connected to a third node (N3); a second pixel switching element (T2) including a control electrode to which a data write gate signal (GW) is applied, an input electrode to which a data voltage (VDATA) is applied, and an output electrode connected to the second node (N2); a third-1 pixel switching element (T3-1) including a control electrode to which a compensation gate signal (GC) is applied, an input electrode connected to the first node (N1), and an output electrode connected to a fourth node (N4); a third-2 pixel switching element (T3-2) including a control electrode to which the compensation gate signal (GC) is applied, an input electrode connected to the fourth node (N4), and an output electrode connected to the third node (N3); a control electrode to which a data initialization gate signal (GI) is applied, an input electrode connected to a fifth node (N5), and an input electrode connected to the first node (N1). A fourth-1 pixel switching element (T4-1) including an output electrode, a fourth-2 pixel switching element (T4-2) including a control electrode to which the data initialization gate signal (GI) is applied, an input electrode to which the first initialization voltage (VINT) is applied, and an output electrode connected to the fifth node (N5), a fifth pixel switching element (T5) including a control electrode to which an emission signal is applied, an input electrode to which the first power supply voltage is applied, and an output electrode connected to the second node (N2), a sixth pixel switching element (T6) including a control electrode to which the emission signal is applied, an input electrode connected to the third node (N3), and an output electrode connected to the anode electrode of the light-emitting element, a control electrode to which the light-emitting element initialization gate signal (EB) is applied, an input electrode to which the first initialization voltage (VINT) is applied, and an output electrode connected to the anode electrode of the light-emitting element,The device may include an eighth pixel switching element (T8) comprising a control electrode to which the light-emitting element initialization gate signal (EB) is applied, an input electrode to which a bias voltage (VBIAS) is applied, and an output electrode connected to the second node (N2); a storage capacitor comprising a first electrode to which the first power supply voltage is applied and a second electrode connected to the first node (N1); and the light-emitting element comprising the anode electrode and the cathode electrode to which the second power supply voltage is applied.

[0182] The driving switching element is the first pixel switching element (T1), the first compensation switching element is the third-1 pixel switching element (T3-1), and the second compensation switching element may be the third-2 pixel switching element (T3-2).

[0183] In addition to the waveform of FIG. 3, the waveforms of FIG. 4, FIG. 5, FIG. 6a, FIG. 6b, FIG. 7, FIG. 8a, FIG. 8b, FIG. 9a, FIG. 9b, FIG. 10a, FIG. 10b, FIG. 11a, FIG. 11b, FIG. 11c, FIG. 12a, and FIG. 12b can each be applied to the circuit diagram of the pixel of the present embodiment.

[0184] According to the present embodiment, when the image displayed on the display panel (100) is a still image or when the display panel (100) operates in a continuous display mode, the driving frequency of the display panel (100) can be reduced to reduce the power consumption of the display device.

[0185] By setting the falling waveform and rising waveform of the compensation switching signal (GC) applied to the control electrodes of the first compensation switching element (T3-1) and the second compensation switching element (T3-2) asymmetrically, it is possible to prevent an increase in the voltage of the node (N4) between the first compensation switching element (T3-1) and the second compensation switching element (T3-2).

[0186] By preventing an increase in the voltage of the node (N4) between the first compensation switching element (T3-1) and the second compensation switching element (T3-2), current leakage of the first compensation switching element (T3-1) and the second compensation switching element (T3-2) during low-frequency driving is prevented, thereby preventing a decrease in brightness and flicker of the display panel (100) in low-frequency driving mode and improving display quality.

[0187] FIG. 14 is a circuit diagram showing a pixel of a display panel of a display device according to one embodiment of the present invention.

[0188] Since the display device according to the present embodiment is substantially the same as the display device of FIGS. 1 to 3 except for the structure of the pixel, the same reference numerals are used for identical or similar components, and redundant descriptions are omitted. The pixel of FIG. 14 is identical to the pixel of FIG. 2 except that it does not include an eighth pixel switching element (T8).

[0189] Referring to FIGS. 1, FIGS. 3 and FIGS. 14, the display panel (100) includes a plurality of pixels, and each of the pixels includes a light-emitting element (EE).

[0190] The pixels receive a data write gate signal (GW), a compensation gate signal (GC), a data initialization gate signal (GI), a light-emitting element initialization gate signal (GB), the data voltage (VDATA), and the emission signal (EM), and display the image by emitting light from the light-emitting element (EE) according to the level of the data voltage (VDATA).

[0191] The pixel may include a light-emitting element (EE), a driving switching element (T1) that applies a driving current to the light-emitting element (EE), and a first compensation switching element (T3-1) and a second compensation switching element (T3-2) that are disposed between the control electrode and the output electrode of the driving switching element (T1) and are connected in series with each other.

[0192] Specifically, the pixel of the display device comprises: a first pixel switching element (T1) including a control electrode connected to a first node (N1), an input electrode connected to a second node (N2), and an output electrode connected to a third node (N3); a second pixel switching element (T2) including a control electrode to which a data write gate signal (GW) is applied, an input electrode to which a data voltage (VDATA) is applied, and an output electrode connected to the second node (N2); a third-1 pixel switching element (T3-1) including a control electrode to which a compensation gate signal (GC) is applied, an input electrode connected to the first node (N1), and an output electrode connected to a fourth node (N4); a third-2 pixel switching element (T3-2) including a control electrode to which the compensation gate signal (GC) is applied, an input electrode connected to the fourth node (N4), and an output electrode connected to the third node (N3); a control electrode to which a data initialization gate signal (GI) is applied, an input electrode connected to a fifth node (N5), and an input electrode connected to the first node (N1). A fourth-1 pixel switching element (T4-1) including an output electrode, a fourth-2 pixel switching element (T4-2) including a control electrode to which the data initialization gate signal (GI) is applied, an input electrode to which the first initialization voltage (VINT) is applied, and an output electrode connected to the fifth node (N5), a fifth pixel switching element (T5) including a control electrode to which an emission signal is applied, an input electrode to which the first power supply voltage is applied, and an output electrode connected to the second node (N2), a sixth pixel switching element (T6) including a control electrode to which the emission signal is applied, an input electrode connected to the third node (N3), and an output electrode connected to the anode electrode of the light-emitting element, a control electrode to which the light-emitting element initialization gate signal (GB) is applied, an input electrode to which the second initialization voltage (VAINT) is applied, and an output electrode connected to the anode electrode of the light-emitting element,It may include a storage capacitor comprising a first electrode to which the first power supply voltage is applied and a second electrode connected to the first node (N1), and a light-emitting element comprising the anode electrode and a cathode electrode to which the second power supply voltage is applied.

[0193] The driving switching element is the first pixel switching element (T1), the first compensation switching element is the third-1 pixel switching element (T3-1), and the second compensation switching element may be the third-2 pixel switching element (T3-2).

[0194] In addition to the waveform of FIG. 3, the waveforms of FIG. 4, FIG. 5, FIG. 6a, FIG. 6b, FIG. 7, FIG. 8a, FIG. 8b, FIG. 9a, FIG. 9b, FIG. 10a, FIG. 10b, FIG. 11a, FIG. 11b, FIG. 11c, FIG. 12a, and FIG. 12b can each be applied to the circuit diagram of the pixel of the present embodiment.

[0195] According to the present embodiment, when the image displayed on the display panel (100) is a still image or when the display panel (100) operates in a continuous display mode, the driving frequency of the display panel (100) can be reduced to reduce the power consumption of the display device.

[0196] By setting the falling waveform and rising waveform of the compensation switching signal (GC) applied to the control electrodes of the first compensation switching element (T3-1) and the second compensation switching element (T3-2) asymmetrically, it is possible to prevent an increase in the voltage of the node (N4) between the first compensation switching element (T3-1) and the second compensation switching element (T3-2).

[0197] By preventing an increase in the voltage of the node (N4) between the first compensation switching element (T3-1) and the second compensation switching element (T3-2), current leakage of the first compensation switching element (T3-1) and the second compensation switching element (T3-2) during low-frequency driving is prevented, thereby preventing a decrease in brightness and flicker of the display panel (100) in low-frequency driving mode and improving display quality.

[0198] FIG. 15 is a circuit diagram showing a pixel of a display panel of a display device according to one embodiment of the present invention.

[0199] Since the display device according to the present embodiment is substantially the same as the display device of FIGS. 1 to 3 except for the structure of the pixel, the same reference numbers are used for identical or similar components, and redundant descriptions are omitted. The pixel of FIG. 15 is identical to the pixel of FIG. 2 except that it does not include an eighth pixel switching element (T8) and a first initialization voltage (VINT) rather than a second initialization voltage is applied to the input electrode of the seventh pixel switching element (T7).

[0200] Referring to FIGS. 1, FIGS. 3 and FIGS. 15, the display panel (100) includes a plurality of pixels, and each of the pixels includes a light-emitting element (EE).

[0201] The pixels receive a data write gate signal (GW), a compensation gate signal (GC), a data initialization gate signal (GI), a light-emitting element initialization gate signal (GB), the data voltage (VDATA), and the emission signal (EM), and display the image by emitting light from the light-emitting element (EE) according to the level of the data voltage (VDATA).

[0202] The pixel may include a light-emitting element (EE), a driving switching element (T1) that applies a driving current to the light-emitting element (EE), and a first compensation switching element (T3-1) and a second compensation switching element (T3-2) that are disposed between the control electrode and the output electrode of the driving switching element (T1) and are connected in series with each other.

[0203] Specifically, the pixel of the display device comprises: a first pixel switching element (T1) including a control electrode connected to a first node (N1), an input electrode connected to a second node (N2), and an output electrode connected to a third node (N3); a second pixel switching element (T2) including a control electrode to which a data write gate signal (GW) is applied, an input electrode to which a data voltage (VDATA) is applied, and an output electrode connected to the second node (N2); a third-1 pixel switching element (T3-1) including a control electrode to which a compensation gate signal (GC) is applied, an input electrode connected to the first node (N1), and an output electrode connected to a fourth node (N4); a third-2 pixel switching element (T3-2) including a control electrode to which the compensation gate signal (GC) is applied, an input electrode connected to the fourth node (N4), and an output electrode connected to the third node (N3); a control electrode to which a data initialization gate signal (GI) is applied, an input electrode connected to a fifth node (N5), and an input electrode connected to the first node (N1). A fourth-1 pixel switching element (T4-1) including an output electrode, a fourth-2 pixel switching element (T4-2) including a control electrode to which the data initialization gate signal (GI) is applied, an input electrode to which the first initialization voltage (VINT) is applied, and an output electrode connected to the fifth node (N5), a fifth pixel switching element (T5) including a control electrode to which an emission signal is applied, an input electrode to which the first power supply voltage is applied, and an output electrode connected to the second node (N2), a sixth pixel switching element (T6) including a control electrode to which the emission signal is applied, an input electrode connected to the third node (N3), and an output electrode connected to the anode electrode of the light-emitting element, a seventh pixel switching element (T7) including a control electrode to which the light-emitting element initialization gate signal (GB) is applied, an input electrode to which the first initialization voltage (VINT) is applied, and an output electrode connected to the anode electrode of the light-emitting element,It may include a storage capacitor comprising a first electrode to which the first power supply voltage is applied and a second electrode connected to the first node (N1), and a light-emitting element comprising the anode electrode and a cathode electrode to which the second power supply voltage is applied.

[0204] The driving switching element is the first pixel switching element, the first compensation switching element is the third-1 pixel switching element, and the second compensation switching element may be the third-2 pixel switching element.

[0205] In addition to the waveform of FIG. 3, the waveforms of FIG. 4, FIG. 5, FIG. 6a, FIG. 6b, FIG. 7, FIG. 8a, FIG. 8b, FIG. 9a, FIG. 9b, FIG. 10a, FIG. 10b, FIG. 11a, FIG. 11b, FIG. 11c, FIG. 12a, and FIG. 12b can each be applied to the circuit diagram of the pixel of the present embodiment.

[0206] According to the present embodiment, when the image displayed on the display panel (100) is a still image or when the display panel (100) operates in a continuous display mode, the driving frequency of the display panel (100) can be reduced to reduce the power consumption of the display device.

[0207] By setting the falling waveform and rising waveform of the compensation switching signal (GC) applied to the control electrodes of the first compensation switching element (T3-1) and the second compensation switching element (T3-2) asymmetrically, it is possible to prevent an increase in the voltage of the node (N4) between the first compensation switching element (T3-1) and the second compensation switching element (T3-2).

[0208] By preventing an increase in the voltage of the node (N4) between the first compensation switching element (T3-1) and the second compensation switching element (T3-2), current leakage of the first compensation switching element (T3-1) and the second compensation switching element (T3-2) during low-frequency driving is prevented, thereby preventing a decrease in brightness and flicker of the display panel (100) in low-frequency driving mode and improving display quality. Industrial applicability

[0209] According to the display device of the present invention described above, the display quality of the display panel can be improved while reducing the power consumption of the display device.

[0210] Although the invention has been described with reference to the above embodiments, those skilled in the art will understand that various modifications and changes can be made to the invention without departing from the spirit and scope of the invention as described in the following claims. Explanation of the symbols

[0211] 100: Display panel 200: Drive control unit 300: Gate driver 400: Gamma reference voltage generator 500: Data driver 600: Emission driver

Claims

Claim 1 A display device comprising: a light-emitting element; a driving switching element that applies a driving current to the light-emitting element; and a first compensation switching element and a second compensation switching element that are disposed between the control electrode and the output electrode of the driving switching element and are connected in series with each other, wherein a compensation gate signal is applied to the control electrode of the first compensation switching element and the control electrode of the second compensation switching element, and the falling waveform of the compensation gate signal and the rising waveform of the compensation gate signal are set asymmetrically, wherein the compensation gate signal is fallen from a high level to a low level, rises from the low level to an intermediate high level, rises from the intermediate high level to a high level, and the compensation gate signal rises from the low level to the intermediate high level and is maintained for the first half of the light-emitting section, and rises from the intermediate high level to a high level and is maintained for the second half of the light-emitting section. Claim 2 delete Claim 3 delete Claim 4 A display device comprising: a light-emitting element; a driving switching element that applies a driving current to the light-emitting element; and a first compensation switching element and a second compensation switching element that are disposed between the control electrode and the output electrode of the driving switching element and are connected in series with each other, wherein a compensation gate signal is applied to the control electrode of the first compensation switching element and the control electrode of the second compensation switching element, and the falling waveform of the compensation gate signal and the rising waveform of the compensation gate signal are set asymmetrically, wherein the compensation gate signal falls from a high level to a low level and rises from the low level to the high level, and when the compensation gate signal rises from the low level to the high level, a first rising slew rate and a second rising slew rate smaller than the first rising slew rate are successively provided. Claim 5 A display device comprising: a light-emitting element; a driving switching element that applies a driving current to the light-emitting element; and a first compensation switching element and a second compensation switching element that are disposed between the control electrode and the output electrode of the driving switching element and are connected in series with each other, wherein a compensation gate signal is applied to the control electrode of the first compensation switching element and the control electrode of the second compensation switching element, and the falling waveform of the compensation gate signal and the rising waveform of the compensation gate signal are set asymmetrically, the compensation gate signal falls from a high level to a low level and rises from the low level to the high level, and the rising slew rate of the compensation gate signal is smaller than the falling slew rate of the compensation gate signal. Claim 6 A display device comprising: a light-emitting element; a driving switching element that applies a driving current to the light-emitting element; and a first compensation switching element and a second compensation switching element that are disposed between the control electrode and the output electrode of the driving switching element and are connected in series with each other, wherein a compensation gate signal is applied to the control electrode of the first compensation switching element and the control electrode of the second compensation switching element, and the falling waveform of the compensation gate signal and the rising waveform of the compensation gate signal are set asymmetrically, wherein for a first grayscale greater than or equal to a reference grayscale, the compensation gate signal has a first rising slew rate, and for a second grayscale smaller than the reference grayscale, the compensation gate signal has a second rising slew rate greater than the first rising slew rate. Claim 7 A display device according to claim 6, characterized in that for the first grayscale, the compensation gate signal has a first on time, and for the second grayscale, the compensation gate signal has a second on time longer than the first on time. Claim 8 A display device according to claim 1, further comprising a data writing switching element including a control electrode to which a data writing gate signal is applied, an input electrode to which a data voltage is applied, and an output electrode connected to the input electrode of the driving switching element. Claim 9 A display device according to claim 8, characterized in that when the data entry gate signal is polled, the compensation gate signal is polled. Claim 10 A display device according to claim 9, further comprising a first initialization switching element and a second initialization switching element connected in series with each other, disposed between the control electrode of the driving switching element and the application node of the initialization voltage. Claim 11 A light-emitting element; a driving switching element that applies a driving current to the light-emitting element; A display device comprising a first compensation switching element and a second compensation switching element connected in series, disposed between a control electrode and an output electrode of the driving switching element, wherein a compensation gate signal is applied to the control electrode of the first compensation switching element and the control electrode of the second compensation switching element, and the falling waveform of the compensation gate signal and the rising waveform of the compensation gate signal are set asymmetrically, and further comprising a data writing switching element including a control electrode to which a data writing gate signal is applied, an input electrode to which a data voltage is applied, and an output electrode connected to the input electrode of the driving switching element, wherein when the data writing gate signal is poured, the compensation gate signal is poured, and further comprising a first initialization switching element and a second initialization switching element connected in series, disposed between the control electrode of the driving switching element and an application node of an initialization voltage, wherein a data initialization gate signal is applied to the control electrode of the first initialization switching element and the control electrode of the second initialization switching element, and when the data initialization gate signal is rising, the compensation gate signal is poured. Claim 12 A light-emitting element; a driving switching element that applies a driving current to the light-emitting element; and includes a first compensation switching element and a second compensation switching element disposed between the control electrode and the output electrode of the driving switching element and connected in series with each other, wherein a compensation gate signal is applied to the control electrode of the first compensation switching element and the control electrode of the second compensation switching element, and the falling waveform of the compensation gate signal and the rising waveform of the compensation gate signal are set asymmetrically, and the pixel of the display device includes a first pixel switching element comprising a control electrode connected to a first node, an input electrode connected to a second node, and an output electrode connected to a third node; a second pixel switching element comprising a control electrode to which a data write gate signal is applied, an input electrode to which a data voltage is applied, and an output electrode connected to the second node; a third-1 pixel switching element comprising a control electrode to which a compensation gate signal is applied, an input electrode connected to the first node, and an output electrode connected to the fourth node; a third-2 pixel switching element comprising a control electrode to which the compensation gate signal is applied, an input electrode connected to the fourth node, and an output electrode connected to the third node; a control electrode to which a data initialization gate signal is applied, and a fifth A 4-1 pixel switching element comprising an input electrode connected to a node and an output electrode connected to the first node; a 4-2 pixel switching element comprising a control electrode to which the data initialization gate signal is applied, an input electrode to which the first initialization voltage is applied, and an output electrode connected to the fifth node; a fifth pixel switching element comprising a control electrode to which an emission signal is applied, an input electrode to which the first power supply voltage is applied, and an output electrode connected to the second node; and a sixth pixel switching element comprising a control electrode to which the emission signal is applied, an input electrode connected to the third node, and an output electrode connected to the anode electrode of the light-emitting element.A display device comprising: a seventh pixel switching element including a control electrode to which a light-emitting element initialization gate signal is applied, an input electrode to which a second initialization voltage is applied, and an output electrode connected to the anode electrode of the light-emitting element; an eighth pixel switching element including a control electrode to which the light-emitting element initialization gate signal is applied, an input electrode to which a bias voltage is applied, and an output electrode connected to the second node; a storage capacitor including a first electrode to which the first power supply voltage is applied and a second electrode connected to the first node; and the light-emitting element including the anode electrode and the cathode electrode to which the second power supply voltage is applied, wherein the driving switching element is the first pixel switching element, the first compensation switching element is the third-1 pixel switching element, and the second compensation switching element is the third-2 pixel switching element. Claim 13 A light-emitting element; a driving switching element that applies a driving current to the light-emitting element; and includes a first compensation switching element and a second compensation switching element disposed between the control electrode and the output electrode of the driving switching element and connected in series with each other, wherein a compensation gate signal is applied to the control electrode of the first compensation switching element and the control electrode of the second compensation switching element, and the falling waveform of the compensation gate signal and the rising waveform of the compensation gate signal are set asymmetrically, and the pixel of the display device includes a first pixel switching element comprising a control electrode connected to a first node, an input electrode connected to a second node, and an output electrode connected to a third node; a second pixel switching element comprising a control electrode to which a data write gate signal is applied, an input electrode to which a data voltage is applied, and an output electrode connected to the second node; a third-1 pixel switching element comprising a control electrode to which a compensation gate signal is applied, an input electrode connected to the first node, and an output electrode connected to the fourth node; a third-2 pixel switching element comprising a control electrode to which the compensation gate signal is applied, an input electrode connected to the fourth node, and an output electrode connected to the third node; a control electrode to which a data initialization gate signal is applied, and a fifth A 4-1 pixel switching element comprising an input electrode connected to a node and an output electrode connected to the first node; a 4-2 pixel switching element comprising a control electrode to which the data initialization gate signal is applied, an input electrode to which the first initialization voltage is applied, and an output electrode connected to the fifth node; a fifth pixel switching element comprising a control electrode to which an emission signal is applied, an input electrode to which the first power supply voltage is applied, and an output electrode connected to the second node; and a sixth pixel switching element comprising a control electrode to which the emission signal is applied, an input electrode connected to the third node, and an output electrode connected to the anode electrode of the light-emitting element.A display device comprising: a seventh pixel switching element including a control electrode to which a light-emitting element initialization gate signal is applied, an input electrode to which a first initialization voltage is applied, and an output electrode connected to the anode electrode of the light-emitting element; an eighth pixel switching element including a control electrode to which a light-emitting element initialization gate signal is applied, an input electrode to which a bias voltage is applied, and an output electrode connected to the second node; a storage capacitor including a first electrode to which the first power supply voltage is applied and a second electrode connected to the first node; and the light-emitting element including the anode electrode and a cathode electrode to which the second power supply voltage is applied, wherein the driving switching element is the first pixel switching element, the first compensation switching element is the third-1 pixel switching element, and the second compensation switching element is the third-2 pixel switching element. Claim 14 A light-emitting element; a driving switching element that applies a driving current to the light-emitting element; and includes a first compensation switching element and a second compensation switching element disposed between the control electrode and the output electrode of the driving switching element and connected in series with each other, wherein a compensation gate signal is applied to the control electrode of the first compensation switching element and the control electrode of the second compensation switching element, and the falling waveform of the compensation gate signal and the rising waveform of the compensation gate signal are set asymmetrically, and the pixel of the display device includes a first pixel switching element comprising a control electrode connected to a first node, an input electrode connected to a second node, and an output electrode connected to a third node; a second pixel switching element comprising a control electrode to which a data write gate signal is applied, an input electrode to which a data voltage is applied, and an output electrode connected to the second node; a third-1 pixel switching element comprising a control electrode to which a compensation gate signal is applied, an input electrode connected to the first node, and an output electrode connected to the fourth node; a third-2 pixel switching element comprising a control electrode to which the compensation gate signal is applied, an input electrode connected to the fourth node, and an output electrode connected to the third node; a control electrode to which a data initialization gate signal is applied, and a fifth A 4-1 pixel switching element comprising an input electrode connected to a node and an output electrode connected to the first node; a 4-2 pixel switching element comprising a control electrode to which the data initialization gate signal is applied, an input electrode to which the first initialization voltage is applied, and an output electrode connected to the fifth node; a fifth pixel switching element comprising a control electrode to which an emission signal is applied, an input electrode to which the first power supply voltage is applied, and an output electrode connected to the second node; and a sixth pixel switching element comprising a control electrode to which the emission signal is applied, an input electrode connected to the third node, and an output electrode connected to the anode electrode of the light-emitting element.A display device comprising: a seventh pixel switching element including a control electrode to which a light-emitting element initialization gate signal is applied, an input electrode to which a second initialization voltage is applied, and an output electrode connected to the anode electrode of the light-emitting element; a storage capacitor including a first electrode to which the first power supply voltage is applied and a second electrode connected to the first node; and the light-emitting element including the anode electrode and the cathode electrode to which the second power supply voltage is applied, wherein the driving switching element is the first pixel switching element, the first compensation switching element is the third-1 pixel switching element, and the second compensation switching element is the third-2 pixel switching element. Claim 15 A light-emitting element; a driving switching element that applies a driving current to the light-emitting element; and includes a first compensation switching element and a second compensation switching element disposed between the control electrode and the output electrode of the driving switching element and connected in series with each other, wherein a compensation gate signal is applied to the control electrode of the first compensation switching element and the control electrode of the second compensation switching element, and the falling waveform of the compensation gate signal and the rising waveform of the compensation gate signal are set asymmetrically, and the pixel of the display device includes a first pixel switching element comprising a control electrode connected to a first node, an input electrode connected to a second node, and an output electrode connected to a third node; a second pixel switching element comprising a control electrode to which a data write gate signal is applied, an input electrode to which a data voltage is applied, and an output electrode connected to the second node; a third-1 pixel switching element comprising a control electrode to which a compensation gate signal is applied, an input electrode connected to the first node, and an output electrode connected to the fourth node; a third-2 pixel switching element comprising a control electrode to which the compensation gate signal is applied, an input electrode connected to the fourth node, and an output electrode connected to the third node; a control electrode to which a data initialization gate signal is applied, and a fifth A 4-1 pixel switching element comprising an input electrode connected to a node and an output electrode connected to the first node; a 4-2 pixel switching element comprising a control electrode to which the data initialization gate signal is applied, an input electrode to which the first initialization voltage is applied, and an output electrode connected to the fifth node; a fifth pixel switching element comprising a control electrode to which an emission signal is applied, an input electrode to which the first power supply voltage is applied, and an output electrode connected to the second node; and a sixth pixel switching element comprising a control electrode to which the emission signal is applied, an input electrode connected to the third node, and an output electrode connected to the anode electrode of the light-emitting element.A display device comprising: a seventh pixel switching element including a control electrode to which a light-emitting element initialization gate signal is applied, an input electrode to which a first initialization voltage is applied, and an output electrode connected to the anode electrode of the light-emitting element; a storage capacitor including a first electrode to which the first power supply voltage is applied and a second electrode connected to the first node; and the light-emitting element including the anode electrode and a cathode electrode to which a second power supply voltage is applied, wherein the driving switching element is the first pixel switching element, the first compensation switching element is the third-1 pixel switching element, and the second compensation switching element is the third-2 pixel switching element. Claim 16 A display device comprising: a light-emitting element; a driving switching element that applies a driving current to the light-emitting element; and a first compensation switching element and a second compensation switching element that are disposed between the control electrode and the output electrode of the driving switching element and are connected in series with each other, wherein a compensation gate signal is applied to the control electrode of the first compensation switching element and the control electrode of the second compensation switching element, and when the driving frequency is smaller than a reference frequency, the falling waveform of the compensation gate signal and the rising waveform of the compensation gate signal are set asymmetrically, and when the driving frequency is greater than or equal to the reference frequency, the falling waveform of the compensation gate signal and the rising waveform of the compensation gate signal are set symmetrically. Claim 17 A display device according to claim 16, characterized in that when the driving frequency is smaller than the reference frequency, the compensation gate signal is polled from a high level to a low level, rises from the low level to an intermediate high level, and rises from the intermediate high level to the high level. Claim 18 A display device according to claim 16, characterized in that when the driving frequency is smaller than the reference frequency, the compensation gate signal is polled from a high level to a low level and rises from the low level to the high level, and when the driving frequency is smaller than the reference frequency and the compensation gate signal rises from the low level to the high level, it sequentially has a first rising slew rate and a second rising slew rate smaller than the first rising slew rate. Claim 19 A display device according to claim 16, characterized in that when the driving frequency is smaller than the reference frequency, the compensation gate signal is fell from a high level to a low level and rises from the low level to the high level, and when the driving frequency is smaller than the reference frequency, the rising slew rate of the compensation gate signal is smaller than the falling slew rate of the compensation gate signal. Claim 20 A display device according to claim 16, characterized in that when the driving frequency is smaller than the reference frequency, the compensation gate signal has a first rising slew rate for a first grayscale greater than or equal to the reference grayscale, and when the driving frequency is smaller than the reference frequency, the compensation gate signal has a second rising slew rate greater than the first rising slew rate for a second grayscale smaller than the reference grayscale. Claim 21 A driving method for a display device comprising the steps of: providing a data writing gate signal and a compensation gate signal to a pixel; providing a data voltage to the pixel; and providing an emission signal to the pixel, wherein the pixel comprises a light-emitting element, a driving switching element that applies a driving current to the light-emitting element, a first compensation switching element and a second compensation switching element that are disposed between the control electrode and the output electrode of the driving switching element and are connected in series with each other, wherein the compensation gate signal is applied to the control electrode of the first compensation switching element and the control electrode of the second compensation switching element, and the falling waveform of the compensation gate signal and the rising waveform of the compensation gate signal are set asymmetrically, wherein the compensation gate signal is fallen from a high level to a low level, rises from the low level to an intermediate high level, rises from the intermediate high level to a high level, and the compensation gate signal rises from the low level to the intermediate high level and is maintained for the first half of the light-emitting section, and rises from the intermediate high level to a high level and is maintained for the second half of the light-emitting section.

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