2 Quantum device that facilitates the suppression of ZZ interactions between junction superconducting qubits

Abstract

Devices and / or computer implementation methods are provided for facilitating static ZZ suppression and Purcell loss reduction using mode-selective coupling in 2-junction superconducting qubits. In one embodiment, the device may include a superconducting bus resonator. The device may further include a first superconducting qubit. The device may further include a second superconducting qubit, wherein the first superconducting qubit and the second superconducting qubit each include a first superconducting pad, a second superconducting pad, a third superconducting pad, a first Josephson junction coupled to the first superconducting pad and the second superconducting pad, and a second Josephson junction coupled to the second superconducting pad and the third superconducting pad. The first superconducting pad and the second superconducting pad of the first superconducting qubit and the second superconducting qubit are coupled to the superconducting bus resonator. The superconducting bus resonator entangles the first superconducting qubit and the second superconducting qubit based on receiving a control signal.

Description

Technology Field

[0001] The subject of the present invention relates to quantum devices, and more specifically, to quantum devices that facilitate the suppression of ZZ interactions between two-junction superconducting quantum bits (qubits). Background Technology

[0002] Qubits coupled via a bus have residual interactions with each other, even in the absence of external drives (e.g., external microwave pulses, magnetic fields, etc.). These residual interactions, known as ZZ interactions, can cause the frequency of a qubit to depend on the state of its neighbors and can impair the fidelity of quantum operations. Furthermore, coupling qubits to a bus can cause energy loss and decoherence, either through internal losses in the bus (e.g., surface losses or two-level systems) or through external energy loss to the outside world via the bus's drive ports.

[0003] Some prior art uses two-junction qubits as a method to enable tunable coupling for a readout resonator and to encode multiple qubits within a single circuit. The problem with these prior art is that they do not use mode-selective coupling in multimode qubits to suppress static ZZ interactions between data modes while enabling purely longitudinal coupling for the bus resonator. means of solving the problem

[0004] A summary is provided below to provide a basic understanding of one or more embodiments of the invention. This summary is not intended to identify key or important components or to explain any scope of specific embodiments or claims. The sole purpose of the following summary is to provide concepts in a simplified form as an introduction to the more detailed description to be provided later. In one or more embodiments described herein, systems, devices, computer implementation methods, and / or computer program products are described that facilitate static ZZ suppression and Purcell loss reduction using mode-selective coupling in two-junction superconducting qubits.

[0005] According to one embodiment, the device may include a superconducting bus resonator. The device may further include a first superconducting qubit. The device may further include a second superconducting qubit, wherein the first superconducting qubit and the second superconducting qubit each include a first superconducting pad, a second superconducting pad, a third superconducting pad, a first Josephson junction coupled to the first superconducting pad and the second superconducting pad, and a second Josephson junction coupled to the second superconducting pad and the third superconducting pad. The first superconducting pad and the second superconducting pad of the first superconducting qubit and the second superconducting qubit are coupled to the superconducting bus resonator. The superconducting bus resonator entangles the first superconducting qubit and the second superconducting qubit based on receiving a control signal. The advantage of such a device is that it can suppress ZZ interactions between the first oscillation modes of both the first superconducting qubit and the second superconducting qubit and / or speed up a quantum gate (e.g., an entangled quantum gate) containing such qubits.

[0006] In some embodiments, the first superconducting pad and the second superconducting pad of the first superconducting qubit and the second superconducting qubit are coupled to the superconducting bus resonator to suppress ZZ interactions between the first superconducting qubit and the second superconducting qubit and reduce energy loss associated with the superconducting bus resonator, thereby facilitating at least one of a reduction in quantum gate errors associated with at least one of the first superconducting qubit and the second superconducting qubit, an increase in the speed of the quantum gate including the first superconducting qubit and the second superconducting qubit, and an improvement in fidelity, accuracy, and performance of the quantum processor including the device. An advantage of such a device is that it can enable the development of logical qubits and / or scalable quantum computers.

[0007] According to another embodiment, a computer implementation method may include the step of encoding quantum information in a first oscillating mode of a first superconducting qubit and a second superconducting qubit by a system operatively coupled to a processor. The computer implementation method may further include the step of coupling a superconducting bus resonator to an oscillating mode structure corresponding to a second oscillating mode of the first superconducting qubit and the second superconducting qubit by the system. An advantage of such a computer implementation method is that it can be implemented to suppress ZZ interactions between the first oscillating modes of both the first superconducting qubit and the second superconducting qubit and / or to increase the speed of a quantum gate (e.g., an entangled quantum gate) containing such qubits.

[0008] In some embodiments, the computer implementation method may further include the step of encoding the quantum information in the first oscillation mode of the first superconducting qubit and the second superconducting qubit by the system, and the step of coupling the superconducting bus resonator to the oscillation mode structure corresponding to the second oscillation mode of the first superconducting qubit and the second superconducting qubit by the system. Thus, ZZ interactions between the first superconducting qubit and the second superconducting qubit are suppressed and energy loss associated with the superconducting bus resonator is reduced, thereby facilitating at least one of the reduction of quantum gate errors associated with at least one of the first superconducting qubit and the second superconducting qubit, the increase in speed of the quantum gate including the first superconducting qubit and the second superconducting qubit, and the improvement of fidelity, accuracy, and performance of the quantum processor including the first superconducting qubit, the second superconducting qubit and the superconducting bus resonator. The advantage of this computer implementation method is that it can be implemented to enable the development of logical qubits and / or scalable quantum computers.

[0009] According to another embodiment, the device may include a superconducting bus resonator. The device may further include a first superconducting qubit. The device may further include a second superconducting qubit, and the first superconducting qubit and the second superconducting qubit each include a first superconducting pad, a second superconducting pad, a third superconducting pad, a first Josephson junction coupled to the first superconducting pad and the second superconducting pad, and a second Josephson junction coupled to the second superconducting pad and the third superconducting pad. The second superconducting pads of the first superconducting qubit and the second superconducting qubit are coupled to the superconducting bus resonator. The superconducting bus resonator entangles the first superconducting qubit and the second superconducting qubit based on receiving a control signal. The advantage of such a device is that it can suppress ZZ interactions between the first oscillation modes of both the first superconducting qubit and the second superconducting qubit and / or improve the speed of a quantum gate (e.g., an entangled quantum gate) containing such qubits.

[0010] In some embodiments, the second superconducting pad of the first superconducting qubit and the second superconducting pad of the second superconducting qubit are coupled to the superconducting bus resonator to suppress ZZ interactions between the first superconducting qubit and the second superconducting qubit and reduce energy loss associated with the superconducting bus resonator, thereby facilitating at least one of a reduction in quantum gate errors associated with at least one of the first superconducting qubit and the second superconducting qubit, an increase in the speed of the quantum gate including the first superconducting qubit and the second superconducting qubit, and an improvement in fidelity, accuracy, and performance of the quantum processor including the device. An advantage of such a device is that it can enable the development of logical qubits and / or scalable quantum computers.

[0011] According to another embodiment, a computer implementation method may include the step of encoding quantum information in the data mode of a first superconducting qubit and a second superconducting qubit by a system operatively coupled to a processor. The computer implementation method may further include the step of coupling a superconducting bus resonator to a coupling mode structure corresponding to the coupling mode of the first superconducting qubit and the second superconducting qubit by the system. An advantage of such a computer implementation method is that it can be implemented to suppress ZZ interactions between the first oscillation modes of both the first superconducting qubit and the second superconducting qubit and / or to increase the speed of a quantum gate (e.g., an entangled quantum gate) containing such qubits.

[0012] In some embodiments, the computer implementation method may further include the step of encoding the quantum information in the data mode of the first superconducting qubit and the second superconducting qubit by the system, and the step of coupling the superconducting bus resonator to the coupling mode structure corresponding to the coupling mode of the first superconducting qubit and the second superconducting qubit by the system. Thus, ZZ interactions between the first superconducting qubit and the second superconducting qubit are suppressed and energy loss associated with the superconducting bus resonator is reduced, thereby facilitating at least one of the reduction of quantum gate errors associated with at least one of the first superconducting qubit and the second superconducting qubit, the increase in the speed of the quantum gate including the first superconducting qubit and the second superconducting qubit, and at least one of the improvement in fidelity, the improvement in accuracy, and the improvement in performance of the quantum processor including the first superconducting qubit, the second superconducting qubit, and the superconducting bus resonator. The advantage of this computer implementation method is that it can be implemented to enable the development of logical qubits and / or scalable quantum computers.

[0013] According to another embodiment, the device may include a first superconducting qubit and a second superconducting qubit operating in a first oscillation mode. The device may further include a superconducting bus resonator coupled to an oscillation mode structure corresponding to a second oscillation mode of the first superconducting qubit and the second superconducting qubit. An advantage of such a device is that it can suppress ZZ interactions between the first oscillation modes of both the first superconducting qubit and the second superconducting qubit and / or improve the speed of a quantum gate (e.g., an entangled quantum gate) containing such qubits.

[0014] In some embodiments, the first superconducting qubit and the second superconducting qubit operate in the first oscillation mode, and the superconducting bus resonator is coupled to the oscillation mode structure corresponding to the second oscillation mode, thereby suppressing ZZ interactions between the first superconducting qubit and the second superconducting qubit and reducing energy loss associated with the superconducting bus resonator, thereby facilitating at least one of a reduction in quantum gate errors associated with at least one of the first superconducting qubit and the second superconducting qubit, an increase in the speed of the quantum gate including the first superconducting qubit and the second superconducting qubit, and an improvement in fidelity, accuracy, and performance of a quantum processor including the device. An advantage of such a device is that it can enable the development of logical qubits and / or scalable quantum computers. Brief explanation of the drawing

[0015] FIG. 1a shows a plan view of an example (but not limited to) of a device that can facilitate static ZZ suppression and Purcell loss reduction using mode-selective coupling in two-junction superconducting qubits according to one or more embodiments described herein, and FIG. 1b shows an example (but not limited to) of a circuit diagram of the device of FIG. 1a.

[0016] FIG. 2a shows a plan view of an example (but not limited to) of a device that can facilitate static ZZ suppression and Purcell loss reduction using mode-selective coupling in two-junction superconducting qubits according to one or more embodiments described herein, and FIG. 2b shows an example (but not limited to) of a circuit diagram of the device of FIG. 2a.

[0017] FIG. 3 shows a plan view of an example of a device (not limited to such example) that can facilitate static ZZ suppression and Purcell loss reduction using mode-selective coupling in two-junction superconducting qubits according to one or more embodiments described herein.

[0018] FIGS. 4, 5 and 6 show examples of graphs (not limited to these examples) that can facilitate static ZZ suppression and Purcell loss reduction using mode-selective coupling in two-junction superconducting qubits according to one or more embodiments described herein.

[0019] FIGS. 7, 8, and 9 show flow diagrams of examples of computer implementation methods (not limited to these examples) that can facilitate static ZZ suppression and Purcell loss reduction using mode-selective coupling in two-junction superconducting qubits according to one or more embodiments described herein.

[0020] FIG. 10 shows a block diagram of an example of an operating environment (not limited to such example) in which one or more of the embodiments described herein can be easily implemented. Specific details for implementing the invention

[0021] The following detailed description is for illustrative purposes only and is not intended to limit the embodiments and / or the application or use of the embodiments. Furthermore, there is no intention to limit the description by any expressions or implied information provided in the preceding background art or means of solution sections, or in the detailed description section.

[0022] One or more embodiments are now described with reference to the drawings, in which similar reference numbers are used to refer to similar components throughout the drawings. In the following description, many specific details are provided for illustrative purposes to provide a more thorough understanding of one or more embodiments. However, it is evident that in various cases, one or more embodiments may be practiced without these specific details.

[0023] Quantum computing generally involves the use of quantum-mechanical phenomena for the purpose of performing computing and information processing functions. Quantum computing can be viewed in contrast to classical computing, which typically operates on binary values ​​using transistors. That is, while classical computers can operate on bit values ​​that are either 0 or 1, quantum computers operate on quantum bits (qubits) that include superpositions of 0 and 1, can entangle multiple quantum bits, and use interference.

[0024] Considering the problems described above in relation to prior art, the present invention may be implemented to provide solutions to these problems in the form of devices and / or computer implementation methods, the devices and / or computer implementation methods of the present invention may facilitate static ZZ suppression and Purcell loss reduction by using mode-selective coupling in two-junction superconducting qubits by utilizing the device. The above device comprises a superconducting bus resonator, a first superconducting qubit, and a second superconducting qubit, wherein the first superconducting qubit and the second superconducting qubit each comprise a first superconducting pad, a second superconducting pad, a third superconducting pad, a first Josephson junction coupled to the first superconducting pad and the second superconducting pad, and a second Josephson junction coupled to the second superconducting pad and the third superconducting pad, wherein the first superconducting pad and the second superconducting pad of the first superconducting qubit and the second superconducting qubit are coupled to the superconducting bus resonator, and the superconducting bus resonator entangles the first superconducting qubit and the second superconducting qubit based on receiving a control signal. The advantage of these devices and / or computer implementation methods is that they can be implemented to suppress ZZ interactions between the first oscillation modes of both the first superconducting qubit and the second superconducting qubit and / or to increase the speed of a quantum gate (e.g., an entangled quantum gate) containing such qubits.

[0025] In some embodiments, the present invention may be implemented in the form of devices and / or computer implementation methods to produce solutions to the problems described above. In said devices and / or computer implementation methods, the first superconducting pad and the second superconducting pad of said first superconducting qubit and said second superconducting qubit are coupled to said superconducting bus resonator to suppress ZZ interactions between said first superconducting qubit and said second superconducting qubit and to reduce energy loss associated with said superconducting bus resonator, thereby facilitating at least one of a reduction in quantum gate errors associated with at least one of said first superconducting qubit and said second superconducting qubit, an increase in the speed of a quantum gate including said first superconducting qubit and said second superconducting qubit, and an improvement in fidelity, an improvement in accuracy, and an improvement in performance of a quantum processor including said device. An advantage of said devices and / or computer implementation methods is that they may be implemented to enable the development of logical qubits and / or scalable quantum computers.

[0026] It will be understood that when one component is referred to as being "coupled" to another component, it may describe one or more different types of coupling, including (but not limited to) chemical coupling, communication coupling, electrical coupling, electromagnetic coupling, kinetic coupling, optical coupling, physical coupling, thermal coupling, and / or other types of coupling. It will also be understood that the following terms referenced herein will be defined as follows.

[0027] FIG. 1a shows a plan view of one example (but not limited to this example) of a device (100a) that can facilitate static ZZ suppression and Purcell loss reduction using mode-selective coupling in two-junction superconducting qubits according to one or more embodiments described herein, and FIG. 1b shows one example (but not limited to this example) of a circuit diagram of the device (100a).

[0028] The device (100a) may include a semiconducting and / or superconducting device that can be implemented in a quantum device. For example, the device (100a) may include an integrated semiconducting and / or superconducting circuit (e.g., a quantum circuit) which can be implemented in a quantum device such as, for example, quantum hardware, a quantum processor, a quantum computer, and / or another quantum device. The device (100a) may include a semiconducting and / or superconducting device such as a quantum coupler device that can be implemented in, for example, such a quantum device defined above.

[0029] As illustrated by the embodiment shown in FIGS. 1a and 1b, the device (100a) may include a superconducting bus resonator (102) (labeled as resonator in FIGS. 1a and 1b). The superconducting bus resonator (102) may be coupled to a first superconducting qubit (104a) (labeled as tunable coupler qubit (TCQ1) in FIGS. 1a and 1b) and a second superconducting qubit (104b) (labeled as tunable qubit (TCQ2) in FIGS. 1a and 1b). The superconducting bus resonator (102) shown in the embodiment shown in FIGS. 1a and 1b may include a coplanar waveguide resonator. The first superconducting qubit (104a) and / or the second superconducting qubit (104b) shown in the embodiments illustrated in FIG. 1a and 1b may each include at least one of a tunable coupler qubit, a two junction qubit, a multimode qubit, a multimode two junction qubit, and a tunable qubit.

[0030] The superconducting bus resonator (102) shown in the embodiment illustrated in FIGS. 1a and 1b may include a first superconducting pad (102a), a second superconducting pad (102b), a third superconducting pad (102c), and / or a fourth superconducting pad (102d), each of which may include an electrode. In this embodiment, the first superconducting pad (102a), the second superconducting pad (102b), the third superconducting pad (102c), and / or the fourth superconducting pad (102d) may each include a superconducting film (e.g., a superconducting metal film). Such a superconducting film may be formed on a substrate (e.g., a silicon (Si) substrate, etc.) using one or more semiconductor and / or superconducting device manufacturing techniques described below. As shown in the embodiment illustrated in FIG. 1b, the superconducting bus resonator (102) is an inductor (132) (in FIG. 1b L R (indicated as ), capacitor (134) (in FIG. 1b) C R It may further include (indicated as ), and / or ground (136). As shown in the embodiment illustrated in FIG. 1b, the superconducting bus resonator (102) may have a resonant frequency of 6 gigahertz (GHz).

[0031] The first superconducting qubit (104a) shown in the embodiment illustrated in FIGS. 1a and 1b may include a first superconducting pad (106a), a second superconducting pad (108a), and / or a third superconducting pad (110a), each of which may include an electrode. In this embodiment, each of the first superconducting pad (106a), the second superconducting pad (108a), and / or the third superconducting pad (110a) may include a superconducting film (e.g., a superconducting metal film). Such a superconducting film may be formed on a substrate (e.g., a silicon (Si) substrate, etc.) using one or more semiconductor and / or superconducting device manufacturing techniques described below. The first superconducting qubit (104a) shown in the embodiment illustrated in FIG. 1a and 1b is coupled to a first Josephson junction (112a) (in FIG. 1b) which is coupled to a first superconducting pad (106a) and a second superconducting pad (108a). E J1 It may further include (indicated as ). The first superconducting qubit (104a) shown in the embodiment illustrated in FIG. 1a and 1b is coupled to a second Josephson junction (114a) (in FIG. 1b) which is coupled to a second superconducting pad (108a) and a third superconducting pad (110a). E J2 It may further include (indicated by ). In this embodiment, the first Josephson junction (112a) and / or the second Josephson junction (114a) may include one or more superconducting films (e.g., superconducting metal films) and / or one or more non-superconducting films (e.g., normal metal films) formed on a substrate (e.g., a silicon (Si) substrate, etc.).

[0032] As shown in the embodiments illustrated in FIGS. 1a and 1b, the first superconducting pad (106a) and the second superconducting pad (108a) of the first superconducting qubit (104a) can be capacitively coupled to each other, and this capacitive coupling is the first capacitor (116a) in FIG. 1b (in FIG. 1b C 1 It is expressed as (indicated as ). As shown in the embodiment illustrated in FIGS. 1a and 1b, the second superconducting pad (108a) and the third superconducting pad (108b) of the first superconducting qubit (104a) can be capacitively coupled to each other, and this capacitive coupling is the second capacitor (118a) in FIG. 1b (in FIG. 1b C 2 It is expressed as (indicated as ). In the embodiment shown in FIG. 1b, the first capacitor (116b) and the second capacitor (118a) each represent direct capacitive shunting across the first Josephson junction (112a) and the second Josephson junction (114a). As shown in FIG. 1a and 1b, in this embodiment, the first superconducting qubit (104a) may include two capacitively shunted Josephson junctions connected in series, namely the first Josephson junction (112a) and the second Josephson junction (114a).

[0033] The second superconducting qubit (104b) shown in the embodiment illustrated in FIGS. 1a and 1b may include a first superconducting pad (106b), a second superconducting pad (108b), and / or a third superconducting pad (110b), each of which may include an electrode. In this embodiment, each of the first superconducting pad (106b), the second superconducting pad (108b), and / or the third superconducting pad (110b) may include a superconducting film (e.g., a superconducting metal film). Such a superconducting film may be formed on a substrate (e.g., a silicon (Si) substrate, etc.) using one or more semiconductor and / or superconducting device manufacturing techniques described below. The second superconducting qubit (104b) shown in the embodiment illustrated in FIG. 1a and 1b is coupled to a first Josephson junction (112b) (in FIG. 1b) which is coupled to a first superconducting pad (106b) and a second superconducting pad (108b). E J3 It may further include (indicated as ). The second superconducting qubit (104b) shown in the embodiment illustrated in FIG. 1a and 1b is a second Josephson junction (114b) coupled to the second superconducting pad (108b) and the third superconducting pad (110b) (in FIG. 1b E J4 It may further include (indicated by ). In this embodiment, the first Josephson junction (112b) and / or the second Josephson junction (114b) may include one or more superconducting films (e.g., superconducting metal films) and / or one or more non-superconducting films (e.g., normal metal films) formed on a substrate (e.g., a silicon (Si) substrate, etc.).

[0034] As shown in the embodiments illustrated in FIGS. 1a and 1b, the first superconducting pad (106b) and the second superconducting pad (108b) of the second superconducting qubit (104b) can be capacitively coupled to each other, and this capacitive coupling is the first capacitor (116b) in FIG. 1b (in FIG. 1b C3 It is expressed as (indicated as ). As shown in the embodiment illustrated in FIGS. 1a and 1b, the second superconducting pad (108b) and the third superconducting pad (110b) of the second superconducting qubit (104b) can be capacitively coupled to each other, and this capacitive coupling is the second capacitor (116b) in FIG. 1b (in FIG. 1b C 4 It is expressed as (indicated as ). In the embodiment shown in FIG. 1b, the first capacitor (116b) and the second capacitor (118b) each represent a direct capacitive shunt across the first Josephson junction (112b) and the second Josephson junction (114b). In this embodiment, as shown in FIG. 1a and 1b, the second superconducting qubit (104b) may include two capacitively shunted Josephson junctions connected in series, namely the first Josephson junction (112b) and the second Josephson junction (114b).

[0035] The first superconducting qubit (104a) and the second superconducting qubit (104b) shown in the embodiments illustrated in FIGS. 1a and 1b may each operate in a first oscillation mode and a second oscillation mode (not shown in the drawings). In some embodiments of the subject matter of the invention described herein, the first oscillation mode and the second oscillation mode may correspond to different (e.g., distinct) frequencies and / or different (e.g., distinct) spatial symmetries with respect to each other. In these embodiments, the first oscillation mode and the second oscillation mode may represent symmetric and antisymmetric combinations of excitations associated with the first Josephson junction (112a) and the second Josephson junction (114a) of the first superconducting qubit (104a), and / or the first Josephson junction (112b) and the second Josephson junction (114b) of the second superconducting qubit (104b). In these embodiments, these symmetric and antisymmetric combinations of excitations associated with the first Josephson junction (112a) and the second Josephson junction (114a) of the first superconducting qubit (104a) may occur as a result of capacitive coupling of the first superconducting pad (106a) and the third superconducting pad (110a) of the first superconducting qubit (104a), and such capacitive coupling is the third capacitor (120a) in FIG. 1b (in FIG. 1b C S1 It is expressed as (indicated as ). In these embodiments, these symmetric and antisymmetric combinations of excitations associated with the first Josephson junction (112b) and the second Josephson junction (114b) of the second superconducting qubit (104b) may occur as a result of capacitive coupling of the first superconducting pad (106b) and the third superconducting pad (110b) of the second superconducting qubit (104b), and such capacitive coupling is the third capacitor (120b) in FIG. 1b (in FIG. 1b C S2 It is expressed as (indicated as ).

[0036] In the embodiment shown in FIGS. 1a and 1b, the third capacitor (120a) represents a capacitive coupling between the first superconducting pad (106a) and the third superconducting pad (110a) of the first superconducting qubit (104a), and such capacitive coupling can enable the generation of the first oscillation mode and the second oscillation mode having different frequencies and different spatial symmetries with respect to each other as described above. In this embodiment, such capacitive coupling represented by the third capacitor (120a) in FIG. 1b can enable the first oscillation mode and the second oscillation mode to interact with each other, whereas without such capacitive coupling represented by the third capacitor (120a), these modes would be isolated across the first Josephson junction (112a) and the second Josephson junction (114a) of the first superconducting qubit (110a). In this embodiment, such interaction between the first oscillation mode and the second oscillation mode may enable the generation of extended states of the first superconducting qubit (104a) (e.g., hybridized quantum states, hybridized oscillation modes, etc.) (hybridized quantum states and / or hybridized oscillation modes corresponding to different frequencies and different spatial symmetries). In this embodiment, such capacitive coupling, represented by the third capacitor (120a) in FIG. 1b, may allow the fundamental mode of the first superconducting qubit (104a) to be extended symmetrically or antisymmetrically across the first Josephson junction (112a) and the second Josephson junction (114a).

[0037] In the embodiment shown in FIGS. 1a and 1b, the third capacitor (120b) represents a capacitive coupling between the first superconducting pad (106b) and the third superconducting pad (110b) of the second superconducting qubit (104b), and such capacitive coupling can enable the generation of a first oscillation mode and a second oscillation mode having different frequencies and different spatial symmetries with respect to each other as described above. In this embodiment, such capacitive coupling represented by the third capacitor (120b) in FIG. 1b can enable the first oscillation mode and the second oscillation mode to interact with each other, whereas without such capacitive coupling represented by the third capacitor (120b), these modes would be isolated across the first Josephson junction (112b) and the second Josephson junction (114b) of the second superconducting qubit (104b). In this embodiment, such interaction between the first oscillation mode and the second oscillation mode may enable the generation of extended states of the second superconducting qubit (104b) (e.g., hybridized quantum states, hybridized oscillation modes, etc.) (e.g., hybridized quantum states and / or hybridized oscillation modes corresponding to different frequencies and different spatial symmetries). In this embodiment, such capacitive coupling, represented by the third capacitor (120b) in FIG. 1b, may allow the fundamental mode of the first superconducting qubit (104b) to be extended symmetrically or antisymmetrically across the first Josephson junction (112b) and the second Josephson junction (114b).

[0038] The first oscillation mode and the second oscillation mode may correspond to the first oscillation mode structure (124a) (labeled as mode A in FIG. 1a) and the second oscillation mode structure (124b) (labeled as mode B in FIG. 1a), respectively. In the embodiment shown in FIG. 1a and 1b, the first oscillation mode structure (124a) and the second oscillation mode structure (124b) may each define any coupling technique (e.g., coupling scheme, coupling array, coupling pattern, etc.) that can be used to encode and / or store quantum information in the first oscillation mode of the first superconducting qubit (104a) and / or the second superconducting qubit (104b). Consequently, in this embodiment, the first oscillation mode and / or second oscillation mode of the first superconducting qubit (104a) and / or second superconducting qubit (104b) may include encoded quantum information (e.g., qubit information, quantum state information, etc.). In this embodiment, the first oscillation mode structure (124a) and / or second oscillation mode structure (124b) may be used to couple a superconducting bus resonator (102) to the first oscillation mode and / or second oscillation mode, so that the superconducting bus resonator (102) may operate according to the first oscillation mode and / or second oscillation mode of the first superconducting qubit (104a) and / or second superconducting qubit (104b).

[0039] The first superconducting qubit (104a) and / or the second superconducting qubit (104b) shown in the embodiment illustrated in FIG. 1a and 1b may be capacitively coupled to the superconducting bus resonator (102). In the embodiment illustrated in FIG. 1a and 1b, the first superconducting pad (102a) of the superconducting bus resonator (102) may be capacitively coupled to the first superconducting pad (106a) of the first superconducting qubit (104a), and this capacitive coupling is a capacitor (126a) in FIG. 1b (in FIG. 1b C C1 It is expressed as (indicated as ). In this embodiment, the second superconducting pad (102b) of the superconducting bus resonator (102) can be capacitively coupled to the second superconducting pad (108a) of the first superconducting qubit (104a), and this capacitive coupling is a capacitor (128a) in FIG. 1b (in FIG. 1b C C2 It is expressed as (indicated by ). In this embodiment, the third superconducting pad (102c) of the superconducting bus resonator (102) can be capacitively coupled to the first superconducting pad (106b) of the second superconducting qubit (104b), and this capacitive coupling is a capacitor (126b) in FIG. 1b (in FIG. 1b C C3 It is expressed as (indicated by ). In this embodiment, the fourth superconducting pad (102d) of the superconducting bus resonator (102) can be capacitively coupled to the second superconducting pad (108a) of the second superconducting qubit (104b), and this capacitive coupling is a capacitor (128b) in FIG. 1b (in FIG. 1b C C4 It is expressed as (indicated as ).

[0040] In some embodiments, the superconducting bus resonator (102) may be coupled to the first superconducting qubit (104a) and the second superconducting qubit (104b) based on a first oscillation mode structure (124a) corresponding to a first oscillation mode of the first superconducting qubit (104a) and the second superconducting qubit (104b) (e.g., thus), and the first oscillation mode may include a coupled mode. In these embodiments, a second oscillation mode structure (124b) corresponding to a second oscillation mode of a first superconducting qubit (104a) and a second superconducting qubit (104b) can enable encoding and / or storing quantum information (e.g., qubit information, quantum state information, etc.) in the second oscillation mode of the first superconducting qubit (104a) and the second superconducting qubit (104b), and said second oscillation mode may include a data mode. In other embodiments, the superconducting bus resonator (102) may be coupled to the first superconducting qubit (104a) and the second superconducting qubit (104b) based on a second oscillation mode structure (124b) corresponding to a second oscillation mode of the first superconducting qubit (104a) and the second superconducting qubit (104b) (e.g., thus), and the second oscillation mode may include a coupled mode. In these embodiments, a first oscillation mode structure (124a) corresponding to a first oscillation mode of a first superconducting qubit (104a) and a second superconducting qubit (104b) can enable encoding and / or storing quantum information (e.g., qubit information, quantum state information, etc.) in the first oscillation mode of the first superconducting qubit (1104a) and the second superconducting qubit (104b), and the first oscillation mode may include a data mode.As referenced herein, these mode-selective combination schemes described in the above embodiments may constitute mode-selective combination schemes that can be realized by an entity (e.g., human, computing device, software application, agent, machine learning model, artificial intelligence model, etc.) implementing one or more of the embodiments of the subject matter of the invention described herein (e.g., device (100a), device (200a), device (300), etc.).

[0041] In the embodiment illustrated in FIG. 1a and 1b, the superconducting bus resonator (102) may be coupled to the first superconducting qubit (104a) and the second superconducting qubit (104b) based on a second oscillation mode structure (124b) corresponding to the second oscillation mode of the first superconducting qubit (104a) and the second superconducting qubit (104b) (e.g., thus), and the second oscillation mode may include a coupled mode. In this embodiment illustrated in FIG. 1a and 1b, a first oscillation mode structure (124a) corresponding to a first oscillation mode of a first superconducting qubit (104a) and a second superconducting qubit (104b) can enable encoding and / or storing quantum information (e.g., qubit information, quantum state information, etc.) in the first oscillation mode of the first superconducting qubit (104a) and the second superconducting qubit (104b), and the first oscillation mode may include a data mode.

[0042] In the embodiment shown in FIG. 1a and 1b, by coupling a superconducting bus resonator (102) to the first superconducting qubit (104a) and the second superconducting qubit (104b) based on a second oscillation mode structure (124b) corresponding to the second oscillation mode (e.g., thus) and encoding and / or storing quantum information in the first oscillation mode of the first superconducting qubit (104a) and the second superconducting qubit (104b), the device (100a) can thereby facilitate the suppression (elimination, reduction, etc.) of direct interactions between the first oscillation mode of the first superconducting qubit (104a) and the first oscillation mode of the second superconducting qubit (104b). For example, in this embodiment, the device (100a) can facilitate the suppression (e.g., cancellation, reduction, etc.) of direct interactions such as exchange interactions and / or static ZZ interactions between the first superconducting qubit (104a) and the second superconducting qubit (104b) (e.g., between the first oscillation mode of the first superconducting qubit (104a) and the first oscillation mode of the second superconducting qubit (104b)). In this embodiment, the device (100a) can facilitate the suppression of static ZZ interactions between the first oscillation mode of the first superconducting qubit (104a) and the first oscillation mode of the second superconducting qubit (104b) because there are higher-order interactions (e.g., data mode 1 → coupling mode 1 → bus resonator → coupling mode 2 → data mode 2). For example, higher-order interactions can be expressed as follows.That is, data mode 1 (e.g., first oscillation mode of the first superconducting qubit (104a)) → coupling mode 1 (e.g., second oscillation mode of the first superconducting qubit (104a)) → bus resonator (e.g., superconducting bus resonator (102)) → coupling mode 2 (e.g., second oscillation mode of the second superconducting qubit (104b)) → data mode 2 (first oscillation mode of the second superconducting qubit (104b)).

[0043] In the embodiment shown in FIG. 1a and 1b, by coupling a superconducting bus resonator (102) to the first superconducting qubit (104a) and the second superconducting qubit (104b) based on (e.g., thus) a second oscillation mode structure (124b) corresponding to the second oscillation mode, and encoding and / or storing quantum information in the first oscillation mode of the first superconducting qubit (104a) and the second superconducting qubit (104b), the device (100a) can thereby more facilitate a strong (e.g., relatively strong) longitudinal coupling between the first oscillation mode and the second oscillation mode of the first superconducting qubit (104a) and the second superconducting qubit (104b) (e.g., between the first oscillation mode structure (124a) and the second oscillation mode structure (124b). In this embodiment, such strong (e.g., relatively strong) longitudinal coupling between the first oscillation mode and the second oscillation mode of the first superconducting qubit (104a) and the second superconducting qubit (104b) (e.g., between the first oscillation mode structure (124a) and the second oscillation mode structure (124b)) can enable net longitudinal coupling between the superconducting bus resonator (102) and the first oscillation mode of the first superconducting qubit (104a) and the second superconducting qubit (104b). In this embodiment, such net longitudinal coupling between the superconducting bus resonator (102) and the first oscillation mode of the first superconducting qubit (104a) and the second superconducting qubit (104b) (which is also referred to as the chi shift (chi_01 shift)) can enable the generation and / or execution of two-qubit entangling gates through a resonator-induced phase (RIP) by driving the superconducting bus resonator (102) in a detuned state from its resonant frequency (e.g., 6 GHz) (e.g., through microwave pulses).

[0044] Also, or alternatively, in the embodiment shown in FIGS. 1a and 1b, the device (100a) may further prevent exchange coupling between data modes and the superconducting bus resonator (102), which may protect such data modes from energy loss associated with the superconducting bus resonator (102) (e.g., Purcell loss) (e.g., internal energy propagation to an external environment or energy loss to the device (100a) through a drive port near the superconducting bus resonator (102). For example, in the embodiment shown in FIGS. 1a and 1b, the device (100a) may prevent exchange coupling between the superconducting bus resonator (102) and the first oscillation mode of the first superconducting qubit (104a), and / or exchange coupling between the superconducting bus resonator (102) and the first oscillation mode of the second superconducting qubit (104b). In this embodiment, by preventing such exchange coupling between these data modes and the superconducting bus resonator (102) as described above, the device (100a) can thereby facilitate the reduction of Purcell loss and / or decoherence associated with the device (100a) and / or one or more components of the device (100a) (e.g., superconducting bus resonator (102), first superconducting qubit (104a), second superconducting qubit (104b), etc.).

[0045] Various embodiments of the subject matter of the invention described herein and / or illustrated in the drawings (e.g., device (100a), device (200a), device (300), etc.) may be coupled to one or more external devices (not shown in FIG. 1a or 1b) to facilitate the operation of these embodiments. For example, in relation to the embodiment illustrated in FIG. 1a and 1b, device (100a), superconducting bus resonator (102), first superconducting qubit (104a), and / or second superconducting qubit (104b) may be coupled to one or more external devices—such as, for example, a pulse generator device, an electric power source, and / or a magnetic field generator—which may be located outside of device (100a).

[0046] In one embodiment, although not illustrated in FIG. 1a or 1b, the device (100a), the superconducting bus resonator (102), the first superconducting qubit (104a), and / or the second superconducting qubit (104b) may be coupled to a pulse generator device. For example, the pulse generator device may include, but is not limited to, another pulse generator device that is located outside of the device (100a), the device (100a), the device (100a), the superconducting bus resonator (102), the first superconducting qubit (104a), and / or the second superconducting qubit (104b) and can transmit pulses (e.g., microwave pulses, microwave signals, control signals, etc.) to and / or receive such pulses from the device (100a). In another embodiment, although not illustrated in FIG. 1a or 1b, the device (100a), superconducting bus resonator (102), first superconducting qubit (104a), and / or second superconducting qubit (104b) may be coupled to an electric power source and / or magnetic field generator. Such electric power source and / or magnetic field generator may be located outside the device (100a) and may supply an electric current, an electric potential, and / or a magnetic field to the device (100a), superconducting bus resonator (102), first superconducting qubit (104a), and / or second superconducting qubit (104b).

[0047] In the above embodiments, such one or more external devices (e.g., pulse generator devices (e.g., AWG, VNA, etc.), electric power sources, and / or magnetic field generators) may also be coupled to a computer (computer (1012) described below with reference to FIG. 10) comprising a memory (e.g., system memory (1016) described below with reference to FIG. 10) and a processor (e.g., processing unit (1014) described below with reference to FIG. 10). The memory may store instructions (e.g., software, routines, processing threads, etc.) therein, and the processor may execute such instructions that may be stored in the memory. In these embodiments, the computer may be used to operate and / or control one or more of these external devices (e.g., pulse generator devices (e.g., AWG, VNA, etc.), electric power sources, and / or magnetic field generators) (e.g., through a processing unit (1014) that executes instructions stored in the system memory (1016)). For example, in these embodiments, such a computer may be used to enable one or more external devices (e.g., pulse generator device (e.g., AWG, VNA, etc.), electric power source, and / or magnetic field generator) to a) transmit pulses (e.g., microwave pulses, microwave signals, control signals, etc.) to a device (100a), a superconducting bus resonator (102), a first superconducting qubit (104a), and / or a second superconducting qubit (104b) and / or receive pulses (e.g., microwave pulses, microwave signals, control signals, etc.) from them, and / or b) provide an electric current, an electric potential, and / or a magnetic field to the device (100a), the superconducting bus resonator (102), the first superconducting qubit (104a), and / or the second superconducting qubit (104b).

[0048] In various embodiments, an entity implementing the device (100a) (e.g., an entity such as a human, a computing device, a software application, an agent, a machine learning model, an artificial intelligence model, etc.) may implement one or more of the mode-selective coupling schemes described herein according to one or more embodiments of the subject matter of the present invention (mode-selective coupling schemes described and shown in FIG. 1a, 1b, 2a, 2b, and / or 3). In these embodiments, such an entity may implement one or more of these mode-selective schemes by setting and / or adjusting one or more coupling capacitances between the superconducting bus resonator (102) and one or more superconducting pads of the first superconducting qubit (104a) and / or the second superconducting qubit (104b), so as to achieve one or more of these mode-selective schemes. In these embodiments, such an entity may set and / or adjust one or more of these combined capacitances (e.g., capacitors (126a), capacitors (126b), capacitors (128a), and / or capacitors (128b)) by applying and / or adjusting a magnetic field, electric current, electric potential, and / or microwave pulse applied to the device (100a) and / or one or more components of the device (100a) (e.g., superconducting bus resonator (102), first superconducting qubit (104a), second superconducting qubit (104b), etc.) (e.g., through one or more of the external devices defined above as described above and / or computer (1012)).

[0049] In the embodiment shown in FIGS. 1a and 1b, the entity defined above can set and / or adjust the coupled capacitances represented by capacitor (126a), capacitor (126b), capacitor (128a), and / or capacitor (128b) in FIG. 1b by applying and / or adjusting a magnetic field, electric current, electric potential, and / or microwave pulse applied to the device (100a) and / or one or more components of the device (100a) (e.g., superconducting bus resonator (102), first superconducting qubit (104a), second superconducting qubit (104b), etc.) (e.g., through one or more of the external devices defined above and / or computer (1012) as described above). In this embodiment, based on setting and / or adjusting these coupling capacitances described above, the entity defined herein realizes the mode-selective coupling scheme described above by it, wherein the superconducting bus resonator (102) may be coupled to the first superconducting qubit (104a) and the second superconducting qubit (104b) based on a second oscillation mode structure (124b) corresponding to a second oscillation mode of the first superconducting qubit (104a) and the second superconducting qubit (104b)—the second oscillation mode includes a coupling mode—e.g., thus, and / or quantum information (e.g., qubit information, quantum state information, etc.) may be coupled to the first oscillation mode of the first superconducting qubit (104a) and the second superconducting qubit (104b)—the first oscillation mode includes a data mode—based on the first oscillation mode structure (124a) (e.g., thus, thus). Can be encoded and / or stored.

[0050] In this embodiment, to realize a net exchange coupling of the superconducting bus resonator (102) for a second oscillation mode of only the first superconducting qubit (104a) and the second superconducting qubit (104b) (e.g., net exchange coupling of the superconducting bus resonator (102) for a second oscillation mode structure (124b) corresponding to a second oscillation mode of only the first superconducting qubit (104a) and the second superconducting qubit (104b)), such an entity defined herein may set and / or adjust such coupling capacitances as follows: namely, capacitor 126a = 2 * capacitor 128a (e.g., C C1 = 2 * C C2 ) and capacitor 126b = 2 * capacitor 128b(e.g., C C3 = 2 * C C4 )am.

[0051] In the above embodiment, based on realizing the mode-selective coupling scheme described above, an entity implementing the device (100a) thereby suppresses (e.g., erasure, reduction, etc.) direct interactions such as exchange interactions and / or static ZZ interactions between, for example, a first superconducting qubit (104a) and a second superconducting qubit (104b) (e.g., between a first oscillation mode of the first superconducting qubit (104a) and a first oscillation mode of the second superconducting qubit (104b) - said first oscillation mode and said second oscillation mode may include data modes of the first superconducting qubit (104a) and the second superconducting qubit (104b) -), b) between a first oscillation mode of the first superconducting qubit (104a) and a second oscillation mode of the second superconducting qubit (104b) (e.g., said first oscillation mode A strong (e.g., relatively strong) longitudinal coupling between structure (124a) and second oscillation mode structure (124b), c) prevention of exchange coupling between data modes (e.g., first oscillation mode and second oscillation mode) and superconducting bus resonator (102) - which can reduce energy loss (e.g., Purcell loss) and / or decoherence associated with device (100a) and / or superconducting bus resonator (102). In this embodiment, based on such suppression of these ZZ interactions associated with the superconducting bus resonator (102), reduction of energy loss, and / or reduction of decoherence, the device (100a) can thereby facilitate at least one of the reduction of quantum gate errors associated with the first superconducting qubit (104a) and / or the second superconducting qubit (104b), an increase in the speed of the quantum gate including the first superconducting qubit (104a) and the second superconducting qubit (104b), and / or an improvement in the fidelity, accuracy, or performance of the quantum processor including the device (100a).

[0052] In the above embodiment, the entity defined herein implementing the device (100a) may further drive the superconducting bus resonator (102) to a detuned state from its resonant frequency (e.g., 6 GHz) to generate and / or perform two quantum entanglement gates via a RIP gate (e.g., via microwave pulses using one or more of the external devices defined above and / or a computer (1012)). For example, in this embodiment, by driving the superconducting bus resonator (102) to a detuned state from its resonant frequency as described above, such an entity may entangle the first superconducting qubit (104a) and the second superconducting qubit (104b) (e.g., to generate an entanglement quantum gate between the first superconducting qubit (104a) and the second superconducting qubit (104b)). In this embodiment, such entanglement of the first superconducting qubit (104a) and the second superconducting qubit (104b) can enable quantum gate operations to be performed between the first superconducting qubit (104a) and the second superconducting qubit (104b). For example, in this embodiment, based on driving the superconducting bus resonator (102) in a state detuned from its resonant frequency, the device (100a) and / or the superconducting bus resonator (102) may operate as a RIP gate, which can generate ZZ interactions between a first qubit (e.g., a first superconducting qubit (104a)) and a second qubit (e.g., a second superconducting qubit (104b)) that exist when there is a microwave drive (e.g., a microwave pulse, a microwave signal, a control signal, etc.) in the superconducting bus resonator (102) (e.g., when there is a microwave signal applied to the superconducting bus resonator (102)).

[0053] The fabrication of various embodiments of the subject matter of the present invention described herein and / or illustrated in the drawings (e.g., device (100a), device (200a), device (300), etc.) may include, for example, a multi-step sequence of photolithographic and / or chemical treatment steps. These steps facilitate the progressive creation of electronic-based systems, devices, components, and / or circuits in semiconducting and / or superconducting devices (e.g., integrated circuits). For example, various embodiments of the subject matter of the present invention described herein and / or illustrated in the drawings (e.g., device (100a), device (200a), device (300), etc.) may be fabricated on a substrate (e.g., a silicon (Si) substrate, etc.) by utilizing the following techniques.Examples of the above technologies include photolithography, microlithography, nanolithography, nanoimprint lithography, photomasking technologies, patterning technologies, photoresist technologies (e.g., positive-tone photoresist, negative-tone photoresist, hybrid-tone photoresist, etc.), etching technologies (e.g., reactive ion etching (RIE), dry etching, wet etching, ion beam etching, plasma etching, laser ablation, etc.), evaporation technologies, sputtering technologies, and plasma ashing. Technologies, heat treatments (e.g., rapid thermal anneal, furnace anneals, thermal oxidation, etc.), chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), molecular beam epitaxy (MBE), electrochemical deposition (ECO), chemical-mechanical planarization (CMP), backgrinding technologies, and / or other technologies for manufacturing integrated circuits, including but not limited to these examples.

[0054] Various embodiments of the subject matter of the present invention described herein and / or illustrated in the drawings (e.g., device (100a), device (200a), device (300), etc.) may be manufactured using various materials. For example, various embodiments of the subject matter of the present invention described herein and / or illustrated in the drawings (e.g., device (100a), device (200a), device (300), etc.) may be manufactured using materials of one or more different material classes as follows. The above material classifications may be, for example, conductive materials, semiconducting materials, superconducting materials, dielectric materials, polymer materials, organic materials, inorganic materials, non-conductive materials, and / or other materials that can be used in one or more of the techniques described above for manufacturing integrated circuits, but are not limited to these examples.

[0055] FIG. 2a shows a plan view of an example (but not limited to) of a device (200a) capable of facilitating static ZZ suppression and Purcell loss reduction using mode-selective coupling in two-junction superconducting qubits according to one or more embodiments described herein. FIG. 2b shows an example (but not limited to) of a circuit diagram (200b) of the device (200a). Repetitive descriptions of similar components and / or processes used in each embodiment are omitted for brevity.

[0056] The device (200a) may include an alternative embodiment of the device (100a) described above with reference to FIGS. 1a and 1b (but is not limited to such examples). For example, as shown in the embodiment illustrated in FIGS. 2a and 2b, the device (200a) may include an alternative embodiment of the device (100a) (but is not limited to such examples), wherein only the second superconducting pad (108a) of the first superconducting qubit (104a) and the second superconducting pad (108b) of the second superconducting qubit (104b) are coupled to the third superconducting pad (102c) and the fourth superconducting pad (102d) of the superconducting bus resonator (102), respectively. Also, or alternatively, as shown in the embodiment illustrated in FIG. 2b, the superconducting bus resonator (102) of the device (200a) may have a resonant frequency (fr) of 4 GHz.

[0057] As shown in the embodiments illustrated in FIGS. 2a and 2b, the second superconducting pad (08a) of the first superconducting qubit (104a) can be capacitively coupled to the third superconducting pad (102c) of the superconducting bus resonator (102), and this capacitive coupling is the first capacitor (228a) in FIG. 2b (in FIG. 2b C C1 It is expressed as (indicated as ). In this embodiment, the second superconducting pad (108b) of the second superconducting qubit (104b) can be capacitively coupled to the fourth superconducting pad (102d) of the superconducting bus resonator (102), and this capacitive coupling is the second capacitor (228b) in FIG. 2b (in FIG. 2b C C2 It is expressed as (indicated as ).

[0058] As described above with reference to FIGS. 1a and 1b, in some embodiments, the superconducting bus resonator (102) may be coupled to the first superconducting qubit (104a) and the second superconducting qubit (104b) based on a first oscillation mode structure (124a) corresponding to a first oscillation mode of the first superconducting qubit (104a) and the second superconducting qubit (104b) (e.g., thus), and the first oscillation mode may include a coupled mode. In these embodiments, a second oscillation mode structure (124b) corresponding to a second oscillation mode of a first superconducting qubit (104a) and a second superconducting qubit (104b) can enable encoding and / or storing quantum information (e.g., qubit information, quantum state information, etc.) in the second oscillation mode of the first superconducting qubit (104a) and the second superconducting qubit (104b), and said second oscillation mode may include a data mode.

[0059] In the embodiment shown in FIG. 2a and 2b, the superconducting bus resonator (102) may be coupled to the first superconducting qubit (104a) and the second superconducting qubit (104b) based on a first oscillation mode structure (124a) corresponding to a first oscillation mode of the first superconducting qubit (104a) and the second superconducting qubit (104b) (e.g., thus), and the first oscillation mode may include a coupled mode. In the embodiments shown in FIG. 2a and 2b, a second oscillation mode structure (124b) corresponding to a second oscillation mode of a first superconducting qubit (104a) and a second superconducting qubit (104b) can enable encoding and / or storing quantum information (e.g., qubit information, quantum state information, etc.) in the second oscillation mode of the first superconducting qubit (104a) and the second superconducting qubit (104b), and said second oscillation mode may include a data mode.

[0060] In the embodiment shown in FIG. 2a and 2b, by coupling a superconducting bus resonator (102) to the first superconducting qubit (104a) and the second superconducting qubit (104b) based on a first oscillation mode structure (124a) corresponding to the first oscillation mode (e.g., thus) and encoding and / or storing quantum information in the second oscillation mode of the first superconducting qubit (104a) and the second superconducting qubit (104b), the device (200a) can thereby facilitate the suppression (e.g., erasure, reduction, etc.) of direct interactions between the second oscillation mode of the first quantum qubit (104a) and the second oscillation mode of the second quantum qubit (104b). For example, in this embodiment, the device (200a) can facilitate the suppression (e.g., cancellation, reduction, etc.) of direct interactions, such as exchange interactions and / or static ZZ interactions, between, for example, the first superconducting qubit (104a) and the second superconducting qubit (104b) (e.g., between the second oscillation mode of the first superconducting qubit (104a) and the second oscillation mode of the second superconducting qubit (104b). In this embodiment, the device (200a) can facilitate the suppression of static ZZ interactions between the second oscillation mode of the first superconducting qubit (104a) and the second oscillation mode of the second superconducting qubit (104b). This is because there are higher-order interactions (e.g., Data Mode 1 → Coupled Mode 1 → Bus Resonator → Coupled Mode 2 → Data Mode 2). For example, higher-order interactions can be expressed as follows. That is, data mode 1 (e.g., second oscillation mode of the first superconducting qubit (104a)) → coupling mode 1 (e.g., first oscillation mode of the first superconducting qubit (104a)) → bus resonator (e.g., superconducting bus resonator (102)) → coupling mode 2 (e.g., first oscillation mode of the second superconducting qubit (104b)) → data mode 2 (second oscillation mode of the second superconducting qubit (104b)).

[0061] In the embodiment shown in FIG. 2a and 2b, by coupling a superconducting bus resonator (102) to the first superconducting qubit (104a) and the second superconducting qubit (104b) based on (e.g., thus) a first oscillation mode structure (124a) corresponding to the first oscillation mode, and encoding and / or storing quantum information in the second oscillation mode of the first superconducting qubit (104a) and the second superconducting qubit (104b), the device (200a) can thereby more facilitate a strong (e.g., relatively strong) longitudinal coupling between the first oscillation mode and the second oscillation mode of the first superconducting qubit (104a) and the second superconducting qubit (104b) (e.g., between the first oscillation mode structure (124a) and the second oscillation mode structure (124b). In this embodiment, such strong (e.g., relatively strong) longitudinal coupling between the first oscillation mode and the second oscillation mode of the first superconducting qubit (104a) and the second superconducting qubit (104b) (e.g., between the first oscillation mode structure (124a) and the second oscillation mode structure (124b)) can enable net longitudinal coupling between the superconducting bus resonator (102) and the second oscillation mode of the first superconducting qubit (104a) and the second superconducting qubit (104b). In this embodiment, this net longitudinal coupling between the superconducting bus resonator (102) and the second oscillation mode of the first superconducting qubit (104a) and the second superconducting qubit (104b) (which is also referred to as the chi shift (chi_01 shift)) can enable the generation and / or execution of two qubit entanglement gates through a resonator-induced phase (RIP) by driving the superconducting bus resonator (102) in a detuned state from its resonant frequency (e.g., 4 GHz) (e.g., through microwave pulses).

[0062] Also, or alternatively, in the embodiment shown in FIGS. 2a and 2b, the device (200a) may further prevent exchange coupling between data modes and the superconducting bus resonator (102), which may protect such data modes from energy loss associated with the superconducting bus resonator (102) (e.g., Purcell loss) (e.g., internal energy propagation to an external environment or energy loss to the device (200a) through a drive port near the superconducting bus resonator (102). For example, in the embodiment shown in FIGS. 2a and 2b, the device (200a) may prevent exchange coupling between the superconducting bus resonator (102) and the second oscillation mode of the first superconducting qubit (104a), and / or exchange coupling between the superconducting bus resonator (102) and the second oscillation mode of the second superconducting qubit (104b). In this embodiment, by preventing such exchange coupling between these data modes and the superconducting bus resonator (102) as described above, the device (200a) can thereby facilitate the reduction of Purcell loss and / or decoherence associated with the device (100a) and / or one or more components of the device (100a) (e.g., superconducting bus resonator (102), first superconducting qubit (104a), second superconducting qubit (104b), etc.).

[0063] As described above with reference to FIGS. 1a and 1b, various embodiments of the subject matter of the invention described herein (e.g., device (100a), device (200a), device (300), etc.) may be coupled to one or more external devices (not shown in FIG. 2a or 2b) to facilitate the operation of these embodiments. For example, referring to the embodiment shown in FIG. 2a and 2b, device (200a), superconducting bus resonator (102), first superconducting qubit (104a), and / or second superconducting qubit (104b) may be coupled to one or more external devices—such as, for example, a pulse generator device, an electric power source, and / or a magnetic field generator—which may be located outside of device (100a).

[0064] In one embodiment, although not illustrated in FIG. 2a or 2b, the device (200a), the superconducting bus resonator (102), the first superconducting qubit (104a), and / or the second superconducting qubit (104b) may be coupled to a pulse generator device (e.g., AWG, VNA, etc.). The pulse generator device may be located outside the device (200a) and may transmit pulses (e.g., microwave pulses, microwave signals, control signals, etc.) to the device (200a), the superconducting bus resonator (102), the first superconducting qubit (104a), and / or the second superconducting qubit (104b) and / or receive pulses (e.g., microwave pulses, microwave signals, control signals, etc.) from them. In another embodiment, although not illustrated in FIG. 2a or 2b, the device (200a), superconducting bus resonator (102), first superconducting qubit (104a), and / or second superconducting qubit (104b) may be coupled to an electric power source and / or magnetic field generator. Such electric power source and / or magnetic field generator may be located outside the device (200a) and may supply an electric current, an electric potential, and / or a magnetic field to the device (200a), superconducting bus resonator (102), first superconducting qubit (104a), and / or second superconducting qubit (104b).

[0065] In the above embodiments, one or more of these external devices (e.g., pulse generator devices (e.g., AWG, VNA, etc.), electric power sources, and / or magnetic field generators) may also be coupled to a computer (computer (1012) described below with reference to FIG. 10) comprising a memory (e.g., system memory (1016) described below with reference to FIG. 10) and a processor (e.g., processing unit (1014) described below with reference to FIG. 10). The memory may store instructions (e.g., software, routines, processing threads, etc.) therein, and the processor may execute such instructions that may be stored in the memory. In these embodiments, the computer may be used to operate and / or control one or more of these external devices (e.g., pulse generator devices (e.g., AWG, VNA, etc.), electric power sources, and / or magnetic field generators) (e.g., through a processing unit (1014) that executes instructions stored in the system memory (1016)). For example, in these embodiments, such a computer may be used to enable one or more external devices (e.g., pulse generator device (e.g., AWG, VNA, etc.), electric power source, and / or magnetic field generator) to a) transmit pulses (e.g., microwave pulses, microwave signals, control signals, etc.) to a device (200a), a superconducting bus resonator (102), a first superconducting qubit (104a), and / or a second superconducting qubit (104b) and / or receive pulses (e.g., microwave pulses, microwave signals, control signals, etc.) from them, and / or b) provide an electric current, an electric potential, and / or a magnetic field to the device (200a), the superconducting bus resonator (102), the first superconducting qubit (104a), and / or the second superconducting qubit (104b).

[0066] In various embodiments, an entity implementing the device (200a) as defined above with reference to FIGS. 1a and 1b may implement one or more of the mode-selective coupling schemes described herein (mode-selective coupling schemes described and shown in FIGS. 1a, 1b, 2a, 2b, and / or 3) according to one or more embodiments of the subject matter of the present invention. In these embodiments, such an entity may implement one or more of these mode-selective schemes by setting and / or adjusting one or more coupling capacitances between the superconducting bus resonator (102) and one or more superconducting pads of the first superconducting qubit (104a) and / or the second superconducting qubit (104b), so that one or more of such mode-selective schemes are achieved. In these embodiments, such an entity may set and / or adjust one or more of these coupled capacitances (e.g., the capacitor (228a) and / or the coupled capacitances of the capacitor (228b) of the device (200a) shown in FIG. 1b) by applying and / or adjusting a magnetic field, electric current, electric potential, and / or microwave pulse applied to the device (200a) and / or one or more components of the device (200a) (e.g., a superconducting bus resonator (102), a first superconducting qubit (104a), a second superconducting qubit (104b), etc.) (e.g., through one or more of the external devices defined above as described above and / or a computer (1012)).

[0067] In the embodiment shown in FIGS. 2a and 2b, the entity defined above can set and / or adjust the coupled capacitances represented by capacitor 228a and / or capacitor 228b in FIG. 2b by applying and / or adjusting a magnetic field, electric current, electric potential, and / or microwave pulse applied to the device (200a) and / or one or more components of the device (200a) (e.g., superconducting bus resonator (102), first superconducting qubit (104a), second superconducting qubit (104b), etc.) (e.g., through one or more of the external devices defined above and / or computer (1012) as described above). In this embodiment, based on setting and / or adjusting these coupling capacitances described above, the entity defined herein realizes the mode-selective coupling scheme described above by it, wherein the superconducting bus resonator (102) may be coupled to the first superconducting qubit (104a) and the second superconducting qubit (104b) based on (e.g., thus) a first oscillation mode structure (124a) corresponding to the first oscillation mode of the first superconducting qubit (104a) and the second superconducting qubit (104b)—the first oscillation mode includes a coupling mode—and / or quantum information (e.g., qubit information, quantum state information, etc.) may be coupled to the second oscillation mode of the first superconducting qubit (104a) and the second superconducting qubit (104b) based on (e.g., thus) a second oscillation mode of the first superconducting qubit (104a) and the second superconducting qubit (104b)—the second oscillation mode includes a data mode Can be encoded and / or stored.

[0068] In the above embodiment, based on realizing the mode-selective coupling scheme described above, the entity implementing the device (200a) thereby suppresses (eliminates, reduces, etc.) direct interactions such as exchange interactions and / or static ZZ interactions between, for example, the first superconducting qubit (104a) and the second superconducting qubit (104b) (e.g., between the second oscillation mode of the first superconducting qubit (104a) and the second oscillation mode of the second superconducting qubit (104b)—wherein the first oscillation mode and the second oscillation mode may include data modes of the first superconducting qubit (104a) and the second superconducting qubit (104b)—), b) between the first oscillation mode and the second oscillation mode of the first superconducting qubit (104a) and the second superconducting qubit (104b) (e.g., the first oscillation mode structure (124a) and This can facilitate strong (e.g., relatively strong) longitudinal coupling between the second oscillation mode structure (124b), and / or c) prevention of exchange coupling between the data modes and the superconducting bus resonator (102) (e.g., between the first oscillation mode and the second oscillation mode) - which can reduce energy loss (e.g., Purcell loss) and / or decoherence associated with the device (200a) and / or the superconducting bus resonator (102). In this embodiment, based on such suppression of these ZZ interactions associated with the superconducting bus resonator (102), reduction of energy loss, and / or reduction of decoherence, the device (200a) can thereby facilitate at least one of the reduction of quantum gate errors associated with the first superconducting qubit (104a) and / or the second superconducting qubit (104b), an increase in the speed of the quantum gate including the first superconducting qubit (104a) and the second superconducting qubit (104b), and / or an improvement in the fidelity, accuracy, or performance of the quantum processor including the device (200a).

[0069] In the above embodiment, the entity defined herein implementing the device (200a) may further drive the superconducting bus resonator (102) to a detuned state from its resonant frequency (e.g., 4 GHz) to generate and / or perform 2-qubit entanglement gates via a RIP gate (e.g., via microwave pulses using one or more of the external devices defined above and / or a computer (1012)). For example, in this embodiment, by driving the superconducting bus resonator (102) to a detuned state from its resonant frequency as described above, such an entity may entangle the first superconducting qubit (104a) and the second superconducting qubit (104b) (e.g., to generate an entanglement quantum gate between the first superconducting qubit (104a) and the second superconducting qubit (104b)). In this embodiment, such entanglement of the first superconducting qubit (104a) and the second superconducting qubit (104b) can enable quantum gate operations to be performed between the first superconducting qubit (104a) and the second superconducting qubit (104b). For example, in this embodiment, based on driving the superconducting bus resonator (102) in a state detuned from its resonant frequency, the device (200a) and / or the superconducting bus resonator (102) may operate as a RIP gate, which can generate ZZ interactions between a first qubit (e.g., a first superconducting qubit (104a)) and a second qubit (e.g., a second superconducting qubit (104b)) that exist when there is a microwave drive (e.g., a microwave pulse, a microwave signal, a control signal, etc.) in the superconducting bus resonator (102) (e.g., when there is a microwave signal applied to the superconducting bus resonator (102)).

[0070] FIG. 3 shows a plan view of one example (but not limited to) of a device (300) capable of facilitating static ZZ suppression and Purcell loss reduction using mode-selective coupling in two-junction superconducting qubits according to one or more embodiments described herein. Repetitive descriptions of similar components and / or processes used in each embodiment are omitted for brevity.

[0071] The device (300) may include an alternative embodiment of the device (200a) described above with reference to FIGS. 2a and 2b (but is not limited to such an example), wherein the first readout resonator (302a) (labeled R in FIG. 3) may be coupled to the first superconducting qubit (104a) and the second readout resonator (302b) (labeled R in FIG. 3) may be coupled to the second superconducting qubit (104b). For example, as shown in the embodiment illustrated in FIG. 3, the first readout resonator (302a) can be coupled (e.g., capacitively coupled) to the first superconducting pad (106a) of the first superconducting qubit (104a) through the first coupling pad (304a) of the device (300), and the second readout resonator (302b) can be coupled (e.g., capacitively coupled) to the first superconducting pad (106b) of the second superconducting qubit (104b) through the second coupling pad (304b) of the device (300). In the embodiment shown in FIG. 3, the first readout resonator (302a) and / or the second readout resonator (302b) can facilitate the readout of one or more types of information (e.g., quantum information, qubit information, quantum state information, etc.) from the device (300) (e.g., through one or more of the external devices defined above as described above and / or through a computer (1012) with reference to FIG. 1a-2b).

[0072] As shown in the embodiment illustrated in FIG. 3, the device (300) may further include a third coupling pad (304c) and / or a fourth coupling pad (304d). These may facilitate coupling (e.g., capacitive coupling) of one or more devices (not shown in the drawings) to the device (300) (e.g., coupling of one or more devices to the second superconducting pad (108a) of the first superconducting qubit (104a) and / or the second superconducting pad (108b) of the second superconducting qubit (104b)). In various embodiments, the first coupling pad (304a), the second coupling pad (304b), the third coupling pad (304c), and / or the fourth coupling pad (304d) may include a superconducting film (e.g., a superconducting metal film). Such superconducting films can be formed on a substrate (e.g., a silicon (Si) substrate, etc.) using one or more semiconductor and / or superconducting device manufacturing techniques described above with reference to FIGS. 1a and 1b.

[0073] FIG. 4 illustrates an example (but is not limited to) of a graph (400) that can facilitate static ZZ suppression and Purcell loss reduction using mode-selective coupling in two-junction superconducting qubits according to one or more embodiments described herein. Repetitive descriptions of similar components and / or processes used in each embodiment are omitted for brevity.

[0074] The graph (400) may include result data produced from implementing one or more embodiments of the subject matter of the present invention described herein. For example, the graph (400) may include result data produced from implementing the device (200a) according to one or more embodiments of the subject matter of the present invention described herein (e.g., computer implementation methods (700, 800, and / or 900) described below with reference to FIG. 7, 8, and 9, respectively) (e.g., simulating, quantizing, etc.).

[0075] In the embodiment shown in FIG. 4, the graph (400) may include a simulation represented by the number of ZZ interactions (e.g., static interactions are denoted as ZZ, and TCQ-TCQ, B modes in FIG. 4) between the second oscillation mode of the first superconducting qubit (104a) (indicated as TCQ 1 in FIG. 4) and the second oscillation mode of the second superconducting qubit (104b) (indicated as TCQ 2 in FIG. 4) as a function of the frequencies of the first superconducting qubit (104a) and the second superconducting qubit (104b). In this embodiment, the graph (400) may include a simulation represented by the number of these ZZ interactions described above, wherein quantum information (e.g., qubit information, quantum state information, etc.) may be encoded and / or stored in the second oscillation mode of the first superconducting qubit (104a) and the second superconducting qubit (104b) as described above with reference to FIGS. 2a and 2b (e.g., wherein the second oscillation mode includes the data mode of the first superconducting qubit (104a) and the second superconducting qubit (104b)). In this embodiment, the graph (400) may include a simulation represented by the number of these ZZ interactions described above, wherein the superconducting bus resonator (102) may be coupled only to the first oscillation mode of the first superconducting qubit (104a) and the second superconducting qubit (104b) (e.g., coupled only to the first oscillation mode structure (124a) corresponding to the first oscillation mode of both the first superconducting qubit (104a) and the second superconducting qubit (104b)).

[0076] As shown in one embodiment of the graph (400) illustrated in FIG. 4, the frequencies of the second oscillation mode of the first superconducting qubit (104a) are expressed in gigahertz (GHz) and are extended along the X-axis of the graph (400) (labeled as TCQ 1 fB (GHz) in FIG. 4), the frequencies of the second oscillation mode of the second superconducting qubit (104b) are expressed in GHz and are extended along the Y-axis of the graph (400) (labeled as TCQ 2 fB (GHZ) in FIG. 4), and the ZZ interaction frequencies are expressed in kilohertz (kHz) and are labeled as Log10(ZZ (kHz)) in FIG. 4, and are represented by various hatchings on the Z-axis of the graph (400) (e.g., the Z-axis of the graph (400) extends inward and outward from the ground) corresponding to the frequencies indicated in the ZZ legend shown in FIG. 4.

[0077] In the embodiment shown in FIG. 4, the graph (400) may include a simulation represented by the number of such ZZ interactions described above. Here, the capacitance of capacitor (228a) = the capacitance of capacitor (228b) = 10 femtofarads (fF), and the resonant frequency (fr) of the superconducting bus resonator (102) is 4 GHz. In this embodiment, the graph (400) may include a simulation of the ZZ interactions described above represented by a number, which can be obtained by varying the threshold current of the first superconducting qubit (104a) and the second superconducting qubit (104b) from about 20 nanoamperes (nA) to about 30 nA with a 5 percent (%) asymmetry between current I1 and current I2 for each of the first superconducting qubit (104a) and the second superconducting qubit (104b) (e.g., through one or more of the external devices defined above and / or a computer (1012) with reference to FIG. 1a and 1b). As shown in the graph (400) in FIG. 4, it should be understood that ZZ interactions (e.g., static ZZ interactions) between the second oscillation mode of the first superconducting qubit (104a) and the second oscillation mode of the second superconducting qubit (104b) are lower than 1 kHz when the device (200a) and / or device (300) is implemented according to the parameters defined above, and therefore, under these conditions, these ZZ interactions are suppressed, eliminated, and / or virtually non-existent.

[0078] FIG. 5 illustrates an example (but is not limited to) of a graph (500) that can facilitate static ZZ suppression and Purcell loss reduction using mode-selective coupling in two-junction superconducting qubits according to one or more embodiments described herein. Repetitive descriptions of similar components and / or processes used in each embodiment are omitted for brevity.

[0079] The graph (500) may include result data produced from implementing one or more embodiments of the subject matter of the present invention described herein. For example, the graph (500) may include result data produced from implementing the device (200a) and / or the device (300) according to one or more embodiments of the subject matter of the present invention described herein (e.g., computer implementation methods (700, 800, and / or 900) described below with reference to FIG. 7, 8, and 9, respectively) (e.g., simulating, quantizing, etc.).

[0080] In the embodiment shown in FIG. 5, the graph (500) may include a simulation represented by the number of the above-described net longitudinal couplings, referred to as the chi shift (indicated as chi01 in FIG. 5), between the superconducting bus resonator (102) and the second oscillation mode of the first superconducting qubit (104a) as a function of the frequencies of the first superconducting qubit (104a) and the second superconducting qubit (104b). In this embodiment, the graph (500) may include a simulation represented by the number of net longitudinal combinations (chi shifts) described above, wherein quantum information (e.g., qubit information, quantum state information, etc.) may be encoded and / or stored in the second oscillation mode of the first superconducting qubit (104a) and the second superconducting qubit (104b) as described above with reference to FIGS. 2a and 2b (e.g., wherein the second oscillation mode includes the data mode of the first superconducting qubit (104a) and the second superconducting qubit (104b)). In this embodiment, the graph (500) may include a simulation represented by the number of such net longitudinal couplings (chi shifts) described above, wherein the superconducting bus resonator (102) may be coupled only to the first oscillation mode of the first superconducting qubit (104a) and the second superconducting qubit (104b) (e.g., coupled only to the first oscillation mode structure (124a) corresponding to the first oscillation mode of both the first superconducting qubit (104a) and the second superconducting qubit (104b)).

[0081] As shown in one embodiment of the graph (500) illustrated in FIG. 5, the frequencies of the second oscillation mode of the first superconducting qubit (104a) are expressed in gigahertz (GHz) and are extended along the X-axis of the graph (500) (labeled as TCQ 1 fB (GHz) in FIG. 5), the frequencies of the second oscillation mode of the second superconducting qubit (104b) are expressed in GHz and are extended along the Y-axis of the graph (500) (labeled as TCQ 2 fB (GHZ) in FIG. 5), and the net longitudinal coupling (chi shift) frequencies are expressed in megahertz (MHz) and are labeled as chi01 (MHz) in FIG. 5, and are represented by various hatchings on the Z-axis of the graph (500) (e.g., the Z-axis of the graph (500) extends inward and outward from the ground) corresponding to the frequencies indicated in the chi01 legend shown in FIG. 5.

[0082] In the embodiment shown in FIG. 5, the graph (500) may include a simulation represented by the number of such net longitudinal coupling (chi shift) described above. Here, the capacitance of capacitor (228a) = the capacitance of capacitor (228b) = 10 femtofarads (fF), and the resonant frequency (fr) of the superconducting bus resonator (102) is 4 GHz. In this embodiment, the graph (500) may include a simulation represented by the number of such net longitudinal couplings (chi shifts) described above, which can be obtained by varying the threshold current of the first superconducting qubit (104a) and the second superconducting qubit (104b) from about 20 nanoamperes (nA) to about 30 nA with a 5 percent (%) asymmetry between current I1 and current I2 for each of the first superconducting qubit (104a) and the second superconducting qubit (104b) (e.g., through one or more of the external devices defined above and / or a computer (1012) with reference to FIG. 1a and 1b). As described above with reference to FIGS. 2a and 2b and illustrated by graph (500) in FIG. 5, although the device (200a) and / or device (300) may prevent exchange coupling between the superconducting bus resonator (102) and the second oscillation mode of the first superconducting qubit (104a) and the second superconducting qubit (104b), the device (200a) and / or device (300) may enable a large (e.g., relatively large) net longitudinal coupling (chi shift) between the superconducting bus resonator (102) and the second oscillation mode of the first superconducting qubit (104a).

[0083] FIG. 6 shows an example (but is not limited to) of a graph that can facilitate static ZZ suppression and Purcell loss reduction using mode-selective coupling in two-junction superconducting qubits according to one or more embodiments described herein. Repetitive descriptions of similar components and / or processes used in each embodiment are omitted for brevity.

[0084] The graph (600) may include result data produced from implementing one or more embodiments of the subject matter of the present invention described herein. For example, the graph (600) may include result data produced from implementing the device (200a) and / or the device (300) according to one or more embodiments of the subject matter of the present invention described herein (e.g., computer implementation methods (700, 800, and / or 900) described below with reference to FIG. 7, 8, and 9, respectively) (e.g., simulating, quantizing, etc.).

[0085] In the embodiment shown in FIG. 6, the graph (600) may include a simulation represented by the number of net longitudinal couplings described above, referred to as the chi shift (indicated as chi01 in FIG. 6), between the superconducting bus resonator (102) and the second oscillation mode of the first superconducting qubit (104a) as a function of the frequencies of the first superconducting qubit (104a) and the second superconducting qubit (104b). In this embodiment, the graph (600) may include a simulation represented by the number of net longitudinal combinations (chi shifts) described above, wherein quantum information (e.g., qubit information, quantum state information, etc.) may be encoded and / or stored in the second oscillation mode of the first superconducting qubit (104a) and the second superconducting qubit (104b) as described above with reference to FIGS. 2a and 2b (e.g., wherein the second oscillation mode includes the data mode of the first superconducting qubit (104a) and the second superconducting qubit (104b)). In this embodiment, the graph (600) may include a simulation represented by the number of such net longitudinal couplings (chi shifts) described above, wherein the superconducting bus resonator (102) may be coupled only to the first oscillation mode of the first superconducting qubit (104a) and the second superconducting qubit (104b) (e.g., coupled only to the first oscillation mode structure (124a) corresponding to the first oscillation mode of both the first superconducting qubit (104a) and the second superconducting qubit (104b)).

[0086] As shown in the embodiment of the graph (600) illustrated in FIG. 6, the frequencies of the second oscillation mode of the first superconducting qubit (104a) are expressed in gigahertz (GHz) and are extended along the X-axis of the graph (600) (labeled as TCQ 1 fB (GHz) in FIG. 6), the frequencies of the second oscillation mode of the second superconducting qubit (104b) are expressed in GHz and are extended along the Y-axis of the graph (600) (labeled as TCQ 2 fB (GHZ) in FIG. 6), and the net longitudinal coupling (chi shift) frequencies are expressed in megahertz (MHz) and are labeled as chi01 (MHz) in FIG. 6, and are represented by various hatchings on the Z-axis of the graph (600) (e.g., the Z-axis of the graph (600) extends inward and outward from the ground) corresponding to the frequencies indicated in the chi01 legend shown in FIG. 6.

[0087] In the embodiment shown in FIG. 6, the graph (600) may include a simulation represented by the number of such net longitudinal coupling (chi shift) described above. Here, the capacitance of capacitor (228a) = the capacitance of capacitor (228b) = 10 femtofarads (fF), and the resonant frequency (fr) of the superconducting bus resonator (102) is 4 GHz. In this embodiment, the graph (600) may include a simulation represented by the number of such net longitudinal couplings (chi shifts) described above, which can be obtained by varying the threshold current of the first superconducting qubit (104a) and the second superconducting qubit (104b) from about 20 nanoamperes (nA) to about 30 nA with a 5 percent (%) asymmetry between current I1 and current I2 for each of the first superconducting qubit (104a) and the second superconducting qubit (104b) (e.g., through one or more of the external devices defined above and / or a computer (1012) with reference to FIG. 1a and 1b). As described above with reference to FIGS. 2a and 2b and illustrated by graph (600) in FIG. 6, although the device (200a) and / or device (300) may prevent exchange coupling between the superconducting bus resonator (102) and the second oscillation mode of the first superconducting qubit (104a) and the second superconducting qubit (104b), the device (200a) and / or device (300) may enable large (e.g., relatively large) net longitudinal coupling (chi shift) between the superconducting bus resonator (102) and the second oscillation mode of the second superconducting qubit (104b).

[0088] Various embodiments of the subject matter of the present invention described herein (e.g., device (100a), device (200a), device (300), etc.) may be associated with various technologies. For example, various embodiments of the subject matter of the present invention described herein (e.g., device (100a), device (200a), device (300), etc.) may be associated with quantum computing technologies, quantum gate technologies, quantum coupler technologies, quantum hardware and / or software technologies, quantum circuit technologies, superconducting circuit technologies, machine learning technologies, artificial intelligence technologies, cloud computing technologies, and / or other technologies.

[0089] Various embodiments of the subject matter of the invention described herein (e.g., device (100a), device (200a), device (300), etc.) may provide technical advancements regarding systems, devices, components, operation steps, and / or processing steps associated with the various technologies identified above. For example, various embodiments of the subject matter of the invention described herein (e.g., device (100a), device (200a), device (300), etc.) may encode quantum information in a first oscillation mode of a first superconducting qubit and a second superconducting qubit, and / or may combine a superconducting bus resonator with an oscillation mode structure corresponding to a second oscillation mode of the first superconducting qubit and the second superconducting qubit.

[0090] Referring to the example above and the embodiment described above and illustrated in FIG. 1a and 1b, the device (100a) of the subject of the invention described herein, based on realizing the mode-selective coupling scheme described above, can facilitate the suppression (e.g., elimination, reduction, etc.) of direct interactions such as exchange interactions and / or static ZZ interactions between, for example, a first superconducting qubit (104a) and a second superconducting qubit (104b) (e.g., between a first oscillation mode of the first superconducting qubit (104a) and a first oscillation mode of the second superconducting qubit (104b)—wherein the first oscillation mode and the second oscillation mode may include data modes of the first superconducting qubit (104a) and the second superconducting qubit (104b)—). In this example, based on realizing the mode-selective coupling scheme described above, the device (100a) may also facilitate strong (e.g., relatively strong) longitudinal coupling between the first oscillation mode and the second oscillation mode of the first superconducting qubit (104a) and the second superconducting qubit (104b) (e.g., between the first oscillation mode structure (124a) and the second oscillation mode structure (124b). In this example, based on realizing the mode-selective coupling scheme described above, the device (100a) may also facilitate the prevention of exchange coupling between the data modes and the superconducting bus resonator (102) (e.g., between the first oscillation mode and the second oscillation mode), which may reduce energy loss (e.g., Purcell loss) and / or decoherence associated with the device (200a) and / or the superconducting bus resonator (102).In this example, based on such suppression of these ZZ interactions associated with the superconducting bus resonator (102), reduction of energy loss, and / or reduction of decoherence, the device (100a) can thereby facilitate at least one of the reduction of quantum gate errors associated with the first superconducting qubit (104a) and / or the second superconducting qubit (104b), an increase in the speed of the quantum gate including the first superconducting qubit (104a) and the second superconducting qubit (104b), and / or an improvement in the fidelity, accuracy, or performance of the quantum processor including the device (100a).

[0091] Various embodiments of the subject matter of the invention described herein (e.g., device (100a), device (200a), device (300), etc.) may provide technical enhancements to a processing unit (e.g., quantum processor, quantum hardware, superconducting circuit, etc., including device (100a), device (200a), device (300), etc.) associated with a classical computing device and / or quantum computing device (e.g., quantum processor, quantum hardware, superconducting circuit, etc.) that may be associated with one or more of the various embodiments of the subject matter of the invention described herein (e.g., device (100a), device (200a), device (300), etc.). For example, by realizing the mode-selective coupling scheme described above, device (100a) may facilitate such suppression of these static ZZ interactions associated with the superconducting bus resonator (102), reduction of energy loss, and / or reduction of decoherence. In this example, by suppressing these ZZ interactions associated with the superconducting bus resonator (102), reducing these energy losses, and / or reducing these decoherences, the device (100a) can thereby facilitate a reduction in quantum gate errors associated with the first superconducting qubit (104a) and / or the second superconducting qubit (104b), and / or an increase in the speed of a quantum gate (e.g., an entangled quantum gate) comprising the first superconducting qubit (104a) and the second superconducting qubit (104b). In this example, by reducing these quantum gate errors and / or increasing the speed of the quantum gate, the device (100a) can facilitate an improvement in fidelity, an improvement in accuracy, and / or an improvement in performance of a quantum processor comprising the device (100a).

[0092] Based on this suppression of ZZ interactions between the first oscillation mode of the first superconducting qubit (104a) and the first oscillation mode of the second superconducting qubit (104b) as described above, the practical application of the various embodiments of the subject of the invention described herein (e.g., device (100a), device (200a), device (300), etc.) can be implemented in a quantum device (e.g., quantum processor, quantum computer, etc.) to compute one or more solutions (e.g., heuristic(s), etc.) to various problems of high complexity (e.g., estimation problems, optimization problems, etc.) in various fields (e.g., finance, chemistry, medicine, etc.) faster and more efficiently with enhanced fidelity and / or accuracy. For example, based on this suppression of ZZ interactions between the first oscillation mode of the first superconducting qubit (104a) and the first oscillation mode of the second superconducting qubit (104b) as described above, practical application of one or more embodiments of the subject of the invention described herein (e.g., device (100a), etc.) is that they can be implemented, for example, in a quantum processor (e.g., a quantum processor including device (100a)) to compute one or more solutions (e.g., inferences, etc.) to optimization problems in the fields of chemistry, medicine and / or redefinition with enhanced fidelity and / or accuracy, and such solutions can be used to develop, for example, new chemical compounds, new medicines, and / or new options for pricing systems and / or methods.

[0093] It should be understood that the various embodiments of the subject matter of the invention described herein (e.g., device (100a), device (200a), device (300), etc.) provide a new approach driven by relatively new quantum computing technologies. For example, one or more embodiments of the subject matter of the invention described herein (e.g., device (100a), etc.) provide a new approach for suppressing ZZ interactions between the first oscillation mode of the first superconducting qubit (104a) and the first oscillation mode of the second superconducting qubit (104b), as described above—ZZ interactions eventually lead to quantum gate errors during quantum computations. In this example, this new approach for suppressing ZZ interactions can enable faster and more efficient quantum computations with enhanced fidelity and / or accuracy using a quantum processor comprising one or more of the various embodiments of the subject matter of the invention described herein (e.g., device (100a), etc.).

[0094] Various embodiments of the subject matter of the invention described herein (e.g., device (100a), device (200a), device (300), etc.) may utilize hardware or software to solve problems that are essentially very technical, non-abstract, and cannot be performed by a set of mental operations by humans. In some embodiments, one or more of the processes described herein may be performed by one or more dedicated computers (e.g., dedicated processing units, dedicated classical computers, dedicated quantum computers, etc.) to execute defined tasks related to the various technologies identified above. Various embodiments of the subject matter of the invention described herein (e.g., device (100a), device (200a), device (300), etc.) may be used to solve new problems arising from the use of advancements in the technologies mentioned above, quantum computing systems, cloud computing systems, computer architectures, and / or other technologies.

[0095] Since the various operations that can be performed by the various embodiments of the subject matter of the invention described herein (e.g., device (100a), device (200a), device (300), etc.) are operations greater than the capacity of the human mind, it is understood that the various embodiments of the subject matter of the invention described herein (e.g., device (100a), device (200a), device (300), etc.) may utilize various combinations of electrical components, mechanical components, and circuits that cannot be replicated in the human mind or performed by a human. For example, during a certain time interval, the amount of data processed, the speed at which such data is processed, or the type of data processed by the various embodiments of the subject matter of the invention described herein (e.g., device (100a), device (200a), device (300), etc.) may be greater, faster, or different from the amount, speed, or type of data that can be processed by the human mind during the same time interval.

[0096] According to some embodiments, various embodiments of the subject matter of the invention described herein (e.g., device (100a), device (200a), device (300), etc.) may be fully operated (e.g., fully powered on, fully executed, etc.) in a manner that performs one or more other functions while also performing the various operations described herein. It should be understood that such simultaneous multi-operation execution is beyond the capabilities of the human mind. It should also be understood that various embodiments of the subject matter of the invention described herein (e.g., device (100a), device (200a), device (300), etc.) may contain information that is impossible to obtain manually by an entity such as a human user. For example, the type, amount, and / or variety of information contained in device (100a), device (200a), device (300) may be more complex than information obtained manually by a human user.

[0097] FIG. 7 shows a flow diagram of one example (but not limited to) of a computer implementation method (700) that can facilitate static ZZ suppression and Purcell loss reduction using mode-selective coupling in two-junction superconducting qubits according to one or more embodiments described herein. Repetitive descriptions of similar components and / or processes used in each embodiment are omitted for brevity.

[0098] In 702, the computer implementation method (700) may include the step of encoding quantum information (e.g., qubit information, quantum state information, etc.) in a first oscillation mode (e.g., the first oscillation mode described above with reference to FIGS. 1a and 1b) of a first superconducting qubit (e.g., the first superconducting qubit (104a)) and a second superconducting qubit (e.g., the second superconducting qubit (104b)) by a system (e.g., a processing unit (1014) etc.) operatively coupled to a processor (e.g., a processing unit (1014) etc.) (e.g., a system including one or more types of the external devices defined above with reference to FIGS. 1a and 1b).

[0099] In 704, the computer implementation method (700) may include the step of coupling a superconducting bus resonator (e.g., superconducting bus resonator (102)) to an oscillation mode structure (e.g., second oscillation mode structure (124b)) corresponding to a second oscillation mode of a first superconducting qubit and a second superconducting qubit (e.g., second oscillation mode described above with reference to FIGS. 1a and 1b) by a system (e.g., a device (100a), a computer (1012), and / or a system including one or more types of external devices defined above with reference to FIGS. 1a and 1b).

[0100] FIG. 8 shows flow diagrams of an example (but not limited to) of a computer implementation method (800) that can facilitate static ZZ suppression and Purcell loss reduction using mode-selective coupling in two-junction superconducting qubits according to one or more embodiments described herein. Repetitive descriptions of similar components and / or processes used in each embodiment are omitted for brevity.

[0101] In 802, the computer implementation method (800) may include the step of encoding quantum information (e.g., qubit information, quantum state information, etc.) in a data mode (e.g., the first oscillation mode described above with reference to FIGS. 1a and 1b) of a first superconducting qubit (e.g., the first superconducting qubit (104a) and a second superconducting qubit (e.g., the second superconducting qubit (104b)) by a system operatively coupled to a processor (e.g., a processing unit (1014)), (e.g., a system including one or more types of external devices defined above with reference to FIGS. 1a and 1b).

[0102] In 804, the computer implementation method (800) may include the step of coupling a superconducting bus resonator (e.g., superconducting bus resonator (102)) to a coupling mode structure (e.g., second oscillation mode structure (124b)) corresponding to a coupling mode of a first superconducting qubit and a second superconducting qubit (e.g., the second oscillation mode described above with reference to FIGS. 1a and 1b) by a system (e.g., a device (100a), a computer (1012), and / or a system including one or more types of external devices defined above with reference to FIGS. 1a and 1b).

[0103] FIG. 9 shows flow diagrams of an example (but not limited to) of a computer implementation method (900) that can facilitate static ZZ suppression and Purcell loss reduction using mode-selective coupling in two-junction superconducting qubits according to one or more embodiments described herein. Repetitive descriptions of similar components and / or processes used in each embodiment are omitted for brevity.

[0104] In 902, the computer implementation method (900) may include the step of encoding quantum information (e.g., qubit information, quantum state information, etc.) in a first oscillation mode of a first superconducting qubit (e.g., the first superconducting qubit (104a)) and a second superconducting qubit (e.g., the first oscillation mode described above with reference to FIGS. 1a and 1b) (e.g., through a system including one or more types of the device (200a) or device (300), computer (1012), and / or external devices defined above with reference to FIGS. 1a and 1b).

[0105] In 904, the computer implementation method (900) may include the step of coupling a superconducting bus resonator (e.g., superconducting bus resonator (102)) to an oscillation mode structure (e.g., second oscillation mode structure (124b)) corresponding to a second oscillation mode of a first superconducting qubit and a second superconducting qubit (e.g., the second oscillation mode described above with reference to FIGS. 1a and 1b) (e.g., through a system including one or more types of the device (200a) or device (300), computer (1012), and / or external devices defined above with reference to FIGS. 1a and 1b).

[0106] In 906, the computer implementation method (900) may include the step of adjusting the critical currents of the first superconducting qubit and the second superconducting qubit (e.g., through a system including one or more types of the external devices defined above with reference to FIGS. 1a and 1b) as described above with reference to FIGS. 1a, 1b, 2a, 2b and 4, the entity defined herein implementing the device (200a) and / or device (300) may be set such that the capacitance of capacitor (228a) = the capacitance of capacitor (228b) = 10 femtofarads (fF), where the resonant frequency (fr) of the superconducting bus resonator (102) is 4 GHz. In this example, such an entity can adjust and / or vary the threshold current of the first superconducting qubit (104a) and the second superconducting qubit (104b) from about 20 nanoamperes (nA) to about 30 nA with a 5 percent (%) asymmetry between current I1 and current I2 for each of the first superconducting qubit (104a) and the second superconducting qubit (104b) (e.g., via one or more of the external devices defined above and / or a computer (1012) with reference to FIGS. 1a and 1b).

[0107] In 908, the computer implementation method (900) may include the step of determining whether ZZ interactions (e.g., static ZZ interactions) between the first oscillation mode of the first superconducting qubit and the first oscillation mode of the second superconducting qubit are suppressed (e.g., through a system including one or more types of the entities defined herein, device (200a) or device (300), computer (1012), and / or external devices described above with reference to FIGS. 1a and 1b). For example, referring to the example described above in operation 906, such an entity implementing device (200a) and / or device (300) according to the parameters defined above may use graph (400) to determine whether ZZ interactions (e.g., static ZZ interactions) between the second oscillation mode of the first superconducting qubit (104a) and the second oscillation mode of the second superconducting qubit (104b) are suppressed. In this example, when device (200a) and / or device (300) is implemented according to the parameters defined above, such an entity may use graph (400) to determine whether ZZ interactions (e.g., static ZZ interactions) between the second oscillation mode of the first superconducting qubit (104a) and the second oscillation mode of the second superconducting qubit (104b) are lower than 1 kHz. In this example, when the device (200a) and / or device (300) is implemented according to these parameters defined above, it should be understood that these ZZ interactions having frequency values ​​lower than 1 kHz are suppressed, eliminated, and / or virtually non-existent.

[0108] If it is determined in step 908 that ZZ interactions (e.g., static ZZ interactions) between the first oscillation mode of the first superconducting qubit and the first oscillation mode of the second superconducting qubit are suppressed, then in step 910, the computer implementation method (900) may include the step of performing an entanglement quantum gate between the first superconducting qubit and the second superconducting qubit (e.g., through a system including a device (200a) or a device (300), a computer (1012), and / or one or more types of external devices defined above with reference to FIGS. 1a and 1b). For example, as described above with reference to FIGS. 2a and 2b, the entity defined herein implementing the device (200a) may drive the superconducting bus resonator (102) in a detuned state from its resonant frequency (e.g., 4 GHz) to generate and / or perform 2-qubit entanglement gates (e.g., 2-qubit entanglement quantum gates) through RIP gates (e.g., via microwave pulses using one or more of the external devices defined herein and / or the computer (1012) as described above). In this example, by driving the superconducting bus resonator (102) in a state detuned from its resonant frequency as described above, this entity can entangle the first superconducting qubit (104a) and the second superconducting qubit (104) (e.g., to create an entanglement quantum gate between the first superconducting qubit (104a) and the second superconducting qubit (104b)). In this example, this entanglement of the first superconducting qubit (104a) and the second superconducting qubit (104b) can enable an entanglement quantum gate operation to be performed between the first superconducting qubit (104a) and the second superconducting qubit (104b).

[0109] If it is determined in 908 that ZZ interactions (e.g., static ZZ interactions) between the first oscillation mode of the first superconducting qubit and the first oscillation mode of the second superconducting qubit are suppressed, the computer implementation method (900) may include the step of returning to operation 906 to adjust the threshold current of the first superconducting qubit and the second superconducting qubit. In various embodiments, operations 906 and 908 of the computer implementation method (900) may be repeated until the ZZ interactions between the first oscillation mode of the first superconducting qubit and the first oscillation mode of the second superconducting qubit are suppressed (e.g., 1 kHz or less). In these embodiments, based on repeating operations 906 and 908 until the ZZ interactions between the first oscillation mode of the first superconducting qubit and the first oscillation mode of the second superconducting qubit are suppressed, the computer implementation method (900) may proceed to operation 910.

[0110] In order to provide context for various aspects of the subject matter of the present invention disclosed herein, FIG. 10, as well as the following discussion, is intended to provide a general description of a suitable environment in which various aspects of the subject matter of the present invention disclosed herein may be implemented. FIG. 10 shows a block diagram of an example of an operating environment (not limited to such examples) in which one or more embodiments described herein may be easily made. For example, as described below, the operating environment (1000) may be used to implement examples of multi-stage manufacturing sequences described above with reference to FIG. 1a and 1b (not limited to such examples) which may be implemented to manufacture a device (100a, 200a, and / or 300) according to one or more embodiments of the subject matter of the present invention as described herein. In another example, as described below, the operating environment (1000) may be used to implement one or more examples (but not limited to these examples) of the computer implementation methods (700, 800, and / or 900) described above with reference to FIGS. 7, 8, and 9, respectively. Repetitive descriptions of similar components and / or processes used in other embodiments described herein are omitted for brevity.

[0111] Examples of multi-stage manufacturing sequences described above with reference to FIGS. 1a and 1b (though not limited to such examples)—which may be implemented to manufacture a device (100a, 200a, and / or 300)—may be implemented by a computer system (e.g., the operating environment (1000) shown in FIG. 10 and described below) and / or a computing device (e.g., the computer (1012) shown in FIG. 10 and described below). In embodiments (though not limited to such embodiments), such a computing system (e.g., the operating environment (1000)) and / or such a computing device (e.g., the computer (1012)) may include one or more processors and one or more memory devices. The one or more memory devices may store executable instructions therein that can facilitate the execution of examples of multi-stage manufacturing sequences described above with reference to FIGS. 1a and 1b (but not limited to such examples) when executed by one or more processors. As one example (but not limited to such examples), the one or more processors may facilitate the execution of examples of multi-stage manufacturing sequences described above with reference to FIGS. 1a and 1b (but not limited to such examples) by directing and / or controlling one or more systems and / or equipment operable to perform semiconductor and / or superconductor device manufacturing.

[0112] In another example, with reference to FIGS. 7, 8, and 9, one or more of the examples (but not limited to these examples) of the computer implementation methods (700, 800, and / or 900) described above may also be implemented (e.g., executed) by the operating environment (1000). As an example (but not limited to such examples), one or more processors of such computing device (e.g., computer (1012)) may facilitate the execution of one or more examples (but not limited to such examples) of the computer implementation methods (700, 800, and / or 900) described above with reference to FIGS. 7, 8, and 9 by directing and / or controlling one or more systems and / or equipment (e.g., one or more of the external devices defined above with reference to FIGS. 1a and 1b) that are operable to perform operations and / or routines of such computer implementation methods(s).

[0113] For the sake of brevity, computer implementation methodologies are described and explained as a series of actions. It will be understood that the subject matter of the invention is not limited by the actions illustrated and / or by the order of the actions, for example, that actions may occur in different orders and / or simultaneously, and together with other actions not provided and described herein. Furthermore, not all of the illustrated actions may be required to implement computer implementation methodologies according to the subject matter of the invention. Also, those skilled in the art will understand and recognize that computer implementation methodologies may also be represented as a state diagram or as a series of correlated states through events. It should also be further understood that computer implementation methodologies disclosed thereafter and throughout this specification may be stored on articles of manufacture to facilitate transfer and transmission of such computer implementation methodologies to computers. As used herein, the term "article of manufacture" is intended to include a computer program accessible from any computer-readable device or storage medium.

[0114] Referring to FIG. 10, a suitable operating environment for implementing various aspects of the present invention may also include a computer (1012). The computer (1012) may also include a processing unit (1014), system memory (1016), and a system bus (1018). The system bus (1018) combines system components, including system memory (1016) (but not limited to this), with the processing unit (1014). The processing unit (1014) may be any of various available processors. Dual microprocessors and other multiprocessor architectures may also be used as the processing unit (1014). The system bus (1018) may be any of several types of bus structure(s), including a memory bus or memory controller, a peripheral bus or external bus, and / or a local bus, using any of various available bus architectures. The above available bus architectures may include, for example, Industrial Standard Architecture (ISA), Micro-Channel Architecture (MSA), Extended ISA (EISA), Intelligent Drive Electronics (IDE), VESA Local Bus (VLB), Peripheral Component Interconnect (PCI), Card Bus, Universal Serial Bus (USB), Advanced Graphics Port (AGP), Firewall (IEEE 1394), and Small Computer Systems Interface (SCSI), but are not limited to these examples.

[0115] System memory (1016) may also include volatile memory (1020) and non-volatile memory (1022). For example, a basic input / output system (BIOS) containing basic routines for moving information between components within the computer (1012), such as during startup, is stored in non-volatile memory (1022). The computer (1012) may also include removable / non-removable, volatile / non-volatile computer storage media. FIG. 10 illustrates, for example, disk storage (1024). Disk storage (1024) may also include devices such as magnetic disk drives, floppy disk drives, tape drives, Jazz drives, Zip drives, LS-100 drives, flash memory cards, or memory sticks, but is not limited to these examples. Disk storage (1024) may also include storage media independently or in combination with other storage media. To facilitate the connection of disk storage (1024) to the system bus (1018), a removable or non-removable interface, such as an interface (1026), is commonly used. FIG. 10 also illustrates software that acts as an intermediary between the users described in the appropriate operating environment (1000) and the basic computer resources. Such software may also include, for example, an operating system (1028). The operating system (1028) may be stored on the disk storage (1024) and operates to control and allocate the resources of the computer (1012).

[0116] System applications (1030) utilize the management of resources by the operating system (1028) through program modules (1032) and program data (1034) stored, for example, in either system memory (1016) or disk storage (1024). It should be understood that the present invention may be implemented by various operating systems or combinations of operating systems. A user inputs commands or information to the computer (1012) through input device(s) (1036). Input devices (1036) include, but are not limited to, pointing devices such as a mouse, trackball, stylus, touchpad, keyboard, microphone, joystick, gamepad, satellite dish, scanner, TV tuner card, digital camera, digital video camera, webcam, etc. These and other input devices are connected to the processing unit (1014) via the system bus (1018) through the interface port(s) (1038). Interface port(s) (1038) include, for example, a serial port, a parallel port, a game port, and a universal serial port (USB). Output device(s) (1040) use any of the same type of ports as input device(s) (1036). Thus, for example, a USB port may be used to provide input to the computer (1012) and to output information from the computer (1012) to the output device (1040). An output adapter (1042) is provided to indicate that there are some output devices, such as monitors, speakers, and printers, among other output devices (1040) that require special adapters. The output adapter (1042) includes video and sound cards that provide a means of connection between the output device (1040) and the system bus (1018), but this is for illustrative purposes only and is not limited to these.It should be noted that other devices and / or systems of devices provide both input and output functions, such as remote computer(s) (1044).

[0117] The computer (1012) may operate in a networked environment using logical connections to one or more remote computers, such as remote computer(s) (1044). The remote computer(s) (1044) may be a computer, server, router, network PC, workstation, microprocessor-based device, peer device, or other common network node, and may also include many or all of the components generally described in relation to a computer. For brevity of description, only the memory storage device (1046) is illustrated with the remote computer(s) (1044). The remote computer(s) (1044) are logically connected to the computer (1012) via a network interface (1048) and then physically connected via a communication connection (1050). The network interface (1048) includes wired and / or wireless networks such as local-area networks (LAN), wide-area networks (WAN), and cellular networks. LAN technologies include Fiber Distributed Data Interface (FDDI), Copper Distributed Data Interface (CDDI), Ethernet, Token Ring, etc. WAN technologies include, but are not limited to, Integrated Services Digital Networks (ISDN) and its variations, packet switching networks, and Digital Subscriber Lines (DSL). The communication connection(s) (1050) refers to hardware / software used to connect the network interface (1048) to the system bus (1018).For clarity of explanation, the communication connection (1050) is shown to be inside the computer (1012), but it may also be outside the computer (1012). Hardware / software for the connection to the network interface (1048) may also include internal and external technologies such as modems including standard telephone-grade modems, cable modems and DSL modems, ISDN adapters, Ethernet cards, etc., which are for illustrative purposes only.

[0118] The present invention may be a system, method, and / or computer program product at any possible level of technical detail of integration. The computer program product may include a computer-readable storage medium (or media). The computer-readable storage medium (or media) has computer-readable program instructions on the computer-readable storage medium (or media), and the computer-readable program instructions cause a processor to perform aspects of the present invention. The computer-readable storage medium may be a tangible device capable of holding and storing instructions for use by an instruction execution device. The computer-readable storage medium may be, for example, an electronic storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination thereof, but is not limited to these examples. A list of more specific examples of computer-readable storage media (not including all examples) may also include the following. That is, it may include portable computer diskettes, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), static random access memory (SRAM), portable compact disc read-only memory (CD-ROM), digital multi-purpose disc (DVD), memory sticks, floppy disks, mechanically encoded devices—e.g., punch-cards or structures convex in the grooves having instructions written in the grooves—and any suitable combination of these.As used herein, a computer-readable storage medium is not to be interpreted as the transient signals themselves, such as, for example, radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through waveguides or other transmission media (e.g., optical pulses passing through fiber optic cables), or electrical signals transmitted through wires.

[0119] The computer-readable program instructions described herein may be downloaded from a computer-readable storage medium to each computing / processing device, or to an external computer or external storage device, via a network such as, for example, the Internet, a local area network, a wide area network, and / or a wireless network. The network may include copper transmission cables, optical transmission fibers, wireless transmission, routers, firewalls, switches, gateway computers, and / or edge servers. A network adapter card or network interface at each computing / processing device receives computer-readable program instructions from the network and transmits the computer-readable program instructions to be stored on a computer-readable storage medium within each computing / processing device. Computer-readable program instructions for performing the operations of the present invention may be assembler instructions, instruction-set-architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, state-setting data, configuration data for an integrated circuit, or source code or object code written in any combination of one or more programming languages. The programming languages ​​include object-oriented programming languages ​​such as Smalltalk, C++, etc., and procedural programming languages ​​such as the "C" programming language or similar programming languages.Computer-readable program instructions can be executed entirely or partially on a user's computer as a stand-alone software package, partially on a user's computer and partially on a remote computer, or entirely on a remote computer or server. In the latter scenario, the remote computer may be connected to the user's computer via any type of network including a Local Area Network (LAN) or a Wide Area Network (WAN), or the connection may be made to an external computer (e.g., via the Internet using an Internet Service Provider). In some embodiments, to carry out aspects of the invention, electronic circuitry, for example, including programmable logic circuitry, field-programmable gate arrays (FPGA), or programmable logic arrays (PLA), may execute computer-readable program instructions by utilizing state information of the computer-readable program instructions to customize the electronic circuitry to an individual.

[0120] Aspects of the present invention are described herein with reference to flowchart descriptions and / or block diagrams of methods, apparatuses (systems), and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart descriptions and / or block diagrams, and combinations of blocks in the flowchart descriptions and / or block diagrams, may be implemented by computer-readable program instructions. These computer-readable program instructions may be provided to a processor of a general-purpose computer, a dedicated computer, or other programmable data processing unit to create a machine, and thus executed through the processor of the computer or other programmable data processing unit to create means for implementing the functions / operations specified in the blocks or blocks of the flowchart and / or block diagrams. These computer-readable program instructions may also be stored on a computer-readable storage medium, which may instruct a computer, a programmable data processing unit, and / or other devices to function in a particular manner. Thus, a computer-readable storage medium having instructions stored internally comprises a manufactured article containing instructions that implement aspects of functions / operations specified in blocks or blocks of a flowchart and / or block diagram. Computer-readable program instructions may also be loaded onto a computer, another programmable data processing unit, or another device to create a computer-implemented process by causing a series of operational steps to be performed on the computer, another programmable device, or other device. Thus, instructions executed on the computer, another programmable device, or other device implement functions / operations specified in blocks or blocks of a flowchart and / or block diagram.

[0121] In the drawings, flowcharts and block diagrams illustrate the architecture, functions, and operations of possible implementations of systems, methods, and computer program products according to various embodiments of the present invention. In this regard, each block in the flowcharts or block diagrams may represent a module, segment, or part of instructions, which includes one or more executable instructions for implementing the specified logical function(s). In some other implementations, the functions described in the blocks may occur out of the order described in the drawings. For example, two blocks shown in succession may be executed in fact, substantially simultaneously, depending on the related functions, or the blocks may sometimes be executed in reverse order. It will also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, may be implemented by dedicated hardware-based systems that perform the specified functions or operations or perform combinations of dedicated hardware and computer instructions.

[0122] Although the subject matter of the present invention has been described above in the general context of computer-executable instructions of computer program products executed on computers and / or on computers, those skilled in the art will recognize that the present invention may or may be implemented with other program modules. Generally, program modules include routines, programs, components, data structures, etc., which perform specific tasks and / or implement specific abstract data types. Furthermore, those skilled in the art will understand that the computer implementation methods of the present invention may be implemented with other computer system configurations, including not only computers but also single-processor or multi-processor computer systems, mini-computing devices, mainframe computers, handheld computing devices (e.g., PDAs, telephones), microprocessor-based or programmable consumer or industrial electronics, etc. The described aspects of the present invention may also be implemented in distributed computing environments where tasks are performed by remote processing devices connected via a communication network. However, although not all aspects of the invention, some may be executed on stand-alone computers. In a distributed computing environment, program modules may be located on both local memory storage devices and remote memory storage devices. For example, in one or more embodiments, computer-readable components may be executed from memory that may include or be composed of one or more distributed memory units. As used herein, the terms "memory" and "memory unit" are interchangeable.Furthermore, one or more embodiments described herein may execute code of computer executable components in a distributed manner, for example, on multiprocessors that are combined or work together to execute code from one or more distributed memory units. As used herein, the term “memory” may include a single memory or memory unit at one location, or multiple memories or memory units at one or more locations.

[0123] As used herein, terms such as “component,” “system,” “platform,” “interface,” etc., may refer to and / or include computer-related entities or entities associated with a machine of operation having one or more specific functions. The entities disclosed herein may be hardware, a combination of hardware and software, software, or software in execution. For example, a computer may be a process running on a processor, a processor, an object, an executable file, an execution thread, a program, and / or a computer, but is not limited thereto. For example, both an application running on a server and the server itself may be components. One or more components may reside within a process and / or a thread of execution, and components may be localized on a single computer and / or distributed across two or more computers. In another example, each component may be executed from various computer-readable media having various data structures stored internally. Components may communicate through local and / or remote processes, such as by following a signal having one or more data packets (e.g., data from one component interacting with another component across a network such as the Internet and other systems via signals in a local system or a distributed system, and / or via signals). As another example, a component may be a device having a specific function provided by mechanical parts operated by an electrical or electronic circuit, which is operated by a software or firmware application executed by a processor. In this case, the processor may be inside or outside the device and may execute at least part of the software or firmware application.As another example, the component may be a device that provides a specific function through electronic components without mechanical parts, wherein the electronic components may include a processor or other means for executing software or firmware that provides at least a part of the function of the electronic components. In one aspect, the component may emulate the electronic components through a virtual machine, for example, within a cloud computing system.

[0124] Furthermore, the term “or” is intended to mean an inclusive “or” rather than an exclusive “or.” That is, unless otherwise specified or is not evident from the context, it is intended to mean any of the natural inclusive permutations of “X uses A or B.” In other words, if X uses A, X uses B, or X uses both A and B, then “X uses A or B” is satisfied under any of the aforementioned examples. Moreover, “one” and “one” as used in this specification and the accompanying drawings should generally be interpreted to mean “one or more” unless otherwise specified or it is not evident from the context that they refer to the singular form. As used herein, the terms “example” and / or “exemplary” are used to mean providing an example, case, or illustration. To avoid doubt, the subject matter of the invention disclosed herein is not limited to such examples. Furthermore, any aspect or design described herein as “example” and / or “exemplary” must not be interpreted as meaning that it is necessarily preferred or advantageous over another aspect or design, nor does it mean that it excludes equivalent exemplary structures and technologies known to those skilled in the art.

[0125] As used herein, the term “processor” may generally refer to any computing processing unit or device, such computing processing unit or device may include, but is not limited to, single-core processors, single processors with software multithreaded execution capabilities, multi-core processors, multi-core processors with software multithreaded execution capabilities, multi-core processors with hardware multithreaded technology, parallel platforms, and parallel platforms with distributed shared memory. Additionally, a processor may refer to an integrated circuit, an application-specific integrated circuit (ASIC), a digital signal processor (DSP), a field programmable gate array (FPGA), a programmable logic controller (PLC), a complex programmable logic device (CPLD), discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. Furthermore, processors may utilize nanoscale architectures, such as molecular and quantum-dot-based transistors, switches, and gates, to optimize space usage or enhance the performance of user equipment. Processors may also be implemented as a combination of computing processing units.In this specification, the terms “store,” “storage,” “data store,” “data storage,” “database,” and any other information storage component associated with the operation and function of the component are used to refer to “memory components,” entities implemented within “memory,” or components comprising memory. It is understood that the memory and / or memory components described herein may be either volatile memory or non-volatile memory, or may include both volatile memory and non-volatile memory. For example, non-volatile memory may include, but is not limited to, read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically eraseable ROM (EEPROM), flash memory, or non-volatile random access memory (RAM) (e.g., ferroelectric RAM (FeRAM)). Volatile memory may include, for example, RAM, which may operate as an external cache memory. For example, RAM may be available in various forms such as synchronous RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), enhanced SDRAM (ESDRAM), synchlink DRAM (SLDRAM), direct Rambus RAM (DRRAM), direct Rambus dynamic RAM (DRADRAM), and Rambus dynamic RAM (RDRAM), but is not limited to these examples. Furthermore, the disclosed memory components of the systems or computer implementation methods herein are intended to include these and any other suitable types of memory, but are not necessarily limited to including them.

[0126] The above description includes simple examples of systems and computer implementation methods. Of course, it is not possible to determine all conceivable combinations of components or computer implementation methods for the purpose of describing the present invention, but a person skilled in the art will know that many other combinations and permutations of the present invention are functional. Furthermore, insofar as terms such as “include,” “have,” and “have” are used in the detailed description, claims, and drawings, these terms are intended to be comprehensive in a manner similar to the term “included,” as is interpreted when used as a transitional word in a claim.

[0127] Descriptions of various embodiments have been provided for illustrative purposes, but it is not intended to encompass all embodiments of the invention or to limit it to the disclosed embodiments. Without departing from the scope and spirit of the described embodiments, many modifications and variations will be obvious to those skilled in the art. The terms used herein have been chosen to best explain the principles, practical applications, or technical improvements of the embodiments compared to technologies found in the market, or to enable those skilled in the art to understand the embodiments described herein.

Claims

Claim 1 A device comprising a superconducting bus resonator; a first superconducting qubit; and a second superconducting qubit, wherein the first superconducting qubit and the second superconducting qubit each comprise a first superconducting pad; a second superconducting pad; a third superconducting pad; and a first Josephson junction coupled to the first superconducting pad and the second superconducting pad. A device comprising a second Josephson junction coupled to the second superconducting pad and the third superconducting pad, wherein the first superconducting pad and the second superconducting pad of the first superconducting qubit and the second superconducting qubit are coupled to the superconducting bus resonator, and the superconducting bus resonator entangles the first superconducting qubit and the second superconducting qubit based on receiving a control signal. Claim 2 A device according to claim 1, wherein the first superconducting qubit operates in a first oscillating mode and a second oscillating mode. Claim 3 In claim 1, the second superconducting qubit is a device that operates in a first oscillation mode and a second oscillation mode. Claim 4 A device according to any one of claims 1 to 3, wherein at least one of the first superconducting qubit and the second superconducting qubit comprises at least one of a tunable coupler qubit, a two junction qubit, a multimode qubit, a multimode two junction qubit, and a tunable qubit. Claim 5 A device according to any one of claims 1 to 3, wherein the first superconducting pad and the second superconducting pad of the first superconducting qubit and the second superconducting qubit are coupled to the superconducting bus resonator to suppress ZZ interactions between the first superconducting qubit and the second superconducting qubit and to reduce energy loss associated with the superconducting bus resonator, thereby facilitating at least one of the reduction of quantum gate errors associated with at least one of the first superconducting qubit and the second superconducting qubit, the increase in the speed of the quantum gate including the first superconducting qubit and the second superconducting qubit, and the improvement of fidelity, accuracy, and performance of the quantum processor including the device. Claim 6 A device comprising: a superconducting bus resonator; a first superconducting qubit; and a second superconducting qubit, wherein the first superconducting qubit and the second superconducting qubit each comprise: a first superconducting pad; a second superconducting pad; a third superconducting pad; a first Josephson junction coupled to the first superconducting pad and the second superconducting pad; and a second Josephson junction coupled to the second superconducting pad and the third superconducting pad, wherein the second superconducting pad of the first superconducting qubit and the second superconducting qubit is coupled to the superconducting bus resonator, and the superconducting bus resonator entangles the first superconducting qubit and the second superconducting qubit based on receiving a control signal. Claim 7 In claim 6, the device wherein the first superconducting qubit operates in a first oscillation mode and a second oscillation mode. Claim 8 In claim 6, the device wherein the second superconducting qubit operates in a first oscillation mode and a second oscillation mode. Claim 9 A device according to any one of claims 6 to 8, wherein at least one of the first superconducting qubit and the second superconducting qubit comprises at least one of a tunable coupler qubit, a two-junction qubit, a multimode qubit, a multimode two-junction qubit, and a tunable qubit. Claim 10 A device according to any one of claims 6 to 8, wherein the second superconducting pad of the first superconducting qubit and the second superconducting pad of the second superconducting qubit are coupled to the superconducting bus resonator to suppress ZZ interactions between the first superconducting qubit and the second superconducting qubit and to reduce energy loss associated with the superconducting bus resonator, thereby facilitating at least one of the reduction of quantum gate errors associated with at least one of the first superconducting qubit and the second superconducting qubit, an increase in the speed of a quantum gate including the first superconducting qubit and the second superconducting qubit, and an improvement in fidelity, an improvement in accuracy, and an improvement in performance of a quantum processor including the device. Claim 11 A device according to claim 1 or 6, wherein the first superconducting qubit and the second superconducting qubit operate in a first oscillation mode, and the superconducting bus resonator is coupled to an oscillation mode structure corresponding to the second oscillation mode of the first superconducting qubit and the second superconducting qubit. Claim 12 In claim 11, the device comprises at least one of the first superconducting qubit and the second superconducting qubit, wherein the device comprises at least one of a tunable coupler qubit, a two-junction qubit, a multimode qubit, a multimode two-junction qubit, and a tunable qubit. Claim 13 A device according to claim 11, wherein the first oscillation mode and the second oscillation mode represent symmetric and antisymmetric combinations of excitations associated with the first Josephson junction and the second Josephson junction of the first superconducting qubit and the second superconducting qubit. Claim 14 A device according to claim 11, wherein at least one of the first oscillation mode and the second oscillation mode comprises at least one of a data mode and a combined mode. Claim 15 A device according to claim 11, wherein the first superconducting qubit and the second superconducting qubit operate in the first oscillation mode and the superconducting bus resonator is coupled to the oscillation mode structure corresponding to the second oscillation mode, so as to suppress ZZ interactions between the first superconducting qubit and the second superconducting qubit and reduce energy loss associated with the superconducting bus resonator, thereby facilitating at least one of the reduction of quantum gate errors associated with at least one of the first superconducting qubit and the second superconducting qubit, the increase in speed of the quantum gate including the first superconducting qubit and the second superconducting qubit, and the improvement of fidelity, accuracy, and performance of the quantum processor including the device. Claim 16 A computer-implemented method comprising: encoding quantum information in a first oscillating mode of a first superconducting qubit and a second superconducting qubit by means of a system operatively coupled to a processor; and coupling a superconducting bus resonator to an oscillating mode structure corresponding to a second oscillating mode of the first superconducting qubit and the second superconducting qubit by means of the system, wherein the first superconducting qubit, the second superconducting qubit and the superconducting bus resonator are included in a device according to claim 1 or 6. Claim 17 In paragraph 16, the computer implementation method wherein the first superconducting qubit operates in the first oscillation mode and the second oscillation mode. Claim 18 In paragraph 16, the computer implementation method wherein the second superconducting qubit operates in the first oscillation mode and the second oscillation mode. Claim 19 A computer-implemented method according to claim 16, wherein at least one of the first superconducting qubit and the second superconducting qubit comprises at least one of a tunable coupler qubit, a two-junction qubit, a multimode qubit, a multimode two-junction qubit, and a tunable qubit. Claim 20 In claim 16, the computer implementation method further comprises the step of encoding the quantum information in the first oscillation mode of the first superconducting qubit and the second superconducting qubit by the system; and the step of coupling the superconducting bus resonator to the oscillation mode structure corresponding to the second oscillation mode of the first superconducting qubit and the second superconducting qubit by the system, thereby suppressing ZZ interactions between the first superconducting qubit and the second superconducting qubit and reducing energy loss associated with the superconducting bus resonator, thereby facilitating at least one of the reduction of quantum gate errors associated with at least one of the first superconducting qubit and the second superconducting qubit, the increase in speed of the quantum gate including the first superconducting qubit and the second superconducting qubit, and the improvement in fidelity, the improvement in accuracy, and the improvement in performance of the quantum processor including the first superconducting qubit, the second superconducting qubit and the superconducting bus resonator. Claim 21 A computer implementation method comprising: encoding quantum information in a data mode of a first superconducting qubit and a second superconducting qubit by means of a system operatively coupled to a processor; and coupling a superconducting bus resonator to a coupling mode structure corresponding to a coupling mode of the first superconducting qubit and the second superconducting qubit by means of said system, wherein the first superconducting qubit, the second superconducting qubit and the superconducting bus resonator are included in a device according to claim 1 or 6. Claim 22 A computer implementation method according to claim 21, wherein the first superconducting qubit operates in the data mode and the combined mode. Claim 23 A computer implementation method according to claim 21, wherein the second superconducting qubit operates in the data mode and the combined mode. Claim 24 A computer-implemented method according to claim 21, wherein at least one of the first superconducting qubit and the second superconducting qubit comprises at least one of a tunable coupler qubit, a two-junction qubit, a multimode qubit, a multimode two-junction qubit, and a tunable qubit. Claim 25 In claim 21, the computer implementation method further comprises the step of encoding the quantum information in the data mode of the first superconducting qubit and the second superconducting qubit by the system; and the step of coupling the superconducting bus resonator to the coupling mode structure corresponding to the coupling mode of the first superconducting qubit and the second superconducting qubit by the system, thereby suppressing ZZ interactions between the first superconducting qubit and the second superconducting qubit and reducing energy loss associated with the superconducting bus resonator, thereby facilitating at least one of the reduction of quantum gate errors associated with at least one of the first superconducting qubit and the second superconducting qubit, the increase in speed of the quantum gate including the first superconducting qubit and the second superconducting qubit, and the improvement in fidelity, the improvement in accuracy, and the improvement in performance of the quantum processor including the first superconducting qubit, the second superconducting qubit, and the superconducting bus resonator.

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