A multi-tier memory device having a central staircase region of different widths in different vertical tiers and a method for forming the same

Abstract

The memory device includes an alternating stack of insulating layers and electrically conductive layers that are laterally spaced apart from each other along a second horizontal direction and extend laterally along a first horizontal direction through an inter-array region, a first memory array region, and a second memory array region that is laterally spaced apart from the first memory array region along a first horizontal direction by the inter-array region. Each electrically conductive layer within the alternating stack has a respective bridge region having a strip width along the second horizontal direction within the inter-array region, and the strip width of the uppermost electrically conductive layer of the first tier alternating stack is less than the strip width of the uppermost electrically conductive layer of the second tier alternating stack placed on top of the first tier alternating stack.

Description

Technology Field

[0001] Cross-reference of related applications

[0002] This application claims the benefit of U.S. Regular Application No. 18 / 347,858, filed with the U.S. Patent and Trademark Office on July 6, 2023, titled "MULTI-TIER MEMORY DEVICE WITH DIFFERENT WIDTH CENTRAL STAIRCASE REGIONS IN DIFFERENT VERTICAL TIERS AND METHODS FOR FORMING THE SAME," which claims priority to U.S. Provisional Application No. 63 / 378,534 filed on October 6, 2022, and whose entire contents are incorporated herein by reference for all purposes.

[0003] Technology field

[0004] The present disclosure generally relates to the field of semiconductor devices, and in particular to a multi-tier memory device comprising a central step region of different widths of different vertical tiers and a method for forming the same. Background Technology

[0005] A 3D memory device comprising a 3D vertical NAND string with one bit per cell is described in the literature [T. Endoh et al It is disclosed in the paper titled "Novel Ultra High Density Memory With A Stacked-Surrounding Gate Transistor (S-SGT) Structured Cell", IEDM Proc. (2001) 33-36.

[0006] According to an embodiment of the present disclosure, a multi-tier memory device comprises a substrate and a plurality of tier structures located at a multi-tier level spaced vertically apart from the substrate by different vertical spacings. Each of the plurality of tier structures includes a rear trench fill structure that extends laterally through each of the plurality of tier structures along a first horizontal direction and is laterally spaced from each other along a second horizontal direction, an alternating stack of insulating layers and electrically conductive layers that extends laterally along a first horizontal direction through an inter-array region, a first memory array region, and a second memory array region that is laterally spaced from the first memory array region along a first horizontal direction by the rear trench fill structure, and a memory opening fill structure that extends vertically through each of the plurality of tier structures, and each of the memory opening fill structures includes a vertical stack of memory elements located at the level of each vertical semiconductor channel and electrically conductive layer. Each alternating stack includes a stepped surface of an inter-array region, and each electrically conductive layer within the alternating stack has a bridge region having a strip width along a second horizontal direction within the inter-array region, and each has a uniform width along the second horizontal direction that exceeds the strip width of the inter-array region portion located outside the first memory array region, the second memory array region, and the bridge region, and the strip width of the top electrically conductive layer of the first tier alternating stack is smaller than the strip width of the top electrically conductive layer of the second tier alternating stack placed on top of the first tier alternating stack.

[0007] According to another aspect of the present disclosure, a method for forming a semiconductor device comprises the step of forming a plurality of tier structures located at multi-tier levels vertically spaced from a substrate by different vertical spacings. Each of the plurality of tier structures includes an inter-array region, a first memory array region and an inter-array region, a second memory array region that is laterally spaced from the first memory array region along a first horizontal direction by the first memory array region and the inter-array region, an alternating stack of insulating layers and electrically conductive layers extending laterally along a first horizontal direction, and a memory opening fill structure extending vertically through each of the plurality of tier structures, and each of the memory opening fill structures includes a vertical stack of memory elements located at the level of each vertical semiconductor channel and sacrificial material layer. The method also includes the steps of forming a rear trench by penetrating an alternating stack of insulating layers and sacrificial material layers, converting the alternating stack of insulating layers and sacrificial material layers into an alternating stack of insulating layers and electrically conductive layers by replacing the sacrificial material layers through the rear trench, and filling the rear trench with rear trench fill structures that extend laterally through each of the plurality of tier structures along a first horizontal direction and are laterally spaced from each other along a second horizontal direction.The electrically conductive layers are laterally spaced from each other along the second horizontal direction by a rear trench fill structure, and each alternating stack of insulating layers and electrically conductive layers includes a stepped surface of an inter-array region, and each electrically conductive layer within the alternating stack of insulating layers and electrically conductive layers has a bridge region with a strip width along the second horizontal direction within the inter-array region, and has a uniform width along the second horizontal direction that exceeds the strip width of the inter-array region portion located outside the first memory array region, the second memory array region, and the bridge region, and the strip width of the uppermost electrically conductive layer of the first tier alternating stack of insulating layers and electrically conductive layers is smaller than the strip width of the uppermost electrically conductive layer of the second tier alternating stack of insulating layers and electrically conductive layers placed on top of the first tier alternating stack of insulating layers and electrically conductive layers. Brief explanation of the drawing

[0008] FIG. 1a is a plan view of an exemplary semiconductor die configuration including a plurality of three-dimensional memory array regions according to one embodiment of the present disclosure. FIG. 1b is a schematic perspective plan of the area (M1) of FIG. 1a. FIG. 1c is a schematic vertical cross-sectional view of an exemplary semiconductor die region along the vertical plane C-C' of FIG. 1b. FIG. 1d is a schematic vertical cross-sectional view of an exemplary semiconductor die region along the vertical plane D-D' of FIG. 1b. FIG. 1e is a schematic vertical cross-sectional view of an exemplary semiconductor die region along the vertical plane E-E' of FIG. 1b. FIG. 2a is a schematic vertical cross-sectional view of an exemplary structure for forming a semiconductor die after the formation of an optional semiconductor device, an optional lower-level dielectric layer, an optional lower metal interconnect structure, a semiconductor material layer, a first vertical alternating sequence of a first continuous insulating layer and a first continuous sacrificial material layer, and a first tier retro-stepped dielectric material portion, according to an embodiment of the present disclosure. FIG. 2b is a schematic vertical cross-sectional view of an exemplary structure along the vertical plane B-B' of FIG. 2a. FIG. 2c is another schematic vertical cross-sectional view of the exemplary structure of FIG. 2a and FIG. 2b. FIG. 3a is a schematic vertical cross-sectional view of an exemplary structure after the formation of a second vertical alternating sequence of a second continuous insulating layer and a second continuous sacrificial material layer, and a second tier inverse stepped dielectric material portion, according to one embodiment of the present disclosure. FIG. 3b is a schematic vertical cross-sectional view of an exemplary structure along the vertical plane B-B' of FIG. 3a. FIG. 3c is another schematic vertical cross-sectional view of the exemplary structure of FIG. 3a and FIG. 3b. FIG. 4a is a schematic vertical cross-sectional view of an exemplary structure after the formation of a third vertical alternating sequence of a third continuous insulating layer and a third continuous sacrificial material layer, and a third tier inverse stepped dielectric material portion, according to one embodiment of the present disclosure. FIG. 4b is a schematic vertical cross-sectional view of an exemplary structure along the vertical plane B-B' of FIG. 4a. FIGS. 5a to 5e are vertical cross-sectional views of various configurations of an exemplary structure after the formation of a third tier structure according to one embodiment of the present disclosure. FIGS. 6a through 6c are sequential vertical cross-sectional views of an exemplary structure during the formation of a tier-to-tier memory opening according to one embodiment of the present disclosure. FIGS. 7a through 7e illustrate sequential vertical cross-sectional views of a memory opening during the formation of a memory opening fill structure according to one embodiment of the present disclosure. FIGS. 8A and 8B are schematic vertical cross-sectional views of an exemplary structure after the formation of a memory opening fill structure and a rear trench according to one embodiment of the present disclosure. FIG. 8A is a schematic vertical cross-sectional view of an exemplary structure along the vertical plane B-B' of FIG. 8A. FIG. 9 is a schematic vertical cross-sectional view of an exemplary structure after the formation of a rear recess according to an embodiment of the present disclosure. FIG. 10a is a schematic vertical cross-sectional view of an exemplary structure after the formation of an electrically conductive layer according to an embodiment of the present disclosure. FIG. 10b is another schematic vertical cross-sectional view of the exemplary structure of FIG. 10a. FIGS. 11a to 11d are schematic vertical cross-sectional views of various configurations of the exemplary structure of FIGS. 10a and FIG. 10b. FIG. 11e is a schematic vertical cross-sectional view of another exemplary structure according to one embodiment of the present disclosure. Specific details for implementing the invention

[0009] As discussed above, embodiments of the present disclosure relate to a multi-tier memory device with a central stair region of different widths of different vertical tiers and a method for forming the same, and various aspects thereof are now described in detail.

[0010] The drawings are not drawn to scale. Unless the absence of overlapping elements is explicitly stated or clearly otherwise indicated, multiple instances of an element may overlap where a single instance of an element is depicted. Ordinal numbers such as "first," "second," and "third" are used merely to identify similar elements, and different ordinal numbers may be used throughout the specification and claims of this disclosure. The term "at least one" element refers to all possibilities including the possibility of a single element and the possibility of multiple elements.

[0011] Identical reference numerals denote identical or similar elements. Unless otherwise indicated, elements having the same reference numeral are presumed to have the same composition and the same function. Unless otherwise indicated, "contact" between elements refers to direct contact between elements that provide an edge or surface shared by the elements. Where two or more elements do not come into direct contact with each other or from each other, the two elements are "separated from" each other or "separated between" each other. As used herein, a first element located "on" a second element may be located on the outer side of the surface of the second element or on the inner side of the second element. As used herein, where physical contact exists between the surface of the first element and the surface of the second element, the first element is located "immediately above" the second element. As used herein, where a conductive path made of at least one conductive material exists between the first element and the second element, the first element is "electrically connected" to the second element. As used herein, a “prototype” structure or “in-process” structure refers to a temporary structure in which the shape or composition of at least one component therein is subsequently modified.

[0012] As used herein, “layer” refers to a portion of material comprising a region having thickness. The layer may extend over the entire structure placed below or above, or may have a range less than the range of the structure placed below or above. Additionally, the layer may be a region of a homogeneous continuous structure or a non-homogeneous continuous structure having a thickness less than the thickness of the first continuous structure. For example, the layer may be located between the top surface and the bottom surface of the first continuous structure, or between any pair of horizontal planes on the top surface and the bottom surface. The layer may extend horizontally, vertically, and / or along a tapered surface. The substrate may be a layer, may contain one or more layers within it, or may have one or more layers on, above, and / or below it.

[0013] As used herein, if a second surface lies on or under a first surface and there exists a vertical plane or substantially vertical plane comprising the first surface and the second surface, the first surface and the second surface "coincide perpendicularly" with each other. A substantially vertical plane is a plane that extends in a straight line along a direction that deviates from the vertical direction by an angle of less than 5 degrees. A vertical plane or substantially vertical plane is straight along the vertical direction or substantially vertical direction and may or may not include a curvature along a direction perpendicular to the vertical direction or substantially vertical direction.

[0014] As used herein, “memory level” or “memory array level” refers to a level corresponding to a general region between a first horizontal plane (i.e., a plane parallel to the top surface of the substrate) comprising the uppermost surface of the array of memory elements and a second horizontal plane comprising the lowermost surface of the array of memory elements. As used herein, a “through-stack” element refers to an element that extends vertically through the memory level.

[0015] As used herein, "semiconductor material" is 1.0 x 10 -5 S / m to 1.0 x 10 5 It refers to a material having electrical conductivity in the range of S / m. As used herein, "semiconductor material" refers to a material having 1.0 x 10⁻⁶ in the absence of an electrical dopant. -5 Refers to a material having electrical conductivity in the range of S / m to 1.0 S / m, and 1.0 S / m to 1.0 x 10⁻⁶ when suitablely doped using an electric dopant. 7 Doped materials having electrical conductivity in the range of S / m can be produced. As used herein, "electric dopant" refers to a p-type dopant that adds holes to the valence band within the band structure, or an n-type dopant that adds electrons to the conduction band within the band structure. As used herein, "conductive material" refers to 1.0 x 10⁻⁶ 5 It refers to a material having electrical conductivity greater than S / m. As used herein, "insulating material" or "dielectric material" refers to 1.0 x 10⁻⁶ -5 It refers to a material having electrical conductivity of less than S / m. As used herein, "highly doped semiconductor material" refers to a material that becomes a conductive material, i.e., 1.0 x 10⁻⁶, when formed as a crystalline material or converted into a crystalline material through an annealing process (e.g., from an initial amorphous state). 5It refers to a semiconductor material doped with an electrical dopant at a sufficiently high atomic concentration to provide electrical conductivity greater than S / m. "Doped semiconductor material" may be a highly doped semiconductor material, or 1.0 x 10⁻⁶ -5 S / m to 1.0 x 10 7 It may be a semiconductor material comprising an electric dopant (i.e., a p-type dopant and / or an n-type dopant) at a concentration that provides electrical conductivity in the S / m range. "Intrinsic semiconductor material" refers to a semiconductor material that is not doped with an electric dopant. Thus, the semiconductor material may be semiconductive or conductive, and may be an intrinsic semiconductor material or a doped semiconductor material. A doped semiconductor material may be semiconductive or conductive depending on the atomic concentration of the electric dopant within it. As used herein, "metallic material" refers to a conductive material containing at least one metallic element within it. All measurements of electrical conductivity are performed under standard conditions.

[0016] A monolithic three-dimensional memory array is formed by having multiple memory levels on a single substrate, such as a semiconductor wafer, without having an interposed substrate. The term “monolithic” means that the layer of each level of the array is deposited directly onto the layer of the level placed beneath each of the array. In contrast, two-dimensional arrays can be formed individually and then packaged together to form a non-monolithic memory device. For example, as described in U.S. Patent No. 5,915,167, titled “Three-dimensional Structure Memory,” a non-monolithic stacked memory is constructed by forming memory levels on separate substrates and stacking the memory levels vertically. The substrate may be removed or thinned from the memory levels before bonding, but because the memory levels are initially formed on separate substrates, such a memory is not a true monolithic three-dimensional memory array. The substrate may include integrated circuits manufactured thereon, such as driver circuits for the memory device.

[0017] Various three-dimensional memory devices of the present disclosure include monolithic three-dimensional NAND string memory devices and can be manufactured using various embodiments described in the present application. The monolithic three-dimensional NAND string is located in a monolithic three-dimensional array of NAND strings located on a substrate. At least one memory cell at a first device level of the three-dimensional array of NAND strings is located on another memory cell at a second device level of the three-dimensional array of NAND strings.

[0018] Generally, a semiconductor package (or "package") refers to a unit semiconductor device that can be attached to a circuit board via a set of pins or solder balls. A semiconductor package may include a semiconductor chip (or "chip") or multiple semiconductor chips joined together, for example, by a flip-chip junction or another chip-to-chip junction. A package or chip may include a single semiconductor die (or "die") or multiple semiconductor dies. A die is the smallest unit capable of independently executing external commands or reporting status. Typically, a package or chip having multiple dies can execute as many external commands simultaneously as the total number of dies within it. Each die includes one or more planes. The same simultaneous operation may be executed on each plane within the same die, although there may be some limitations. If the die is a memory die, that is, a die containing memory elements, simultaneous read, simultaneous write, or simultaneous erase operations may be performed on each plane within the same memory die. In a memory die, each plane contains multiple memory blocks (or "blocks"), which are the smallest units that can be erased in a single erase operation. Each memory block contains multiple pages, which are the smallest units that can be selected for programming. A page is also the smallest unit that can be selected for a read operation.

[0019] Referring to FIGS. 1a through 1e, an exemplary semiconductor die (1000) according to one embodiment of the present disclosure is illustrated. The exemplary semiconductor die (1000) includes a plurality of three-dimensional memory regions and a plurality of inter-array regions. The exemplary semiconductor die (1000) may include a plurality of planes (300) (e.g., 300A, 300B), each of which may include two memory array regions (100), such as a first memory region (100A) and a second memory array region (100B), which are laterally spaced apart by a respective inter-array region (200). Generally, the semiconductor die (1000) may include a single plane (300) or a plurality of planes. The total number of planes of the semiconductor die (1000) may be selected based on performance requirements for the semiconductor die (1000). A pair of memory array regions (100) of a plane (300) may be laterally spaced along a first horizontal direction (hd1) (which may be the word line direction). A second horizontal direction (hd2) (which may be the bit line direction) may be perpendicular to the first horizontal direction (hd1).

[0020] According to one aspect of the present disclosure, the size of the first memory array region (100A) may differ from the size of the second memory array region (100B) within a predetermined plane. Specifically, the lateral range of each of the first memory array region (100A) and the second memory array region (100B) may be the same along the second horizontal direction (hd2) within the plane. However, the lateral range of the first memory array region (100A) within the plane (300) along the first horizontal direction (hd1) may exceed the lateral range of the second memory array region (100B) within the same plane (300). In one embodiment, the first memory array area (100A) and the second memory array area (100B) may each have a rectangular area with the same width along the second horizontal direction (hd2), and the lateral range of the first memory array area (100A) along the second horizontal direction (hd2) may exceed the lateral range of the second memory array area (100B) along the first horizontal direction (hd1). Accordingly, the stepped area (200) within each plane (300) may be located off-center from each plane (300) along the first horizontal direction (hd1) (i.e., the stepped area (200) may be located closer to one end than to the other end of each plane (300). For example, the step area (200) of the left plane (300A) can be shifted toward the left edge of the die (1000), while the step area (200) of the right plane (300B) can be shifted toward the right edge of the die (1000).

[0021] Each memory array region (100) includes a first tier alternating stack of a first insulating layer (132) and a first electrically conductive layer (146) (functioning as a first word line), a second tier alternating stack of a second insulating layer (232) and a second electrically conductive layer (246) (functioning as a second word line), and a third tier alternating stack of a third insulating layer (332) and a third electrically conductive layer (346) (functioning as a third word line). Each second tier alternating stack (232, 246) is placed on top of each first tier alternating stack (132, 146), and each third tier alternating stack (332, 346) is placed on top of each second tier alternating stack (232, 246). Each combination of the first tier alternating stack (132, 146), the second tier alternating stack (232, 246) above it, and optionally the third tier alternating stack (332, 346) above it may be laterally spaced from adjacent combinations of the first tier alternating stack (132, 146), the second tier alternating stack (232, 246) above it, and the optional third tier alternating stack (332, 346) above it by a rear trench fill structure (76) that extends laterally along the first horizontal direction (e.g., word line direction) (hd1).

[0022] As used herein, "first tier level" refers to the tier level closest to the substrate, "second tier level" refers to the tier level closest to the substrate among the tier levels placed above the first tier level, "third tier level" refers to the tier level closest to the substrate among the tier levels placed above the second tier level, and so on. "First tier" elements refer to elements located within the first tier level; "second tier" elements refer to elements located within the second tier level; "third tier" elements refer to elements located within the second tier level, and so on. Individual tier levels within a structure comprising multiple tier levels may be labeled as a first tier level, a second tier level, a third tier level, and so on. In this case, the first tier level may be any of the multiple tier levels, and the second tier level may be a tier level different from the first tier level, and so on.

[0023] An exemplary structure may include an optional semiconductor material layer (110) comprising a single-crystal or polycrystalline semiconductor material such as single-crystal silicon or polysilicon. In one embodiment, the semiconductor material layer (110) may be a substrate. Optionally, an underlying dielectric material layer may be provided immediately below the semiconductor material layer (110). In this case, the underlying dielectric material layer is referred to as a lower-level dielectric material layer (760).

[0024] The first tier alternating stack of the first insulating layer (132) and the first electrically conductive layer (146) is positioned on a substrate (which may include a semiconductor material layer (110) or other structures such as a silicon wafer placed under the semiconductor material layer (110)) between each adjacent pair of the back trench fill structure (76). The first tier inverse stepped dielectric material portion (165) is positioned on top and contacts the first stepped surface of the first tier alternating stack (132, 146). The second tier alternating stack of the second insulating layer (232) and the second electrically conductive layer (246) is positioned on top of the first tier alternating stack (132, 146) and is positioned on a horizontal plane comprising the flat upper surface of the first tier inverse stepped dielectric material portion (165) between each adjacent pair of the back trench fill structure (76). A second tier inverted stepped dielectric material portion (265) is placed on top and contacts the second stepped surface of the second tier alternating stack (232, 246). A third tier alternating stack of the third insulating layer (332) and the third electrically conductive layer (346), if present, is placed on top of the second tier alternating stack (232, 246) and is placed on a horizontal plane comprising the flat upper surface of the second tier inverted stepped dielectric material portion (265) between each adjacent pair of the rear trench fill structure (76). A third tier inverted stepped dielectric material portion (365) is placed on top and, if present, contacts the third stepped surface of the third tier alternating stack (332, 346). The vertical ends (S) of the first stepped surface and the second stepped surface extend laterally along the second horizontal direction (hd2) (e.g., bit line direction).

[0025] The memory opening fill structure (58) may be located within each memory array region (100) (including the first memory array region (100A) and the second memory array region (100B)) between each adjacent pair of the rear trench fill structure (76). The memory opening fill structure (58) may be located within a memory opening that extends vertically through each layer within the first tier alternating stack (132, 146), the second tier alternating stack (232, 246), and, if present, the optional third tier alternating stack (332, 346) located between each adjacent pair of the rear trench fill structure (76).

[0026] In one embodiment, each memory opening fill structure (58) comprises a vertical stack of memory elements (e.g., a portion of a memory film or a vertically separated discrete memory element) located at the level of an electrically conductive layer (146, 246, 346) and a vertical semiconductor channel (60) electrically connected to a metal interconnect structure (such as a bit line) placed on top of each. In one embodiment, the inter-array region (200) does not have any memory stack structure electrically contacted by any metal interconnect structure (such as a bit line).

[0027] Each memory opening fill structure (58) includes each memory stack structure including each memory film and each vertical semiconductor channel. The memory opening and memory fill structures (58) are formed in an area where each layer of the first tier alternating stack and each layer of the second tier alternating stack exist. For each area where a continuous combination of the first tier alternating stack (132, 146), the second tier alternating stack (232, 246) and an optional third tier alternating stack (332, 346) is continuously extended laterally, the first memory stack structure may be located within each first memory array area (100A), and the second memory stack structure may be located within each second memory array area (100B). The second memory array region (100B) can be connected to the first memory array region (100A) by penetrating each inter-array region (200) where the first tier inverse stepped dielectric portion (165), the second tier inverse stepped dielectric portion (265), and the optional third tier inverse stepped dielectric material portion (365) are located.

[0028] The first tier inverse stepped dielectric material portion (165) may be located between each adjacent pair of rear trench fill structures (76). Each first tier inverse stepped dielectric material portion (165) is placed on the first stepped surface of each first tier alternating stack (132, 146). Each first tier inverse stepped dielectric material portion (165) may have a side wall that extends laterally along the first horizontal direction (hd1) and contacts each rear trench fill structure (76). The first stepped surface includes the vertical ends of the first tier alternating stacks (132, 146) that are laterally spaced along the first horizontal direction (hd1) and offset perpendicularly from each other.

[0029] The second tier inverse stepped dielectric material portion (265) may be positioned between each adjacent pair of rear trench fill structures (76). Each second tier inverse stepped dielectric material portion (265) is placed on the second stepped surface of each second tier alternating stack (232, 246). Each second tier inverse stepped dielectric material portion (265) may have a side wall that extends laterally along the second horizontal direction (hd1) and contacts each rear trench fill structure (76). The second stepped surface includes the vertical ends of the second tier alternating stacks (232, 246) that are laterally spaced along the first horizontal direction (hd1) and offset perpendicularly from each other. In one embodiment, each second tier inverse stepped dielectric material portion (265) is placed on top and contacts each of the first tier inverse stepped dielectric material portions (165).

[0030] The third tier inverse stepped dielectric material portion (365) may be located between each adjacent pair of rear trench fill structures (76). Each third tier inverse stepped dielectric material portion (365) is placed on the third stepped surface of each third tier alternating stack (332, 346). Each third tier inverse stepped dielectric material portion (365) may have a side wall that extends laterally along the second horizontal direction (hd2) and contacts each rear trench fill structure (76). The third stepped surface includes vertical ends of the third tier alternating stacks (332, 346) that are laterally spaced along the second horizontal direction (hd2) and offset perpendicularly from each other. In one embodiment, each third tier inverse stepped dielectric material portion (365) is placed on top and contacts each of the second tier inverse stepped dielectric material portions (265).

[0031] The rear trench may extend laterally along the first horizontal direction (hd1). Each rear trench may be filled with a rear trench fill structure (76) that may include a combination of a rear contact via structure and an insulating spacer that laterally surrounds the rear contact via structure. Alternatively, each rear trench fill structure (76) may be made of an insulating fill structure. Each vertical stack of the first tier alternating stack (132, 146), the second tier alternating stack (232, 246), and the optional third tier alternating stack (332, 346) may be located between adjacent pairs of rear trench fill structures (76).

[0032] As illustrated in FIG. 1e, for each vertical stack of the first tier alternating stack (132, 146), the second tier alternating stack (232, 246), and the optional third tier alternating stack (332, 346), each first rear trench fill structure (761) extends laterally along the first horizontal direction (hd1) (e.g., word line direction) and may or may not come into contact with the first side wall of the first tier alternating stack (132, 146), the first side wall of the second tier alternating stack (232, 246), and, if present, the first side wall of the third tier alternating stack (332, 346); And the second rear trench fill structure (762) extends laterally along the first horizontal direction (hd1) and may or may not include the second sidewall of the first tier alternating stack (132, 146), the second sidewall of the second tier alternating stack (232, 246), and, if present, the second sidewall of the third tier alternating stack (332, 346). The first rear trench fill structure (761) and the second rear trench fill structure (762) are adjacent pairs of rear trench fill structures (76). Generally, at least one of the first rear trench fill structure (761) and the second rear trench fill structure (762) is in direct contact with each layer within the first tier alternating stack (132, 146); At least one of the first rear trench fill structure (761) and the second rear trench fill structure (762) is in direct contact with each layer within the second tier alternating stack (232, 246); and at least one of the first rear trench fill structure (761) and the second rear trench fill structure (762) is in direct contact with each layer within the third tier alternating stack (332, 346) if the third tier alternating stack (332, 346) is present.

[0033] According to various embodiments, various configurations of exemplary structures are provided in which one or both of the first rear trench fill structure (761) and the second rear trench fill structure (762) are in direct contact with each layer within the first tier alternating stack (132, 146). Furthermore, one or both of the first rear trench fill structure (761) and the second rear trench fill structure (762) are in direct contact with each layer within the second tier alternating stack (232, 246). Furthermore, one or both of the first rear trench fill structure (761) and the second rear trench fill structure (762) are in direct contact with each layer within the third tier alternating stack (332, 346) (if present). FIGS. 1a through 1e illustrate a configuration in which the first rear trench fill structure (761) does not directly contact the first tier alternating stack (132, 146), the second tier alternating stack (232, 246), or the third tier alternating stack (332, 346), and the second rear trench fill structure (762) directly contacts each layer within the first tier alternating stack (132, 146), each layer within the second tier alternating stack (232, 246), and each layer within the third tier alternating stack (332, 346), but the first rear trench fill structure (761) and the second rear trench fill structure (762) do not directly contact the first tier alternating stack (132, 146), the second tier alternating stack (232, 246), and the third tier alternating Various combinations of embodiments that are in contact with or not in contact with each of the stacks (332, 346) are explicitly considered herein.

[0034] In one embodiment, the first contact via structure (86A) extends vertically through the second inverse stepped dielectric material portion (265) and the first inverse stepped dielectric material portion (165) and contacts each of the first electrically conductive layers (146). The second contact via structure (86B) extends vertically through the second inverse stepped dielectric material portion (265) and contacts each of the second electrically conductive layers (246).

[0035] The inter-array region (200) includes strips of a first insulating layer (132), a first electrically conductive layer (146), a second insulating layer (232), a second electrically conductive layer (246), a third insulating layer (332), and a third electrically conductive layer (346) located between each pair of laterally adjacent rear trench fill structures (76). These strips are located in each strip-shaped connecting region (240) (i.e., bridge region) of the inter-array region (200) located near each first tier inverse stepped dielectric material portion (165), each second tier inverse stepped dielectric material portion (265), or each third tier inverse stepped dielectric material portion (365). The strip has a narrower width along the second horizontal direction (hd2) than the portion of the strip located in the alternating stack (132, 146, 232, 246, 332, 346) located in the memory array area (100) and the remaining portion of the strip located in the inter-array area (200) outside each strip-shape connection area (240).

[0036] For each vertical stack of the first tier alternating stack (132, 146), the second tier alternating stack (232, 246), and the optional third tier alternating stack (332, 346), the first memory opening fill structure (58) may be located within the first memory array region (100A) where each layer of the first tier alternating stack (132, 1446), the second tier alternating stack (232, 246), and the optional third tier alternating stack (332, 346) exists. The second memory opening fill structure (58) may be located within a second memory array region (100B) that is laterally offset along the first horizontal direction (hd1) from the first memory array region (100A) by a first tier inverse stepped dielectric material portion (165), a second tier inverse stepped dielectric material portion (265), and an optional third tier inverse stepped dielectric material portion (365). Each layer of the first tier alternating stack (132, 1446), the second tier alternating stack (232, 246), and the optional third tier alternating stack (332, 346) exists within the second memory array region (100B). Each of the electrically conductive layers (146, 246, 346) within the vertical stack can be continuously extended from the first memory array region (100A) to the second memory array region (100B) by penetrating a strip-shaped connection region (240) (also referred to as a bridge region). Each strip-shaped connection area (240) may be located within the inter-array area (200) and may be located between the rear trench fill structure (76) and the first tier inverse stepped dielectric material portion (165) at the level of the first tier alternating stack (132, 146), or between the rear trench fill structure (76) and the second tier inverse stepped dielectric material portion (265) at the level of the second tier alternating stack (232, 246), or between the rear trench fill structure (76) and the third tier inverse stepped dielectric material portion (365) at the level of the third tier alternating stack (332, 346).

[0037] A staircase comprising a first stepped surface of a first tier alternating stack (132, 146), a second stepped surface of a second tier alternating stack (232, 246), and optionally a third tier alternating stack (332, 346) may rise (i.e., ascend) from a substrate along a first horizontal direction (hd1) or along a direction opposite to the first horizontal direction (hd1). In one embodiment, the ascending direction of the staircase may vary for all other pairs of vertical stacks of each first tier alternating stack (132, 146), each second tier alternating stack (232, 246), and each third tier alternating stack (332, 346). In other words, the ascending direction is staggered from one another in nearby alternating stacks separated along the second horizontal direction. For example, when each vertical stack of each first-tier alternating stack (132, 146), each second-tier alternating stack (232, 246), and each third-tier alternating stack (332, 346) is sequentially numbered with a positive integer N starting from 1, each (4N+1)th combination and each (4N+2)th vertical stack {(132, 146), (232, 246), (332, 246)} may have a staircase rising along the first horizontal direction (hd1), and each (4N+3)th combination and each (4N+4)th vertical stack {(132, 146), (232, 246), (332, 246)} may have a staircase rising along the opposite direction of the first horizontal direction (hd1). In this embodiment, the vertical distance between the first stepped surface and the substrate increases along the first horizontal direction (hd1), the vertical distance between the second stepped surface and the substrate increases along the first horizontal direction (hd1), the additional vertical distance between the first stepped surface and the substrate decreases along the first horizontal direction (hd1), and the additional vertical distance between the second stepped surface and the substrate decreases along the first horizontal direction (hd1).

[0038] In an alternative embodiment, the rising direction of the stairs does not change for all other pairs of combinations of each first-tier alternating stack (132, 146), each second-tier alternating stack (232, 246), and each third-tier alternating stack (332, 246). In other words, the rising direction is the same (i.e., not staggered) in nearby alternating stacks separated along the second horizontal direction.

[0039] Laterally isolated vertical interconnect structures (484, 486) may be formed through the inter-array region (200). Each laterally isolated vertical interconnect structure (484, 486) may include a through-memory level conductive via structure (486) and a tubular insulating liner (484) that laterally surrounds the conductive via structure (486). Each through-memory level conductive via structure (486) may be in contact with a lower-level metal interconnect structure (780) located in a lower-level dielectric material layer (760) as shown in FIG. 1d and FIG. 1e. The lower-level metal interconnect structure (780) may be embedded in the lower-level dielectric material layer (760) located between the first tier alternating stack (132, 146) and a substrate (not shown) that may be provided immediately below the lower-level dielectric material layer (760). Laterally isolated vertical interconnect structures (484, 486) extend vertically through strip portions of the first tier alternating stack (132, 146), the second tier alternating stack (232, 246), and the third tier alternating stack (332, 346), and come into contact with one of each of the lower-level metal interconnect structures (780).

[0040] A drain contact via structure (not exemplified) may contact an upper portion of each memory opening fill structure (58) (such as a drain region within each memory opening fill structure (58)). A bit line (not exemplified) may extend laterally along a second horizontal direction (hd2) and may contact an upper surface of each subset of the drain contact via structure. An additional metal interconnect structure embedded in a dielectric material layer (not shown) placed over it may be used to provide electrical connections between various nodes of a three-dimensional memory device located on a semiconductor die (1000).

[0041] Each rear trench fill structure (76) includes an insulating material portion. In one embodiment, each insulating material portion may include an insulating spacer that laterally surrounds a contact via structure, such as a rear contact via structure (not clearly shown). In another embodiment, each insulating material portion may include a dielectric wall structure that occupies the entire volume of each rear trench fill structure (76). In one embodiment, each sidewall of the first alternating stack (132, 146) may be in contact with the sidewall of one insulating material portion of each rear trench fill structure (76).

[0042] According to various embodiments of the present disclosure, various inverse stepped dielectric material portions (165, 265, 365) may be formed in various configurations and may or may not be in contact with adjacent rear trench fill structures (76). In one embodiment, when rear trench fill structures (76) are sequentially numbered with positive integers along a second horizontal direction (e.g., bit line direction) (hd2), each odd-numbered rear trench fill structure (76) may be in contact with each pair of first-tier inverse stepped dielectric material portions (165), and each even-numbered rear trench fill structure (76) may not be in contact with any of the first-tier inverse stepped dielectric material portions (165). Alternatively, the rear trench fill structure (76) may not come into contact with any of the first tier inverse stepped dielectric material portions (165), and the first tier inverse stepped dielectric material portions (165) may be laterally spaced from each adjacent pair of the rear trench fill structure (76). For each configuration of the first tier inverse stepped dielectric material portions (165), each odd-numbered rear trench fill structure (76) may come into contact with each pair of the second tier inverse stepped dielectric material portions (265), and each even-numbered rear trench fill structure (76) does not come into contact with any of the second tier inverse stepped dielectric material portions (265). Alternatively, each even-numbered rear trench fill structure (76) may come into contact with each pair of second-tier inverse-stepped dielectric material portions (265), and each odd-numbered rear trench fill structure (76) does not come into contact with any of the second-tier inverse-stepped dielectric material portions (265).Alternatively, the rear trench fill structure (76) may not come into contact with any of the second-tier inverse stepped dielectric material portions (265), and the second-tier inverse stepped dielectric material portions (265) may be laterally spaced from each adjacent pair of the rear trench fill structure (76). For each configuration of the first-tier inverse stepped dielectric material portion (165) and for each configuration of the second-tier inverse stepped dielectric material portion (265), each odd-numbered rear trench fill structure (76) may come into contact with each pair of the third-tier inverse stepped dielectric material portions (365), and each even-numbered rear trench fill structure (76) does not come into contact with any of the third-tier inverse stepped dielectric material portions (365). Alternatively, each even-numbered rear trench fill structure (76) may be in contact with each pair of third-tier inverse-stepped dielectric material portions (365), and each odd-numbered rear trench fill structure (76) may not be in contact with any of the third-tier inverse-stepped dielectric material portions (365). Even more alternatively, the rear trench fill structure (76) may not be in contact with any of the third-tier inverse-stepped dielectric material portions (365), and the third-tier inverse-stepped dielectric material portions (365) may be laterally spaced from each adjacent pair of rear trench fill structures (76).

[0043] In one embodiment, each plane (300) within an exemplary semiconductor die (100) comprises a three-dimensional memory device comprising an alternating stack of insulating layers (132, 232, 332) and electrically conductive layers (146, 246, 346). Each alternating stack {(132, 146), (232, 246), (332, 346)} extends laterally along a first horizontal direction (hd1) through a first memory array region (100A) and a second memory array region (100B) which are laterally separated by an inter-array region (200). Each alternating stack {(132, 146), (232, 246), (332, 346)} comprises a set of stepped surfaces (i.e., steps) of the inter-array region (200). Each plane (300) within the exemplary semiconductor die (1000) comprises an inverse stepped dielectric material portion (165, 265, 365) placed over each set of stepped surfaces of an alternating stack {(132, 146), (232, 246), (332, 346)}. Each plane (300) within the exemplary semiconductor die (1000) comprises a cluster of memory stack structures located within a memory opening fill structure (58). Each memory stack structure extends vertically through each of the alternating stacks {(132, 146), (232, 246), (332, 346)} and is located within a first memory array region (100A) or a second memory array region (100B). Each memory stack structure may include a vertical stack of memory elements (e.g., memory films) located at the level of each vertical semiconductor channel and electrically conductive layer (146, 246, 346).

[0044] A three-dimensional memory device may include a layer contact via structure (e.g., a word line contact via structure) (86A, 86B, 86C) that extends vertically through each of an inverse step-shaped dielectric material portion (165, 265, 365) and contacts each of an electrically conductive layer (146, 246, 346). In one embodiment, for each pair of electrically conductive layers (146, 246 or 346) located within the same alternating stack, the layer contact via structure (86A, 86B, 86C) contacting the upper electrically conductive layer is closer to the first memory array region (100A) than the layer contact via structure contacting the lower electrically conductive layer is closer to the first memory array region (100A). In other words, the higher the bottom surface of the layer contact via structure (86A, 86B, 86C) is from the substrate (110, 760), the closer the layer contact via structure (86A, 86B, 86C) is to the first memory array region (100A). In other words, the steps generally rise (i.e., ascend) from the shorter second memory array region (100B) to the longer first memory array region (300) in each plane (300).

[0045] The electrical connection between each layer contact via structure (86A, 86B, 86C) and a portion of each electrically conductive layer (146, 246, or 346) within the second memory array region (100B) is provided by a strip portion of the electrically conductive layer (146, 246, or 346) located near each inverse stepped dielectric material portion (165, 265, 365) and in a bridge region (250) located laterally offset along the second horizontal direction from each inverse stepped dielectric material portion (165, 265, 365). The strip portion has a smaller width (i.e., a narrower width) than the portion of the electrically conductive layer (146, 246, 346) located in the first memory array region (100A) or the second memory array region (100B). A portion of the electrically conductive layer (146, 246, 346) located in the first memory array region (100A) or the second memory array region (100B) has a width along the second horizontal direction (hd2) equal to the lateral distance between adjacent pairs of the rear trench fill structure (76).

[0046] In contrast, each strip portion of the electrically conductive layer (146, 246 or 346) of the bridge region (240) has a width along the second horizontal direction (hd2) equal to the difference between the lateral distance between adjacent pairs of rear trench fill structures (76) and the width of adjacent inverse stepped dielectric portions (165 or 265) along the second horizontal direction (hd2). Each electrical connection between the layer contact via structure (86A, 86B, 86C) and the nearest portion of the second memory array region (100B) includes a narrow strip portion of the electrically conductive layer (146, 246, 346) of the bridge region (240), whereas the electrical connection between the layer contact via structure (86A, 86B, 86C) and the nearest portion of the first memory array region (100A) does not include any narrow strip portion of the electrically conductive layer (146, 246, 346) because the first memory array region (100A) is not separated from the layer contact via structure (86A, 86B, 86C) by the bridge region (240).

[0047] In one embodiment, alternating stacks {(132, 146), (232, 246), (332, 346)} are laterally spaced along a second horizontal direction (hd2) by a line trench (such as a rear trench) extending laterally along a first horizontal direction (hd1). The line trench is filled with a rear trench fill structure (76) having a dielectric surface (such as an insulating spacer or the surface of a dielectric wall structure) in contact with the sidewalls of the alternating stacks {(132, 146), (232, 246), (332, 346)}. In one embodiment, when the rear trench fill structures (76) are sequentially numbered with positive integers along the second horizontal direction (hd2), the odd-numbered rear trench fill structures may come into contact with each pair of inverse stepped dielectric material parts (165, 265, 365) (located on both sides of each odd-numbered rear trench fill structure (76)), and the even-numbered rear trench fill structures may not come into contact with any of the inverse stepped dielectric material parts (165, 265, 365), or the even-numbered rear trench fill structures may come into contact with each of the inverse stepped dielectric material parts (165, 265, 365), and the odd-numbered rear trench fill structures may not come into contact with any of the inverse stepped dielectric material parts (165, 265, 365).

[0048] In one embodiment, the strip width of the first electrically conductive layer (146) decreases according to each vertical distance from the substrate (760, 110). The strip width of the second electrically conductive layer (246) decreases according to each vertical distance from the substrate (760, 110). The strip width of the third electrically conductive layer (346) decreases according to each vertical distance from the substrate (760, 110). The bottom second electrically conductive layer (246) in the second tier alternating stack (232, 246) has a strip width that exceeds the top first electrically conductive layer (146) in the first tier alternating stack (132, 146). The lowest third electrically conductive layer (346) in the third tier alternating stack (332, 346) has a strip width that exceeds the uppermost second electrically conductive layer (246) in the second tier alternating stack (232, 246).

[0049] According to one embodiment of the present disclosure illustrated in FIG. 1e, a set of first-tier inverse-step dielectric material portions (165), second-tier inverse-step dielectric material portions (265), and third-tier inverse-step dielectric material portions (365) may be formed between adjacent pairs of rear trench fill structures (76), referred herein to as first rear trench fill structures (761) and second rear trench fill structures (762). The upper surface of the first-tier inverse-step dielectric material portion (165) may have a first width (D1) along a second horizontal direction (hd2) that is less than the lateral spacing between adjacent pairs (761, 762) of rear trench fill structures. The upper surface of the second-tier inverse-step dielectric material portion (265) may have a second width (D2) along a second horizontal direction (hd2) that is less than the first width (D1). The upper surface of the third tier inverse step type dielectric material portion (365) may have a third width (D3) along the second horizontal direction (hd2) which is less than the second width (D1).

[0050] The width of each strip of the electrically conductive layer (146, 246, 346) along the second horizontal direction of the bridge region (240) is referred to herein as the strip width or bridge width. Generally, embedding the reverse stepped dielectric material portion (165, 265, 365) of the alternating stack of insulating layers (132, 232, 332) and electrically conductive layers (146, 246, 346) can cause cracking due to the gap formed in the reverse dielectric material portion (165, 265, 365) and / or tilting toward the rear trench of the alternating stack due to uneven electrically conductive layer material filling.

[0051] According to one aspect of the present disclosure, the bridge width is different at different tier levels of the bridge area (240). For example, a strip portion of the top first electrically conductive layer (146) of each first tier alternating stack (132, 146) may have a first lateral range (i.e., a first width) (E1) along a second horizontal direction (hd2), a second electrically conductive layer (246) of each second tier alternating stack (232, 242) may have a second lateral range (i.e., a second width) (E2) along a second horizontal direction (hd2), and a strip portion of the top third electrically conductive layer (346) of each third tier alternating stack (332, 342) may have a third lateral range (i.e., a third width) (E3) along a second horizontal direction (hd2). The first lateral range (E1) is less than the second lateral range (E2), and the second lateral range (E2) is less than the third lateral range (E3). In other words, the first width of the lower tier is smaller than the second width of the second tier placed above it, and the second width is smaller than the third width of the third tier placed above it (if present). Thus, as described below, the voids formed in the inverse stepped dielectric material portions (165, 265, 365) can be reduced or avoided due to the larger space between the strips of the lower tier of the bridge region (240), and / or the slope toward the rear trench of the alternating stack can be reduced or avoided by filling with a more balanced electrically conductive layer material.

[0052] Furthermore, referring to FIG. 1c, the length of the bridge region (240) in the first horizontal direction (hd1) at the top of the first tier structure may be L1, the length of the bridge region (240) in the first horizontal direction at the top of the second tier structure may be L2, and the length of the bridge region (240) in the first horizontal direction at the top of the third tier structure may be L3. In one embodiment, if L3 is equal to length X, L2 = 2 / 3X and L1 = 1 / 3X, and if E3 is equal to width Y, E2 = 2 / 3Y and E1 = 1 / 3Y. Likewise, for a 2-tier memory device embodiment, if L2 is equal to length X, L1 = ½, and if E2 is equal to width Y, E1 = 1 / 2Y. In these embodiments, the electrical resistance of the electrically conductive layers (146, 246, 346) of the bridge regions (240) of all three tiers may be similar (e.g., differing by 10% or less), because the longer electrically conductive layer (346) has a width that exceeds the shorter electrically conductive layer (146) of the same bridge region (240).

[0053] In one embodiment, the first tier structure may embed a first tier inverse stepped dielectric material portion (165) having a first length along the first horizontal direction (hd1) and a first width (D1) along the second horizontal direction (hd2). The second tier structure may embed a second tier inverse stepped dielectric material portion (265) having a second length exceeding the first length along the first horizontal direction (hd1) and a second width (D2) less than the first width (D1) along the second horizontal direction (hd2). The third tier structure may embed a third tier inverse stepped dielectric material portion (365) having a third length exceeding the second length along the first horizontal direction (hd1) and a third width (D3) less than the second width (D2) along the second horizontal direction (hd2). Accordingly, the average bridge width (i.e., average strip width) of the third electrically conductive layer (346) along the second horizontal direction (hd2) exceeds the average bridge width of the second electrically conductive layer (246) along the second horizontal direction (hd2), which exceeds the average bridge width of the first electrically conductive layer (146) along the second horizontal direction (hd2).

[0054] In some embodiments, various tier structures may be configured in a mirror symmetry with respect to a vertical plane extending along a first horizontal direction through a rear trench fill structure (76) (such as the first rear trench fill structure (761)). According to one aspect of the disclosure, conformal filling of the dielectric material of the inverse stepped trench during the formation of the first tier inverse stepped dielectric material portion (165) may be facilitated by increasing the width of the inverse stepped trench along the horizontal direction (hd2), which entails an increase in the first width (D1) of each first tier inverse stepped dielectric material portion (165). This reduces cracking and tilting while forming a symmetric structure around each rear trench located between each stack pair of the inverse stepped dielectric material portions (165, 265, 365).

[0055] While the illustrated configuration of the exemplary structure illustrated in FIGS. 1a to 1e adopts three tier levels, embodiments in which two tier levels or four or more tier levels are used in alternative configurations are explicitly considered herein.

[0056] The exemplary semiconductor die (1000) of FIGS. 1a through 1e can be manufactured by adopting a sequence of processing steps. Referring to FIGS. 2a through 2c, an exemplary structure for forming the structure of FIGS. 1a through 1e is illustrated after forming a first vertical alternating sequence of a semiconductor material layer (110) and a first insulating layer (132) and a first sacrificial material layer (142), a semiconductor device (720) on a substrate semiconductor layer (9) (provided within at least the upper portion of the substrate (8)), a lower-level dielectric layer (760), a lower-level metal interconnect structure (780) embedded in the lower-level dielectric layer (760) (schematically represented by a dotted area including a physical implementation of the lower-level metal interconnect structure), a semiconductor material layer (110), and a first insulating layer (132) and a first sacrificial material layer (142). The substrate semiconductor layer (9) may include a semiconductor layer located on a substrate such as a silicon wafer (e.g., a doped well) or on an insulating substrate, such as a silicon or semiconductor substrate. The semiconductor device (720) may include a field-effect transistor formed on the top surface of the substrate (8). The lower-level dielectric layer (760) may be an interconnection-level dielectric material layer that embeds a lower-level metal interconnect structure (780).

[0057] As used herein, a vertical alternating sequence refers to a sequence of multiple instances of a first element and multiple instances of a second element arranged such that an instance of the second element is positioned between each vertically adjacent pair of instances of the first element, and an instance of the first element is positioned between each vertically adjacent pair of instances of the second element.

[0058] The first insulating layer (132) may be composed of a first material, and the first sacrificial material layer (142) may be composed of a second material different from the first material. Each of the first insulating layers (132) is an insulating layer that extends continuously over the entire area of ​​the substrate (8) and may have a uniform thickness over the entire area. Each of the first sacrificial material layers (142) may include a dielectric material and may include a sacrificial material layer that extends continuously over the entire area of ​​the substrate (8) and may have a uniform thickness over the entire area. Insulating materials that can be used for the first insulating layer (132) include, but are not limited to, silicon oxide (including doped or undoped silicate glass), silicon nitride, silicon oxynitride, organosilicate glass (OSG), spin-on dielectric materials, dielectric metal oxides and silicates thereof commonly known as high dielectric constant (high-k) dielectric oxides (e.g., aluminum oxide, hafnium oxide, etc.), dielectric metal oxynitrides and silicates thereof, and organic insulating materials. In one embodiment, the first material of the first insulating layer (132) may be silicon oxide.

[0059] The second material of the first continuous sacrificial material layer (142) is a dielectric material that is a sacrificial material that can be selectively removed with respect to the first material of the first insulating layer (132). As used herein, if the removal process removes the first material at a rate that is at least twice the removal rate of the second material, the removal of the first material is “selective” with respect to the second material. The ratio of the removal rate of the first material to the removal rate of the second material is referred to herein as the “selectivity” of the removal process for the first material with respect to the second material.

[0060] The second material of the first sacrificial material layer (142) can subsequently be replaced with an electrically conductive electrode that can function, for example, as a control gate electrode of a vertical NAND device. In one embodiment, the first sacrificial material layer (142) may be a material layer comprising silicon nitride.

[0061] Generally, a vertical alternating sequence of unit layers is stacked on a substrate. Each unit layer stack includes a first insulating layer (such as the first insulating layer (132)) and a first spacer material layer (such as the first sacrificial material layer (142)). Generally, the first spacer material layer is formed as a first electrically conductive layer or subsequently replaced by a first electrically conductive layer. While the present disclosure is described by adopting an embodiment in which the first spacer material layer is formed as a first sacrificial material layer (142) that is subsequently replaced by a first electrically conductive layer, an embodiment in which the first spacer material layer is formed as a first electrically conductive layer is clearly considered herein. In such an embodiment, the step of replacing the material of the first spacer material layer with an electrically conductive material may be omitted.

[0062] A first stepped surface may be formed within a stepped area of ​​an inter-array region (200) to be filled with a first tier inverse stepped dielectric material portion (165). For example, a combination of a sacrificial hard mask layer and a trimming mask layer may be used to form the first stepped surface. In one embodiment, a row of a plurality of first stepped areas may be formed within a respective area corresponding to a combination of an interposed area and the area of ​​a pair of laterally adjacent pairs of the first tier inverse stepped dielectric material portion (165). In this case, the plurality of first stepped areas may subsequently be vertically offset by different depths by subsequently performing an area recess etching process.

[0063] In an exemplary example, 2 of the first stepped surface MA set of 20 can be formed within a combination of the interposed area and the area of ​​a laterally adjacent pair of the first tier inverse stepped dielectric material portion (165). M may be an integer in the range of 1 to 8. Each set of the first stepped steps may include P steps such that the sidewalls of P first continuous spacer material layers are physically exposed with a lateral offset. P may be an integer in the range of 2 to 64. M area recess etching processes are each area recess etching process of P times 2 of the first insulating layer (132) and the first sacrificial material layer (142). i A set of can be performed to vertically recess, where i is a different integer from 0 to (M-1). For the first vertical alternating sequence of the first insulating layer (132) and the first sacrificial material layer (142), a maximum total of 2 M x P stepped surfaces may be formed. The total number of stepped surfaces within each continuous cavity placed on the first stepped surface may be equal to the total number of the first sacrificial material layers (142) of the first vertical alternating sequence (132, 142).

[0064] A first dielectric fill material (such as undoped silicate glass (i.e., silicon oxide) or doped silicate glass) may be deposited in each first continuous inverse step-shaped cavity. The first dielectric fill material may be flattened to remove excess portions of the first dielectric fill material from the horizontal plane, including the top surface of the first vertical alternating sequence (132, 142). Each remaining portion of the first dielectric fill material filling each first continuous inverse step-shaped cavity constitutes a first tier inverse step-shaped dielectric material portion (165). Generally, the first tier inverse step-shaped dielectric material portion (165) may be formed in an inter-array region (200) located between each first memory array region (100A) and each second memory array region (100B) that are laterally spaced along the first horizontal direction (hd1).

[0065] Various first-tier openings may be formed into the semiconductor material layer (110) by penetrating the first vertical alternating sequence (132, 142). A photoresist layer (not shown) may be applied over the first vertical alternating sequence (132, 142) and lithographically patterned to form various openings. The pattern of openings within the photoresist layer may be transferred into the semiconductor material layer (110) by penetrating the first vertical alternating sequence (132, 142) by a first anisotropic etching process to form various first-tier openings simultaneously, i.e., during the first isotropic etching process. Various first-tier openings may include first-tier memory openings formed in the memory array region (100) and first-tier support openings formed in the inter-array region (200). Each cluster of first-tier memory openings may be formed as a two-dimensional array of first-tier memory openings. The first tier support opening is an opening formed within the inter-array area (200) and subsequently used to form a support column structure. A subset of the first tier support openings may be formed by penetrating each horizontal surface of the first stepped surface.

[0066] The sacrificial first tier opening fill portion may be formed in various first tier openings. For example, a sacrificial first tier filling material is deposited simultaneously in each of the first tier openings. The sacrificial first tier filling material comprises a material that can subsequently be removed from the material of the first insulating layer (132) and the first sacrificial material layer (142). In one embodiment, the sacrificial first tier filling material may comprise a semiconductor material such as silicon (e.g., a-Si or polysilicon), a silicon-germanium alloy, germanium, a III-V compound semiconductor material, or a combination thereof. Optionally, a thin etching stop liner may be used before depositing the sacrificial first tier filling material (such as a silicon oxide layer or a silicon nitride layer with a thickness in the range of 1 nm to 3 nm). The sacrificial first tier filling material may be formed by a non-conformal deposition or conformal deposition method.

[0067] In another embodiment, the sacrificial first tier fill material may comprise a silicon oxide material having a higher etching rate than the material of the first insulating layer (132). For example, the sacrificial first tier fill material may comprise borosilicate glass or porous or non-porous organicsilicate glass having an etching rate at least 100 times higher than the etching rate of TEOS oxide densified in 100:1 diluted hydrofluoric acid (i.e., a silicon oxide material formed by the decomposition of tetraethylorthosilicate glass in a chemical vapor deposition process and subsequently densified in an annealing process). In this case, a thin etching stop liner (such as a silicon nitride layer having a thickness in the range of 1 nm to 3 nm) may be used before depositing the sacrificial first tier fill material. The sacrificial first tier fill material may be formed by a non-conformal deposition or conformal deposition method.

[0068] In another embodiment, the sacrificial first tier fill material may comprise a carbon-containing material (such as amorphous carbon or diamond-like carbon) that can be subsequently removed by ashing, or a silicon-based polymer that can be optionally subsequently removed for the material of the first vertical alternating sequence (132, 142).

[0069] A portion of the deposited sacrificial material may be removed from the top layer of the first vertical alternating sequence (132, 142), for example, from the top first insulating layer (132). For example, the sacrificial first tier fill material may be recessed to the top surface of the top first insulating layer (132) using a planarization process. The planarization process may include recess etching, chemical mechanical planarization (CMP), or a combination thereof. The top surface of the top first insulating layer (132) may be used as an etching stop layer or a planarization stop layer.

[0070] The remainder of the sacrificial first tier fill material comprises the sacrificial first tier opening fill portion. Specifically, each remainder of the sacrificial first tier material of the first tier memory opening constitutes the sacrificial first tier memory opening fill portion (148). Each remainder of the sacrificial first tier fill material of the first tier support opening constitutes the sacrificial first tier support opening fill portion (148). Various sacrificial first tier opening fill portions are formed simultaneously, that is, during the same set of processes including a deposition process for depositing the sacrificial first tier fill material and a planarization process for removing the first tier deposition process from above the first vertical alternating sequence (132, 142) (e.g., from above the upper surface of the top first insulating layer (132)). The upper surface of the sacrificial first tier opening fill portion may be coplanar with the upper surface of the top first insulating layer (132). Each sacrificial first tier opening fill portion may or may not contain cavities within it. A set of all structures located between the lowest surface of the first vertical alternating sequence (132, 142) and the uppermost surface of the first vertical alternating sequence (132, 142) or embedded within the first vertical alternating sequence (132, 142) constitutes a first tier structure.

[0071] Referring to FIGS. 3a through 3c, a second vertical alternating sequence of a second insulating layer (232) and a second sacrificial material layer (242) may be formed. Each of the second insulating layers (232) is an insulating layer that extends continuously over the entire area of ​​the substrate (8) and may have a uniform thickness over the entire area. Each of the second sacrificial material layers (242) includes a dielectric material and may include a sacrificial material layer that extends continuously over the entire area of ​​the substrate (8) and may have a uniform thickness over the entire area. The second insulating layer (232) may have the same material composition and the same thickness as the first insulating layer (132). The second sacrificial material layer (242) may have the same material composition and the same thickness as the first continuous sacrificial material layer (142).

[0072] Generally, at least one additional vertical alternating sequence of an additional insulating layer and an additional sacrificial material layer may be optionally formed on the first vertical alternating sequence (132, 142) and the first tier inverse stepped dielectric material portion (165).

[0073] A second stepped surface may be formed within the stepped region of an inter-array region (200) to be filled with a second tier inverse stepped dielectric material portion (265). For example, a combination of a sacrificial hard mask layer and a trimming mask layer may be used to form the second stepped surface. In one embodiment, a row of multiple second stepped regions may be formed within each area corresponding to a combination of the interposed area and the area of ​​a pair of laterally adjacent pairs of the second tier inverse stepped dielectric material portion (265). In this case, the multiple second stepped regions may subsequently be vertically offset by different depths by subsequently performing an area recess etching process.

[0074] In an exemplary example, 2 of the second stepped surface NA set of 20 can be formed within a combination of the interposed area and the area of ​​a laterally adjacent pair of the second tier inverse stepped dielectric material portion (265). N may be an integer in the range of 2 to 8. Each set of the second stepped steps may include P steps such that the sidewalls of Q second continuous spacer material layers are physically exposed with a lateral offset. Q may be an integer in the range of 2 to 64. M area recess etching processes are performed such that each area recess etching process is Q x 2 of the second insulating layer (232) and the second sacrificial material layer (242). j The set can be performed to recess vertically, where j is a different integer from 0 to (N-1). For the second vertical alternating sequence of the second insulating layer (232) and the second sacrificial material layer (242), a maximum total of 2 M x Q stepped surfaces may be formed. The total number of stepped surfaces within each continuous cavity placed on the second stepped surface may be equal to the total number of the second sacrificial material layers (242) of the first vertical alternating sequence (132, 242).

[0075] A second dielectric fill material (such as undoped silicate glass (i.e., silicon oxide) or doped silicate glass) may be deposited in each second continuous reverse stepped cavity. The second dielectric fill material may be flattened to remove excess portions of the second dielectric fill material from the horizontal plane, including the uppermost surface of the second vertical alternating sequence (232, 242). Each remaining portion of the second dielectric fill material filling each second continuous reverse stepped cavity constitutes a second tier reverse stepped dielectric material portion (265).

[0076] Generally, a second tier structure is formed comprising a second tier inverse stepped dielectric material portion (265) placed on the second stepped surface of the second vertical alternating sequence located in the second vertical alternating sequence of the second insulating layer (232) and the second sacrificial material layer (242) and the array inter-region (200).

[0077] Various second tier openings may be formed through the second vertical alternating sequence (232, 242) and on the sacrificial first tier opening fill portion (148, 128). A photoresist layer (not shown) may be applied over the second vertical alternating sequence (232, 242) and lithographically patterned to form various openings. The pattern of openings within the photoresist layer may be transferred through the second vertical alternating sequence (232, 242) to form various second tier openings simultaneously, i.e., during the second isotropic etching process.

[0078] Various second-tier openings may include a second-tier memory opening formed in a memory array region (100) and a second-tier support opening formed in an inter-array region (200). Each second-tier opening may be formed within one area of ​​each sacrificial first-tier opening fill portion. Thus, the upper surface of the sacrificial first-tier opening fill portion may be physically exposed at the bottom of each second-tier opening. Specifically, each second-tier memory opening may be formed directly above each sacrificial first-tier memory opening fill portion (148), and each second-tier support opening may be formed directly above each sacrificial first-tier support opening fill portion. Each cluster of second-tier memory openings may be formed as a two-dimensional array of second-tier memory openings. The second-tier support opening is an opening formed within the inter-array region (200) and subsequently used to form a support pillar structure. A subset of the second tier support openings can be formed by penetrating each horizontal surface of the second stepped surface.

[0079] The sacrificial second tier opening fill portion may be formed in various second tier openings. For example, a sacrificial first tier fill material is simultaneously deposited in each of the second tier openings. The sacrificial second tier fill material may include any material that can be used for the sacrificial first tier fill material. A portion of the deposited sacrificial second tier fill material may be removed from the top layer of the second vertical alternating sequence (232, 242). The remainder of the sacrificial second tier fill material comprises the sacrificial second tier opening fill portion. Specifically, each remainder of the sacrificial second tier material of the second tier memory opening constitutes the sacrificial second tier memory opening fill portion (248). Each remainder of the sacrificial second tier fill material of the first tier support opening constitutes the sacrificial second tier support opening fill portion (not illustrated). The upper surface of the sacrificial second tier opening fill portion may be coplanar with the upper surface of the top second insulating layer (232). Each of the sacrificial second-tier opening fill portions may or may not contain a cavity inside. A set of all structures located between the lowest surface of the second vertical alternating sequence (232, 242) and the uppermost surface of the second vertical alternating sequence (232, 242) or embedded within the second vertical alternating sequence (232, 242) constitutes the second-tier structure.

[0080] Referring to FIGS. 4a and 4b, a third vertical alternating sequence of a third insulating layer (332) and a third sacrificial material layer (342) may be formed. Each of the third insulating layers (332) is an insulating layer that extends continuously over the entire area of ​​the substrate (8) and may have a uniform thickness over the entire area. Each of the third sacrificial material layers (342) includes a dielectric material and may have a sacrificial material layer that extends continuously over the entire area of ​​the substrate (8) and may have a uniform thickness over the entire area. The third insulating layer (332) may have the same material composition and the same thickness as the first insulating layer (132). The third sacrificial material layer (342) may have the same material composition and the same thickness as the first sacrificial material layer (142).

[0081] Generally, at least one additional vertical alternating sequence of an additional insulating layer and an additional sacrificial material layer may be optionally formed on the first vertical alternating sequence (132, 142) and the first tier inverse stepped dielectric material portion (165).

[0082] A third stepped surface may be formed within the stepped region of an inter-array region (200) to be filled with a third-tier inverse stepped dielectric material portion (365). For example, a combination of a sacrificial hard mask layer and a trimming mask layer may be used to form the third stepped surface. In one embodiment, a row of multiple third stepped regions may be formed within each area corresponding to a combination of the interposed area and the area of ​​a pair of laterally adjacent pairs of the third-tier inverse stepped dielectric material portion (365). In this case, the multiple third stepped regions may subsequently be vertically offset by different depths by subsequently performing an area recess etching process.

[0083] A third dielectric fill material (such as undoped silicate glass (i.e., silicon oxide) or doped silicate glass) may be deposited in each third consecutive reverse stepped cavity. The third dielectric fill material may be flattened to remove excess portions of the second dielectric fill material from the horizontal plane, including the top surface of the third vertical alternating sequence (332, 342). Each remaining portion of the third dielectric fill material filling each third consecutive reverse stepped cavity constitutes a third tier reverse stepped dielectric material portion (365).

[0084] Generally, a third tier structure is formed comprising a third tier inverse stepped dielectric material portion (365) placed on the third stepped surface of the third vertical alternating sequence located in the third vertical alternating sequence of the third insulating layer (332) and the third sacrificial material layer (342) and the array inter-region (200).

[0085] FIGS. 5a through 5e are vertical cross-sectional views of various configurations of an exemplary structure after the formation of a third tier structure according to one embodiment of the present disclosure. The width of the vertical cross-sectional views illustrated in FIGS. 5a through 5e corresponds to the lateral range along the second horizontal direction (hd2) of three adjacent rear trench fill structures (76) to be subsequently formed with various configurations of the exemplary structure. In other words, the three adjacent rear trench fill structures (76) may be subsequently formed within the lateral range of each of the exemplified areas of the various exemplified configurations of the exemplary structure.

[0086] The configurations exemplified in FIGS. 5a through 5d adopt three tiers, and the configuration exemplified in FIG. 5e adopts two tiers. Various exemplified configurations of the exemplary structures of FIGS. 5a through 5e adopt an optional layer that may or may not be formed on each vertical alternating sequence of insulating layers (132, 232, 332) and sacrificial material layers (142, 242, 342). The optional layer may be referred to herein as a first insulating cap layer (170), a second insulating cap layer (270), and a third insulating cap layer (370). Each of the insulating cap layers (170, 270, 370) comprises an insulating material such as silicon oxide and may have a thickness in the range of 30 nm to 600 nm, e.g., 60 nm to 300 nm, but smaller or larger thicknesses may also be used.

[0087] Referring to FIG. 5a, a first configuration of an exemplary structure is illustrated, which includes a stack of a first inverse stepped dielectric material portion (165), a second inverse stepped dielectric material portion (265) having a smaller lateral range along the second horizontal direction (hd2) than the first inverse stepped dielectric material portion (165), and a third inverse stepped dielectric material portion (365) having a smaller lateral range along the second horizontal direction (hd2) than the second inverse stepped dielectric material portion (265).

[0088] Referring to FIG. 5b, a second configuration of an exemplary structure is illustrated, which includes a stack of two first inverse stepped dielectric material parts (165) spaced laterally from each other along a second horizontal direction (hd2), a second inverse stepped dielectric material part (265) having a smaller lateral range along the second horizontal direction (hd2) than the two first inverse stepped dielectric material parts (165), and a third inverse stepped dielectric material part (365) having a smaller lateral range along the second horizontal direction (hd2) than the second inverse stepped dielectric material part (265).

[0089] Referring to FIG. 5c, a third configuration of an exemplary structure is illustrated, which includes a stack of a first inverse stepped dielectric material portion (165), two second inverse stepped dielectric material portions (265), and a third inverse stepped dielectric material portion (365) having a smaller lateral range along the second horizontal direction (hd2) than the two second inverse stepped dielectric material portions (265).

[0090] Referring to FIG. 5d, a fourth configuration of an exemplary structure is illustrated, which comprises a stack of two first inverse stepped dielectric material parts (165) spaced laterally from each other along a second horizontal direction (hd2), two second inverse stepped dielectric material parts (265) having a smaller lateral range along the second horizontal direction (hd2) than the two first inverse stepped dielectric material parts (165), and a third inverse stepped dielectric material part (365) having a smaller lateral range along the second horizontal direction (hd2) than the two second inverse stepped dielectric material parts (265).

[0091] Referring to FIG. 5e, a fifth configuration of an exemplary structure is illustrated, which includes a stack of two first inverse stepped dielectric material parts (165) that are laterally spaced from each other along a second horizontal direction (hd2), and a second inverse stepped dielectric material part (265) that has a smaller lateral range along the second horizontal direction (hd2) than the two first inverse stepped dielectric material parts (165).

[0092] In one embodiment, a plurality of vertically stacked tier structures may be formed on a substrate (8). Each tier structure within the plurality of tier structures comprises a vertical alternating sequence of a continuous insulating layer (132, 232, 332) and a continuous sacrificial material layer (142, 242, 342). In one embodiment, among the plurality of tier structures, a first tier structure comprises a pair of first inverse stepped dielectric material portions (e.g., first tier inverse stepped dielectric material portions (165)) placed on a first vertical alternating sequence of a first continuous insulating layer (132, 232, 332) and a first continuous sacrificial material layer (142, 242, 342), as illustrated in FIG. 5b, 5d, and 5e. Furthermore, as illustrated in FIGS. 5b to 5e, among the plurality of tier structures, the second tier structure is placed on the first tier level and includes a second inverse stepped dielectric material portion (265 and / or 365) having a partial area overlap of each of the first inverse stepped dielectric material portions (165) in a plan view along a vertical direction perpendicular to the upper surface of the substrate (8).

[0093] FIGS. 6a through 6c are sequential vertical cross-sectional views of an exemplary structure during the formation of a tier-to-tier memory opening (49) according to one embodiment of the present disclosure.

[0094] Referring to FIG. 6a, an exemplary structure in a process step corresponding to the process steps of FIG. 4a and 4b and FIG. 5a through 5e is illustrated.

[0095] Referring to FIG. 6b, various third-tier openings may be formed through the third vertical alternating sequence (332, 342) and over the sacrificial first-tier opening fill portion. A photoresist layer (not shown) may be applied over the third vertical alternating sequence (332, 342) and lithographically patterned to form various openings. The pattern of openings within the photoresist layer may be transferred through the third vertical alternating sequence (332, 342) to form various third-tier openings simultaneously, i.e., during the third isotropic etching process.

[0096] Various third-tier openings may include a third-tier memory opening formed in a memory array region (100) and a third-tier support opening formed in an inter-array region (200). Each third-tier opening may be formed within one area of ​​each of the sacrificial second-tier opening fill portions. Thus, the upper surface of the sacrificial second-tier opening fill portions may be physically exposed at the bottom of each third-tier opening. Specifically, each third-tier memory opening (349) may be formed directly above each sacrificial second-tier memory opening fill portion (248), and each third-tier support opening may be formed directly above each sacrificial second-tier support opening fill portion. Each cluster of the third-tier memory openings (349) may be formed as a two-dimensional array of the third-tier memory openings (349). A third tier support opening (not shown) is an opening formed within the inter-array area (200) and subsequently used to form a support column structure. A subset of the third tier support openings may be formed by penetrating each horizontal surface of the third stepped surface.

[0097] Referring to FIG. 6c, the sacrificial first tier fill material of the sacrificial second tier opening fill portion (248) and the sacrificial first tier opening fill portion (148) can be removed using an etching process that selectively etches the sacrificial second tier fill material and the sacrificial first tier fill material with respect to the materials of the insulating layer (132, 232, 332) and the sacrificial material layer (142, 242, 342). The memory opening, also referred to as the inter-tier memory opening (49), is formed by the respective combination of the volume from which the sacrificial second tier memory opening fill portion (248) and the sacrificial first tier memory opening fill portion (148) are removed and the third tier memory opening (349). The support opening, also referred to as the inter-tier support opening (19), is formed by the respective combination of the volume from which the sacrificial second tier support opening fill portion and the sacrificial first tier support opening fill portion are removed and the third tier support opening. The inter-tier memory opening (49) extends through the third tier structure, the second tier structure, and the first tier structure. Generally, the memory opening (49) may be formed within each memory array region (100) in which each layer of the first vertical alternating sequence (132, 142), the second vertical alternating sequence (232, 242), and the third vertical alternating sequence (332, 342) exists.

[0098] FIGS. 7a through 7e illustrate sequential vertical cross-sectional views of a memory opening (49) during the formation of a memory opening fill structure (58) according to one embodiment of the present disclosure.

[0099] Referring to FIG. 7a, an inter-tier memory opening (49) in the processing step of FIG. 6c is illustrated.

[0100] Referring to FIG. 7b, a stack of layers comprising a blocking dielectric layer (52), a charge storage layer (54), a tunneling dielectric layer (56), and an optional sacrificial cover layer (57) may be sequentially deposited within the inter-tier memory opening (49). The blocking dielectric layer (52) may comprise a single dielectric material layer or a stack of multiple dielectric material layers. In one embodiment, the blocking dielectric layer may comprise a dielectric metal oxide layer composed essentially of a dielectric metal oxide. As used herein, a dielectric metal oxide refers to a dielectric material comprising at least one metallic element and at least oxygen. The dielectric metal oxide may essentially consist of at least one metallic element and oxygen, or may essentially consist of at least one metallic element, oxygen, and at least one non-metallic element such as nitrogen. In one embodiment, the blocking dielectric layer (52) may comprise a dielectric metal oxide having a dielectric constant greater than 7.9, i.e., a dielectric constant greater than the dielectric constant of silicon oxide. The thickness of the dielectric metal oxide layer may be in the range of 1 nm to 20 nm, but smaller and larger thicknesses may also be used. The dielectric metal oxide layer may subsequently function as a dielectric material portion that blocks stored electric charge from leaking to the control gate electrode. In one embodiment, the blocking dielectric layer (52) comprises aluminum oxide. Alternatively or additionally, the blocking dielectric layer (52) may comprise a dielectric semiconductor compound such as silicon oxide, silicon oxynitride, silicon nitride, or a combination thereof.

[0101] Subsequently, a charge storage layer (54) may be formed. In one embodiment, the charge storage layer (54) may be a continuous layer or a patterned discrete portion of a charge trapping material comprising a dielectric charge trapping material, which may be, for example, silicon nitride. Alternatively, the charge storage layer (54) may comprise a patterned discrete portion or a continuous layer of a conductive material, such as a metallic material or doped polysilicon, which is patterned into a plurality of electrically isolated portions (e.g., floating gates) by being formed, for example, within a lateral recess into a sacrificial material layer (142, 242, 342). In one embodiment, the charge storage layer (54) comprises a silicon nitride layer. In one embodiment, the sacrificial material layer (142, 242, 342) and the insulating layer (132, 232, 332) may have vertically aligned sidewalls, and the charge storage layer (54) may be formed as a single continuous layer. Alternatively, the sacrificial material layer (142, 242, 342) may be laterally recessed with respect to the sidewalls of the insulating layer (132, 232, 332), and a combination of a deposition process and an anisotropic etching process may be used to form the charge storage layer (54) as a plurality of vertically spaced memory material portions. The thickness of the charge storage layer (54) may be in the range of 2 nm to 20 nm, but smaller and larger thicknesses may also be used.

[0102] The tunneling dielectric layer (56) comprises a dielectric material in which charge tunneling can be performed under appropriate electric bias conditions. Charge tunneling can be performed via hot-carrier injection or by Fowler-Nodheim tunneling-induced charge transfer depending on the operating mode of the monolithic three-dimensional NAND string memory device to be formed. The tunneling dielectric layer (56) may comprise silicon oxide, silicon nitride, silicon oxynitride, dielectric metal oxide (such as aluminum oxide and hafnium oxide), dielectric metal oxynitride, dielectric metal silicate, alloys thereof, and / or combinations thereof. In one embodiment, the tunneling dielectric layer (56) may comprise a stack of a first silicon oxide layer, a silicon oxynitride layer, and a second silicon oxide layer, which is commonly known as an ONO stack. In one embodiment, the tunneling dielectric layer (56) may comprise a substantially carbon-free silicon oxide layer or a substantially carbon-free silicon oxynitride layer. The thickness of the tunneling dielectric layer (56) may be in the range of 2 nm to 20 nm, but smaller and larger thicknesses may also be used. A stack of the blocking dielectric layer (52), the charge storage layer (54), and the tunneling dielectric layer (56) constitutes a memory film (50) that stores memory bits.

[0103] The sacrificial cover material layer (57) may include a sacrificial material that can be selectively and subsequently removed from the material of the tunneling dielectric layer (56). For example, the sacrificial cover layer may include a semiconductor material (e.g., amorphous silicon), silicon oxide, or a carbon-based material (such as amorphous carbon or diamond-like carbon). The thickness of the sacrificial cover layer may be in the range of 1 nm to 10 nm, but smaller and larger thicknesses may also be used.

[0104] Referring to FIG. 7c, an anisotropic etching process may be performed to remove the horizontal portions of the sacrificial cover layer (57), the tunneling dielectric layer (56), the charge storage layer (54), and the blocking dielectric layer (52). The remaining cylindrical portion of the sacrificial cover layer (57) may be selectively removed from the material of the tunneling dielectric layer (56) during the anisotropic etching process or by an isotropic etching process (e.g., wet etching process) or ashing. Alternatively, if the sacrificial cover layer (57) comprises a semiconductor material (e.g., amorphous silicon), it may be retained thereafter.

[0105] Referring to FIG. 7d, a semiconductor channel material layer (60L) may be deposited by a conformal deposition process. The semiconductor channel material layer (60L) comprises a p-doped semiconductor material, such as at least one elemental semiconductor material, at least one III-V compound semiconductor material, at least one II-VI compound semiconductor material, at least one organic semiconductor material, or other semiconductor materials known in the art. In one embodiment, the semiconductor channel material layer (60L) may have uniform doping. In one embodiment, the semiconductor channel material layer (60L) has a p-type dopant (such as a boron atom) of 1.0 x 10⁻⁶ 12 / cm 3 Up to 1.0 x 10 18 / cm 3 Range, e.g., 1.0 x 10 14 / cm 3 Up to 1.0 x 10 17 / cm 3 It has p-type doping present at an atomic concentration of . In one embodiment, the semiconductor channel material layer (60L) comprises boron-doped amorphous silicon or boron-doped polysilicon and / or is essentially composed of these. In another embodiment, the semiconductor channel material layer (60L) has an n-type dopant (such as phosphorus atoms or arsenic atoms) of 1.0 x 10⁻⁶ 12 / cm 3 Up to 1.0 x 10 18 / cm 3 , for example 1.0 x 10 14 / cm 3 Up to 1.0 x 10 17 / cm 3 It has n-type doping present at an atomic concentration. The semiconductor channel material layer (60L) can be formed by a conformal deposition method such as low pressure chemical vapor deposition (LPCVD). The thickness of the semiconductor channel material layer (60L) may be in the range of 2 nm to 10 nm, but smaller and larger thicknesses may also be used. A cavity (49') is formed in the volume of each inter-tier memory opening (49) that is not filled with the deposited material layer (52, 54, 56, 60L).

[0106] Referring to FIG. 7e, if the cavity (49') within each memory opening is not completely filled by the semiconductor channel material layer (60L), a dielectric core layer may be deposited within the cavity (49') to fill any remaining portion of the cavity (49') within each memory opening. The dielectric core layer comprises a dielectric material such as silicon oxide or organosilicate glass. The dielectric core layer may be deposited by a conformal deposition method such as LPCVD (low pressure chemical vapor deposition) or by a self-planarizing deposition process such as spin coating. The horizontal portion of the dielectric core layer placed over the upper second continuous insulating layer (232L) may be removed, for example, by recess etching. Recess etching continues until the upper surface of the remaining portion of the dielectric core layer is recessed to a height between the upper surface and the bottom surface of the upper second insulating layer (232). Each remaining portion of the dielectric core layer constitutes a dielectric core (62).

[0107] Referring to FIG. 7f, a doped semiconductor material having a second type of conductivity doping can be deposited in a cavity that lies over a dielectric core (62). The second type of conductivity is opposite to the first type of conductivity. For example, if the first type of conductivity is p-type, the second type of conductivity is n-type, and vice versa. The portions of the deposited doped semiconductor material, semiconductor channel material layer (60L), tunneling dielectric layer (56), charge storage layer (54), and blocking dielectric layer (52) that lie on a horizontal plane, including the upper surface of the second insulating cap layer (232), can be removed by a planarization process such as a chemical mechanical planarization (CMP) process.

[0108] Each remaining portion of the doped semiconductor material of the second conductive type constitutes a drain region (63). The dopant concentration within the drain region (63) is 5.0 x 10⁻⁶ 18 / cm 3 Up to 2.0 x 10 21 / cm 3 It may be in the range, but lower or higher dopant concentrations may also be used. The doped semiconductor material may be, for example, doped polysilicon.

[0109] Each remaining portion of the semiconductor channel material layer (60L) forms a vertical semiconductor channel (60), thereby allowing current to flow when the vertical NAND device containing the vertical semiconductor channel (60) is turned on. The tunneling dielectric layer (56) is surrounded by the charge storage layer (54) and laterally surrounds the vertical semiconductor channel (60). Each adjacent set of the blocking dielectric layer (52), the charge storage layer (54), and the tunneling dielectric layer (56) collectively forms a memory film (50), which can store electric charge over a macroscopic retention time. In some embodiments, the blocking dielectric layer (52) may not be present in the memory film (50) at this stage, and the blocking dielectric layer may be subsequently formed after the formation of the back recesses. As used herein, a macroscopic retention time refers to a retention time suitable for operation of the memory device as a permanent memory device, such as a retention time exceeding 24 hours.

[0110] Each combination of a memory film (50) and a vertical semiconductor channel (60) (which is a vertical semiconductor channel) within a tier-to-tier memory opening (49) constitutes a memory stack structure (55). The memory stack structure (55) is a combination of a plurality of memory elements including a portion of a vertical semiconductor channel (60), a tunneling dielectric layer (56), and a charge storage layer (54), and an optional blocking dielectric layer (52). The memory stack structure (55) may be formed by penetrating the memory array region (100) of the first and second vertical alternating sequences, in which all layers of the first and second vertical alternating sequences exist. Each combination of the memory stack structure (55), the dielectric core (62), and the drain region (63) within the tier-to-tier memory opening (49) constitutes a memory opening fill structure (58). Generally, the memory opening fill structure (58) is formed within the memory opening (49). Each memory opening fill structure (58) includes each memory film (50) and each vertical semiconductor channel (60).

[0111] In one embodiment, each memory stack structure (55) comprises a vertical NAND string comprising each vertical stack of memory elements (including a portion of a charge storage layer (54) located at the level of the sacrificial material layer (142, 242, 342)), and a vertical semiconductor channel (60) extending vertically through the sacrificial material layer (142, 242, 342) near each vertical stack of memory elements.

[0112] Referring to FIGS. 8a and 8b, an exemplary structure is illustrated after the processing step of FIG. 7f, that is, after the formation of the memory opening fill structure (58) of the memory opening (49). In one embodiment, a support pillar structure (not shown) may be formed in the support opening. Generally, each memory opening fill structure (58) comprises a vertical stack of memory elements located at the level of the electrically conductive layers (146, 246, 346) within a plurality of tier structures, and further comprises a vertical semiconductor channel (60) extending vertically through the plurality of tier structures.

[0113] Subsequently, as illustrated in FIG. 8b, a rear trench (79) may be formed extending laterally along a first horizontal direction (hd1) through a plurality of tier structures. The location of the rear trench (79) may be the same as the location of the rear trench fill structure (76) exemplified in FIG. 1a and FIG. 1e. Each vertical alternating sequence is divided into a set of alternating stacks of insulating layers (132, 232, 332) and sacrificial material layers (142, 242, 342) that are laterally spaced along a second horizontal direction (hd2) {(132, 142), (232, 242), (332, 342)}.

[0114] In one embodiment, the first back trench (79) divides each dielectric material portion (165, 265, 365) into a pair of inverse stepped dielectric material portions (such as the first tier inverse stepped dielectric material portion (265), the second tier inverse stepped dielectric material portion (265), and / or the third tier inverse stepped dielectric material portion (365). Generally, a plurality of vertically stacked tier structures may be formed on the substrate (8). Each tier structure within the plurality of tier structures comprises a set of alternating stacks of insulating layers (132, 232, 332) and sacrificial material layers (142, 242, 342). A first tier structure within a plurality of tier structures comprises a pair of first inverse stepped dielectric portions (such as the first tier inverse stepped dielectric material portion (165)) that are placed on each of the first alternating stacks of the first insulating layer (132) and the first sacrificial material layer (142), and a second tier structure comprises a pair of second inverse stepped dielectric material portions (265) that are placed on the first tier level and have partial area overlap with each of the pair of first inverse stepped dielectric material portions (165) in a plan view along a vertical direction perpendicular to the upper surface of the substrate (8).

[0115] Referring to FIG. 9, the sacrificial material layer (142, 242, 342) can be selectively isotropically etched for the insulating layer (132, 232, 332), the first inverse stepped dielectric material part (such as the first tier inverse stepped dielectric material part (165) or the second tier inverse stepped dielectric material part (265)), the second inverse stepped dielectric material part (such as the second tier inverse stepped dielectric material part (265) or the third layer inverse stepped dielectric material part (365)), and any additional inverse stepped dielectric material part by supplying an isotropic etching agent to the back trench (79).

[0116] Generally, the sacrificial material layer (142, 242, 342) can be selectively isotropically etched with respect to the insulating layer (132, 232, 332), the inverse step dielectric material portion (165, 265, 365), and the semiconductor material layer (110) by supplying an isotropic etching agent to the back trench. For example, an etching agent that selectively etches the material of the sacrificial material layer (142, 242, 342) with respect to the material of the insulating layer (132, 232, 332), the inverse step dielectric material portion (165, 265, 365), and the material of the outermost layer of the memory film (50) can be introduced into the back trench, for example, using an isotropic etching process. For example, the sacrificial material layer (142, 242, 342) may include silicon nitride, and the material of the insulating layer (132, 232, 332), the inverse step-type dielectric material portion (165, 265, 365), and the outermost layer of the memory film (50) may include silicon oxide material.

[0117] The isotropic etching process may be a wet etching process using a wet etching solution, or a vapor phase (dry) etching process in which an etchant is introduced into the back trench in a vapor phase. For example, if the sacrificial material layer (142, 242, 342) comprises silicon nitride, the etching process may be a wet etching process in which the exemplary structure is immersed in a wet etching tank containing phosphoric acid, which selectively etches silicon nitride against silicon oxide, silicon, and various other materials used in the art.

[0118] A rear recess (143, 243, 343) is formed within a volume from which a sacrificial material layer (142, 242, 342) is removed. The rear recess (143, 243, 343) includes a first rear recess (143) formed within a volume from which a first sacrificial material layer (142) is removed, a second rear recess (243) formed within a volume from which a second sacrificial material layer (242) is removed, and a third rear recess (343) formed within a volume from which a third sacrificial material layer (342) is removed. Each of the rear recesses (143, 243, 343) may be a laterally extending cavity having lateral dimensions that exceed the vertical range of the cavity. In other words, the lateral dimensions of each of the rear recesses (143, 243, 343) may exceed the height of each rear recess. A plurality of rear recesses (143, 243, 343) may be formed within the volume from which the material of the sacrificial material layer (142, 242, 342) is removed. Each of the rear recesses (143, 243, 343) may extend substantially parallel to the upper surface of the semiconductor material layer (110). The rear recesses (143, 243, 343) may be vertically bounded by the upper surface of the insulating layer (132, 232, 332) placed below and the bottom surface of the insulating layer (132, 232, 332) placed above. In one embodiment, each of the rear recesses (143, 243, 343) may have a uniform height over the entire length.

[0119] Referring to FIGS. 10a and 10b, an optional back-blocking dielectric layer (not shown) may be optionally deposited within the back-recess (143, 243, 343) and back-trench. The back-blocking dielectric layer comprises a dielectric material such as a dielectric metal oxide (e.g., aluminum oxide), silicon oxide, or a combination thereof.

[0120] An electrically conductive layer (146, 246, 346) may be deposited on the remaining volume of the rear recess (143, 243, 343) by performing a conformal deposition process in which a precursor gas for the conductive material of the electrically conductive layer (146, 246, 346) penetrates the rear trench (79) and is supplied to the rear recess (143, 243, 343). At least one conductive material may be deposited within a plurality of rear recesses (143, 243, 343), on the sidewalls of the rear trench, and on the top tier structure. At least one conductive material may be deposited by a conformal deposition method, which may be, for example, chemical vapor deposition (CVD), atomic layer deposition (ALD), electroless plating, electroplating, or a combination thereof. At least one conductive material may include an elemental metal, an intermetallic alloy of at least two elemental metals, a conductive nitride of at least one elemental metal, a conductive metal oxide, a conductive doped semiconductor material, a conductive metal-semiconductor alloy such as a metal silicide, alloys thereof, and combinations thereof or stacks thereof.

[0121] In one embodiment, at least one conductive material may comprise at least one metallic material, that is, an electrically conductive material comprising at least one metallic element. Non-limiting exemplary metallic materials that may be deposited within the back recess (143, 243, 343) include tungsten, tungsten nitride, titanium, titanium nitride, tantalum, tantalum nitride, cobalt, and ruthenium. For example, at least one conductive material may comprise a conductive metal nitride material such as TiN, TaN, WN, or a combination thereof, and a conductive metal nitride liner comprising a conductive fill material such as W, Co, Ru, Mo, Cu, or a combination thereof. In one embodiment, at least one conductive material for filling the back recess (143, 243, 343) may be a combination of a titanium nitride layer and a tungsten fill material.

[0122] An electrically conductive layer (146, 246, 346) may be formed within a rear recess (143, 243, 343) by the deposition of at least one conductive material. A plurality of first electrically conductive layers (146) may be formed within a plurality of first rear recesses (143), a plurality of second electrically conductive layers (246) may be formed within a plurality of second rear recesses (243), a plurality of third electrically conductive layers (346) may be formed within a plurality of third rear recesses (343), and a continuous metallic material layer (not shown) may be formed on the sidewalls of each rear trench and on the top tier structure. Each of the electrically conductive layers (146, 246, 346) may comprise a conductive metallic nitride liner and a conductive fill material. Accordingly, each sacrificial material layer (142, 242, 342) can be replaced with an electrically conductive layer (146, 246, 346). Specifically, each first sacrificial material layer (142) can be replaced with an optional portion of the rear blocking dielectric layer and the first electrically conductive layer (146), each second sacrificial material layer (242) can be replaced with an optional portion of the rear blocking dielectric layer and the second electrically conductive layer (246), and each third sacrificial material layer (342) can be replaced with an optional portion of the rear blocking dielectric layer and the third electrically conductive layer (346). A rear cavity exists in the portion of each rear trench that is not filled with a continuous metallic material layer.

[0123] A continuous metallic material layer is formed in the surrounding area of ​​the rear trench (79) and on a plurality of tier structures during the formation of the electrically conductive layer (146, 246, 346).

[0124] The residual conductive material of the continuous metallic material layer can be removed from within the rear trench (79) and from above the plurality of tier structures. Specifically, the deposited metallic material of the continuous metallic material layer can be etched back from the sidewalls of each rear trench and from above the top tier structure, for example, by anisotropic or isotropic etching. Each remaining portion of the deposited metallic material within the first rear recess forms the first electrically conductive layer (146). Each remaining portion of the deposited metallic material within the second rear recess forms the second electrically conductive layer (246). Each remaining portion of the deposited metallic material within the third rear recess forms the third electrically conductive layer (346). The sidewalls of the electrically conductive layers (146, 246, 346) can be physically exposed to each rear trench (79).

[0125] Each electrically conductive layer (146, 246, 346) may be a conductive sheet including an opening. A first subset of openings penetrating each electrically conductive layer (146, 246, 346) may be filled with a memory opening fill structure (58). A second subset of openings penetrating each electrically conductive layer (146, 246, 346) may be filled with a support column structure (20).

[0126] A subset of the electrically conductive layers (146, 246, 346) may include word lines for memory elements. A semiconductor device within the semiconductor device (720) placed underneath may include a word line switch device configured to control a bias voltage for each word line, and / or a bit line driver device such as a sense amplifier. A memory-level assembly is located on the substrate semiconductor layer (9). The memory-level assembly includes at least one alternating stack (132, 146, 232, 246, 332, 346) and a memory stack structure (55) extending vertically through at least one alternating stack (132, 146, 232, 246, 332, 346). Each memory stack structure (55) includes a vertical stack of memory elements located at each level of the electrically conductive layers (146, 246, 346).

[0127] FIGS. 11a through 11d are schematic vertical cross-sectional views of various configurations of the exemplary structure of FIGS. 10a and FIGS. 10b. Referring to FIGS. 11a through 11d, a rear trench fill structure (76) is formed in the volume of the rear trench (79) after the removal of a continuous metallic material layer.

[0128] A rear trench fill structure (76) may be formed within each rear trench (79). In one embodiment, an insulating liner layer comprising a dielectric material (such as silicon oxide) may be conformally deposited on the periphery of each rear trench and may be anisotropically etched to form an insulating spacer within each rear trench. At least one conductive material may be deposited on the remaining volume of the rear trench, and any excess of the at least one conductive material may be removed from the top tier structure by a planarization process. Each remainder of the at least one conductive material, in contact with the source region and laterally surrounded by each insulating spacer, constitutes a rear contact via structure extending laterally along the first horizontal direction (hd1). Each successive combination of the insulating spacer and the rear contact via structure filling the rear trench constitutes the trench fill structure (76).

[0129] Alternatively, at least one dielectric material, such as silicon oxide, may be conformally deposited within the back trench by a conformal deposition process. Each portion of the deposited dielectric material filling the back trench constitutes a back trench fill structure (76). In this case, each back trench fill structure may fill the entire volume of the back trench and may essentially consist of at least one dielectric material. In this alternative embodiment, the source region may be omitted, and a horizontal source line (e.g., a direct strap contact layer) may be in contact with the side of the lower portion of the semiconductor channel (60).

[0130] Various contact via structures may subsequently be formed. Various contact via structures may include drain contact via structures (not shown) formed within a memory array region (100) on the upper surface of each drain region (63). Various contact via structures may include layer contact via structures (86A, 86B, 86C) formed in an inter-array region (200) as illustrated in FIGS. 1a through 1e. The layer contact via structures (86A, 86B, 86C) may include a first contact via structure (86A) in contact with each first electrically conductive layer (146), a second contact via structure (86B) in contact with each second electrically conductive layer (246), and a third contact via structure (86C) in contact with each third electrically conductive layer (346).

[0131] Referring collectively to FIGS. 11b, 11d, and 11e, the first inverse stepped dielectric material portion (165) is not physically exposed to any of the rear trenches (79) during rear trench formation. In some embodiments, the second inverse stepped dielectric material portion (such as the second tier inverse stepped dielectric material portion (265) and / or the third tier inverse stepped dielectric material portion (365)) is cut by the first rear trench subset during the formation of the rear trench (79), and the cut portion of the second inverse stepped dielectric material portion is physically exposed to the first rear trench subset and not to the second rear trench subset. Accordingly, each cut portion of the second inverse stepped dielectric material portion (such as the second tier inverse stepped dielectric material portion (265) and / or the third tier inverse stepped dielectric material portion (365)) may be physically exposed only to each first rear trench and not physically exposed to any other rear trench other than each first rear trench.

[0132] In one embodiment, each of the first tier inverse stepped dielectric material portions (165) may have a first width (D1) along the second horizontal direction (hd2) on the top surface, each of the second tier inverse stepped dielectric material portions (265) may have a second width (D2) along the second horizontal direction (hd2) on the top surface, and each of the third tier inverse stepped dielectric material portions (365) may have a third width (D3) along the second horizontal direction (hd2) on the top surface. The first width (D1) exceeds the second width (D2), and the second width (D2) exceeds the third width (D3).

[0133] Referring to the embodiments of the present disclosure and all the drawings, a multi-tier memory device comprises a substrate (8) and a plurality of tier structures located at multi-tier levels spaced vertically apart from the substrate (8) by different vertical intervals. Each of the plurality of tier structures includes a rear trench fill structure (76) that extends laterally through each of the plurality of tier structures along a first horizontal direction (hd1) and is spaced laterally from each other along a second horizontal direction (hd2). Each of the plurality of tier structures also includes an alternating stack of insulating layers (132, 232, 332) and electrically conductive layers (146, 246, 346) that are laterally spaced from each other along the second horizontal direction (hd2) by a rear trench fill structure (76) and extend laterally along the first horizontal direction (hd1) through an inter-array region (200), a first memory array region (100A), and a second memory array region (100B) that is laterally spaced from the first memory array region (100A) along the first horizontal direction (hd1) by the inter-array region (200). Each of the plurality of tier structures further includes a memory opening fill structure (58) that extends vertically through each of the plurality of tier structures. Each memory opening fill structure (58) includes a vertical stack of memory elements (e.g., parts of the charge storage region (54) of the memory film) located at the level of each vertical semiconductor channel (60) and electrically conductive layer (146, 246, 346).

[0134] Each alternating stack includes a stepped surface of the inter-array region (200). Each electrically conductive layer (146, 246, 346) within the alternating stack has a respective bridge region (240) having a respective strip width (E1, E2, E3) along the second horizontal direction (hd2) within the inter-array region (200), and a respective uniform width along the second horizontal direction (hd2) that exceeds the strip width of the first memory array region (100A), the second memory array region (100B), and the portion of the inter-array region (200) located outside the bridge region (240). The strip width (E1) of the uppermost electrically conductive layer (146) of the first tier alternating stack (132, 146) is smaller than the strip width (E2) of the uppermost electrically conductive layer (246) of the second tier alternating stack (232, 246) placed on top of the first tier alternating stack (132, 146).

[0135] In some embodiments illustrated in FIGS. 11a through 11d, the strip width (E2) of the top electrically conductive layer (246) of the second tier alternating stack (232, 246) is smaller than the strip width (E3) of the top electrically conductive layer (346) of the third tier alternating stack (332, 346) placed on top of the second tier alternating stack (232, 246).

[0136] In one embodiment, each rear trench fill structure (76) includes a dielectric material portion that extends continuously from the upper surface of the substrate to the uppermost surface of the plurality of tier structures. In one embodiment, each of the plurality of tier structures further includes a reverse stepped dielectric material portion (165, 265, 365) that contacts the stepped surface of each alternating stack in the inter-array region (200).

[0137] In some embodiments illustrated in FIG. 11b and FIG. 11e, a pair of first inverse stepped dielectric material portions (165) are located at a first tier level and each includes a pair of bottom surfaces that are laterally spaced from the first rear trench fill structure (761) of the rear trench fill structure (76) along the second horizontal direction (hd2). A pair of second inverse stepped dielectric material portions (265) are located at a second tier level that is positioned above the first tier level and each includes a pair of bottom surfaces that are in contact with the respective longitudinal sidewalls of the first rear trench fill structure (761).

[0138] In the embodiment illustrated in FIG. 11b and FIG. 11e, each electrically conductive layer (146) within the first tier alternating stack (132, 146) has each first bridge region (240A) having a first portion of each strip width (E1) and each second bridge region (240B) having a second portion of each strip width (E1). For example, if E3 is equal to width Y, E2 = 2 / 3Y and E1 = 1 / 3Y, and (if the widths of the first and second parts are the same) the first and second parts of E1 are equal to 1 / 6Y. The first bridge region (240A) is located between the first rear trench fill structure (761) and the second rear trench fill structure (762) of the trench fill structure (76) along the second horizontal direction (hd2). The first of a pair of first reverse stepped dielectric material portions (165) (e.g., the one on the left) is located between the first bridge region and the second bridge region (761, 762) along the second horizontal direction (hd2). Conversely, each electrically conductive layer (246) within the second tier alternating stack (232, 246) has a bridge region (240A) having a strip width between the first rear trench fill structure and the second rear trench fill structure (761, 762) along the second horizontal direction (hd2).

[0139] In an alternative embodiment of FIG. 11c, the electrically conductive layer (246) of the second tier alternating stack has divided bridge regions (240A and 240B), whereas the electrically conductive layers (146, 346) of the first tier alternating stack and the third tier alternating stack have a single bridge region (240A).

[0140] In an alternative embodiment of FIG. 11d, the electrically conductive layers (146, 246) of the first tier alternating stack and the second tier alternating stack have separate bridge regions (240A and 240B), whereas the electrically conductive layer (346) of the third tier alternating stack has a single bridge region (240A).

[0141] In the embodiment illustrated in FIG. 11b and FIG. 11e, each of the pair of second inverse stepped dielectric material portions (265) contacts the respective longitudinal sidewalls of the first rear trench fill structure (761) between a horizontal plane containing the lowest surface of the pair of second inverse stepped dielectric material portions and a horizontal plane containing the uppermost surface of the pair of second inverse stepped dielectric material portions. Conversely, each of the pair of first inverse stepped dielectric material portions (165) is laterally spaced apart from the first rear trench fill structure (761) and does not contact it.

[0142] In the embodiment illustrated in FIG. 11b and FIG. 11e, the rear trench fill structure (76) includes a second rear trench fill structure (762) and a third rear trench fill structure (763) that are closest neighbors to the rear trench fill structure of the first rear trench fill structure (761). Each of the pair of first inverse stepped dielectric material portions (165) is laterally spaced along the second horizontal direction (hd2) without contacting the second rear trench fill structure (762) and the third rear trench fill structure (763). Each of the pair of second inverse stepped dielectric material portions (265) is laterally spaced along the second horizontal direction (hd2) without contacting the second rear trench fill structure (762) and the third rear trench fill structure (763).

[0143] In one embodiment, the width (D1) of one of the pair of first inverse stepped dielectric material parts (165) along the second horizontal direction (h2) exceeds the width (D2) of one of the pair of second inverse stepped dielectric material parts (265) along the second horizontal direction (hd2).

[0144] In one embodiment, a pair of third inverse step dielectric material portions (365) of the inverse step dielectric material portions are located at a third tier level that is positioned above a second tier level and each includes a pair of bottommost surfaces that are in direct contact with a first rear trench fill structure (761).

[0145] In one embodiment, the layer contact via structure (86A) extends vertically through the inverse stepped dielectric material portions (165, 265, 365) and contacts each of the electrically conductive layers (146).

[0146] While the foregoing refers to specific embodiments, it will be understood that the present disclosure is not so limited. It will come to those skilled in the art that various modifications may be made to the disclosed embodiments and that such modifications are intended to be within the scope of the present disclosure. Compatibility is presumed between all non-alternative embodiments. The word “comprise” or “include” considers all embodiments in which the word “consist essentially of” or the word “consist essentially of” replaces the word “comprise” unless otherwise expressly stated. Where embodiments using a specific structure and / or configuration are exemplified in the present disclosure, it is understood that the present disclosure may be practiced with any other compatible structure and / or configuration that is functionally equivalent, unless such substitution is expressly prohibited or otherwise known to be impossible to those skilled in the art. All publications, patent applications, and patents cited herein are incorporated herein in their entirety.

Claims

Claim 1 A multi-tier memory device comprises: a substrate; and a plurality of tier structures located at multi-tier levels vertically spaced from the substrate by different vertical intervals, wherein each of the plurality of tier structures comprises: a rear trench fill structure extending laterally through each of the plurality of tier structures along a first horizontal direction and laterally spaced from each other along a second horizontal direction; an alternating stack of an insulating layer and an electrically conductive layer extending laterally along the first horizontal direction through an inter-array region, a first memory array region, and a second memory array region that is laterally spaced from the first memory array region along the first horizontal direction by the inter-array region and is laterally spaced from each other along the second horizontal direction by the rear trench fill structure; and a memory opening fill structure extending vertically through each of the plurality of tier structures, wherein each of the memory opening fill structures comprises a vertical stack of memory elements located at the level of each vertical semiconductor channel and the electrically conductive layer, wherein each of the alternating stacks comprises a stepped surface of the inter-array region; Each electrically conductive layer within the alternating stack has a respective bridge region having a respective strip width along the second horizontal direction within the inter-array region, and each has a uniform width along the second horizontal direction exceeding the strip width of the first memory array region, the second memory array region, and the inter-array region portion located outside the bridge region; a multi-tier memory device in which the strip width of the uppermost electrically conductive layer of the first tier alternating stack is less than the strip width of the uppermost electrically conductive layer of the second tier alternating stack placed on top of the first tier alternating stack. Claim 2 A multi-tier memory device according to claim 1, wherein the strip width of the uppermost electrically conductive layer of the second tier alternating stack is less than the strip width of the uppermost electrically conductive layer of the third tier alternating stack placed on top of the second tier alternating stack; and each rear trench fill structure comprises a dielectric material portion that extends continuously from the upper surface of the substrate to the uppermost surface of the plurality of tier structures. Claim 3 A multi-tier memory device according to claim 1, wherein each of the plurality of tier structures further comprises a portion of an inversely stepped dielectric material that contacts the stepped surface of the inter-array region. Claim 4 A multi-tier memory device according to claim 3, wherein a pair of first inverse stepped dielectric material portions of the inverse stepped dielectric material portions are located at a first tier level and each includes a pair of bottommost surfaces spaced laterally from the first rear trench fill structure of the rear trench fill structure along the second horizontal direction; and a pair of second inverse stepped dielectric material portions of the inverse stepped dielectric material portions are located at a second tier level that is positioned above the first tier level and each includes a pair of bottommost surfaces in contact with the respective longitudinal sidewalls of the first rear trench fill structure. Claim 5 A multi-tier memory device according to claim 4, wherein each electrically conductive layer in the first tier alternating stack has each first bridge region having a first portion of each strip width and each second bridge region having a second portion of each strip width; the first bridge region is located between the first rear trench fill structure and the second rear trench fill structure of the trench fill structure along the second horizontal direction; the first portion of the pair of first inverse stepped dielectric material portions is located between the first bridge region and the second bridge region along the second horizontal direction; and each electrically conductive layer in the second tier alternating stack has one bridge region having each strip width between the first rear trench fill structure and the second rear trench fill structure along the second horizontal direction. Claim 6 A multi-tier memory device, wherein each of the pair of second inverse stepped dielectric material portions contacts the respective longitudinal sidewalls of the first rear trench fill structure between a horizontal plane including the lowest surface of the pair of second inverse stepped dielectric material portions and a horizontal plane including the uppermost surface of the pair of second inverse stepped dielectric material portions; and each of the pair of first inverse stepped dielectric material portions is laterally spaced from the first rear trench fill structure and does not contact it. Claim 7 A multi-tier memory device according to claim 6, wherein the rear trench fill structure comprises a second rear trench fill structure and a third rear trench fill structure adjacent to the rear trench fill structure of the first rear trench fill structure; each of the pair of first inverse stepped dielectric material portions is laterally spaced along the second horizontal direction without contacting the second rear trench fill structure and the third rear trench fill structure; and each of the pair of second inverse stepped dielectric material portions is laterally spaced along the second horizontal direction without contacting the second rear trench fill structure and the third rear trench fill structure. Claim 8 A multi-tier memory device according to claim 4, wherein the width of one of the pair of first inverse step-shaped dielectric material portions along the second horizontal direction exceeds the width of one of the pair of second inverse step-shaped dielectric material portions along the second horizontal direction. Claim 9 A multi-tier memory device according to claim 4, wherein a pair of third inverse step dielectric material portions of the inverse step dielectric material portions are located at a third tier level positioned above a second tier level and each includes a pair of bottommost surfaces in direct contact with the first rear trench fill structure. Claim 10 A multi-tier memory device according to claim 3, further comprising a layer contact via structure that extends vertically through the inverse step-shaped dielectric material portion and contacts each of the electrically conductive layers. Claim 11 A method for forming a semiconductor device, comprising the steps of: forming a plurality of tier structures located at multi-tier levels vertically spaced from a substrate by different vertical spacings; wherein each of the plurality of tier structures comprises: an inter-array region, a first memory array region, and a second memory array region that is laterally spaced from the first memory array region along a first horizontal direction by the inter-array region, and extending laterally along the first horizontal direction through the inter-array region; and a memory opening fill structure extending vertically through each of the plurality of tier structures, wherein each of the memory opening fill structures comprises a vertical stack of memory elements located at the level of each vertical semiconductor channel and the sacrificial material layer; forming a back trench through the alternating stack of the insulating layer and the sacrificial material layer; and replacing the sacrificial material layer with an electrically conductive layer through the back trench to convert the alternating stack of the insulating layer and the sacrificial material layer into an alternating stack of the insulating layer and the electrically conductive layer. The method comprises the step of filling the rear trench with a rear trench fill structure that extends laterally through each of the plurality of tier structures along the first horizontal direction and is laterally spaced from each other along the second horizontal direction; wherein the electrically conductive layers are laterally spaced from each other along the second horizontal direction by the rear trench fill structure; and each of the alternating stacks of the insulating layer and the electrically conductive layer comprises a stepped surface of the inter-array region; and each electrically conductive layer within the alternating stack of the insulating layer and the electrically conductive layer has a respective bridge region having a respective strip width along the second horizontal direction within the inter-array region, and has a respective uniform width along the second horizontal direction that exceeds the strip width of the first memory array region, the second memory array region, and the portion of the inter-array region located outside the bridge region;A method for forming a semiconductor device, wherein the strip width of the uppermost electrically conductive layer of a first-tier alternating stack of insulating layers and electrically conductive layers is less than the strip width of the uppermost electrically conductive layer of a second-tier alternating stack of insulating layers and electrically conductive layers placed on top of the first-tier alternating stack of insulating layers and electrically conductive layers.; Claim 12 A method for forming a semiconductor device according to claim 11, wherein the strip width of the uppermost electrically conductive layer of the second tier alternating stack is less than the strip width of the uppermost electrically conductive layer of the third tier alternating stack placed on top of the second tier alternating stack; and each of the rear trench fill structures comprises a dielectric material portion that extends continuously from the upper surface of the substrate to the uppermost surface of the plurality of tier structures. Claim 13 A method for forming a semiconductor device according to claim 11, further comprising the step of forming each inverse step-shaped dielectric material portion in contact with the stepped surface of the inter-array region. Claim 14 A method for forming a semiconductor device according to claim 13, wherein a pair of first inverse step dielectric material portions of the inverse step dielectric material portions are located at a first tier level and each includes a pair of bottom surfaces spaced laterally from the first rear trench fill structure of the rear trench fill structure along the second horizontal direction; and a pair of second inverse step dielectric material portions of the inverse step dielectric material portions are located at a second tier level that is positioned above the first tier level and each includes a pair of bottom surfaces in contact with the respective longitudinal sidewalls of the first rear trench fill structure. Claim 15 A method for forming a semiconductor device according to claim 14, wherein each electrically conductive layer in the first tier alternating stack has each first bridge region having a first portion of each strip width and each second bridge region having a second portion of each strip width; the first bridge region is located between the first rear trench fill structure and the second rear trench fill structure of the trench fill structure along the second horizontal direction; the first portion of the pair of first inverse stepped dielectric material portions is located between the first bridge region and the second bridge region along the second horizontal direction; and each electrically conductive layer in the second tier alternating stack has one bridge region having each strip width between the first rear trench fill structure and the second rear trench fill structure along the second horizontal direction. Claim 16 A method for forming a semiconductor device according to claim 14, wherein each of the pair of second inverse stepped dielectric material portions contacts each longitudinal sidewall of the first rear trench fill structure between a horizontal plane including the lowest surface of the pair of second inverse stepped dielectric material portions and a horizontal plane including the uppermost surface of the pair of second inverse stepped dielectric material portions; and each of the pair of first inverse stepped dielectric material portions is laterally spaced apart from the first rear trench fill structure and does not contact it. Claim 17 A method for forming a semiconductor device according to claim 16, wherein the rear trench fill structure comprises a second rear trench fill structure and a third rear trench fill structure adjacent to the rear trench fill structure of the first rear trench fill structure; each of the pair of first inverse stepped dielectric material portions is laterally spaced along the second horizontal direction without contacting the second rear trench fill structure and the third rear trench fill structure; and each of the pair of second inverse stepped dielectric material portions is laterally spaced along the second horizontal direction without contacting the second rear trench fill structure and the third rear trench fill structure. Claim 18 A method for forming a semiconductor device according to claim 14, wherein the width of one of the pair of first inverse step-shaped dielectric material portions along the second horizontal direction exceeds the width of one of the pair of second inverse step-shaped dielectric material portions along the second horizontal direction. Claim 19 A method for forming a semiconductor device according to claim 14, wherein a pair of third inverse step dielectric material portions of the inverse step dielectric material portions are located at a third tier level that is positioned above the second tier level and each includes a pair of bottommost surfaces that are in direct contact with the first back trench fill structure. Claim 20 A method for forming a semiconductor device according to claim 13, further comprising the step of forming a layer contact via structure that penetrates the inverse step-type dielectric material portion and contacts each of the electrically conductive layers.

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