Display device

Abstract

The display device includes a light-emitting element, a driving transistor that transmits a driving current to the light-emitting element, a bias transistor including an input terminal electrically connected to a bias voltage line, a first light-emitting control transistor including an output terminal electrically connected to the input terminal of the driving transistor and a gate electrode to which a light-emitting control signal is applied, a second light-emitting control transistor including an input terminal electrically connected to the output terminal of the driving transistor and a gate electrode to which the light-emitting control signal is applied, a bias bridge electrode electrically contacting the output terminal of the bias transistor and the input terminal of the driving transistor, respectively, and a first light-emitting control bridge electrode to which the light-emitting control signal is applied, which defines the gate electrode of the first light-emitting control transistor and the gate electrode of the second light-emitting control transistor, and which is spaced apart from the bias bridge electrode in a plane.

Description

Technology Field

[0001] The present invention relates to a display device. Background Technology

[0002] Electronic devices such as smartphones, computers, and tablet PCs may include display devices. Recently, there has been a growing need for technology to reduce the power consumption of display devices in order to minimize battery drain in electronic devices. Accordingly, low-frequency driving methods that drive display devices at relatively low frequencies are being researched.

[0003] When a display device is driven at a relatively low frequency (for example, when the duration of a frame is relatively long), leakage current in the pixel circuit may increase. Consequently, differences in pixel brightness may occur between consecutive frames, and defects may be visible in the image displayed on the display device. The problem to be solved

[0004] The objective of the present invention is to provide a display device with improved low-frequency characteristics.

[0005] However, the purpose of the present invention is not limited to the purpose described above, and may be expanded in various ways without departing from the spirit and scope of the present invention. means of solving the problem

[0006] To achieve the aforementioned objective of the present invention, a display device according to one embodiment of the present invention may include a light-emitting element, a driving transistor that transmits a driving current to the light-emitting element, a bias transistor including an input terminal electrically connected to a bias voltage line, a first light-emitting control transistor including an output terminal electrically connected to the input terminal of the driving transistor and a gate electrode to which a light-emitting control signal is applied, a second light-emitting control transistor including an input terminal electrically connected to the output terminal of the driving transistor and a gate electrode to which the light-emitting control signal is applied, a bias bridge electrode electrically contacting the output terminal of the bias transistor and the input terminal of the driving transistor, respectively, and a first light-emitting control bridge electrode to which the light-emitting control signal is applied, which defines the gate electrode of the first light-emitting control transistor and the gate electrode of the second light-emitting control transistor and is spaced apart from the bias bridge electrode in a plane.

[0007] In one embodiment, the display device may further include a second light-emitting control bridge electrode disposed on the first light-emitting control bridge electrode in cross-section and electrically in contact with the first light-emitting control bridge electrode, and a light-emitting control line disposed on the second light-emitting control bridge electrode in cross-section and electrically in contact with the second light-emitting control bridge electrode, to which the light-emitting control signal is applied.

[0008] In one embodiment, the display device is characterized by further including at least one inorganic insulating layer disposed between the second light-emitting control bridge electrode and the first light-emitting control bridge electrode in cross-section.

[0009] In one embodiment, the display device is characterized by further including at least one organic insulating layer disposed between the light-emitting control line and the second light-emitting control bridge electrode in cross-section.

[0010] In one embodiment, the distance between the lower surface of the light-emitting control line and the upper surface of the second light-emitting control bridge electrode in cross-section may be greater than the distance between the lower surface of the second light-emitting control bridge electrode and the upper surface of the first light-emitting control bridge electrode in cross-section.

[0011] In one embodiment, the second light-emitting control bridge electrode may be spaced apart from the bias bridge electrode in a plane.

[0012] In one embodiment, the second light-emitting control bridge electrode may be disposed on the same layer as the bias bridge electrode.

[0013] In one embodiment, the display device may further include a diode transistor comprising a first sub-transistor, the output terminal of which is connected to the gate electrode of the driving transistor, and a second sub-transistor, the output terminal of which is connected to the input terminal of the first sub-transistor and the input terminal of which is connected to the output terminal of the driving transistor.

[0014] In one embodiment, the display device may further include a first stabilizing electrode defining a first stabilizing capacitor by overlapping with a first common region of a semiconductor layer defining each of the input terminal of the first sub-transistor and the output terminal of the second sub-transistor.

[0015] In one embodiment, the display device may further include a first lower metal electrode defining an additional-stabilizing capacitor by overlapping with the first common region of the semiconductor layer defining each of the input terminal of the first sub-transistor and the output terminal of the second sub-transistor.

[0016] In one embodiment, the first stabilizing electrode is positioned above the first common region of the semiconductor layer in cross-section, and the first lower metal electrode may be positioned below the first common region of the semiconductor layer in cross-section.

[0017] In one embodiment, the first stabilizing electrode and the first lower metal electrode are electrically connected to each other, and the same signal can be applied to the first stabilizing electrode and the first lower metal electrode.

[0018] In one embodiment, the signal applied to the first stabilizing electrode and the first lower metal electrode may be a constant voltage signal.

[0019] In one embodiment, the first sub-transistor and the second sub-transistor, respectively, may each be a double-gate transistor comprising an upper gate electrode and a lower gate electrode.

[0020] In one embodiment, the display device may further include a first gate voltage line defining the upper gate electrode of the first sub-transistor and the upper gate electrode of the second sub-transistor, and a second lower metal electrode defining the lower gate electrode of the first sub-transistor and the lower gate electrode of the second sub-transistor.

[0021] In one embodiment, the first gate voltage line and the second lower metal electrode are electrically connected to each other, and a first gate voltage provided by the first gate voltage line can be applied to the second lower metal electrode.

[0022] In one embodiment, the display device may further include a driving initialization transistor comprising a third sub-transistor, the output terminal of which is connected to the gate electrode of the driving transistor, and a fourth sub-transistor, the output terminal of which is connected to the input terminal of the third sub-transistor and the input terminal of which is connected to an initialization voltage line.

[0023] In one embodiment, the bias voltage line may define a second stabilization capacitor by overlapping with a second common region of a semiconductor layer that defines the input terminal of the third sub-transistor and the output terminal of the fourth sub-transistor, respectively.

[0024] To achieve the aforementioned objective of the present invention, a display device according to another embodiment of the present invention may include a light-emitting element, a driving transistor that transmits a driving current to the light-emitting element, a bias transistor including an input terminal electrically connected to a bias voltage line, a first light-emitting control transistor including an output terminal electrically connected to the input terminal of the driving transistor and a gate electrode to which a light-emitting control signal is applied, a second light-emitting control transistor including an input terminal electrically connected to the output terminal of the driving transistor and a gate electrode to which the light-emitting control signal is applied, a diode transistor including a first sub-transistor having an output terminal connected to the gate electrode of the driving transistor and a second sub-transistor having an output terminal connected to the input terminal of the first sub-transistor and an input terminal connected to the output terminal of the driving transistor, and a first lower metal electrode defining an additional-stabilizing capacitor by overlapping with a first common region of a semiconductor layer defining each of the input terminal of the first sub-transistor and the output terminal of the second sub-transistor.

[0025] In one embodiment, the display device may further include a first stabilizing electrode defining a first stabilizing capacitor by overlapping with the first common region of the semiconductor layer defining each of the input terminal of the first sub-transistor and the output terminal of the second sub-transistor.

[0026] In one embodiment, the first sub-transistor and the second sub-transistor, respectively, may each be a double-gate transistor comprising an upper gate electrode and a lower gate electrode.

[0027] In one embodiment, the display device may further include a first gate voltage line defining the upper gate electrode of the first sub-transistor and the lower gate electrode of the second sub-transistor, and a second lower metal electrode defining the lower gate electrode of the first sub-transistor and the lower gate electrode of the second sub-transistor and electrically connected to the first gate voltage line.

[0028] In one embodiment, the first lower metal electrode and the second lower metal electrode may be disposed on the same layer.

[0029] In one embodiment, in a cross-sectional view, the first lower metal electrode and the second lower metal electrode are each disposed below the semiconductor layer, and in a planar view, the first lower metal electrode and the second lower metal electrode may be spaced apart from each other.

[0030] To achieve the aforementioned objective of the present invention, a display device according to another embodiment of the present invention may include a light-emitting element, a driving transistor that transmits a driving current to the light-emitting element, a bias transistor including an input terminal electrically connected to a bias voltage line, a first light-emitting control transistor including an output terminal electrically connected to the input terminal of the driving transistor and a gate electrode to which a light-emitting control signal is applied, a second light-emitting control transistor including an input terminal electrically connected to the output terminal of the driving transistor and a gate electrode to which the light-emitting control signal is applied, a diode transistor including a first sub-transistor whose output terminal is connected to the gate electrode of the driving transistor and a second sub-transistor whose output terminal is connected to the input terminal of the first sub-transistor and whose input terminal is connected to the output terminal of the driving transistor, a first gate voltage line defining the upper gate electrode of the first sub-transistor and the upper gate electrode of the second sub-transistor, and a second lower metal electrode defining the lower gate electrode of the first sub-transistor and the lower gate electrode of the second sub-transistor. Effects of the invention

[0031] A display device according to one embodiment of the present invention may include a bias bridge electrode that is electrically in contact with the output terminal of a bias transistor and the input terminal of a driving transistor, respectively, and a first light-emitting control bridge electrode to which the light-emitting control signal is applied and which is spaced apart from the bias bridge electrode in a plane. In the present invention, since the first light-emitting control bridge electrode is spaced apart from the bias bridge electrode in a plane, signal interference may not substantially occur between the signal applied to the first light-emitting control bridge electrode and the signal applied to the bias bridge electrode.

[0032] A display device according to another embodiment of the present invention may include a diode transistor comprising a first sub-transistor, the output terminal of which is connected to the gate electrode of a driving transistor, and a second sub-transistor, the output terminal of which is connected to the input terminal of the first sub-transistor and the input terminal of which is connected to the output terminal of the driving transistor, and a first lower metal electrode that defines an additional-stabilizing capacitor by overlapping with a first common region of a semiconductor layer that defines each of the input terminal of the first sub-transistor and the output terminal of the second sub-transistor. Accordingly, the voltage level at each of the input terminal of the first sub-transistor and the output terminal of the second sub-transistor can be maintained relatively constant.

[0033] A display device according to another embodiment of the present invention may include a diode transistor comprising a first sub-transistor having an output terminal connected to the gate electrode of a driving transistor and a second sub-transistor having an output terminal connected to the input terminal of the first sub-transistor and an input terminal connected to the output terminal of the driving transistor, a first gate voltage line defining the upper gate electrode of the first sub-transistor and the upper gate electrode of the second sub-transistor, and a second lower metal electrode defining the lower gate electrode of the first sub-transistor and the lower gate electrode of the second sub-transistor. Accordingly, each of the first sub-transistor and the second sub-transistor may have a double-gate structure, and the device characteristics of the first sub-transistor and the second sub-transistor may be improved.

[0034] However, the effects of the present invention are not limited to the effects described above, and may be extended in various ways without departing from the spirit and scope of the present invention. Brief explanation of the drawing

[0035] FIG. 1 is a circuit diagram for explaining a pixel included in a display device according to one embodiment of the present invention. FIGS. 2 to 20 are drawings for explaining the pixels of FIG. 1. FIG. 21 is a circuit diagram for explaining a pixel included in a display device according to another embodiment of the present invention. FIGS. 22 to 24 are drawings for explaining the pixels of FIG. 21. FIG. 25 is a circuit diagram for explaining a pixel included in a display device according to another embodiment of the present invention. FIGS. 26 to 28 are drawings for explaining the pixels of FIG. 25. Specific details for implementing the invention

[0036] Hereinafter, a display device according to embodiments of the present invention will be described in more detail with reference to the attached drawings. Identical or similar reference numerals are used for identical components in the attached drawings.

[0037] FIG. 1 is a circuit diagram for explaining a pixel included in a display device according to one embodiment of the present invention.

[0038] Referring to FIG. 1, a display device according to one embodiment of the present invention may include a pixel (PXa). The pixel (PXa) may be defined as a minimum unit for emitting light and may include a pixel circuit (PXCa) and a light-emitting element (DIOD).

[0039] The pixel circuit (PXCa) may include at least one transistor and at least one capacitor. The light-emitting element (DIOD) may be electrically connected to the pixel circuit (PXCa) and may include any component (e.g., an organic light-emitting diode) capable of emitting light based on a signal provided by the pixel circuit (PXCa).

[0040] The pixel circuit (PXCa) may include a driving transistor (T1), at least one switching transistor, and a storage capacitor (CST). For example, the pixel circuit (PXCa) may include a driving transistor (T1), a switching transistor (T2) that provides a data voltage to the driving transistor (T1), a first light-emitting control transistor (T5) connected between a first power supply voltage line (ELVDD) and the driving transistor (T1), a second light-emitting control transistor (T6) connected between the driving transistor (T1) and a light-emitting element (DIOD), a bias transistor (T8) connected to each of the driving transistor (T1) and the first light-emitting control transistor (T5), and a storage capacitor (CST).

[0041] Optionally, the pixel circuit (PXCa) may further include at least one other switching transistor. For example, the pixel circuit (PXCa) may further include at least one of a diode transistor (T3), a driving initialization transistor (T4), and a diode initialization transistor (T7).

[0042] Additionally, optionally, the pixel circuit (PXCa) may further include at least one other capacitor. For example, the pixel circuit (PXCa) may further include at least one of a first stabilization capacitor (CS1), a second stabilization capacitor (CS2), and an additional-stabilization capacitor (CSA).

[0043] Below, the aforementioned transistors (T1, T2, T3, T4, T5, T6, T7, T8) and capacitors (CST, CS1, CS2, CSA) will be described in detail.

[0044] The input terminal of the driving transistor (T1) can be connected to the data voltage line (DATA), and the output terminal of the driving transistor (T1) can be connected to the light-emitting element (DIOD).

[0045] The driving transistor (T1) receives the data voltage from the data voltage line (DATA) and can generate a driving current corresponding to the data voltage. The driving current can be supplied to a light-emitting element (DIOD).

[0046] The input terminal of the switching transistor (T2) can be connected to the data voltage line (DATA), the output terminal of the switching transistor (T2) can be connected to the input terminal of the driving transistor (T1), and the gate electrode of the switching transistor (T2) can be connected to the first gate voltage line (GW).

[0047] Accordingly, the switching transistor (T2) can be turned on by the first gate voltage provided by the first gate voltage line (GW). During the period in which the switching transistor (T2) is turned on, the switching transistor (T2) can provide the data voltage to the driving transistor (T1).

[0048] The diode transistor (T3) may include a first sub-transistor (T3-1) and a second sub-transistor (T3-2) connected to each other. The input terminal of the first sub-transistor (T3-1) may be connected to the output terminal of the second sub-transistor (T3-2), the output terminal of the first sub-transistor (T3-1) may be connected to the gate electrode of the driving transistor (T1), and the input terminal of the second sub-transistor (T3-2) may be connected to the output terminal of the driving transistor (T1). The gate electrode of the first sub-transistor (T3-1) and the gate electrode of the second sub-transistor (T3-2) may each be connected to a first gate voltage line (GW).

[0049] Accordingly, the diode transistor (T3) can be turned on by the first gate voltage provided by the first gate voltage line (GW). During the period when the diode transistor (T3) is turned on, the diode transistor (T3) can compensate for the threshold voltage of the driving transistor (T1) by diode connecting the driving transistor (T1).

[0050] In one embodiment, as shown in FIG. 1, the first sub-transistor (T3-1) and the second sub-transistor (T3-2) may each be a double-gate transistor including an upper gate electrode and a lower gate electrode. In this case, the upper gate electrode and the lower gate electrode included in each of the first sub-transistor (T3-1) and the second sub-transistor (T3-2) may be connected to a first gate voltage line (GW).

[0051] The driving initialization transistor (T4) may include a third sub-transistor (T4-1) and a fourth sub-transistor (T4-2) connected to each other. The input terminal of the third sub-transistor (T4-1) may be connected to the output terminal of the fourth sub-transistor (T4-2), the output terminal of the third sub-transistor (T4-1) may be connected to the gate electrode of the driving transistor (T1), and the input terminal of the fourth sub-transistor (T4-2) may be connected to the initialization voltage line (VINT). The gate electrode of the third sub-transistor (T4-1) and the gate electrode of the fourth sub-transistor (T4-2) may each be connected to the second gate voltage line (GI).

[0052] Accordingly, the driving initialization transistor (T4) can be turned on by the second gate voltage provided by the second gate voltage line (GI). During the period in which the driving initialization transistor (T4) is turned on, the driving initialization transistor (T4) can provide the initialization voltage provided by the initialization voltage line (VINT) to the gate electrode of the driving transistor (T1).

[0053] The input terminal of the first light-emitting control transistor (T5) can be connected to the first power supply voltage line (ELVDD), the output terminal of the first light-emitting control transistor (T5) can be connected to the input terminal of the driving transistor (T1), and the gate electrode of the first light-emitting control transistor (T5) can be connected to the light-emitting control line (EM).

[0054] Accordingly, the first light-emitting control transistor (T5) can be turned on by a light-emitting control signal provided by the light-emitting control line (EM). During the period in which the first light-emitting control transistor (T5) is turned on, the first light-emitting control transistor (T5) can provide a first power supply voltage provided by the first power supply voltage line (ELVDD) to the driving transistor (T1).

[0055] In one embodiment, the first power voltage provided by the first power voltage line (ELVDD) and the second power voltage provided by the second power voltage line (ELVSS) connected to the light-emitting element (DIOD) may each be a constant voltage. In this case, the first power voltage and the second power voltage may have different voltage levels.

[0056] The input terminal of the second light-emitting control transistor (T6) can be connected to the output terminal of the driving transistor (T1), the output terminal of the second light-emitting control transistor (T6) can be connected to a light-emitting element (DIOD), and the gate electrode of the second light-emitting control transistor (T6) can be connected to a light-emitting control line (EM).

[0057] Accordingly, the second light-emitting control transistor (T6) can be turned on by the light-emitting control signal. During the period in which the second light-emitting control transistor (T6) is turned on, the second light-emitting control transistor (T6) can provide the driving current to the light-emitting element (DIOD).

[0058] The input terminal of the diode initialization transistor (T7) can be connected to the diode initialization voltage line (VAINT), the output terminal of the diode initialization transistor (T7) can be connected to the light-emitting element (DIOD), and the gate electrode of the diode initialization transistor (T7) can be connected to the third gate voltage line (GB).

[0059] Accordingly, the diode initialization transistor (T7) can be turned on by the third gate voltage provided by the third gate voltage line (GB). During the period in which the diode initialization transistor (T7) is turned on, the diode initialization transistor (T7) can provide the diode initialization voltage provided by the diode initialization voltage line (VAINT) to the light-emitting element (DIOD).

[0060] The input terminal of the bias transistor (T8) can be connected to the bias voltage line (VBIAS), the output terminal of the bias transistor (T8) can be connected to the input terminal of the driving transistor (T1), and the gate electrode of the bias transistor (T8) can be connected to the third gate voltage line (GB).

[0061] Accordingly, the bias transistor (T8) can be turned on by the third gate voltage. During the period when the bias transistor (T8) is turned on, the bias transistor (T8) can provide a bias voltage to the driving transistor (T1).

[0062] The first terminal of the storage capacitor (CST) can be connected to the gate electrode of the driving transistor (T1), and the second terminal of the storage capacitor (CST) can be connected to the first power supply voltage line (ELVDD).

[0063] The storage capacitor (CST) can maintain the voltage level of the gate electrode of the driving transistor (T1) during the deactivation period of the first gate voltage provided by the first gate voltage line (GW).

[0064] The first terminal of the first stabilization capacitor (CS1) can be connected to the input terminal of the first sub-transistor (T3-1) and the output terminal of the second sub-transistor (T3-2), respectively, and the second terminal of the first stabilization capacitor (CS1) can be connected to the first power supply voltage line (ELVDD).

[0065] The first stabilization capacitor (CS1) can maintain the voltage level at the input terminal of the first sub-transistor (T3-1) and the output terminal of the second sub-transistor (T3-2), respectively, at a relatively constant level. Accordingly, the leakage current in the diode transistor (T3) can be reduced, and the low-frequency characteristics of the display device can be improved.

[0066] The first terminal of the second stabilization capacitor (CS2) can be connected to the input terminal of the third sub-transistor (T4-1) and the output terminal of the fourth sub-transistor (T4-2), respectively, and the second terminal of the second stabilization capacitor (CS2) can be connected to the bias voltage line (VBIAS).

[0067] The second stabilization capacitor (CS2) can maintain the voltage level at the input terminal of the third sub-transistor (T4-1) and the output terminal of the fourth sub-transistor (T4-2), respectively, at a relatively constant level. Accordingly, the leakage current in the driving initialization transistor (T4) can be reduced, and the low-frequency characteristics of the display device can be improved.

[0068] The first terminal of the additional-stabilizing capacitor (CSA) can be connected to the input terminal of the first sub-transistor (T3-1) and the output terminal of the second sub-transistor (T3-2), respectively, and the second terminal of the additional-stabilizing capacitor (CSA) can be connected to the first power supply voltage line (ELVDD).

[0069] The additional-stabilizing capacitor (CSA) can perform substantially the same function as the first stabilizing capacitor (CS1). Specifically, the additional-stabilizing capacitor (CSA) can maintain the voltage levels at the input terminal of the first sub-transistor (T3-1) and the output terminal of the second sub-transistor (T3-2), respectively, at a relatively constant level.

[0070] In one embodiment, as shown in FIG. 1, when the pixel circuit (PXa) includes a first stabilization capacitor (CS1) and an additional-stabilization capacitor (CSA) simultaneously, the leakage current in the diode transistor (T3) can be further reduced and the low-frequency characteristics of the display device can be further improved.

[0071] FIGS. 2 to 20 are drawings for explaining the pixel of FIG. 1. FIGS. 2 to 20 are drawings for explaining a plurality of pixel circuits arranged adjacently to each other in a part of a display area for displaying an image in a display device according to an embodiment of the present invention. The plurality of pixel circuits may include substantially identical configurations. Therefore, for convenience of explanation, FIGS. 2 to 20 will describe only the configuration corresponding to one of the plurality of pixel circuits (e.g., PXCa of FIG. 1).

[0072] Figure 2 is a plan view illustrating the lower metal electrode (BML).

[0073] Referring to FIG. 2, the pixel circuit (PXCa) may include a bottom metal electrode (BML). The bottom metal electrode (BML) may also be referred to as an overlapping layer, a bottom electrode layer, a bottom shield layer, a bottom metal layer, or a bottom light blocking layer.

[0074] The bottom metal electrode (BML) may include a conductive material. For example, the bottom metal electrode (BML) may include silver, a silver-containing alloy, molybdenum, a molybdenum-containing alloy, aluminum, an aluminum-containing alloy, aluminum nitride, tungsten, tungsten nitride, copper, indium tin oxide, and indium zinc oxide, etc., and these may be used alone or in combination with each other.

[0075] The lower metal electrode (BML) may include a first lower metal electrode (BML1) and a second lower metal electrode (BML2). The first lower metal electrode (BML1) and the second lower metal electrode (BML2) may be spaced apart from each other in a planar manner.

[0076] The first lower metal electrode (BML1) and the second lower metal electrode (BML2) can be formed by the same process. For example, the first lower metal electrode (BML1) and the second lower metal electrode (BML2) may contain the same material, and also, as shown in FIG. 7, the first lower metal electrode (BML1) and the second lower metal electrode (BML2) may be placed on the same layer (e.g., IL1 in FIG. 7).

[0077] Each of the first lower metal electrode (BML1) and the second lower metal electrode (BML2) may be arranged to overlap in a plane with the semiconductor layer (ATV) described later. For example, the first lower metal electrode (BML1) may overlap with the first common region (ATV_T3c) of the semiconductor layer (ATV) to define the second terminal of the additional-stabilization capacitor (CSA), and the second lower metal electrode (BML2) may overlap with the first sub-channel region (T3-1c) and the second sub-channel region (T3-2c) of the semiconductor layer (ATV) to define the lower gate electrode of the first sub-transistor (T3-1) and the lower gate electrode of the second sub-transistor (T3-2).

[0078] Figure 3 is a plan view illustrating a semiconductor layer (ATV).

[0079] Referring to FIG. 3, the pixel circuit (PXCa) may include a semiconductor layer (ATV). The semiconductor layer (ATV) may include a semiconductor material. In one embodiment, the semiconductor layer (ATV) may include a silicon semiconductor material. For example, the semiconductor layer (ATV) may include amorphous silicon, polycrystalline silicon, etc. In another embodiment, the semiconductor layer (ATV) may include an oxide semiconductor material. For example, the semiconductor layer (ATV) may include indium-gallium-zinc oxide, indium-gallium oxide, indium-zinc oxide, etc.

[0080] The semiconductor layer (ATV) may include a first semiconductor region (ATV1) having a relatively high conductivity and a second semiconductor region (ATV2) having a relatively low conductivity. For example, the first semiconductor region (ATV1) may be a doped region doped with an N-type dopant or a P-type dopant, and the second semiconductor region (ATV2) may be a non-doped region or a region doped at a lower concentration compared to the first semiconductor region (ATV1).

[0081] The first semiconductor region (ATV1) may include the first to ninth regions (A1, A2, A3, A4, A5, A6, A7, A8, A9), the first common region (ATV_T3c), and the second common region (ATV_T4c). In this case, the fifth region (A5) may include the Nth region (A5(N)) included in the pixel circuit of the Nth row and the N+1th region (A5(N+1)) included in the pixel circuit of the N+1th row adjacent to the Nth row. The first semiconductor region (ATV1) may serve as an electrode, a signal line, an input terminal of a transistor, an output terminal of a transistor, and / or one terminal of a capacitor.

[0082] The second semiconductor region (ATV2) may include a plurality of channel regions (T1c, T2c, T3-1c, T3-2c, T4-1c, T4-2c, T5c, T6c, T7c, T8c). The second semiconductor region (ATV2) is a region that overlaps with the first conductive layer (C1) and may be a region that defines the channel region (or active region) of the transistor.

[0083] FIG. 4 is a plan view for explaining the first conductive layer (C1).

[0084] Referring to FIG. 4, the pixel circuit (PXCa) may include a first conductive layer (C1). The first conductive layer (C1) may include a conductive material. For example, the first conductive layer (C1) may include silver, an alloy containing silver, molybdenum, an alloy containing molybdenum, aluminum, an alloy containing aluminum, aluminum nitride, tungsten, tungsten nitride, copper, indium tin oxide, and indium zinc oxide, etc., and these may be used alone or in combination with each other.

[0085] The first conductive layer (C1) may include a first gate voltage line (GW), a second gate voltage line (GI), a third gate voltage line (GB), a first light-emitting control bridge electrode (BR1_EM), and a first storage electrode (CSTE1).

[0086] The first gate voltage may be applied to the first gate voltage line (GW), the second gate voltage may be applied to the second gate voltage line (GI), and the third gate voltage may be applied to the third gate voltage line (GB).

[0087] The first light-emitting control bridge electrode (BR1_EM) can be electrically connected to the light-emitting control line (EM in FIG. 16 and FIG. 17) described later, and accordingly, the light-emitting control signal can be provided to the first light-emitting control bridge electrode (BR1_EM).

[0088] The first conductive layer (C1) can overlap with the second region (A2) of the semiconductor layer (ATV). Specifically, the first storage electrode (CSTE1) can overlap with the first channel region (T1c), the first gate voltage line (GW) can overlap with the second channel region (ATV2) and the third channel region (ATV3), the second gate voltage line (GI) can overlap with the fourth channel region (ATV4), the first light-emitting control bridge electrode (BR1_EM) can overlap with the fifth channel region (T5c) and the sixth channel region (T6c), and the third gate voltage line (GB) can overlap with the seventh channel region (T7c) and the eighth channel region (T8c). Accordingly, the first conductive layer (C1) can define the gate electrode of the transistor. In this case, the first conductive layer (C1) may also function as a mask in the process of doping the semiconductor layer (ATV).

[0089] FIGS. 5 and 6 are plan views illustrating a lower metal electrode (BML), a semiconductor layer (ATV), and a first conductive layer (C1).

[0090] Referring to FIGS. 2 to 6, the semiconductor layer (ATV) can be placed on the lower metal electrode (BML), and the first conductive layer (C1) can be placed on the semiconductor layer (ATV).

[0091] The lower metal electrode (BML), the semiconductor layer (ATV), and the first conductive layer (C1) can define the transistors (T1, T2, T3, T4, T5, T6, T7, T8) and the additional-stabilizing capacitor (CSA) described with reference to FIG. 1. Below, the transistors (T1, T2, T3, T4, T5, T6, T7, T8) and the additional-stabilizing capacitor (CSA) defined by the lower metal electrode (BML), the semiconductor layer (ATV), and the first conductive layer (C1) will be described.

[0092] The driving transistor (T1) can be defined by the first storage electrode (CSTE1) and the first channel region (T1c), first region (A1), and second region (A2) of the semiconductor layer (ATV).

[0093] Specifically, the first storage electrode (CSTE1) may define the gate electrode of the driving transistor (T1), and the first channel region (T1c) may be the channel region of the driving transistor (T1). Additionally, the first region (A1) adjacent to the first channel region (T1c) may be the input terminal of the driving transistor (T1), and the second region (A2) adjacent to the first channel region (T1c) may be the output terminal of the driving transistor (T1).

[0094] The switching transistor (T2) can be defined by the first gate voltage line (GW), the second channel region (T2c) of the semiconductor layer (ATV), the first region (A1), and the third region (A3).

[0095] Specifically, the first gate voltage line (GW) may define the gate electrode of the switching transistor (T2), and the second channel region (T2c) may be the channel region of the switching transistor (T2). Additionally, the third region (A3) adjacent to the second channel region (T2c) may be the input terminal of the switching transistor (T2), and the first region (A1) adjacent to the second channel region (T2c) may be the output terminal of the switching transistor (T2).

[0096] The first sub-transistor (T3-1) and the second sub-transistor (T3-2) can be defined by the first gate voltage line (GW), the second lower metal electrode (BML2), and the first sub-channel region (T3-1c), the second sub-channel region (T3-2c), the second region (A2), the fourth region (A4), and the first common region (ATV_T3c) of the semiconductor layer (ATV).

[0097] The first gate voltage line (GW) can define the upper gate electrode of the first sub-transistor (T3-1) and the upper gate electrode of the second sub-transistor (T3-2). In one embodiment, when the first sub-transistor (T3-1) and the second sub-transistor (T3-2) are each double-gate transistors, the second lower metal electrode (BML2) can define the lower gate electrode of the first sub-transistor (T3-1) and the lower gate electrode of the second sub-transistor (T3-2).

[0098] The first sub-channel region (T3-1c) may be the channel region of the first sub-transistor (T3-1), and the second sub-channel region (T3-2c) may be the channel region of the second sub-transistor (T3-2).

[0099] The fourth region (A4) adjacent to the first sub-channel region (T3-1c) may be the output terminal of the first sub-transistor (T3-1), and the second region (A2) adjacent to the second sub-channel region (T3-2c) may be the input terminal of the second sub-transistor (T3-2).

[0100] Additionally, in the first common region (ATV_T3c), the region adjacent to the first sub-channel region (T3-1c) may be the input terminal of the first sub-transistor (T3-1), and the region adjacent to the second sub-channel region (T3-2c) may be the output terminal of the second sub-transistor (T3-2). That is, the first common region (ATV_T3c) may define the input terminal of the first sub-transistor (T3-1) and the output terminal of the second sub-transistor (T3-2), respectively. In this case, the first common region (ATV_T3c) may serve as an electrode (or signal line) that electrically connects the input terminal of the first sub-transistor (T3-1) and the output terminal of the second sub-transistor (T3-2) to each other.

[0101] The third sub-transistor (T4-1) and the fourth sub-transistor (T4-2) can be defined by the second gate voltage line (GI) and the third sub-channel region (T4-1c), the fourth sub-channel region (T4-2c), the N region (A5(N)), the fourth region (A4), and the second common region (ATV_T4c) of the semiconductor layer (ATV).

[0102] The second gate voltage line (GI) can define the gate electrode of the third sub-transistor (T4-1) and the gate electrode of the fourth sub-transistor (T4-2), the third sub-channel region (T4-1c) may be the channel region of the third sub-transistor (T4-1), and the fourth sub-channel region (T4-2c) may be the channel region of the fourth sub-transistor (T4-2).

[0103] The fourth region (A4) adjacent to the third sub-channel region (T4-1c) may be the output terminal of the third sub-transistor (T4-1), and the Nth region (A5(N)) adjacent to the fourth sub-channel region (T4-2c) may be the input terminal of the fourth sub-transistor (T4-2).

[0104] Additionally, in the second common region (ATV_T4c), the region adjacent to the third sub-channel region (T4-1c) may be the input terminal of the third sub-transistor (T4-1), and the region adjacent to the fourth sub-channel region (T4-2c) may be the output terminal of the fourth sub-transistor (T4-2). That is, the second common region (ATV_T4c) can define the input terminal of the third sub-transistor (T4-1) and the output terminal of the fourth sub-transistor (T4-2), respectively. Furthermore, the second common region (ATV_T4c) may serve as an electrode (or signal line) that electrically connects the input terminal of the third sub-transistor (T4-1) and the output terminal of the fourth sub-transistor (T4-2) to each other.

[0105] The first light-emitting control transistor (T5) can be defined by the first light-emitting control bridge electrode (BR1_EM) and the fifth channel region (T5c), sixth region (A6), and first region (A1) of the semiconductor layer (ATV).

[0106] Specifically, the first light-emitting control bridge electrode (BR1_EM) may define the gate electrode of the first light-emitting control transistor (T5), and the fifth channel region (T5c) may be the channel region of the first light-emitting control transistor (T5). Additionally, the sixth region (A6) adjacent to the fifth channel region (T5c) may be the input terminal of the first light-emitting control transistor (T5), and the first region (A1) adjacent to the fifth channel region (T5c) may be the output terminal of the first light-emitting control transistor (T5).

[0107] The second light-emitting control transistor (T6) can be defined by the first light-emitting control bridge electrode (BR1_EM) and the sixth channel region (T6c), second region (A2), and seventh region (A7) of the semiconductor layer (ATV).

[0108] Specifically, the first light-emitting control bridge electrode (BR1_EM) may define the gate electrode of the second light-emitting control transistor (T6), and the sixth channel region (T6c) may be the channel region of the second light-emitting control transistor (T6). Additionally, the second region (A2) adjacent to the sixth channel region (T6c) may be the input terminal of the second light-emitting control transistor (T6), and the seventh region (A7) adjacent to the sixth channel region (T6c) may be the output terminal of the second light-emitting control transistor (T6).

[0109] As described above, the first light-emitting control bridge electrode (BR1_EM) can overlap simultaneously with the fifth channel region (T5c) and the sixth channel region (T6c) of the semiconductor layer (ATV). Accordingly, the first light-emitting control bridge electrode (BR1_EM) can define the gate electrode of the first light-emitting control transistor (T5) and the gate electrode of the second light-emitting control transistor (T6), respectively.

[0110] The diode initialization transistor (T7) can be defined by the third gate voltage line (GB), the seventh channel region (T7c) of the semiconductor layer (ATV), the N+1 region (A5(N+1)), and the seventh channel region (A7).

[0111] Specifically, the third gate voltage line (GB) may define the gate electrode of the diode initialization transistor (T7), and the seventh channel region (T7c) may be the channel region of the diode initialization transistor (T7). Additionally, the N+1 region (A5(N+1)) adjacent to the seventh channel region (T7c) may be the input terminal of the diode initialization transistor (T7), and the seventh region (A7) adjacent to the seventh channel region (T7c) may be the output terminal of the diode initialization transistor (T7).

[0112] The bias transistor (T8) can be defined by the third gate voltage line (GB) and the eighth channel region (T8c), eighth region (A8), and ninth region (A9) of the semiconductor layer (ATV).

[0113] Specifically, the third gate voltage line (GB) may define the gate electrode of the bias transistor (T8), and the eighth channel region (T8c) may be the channel region of the bias transistor (T8). Additionally, the ninth region (A9) adjacent to the eighth channel region (T8c) may be the input terminal of the bias transistor (T8), and the eighth region (A8) adjacent to the eighth channel region (T8c) may be the output terminal of the bias transistor (T8).

[0114] As described above, the third gate voltage line (GB) can overlap simultaneously with the seventh channel region (T7c) and the eighth channel region (T8c) of the semiconductor layer (ATV). Accordingly, the third gate voltage line (GB) can define the gate electrode of the diode initialization transistor (T7) and the gate electrode of the bias transistor (T8), respectively.

[0115] The additional-stabilization capacitor (CSA) can be defined by the first lower metal electrode (BML1) and the first common region (ATV_T3c) of the semiconductor layer (ATV). This will be described later with reference to FIG. 10.

[0116] As described above, the lower metal electrode (BML), the semiconductor layer (ATV), and the first conductive layer (C1) can define transistors (T1, T2, T3, T4, T5, T6, T7, T8). In this case, the first region (A1) of the semiconductor layer (ATV) may serve as an electrode (or signal line) that electrically connects two different transistors to each other.

[0117] For example, the first region (A1) of the semiconductor layer (ATV) can serve as an electrode that electrically connects the input terminal of the driving transistor (T1), the output terminal of the switching transistor (T2), and the output terminal of the first light-emitting control transistor (T5) to each other.

[0118] As another example, the second region (A2) of the semiconductor layer (ATV) can serve as an electrode that electrically connects the output terminal of the driving transistor (T1), the input terminal of the second sub-transistor (T3-2), and the input terminal of the second light-emitting control transistor (T6) to each other.

[0119] As another example, the seventh region (A7) of the semiconductor layer (ATV) can serve as an electrode that electrically connects the output terminal of the second light-emitting control transistor (T6) and the output terminal of the diode initialization transistor (T7) to each other, and the fourth region (A4) of the semiconductor layer (ATV) can serve as an electrode that electrically connects the output terminal of the first sub-transistor (T3-1) and the output terminal of the third sub-transistor (T4-1) to each other.

[0120] Figure 7 is a cross-sectional view taken along line II' and line II-II' of Figure 6.

[0121] Referring to FIG. 7, a display device according to one embodiment of the present invention may include a substrate (SUB), a first insulating layer (IL1), a second insulating layer (IL2), a third insulating layer (IL3), and a fourth insulating layer (IL4).

[0122] The substrate (SUB) may include glass, quartz, sapphire, etc. The first insulating layer (IL1), the second insulating layer (IL2), the third insulating layer (IL3), and the fourth insulating layer (IL4) may be stacked sequentially on the substrate (SUB).

[0123] Each of the first to fourth insulating layers (IL1, IL2, IL3, IL4) may include an inorganic insulating material. For example, each of the first to fourth insulating layers (IL1, IL2, IL3, IL4) may include aluminum oxide, titanium oxide, silicon oxide, silicon nitride, silicon oxynitride, zirconium oxide, hafnium oxide, etc., and these may be used alone or in combination with each other. Additionally, each of the first to fourth insulating layers (IL1, IL2, IL3, IL4) may have a single-layer or multi-layer structure including at least one of the materials described above.

[0124] A lower metal electrode (BML) can be placed on a first insulating layer (IL1), and a second insulating layer (IL2) can cover the lower metal electrode (BML). For example, as shown in FIG. 7, a second lower metal electrode (BML2) can be placed on a first insulating layer (IL1), and a second insulating layer (IL2) can cover the second lower metal electrode (BML2).

[0125] A semiconductor layer (ATV) can be placed on a second insulating layer (IL2), and a third insulating layer (IL3) can cover the semiconductor layer (ATV).

[0126] The first conductive layer (C1) can be placed on the third insulating layer (IL3), and the fourth insulating layer (IL4) can cover the first conductive layer (C1). For example, as shown in FIG. 7, the first gate voltage line (GW) can be placed on the third insulating layer (IL3), and the fourth insulating layer (IL4) can cover the first gate voltage line (GW).

[0127] The second lower metal electrode (BML2), the semiconductor layer (ATV), and the first gate voltage line (GW) can each define a first sub-transistor (T3-1) and a second sub-transistor (T3-2) having a double-gate structure. In this case, the second lower metal electrode (BML2) can define the lower gate electrode of each of the first sub-transistor (T3-1) and the second sub-transistor (T3-2) by overlapping with the first sub-channel region (T3-1c) and the second sub-channel region (T3-2c) of the semiconductor layer (ATV), and the first gate voltage line (GW) can define the upper gate electrode of each of the first sub-transistor (T3-1) and the second sub-transistor (T3-2) by overlapping with the first sub-channel region (T3-1c) and the second sub-channel region (T3-2c) of the semiconductor layer (ATV).

[0128] In this way, as the first sub-transistor (T3-1) and the second sub-transistor (T3-2) each have a double-gate structure, the voltage levels of the first sub-transistor (T3-1) and the second sub-transistor (T3-2) respectively can be maintained relatively constant. Accordingly, leakage current in the first sub-transistor (T3-1) and the second sub-transistor (T3-2) can be reduced, and the low-frequency characteristics of the display device can be improved.

[0129] FIG. 8 is a plan view for explaining the second conductive layer (C2).

[0130] Referring to FIG. 8, the pixel circuit (PXCa) may include a second conductive layer (C2). The second conductive layer (C2) may include a conductive material. For example, the second conductive layer (C2) may include silver, a silver-containing alloy, molybdenum, a molybdenum-containing alloy, aluminum, an aluminum-containing alloy, aluminum nitride, tungsten, tungsten nitride, copper, indium tin oxide, and indium zinc oxide, etc., and these may be used alone or in combination with each other.

[0131] The second conductive layer (C2) may include a first stabilizing electrode (CS1E), a bias voltage line (VBIAS), and a second storage electrode (CSTE2).

[0132] The bias voltage may be applied to the bias voltage line (VBIAS). The bias voltage line (VBIAS) may include the Nth bias voltage line (VBIAS(N)) included in the pixel circuit of the Nth row and the N+1th bias voltage line (VBIAS(N+1)) included in the pixel circuit of the N+1th row.

[0133] FIG. 9 is a plan view illustrating a lower metal electrode (BML), a semiconductor layer (ATV), a first conductive layer (C1), and a second conductive layer (C2).

[0134] Referring to FIG. 9, the second conductive layer (C2) can be placed on the lower metal electrode (BML), the semiconductor layer (ATV), and the first conductive layer (C1).

[0135] The first stabilization electrode (CS1E) may define an additional-stabilization capacitor (CSA) by overlapping with the first common region (ATV_T3c) of the semiconductor layer (ATV) that defines the input terminal of the first sub-transistor (T3-1) and the output terminal of the second sub-transistor (T3-2). This will be described later with reference to FIG. 10.

[0136] The Nth bias voltage line (VBIAS(N)) may define a second stabilization capacitor (CS2) by overlapping with the second common region (ATV_T4c) of the semiconductor layer (ATV) that defines the input terminal of the third sub-transistor (T4-1) and the output terminal of the fourth sub-transistor (T4-2). This will be described later with reference to FIG. 10.

[0137] The second storage electrode (CSTE2) may overlap with the first storage electrode (CSTE1) to define a storage capacitor (CST). In this case, the first storage electrode (CSTE1) may define the first terminal of the storage capacitor (CST), and the second storage electrode (CSTE2) may define the second terminal of the storage capacitor (CST). The second storage electrode (CSTE2) may define an opening that exposes a portion of the first storage electrode (CSTE1), as shown in FIG. 9.

[0138] Figure 10 is a cross-sectional view taken along the lines III-III' and IV-IV' of Figure 9.

[0139] Referring to FIG. 10, a fifth insulating layer (IL5) may be disposed on a fourth insulating layer (IL4). The fifth insulating layer (IL5) may include an inorganic insulating material. For example, the fifth insulating layer (IL5) may include aluminum oxide, titanium oxide, silicon oxide, silicon nitride, silicon oxynitride, zirconium oxide, hafnium oxide, etc., which may be used alone or in combination with each other. Additionally, the fifth insulating layer (IL5) may have a single-layer or multi-layer structure comprising at least one of the materials described above.

[0140] The second conductive layer (C2) may be placed on the fourth insulating layer (IL4), and the fifth insulating layer (IL5) may cover the second conductive layer (C2). For example, as shown in FIG. 10, the first stabilizing electrode (CS1E) and the Nth bias voltage line (VBIAS(N)) may be placed on the fourth insulating layer (IL4), and the fifth insulating layer (IL5) may cover the first stabilizing electrode (CS1E) and the Nth bias voltage line (VBIAS(N)).

[0141] The first lower metal electrode (BML1) may define an additional-stabilizing capacitor (CSA) by overlapping with the first common region (ATV_T3c) of the semiconductor layer (ATV). In this case, the first common region (ATV_T3c) of the semiconductor layer (ATV) may define the first terminal of the additional-stabilizing capacitor (CSA), and the first lower metal electrode (BML1) may define the second terminal of the additional-stabilizing capacitor (CSA).

[0142] The first stabilization electrode (CS1E) can define the first stabilization capacitor (CS1) by overlapping with the first common region (ATV_T3c) of the semiconductor layer (ATV). In this case, the first common region (ATV_T3c) of the semiconductor layer (ATV) can define the first terminal of the first stabilization capacitor (CS1), and the first stabilization electrode (CS1E) can define the second terminal of the first stabilization capacitor (CS1).

[0143] The Nth bias voltage line (VBIAS(N)) may define a second stabilized capacitor (CS2) by overlapping with the second common region (ATV_T4c) of the semiconductor layer (ATV). In this case, the second common region (ATV_T4c) of the semiconductor layer (ATV) may define the first terminal of the second stabilized capacitor (CS2), and the Nth bias voltage line (VBIAS(N)) may define the second terminal of the second stabilized capacitor (CS2).

[0144] FIG. 11 is a plan view for explaining the third conductive layer (C3).

[0145] Referring to FIG. 11, the pixel circuit (PXa) may include a third conductive layer (C3). The third conductive layer (C3) may include a conductive material. For example, the third conductive layer (C3) may include silver, a silver-containing alloy, titanium, a titanium-containing alloy, molybdenum, a molybdenum-containing alloy, aluminum, an aluminum-containing alloy, aluminum nitride, tungsten, tungsten nitride, copper, indium tin oxide, and indium zinc oxide, etc., and these may be used alone or in combination with each other. Additionally, the third conductive layer (C3) may have a single-layer or multi-layer structure including at least one of the materials described above.

[0146] The third conductive layer (C3) may include an initialization voltage line (VINT), a first vertical power supply voltage line (ELVDD_V), a diode initialization voltage line (VAINT), a first connection electrode (CE1), a second connection electrode (CE2), a first pixel bridge electrode (BR1_PXE), a first bias bridge electrode (BR1_VBIAS), a second bias bridge electrode (BR2_VBIAS), a second light emission control bridge electrode (BR2_EM), and a first data bridge electrode (BR1_DATA).

[0147] The initialization voltage may be applied to the initialization voltage line (VINT), the first power supply voltage may be applied to the first vertical power supply voltage line (ELVDD_V), and the diode initialization voltage may be applied to the diode initialization voltage line (VAINT).

[0148] FIG. 12 is a plan view illustrating a lower metal electrode (BML), a semiconductor layer (ATV), a first conductive layer (C1), a second conductive layer (C2), and a third conductive layer (C3).

[0149] Referring to FIG. 12, the third conductive layer (C3) can be placed on the lower metal electrode (BML), the semiconductor layer (ATV), the first conductive layer (C1), and the second conductive layer (C2).

[0150] The initialization voltage line (VINT) can be electrically contacted with the Nth region (A5(N)) of the semiconductor layer (ATV). Accordingly, the initialization voltage line (VINT) can provide the initialization voltage to the input terminal of the 4 sub-transistor (T4-2).

[0151] The first vertical power voltage line (ELVDD_V) can be electrically in contact with the second storage electrode (CSTE2). Accordingly, the first vertical power voltage line (ELVDD_V) can provide the first power voltage to the second storage electrode (CSTE2).

[0152] Additionally, the first vertical power voltage line (ELVDD_V) can be electrically contacted with the first stabilizing electrode (CS1E) and the first lower metal electrode (BML1), respectively. Accordingly, the first vertical power voltage line (ELVDD_V) electrically connects the first stabilizing electrode (CS1E) and the first lower metal electrode (BML1) to each other and can provide the first power voltage to the first stabilizing electrode (CS1E) and the first lower metal electrode (BML1), respectively. This will be described later with reference to FIG. 13.

[0153] The diode initialization voltage line (VAINT) can be electrically contacted with the N+1 region (A5(N+1)) of the semiconductor layer (ATV). Accordingly, the diode initialization voltage line (VAINT) can provide the diode initialization voltage to the input terminal of the diode initialization transistor (T7).

[0154] The first connecting electrode (CE1) can be electrically contacted with the first storage electrode (CSTE1) and the fourth region (A4) of the semiconductor layer (ATV). Accordingly, the first connecting electrode (CE1) can electrically connect the first storage electrode (CSTE1), the output terminal of the first sub-transistor (T3-1), and the output terminal of the third sub-transistor (T4-1) to each other.

[0155] The second connecting electrode (CE2) can be electrically contacted with the first gate voltage line (GW) and the second lower metal electrode (BML2), respectively. Accordingly, the second connecting electrode (CE2) can electrically connect the first gate voltage line (GW) and the second lower metal electrode (BML2) to each other.

[0156] The first pixel bridge electrode (BR1_PXE) can be electrically contacted with the seventh region (A7) of the semiconductor layer (ATV).

[0157] The first bias bridge electrode (BR1_VBIAS) can be electrically contacted with the N+1 bias voltage line (VBIAS(N+1)) and the 9th region (A9) of the semiconductor layer (ATV), respectively. Accordingly, the first bias bridge electrode (BR1_VBIAS) can electrically connect the N+1 bias voltage line (VBIAS(N+1)) and the input terminal of the bias transistor (T8) to each other, and the bias voltage can be provided to the input terminal of the bias transistor (T8) through the first bias bridge electrode (BR1_VBIAS).

[0158] The second bias bridge electrode (BR2_VBIAS) can be electrically connected to each of the first region (A1) and the eighth region (A8) of the semiconductor layer (ATV). Accordingly, the second bias bridge electrode (BR2_VBIAS) can electrically connect the output terminal of the bias transistor (T8) and the input terminal of the driving transistor (T1) to each other, and a signal output from the output terminal of the bias transistor (T8) can be provided to the input terminal of the driving transistor (T1) through the second bias bridge electrode (BR2_VBIAS).

[0159] The second light-emitting control bridge electrode (BR2_EM) can be electrically contacted with the first light-emitting control bridge electrode (BR1_EM).

[0160] The first data bridge electrode (BR1_DATA) can electrically contact the third region (A3) of the semiconductor layer (ATV).

[0161] FIG. 13 is a cross-sectional view taken along the line VV' of FIG. 12, FIG. 14 is a cross-sectional view taken along the line VI-VI' of FIG. 12, and FIG. 15 is a cross-sectional view taken along the line VII-VII' of FIG. 12.

[0162] Referring to FIGS. 13 to 15, the first organic insulating layer (ILO1) may be disposed on the fifth insulating layer (IL5) and may include an organic insulating material. For example, the first organic insulating layer (ILO1) may include at least one of an acrylic resin, a methacrylic resin, a polyisoprene, a vinyl resin, an epoxy resin, a urethane resin, a cellulose resin, a siloxane resin, a polyimide resin, a polyamide resin, and a perylene resin.

[0163] A third conductive layer (C3) may be placed on top of a fifth insulating layer (IL5), and a first organic insulating layer (ILO1) may cover the third conductive layer (C3). For example, as shown in FIGS. 13 to 15, a first vertical power supply voltage line (ELVDD_V), a second connecting electrode (CE2), a first bias bridge electrode (BR1_VBIAS), and a second bias bridge electrode (BR2_VBIAS) may each be placed on top of the fifth insulating layer (IL5), and a first organic insulating layer (ILO1) may cover a first vertical power supply voltage line (ELVDD_V), a second connecting electrode (CE2), a first bias bridge electrode (BR1_VBIAS), and a second bias bridge electrode (BR2_VBIAS).

[0164] Referring to FIG. 13, the first vertical power voltage line (ELVDD_V) can be electrically contacted with the first lower metal electrode (BML1) and the first stabilizing electrode (CS1E), respectively. Accordingly, the first vertical power voltage line (ELVDD_V) can electrically connect the first lower metal electrode (BML1) and the first stabilizing electrode (CS1E).

[0165] Since the first power supply voltage is applied to the first vertical power supply voltage line (ELVDD_V), the first power supply voltage can be applied to each of the first lower metal electrode (BML1) and the first stabilizing electrode (CS1E). In one embodiment, the first power supply voltage may be a constant voltage signal, and in this case, the same constant voltage signal may be applied to each of the first lower metal electrode (BML1) and the first stabilizing electrode (CS1E).

[0166] Referring to FIG. 14, the second connecting electrode (CE2) can be electrically contacted with the second lower metal electrode (BML2) and the first gate voltage line (GW), respectively. Accordingly, the first gate voltage applied to the first gate voltage line (GW) can be provided to the second lower metal electrode (BML2).

[0167] Referring to FIG. 15, the first bias bridge electrode (BR1_VBIAS) can be electrically contacted with the N+1 bias voltage line (VBIAS(N+1)) and the 9th region (A9) of the semiconductor layer (ATV), respectively. Accordingly, the bias voltage applied to the N+1 bias voltage line (VIBAS(N+1)) can be provided to the input terminal of the bias transistor (T8).

[0168] Additionally, the second bias bridge electrode (BR2_VBIAS) can be electrically contacted with the first region (A1) and the eighth region (A8) of the semiconductor layer (ATV), respectively. Accordingly, a signal output from the output terminal of the bias transistor (T8) can be provided to the input terminal of the driving transistor (T1).

[0169] FIG. 16 is a plan view for explaining the fourth conductive layer (C4).

[0170] Referring to FIG. 16, the pixel circuit (PXa) may include a fourth conductive layer (C4). The fourth conductive layer (C4) may include a conductive material. For example, the fourth conductive layer (C4) may include silver, a silver-containing alloy, titanium, a titanium-containing alloy, molybdenum, a molybdenum-containing alloy, aluminum, an aluminum-containing alloy, aluminum nitride, tungsten, tungsten nitride, copper, indium tin oxide, and indium zinc oxide, etc., and these may be used alone or in combination with each other. Additionally, the fourth conductive layer (C4) may have a single-layer or multi-layer structure including at least one of the materials described above.

[0171] The fourth conductive layer (C4) may include a horizontal bridge line (BRS_H), a third connecting electrode (CE3), a light emission control line (EM), a first horizontal power supply voltage line (ELVDD_H), a second data bridge electrode (BR2_DATA), and a second pixel bridge electrode (BR2_PXE).

[0172] The first power supply voltage may be applied to the first horizontal power supply voltage line (ELVDD_H), and the light emission control signal may be applied to the light emission control line (EM).

[0173] A horizontal bridge line (BRS_H) may include an Nth horizontal bridge line (BRS_H(N)) included in the pixel circuit of the Nth row and an N+1th horizontal bridge line (BRS_H(N+1)) included in the pixel circuit of the N+1th row.

[0174] FIG. 17 is a plan view illustrating a lower metal electrode (BML), a semiconductor layer (ATV), a first conductive layer (C1), a second conductive layer (C2), a third conductive layer (C3), and a fourth conductive layer (C4).

[0175] Referring to FIG. 17, the fourth conductive layer (C4) can be placed on the lower metal electrode (BML), the semiconductor layer (ATV), the first conductive layer (C1), the second conductive layer (C2), and the third conductive layer (C3).

[0176] The third connection electrode (CE3) can be electrically contacted with the initialization voltage line (VINT). In this case, although not shown in the drawing, the third connection electrode (CE3) can additionally be contacted with the initialization voltage line included in the adjacent pixel circuit.

[0177] FIG. 17 illustrates an embodiment in which the third connecting electrode (CE3) is electrically in contact with the initialization voltage line (VINT), but alternatively, the third connecting electrode (CE3) may be electrically in contact with the diode initialization voltage line (VAINT) instead of the initialization voltage line (VINT). In this case, the third connecting electrode (CE3) may additionally be in contact with the diode initialization voltage line included in the adjacent pixel circuit.

[0178] The light emission control line (EM) can be electrically contacted with the second light emission control bridge electrode (BR2_EM). This will be described later with reference to FIG. 18.

[0179] The first horizontal power voltage line (ELVDD_H) can be electrically connected to the first vertical power voltage line (ELVDD_V).

[0180] In addition, the first horizontal power voltage line (ELVDD_H) can overlap with the first connection electrode (CE1) in a plane. In this way, by shielding the first connection electrode (CE1) with the first horizontal power voltage line (ELVDD_H), the stability of the pixel circuit (PXCa) can be improved.

[0181] The second data bridge electrode (BR2_DATA) can be electrically contacted with the first data bridge electrode (BR1_DATA).

[0182] The second pixel bridge electrode (BR2_PXE) can be electrically contacted with the first pixel bridge electrode (BR1_PXE).

[0183] FIG. 18 is a cross-sectional view taken along the VIII-VIII' and IX-IX' lines of FIG. 17.

[0184] Referring to FIG. 18, the second organic insulating layer (ILO2) may be disposed on the first organic insulating layer (ILO1) and may include an organic insulating material. For example, the second organic insulating layer (ILO2) may include at least one of an acrylic resin, a methacrylic resin, a polyisoprene, a vinyl resin, an epoxy resin, a urethane resin, a cellulose resin, a siloxane resin, a polyimide resin, a polyamide resin, and a perylene resin.

[0185] The fourth conductive layer (C4) may be placed on the first organic insulating layer (ILO1), and the second organic insulating layer (ILO2) may cover the fourth conductive layer (C4). For example, as shown in FIG. 18, the light emission control line (EM) may be placed on the first organic insulating layer (ILO1), and the second organic insulating layer (ILO2) may cover the light emission control line (EM).

[0186] The light emission control line (EM) can be electrically contacted with the second light emission control bridge electrode (BR2_EM), and the second light emission control bridge electrode (BR2_EM) can be electrically contacted with the first light emission control bridge electrode (BR1_EM). Accordingly, the light emission control signal applied to the light emission control line (EM) can be provided to the first light emission control bridge electrode (BR1_EM) through the second light emission control bridge electrode (BR2_EM).

[0187] Referring to FIGS. 12, 17, and 18, the first light-emitting control bridge electrode (BR1_EM) may be spaced apart from the second bias bridge electrode (BR2_VBIAS) in a plane. That is, the first light-emitting control bridge electrode (BR1_EM) may not overlap with the second bias bridge electrode (BR2_VBIAS) in a plane.

[0188] Accordingly, signal interference between the light emission control signal provided to the first light emission control bridge electrode (BR1_EM) and the signal passing through the second bias bridge electrode (BR2_VBIAS) (e.g., the signal output from the output terminal of the bias transistor (T8)) may not substantially occur. That is, during the interval in which the light emission control signal provided to the first light emission control bridge electrode (BR1_EM) fluctuates, the signal passing through the second bias bridge electrode (BR2_VBIAS) may not substantially fluctuate.

[0189] Likewise, the second light emission control bridge electrode (BR2_EM) may be spaced apart in a plane from the second bias bridge electrode (BR2_VBIAS). Accordingly, signal interference between the light emission control signal provided to the second light emission control bridge electrode (BR2_EM) and the signal passing through the second bias bridge electrode (BR2_VBIAS) may not occur substantially.

[0190] Referring to FIGS. 17 and 18, in one embodiment, the light emission control line (EM) may overlap in a plane with the second light emission control bridge electrode (BR2_EM). However, in this case, signal interference between the light emission control signal applied to the light emission control line (EM) and the signal passing through the second bias bridge electrode (BR2_VBIAS) may not substantially occur.

[0191] Specifically, a first organic insulating layer (ILO1) may be disposed between the light emission control line (EM) and the second light emission control bridge electrode (BR2_EM), and the first organic insulating layer (ILO1) may have a relatively large thickness. For example, the thickness of the first organic insulating layer (ILO1) may be greater than the sum of the thickness of the third insulating layer (IL3), the thickness of the fourth insulating layer (IL4), and the thickness of the fifth insulating layer (IL5).

[0192] In this case, the distance between the lower surface of the light emission control line (EM) and the upper surface of the second light emission control bridge electrode (BR2_EM) may be relatively large, and accordingly, signal interference between the light emission control signal applied to the light emission control line (EM) and the signal passing through the second bias bridge electrode (BR2_VBIAS) may not substantially occur.

[0193] In contrast, a fourth inorganic insulating layer (IL4) and a fifth inorganic insulating layer (IL5) may be disposed between the first light-emitting control bridge electrode (BR1_EM) and the second bias bridge electrode (BR2_VBIAS), and each of the fourth inorganic insulating layer (IL4) and the fifth inorganic insulating layer (IL5) may have a relatively small thickness. For example, the sum of the thickness of the fourth inorganic insulating layer (IL4) and the thickness of the fifth inorganic insulating layer (IL5) may be smaller than the thickness of the first organic insulating layer (ILO1).

[0194] In this case, the distance between the upper surface of the first light-emitting control bridge electrode (BR1_EM) and the lower surface of the second bias bridge electrode (BR2_VBIAS) may be smaller than the distance between the lower surface of the light-emitting control line (EM) and the upper surface of the second light-emitting control bridge electrode (BR2_EM). Accordingly, when the first light-emitting control bridge electrode (BR1_EM) and the second bias bridge electrode (BR2_VBIAS) are arranged in an overlapping manner on a plane, signal interference may occur between the light-emitting control signal provided to the first light-emitting control bridge electrode (BR1_EM) and the signal passing through the second bias bridge electrode (BR2_VBIAS).

[0195] FIGS. 17 and 18 illustrate an embodiment in which the light emission control line (EM) overlaps in a plane with the second light emission control bridge electrode (BR2_EM), but the present invention is not limited thereto. For example, the light emission control line (EM) may not overlap in a plane with the second light emission control bridge electrode (BR2_EM).

[0196] FIG. 19 is a plan view for explaining the fifth conductive layer (C5).

[0197] Referring to FIG. 19, the pixel circuit (PXa) may include a fifth conductive layer (C5). The fifth conductive layer (C5) may include a conductive material. For example, the fifth conductive layer (C5) may include silver, a silver-containing alloy, titanium, a titanium-containing alloy, molybdenum, a molybdenum-containing alloy, aluminum, an aluminum-containing alloy, aluminum nitride, tungsten, tungsten nitride, copper, indium tin oxide, and indium zinc oxide, etc., and these may be used alone or in combination with each other. Additionally, the fifth conductive layer (C5) may have a single-layer or multi-layer structure including at least one of the materials described above.

[0198] The fifth conductive layer (C5) may include a data voltage line (DATA) and a vertical bridge line (BRS_V). The data voltage may be applied to the data voltage line (DATA).

[0199] FIG. 20 is a plan view illustrating a lower metal electrode (BML), a semiconductor layer (ATV), a first conductive layer (C1), a second conductive layer (C2), a third conductive layer (C3), a fourth conductive layer (C4), and a fifth conductive layer (C5).

[0200] Referring to FIG. 20, the fifth conductive layer (C5) can be placed on the lower metal electrode (BML), semiconductor layer (ATV), first conductive layer (C1), second conductive layer (C2), third conductive layer (C3) and fourth conductive layer (C4).

[0201] The data voltage line (DATA) can be electrically contacted with the second data bridge electrode (BR2_DATA). Accordingly, the data voltage applied to the data voltage line (DATA) can be provided to the input terminal of the switching transistor (T2) through the second data bridge electrode (BR2_DATA) and the first data bridge electrode (BR1_DATA).

[0202] In one embodiment, although not shown in the drawings, a horizontal bridge line (BRS_H) may be in electrical contact with a data line (DATA), or a vertical bridge line (BRS_V) may be in electrical contact with a horizontal bridge line (BRS_H). Accordingly, the data voltage applied to the data line (DATA) may be transmitted through various paths via the vertical bridge line (BRS_V) and / or the horizontal bridge line (BRS_H).

[0203] For example, a data line (DATA) can be electrically contacted with a horizontal bridge line (BRS_H), and the horizontal bridge line (BRS_H) can additionally be contacted with a data line included in a pixel circuit of the Mth row that is spaced apart from the pixel circuit (PXCa) in the row direction. Accordingly, the same data voltage can be applied to the data line (DATA) and the data line included in the pixel circuit of the Mth row. In this way, the vertical bridge line (BRS_V) and the horizontal bridge line (BRS_H) can serve to provide various paths so that the same data voltage can be applied to the data line (DATA) included in the pixel circuit (PXCa) and to the data line included in another pixel circuit spaced apart from the pixel circuit (PXCa).

[0204] FIG. 21 is a circuit diagram for explaining a pixel included in a display device according to another embodiment of the present invention.

[0205] Referring to FIG. 21, a display device according to another embodiment of the present invention may include a pixel (PXb). A pixel (PXb) may be defined as a minimum unit for emitting light and may include a pixel circuit (PXCb) and a light-emitting element (DIOD).

[0206] The light-emitting element (DIOD) may be substantially the same as the light-emitting element (DIOD) described with reference to FIG. 1. In addition, the pixel circuit (PXCb) may be substantially similar to the pixel circuit (PXCa) described with reference to FIG. 1. Specifically, the pixel circuit (PXCb) may be substantially the same as the pixel circuit (PXCa) described with reference to FIG. 1, except for the structure of the diode transistor (T3). Therefore, the description of redundant content is omitted below.

[0207] Each of the first sub-transistor (T3-1) and the second sub-transistor (T3-2) may have only one gate electrode. That is, each of the first sub-transistor (T3-1) and the second sub-transistor (T3-2) may not have a double-gate structure.

[0208] FIGS. 22 to 24 are drawings for explaining the pixels of FIG. 21. FIG. 22 is a plan view for explaining the lower metal electrode (BML'), FIG. 23 is a plan view for explaining the lower metal electrode (BML'), the semiconductor layer (ATV), and the first conductive layer (C1), and FIG. 24 is a cross-sectional view taken along the line XX' and the line XI-XI' of FIG. 23.

[0209] Referring to FIGS. 22 through 24, the pixel circuit (PXCb) may include a lower metal electrode (BML'), a semiconductor layer (ATV), and a first conductive layer (C1). Additionally, although not shown in the drawings, the pixel circuit (PXCb) may include a second conductive layer (C2), a third conductive layer (C3), a fourth conductive layer (C4), and a fifth conductive layer (C5). That is, the pixel circuit (PXCb) may include substantially the same components as the pixel circuit (PXCa) described with reference to FIGS. 2 through 20, except for the lower metal electrode (BML'). Therefore, descriptions of redundant content are omitted.

[0210] The lower metal electrode (BML') may include a first lower metal electrode (BML1). That is, the lower metal electrode (BML') may be a structure in which the second lower metal electrode (BML2) is omitted from the lower metal electrode (BML) described with reference to FIG. 2. In this case, the first sub-transistor (T3-1) and the second sub-transistor (T3-2) included in the pixel circuit (PXCb) may each be a single-gate transistor comprising only the top gate electrode defined by the first gate voltage line (GW).

[0211] In addition, in this case, the second connecting electrode (CE2) for electrically connecting the second lower metal electrode (BML2) and the first gate voltage line (GW) to each other in the third conductive layer (C3) included in the pixel circuit (PXCb) may be omitted.

[0212] FIG. 25 is a circuit diagram for explaining a pixel included in a display device according to another embodiment of the present invention.

[0213] Referring to FIG. 25, a display device according to another embodiment of the present invention may include a pixel (PXc). The pixel (PXc) may be defined as a minimum unit for emitting light and may include a pixel circuit (PXCc) and a light-emitting element (DIOD).

[0214] The light-emitting element (DIOD) may be substantially the same as the light-emitting element (DIOD) described with reference to FIG. 1. Additionally, the pixel circuit (PXCc) may be substantially similar to the pixel circuit (PXCa) described with reference to FIG. 1. Specifically, the pixel circuit (PXCc) may be substantially the same as the pixel circuit (PXCa) described with reference to FIG. 1, except that the additional-stabilization capacitor (CSA) is omitted. Therefore, descriptions of redundant content are omitted below.

[0215] FIGS. 26 to 28 are drawings for explaining the pixels of FIG. 25. FIG. 26 is a plan view for explaining the lower metal electrode (BML''), FIG. 27 is a plan view for explaining the lower metal electrode (BML'), the semiconductor layer (ATV), and the first conductive layer (C1), and FIG. 28 is a cross-sectional view taken along the lines XII-XII' and XIII-XIII' of FIG. 27.

[0216] Referring to FIGS. 26 through 28, the pixel circuit (PXCc) may include a lower metal electrode (BML``), a semiconductor layer (ATV), and a first conductive layer (C1). Additionally, although not shown in the drawings, the pixel circuit (PXCc) may include a second conductive layer (C2), a third conductive layer (C3), a fourth conductive layer (C4), and a fifth conductive layer (C5). That is, the pixel circuit (PXCc) may include substantially the same components as the pixel circuit (PXCa) described with reference to FIGS. 2 through 20, except for the lower metal electrode (BML``). Therefore, descriptions of redundant content are omitted.

[0217] The lower metal electrode (BML`') may include a second lower metal electrode (BML2). That is, the lower metal electrode (BML`') may be a structure in which the first lower metal electrode (BML1) is omitted from the lower metal electrode (BML`') described with reference to FIG. 2. In this case, the pixel circuit (PXCc) may not include an additional-stabilization capacitor (CSA).

[0218] In addition, in this case, in the third conductive layer (C3) included in the pixel circuit (PXCc), the first vertical power voltage line (ELVDD_V) can be electrically contacted with the second storage electrode (CSTE2) and the first stabilization electrode (CS1E), respectively.

[0219] Although the present invention has been described above with reference to embodiments thereof, those skilled in the art will understand that various modifications and changes can be made to the present invention without departing from the spirit and scope of the invention as described in the following claims. Industrial applicability

[0220] The display device according to the embodiments of the present invention can be applied to various electronic devices. For example, the display device according to the embodiments of the present invention can be applied to display devices included in computers, smartphones, smartpads, tablet PCs, etc. Explanation of the symbols

[0221] DIOD: Light-emitting element T1: Driving transistor T2: Switching transistor T3: Diode transistor T4: Driving initialization transistor T5: First light emission control transistor T6: Second light emission control transistor T7: Diode initialization transistor T8: Bias transistor CS1: First stabilization capacitor CS2: Second stabilization capacitor CSA: Additional stabilization capacitor T3-1: 1st sub-transistor T3-2: 2nd sub-transistor T4-1: 3rd sub-transistor T4-2: 4th sub-transistor VBIAS: Bias voltage line GW: 1st gate voltage line BR1_VBIAS: First bias bridge electrode BR2_VBIAS: Second bias bridge electrode BR1_EM: First light emission control bridge electrode BR2_EM: Second light emission control bridge electrode EM: Light emission control line BML1: First lower metal electrode BML2: Second lower metal electrode CS1E: First stabilizing electrode ATV_T3c: 1st common area ATV_T4c: 2nd common area

Claims

Claim 1 A display device comprising: a light-emitting element; a driving transistor that transmits a driving current to the light-emitting element; a bias transistor including an input terminal electrically connected to a bias voltage line; a first light-emitting control transistor including an output terminal electrically connected to the input terminal of the driving transistor and a gate electrode to which a light-emitting control signal is applied; a second light-emitting control transistor including an input terminal electrically connected to the output terminal of the driving transistor and a gate electrode to which the light-emitting control signal is applied; a bias bridge electrode electrically contacting the output terminal of the bias transistor and the input terminal of the driving transistor, respectively; and a first light-emitting control bridge electrode to which the light-emitting control signal is applied, which defines the gate electrode of the first light-emitting control transistor and the gate electrode of the second light-emitting control transistor, electrically connects the gate electrode of the first light-emitting control transistor and the gate electrode of the second light-emitting control transistor, and is spaced apart from the bias bridge electrode in a plane. Claim 2 A display device according to claim 1, further comprising: a second light-emitting control bridge electrode disposed on the first light-emitting control bridge electrode in a cross-section and electrically in contact with the first light-emitting control bridge electrode; and a light-emitting control line disposed on the second light-emitting control bridge electrode in a cross-section, electrically in contact with the second light-emitting control bridge electrode, to which the light-emitting control signal is applied. Claim 3 A display device according to claim 2, further comprising at least one inorganic insulating layer disposed between the second light-emitting control bridge electrode and the first light-emitting control bridge electrode in cross-section. Claim 4 A display device according to claim 2, further comprising at least one organic insulating layer disposed between the light-emitting control line and the second light-emitting control bridge electrode in cross-section. Claim 5 A display device according to claim 2, characterized in that, in cross-section, the distance between the lower surface of the light-emitting control line and the upper surface of the second light-emitting control bridge electrode is greater than the distance between the lower surface of the second light-emitting control bridge electrode and the upper surface of the first light-emitting control bridge electrode. Claim 6 A display device according to claim 2, wherein the second light-emitting control bridge electrode is spaced apart from the bias bridge electrode in a plane. Claim 7 A display device according to claim 2, wherein the second light-emitting control bridge electrode is disposed on the same layer as the bias bridge electrode. Claim 8 A display device according to claim 1, further comprising a diode transistor including: a first sub-transistor having an output terminal connected to the gate electrode of the driving transistor; and a second sub-transistor having an output terminal connected to the input terminal of the first sub-transistor and an input terminal connected to the output terminal of the driving transistor. Claim 9 A display device according to claim 8, further comprising a first stabilizing electrode defining a first stabilizing capacitor, overlapping with a first common region of a semiconductor layer defining each of the input terminal of the first sub-transistor and the output terminal of the second sub-transistor. Claim 10 A display device according to claim 9, further comprising a first lower metal electrode defining an additional-stabilizing capacitor, overlapping with the first common region of the semiconductor layer defining each of the input terminal of the first sub-transistor and the output terminal of the second sub-transistor. Claim 11 A display device according to claim 10, characterized in that, in cross-section, the first stabilizing electrode is disposed above the first common region of the semiconductor layer, and in cross-section, the first lower metal electrode is disposed below the first common region of the semiconductor layer. Claim 12 A display device according to claim 10, wherein the first stabilizing electrode and the first lower metal electrode are electrically connected to each other, and the same signal is applied to the first stabilizing electrode and the first lower metal electrode. Claim 13 A display device according to claim 12, characterized in that the signal applied to the first stabilizing electrode and the first lower metal electrode is a constant voltage signal. Claim 14 A display device according to claim 8, wherein each of the first sub-transistor and the second sub-transistor is a double-gate transistor comprising an upper gate electrode and a lower gate electrode. Claim 15 A display device according to claim 14, further comprising: a first gate voltage line defining the upper gate electrode of the first sub-transistor and the upper gate electrode of the second sub-transistor; and a second lower metal electrode defining the lower gate electrode of the first sub-transistor and the lower gate electrode of the second sub-transistor. Claim 16 A display device according to claim 15, wherein the first gate voltage line and the second lower metal electrode are electrically connected to each other, and the first gate voltage provided by the first gate voltage line is applied to the second lower metal electrode. Claim 17 A display device according to claim 1, further comprising a driving initialization transistor including: a third sub-transistor having an output terminal connected to the gate electrode of the driving transistor; and a fourth sub-transistor having an output terminal connected to the input terminal of the third sub-transistor and an input terminal connected to an initialization voltage line. Claim 18 A display device according to claim 17, wherein the bias voltage line overlaps with a second common region of a semiconductor layer defining the input terminal of the third sub-transistor and the output terminal of the fourth sub-transistor, respectively, to define a second stabilization capacitor. Claim 19 A display device characterized by comprising: a light-emitting element; a driving transistor that transmits a driving current to the light-emitting element; a bias transistor including an input terminal electrically connected to a bias voltage line; a first light-emitting control transistor including an output terminal electrically connected to the input terminal of the driving transistor and a gate electrode to which a light-emitting control signal is applied; a second light-emitting control transistor including an input terminal electrically connected to the output terminal of the driving transistor and a gate electrode to which the light-emitting control signal is applied; a diode transistor including a first sub-transistor whose output terminal is connected to the gate electrode of the driving transistor and a second sub-transistor whose output terminal is connected to the input terminal of the first sub-transistor and whose input terminal is connected to the output terminal of the driving transistor; and a first lower metal electrode that defines an additional-stabilization capacitor by overlapping with a first common region of a semiconductor layer defining each of the input terminal of the first sub-transistor and the output terminal of the second sub-transistor. Claim 20 A display device according to claim 19, further comprising a first stabilizing electrode defining a first stabilizing capacitor by overlapping with the first common region of the semiconductor layer defining each of the input terminal of the first sub-transistor and the output terminal of the second sub-transistor. Claim 21 A display device according to claim 19, wherein each of the first sub-transistor and the second sub-transistor is a double-gate transistor comprising an upper gate electrode and a lower gate electrode. Claim 22 A display device according to claim 21, further comprising: a first gate voltage line defining the upper gate electrode of the first sub-transistor and the lower gate electrode of the second sub-transistor; and a second lower metal electrode defining the lower gate electrode of the first sub-transistor and the lower gate electrode of the second sub-transistor, and electrically connected to the first gate voltage line. Claim 23 A display device according to claim 22, characterized in that the first lower metal electrode and the second lower metal electrode are disposed on the same layer. Claim 24 A display device according to claim 22, wherein, in a cross-sectional view, the first lower metal electrode and the second lower metal electrode are each disposed below the semiconductor layer, and in a planar view, the first lower metal electrode and the second lower metal electrode are spaced apart from each other. Claim 25 A display device comprising: a light-emitting element; a driving transistor that transmits a driving current to the light-emitting element; a bias transistor including an input terminal electrically connected to a bias voltage line; a first light-emitting control transistor including an output terminal electrically connected to the input terminal of the driving transistor and a gate electrode to which a light-emitting control signal is applied; a second light-emitting control transistor including an input terminal electrically connected to the output terminal of the driving transistor and a gate electrode to which the light-emitting control signal is applied; a diode transistor including a first sub-transistor whose output terminal is connected to the gate electrode of the driving transistor and a second sub-transistor whose output terminal is connected to the input terminal of the first sub-transistor and whose input terminal is connected to the output terminal of the driving transistor; a first gate voltage line defining the upper gate electrode of the first sub-transistor and the upper gate electrode of the second sub-transistor; and a second lower metal electrode defining the lower gate electrode of the first sub-transistor and the lower gate electrode of the second sub-transistor, wherein each of the first sub-transistor and the second sub-transistor is a double-gate transistor including an upper gate electrode and a lower gate electrode.

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