Chip packaging structure, semiconductor structure and method of manufacturing the same

Abstract

An implementation of a chip packaging structure, a semiconductor structure, and a method for manufacturing the same is disclosed. The chip packaging structure includes a substrate, and the substrate includes a signal transmission wiring structure embedded in the substrate and a heat transfer wiring structure embedded in the substrate. The chip packaging structure further includes a first chip that is on the substrate and is electrically connected to the signal transmission wiring structure. The chip packaging structure further includes at least one thermally conductive structure that is on the substrate, is in thermal contact with the heat transfer wiring structure, and laterally surrounds the first chip.

Description

Technology Field

[0001] This application is a continuation of International Application No. PCT / CN2023 / 109252, filed on July 26, 2023, titled “Chip packaging structure, semiconductor structure, and method of manufacturing the same,” which is incorporated herein in its entirety by reference. This disclosure generally relates to the field of semiconductor technology, and more specifically to chip packaging structures, related semiconductor structures, and methods of manufacturing the same. Background Technology

[0002] As the power consumption of semiconductor chips continues to increase, the requirements for heat dissipation in packages are also becoming higher. However, package materials have low thermal conductivity on the one hand, and on the other, most existing heat dissipation methods are handled at the system level. Specialized thermal conduction channels are required inside the chip package.

[0003] The present disclosure describes the implementation of a chip packaging structure, a semiconductor structure, and a method for manufacturing the same.

[0004] One aspect of the present disclosure provides a chip packaging structure, wherein the chip packaging structure comprises a substrate—the substrate includes a signal transmitting wiring structure embedded in the substrate and a thermal transmitting wiring structure embedded in the substrate—; a first chip on the substrate and electrically connected to the signal transmitting wiring structure; and at least one thermal conductive structure on the substrate and thermally contacting the thermal transmitting wiring structure and laterally surrounding the first chip.

[0005] In some embodiments, the chip packaging structure comprises: a mold compound layer on a substrate and covering a first chip—at least one thermally conductive structure embedded in the mold compound layer—; and a thermally conductive cover on the mold compound layer and in thermal contact with at least one thermally conductive structure.

[0006] In some embodiments, the chip packaging structure further comprises: a ball grid array on the side of the substrate opposite to the first chip and at least one thermally conductive structure, and the ball grid array further comprises: a plurality of signal solder balls in contact with a signal transmission wiring structure and at least one thermal solder ball in contact with a heat transfer wiring structure.

[0007] In some embodiments, at least one thermal conductive structure comprises: a top surface in contact with a thermal conductive cover and a bottom surface in contact with a thermal pad connected to a heat transfer wiring structure, and a plurality of thermal conductive blocks each penetrating a mold compound layer vertically.

[0008] In some implementations, the ratio between the first lateral area of ​​each thermally conductive block and the second lateral area of ​​the first chip is in the range between about 1 / 20 and about 1 / 10.

[0009] In some implementations, the chip packaging structure further includes a second chip located on a substrate and outside of at least one thermally conductive structure.

[0010] In some implementations, the chip packaging structure is: the first operating power of the first chip is greater than the second operating power of the second chip.

[0011] In some implementations, the first chip includes at least one of a microprocessing chip, a logic control chip, a power management chip, a driver chip, and an analog chip, and the second chip includes at least one of a memory chip and a sensing chip.

[0012] In some implementations, the chip packaging structure further includes a third chip that is on a substrate, is next to the first chip, and is laterally surrounded by at least one thermally conductive structure.

[0013] In some implementations, at least one part of a thermally conductive structure is located between the third chip and the first chip.

[0014] In some implementations, at least one material of the thermally conductive structure has a thermal conductive coefficient greater than 1.

[0015] In some implementations, the material is one of metal, ceramic material, or silicon material.

[0016] In some implementations, the chip packaging structure is such that the ratio between the first wiring width of the heat transfer wiring structure and the second wiring width of the signal transmission wiring structure is in the range of about 1.5 to about 2.

[0017] Another aspect of the present disclosure provides a method for forming a chip packaging structure, the method comprising: providing a substrate—the substrate comprises a signal transmission wiring structure embedded in the substrate and a heat transfer wiring structure embedded in the substrate—; forming at least one thermally conductive structure on a first side of the substrate that is in thermal contact with the heat transfer wiring structure; forming a first chip on a first side of the substrate—the first chip is laterally surrounded by the first chip—; and electrically connecting the first chip to the signal transmission wiring structure.

[0018] In some embodiments, the method further comprises: forming a mold compound layer on a first side of a substrate to cover a first chip and at least one thermally conductive structure; and forming a thermally conductive cover on the mold compound layer that is in thermal contact with at least one thermally conductive structure.

[0019] In some implementations, the method further comprises the step of forming a ball grid array on a second side of a substrate opposite to the first side, wherein the step comprises: forming a plurality of signal solder balls in contact with a signal transmission wiring structure and forming at least one thermal solder ball in contact with a heat transfer wiring structure.

[0020] In some embodiments, the step of forming at least one thermally conductive structure includes forming a plurality of thermally conductive blocks on a thermal pad, each of which is on a first side of the substrate and connected to a heat transfer wiring structure.

[0021] In some implementations, at least one thermally conductive structure and the first chip are formed on a substrate using a surface mount technology (SMT) process.

[0022] In some implementations, the method comprises: forming a second chip on a first side of a substrate, outside of at least one thermally conductive structure, wherein the first operating power of the first chip is greater than the second operating power of the second chip.

[0023] Another aspect of the present disclosure provides a semiconductor structure, wherein the semiconductor structure comprises: a printed circuit board; a chip packaging structure; and a ball grid array connected between the printed circuit board and the chip packaging structure, wherein the chip packaging structure comprises a substrate—the substrate comprises a signal transmission wiring structure embedded in the substrate and a heat transfer wiring structure embedded in the substrate—; a first chip on the substrate and electrically connected to the signal transmission wiring structure; and at least one thermally conductive structure on the substrate and thermally contacting the heat transfer wiring structure and laterally surrounding the first chip, and the ball grid array comprises a plurality of signal solder balls in contact with the signal transmission wiring structure and at least one thermal solder ball in contact with the heat transfer wiring structure.

[0024] Other aspects of the present disclosure may be understood by those skilled in the art in consideration of the description, claims, and drawings of the present disclosure. Brief explanation of the drawing

[0025] The attached drawings included herein and forming part of the specification serve to illustrate an implementation of the present disclosure, explain the principles of the present disclosure together with the description, and enable those skilled in the art to implement and use the present disclosure. FIG. 1 illustrates a schematic diagram in a side perspective view of an exemplary semiconductor structure according to a part of the present disclosure. FIG. 2a illustrates a schematic diagram in a plan view of an exemplary semiconductor structure according to a part of the present disclosure. FIG. 2b illustrates a schematic diagram in a plan view of another exemplary semiconductor structure according to some other implementation of the present disclosure. FIG. 2c illustrates a schematic diagram in a plan view of another exemplary semiconductor structure according to some other embodiment of the present disclosure. FIG. 2d illustrates a schematic diagram in a plan view of another exemplary semiconductor structure according to some other implementation of the present disclosure. FIG. 3 illustrates a flowchart of an exemplary method for forming a semiconductor structure according to a partial embodiment of the present disclosure. FIGS. 4 through 9 illustrate schematic diagrams in side perspective views of an exemplary semiconductor structure at a specific manufacturing step of the method illustrated in FIG. 3, according to a partial embodiment of the present disclosure. The features and advantages of the present disclosure will become more apparent from the detailed description below when similar reference numbers are taken together with drawings identifying corresponding elements throughout. In the drawings, similar reference numbers generally indicate elements that are identical, functionally similar, and / or structurally similar. The drawing in which each element first appears is indicated by the leftmost digit(s) of the corresponding reference number. An embodiment of the present disclosure will be described with reference to the accompanying drawings. Specific details for implementing the invention

[0026] It should be understood that while specific configurations and arrangements are discussed, they are for illustrative purposes only. Those skilled in the art will understand that other configurations and arrangements may be used without departing from the spirit and scope of this disclosure. Those skilled in the art will also understand that this disclosure may be used in various other applications.

[0027] Note that references in the specification to "one implementation," "implementation," "exemplary implementation," "partial implementation," etc., indicate that the described implementation may include specific features, structures, or characteristics, but that not all implementations are required to include specific features, structures, or characteristics. Furthermore, these phrases do not necessarily refer to the same implementation. Additionally, when specific features, structures, or characteristics are described in relation to an implementation, a person skilled in the art would know that such features, structures, or characteristics may affect other implementations, regardless of whether they are explicitly described.

[0028] Generally, terms can be understood, at least in part, through their use within the context. For example, the term "one or more" as used here may, at least in part depending on the context, be used to describe any feature, structure, or characteristic in a singular sense, or to describe a combination of features, structures, or characteristics in a plural sense. Similarly, even without the use of the suffix "s," it can be understood to convey either a singular or plural usage, at least in part depending on the context. Furthermore, the term "based on" is not necessarily intended to convey an exclusive set of factors; instead, it can be understood to allow for the existence of additional factors that do not need to be explicitly described, at least in part depending on the context.

[0029] It should be readily understood that in the present disclosure, the meanings of “on,” “above,” and “over” are to be interpreted in the broadest sense to include not only “immediately on” something, but also “on” something with intermediate features or layers between them. Furthermore, “above” or “over” includes not only “above” or “over” something, but also “above” or “over” something without intermediate features or layers between them (i.e., immediately above something).

[0030] Additionally, spatially relative terms such as "beneath," "below," "lower," "above," and "upper" may be used for convenience of description to explain the relationship of features to one element or other element(s) or feature(s), as exemplified in the drawings. Spatially relative terms are intended to encompass different orientations of the device during use or processing, in addition to the orientation depicted in the drawings. The device may be oriented differently (rotated 90 degrees or oriented in a different way), and the spatially relative descriptions used herein may likewise be interpreted accordingly.

[0031] As used herein, the term "substrate" refers to a material to which a subsequent layer of material is added. The substrate includes a "top" surface and a "bottom" surface. Since the front surface of the substrate is generally where the semiconductor device is formed, the semiconductor device is formed on the top side of the substrate unless otherwise specified. Since the bottom surface is opposite to the front surface, the bottom surface of the substrate is opposite to the top side of the substrate. The substrate itself may also be patterned. The material added on the top surface of the substrate may be patterned or may remain unpatterned. Additionally, the substrate may include a wide range of semiconductor materials such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate may be made of electrically nonconductive materials such as glass, plastic, or sapphire wafers.

[0032] As used herein, the term "layer" refers to a portion of material comprising a region of thickness. A layer has a top side and a bottom side, where the bottom side of the layer is adjacent to the substrate and the top side is relatively far from the substrate. A layer may extend across the entirety of an underlying or overlying structure, or may have an extent smaller than that of the underlying or overlying structure. Additionally, a layer may be a region of a homogeneous or heterogeneous continuous structure having a thickness smaller than that of the continuous structure. For example, a layer may be located between the top and bottom surfaces of the continuous structure or between any set of horizontal planes on those surfaces. A layer may extend along horizontal, vertical, and / or tapered surfaces. The substrate may be a layer, may contain one or more layers within it, and / or may have one or more layers on, above, and / or below it. A layer may comprise multiple layers. For example, the interconnect layer may include one or more conductive contact layers (where contacts, interconnect lines, and / or vertical interconnect accesses (VIAs) are formed) and one or more dielectric layers.

[0033] As used herein, the term "nominal / nominally" refers to a value range above and / or below the desired value, along with the desired or target value of a characteristic or parameter for a component or process step set during the design phase of a product or process. The range of values ​​may occur due to fine variations in the manufacturing process or tolerances. As used herein, the term "approximately" refers to a value of a given quantity that may vary based on a specific technology node associated with the target semiconductor device. Based on a specific technology node, the term "approximately" may refer to a value of a given quantity that varies, for example, within 10 to 30 percent of the value (e.g., ±10 percent, ±20 percent, or ±30 percent of the value).

[0034] In this disclosure, the terms “horizontal / horizontally / lateral / laterally” mean nominally parallel to the lateral surface of the substrate, and the terms “vertical” or “vertically” mean nominally perpendicular to the lateral surface of the substrate.

[0035] The present disclosure provides a chip packaging structure having high thermal conductivity. The manufacturing process can be modularized. In the disclosed chip packaging space, multiple thermally conductive structures of the same or different sizes are packaged around a chip stack and connected between a metal layer on the front of the package and a solder ball on the back to realize a strong heat dissipation effect. Through a surface mount technology (SMT) packaging process, a connection between the high thermal conductivity material and the copper layer of the substrate and a connection to the surface metal coating can be realized. Through this, high thermal conductivity can be obtained within the packaging structure, thereby significantly improving heat dissipation of the product and enhancing product performance.

[0036] The disclosed manufacturing process for forming the disclosed chip packaging structure is simple because it can be modularized. Existing equipment can be utilized in the disclosed manufacturing process without significant cost investment. Adopting a modular packaging solution reduces the difficulties of packaging and processing, thereby facilitating mass production. The disclosed design can achieve better internal thermal conductivity of the chip packaging structure without altering the external dimensions of the existing package or the existing packaging materials. Since materials with high thermal conductivity and high mechanical strength can be selected for the thermal conductive structures, the entire chip packaging structure can possess better heat dissipation and better mechanical properties. Furthermore, the disclosed manufacturing process allows for the flexible design of thermal conductive structures of different sizes and / or different quantities depending on space requirements. Consequently, the heat dissipation conditions of high-power chips within the disclosed chip packaging structure can be significantly improved, and the operating temperature of the disclosed chip packaging structure can be significantly reduced.

[0037] Referring to FIG. 1, a schematic diagram in a side perspective view of an exemplary semiconductor device structure according to some embodiment of the present disclosure is shown. As illustrated, the semiconductor device structure comprises a chip packaging structure (100), the chip packaging structure (100) comprises a substrate (120), a packaging body (110) on a first side of the substrate (120), and a ball grid array (BGA) (130) on a second side opposite to the first side of the substrate (120). Note that the semiconductor device structure (100) may further comprise other suitable components not shown in FIG. 1. For example, the semiconductor device may further comprise a printed circuit board (PCB) on which the chip packaging structure (100) is mounted via the BGA (130).

[0038] The substrate (120) may be any suitable semiconductor substrate having any suitable structure, such as a single-crystal single-layer substrate, a polycrystalline silicon (polysilicon) single-layer substrate, a polysilicon and metal multilayer substrate, etc. The substrate (120) may include a signal transmission wiring structure (146) and a heat transfer wiring structure (148) embedded in the substrate. The signal transmission wiring structure (146) may include any suitable conductive interconnect structure, such as a conductive via and a patterned conductive layer, and may be configured to transmit an electrical signal. The heat transfer wiring structure (148) may include any suitable thermal conductive interconnect structure, such as a thermal conductive channel, and may be configured to transfer heat. The signal transmission wiring structure (146) and the heat transfer wiring structure (148) may be isolated from each other.

[0039] In some embodiments, the signal transmission wiring structure (146) may comprise any suitable conductive material such as copper (Cu), nickel (Ni), gold (Au), silver (Ag), platinum (Pt), cobalt (Co), titanium (Ti), chromium (Cr), zirconium (Zr), molybdenum (Mo), ruthenium (Ru), hafnium (Hf), tungsten (W), rhenium (Re), graphite, carbon black, combinations thereof and / or other materials known to those skilled in the art. The heat transfer wiring structure (148) may comprise a suitable thermally conductive material such as Ag, Cu, aluminum (Al), aluminum nitride, silicon carbide, W, graphite, zinc (Zn), combinations thereof and / or other materials known to those skilled in the art. In some embodiments, the ratio between the first wiring width of the heat transfer wiring structure (148) and the second wiring width of the signal transmission wiring structure (146) may be in the range of about 1.5 to about 2.

[0040] The packaging body (110) may include a first die / die stack (162) and a second die / die stack (164) attached to a first side of the substrate (120) by an adhesive film (not shown). In some embodiments, the first die / die stack (162) and the second die / die stack (164) may be any suitable semiconductor die / die stack comprising one or more semiconductor chips. The first die / die stack (162) may include a low-power chip having a maximum operating power lower than a threshold power value. The second die / die stack (164) may include a high-power chip having a maximum operating power higher than a threshold power value. For example, the second die / die stack (164) may include at least one of a microprocessing chip, a logic control chip, a power management chip, a driver chip, and an analog chip, and the first die / die stack (162) may include at least one of a memory chip and a sensing chip. In some implementations, the adhesive film may be any suitable die attach film (DAF).

[0041] In some embodiments, a plurality of bond pads (157) (also referred to as contact pads, redistribution pads, or similar structures as known to those skilled in the art) may be located around the first die / die stack (162) and the second die / die stack (164) and may be electrically connected to a signal transmission wiring structure (146). In some embodiments, a plurality of signal wires (153) may be electrically connected between the plurality of bond pads (157) and the first die / die stack (162) or the second die / die stack (164). Thus, an electrical signal may be transmitted from the first die / die stack (162) and the second die / die stack (164) to the signal transmission wiring structure (146).

[0042] The chip packaging structure (100) may further include a mold compound layer (116) on a substrate (120) to completely cover a first die / die stack (162), a second die / die stack (164), and a plurality of signal wires (153). In some embodiments, the mold compound layer (116) may be a thermosetting epoxy mold compound or a thermosetting epoxy mold resin. For example, the mold compound layer (116) comprises an inorganic filler (e.g., silica), an epoxy resin, a curing agent, a flame retardant, a curing accelerator, a release agent, and any other suitable component known to those skilled in the art.

[0043] In some embodiments, a thermally conductive cover (190) may cover the mold compound layer (116). At least one thermally conductive structure (180) is arranged to laterally surround the second die / die stack (164) and to vertically penetrate the mold compound layer (116), and is connected between the thermally conductive cover (190) and the heat transfer wiring structure (148). In some embodiments, the height of at least one thermally conductive structure (180) may be greater than the height of the first die / die stack (162) or the second die / die stack (164). At least one thermally conductive structure (180) may include a plurality of thermally conductive blocks, each of which penetrates the mold compound layer (116) vertically and includes an upper surface in contact with the thermally conductive cover (190) and a lower surface in contact with a heat pad connected to the heat transfer wiring structure (148). In some embodiments, the material of the thermally conductive cover (190) and / or at least one thermally conductive structure (180) has a thermal conductivity coefficient greater than 1, for example, between 1 and 3. In some embodiments, the material of the thermally conductive cover (190) and / or at least one thermally conductive structure (180) is one of a metal, a ceramic material, or a silicon material.

[0044] In some implementations, the ball grid array (BGA) (130) may include a plurality of solder balls (132 / 135) attached to a second side opposite to the first side of the substrate (120). The BGA (130) may include a plurality of signal solder balls (132) in contact with a signal transmission wiring structure (146) and at least one thermal solder ball (135) in contact with a thermal transmission wiring structure (148). That is, the signal solder balls (132) are electrically coupled to a first die / die stack (162) and a second die / die stack (164) to provide transmission of electrical signals between the first die / die stack (162) and the second die / die stack (164) and the PCB. The thermal solder ball (135) can be combined with the thermal conductive structure (180) through the thermal transfer wiring structure (148) and can be configured for heat dissipation of the second die / die stack (164).

[0045] In some embodiments, the signal solder ball (132) and the thermal solder ball (135) may be composed of the same material and may be formed by the same process. For example, the signal solder ball (132) and the thermal solder ball (135) may comprise any suitable metal material such as aluminum (Al), antimony (Sb), arsenic (As), bismuth (Bi), cadmium (Cd), Co, Cu, Ni, Au, Ag, indium (In), iron (Fe), lead (Pb), phosphorus (P), tin (Sn), sulfur (S), zinc (Zn), germanium (Ge), and any suitable alloy thereof. In some other embodiments, the signal solder ball (132) and the thermal solder ball (135) may be composed of different materials. For example, the signal solder ball (132) may comprise a first material having a high electrical conductivity coefficient, and the thermal solder ball (135) may comprise a second material having a high thermal conductivity coefficient.

[0046] FIGS. 2a through 2d illustrate schematic plans of various designs of exemplary semiconductor structures (200A, 200B, 200C, 200D) according to various embodiments of the present disclosure. Note that the disclosed flexible design may allow for different sizes, different shapes, and / or different quantities of thermally conductive structures (180) depending on space requirements. In the examples illustrated in 200A, 200B, 200C, and 200D, the thermally conductive structures (180) may comprise a plurality of thermally conductive blocks (185) having a planar cross-section that is approximately square in shape. In some other embodiments not illustrated, the planar cross-section of each thermally conductive structure (180) may have a planar shape that is approximately rectangular, approximately circular, approximately elliptical, approximately trapezoidal, etc.

[0047] As illustrated in FIG. 2a, a plurality of thermally conductive blocks (185) may be arranged to surround a first chip (264) laterally. The first chip (264) may be a high-power chip having a first operating power higher than a threshold power value. A second chip (264) outside the plurality of thermally conductive blocks (185) may be a low-power chip having a second operating power higher than a threshold power value. In some implementations, the first chip (264) may be a microprocessing chip, a logic control chip, a power management chip, a driver chip, or an analog chip. The second chip (262) may be a memory chip or a sensing chip.

[0048] In some other implementations, as illustrated in FIG. 2b, a plurality of second chips (262) (e.g., number M of low-power chips) may be stacked vertically to form a die stack. Due to thermal management, the first chips (264) are not stacked together to form the die stack. Instead, the first chips (264) may be arranged side by side and laterally surrounded by a plurality of thermally conductive blocks (185), as illustrated in FIG. 2c. In some other implementations, as illustrated in FIG. 2d, some of the plurality of thermally conductive blocks (185) may be positioned between adjacent first chips (264).

[0049] In some embodiments, the first side area of ​​the planar cross-section of each thermally conductive block (185) may be about 1 mm. In some embodiments, the ratio between the first side area of ​​each thermally conductive block (185) and the second side area of ​​the first chip (264) may be in the range between about 1 / 20 and about 1 / 10. Note that while a plurality of thermally conductive blocks (185) surround the first chip (264) in a single circle as shown in FIGS. 2a through 2d, in some other embodiments not shown, a plurality of thermally conductive blocks (185) may surround the first chip (264) in more than one circle.

[0050] Referring to FIG. 3, a flowchart of an exemplary method for forming a semiconductor structure according to some embodiment of the present disclosure is illustrated. The operations and / or steps illustrated in FIG. 3 are not exhaustive, and other operations may be performed before, after, or between the illustrated operations. FIGS. 4 through 9 illustrate schematic diagrams in side perspective views of an exemplary semiconductor structure at a specific manufacturing step of the method illustrated in FIG. 3 according to some embodiment of the present disclosure.

[0051] As illustrated in FIG. 3, the method (300) begins with an operation (310), wherein a substrate including a signal transmission wiring structure and a heat transfer wiring structure may be provided. FIG. 4 illustrates a schematic diagram in a side perspective view of an exemplary semiconductor structure after the operation (310) of the method (300) illustrated in FIG. 3, according to a partial embodiment of the present disclosure.

[0052] As illustrated in FIG. 4, in some embodiments, the substrate (120) may include a signal transmission wiring structure (146) and a heat transfer wiring structure (148) embedded therein. The substrate (120) may be any suitable semiconductor substrate having any suitable structure, such as a single-crystal single-layer substrate, a polycrystalline silicon (polysilicon) single-layer substrate, a polysilicon and metal multilayer substrate, etc.

[0053] The signal transmission wiring structure (146) may include suitable conductive interconnect structures, such as conductive vias and patterned conductive layers, and may be configured to transmit electrical signals. The heat transfer wiring structure (148) may include suitable thermal conductive interconnect structures, such as thermal conductive channels, and may be configured to transfer heat. The signal transmission wiring structure (146) and the heat transfer wiring structure (148) may be isolated from each other.

[0054] In some embodiments, the signal transmission wiring structure (146) may comprise any suitable conductive material such as copper (Cu), nickel (Ni), gold (Au), silver (Ag), platinum (Pt), cobalt (Co), titanium (Ti), chromium (Cr), zirconium (Zr), molybdenum (Mo), ruthenium (Ru), hafnium (Hf), tungsten (W), rhenium (Re), graphite, carbon black, combinations thereof and / or other materials known to those skilled in the art. The heat transfer wiring structure (148) may comprise any suitable thermally conductive material such as Ag, Cu, aluminum (Al), aluminum nitride, silicon carbide, W, graphite, zinc (Zn), combinations thereof and / or other materials known to those skilled in the art. In some embodiments, the ratio between the first wiring width of the heat transfer wiring structure (148) and the second wiring width of the signal transmission wiring structure (146) may be in the range of about 1.5 to about 2.

[0055] In some embodiments, a plurality of bond pads (157) (also referred to as contact pads, redistribution pads, or similar structures as known to those skilled in the art) may be formed on a first surface of the substrate (120) and may be electrically connected to a signal transmission wiring structure (146). In some embodiments, an array of ball pads (not shown) may be formed on a second surface of the substrate (120) opposite to the first surface. The array of ball pads may be used to form an array of BGAs in a subsequent process.

[0056] Referring again to FIG. 3, the method (300) may proceed to operation (320), wherein at least one thermally conductive structure may be formed on a first side of the substrate. FIG. 5 illustrates a schematic diagram in a side perspective view of an exemplary semiconductor structure (500) after operation (320) of the method (300) illustrated in FIG. 3, according to a partial embodiment of the present disclosure.

[0057] In some embodiments, at least one thermally conductive structure (180) may be formed on a first surface of the substrate (120) and may be in thermal contact with a heat transfer wiring structure (148). In some embodiments, at least one thermally conductive structure (180) may laterally surround at least one area for attaching at least one first chip having a first operating power higher than a threshold power value in a subsequent process. In some embodiments, forming at least one thermally conductive structure (180) comprises forming a plurality of thermally conductive blocks (e.g., thermally conductive blocks shown in FIGS. 2a through 2d), each thermally conductive block being on a first side of the substrate (120) and on a thermal pad (582) connected to a heat transfer wiring structure (148).

[0058] In some embodiments, the material of at least one thermally conductive structure (180) has a thermal conductivity greater than 1, for example, a thermal conductivity between 1 and 3. In some embodiments, the material of at least one thermally conductive structure (180) is one of a metal, a ceramic material, or a silicon material. In some embodiments, the first side area of ​​the planar cross-section of each thermally conductive block may be about 1 mm.

[0059] Referring again to FIG. 3, the method (300) may proceed to operation (330), wherein a first chip is formed on a first side of a substrate and may be laterally surrounded by at least one thermally conductive structure. In some embodiments, the operation (330) further includes the step of forming a second chip on the first side of the substrate, outside of at least one thermally conductive structure. FIG. 6 illustrates a schematic diagram in a side perspective view of an exemplary semiconductor structure (600) after operation (330) of the method (300) illustrated in FIG. 3, according to some embodiments of the present disclosure.

[0060] In some embodiments, the first chip (664) and / or the second chip (662) may be attached to a first surface of the substrate (120) using any suitable adhesive or fixing means known in the art. In some embodiments, an adhesive film (not shown), such as a die attach film (DAF), may be attached to the bottom surface of the first chip (664) and / or the second chip (662). The first chip (664) and / or the second chip (662) may be permanently attached or fixed to the first surface of the substrate (120).

[0061] In some implementations, the first chip (664) may be a high-power chip having a first operating power higher than a threshold power value and may be attached within an area enclosed by at least one thermally conductive structure (180). The second chip (664) may be a low-power chip having a second operating power higher than a threshold power value and may be attached within an area outside of at least one thermally conductive structure (180). In some implementations, the first chip (664) may be a microprocessing chip, a logic control chip, a power management chip, a driver chip, or an analog chip. The second chip (662) may be a memory chip or a sensing chip.

[0062] In some implementations, multiple second chips (662) may be stacked vertically to form a die stack. Due to thermal management, the first chips (264) are not stacked together to form a die stack. Instead, the first chips (664) may be arranged side by side and laterally surrounded by at least one thermally conductive structure (180). In some implementations, the ratio between the first side area of ​​each thermally conductive block and the second side area of ​​the first chips (664) may be in the range between about 1 / 20 and about 1 / 10.

[0063] In some implementations, the operation (330) further includes the step of wiring the first chip (664) and / or the second chip (662) to a plurality of bond pads (157). For example, a plurality of signal wires (153) may be formed to electrically connect a plurality of bond pads (157) to the first chip (664) and / or the second chip (662), so that the first chip (664) and / or the second chip (662) are electrically coupled to the signal transmission wiring structure (146).

[0064] Referring again to FIG. 3, the method (300) may proceed to operation (340), wherein a mold compound layer may be formed on a first side of the substrate to cover the chip and at least one thermally conductive structure. FIG. 7 illustrates a schematic diagram in a side perspective view of an exemplary semiconductor structure (700) after operation (340) of the method (300) illustrated in FIG. 3, according to a partial embodiment of the present disclosure.

[0065] In some embodiments, the mold compound layer (116) is formed on a first side of the substrate (120) to cover the first chip (664) and / or the second chip (662), at least one thermally conductive structure (180), and a plurality of signal wires (153). In some embodiments, the mold compound layer (116) may be formed from any suitable material, such as a thermosetting epoxy mold compound material or a thermosetting epoxy mold resin. For example, the mold compound layer (116) may be formed using an inorganic filler (e.g., silica), an epoxy resin, a curing agent, a flame retardant, a curing accelerator, a release agent, and any other suitable component known to those skilled in the art.

[0066] Referring again to FIG. 3, the method (300) may proceed to operation (350), wherein a thermally conductive cover is formed on a molded compound layer and may come into contact with at least one thermally conductive structure. FIG. 8 illustrates a schematic diagram in a side perspective view of an exemplary semiconductor structure (800) after operation (350) of the method (300) illustrated in FIG. 3, according to a partial embodiment of the present disclosure.

[0067] In some embodiments, the upper portion of the mold compound layer (116) can be removed through any suitable process, such as chemical mechanical polishing (CMP) or gridding, so that at least one thermally conductive structure (180) may be exposed. Then, a thermally conductive cover (190) is formed on the remaining portion of the mold compound layer (116) and may be in direct contact with at least one thermally conductive structure (180). Accordingly, heat generated by the first chip (664) can be distributed by the at least one thermally conductive structure (180) to two surfaces of the formed semiconductor, namely the thermally conductive cover (190) and the heat transfer wiring structure (148). In some embodiments, the thermally conductive cover (190) may be formed of a thermal conductor having a thermal conductivity coefficient greater than 1, for example, between 1 and 3. In some embodiments, the material of the thermally conductive cover (190) is one of a metal, a ceramic material, or a silicon material.

[0068] Referring again to FIG. 3, the method (300) may proceed to operation (360), where a ball grid array (BGA) may be formed on a second side of the semiconductor structure. FIG. 9 illustrates a schematic diagram in a side perspective view of an exemplary semiconductor structure (900) after operation (360) of the method (300) illustrated in FIG. 3, according to a partial embodiment of the present disclosure.

[0069] As illustrated in FIG. 9, a ball grid array (BAG) (130) may be formed on a second surface of a base substrate (120) opposite to the packaging body (110). The BAG (130) may include a plurality of solder balls (132 / 135) attached to an array (not shown) of ball pads on the second surface of the base substrate (120). A plurality of signal solder balls (132) may be formed in contact with a signal transmission wiring structure (146), and at least one thermal solder ball (135) may be formed in contact with a heat transfer wiring structure (148). Accordingly, the thermal solder ball (135) may be coupled to a thermal conductive structure (180) through the heat transfer wiring structure (148) and may be configured to dissipate operating heat generated by the first chip (664). The signal solder ball (132) can be electrically coupled with the first chip (664) and the second chip (662) to provide signal transmission.

[0070] In some embodiments, the signal solder ball (132) and the thermal solder ball (135) may be formed simultaneously in the same process using the same material. For example, the signal solder ball (132) and the thermal solder ball (135) may be formed using any suitable metal material such as aluminum (Al), antimony (Sb), arsenic (As), bismuth (Bi), cadmium (Cd), Co, Cu, Ni, Au, Ag, indium (In), iron (Fe), lead (Pb), phosphorus (P), tin (Sn), sulfur (S), zinc (Zn), germanium (Ge), etc. and suitable alloys thereof. In some other embodiments, the signal solder ball (132) and the thermal solder ball (135) may be formed using different materials through different processes. For example, the signal solder ball (132) can be formed using a first material having a high electrical conductivity coefficient, and the thermal solder ball (135) can be formed using a second material having a high thermal conductivity coefficient.

[0071] Note that although not illustrated, the method (300) may further include any other suitable operation to further form a semiconductor structure. For example, the formed chip packaging structure (900) may be attached to a printed circuit board (PCB). And a plurality of signal solder balls (132) and thermal solder balls (135) may be used to provide a mechanical connection between the chip packaging structure (900) and the PCB.

[0072] Accordingly, the present disclosure provides a chip packaging structure having high thermal conductivity. The manufacturing process can be modularized. In the disclosed chip packaging space, multiple thermally conductive structures of the same or different sizes can be packaged around a chip stack and connected between a metal layer on the front of the package and a solder ball on the back to realize a strong heat dissipation effect. Through a surface mount technology (SMT) packaging process, a connection between the high thermal conductivity material and the copper layer of the substrate and a connection of the surface metal coating can be realized. This allows for high thermal conductivity to be obtained within the packaging structure, thereby significantly improving product heat dissipation and enhancing product performance.

[0073] The disclosed manufacturing process for forming the disclosed chip packaging structure is simple because it can be modularized. Existing equipment can be utilized in the disclosed manufacturing process without significant cost investment. Adopting a modular packaging solution reduces packaging and processing difficulties, thereby facilitating mass production. The disclosed design can achieve better internal thermal conductivity of the chip packaging structure without altering the external dimensions of the existing package or the existing packaging materials. Since materials with high thermal conductivity and high mechanical strength can be selected for the thermal conductive structures, the entire chip packaging structure can possess better heat dissipation and better mechanical properties. Furthermore, the disclosed manufacturing process allows for the flexible design of thermal conductive structures of different sizes and / or different quantities depending on space requirements. Consequently, the heat dissipation conditions of high-power chips within the disclosed chip packaging structure can be significantly improved, and the operating temperature of the disclosed chip packaging structure can be significantly reduced.

[0074] The description of the specific implementations given above is sufficient to reveal the general nature of the present disclosure, so that others can easily modify and / or adapt these specific implementations for various applications by applying their knowledge of the art, without unnecessary experimentation, and without departing from the general concept of the present disclosure. Accordingly, such adaptations and modifications are intended to be within the equivalent meaning and scope of the disclosed implementations based on the disclosures and guidelines set forth herein. Phrases and terms used herein are for illustrative purposes only and not for limitation, and it should be understood that the terms and phrases of this specification are to be interpreted by a person skilled in the art in light of the present disclosures and guidelines.

[0075] The implementation of the present disclosure has been described above with the help of functional building blocks that exemplify the implementation of specific functions and their relationships. The boundaries of these functional building blocks have been defined arbitrarily for convenience of explanation. Alternative boundaries may be defined as long as the specified functions and relationships are properly performed.

[0076] Since the Description and Summary section may describe one or more embodiments of the present disclosure, not all exemplary embodiments conceived by the inventor(s), there is no intention to limit the present disclosure and the appended claims in any way.

[0077] The breadth and scope of the present disclosure should not be limited by the exemplary implementations described above, but should be defined only by the following claims and their equivalents.

Claims

Claim 1 A chip packaging structure comprising: a substrate - said substrate includes a signal transmitting wiring structure embedded in said substrate and a thermal transmitting wiring structure embedded in said substrate -; a first chip on said substrate and electrically connected to said signal transmitting wiring structure; and at least one thermally conductive structure on said substrate, in thermal contact with said thermal transmitting wiring structure and laterally surrounding said first chip. Claim 2 A chip packaging structure according to claim 1, further comprising: a mold compound layer on the substrate and covering the first chip, wherein at least one thermally conductive structure is embedded in the mold compound layer; and a thermally conductive cover on the mold compound layer and in thermal contact with the at least one thermally conductive structure. Claim 3 A chip packaging structure according to claim 1, further comprising a ball grid array on a side of the substrate opposite to the first chip and the at least one thermal conductive structure, wherein the ball grid array comprises a plurality of signal solder balls in contact with the signal transmission wiring structure and at least one thermal solder ball in contact with the heat transfer wiring structure. Claim 4 A chip packaging structure according to paragraph 2, wherein the at least one thermally conductive structure comprises a plurality of thermally conductive blocks, and each of the plurality of thermally conductive blocks vertically penetrates the mold compound layer and comprises an upper surface in contact with the thermally conductive cover and a lower surface in contact with a thermal pad connected to the heat transfer wiring structure. Claim 5 A chip packaging structure according to claim 4, wherein the ratio between the first side area of ​​each thermally conductive block and the second side area of ​​the first chip is in the range between 1 / 20 and 1 / 10. Claim 6 A chip packaging structure according to claim 1, further comprising a second chip located on the substrate and outside of the at least one thermally conductive structure. Claim 7 In claim 6, the chip packaging structure wherein the first operating power of the first chip is greater than the second operating power of the second chip. Claim 8 A chip packaging structure according to claim 6, wherein the first chip comprises at least one of a microprocessing chip, a logic control chip, a power management chip, a driver chip, and an analog chip, and the second chip comprises at least one of a memory chip and a sensing chip. Claim 9 A chip packaging structure according to claim 1, further comprising a third chip located on the substrate, next to the first chip, and laterally surrounded by the at least one thermally conductive structure. Claim 10 In claim 9, a chip packaging structure wherein a portion of the at least one thermally conductive structure is located between the third chip and the first chip. Claim 11 In claim 1, the material of the at least one thermally conductive structure has a thermal conductivity coefficient greater than 1, forming a chip packaging structure. Claim 12 In claim 11, the above material is a chip packaging structure, which is one of a metal, a ceramic material, or a silicon material. Claim 13 A chip packaging structure according to claim 1, wherein the ratio between the first wiring width of the heat transfer wiring structure and the second wiring width of the signal transmission wiring structure is in the range of 1.5 to 2. Claim 14 A method for forming a chip packaging structure comprising: providing a substrate, wherein the substrate comprises a signal transmission wiring structure embedded in the substrate and a heat transfer wiring structure embedded in the substrate; forming at least one thermally conductive structure on a first side of the substrate that is in thermal contact with the heat transfer wiring structure; forming a first chip on the first side of the substrate, wherein the first chip is laterally surrounded by the first chip; and electrically connecting the first chip to the signal transmission wiring structure. Claim 15 A method for forming a chip packaging structure according to claim 14, further comprising the steps of: forming a mold compound layer on a first side of the substrate to cover the first chip and the at least one thermally conductive structure; and forming a thermally conductive cover on the mold compound layer that is in thermal contact with the at least one thermally conductive structure. Claim 16 A method for forming a chip packaging structure according to claim 15, further comprising the step of forming a ball grid array on a second side of a substrate opposite to the first side, wherein the step of forming the ball grid array comprises: forming a plurality of signal solder balls in contact with the signal transmission wiring structure; and forming at least one thermal solder ball in contact with the thermal transfer wiring structure. Claim 17 A method for forming a chip packaging structure according to claim 14, wherein the step of forming at least one thermally conductive structure comprises: forming a plurality of thermally conductive blocks on a thermal pad that is on a first side of the substrate and connected to the thermal transfer wiring structure. Claim 18 A method for forming a chip packaging structure according to claim 14, wherein the at least one thermally conductive structure and the first chip are formed on the substrate using a surface mount technology (SMT) process. Claim 19 A method for forming a chip packaging structure according to claim 15, further comprising the step of forming a second chip on a first side of the substrate, outside of the at least one thermally conductive structure, wherein the first operating power of the first chip is greater than the second operating power of the second chip. Claim 20 A semiconductor structure comprising: a printed circuit board; a chip packaging structure; and a ball grid array connected between the printed circuit board and the chip packaging structure, wherein the chip packaging structure comprises: a substrate - the substrate comprises a signal transmission wiring structure embedded in the substrate and a heat transfer wiring structure embedded in the substrate -; a first chip on the substrate and electrically connected to the signal transmission wiring structure; and at least one thermally conductive structure on the substrate, in thermal contact with the heat transfer wiring structure and laterally surrounding the first chip, and wherein the ball grid array comprises a plurality of signal solder balls in contact with the signal transmission wiring structure; and at least one thermal solder ball in contact with the heat transfer wiring structure.

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