Display device and method of manufacturing the display device

Abstract

A display device and a method for manufacturing the same are provided. The display device includes light-emitting elements disposed on a substrate, and each of the light-emitting elements includes a first semiconductor layer, an active layer disposed on the first semiconductor layer, a second semiconductor layer disposed on the active layer, and a porous layer disposed on the second semiconductor layer.

Description

Technology Field

[0001] The present invention relates to a light-emitting display device and a method for manufacturing the same. Background Technology

[0002] With the recent rise in interest in information displays, research and development on display devices is continuously being carried out. The problem to be solved

[0003] The problem that the present invention aims to solve is to provide a display device and a method for manufacturing the same that can improve the light emission efficiency of a display panel while simultaneously simplifying the manufacturing process.

[0004] The problems of the present invention are not limited to those mentioned above, and other unmentioned technical problems will be clearly understood by those skilled in the art from the description below. means of solving the problem

[0005] A display device according to one embodiment for solving the above problem includes light-emitting elements disposed on a substrate, and each of the light-emitting elements includes a first semiconductor layer, an active layer disposed on the first semiconductor layer, a second semiconductor layer disposed on the active layer, and a porous layer disposed on the second semiconductor layer.

[0006] The above porous layer may include nanoscale pores.

[0007] The porous layer may include the same material as the second semiconductor layer.

[0008] The above display device further includes bank patterns disposed on the substrate, and the light-emitting elements may each be disposed between the bank patterns.

[0009] The bank patterns above may include the same material as the light-emitting elements.

[0010] The above display device may further include a color conversion layer disposed on the light-emitting elements.

[0011] The above display device may further include a reflective layer disposed between the light-emitting elements.

[0012] The above display device may further include an insulating layer disposed between the light-emitting elements and the reflective layer.

[0013] The light-emitting elements may include a first light-emitting element that emits a first color, a second light-emitting element that emits a second color, and a third light-emitting element that emits a third color.

[0014] A method for manufacturing a display device according to one embodiment for solving the above problem comprises the steps of forming a semiconductor layer, forming a porous layer by at least partially etching the semiconductor layer, and forming light-emitting elements by providing a light-emitting laminate on the porous layer.

[0015] Nanoscale voids may be formed during the step of etching the semiconductor layer.

[0016] The step of forming the light-emitting elements may further include the step of etching the porous layer and the light-emitting laminate.

[0017] The light-emitting laminate may include a first semiconductor layer, a second semiconductor layer formed on the first semiconductor layer, and an active layer formed between the first semiconductor layer and the second semiconductor layer.

[0018] The second semiconductor layer can be formed of the same material as the porous layer.

[0019] The method for manufacturing the above display device may further include the step of etching the porous layer and the light-emitting laminate to form bank patterns.

[0020] The bank patterns mentioned above can be formed simultaneously with the light-emitting elements.

[0021] The semiconductor layer may include a second semiconductor layer provided between the porous layer and the light-emitting laminate.

[0022] The step of providing the light-emitting laminate may include the step of providing an active layer on the second semiconductor layer and the step of providing a first semiconductor layer on the active layer.

[0023] The above display device may further include the step of forming a flattening layer between the light-emitting elements.

[0024] The above display device may further include the step of forming a reflective layer between the light-emitting elements.

[0025] Specific details of other embodiments are included in the detailed description and drawings. Effects of the invention

[0026] According to an embodiment of the present invention, a porous region embedded in the light-emitting elements can scatter light emitted from the light-emitting region to improve light emission efficiency. Accordingly, since a scattering layer separately provided within the pixel can be omitted, the manufacturing process can be simplified and costs can be reduced.

[0027] The effects according to the embodiments are not limited to those exemplified above, and a wider variety of effects are included in this specification. Brief explanation of the drawing

[0028] FIG. 1 is a plan view showing a display device according to one embodiment. FIG. 2 is a circuit diagram of a pixel according to one embodiment. FIGS. 3 and FIGS. 4 are cross-sectional views showing a pixel according to one embodiment. FIG. 5 is a cross-sectional view showing a pixel according to another embodiment. FIG. 6 is a cross-sectional view showing a pixel according to another embodiment. FIGS. 7 to 16 are cross-sectional views of the process steps of a method for manufacturing a display device according to one embodiment. FIGS. 17 to 26 are cross-sectional views of process steps of a method for manufacturing a display device according to another embodiment. FIGS. 27 to 30 are exemplary drawings illustrating electronic devices according to various embodiments. Specific details for implementing the invention

[0029] The advantages and features of the present invention and the methods for achieving them will become clear by referring to the embodiments described below in detail together with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below but can be implemented in various different forms. These embodiments are provided to ensure that the disclosure of the present invention is complete and to fully inform those skilled in the art of the scope of the invention, and the present invention is defined only by the scope of the claims.

[0030] The terms used herein are for describing the embodiments and are not intended to limit the invention. In this specification, the singular form includes the plural form unless specifically stated otherwise. As used herein, "comprises" and / or "comprising" do not exclude the presence or addition of one or more other components, steps, actions, and / or elements to the mentioned components, steps, actions, and / or elements.

[0031] In addition, the terms "connection" or "connection" may comprehensively mean physical and / or electrical connections or connections. In addition, it may comprehensively mean direct or indirect connections or connections, and integral or non-integrated connections or connections.

[0032] When elements or layers are referred to as being on another element or layer, this includes cases where another layer or element is interposed directly on or in the middle of another element. Throughout the specification, the same reference numerals refer to the same components.

[0033] Although terms such as "first," "second," etc., are used to describe various components, it goes without saying that these components are not limited by these terms. These terms are used merely to distinguish one component from another. Therefore, it goes without saying that the first component mentioned below may also be the second component within the technical scope of the present invention.

[0034] Hereinafter, embodiments of the present invention will be described in detail with reference to the attached drawings.

[0035] FIG. 1 is a plan view showing a display device according to one embodiment.

[0036] FIG. 1 illustrates a display device capable of using a light-emitting element as a light source, in particular a display panel (PNL) provided in the display device.

[0037] For convenience of explanation, the structure of the display panel (PNL) in FIG. 1 is briefly illustrated with the display area (DA) as the center. However, depending on the embodiment, at least one driving circuit part (e.g., at least one of a scanning driving part and a data driving part), wiring, and / or pads that are not illustrated may be further disposed on the display panel (PNL).

[0038] Referring to FIG. 1, a display panel (PNL) may include a substrate (SUB) and a pixel unit (PXU) disposed on the substrate (SUB). The pixel unit (PXU) may include first pixels (PXL1), second pixels (PXL2) and / or third pixels (PXL3). Hereinafter, when arbitrarily referring to at least one pixel among the first pixels (PXL1), second pixels (PXL2) and third pixels (PXL3), or when referring to two or more types of pixels collectively, it will be referred to as "pixel (PXL)" or "pixels (PXL)".

[0039] The substrate (SUB) constitutes the base member of the display panel (PNL) and may be a rigid or flexible substrate or film. For example, the substrate (SUB) may be a rigid substrate made of glass or reinforced glass, or a flexible substrate made of plastic or metal (or a thin film), and the material and / or physical properties of the substrate (SUB) are not particularly limited.

[0040] A display panel (PNL) and a substrate (SUB) for forming the same may include a display area (DA) for displaying an image and a non-display area (NDA) excluding the display area (DA). Pixels (PXL) may be disposed in the display area (DA). Various wirings, pads, and / or embedded circuits connected to the pixels (PXL) of the display area (DA) may be disposed in the non-display area (NDA). The pixels (PXL) may be arranged in a stripe or pentile pattern. TM ) They may be arranged regularly according to the arrangement structure, etc. However, the arrangement structure of the pixels (PXL) is not necessarily limited to this, and the pixels (PXL) may be arranged in the display area (DA) in various structures and / or ways.

[0041] According to an embodiment, two or more types of pixels (PXL) emitting different colors of light may be arranged in a display area (DA). For example, first pixels (PXL1) emitting a first color of light, second pixels (PXL2) emitting a second color of light, and third pixels (PXL3) emitting a third color of light may be arranged in the display area (DA). At least one first to third pixel (PXL1, PXL2, PXL3) adjacent to each other may constitute a single pixel unit (PXU) capable of emitting various colors of light. For example, the first to third pixels (PXL1, PXL2, PXL3) may each be a subpixel emitting a predetermined color of light. According to an embodiment, the first pixel (PXL1) may be a red pixel emitting red light, the second pixel (PXL2) may be a green pixel emitting green light, and the third pixel (PXL3) may be a blue pixel emitting blue light, but is not necessarily limited thereto.

[0042] In one embodiment, the first pixel (PXL1), the second pixel (PXL2), and the third pixel (PXL3) each have light-emitting elements that emit light of the same color, and by including different colored color conversion layers and / or color filters disposed on each light-emitting element, they may emit light of the first color, the second color, and the third color, respectively. In another embodiment, the first pixel (PXL1), the second pixel (PXL2), and the third pixel (PXL3) may each have a light-emitting element of the first color, a light-emitting element of the second color, and a light-emitting element of the third color as light sources, respectively, so as to emit light of the first color, the second color, and the third color, respectively. However, the color, type, and / or number of pixels (PXL) constituting the pixel unit (PXU) are not particularly limited. That is, the color of the light emitted by each pixel (PXL) can be varied.

[0043] A pixel (PXL) may include at least one light source driven by a predetermined control signal (e.g., a scan signal and a data signal) and / or a predetermined power source (e.g., a first power source and a second power source). In one embodiment, the light source may include ultra-small pillar-shaped light-emitting elements having a size small to the nanometer scale or micrometer scale. However, it is not necessarily limited thereto, and various other types of light-emitting elements may also be used as the light source of the pixel (PXL).

[0044] In one embodiment, each pixel (PXL) may be composed of an active pixel. However, the type, structure, and / or driving method of the pixels (PXL) that can be applied to the display device is not particularly limited. For example, each pixel (PXL) may be composed of a pixel of a passive or active light-emitting display device with various structures and / or driving methods.

[0045] FIG. 2 is a circuit diagram of a pixel according to one embodiment.

[0046] FIG. 2 illustrates the electrical connection relationships of components included in a pixel (PXL) that can be applied to an active display device. However, the types of components included in the pixel (PXL) are not necessarily limited to this.

[0047] According to an embodiment, the pixel (PXL) illustrated in FIG. 2 may be any one of the first pixel (PXL1), the second pixel (PXL2), and the third pixel (PXL3) provided in the display panel (PNL) of FIG. 1. The first pixel (PXL1), the second pixel (PXL2), and the third pixel (PXL3) may have substantially the same or similar structure to each other.

[0048] Referring to FIG. 2, each pixel (PXL) may include a light-emitting unit (EMU) that generates light of a luminance corresponding to a data signal. Additionally, the pixel (PXL) may further include a pixel circuit (PXC) for driving the light-emitting unit (EMU).

[0049] According to an embodiment, the light-emitting unit (EMU) may include at least one light-emitting element (LD) electrically connected between a first power line (PL1) to which the voltage of a first power source (VDD) is applied and a second power line (PL2) to which the voltage of a second power source (VSS) is applied. As an example, the light-emitting unit (EMU) may include a first electrode (ET1) connected to the first power source (VDD) via a pixel circuit (PXC) and the first power line (PL1), a second electrode (ET2) connected to the second power source (VSS) via the second power line (PL2), and a light-emitting element (LD) connected between the first electrode (ET1) and the second electrode (ET2). In one embodiment, the first electrode (ET1) may be an anode electrode and the second electrode (ET2) may be a cathode electrode.

[0050] A light-emitting element (LD) may include one end connected to a first power source (VDD) and the other end connected to a second power source (VSS). According to an embodiment, one end of the light-emitting element (LD) may be provided integrally with a first electrode (ET1) and connected to the first electrode (ET1), and the other end of the light-emitting element (LD) may be provided integrally with a second electrode (ET2) and connected to the second electrode (ET2). The first power source (VDD) and the second power source (VSS) may have different potentials. In this case, the potential difference between the first and second power sources (VDD, VSS) may be set to be greater than or equal to the threshold voltage of the light-emitting element (LD) during the light emission period of the pixel (PXL).

[0051] A light-emitting element (LD) can constitute an effective light source for an light-emitting unit (EMU). The light-emitting element (LD) can emit light with a brightness corresponding to the driving current supplied through the pixel circuit (PXC). For example, during each frame period, the pixel circuit (PXC) can supply a driving current to the light-emitting unit (EMU) that corresponds to the grayscale value of the corresponding frame data. The driving current supplied to the light-emitting unit (EMU) can flow through the light-emitting element (LD). Accordingly, the light-emitting unit (EMU) can emit light as the light-emitting element (LD) emits light with a brightness corresponding to the driving current.

[0052] A pixel circuit (PXC) may be connected to a scan line (Si) and a data line (Dj) of a pixel (PXL). For example, when a pixel (PXL) is placed in the i-th row (i is a natural number) and j-th column (j is a natural number) of a display area (DA), the pixel circuit (PXC) of the pixel (PXL) may be connected to the i-th scan line (Si) and the j-th data line (Dj) of the display area (DA). According to an embodiment, the pixel circuit (PXC) may include first and second transistors (T1, T2) and a storage capacitor (Cst). However, the structure of the pixel circuit (PXC) is not limited to the embodiment shown in FIG. 2.

[0053] The pixel circuit (PXC) may include first and second transistors (T1, T2) and a storage capacitor (Cst).

[0054] The first terminal of the first transistor (T1; driving transistor) can be connected to the first power supply (VDD), and the second terminal can be electrically connected to the light-emitting element (LD). The gate electrode of the first transistor (T1) can be connected to the first node (N1). The first transistor (T1) controls the amount of driving current supplied to the light-emitting element (LD) in response to the voltage of the first node (N1).

[0055] The first terminal of the second transistor (T2; switching transistor) can be connected to the j-th data line (Dj), and the second terminal can be connected to the first node (N1). Here, the first terminal and the second terminal of the second transistor (T2) are different terminals; for example, if the first terminal is the source electrode, the second terminal can be the drain electrode. Also, the gate electrode of the second transistor (T2) can be connected to the i-th scan line (Si).

[0056] The second transistor (T2) is turned on when a scan signal of a voltage capable of turning on the second transistor (T2) is supplied from the i-th scan line (Si), thereby electrically connecting the j-th data line (Dj) and the first node (N1). At this time, the data signal of the corresponding frame is supplied to the j-th data line (Dj), and accordingly, the data signal can be transmitted to the first node (N1). The data signal transmitted to the first node (N1) can be charged into the storage capacitor (Cst).

[0057] The storage capacitor (Cst) charges a voltage corresponding to the data signal supplied to the first node (N1) and can maintain the charged voltage until the data signal of the next frame is supplied.

[0058] FIG. 2 illustrates a pixel circuit (PXC) comprising a second transistor (T2) for transmitting a data signal into a pixel (PXL), a storage capacitor (Cst) for storing the data signal, and a first transistor (T1) for supplying a driving current corresponding to the data signal to a light-emitting element (LD). However, it is not necessarily limited thereto, and the structure of the pixel circuit (PXC) can be implemented in various ways. For example, the pixel circuit (PXC) may additionally include at least one transistor element, such as a transistor element for compensating the threshold voltage of the first transistor (T1), a transistor element for initializing a first node (N1), and / or a transistor element for controlling the light-emitting time of the light-emitting elements (LD), or other circuit elements, such as a boosting capacitor for boosting the voltage of the first node (N1). Furthermore, the first and second transistors (T1, T2) of the pixel circuit (PXC) are not limited to FIG. 2 and can be changed in various ways, such as NMOS or PMOS.

[0059] FIGS. 3 and FIGS. 4 are cross-sectional views showing a pixel according to one embodiment.

[0060] FIGS. 3 and 4 schematically illustrate the cross-sectional structure of adjacent first pixels (PXL1), second pixels (PXL2), and third pixels (PXL3).

[0061] Referring to FIGS. 3 and 4, a pixel (PXL) and a display device equipped with the same may include a substrate (SUB), bank patterns (BNP) disposed on the substrate (SUB), light-emitting elements (LD), a color conversion layer (CCL), and a color filter layer (CFL).

[0062] The substrate (SUB) may be a driving substrate including circuit elements, such as transistors that constitute the pixel circuit (PXC in FIG. 2) of each pixel (PXL). As an example, the substrate (SUB) may be a driving substrate fabricated in a wafer state. The substrate (SUB) may use a CMOS substrate composed of a combination of NMOS and PMOS, but is not necessarily limited thereto.

[0063] Bank patterns (BNP) can be placed at the boundaries of the first to third pixels (PXL1, PXL2, PXL3) on the substrate (SUB). Each bank pattern (BNP) can be provided in a shape extending in one direction. For example, each bank pattern (BNP) can be provided on the substrate (SUB) in a shape extending from the substrate (SUB) in a third direction (Z-axis direction).

[0064] Bank patterns (BNP) may include a first semiconductor layer (B1), an active layer (B2), a second semiconductor layer (B3), and a porous layer (BP). For example, the first semiconductor layer (B1), the active layer (B2), the second semiconductor layer (B3), and the porous layer (BP) of the bank patterns (BNP) may be sequentially stacked along a third direction (Z-axis direction) on a substrate (SUB).

[0065] The first semiconductor layer (B1) of the bank patterns (BNP) may, for example, include at least one p-type semiconductor layer. For example, the first semiconductor layer (B1) of the bank patterns (BNP) may include at least one semiconductor material among GaN, InGaN, InAlGaN, AlGaN, or AlN, and may include a p-type semiconductor layer doped with a first conductive dopant (or p-type dopant) such as Mg, Zn, Ca, Sr, Ba, etc. For example, the first semiconductor layer (B1) of the bank patterns (BNP) may include a GaN semiconductor material doped with a first conductive dopant (or p-type dopant), but is not necessarily limited thereto, and various other materials may also constitute the first semiconductor layer (B1) of the bank patterns (BNP).

[0066] The active layer (B2) of the bank patterns (BNP) may be disposed between the first semiconductor layer (B1) and the second semiconductor layer (B3). The active layer (B2) of the bank patterns (BNP) may include any one of a single well structure, a multi-well structure, a single quantum well structure, a multi-quantum well (MQW) structure, a quantum dot structure, or a quantum wire structure, but is not necessarily limited thereto. The active layer (B2) of the bank patterns (BNP) may include GaN, InGaN, InAlGaN, AlGaN, or AlN, and various other materials may also constitute the active layer (B2) of the bank patterns (BNP).

[0067] The second semiconductor layer (B3) of the bank patterns (BNP) is disposed on the active layer (B2) and may include a semiconductor layer of a different type from the first semiconductor layer (B1). In one embodiment, the second semiconductor layer (B3) of the bank patterns (BNP) may include at least one n-type semiconductor layer. For example, the second semiconductor layer (B3) of the bank patterns (BNP) may include any one of the semiconductor materials of GaN, InGaN, InAlGaN, AlGaN, or AlN, and may be an n-type semiconductor layer doped with a second conductive dopant (or n-type dopant) such as Si, Ge, Sn, etc. As an example, the second semiconductor layer (B3) of the bank patterns (BNP) may include a GaN semiconductor material doped with a second conductive dopant (or n-type dopant). However, the material constituting the second semiconductor layer (B3) of the bank patterns (BNP) is not limited to this, and the second semiconductor layer (B3) of the bank patterns (BNP) can be composed of various other materials.

[0068] The porous layer (BP) of the bank patterns (BNP) may be disposed on the second semiconductor layer (B3). The porous layer (BP) of the bank patterns (BNP) may include the same material as the second semiconductor layer (B3), but is not necessarily limited thereto. For example, the porous layer (BP) of the bank patterns (BNP) may include at least one n-type semiconductor layer. For example, the porous layer (BP) of the bank patterns (BNP) may include a semiconductor material such as GaN, InGaN, InAlGaN, AlGaN, or AlN, and may be an n-type semiconductor layer doped with a second conductive dopant (or n-type dopant) such as Si, Ge, Sn, etc. For example, the porous layer (BP) of the bank patterns (BNP) may include a GaN semiconductor material doped with a second conductive dopant (or n-type dopant). However, the material constituting the porous layer (BP) of the bank patterns (BNP) is not limited to this, and the porous layer (BP) of the bank patterns (BNP) can be constituting various other materials.

[0069] The porous layer (BP) of the bank patterns (BNP) may contain a plurality of pores (P). The pores (P) may be nanoscale pores (P) formed through electrochemical etching, but are not necessarily limited thereto. A detailed explanation thereof will be provided later with reference to FIG. 8.

[0070] Bank patterns (BNP) may further include mask layers (MK1, MK2) disposed on a porous layer (BP). The mask layers (MK1, MK2) may include a first mask layer (MK1) disposed on the porous layer (BP) and a second mask layer (MK2) disposed on the first mask layer (MK1). The first mask layer (MK1) and the second mask layer (MK2) may be composed of different materials. For example, the first mask layer (MK1) may include silicon oxide (SiOx) and the second mask layer (MK2) may include nickel (Ni), but is not necessarily limited thereto.

[0071] According to an embodiment, as illustrated in FIG. 4, bank patterns (BNP) may further include a semiconductor layer (B4) disposed between a porous layer (BP) and mask layers (MK1, MK2). The semiconductor layer (B4) may include semiconductor materials such as undoped GaN, InGaN, InAlGaN, AlGaN, or AlN, but is not necessarily limited thereto. The thickness of the semiconductor layer (B4) in the third direction (Z-axis direction) may be smaller than the thickness of the porous layer (BP) in the third direction (Z-axis direction), but is not necessarily limited thereto.

[0072] Light-emitting elements (LDs) can be placed in each of the first to third pixels (PXL1, PXL2, PXL3). Light-emitting elements (LDs) can be placed between bank patterns (BNP) on a substrate (SUB).

[0073] Each light-emitting element (LD) may be provided in various shapes. For example, the light-emitting element (LD) may have a rod-like shape or a bar-like shape that is long in the third direction (Z-axis direction) (i.e., the aspect ratio is greater than 1), but is not necessarily limited thereto. For example, the light-emitting element (LD) may have a column shape in which the diameter of one end and the diameter of the other end are different. Additionally, the light-emitting element (LD) may be a light-emitting diode (LED) fabricated to be ultra-small enough to have a diameter and / or length on a nanometer scale or a micrometer scale. However, it is not necessarily limited thereto, and the size of the light-emitting element (LD) may be varied to meet the requirements (or design conditions) of the lighting device or display device to which the light-emitting element (LD) is applied.

[0074] Each light-emitting element (LD) may include a light-emitting region (EA) and a porous region (PA). The light-emitting region (EA) may be provided between a substrate (SUB) and a porous region (PA).

[0075] The light-emitting region (EA) may include a first semiconductor layer (L1), a second semiconductor layer (L3), and an active layer (L2) interposed between the first and second semiconductor layers (L1, L3). For example, the first semiconductor layer (L1), the active layer (L2), and the second semiconductor layer (L3) of the light-emitting elements (LD) may be sequentially stacked along a third direction (Z-axis direction) on a substrate (SUB).

[0076] The first semiconductor layer (L1) of the light-emitting device (LD) may, for example, include at least one p-type semiconductor layer. For example, the first semiconductor layer (L1) of the light-emitting device (LD) may include a semiconductor material such as GaN, InGaN, InAlGaN, AlGaN, or AlN, and may include a p-type semiconductor layer doped with a first conductive dopant (or p-type dopant) such as Mg, Zn, Ca, Sr, or Ba. For example, the first semiconductor layer (L1) of the light-emitting device (LD) may include a GaN semiconductor material doped with a first conductive dopant (or p-type dopant), but is not necessarily limited thereto, and various other materials may also constitute the first semiconductor layer (L1) of the light-emitting device (LD).

[0077] The active layer (L2) of the light-emitting device (LD) may be disposed between the first semiconductor layer (L1) and the second semiconductor layer (L3). The active layer (L2) of the light-emitting device (LD) may include any one of a single well structure, a multi-well structure, a single quantum well structure, a multi-quantum well (MQW) structure, a quantum dot structure, or a quantum wire structure, but is not necessarily limited thereto. The active layer (L2) of the light-emitting device (LD) may include GaN, InGaN, InAlGaN, AlGaN, or AlN, and various other materials may also constitute the active layer (L2) of the light-emitting device (LD).

[0078] When a predetermined signal (or voltage) is applied to each end of the light-emitting elements (LD), electron-hole pairs combine in the active layer (L2) of the light-emitting elements (LD), causing each light-emitting element (LD) to emit light. By controlling the light emission of each light-emitting element (LD) using this principle, the light-emitting element (LD) can be used as a light source for various light-emitting devices, including pixels (PXL) of a display device.

[0079] According to an embodiment, an electron blocking layer (EBL) may be further disposed between the active layer (L2) and the first semiconductor layer (L1) of the light-emitting elements (LD). The electron blocking layer blocks the flow of electrons supplied from the second semiconductor layer (L3) to the first semiconductor layer (L1), thereby increasing the probability of electron-hole recombination within the active layer (L2). The energy bandgap of the electron blocking layer may be larger than the energy bandgap of the active layer (L2) and / or the first semiconductor layer (L1), but is not necessarily limited thereto.

[0080] According to an embodiment, a super lattice layer (SLs) may be further disposed between the active layer (L2) and the second semiconductor layer (L3) of the light-emitting devices (LD). The super lattice layer can relieve stress between the active layer (L2) and the second semiconductor layer (L3) to improve the quality of the light-emitting devices (LD). For example, the super lattice layer may be formed in a structure in which InGaN and GaN are alternately stacked, but is not necessarily limited thereto.

[0081] The second semiconductor layer (L3) of the light-emitting elements (LD) is disposed on the active layer (L2) and may include a semiconductor layer of a different type from the first semiconductor layer (L1). In one embodiment, the second semiconductor layer (L3) of the light-emitting elements (LD) may include at least one n-type semiconductor layer. For example, the second semiconductor layer (L3) of the light-emitting elements (LD) may include a semiconductor material such as GaN, InGaN, InAlGaN, AlGaN, or AlN, and may be an n-type semiconductor layer doped with a second conductive dopant (or n-type dopant) such as Si, Ge, Sn, etc. As an example, the second semiconductor layer (L3) of the light-emitting elements (LD) may include a GaN semiconductor material doped with a second conductive dopant (or n-type dopant). However, the material constituting the second semiconductor layer (L3) of the light-emitting elements (LD) is not limited to this, and the second semiconductor layer (L3) of the light-emitting elements (LD) can be constituting various other materials.

[0082] A porous region (PA) may be provided on the second semiconductor layer (L3) of the light-emitting region (EA). For example, the porous region (PA) may be formed directly on the second semiconductor layer (L3) of the light-emitting region (EA). The porous region (PA) may include the same material as the second semiconductor layer (L3), but is not necessarily limited thereto.

[0083] The porous region (PA) may include a porous layer (LP). The porous layer (LP) of the light-emitting device (LD) may include the same material as the second semiconductor layer (L3), but is not necessarily limited thereto. For example, the porous layer (LP) of the light-emitting device (LD) may include at least one n-type semiconductor layer. For example, the porous layer (LP) of the light-emitting device (LD) may include a semiconductor material such as GaN, InGaN, InAlGaN, AlGaN, or AlN, and may be an n-type semiconductor layer doped with a second conductive dopant (or n-type dopant) such as Si, Ge, Sn, etc. For example, the porous layer (LP) of the light-emitting device (LD) may include a GaN semiconductor material doped with a second conductive dopant (or n-type dopant). However, the material constituting the porous layer (LP) of the light-emitting elements (LD) is not limited to this, and the porous layer (LP) of the light-emitting elements (LD) can be composed of various other materials.

[0084] The porous region (PA) may include a plurality of pores (P) present within the porous layer (LP). The pores (P) may be nanoscale pores (P) formed through electrochemical etching, but are not necessarily limited thereto. A detailed explanation thereof will be provided later with reference to FIG. 8.

[0085] A porous region (PA) is provided on a light-emitting region (EA) to scatter light emitted from the light-emitting region (EA), thereby improving light emission efficiency. For example, the refractive index of the porous region (PA) is reduced due to a number of pores (P), which can increase light extraction efficiency. In other words, the porous region (PA) can function as a scattering layer. Thus, when the porous region (PA) is embedded in the light-emitting device (LD), a scattering layer separately provided within the pixel (PXL) can be omitted, thereby simplifying the manufacturing process and reducing costs. Additionally, the porous region (PA) is provided between the light-emitting region (EA) and the color conversion layer (CCL) described later, effectively preventing the color conversion layer (CCL) from being damaged by heat generated by the light-emitting region (EA).

[0086] In one embodiment, the light-emitting elements (LD) and the bank patterns (BNP) may comprise the same material. For example, the first semiconductor layer (L1), active layer (L2), second semiconductor layer (L3), and / or porous layer (LP) of the light-emitting elements (LD) may each comprise the same material as the first semiconductor layer (B1), active layer (B2), second semiconductor layer (B3), and / or porous layer (BP) of the bank patterns (BNP) described above. In this case, the first semiconductor layer (L1), active layer (L2), second semiconductor layer (L3), and / or porous layer (LP) of the light-emitting elements (LD) may each be formed simultaneously in the same process as the first semiconductor layer (B1), active layer (B2), second semiconductor layer (B3), and / or porous layer (BP) of the bank patterns (BNP). Accordingly, the manufacturing process of the display device can be simplified to ensure process economics. A detailed explanation of this will be provided later with reference to Fig. 12.

[0087] Light-emitting elements (LDs) may be disposed on a first electrode (ET1) provided on a substrate (SUB). For example, a first semiconductor layer (L1) of the light-emitting elements (LDs) may be disposed on the first electrode (ET1) and electrically connected to the first electrode (ET1). The first electrode (ET1) may include a metal or a metal oxide. For example, the first electrode (ET1) may include copper (Cu), gold (Au), chromium (Cr), titanium (Ti), aluminum (Al), nickel (Ni), indium tin oxide (ITO), and oxides or alloys thereof, but is not necessarily limited thereto.

[0088] According to an embodiment, connecting electrodes (CE1, CE2) may be further disposed between the substrate (SUB) and the light-emitting elements (LD) and / or bank patterns (BNP). The connecting electrodes (CE1, CE2) may include a first connecting electrode (CE1) provided between the light-emitting elements (LD) and the substrate (SUB) and a second connecting electrode (CE2) provided between the bank patterns (BNP) and the substrate (SUB).

[0089] A first connecting electrode (CE1) may be disposed between a first semiconductor layer (L1) of a light-emitting element (LD) and a first electrode (ET1) provided on a substrate (SUB). The light-emitting element (LD) may be electrically connected to the first electrode (ET1) provided on the substrate (SUB) through the first connecting electrode (CE1).

[0090] The second connecting electrode (CE2) may include the same material as the first connecting electrode (CE1). For example, the first and second connecting electrodes (CE1, CE2) may each include a metal or a metal oxide. As an example, the first and second connecting electrodes (CE1, CE2) may each include copper (Cu), gold (Au), chromium (Cr), titanium (Ti), aluminum (Al), nickel (Ni), indium tin oxide (ITO), and oxides or alloys thereof, but are not necessarily limited thereto. The second connecting electrode (CE2) may be formed simultaneously with the first connecting electrode (CE1) in the same process, but is not necessarily limited thereto.

[0091] A hard mask layer (HM) may be further disposed between the bank patterns (BNP) and the second connecting electrode (CE2). The hard mask layer (HM) may be disposed between the first semiconductor layer (B1) of the bank patterns (BNP) and the second connecting electrode (CE2). The hard mask layer (HM) may be omitted depending on the embodiment.

[0092] An insulating film (INS) may be provided on the surface of the light-emitting elements (LD) and / or bank patterns (BNP). The insulating film (INS) may be provided on the side of the light-emitting elements (LD) and / or bank patterns (BNP). The insulating film (INS) can prevent electrical short circuits that may occur when the active layer (L2) of the light-emitting elements (LD) comes into contact with a conductive material other than the first and second semiconductor layers (L1, L3). Additionally, the insulating film (INS) can improve the lifespan and luminous efficiency of the light-emitting elements (LD) by minimizing surface defects of the light-emitting elements (LD).

[0093] The insulating film (INS) can be partially removed to cover the sides of the light-emitting elements (LD) and / or bank patterns (BNP) while exposing the top surface of the light-emitting elements (LD) and / or bank patterns (BNP). For example, the insulating film (INS) can be partially removed to cover the sides of the light-emitting elements (LD) while exposing the porous region (PA) of the light-emitting elements (LD), i.e., the porous layer (LP).

[0094] The insulating film (INS) may include silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiOxNy), silicon oxycarbide (SiOxCy), aluminum oxide (AlOx), aluminum nitride (AlNx), zirconium oxide (ZrOx), hafnium oxide (HfOx), or titanium oxide (TiOx), but is not necessarily limited thereto.

[0095] A second electrode (ET2) may be disposed on the light-emitting elements (LD). The second electrode (ET2) may be disposed directly on the upper surface of the light-emitting elements (LD) exposed by an insulating film (INS). For example, the second electrode (ET2) may be disposed directly on the porous region (PA) of the light-emitting elements (LD), i.e., the porous layer (LP). The second electrode (ET2) may be disposed across the first to third pixels (PXL1, PXL2, PXL3).

[0096] The second electrode (ET2) may be composed of various transparent conductive materials. For example, the second electrode (ET2) may include at least one of various transparent conductive materials, including indium tin oxide (ITO), indium zinc oxide (IZO), indium tin zinc oxide (ITZO), aluminum zinc oxide (AZO), gallium zinc oxide (GZO), zinc tin oxide (ZTO), or gallium tin oxide (GTO), and may be implemented to be substantially transparent or translucent to satisfy a predetermined light transmittance. Accordingly, light emitted from the light-emitting elements (LD) may pass through the second electrode (ET2) and be emitted to the outside of the display panel (PNL).

[0097] A color conversion layer (CCL) may be disposed on the light-emitting elements (LD). The color conversion layer (CCL) may be disposed between bank patterns (BNP). That is, the color conversion layer (CCL) may be provided within the space or opening defined by the bank patterns (BNP).

[0098] The color conversion layer (CCL) may include quantum dots as a color conversion material that converts light emitted from light-emitting elements (LDs) of each pixel (PXL) into light of a specific color. For example, the color conversion layer (CCL) may include a plurality of quantum dots dispersed within a predetermined matrix material such as a base resin.

[0099] In one embodiment, the first to third pixels (PXL1, PXL2, PXL3) may include light-emitting elements (LDs) that emit light of the same color. For example, the first to third pixels (PXL1, PXL2, PXL3) may include light-emitting elements (LDs) that emit a third color (or, blue). The color conversion layer (CCL) may include quantum dots that convert blue light emitted from the light-emitting elements (LDs) into white light. For example, the color conversion layer (CCL) may include a first quantum dot that converts blue light emitted from the blue light-emitting elements into red light and a second quantum dot that converts blue light into green light, but is not necessarily limited thereto. When using quantum dots as a color conversion material, the absorption coefficient of the quantum dots can be increased by irradiating the quantum dots with blue light having a relatively short wavelength in the visible light region. Accordingly, the light efficiency emitted from the pixels (PXL) can be improved, and excellent color reproduction can be secured. In addition, the manufacturing efficiency of the display device can be increased by configuring the light-emitting units (EMUs) of the first to third pixels (PXL1, PXL2, PXL3) using light-emitting elements (LDs) of the same color (for example, blue light-emitting elements). However, this is not necessarily limited thereto, and the first to third pixels (PXL1, PXL2, PXL3) may be equipped with light-emitting elements (LDs) that emit light of different colors. For example, the first pixel (PXL1) may include a first color (or red) light-emitting element (LD), the second pixel (PXL2) may include a second color (or green) light-emitting element (LD), and the third pixel (PXL3) may include a third color (or blue) light-emitting element (LD).

[0100] According to an embodiment, a reflective layer (RF) may be disposed between bank patterns (BNP) and a color conversion layer (CCL). The reflective layer (RF) can reflect light emitted from light-emitting elements (LD) to improve the light emission efficiency of the display panel (PNL). Additionally, the reflective layer (RF) may be disposed on the side of the bank patterns (BNP) to prevent color mixing between adjacent pixels (PXL). The material of the reflective layer (RF) is not particularly limited and may be composed of various reflective materials.

[0101] A protective layer (PSV) may be disposed on the color conversion layer (CCL). The protective layer (PSV) may directly cover the color conversion layer (CCL). The protective layer (PSV) may be disposed across the first to third pixels (PXL1, PXL2, PXL3). The protective layer (PSV) can prevent impurities, such as moisture or air, from penetrating from the outside and damaging or contaminating the color conversion layer (CCL). One side of the protective layer (PSV) may be in contact with the color conversion layer (CCL), and the other side of the protective layer (PSV) may be in contact with the color filter layer (CFL) to be described later.

[0102] The protective layer (PSV) may include organic materials such as acrylates resin, epoxy resin, phenolic resin, polyamides resin, polyimides resin, polyesters resin, polyphenylenesulfides resin, or benzocyclobutene (BCB), but is not necessarily limited thereto.

[0103] According to an embodiment, the protective layer (PSV) may include an inorganic material such as silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiOxNy), silicon oxycarbide (SiOxCy), aluminum oxide (AlOx), aluminum nitride (AlNx), zirconium oxide (ZrOx), hafnium oxide (HfOx), or titanium oxide (TiOx).

[0104] A color filter layer (CFL) may be disposed on the protective layer (PVS). The color filter layer (CFL) may be disposed between bank patterns (BNP). The color filter layer (CFL) may include color filters (CF1, CF2, CF3) that correspond to the color of each pixel (PXL). By disposing of color filters (CF1, CF2, CF3) that correspond to the color of each of the first to third pixels (PXL1, PXL2, PXL3), a full-color image can be displayed.

[0105] The color filter layer (CFL) may include a first color filter (CF1) disposed in a first pixel (PXL1) to selectively transmit light emitted from the first pixel (PXL1), a second color filter (CF2) disposed in a second pixel (PXL2) to selectively transmit light emitted from the second pixel (PXL2), and a third color filter (CF3) disposed in a third pixel (PXL3) to selectively transmit light emitted from the third pixel (PXL3).

[0106] In one embodiment, the first color filter (CF1), the second color filter (CF2), and the third color filter (CF3) may be a red color filter, a green color filter, and a blue color filter, respectively, but are not necessarily limited thereto. Hereinafter, when referring to any of the first color filter (CF1), the second color filter (CF2), and the third color filter (CF3), or when referring to two or more types of color filters collectively, it will be referred to as "color filter (CF)" or "color filters (CF)".

[0107] The first color filter (CF1) can be superimposed in a third direction (Z-axis direction) with the light-emitting element (LD) and the color conversion layer (CCL) of the first pixel (PXL1). The first color filter (CF1) may include a color filter material that selectively transmits light of a first color (or red). For example, when the first pixel (PXL1) is a red pixel, the first color filter (CF1) may include a red color filter material.

[0108] The second color filter (CF2) can be superimposed in a third direction (Z-axis direction) with the light-emitting element (LD) and the color conversion layer (CCL) of the second pixel (PXL2). The second color filter (CF2) may include a color filter material that selectively transmits light of the second color (or green). For example, when the second pixel (PXL2) is a green pixel, the second color filter (CF2) may include a green color filter material.

[0109] The third color filter (CF3) can overlap the light-emitting element (LD) and the color conversion layer (CCL) of the third pixel (PXL3) in a third direction (Z-axis direction). The third color filter (CF3) may include a color filter material that selectively transmits light of a third color (or blue). For example, when the third pixel (PXL3) is a blue pixel, the third color filter (CF3) may include a blue color filter material.

[0110] According to the above-described embodiment, the manufacturing process of a display device can be simplified by simultaneously forming light-emitting elements (LD) and bank patterns (BNP). In addition, the porous region (PA) embedded in the light-emitting elements (LD) can scatter light emitted from the light-emitting region (EA), thereby improving light emission efficiency. Accordingly, a scattering layer separately provided within the pixel (PXL) can be omitted, thereby simplifying the manufacturing process and reducing costs. Furthermore, since the porous region (PA) is provided between the light-emitting region (EA) and the color conversion layer (CCL), the color conversion layer (CCL) can be effectively prevented from being damaged by heat generated by the light-emitting region (EA).

[0111] Other embodiments are described below. In the following embodiments, configurations identical to those already described are referred to by the same reference numerals, and redundant descriptions are omitted or simplified.

[0112] FIG. 5 is a cross-sectional view showing a pixel according to another embodiment.

[0113] Referring to FIG. 5, the color conversion layer (CCL) according to the present embodiment is distinguished from the embodiments of FIG. 1 to 4 in that it includes a first color conversion layer (CC1) disposed in a first pixel (PXL1), a second color conversion layer (CC2) disposed in a second pixel (PXL2), and a light-transmitting layer (LS) disposed in a third pixel (PXL3).

[0114] In one embodiment, the first to third pixels (PXL1, PXL2, PXL3) may include light-emitting elements (LDs) that emit light of the same color. For example, the first to third pixels (PXL1, PXL2, PXL3) may include light-emitting elements (LDs) that emit light of a third color (or blue). A full-color image can be displayed by placing a color conversion layer (CCL) containing color conversion particles on each of these first to third pixels (PXL1, PXL2, PXL3).

[0115] When the first pixel (PXL1) is a red pixel, the first color conversion layer (CC1) may include a first quantum dot that converts blue light emitted from the blue light-emitting element into red light. The first quantum dot may absorb blue light and emit red light by shifting the wavelength according to an energy transition. Meanwhile, when the first pixel (PXL1) is a pixel of a different color, the first color conversion layer (CC1) may include a first quantum dot corresponding to the color of the first pixel (PXL1).

[0116] When the second pixel (PXL2) is a green pixel, the second color conversion layer (CC2) may include a second quantum dot that converts blue light emitted from the blue light-emitting element into green light. The second quantum dot may absorb blue light and emit green light by shifting the wavelength according to an energy transition. Meanwhile, when the second pixel (PXL2) is a pixel of a different color, the second color conversion layer (CC2) may include a second quantum dot corresponding to the color of the second pixel (PXL2).

[0117] By irradiating the first quantum dot and the second quantum dot with blue light having a relatively short wavelength in the visible light region, respectively, the absorption coefficients of the first quantum dot and the second quantum dot can be increased. Accordingly, the light efficiency emitted from the first pixel (PXL1) and the second pixel (PXL2) can be improved, and excellent color reproduction can be secured. In addition, by configuring the light-emitting units (EMUs) of the first to third pixels (PXL1, PXL2, PXL3) using light-emitting elements (LDs) of the same color (for example, blue light-emitting elements), the manufacturing efficiency of the display device can be increased.

[0118] A light-transmitting layer (LS) may be provided to efficiently utilize the third color (or blue) light emitted from a light-emitting element (LD). For example, if the light-emitting element (LD) is a blue light-emitting element that emits blue light and the third pixel (PXL3) is a blue pixel, the light-transmitting layer (LS) may include light-scattering particles to efficiently utilize the light emitted from the light-emitting element (LD), but is not necessarily limited thereto. Depending on the embodiment, the light-transmitting layer (LS) may be omitted, or a transparent polymer may be provided in place of the light-transmitting layer (LS).

[0119] FIG. 6 is a cross-sectional view showing a pixel according to another embodiment.

[0120] Referring to FIG. 6, the first to third pixels (PXL1, PXL2, PXL3) according to the present embodiment each include first to third light-emitting elements (LD1, LD2, LD3), and are distinguished from the embodiments of FIG. 1 to 5 in that the color conversion layer (CCL of FIG. 3, etc.) and bank patterns (BNP of FIG. 3, etc.) are omitted.

[0121] Specifically, the light-emitting elements (LD) may include a first light-emitting element (LD1) placed in a first pixel (PXL1), a second light-emitting element (LD2) placed in a second pixel (PXL2), and a third light-emitting element (LD3) placed in a third pixel (PXL3).

[0122] The first to third light-emitting elements (LD1, LD2, LD3) may each include a light-emitting region (EA) and a porous region (PA). The light-emitting region (EA) may be provided between a substrate (SUB) and a porous region (PA).

[0123] Each of the first to third light-emitting elements (LD1, LD2, LD3) may emit light of a different color. For example, the first light-emitting element (LD1) may include a light-emitting area (EA) that emits a first color (or, red), the second light-emitting element (LD2) may include a light-emitting area (EA) that emits a second color (or, green), and the third light-emitting element (LD3) may include a light-emitting area (EA) that emits a third color (or, blue). As such, since the first to third light-emitting elements (LD1, LD2, LD3) each include a light-emitting area (EA) that emits light of a different color, a full-color image can be displayed. Accordingly, a color conversion layer and / or a color filter layer separately provided for each of the first to third pixels (PXL1, PXL2, PXL3) can be omitted, thereby simplifying the manufacturing process and reducing costs.

[0124] The light-emitting region (EA) may include a first semiconductor layer (L1), a second semiconductor layer (L3), and an active layer (L2) interposed between the first and second semiconductor layers (L1, L3). For example, the first semiconductor layer (L1), the active layer (L2), and the second semiconductor layer (L3) of each of the first to third light-emitting elements (LD1, LD2, LD3) may be sequentially stacked along a third direction (Z-axis direction) on a substrate (SUB).

[0125] Each of the first to third light-emitting elements (LD1, LD2, LD3) may include at least one p-type semiconductor layer. For example, the first semiconductor layer (L1) may include a semiconductor material such as GaN, InGaN, InAlGaN, AlGaN, AlN, AlGaAs, GaAsP, AlGaInP, or GaP, and may include a p-type semiconductor layer doped with a first conductive dopant (or p-type dopant) such as Mg, Zn, Ca, Sr, Ba, etc. As an example, the first semiconductor layer (L1) may include a GaN semiconductor material doped with a first conductive dopant (or p-type dopant), but is not necessarily limited thereto, and various other materials may also constitute the first semiconductor layer (L1).

[0126] The active layer (L2) of each of the first to third light-emitting elements (LD1, LD2, LD3) may be disposed between the first semiconductor layer (L1) and the second semiconductor layer (L3). The active layer (L2) may include any one of a single well structure, a multi-well structure, a single quantum well structure, a multi-quantum well (MQW) structure, a quantum dot structure, or a quantum wire structure, but is not necessarily limited thereto. The active layer (L2) may include GaN, InGaN, InAlGaN, AlGaN, AlN, AlGaAs, GaAsP, AlGaInP, or GaP, and various other materials may also constitute the active layer (L2).

[0127] When a predetermined signal (or voltage) is applied to each end of the first to third light-emitting elements (LD1, LD2, LD3), electron-hole pairs combine in the active layer (L2) of each of the first to third light-emitting elements (LD1, LD2, LD3), causing the light-emitting element (LD) to emit light. By controlling the light emission of each light-emitting element (LD) using this principle, the light-emitting element (LD) can be used as a light source for various light-emitting devices, including pixels (PXL) of a display device.

[0128] According to an embodiment, an electron blocking layer (EBL) may be further disposed between the active layer (L2) and the first semiconductor layer (L1). The electron blocking layer blocks the flow of electrons supplied from the second semiconductor layer (L3) to the first semiconductor layer (L1), thereby increasing the probability of electron-hole recombination within the active layer (L2). The energy bandgap of the electron blocking layer may be larger than the energy bandgap of the active layer (L2) and / or the first semiconductor layer (L1), but is not necessarily limited thereto.

[0129] According to an embodiment, a super lattice layer (SLs) may be further disposed between the active layer (L2) and the second semiconductor layer (L3). The super lattice layer can relieve stress on the active layer (L2) and the second semiconductor layer (L3) to improve the quality of the light-emitting devices (LD). The super lattice layer may be formed in a structure in which InGaN and GaN are alternately stacked, but is not necessarily limited thereto.

[0130] The second semiconductor layer (L3) of each of the first to third light-emitting elements (LD1, LD2, LD3) is disposed on the active layer (L2) and may include a semiconductor layer of a different type from the first semiconductor layer (L1). In one embodiment, the second semiconductor layer (L3) may include at least one n-type semiconductor layer. For example, the second semiconductor layer (L3) may include a semiconductor material such as GaN, InGaN, InAlGaN, AlGaN, AlN, AlGaAs, GaAsP, AlGaInP, or GaP, and may be an n-type semiconductor layer doped with a second conductive dopant (or n-type dopant) such as Si, Ge, Sn, etc. As an example, the second semiconductor layer (L3) may include a GaN semiconductor material doped with a second conductive dopant (or n-type dopant). However, the material constituting the second semiconductor layer (L3) is not limited to this, and the second semiconductor layer (L3) of the light-emitting device (LD) can be composed of various other materials.

[0131] A porous region (PA) of each of the first to third light-emitting elements (LD1, LD2, LD3) may be provided on the second semiconductor layer (L3) of the light-emitting region (EA). For example, the porous region (PA) may be formed directly on the second semiconductor layer (L3) of the light-emitting region (EA). The porous region (PA) may include the same material as the second semiconductor layer (L3), but is not necessarily limited thereto.

[0132] The porous region (PA) may include a porous layer (LP) and a plurality of pores (P) present within the porous layer (LP). The porous region (PA) is provided on the light-emitting region (EA) to scatter light emitted from the light-emitting region (EA), thereby improving light emission efficiency. For example, the refractive index of the porous region (PA) may be reduced due to the plurality of pores (P), thereby increasing light extraction efficiency. That is, the porous region (PA) can function as a scattering layer. As previously explained, when the porous region (PA) is embedded in the light-emitting device (LD), the scattering layer separately provided within the pixel (PXL) can be omitted, thereby simplifying the manufacturing process and reducing costs. Furthermore, the porous region (PA), the porous layer (LP), and the pores (P) have been described in detail with reference to FIG. 3, etc., so redundant details are omitted.

[0133] The first to third light-emitting elements (LD1, LD2, LD3) may each be placed on a first electrode (ET1) provided on a substrate (SUB). For example, the first semiconductor layer (L1) of the light-emitting elements (LD) may be placed on the first electrode (ET1) and electrically connected to the first electrode (ET1).

[0134] According to an embodiment, a connecting electrode (CE) may be further disposed between the substrate (SUB) and the light-emitting elements (LD). The connecting electrode (CE) may be disposed between the first semiconductor layer (L1) of the light-emitting elements (LD) and the first electrode (ET1) provided on the substrate (SUB). The light-emitting elements (LD) may be electrically connected to the first electrode (ET1) provided on the substrate (SUB) through the connecting electrode (CE). The connecting electrode (CE) may include a metal or a metal oxide. As an example, the connecting electrode (CE) may include copper (Cu), gold (Au), chromium (Cr), titanium (Ti), aluminum (Al), nickel (Ni), indium tin oxide (ITO), and oxides or alloys thereof, but is not necessarily limited thereto.

[0135] An insulating film (INS) and a reflective layer (RF) may be disposed between the first to third light-emitting elements (LD1, LD2, LD3). The insulating film (INS) may be provided between the light-emitting elements (LD) and the reflective layer (RF).

[0136] An insulating film (INS) may be provided on the surface of the light-emitting elements (LD). An insulating film (INS) may be provided on the side of the light-emitting elements (LD). The insulating film (INS) can prevent electrical short circuits that may occur when the active layer (L2) of the light-emitting elements (LD) comes into contact with a conductive material other than the first and second semiconductor layers (L1, L3). Additionally, the insulating film (INS) can improve the lifespan and luminous efficiency of the light-emitting elements (LD) by minimizing surface defects of the light-emitting elements (LD).

[0137] The insulating film (INS) can be partially removed to cover the sides of the light-emitting elements (LD) but expose the top surface of the light-emitting elements (LD). For example, the insulating film (INS) can be partially removed to cover the sides of the light-emitting elements (LD) but expose one side of the porous region (PA) of the light-emitting elements (LD).

[0138] A reflective layer (RF) can be placed between light-emitting elements (LD). A reflective layer (RF) can be placed at the boundaries of the first to third pixels (PXL1, PXL2, PXL3) on a substrate (SUB). The reflective layer (RF) can be placed between the light-emitting elements (LD) to reflect light emitted from the light-emitting elements (LD) and improve the light emission efficiency of the display panel (PNL). Additionally, the reflective layer (RF) can be placed at the boundaries of the first to third pixels (PXL1, PXL2, PXL3) to prevent color mixing between adjacent pixels (PXL).

[0139] A second electrode (ET2) may be disposed on each of the first to third light-emitting elements (LD1, LD2, LD3). The second electrode (ET2) may be disposed directly on the upper surface of the light-emitting elements (LD) exposed by an insulating film (INS). For example, the second electrode (ET2) may be disposed directly on the porous region (PA) of the light-emitting elements (LD), i.e., the porous layer (LP). The second electrode (ET2) may be disposed on each of the first to third pixels (PXL1, PXL2, PXL3).

[0140] According to the above-described embodiment, since the first to third light-emitting elements (LD1, LD2, LD3) each include a light-emitting region (EA) that emits light of a different color, a separately provided color conversion layer and / or color filter layer can be omitted, thereby simplifying the manufacturing process and reducing costs. In addition, as previously explained, a porous region (PA) is embedded in the light-emitting elements (LD) to improve the light-emitting efficiency of the display panel (PNL) and simultaneously simplify the manufacturing process.

[0141] Next, a method for manufacturing a display device according to the above-described embodiment will be described.

[0142] FIGS. 7 to 16 are cross-sectional views of process steps of a method for manufacturing a display device according to one embodiment. FIGS. 7 to 16 are cross-sectional views for explaining the method for manufacturing a display device of FIG. 3, wherein components substantially identical to those in FIG. 3 are indicated by the same reference numerals and detailed reference numerals are omitted.

[0143] Referring to FIG. 7, a base layer (BSL) is first prepared, and a semiconductor layer (PL') is formed on the base layer (BSL). The base layer (BSL) may use a sapphire substrate, a silicon (Si) substrate, or a silicon carbide (SiC) substrate, but is not necessarily limited thereto, and may use a single-crystal substrate having a lattice structure. The base layer (BSL) may further include a buffer layer formed on one side.

[0144] The semiconductor layer (PL') may include at least one n-type semiconductor layer. For example, the semiconductor layer (PL') may include a semiconductor material such as GaN, InGaN, InAlGaN, AlGaN, or AlN, and may be an n-type semiconductor layer doped with a second conductive dopant (or n-type dopant) such as Si, Ge, or Sn. As an example, the semiconductor layer (PL') may include a GaN semiconductor material doped with a second conductive dopant (or n-type dopant). However, the material constituting the semiconductor layer (PL') is not limited to this, and the semiconductor layer (PL') may be composed of various other materials.

[0145] Referring to FIG. 8, the semiconductor layer (PL') is then etched to form a porous layer (PL). For example, the semiconductor layer (PL') can be electrochemically etched to form nanoscale pores (P) of the porous layer (PL). During the process of electrochemically etching the semiconductor layer (PL'), the size, shape, and distribution of the pores (P) can be varied depending on the etchant, voltage, and / or doping concentration.

[0146] Referring to FIG. 9, a light-emitting laminate (11, 12, 13) is subsequently formed on a porous layer (PL). The light-emitting laminate (11, 12, 13) can be formed by growing a seed crystal by an epitaxial method. In this case, the stress of the light-emitting laminate (11, 12, 13) can be relieved by the porous structure of the porous layer (PL), thereby improving the quality of the light-emitting elements (LD).

[0147] According to the embodiment, the light-emitting laminate (11, 12, 13) may be formed by metal organic chemical vapor deposition (MOCVD). However, it is not necessarily limited thereto, and the light-emitting laminate (11, 12, 13) may be formed by various methods such as electron beam deposition, physical vapor deposition (PVD), chemical vapor deposition (CVD), plasma laser deposition (PLD), dual-type thermal evaporation, sputtering, or metal organic chemical vapor deposition (MOCVD).

[0148] The light-emitting laminate (11, 12, 13) may include an epitaxially grown first semiconductor layer (11), an active layer (12), and a second semiconductor layer (13).

[0149] The second semiconductor layer (13) is provided on the porous layer (PL) and may be formed of the same material as the porous layer (PL). For example, the second semiconductor layer (13) may include at least one n-type semiconductor layer. For example, the second semiconductor layer (13) may include any one of the semiconductor materials of GaN, InGaN, InAlGaN, AlGaN, or AlN, and may be an n-type semiconductor layer doped with a second conductive dopant (or n-type dopant) such as Si, Ge, Sn, etc. As an example, the second semiconductor layer (13) may include a GaN semiconductor material doped with a second conductive dopant (or n-type dopant). However, the material constituting the second semiconductor layer (13) is not limited thereto, and the second semiconductor layer (13) may be composed of various other materials. The second semiconductor layer (13) may be formed directly on the porous layer (PL), but is not necessarily limited thereto.

[0150] The active layer (12) is provided on the second semiconductor layer (13) and may include any one of a single well structure, a multi-well structure, a single quantum well structure, a multi-quantum well (MQW) structure, a quantum dot structure, or a quantum wire structure, but is not necessarily limited thereto. The active layer (12) may include GaN, InGaN, InAlGaN, AlGaN, or AlN, and various other materials may also constitute the active layer (12) of the bank patterns active layer (12).

[0151] The first semiconductor layer (11) is provided on the active layer (12) and may include at least one p-type semiconductor layer. For example, the first semiconductor layer (11) may include a semiconductor material such as GaN, InGaN, InAlGaN, AlGaN, or AlN, and may include a p-type semiconductor layer doped with a first conductive dopant (or p-type dopant) such as Mg, Zn, Ca, Sr, Ba, etc. As an example, the first semiconductor layer (11) may include a GaN semiconductor material doped with a first conductive dopant (or p-type dopant), but is not necessarily limited thereto, and various other materials may also constitute the first semiconductor layer (11).

[0152] Referring to FIG. 10, the light-emitting laminate (11, 12, 13) and the porous layer (PL) are then combined with a substrate (SUB). The substrate (SUB) is a driving substrate including circuit elements such as transistors constituting the pixel circuit (PXC in FIG. 2) of each pixel (PXL), and may be provided with a first electrode (ET1), a connecting electrode layer (CEL), and / or a hard mask layer (HM).

[0153] The first electrode (ET1) may be formed at a location where the light-emitting elements (LD) described later are to be provided. The connecting electrode layer (CEL) may be formed across the entire surface of the substrate (SUB), but is not necessarily limited thereto. The hard mask layer (HM) may be formed at a location where the bank patterns (BNP) are to be provided so as to form the bottom of the bank patterns (BNP) described later. However, it is not necessarily limited thereto, and the hard mask layer (HM) may be omitted depending on the embodiment.

[0154] The first semiconductor layer (11) of the light-emitting laminate (11, 12, 13) can be coupled with a first electrode (ET1) formed on a substrate (SUB). The first semiconductor layer (11) can be easily bonded with the first electrode (ET1) provided on the substrate (SUB) through a connecting electrode layer (CEL). The connecting electrode layer (CEL) can be formed of a metal or a metal oxide.

[0155] After combining the light-emitting laminate (11, 12, 13) and the porous layer (PL) with the substrate (SUB), the base layer (BSL) can be separated from one side of the porous layer (PL).

[0156] Referring to FIG. 11, first and second mask layers (MK1, MK2) are subsequently formed on the light-emitting laminate (11, 12, 13) and the porous layer (PL). The first and second mask layers (MK1, MK2) may be formed directly on the porous layer (PL), but are not necessarily limited thereto.

[0157] The first mask layer (MK1) may be partially formed at the location where the light-emitting elements (LD) and bank patterns (BNP) to be described later are to be provided. The second mask layer (MK2) may be formed on the first mask layer (MK1). The second mask layer (MK2) may be optionally formed at the location where the bank patterns (BNP) are to be provided.

[0158] The first mask layer (MK1) and the second mask layer (MK2) may be composed of different materials. For example, the first mask layer (MK1) may include silicon oxide (SiOx) and the second mask layer (MK2) may include nickel (Ni), but is not necessarily limited thereto.

[0159] Referring to FIG. 12, the light-emitting laminate (11, 12, 13) and the porous layer (PL) are then patterned to form light-emitting elements (LD) and bank patterns (BNP). The bank patterns (BNP) may be formed at the boundaries of the first to third pixels (PXL1, PXL2, PXL3). The light-emitting elements (LD) may be formed within the first to third pixels (PXL1, PXL2, PXL3), respectively, between the bank patterns (BNP).

[0160] In the process of patterning the light-emitting laminate (11, 12, 13) and the porous layer (PL), the first semiconductor layer (11) may be separated into the first semiconductor layer (L1) of the light-emitting elements (LD) and the first semiconductor layer (B1) of the bank patterns (BNP), the active layer (12) may be separated into the active layer (L2) of the light-emitting elements (LD) and the active layer (B2) of the bank patterns (BNP), and the second semiconductor layer (13) may be separated into the second semiconductor layer (L3) of the light-emitting elements (LD) and the second semiconductor layer (B3) of the bank patterns (BNP). Similarly, the porous layer (PL) may be separated into the porous layer (LP) of the light-emitting elements (LD) and the porous layer (BP) of the bank patterns (BNP). The porous layer (LP) of the light-emitting elements (LD) may constitute the porous region (PA) of the light-emitting elements (LD). The first semiconductor layer (L1), active layer (L2), and second semiconductor layer (L3) of the light-emitting elements (LD) can form a light-emitting region (EA) of the light-emitting elements (LD).

[0161] In the process of patterning the light-emitting laminate (11, 12, 13) and the porous layer (PL), the difference in etching selectivity between the first mask layer (MK1) and the second mask layer (MK2) can be used to simultaneously form light-emitting elements (LD) and bank patterns (BNP) having different thicknesses.

[0162] According to an embodiment, during the process of patterning the light-emitting laminate (11, 12, 13) and the porous layer (PL), the connecting electrode layer (CEL) may be separated into a first connecting electrode (CE1) and a second connecting electrode (CE2). For example, the connecting electrode layer (CEL) may be separated into a first connecting electrode (CE1) below the light-emitting elements (LD) and a second connecting electrode (CE2) below the hard mask layer (HM).

[0163] Referring to FIG. 13, an insulating film (INS) is subsequently formed on the light-emitting elements (LD) and / or bank patterns (BNP). The insulating film (INS) may be partially formed on the side of the light-emitting elements (LD) and / or bank patterns (BNP). After the insulating film (INS) is formed across the first to third pixels (PXL1, PXL2, PXL3), it may be partially removed so that the upper surface of the light-emitting elements (LD) and / or bank patterns (BNP) is exposed. In one embodiment, when the light-emitting elements (LD) and / or bank patterns (BNP) are formed in a third direction (Z-axis direction), i.e., perpendicular to the substrate (SUB), the insulating film (INS) provided on the upper surface of the light-emitting elements (LD) and / or bank patterns (BNP) can be etched without a separate mask during the etching of the insulating film (INS).

[0164] Referring to FIG. 14, a second electrode (ET2) is subsequently formed on the light-emitting elements (LD). The second electrode (ET2) is formed directly on the upper surface of the light-emitting elements (LD) exposed by the insulating film (INS) so as to be in contact with the porous layer (LP) of the light-emitting elements (LD).

[0165] The second electrode (ET2) may be formed across the first to third pixels (PXL1, PXL2, PXL3). That is, the second electrode (ET2) may be formed to cover at least partially the bank patterns (BNP), but is not necessarily limited thereto.

[0166] The second electrode (ET2) can be formed from various transparent conductive materials. For example, the second electrode (ET2) is formed from at least one of various transparent conductive materials including indium tin oxide (ITO), indium zinc oxide (IZO), indium tin zinc oxide (ITZO), aluminum zinc oxide (AZO), gallium zinc oxide (GZO), zinc tin oxide (ZTO), or gallium tin oxide (GTO), and can be implemented to be substantially transparent or translucent to satisfy a predetermined light transmittance. Accordingly, light emitted from the light-emitting elements (LD) can pass through the second electrode (ET2) and be emitted to the outside of the display panel (PNL).

[0167] Referring to FIG. 15, a reflective layer (RF) is subsequently formed on bank patterns (BNP). The reflective layer (RF) may be partially formed on the side of the bank patterns (BNP). The reflective layer (RF) can reflect light emitted from light-emitting elements (LD) to improve the light emission efficiency of the display panel (PNL). Additionally, the reflective layer (RF) is placed on the side of the bank patterns (BNP) to prevent color mixing between adjacent pixels (PXL). The material of the reflective layer (RF) is not particularly limited and can be formed from various reflective materials.

[0168] Referring to FIG. 16, a color conversion layer (CCL) is subsequently formed on the light-emitting elements (LD). The color conversion layer (CCL) may be formed between bank patterns (BNP). That is, the color conversion layer (CCL) may be formed within the space or opening defined by the bank patterns (BNP). The color conversion layer (CCL) may include quantum dots as a color conversion material that converts light emitted from the light-emitting elements (LD) of each pixel (PXL) into light of a specific color. Since the color conversion layer (CCL) has been described in detail with reference to FIG. 3 and others, redundant details are omitted.

[0169] Next, a protective layer (PSV1) and a color filter layer (CFL) are formed on the color conversion layer (CCL) to complete the display device of FIG. 3. The protective layer (PSV) can be formed across the first to third pixels (PXL1, PXL2, PXL3). The protective layer (PSV) can directly cover the color conversion layer (CCL). The protective layer (PSV) can prevent impurities such as moisture or air from penetrating from the outside and damaging or contaminating the color conversion layer (CCL).

[0170] The color filter layer (CFL) may include color filters (CF1, CF2, CF3) corresponding to the color of each pixel (PXL). Since the color filter layer (CFL) has been described in detail with reference to FIG. 3 and others, redundant details are omitted.

[0171] According to the above-described embodiment, the manufacturing process of a display device can be simplified by simultaneously forming light-emitting elements (LD) and bank patterns (BNP). In addition, as previously explained, porous regions (PA) are embedded in the light-emitting elements (LD) to improve the light emission efficiency of the display panel (PNL) and simultaneously simplify the manufacturing process.

[0172] Other embodiments are described below. In the following embodiments, configurations identical to those already described are referred to by the same reference numerals, and redundant descriptions are omitted or simplified.

[0173] FIGS. 17 to 26 are cross-sectional views of process steps of a method for manufacturing a display device according to another embodiment. FIGS. 17 to 26 are cross-sectional views for explaining the method for manufacturing a display device of FIG. 6, wherein components substantially identical to those in FIG. 6 are indicated by the same reference numerals and detailed reference numerals are omitted.

[0174] Referring to FIG. 17, a base layer (BSL) is prepared first, and a semiconductor layer (PL') is formed on the base layer (BSL). Since the base layer (BSL) and the semiconductor layer (PL') have been described in detail with reference to FIG. 7, redundant details are omitted.

[0175] Referring to FIG. 18, the semiconductor layer (PL') is then patterned to form the semiconductor layer (PL') on each of the first to third pixels (PXL1, PXL2, PXL3). The semiconductor layer (PL') of each of the first to third pixels (PXL1, PXL2, PXL3) can be formed at a location where the light-emitting elements (LD) described later will be provided.

[0176] Referring to FIG. 19, the semiconductor layer (PL') of each of the first to third pixels (PXL1, PXL2, PXL3) is then at least partially etched to form a porous layer (LP). For example, the semiconductor layer (PL') can be electrochemically etched to form nanoscale pores (P) of the porous layer (PL). During the process of electrochemically etching the semiconductor layer (PL'), the size, shape, and distribution of the pores (P) can be varied depending on the etchant, voltage, and / or doping concentration. The porous layer (LP) of each of the first to third pixels (PXL1, PXL2, PXL3) can constitute a porous region (PA) of each of the first to third light-emitting elements (LD1, LD2, LD3) to be described later. The unetched region in the semiconductor layer (PL') can form the second semiconductor layer (L3) and together with the first semiconductor layer (L1) and the active layer (L2) formed in a subsequent process, the light-emitting region (EA) of each of the first to third light-emitting elements (LD1, LD2, LD3).

[0177] Referring to FIG. 20, a first semiconductor layer (L1) and an active layer (L2) are subsequently formed on the porous layer (LP) and the second semiconductor layer (L3) of each of the first to third pixels (PXL1, PXL2, PXL3). The first semiconductor layer (L1) and / or the active layer (L2) of each of the first to third pixels (PXL1, PXL2, PXL3) may be formed by growing a seed crystal by an epitaxial method.

[0178] The first semiconductor layer (L1), active layer (L2), and second semiconductor layer (L3) provided on the porous layer (LP) of each of the first to third pixels (PXL1, PXL2, PXL3) are light-emitting laminates and can form light-emitting regions (EA) of each of the first to third pixels (PXL1, PXL2, PXL3). As described above, the light-emitting regions (EA) of each of the first to third light-emitting elements (LD1, LD2, LD3) can be formed to emit light of different colors. For example, the light-emitting region (EA) of the first light-emitting element (LD1) can emit a first color (or red), the light-emitting region (EA) of the second light-emitting element (LD2) can emit a second color (or green), and the light-emitting region (EA) of the third light-emitting element (LD3) can emit a third color (or blue). As such, since the first to third light-emitting elements (LD1, LD2, LD3) each include a light-emitting region (EA) that emits light of a different color, a full-color image can be displayed. Accordingly, as previously explained, the color conversion layer and / or color filter layer separately provided for each of the first to third pixels (PXL1, PXL2, PXL3) can be omitted, thereby simplifying the manufacturing process and reducing costs.

[0179] Referring to FIG. 21, a flattening layer (PN) is subsequently formed between the first to third light-emitting elements (LD1, LD2, LD3). The flattening layer (PN) may be formed at the boundaries of the first to third pixels (PXL1, PXL2, PXL3). The flattening layer (PN) may be formed between the light-emitting elements (LD) to flatten the step difference of the light-emitting elements (LD). The flattening layer (PN) may be formed on the side of the light-emitting elements (LD). That is, the flattening layer (PN) may cover the side of the light-emitting elements (LD) while exposing the top surface of the light-emitting elements (LD).

[0180] In one embodiment, the planarization layer (PN) may be formed from organic materials such as acrylates resin, epoxy resin, phenolic resin, polyamides resin, polyimides resin, polyesters resin, polyphenylenesulfides resin, or benzocyclobutene (BCB), but is not necessarily limited thereto.

[0181] According to an embodiment, the planarization layer (PN) may be formed of an inorganic material such as silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiOxNy), silicon oxycarbide (SiOxCy), aluminum oxide (AlOx), aluminum nitride (AlNx), zirconium oxide (ZrOx), hafnium oxide (HfOx), or titanium oxide (TiOx).

[0182] Referring to FIG. 22, a connecting electrode (CE) is subsequently formed on the first to third light-emitting elements (LD1, LD2, LD3) and the planarization layer (PN). The connecting electrode (CE) may be formed across the first to third pixels (PXL1, PXL2, PXL3). The connecting electrode (CE) may be formed of a metal or a metal oxide. For example, the connecting electrode (CE) may be formed of copper (Cu), gold (Au), chromium (Cr), titanium (Ti), aluminum (Al), nickel (Ni), indium tin oxide (ITO), and oxides or alloys thereof, but is not necessarily limited thereto.

[0183] Referring to FIG. 23, the first to third light-emitting elements (LD1, LD2, LD3) and the substrate (SUB) are then combined. The substrate (SUB) is a driving substrate including circuit elements such as transistors that constitute the pixel circuit (PXC in FIG. 2) of each pixel (PXL), and may be provided with a first electrode (ET1).

[0184] The first semiconductor layer (L1) of each of the first to third light-emitting elements (LD1, LD2, LD3) can be coupled with a first electrode (ET1) formed on a substrate (SUB). The first semiconductor layer (L1) can be easily coupled with the first electrode (ET1) provided on the substrate (SUB) through a connecting electrode (CE). After coupling the first to third light-emitting elements (LD1, LD2, LD3) with the substrate (SUB), the base layer (BSL) can be separated from one side of the porous layer (LP).

[0185] Referring to FIG. 24, a second electrode layer (ET2') is subsequently formed on the first to third light-emitting elements (LD1, LD2, LD3). The second electrode layer (ET2') is formed directly on the upper surface of the light-emitting elements (LD) exposed by the planarization layer (PN) so as to be in contact with the porous region (PA) of the light-emitting elements (LD), i.e., the porous layer (LP). The second electrode layer (ET2') can be formed across the first to third pixels (PXL1, PXL2, PXL3).

[0186] The second electrode layer (ET2') can be formed from various transparent conductive materials. For example, the second electrode layer (ET2') is formed from at least one of various transparent conductive materials including indium tin oxide (ITO), indium zinc oxide (IZO), indium tin zinc oxide (ITZO), aluminum zinc oxide (AZO), gallium zinc oxide (GZO), zinc tin oxide (ZTO), or gallium tin oxide (GTO), and can be implemented to be substantially transparent or translucent to satisfy a predetermined light transmittance.

[0187] Referring to FIG. 25, the second electrode layer (ET2') is then patterned to form the second electrode (ET2) on each of the first to third light-emitting elements (LD1, LD2, LD3), and the planarization layer (PN) is removed.

[0188] Referring to FIG. 26, an insulating film (INS) is subsequently formed on the first to third light-emitting elements (LD1, LD2, LD3). The insulating film (INS) may be partially formed on the sides of the light-emitting elements (LD) and / or bank patterns (BNP). After being formed across the first to third pixels (PXL1, PXL2, PXL3), the insulating film (INS) may be partially removed so that the upper surface of the light-emitting elements (LD) is exposed. In one embodiment, when the light-emitting elements (LD) are formed in a third direction (Z-axis direction), i.e., perpendicular to the substrate (SUB), the insulating film (INS) provided on the upper surface of the light-emitting elements (LD) can be etched without a separate mask during the etching of the insulating film (INS).

[0189] Subsequently, a reflective layer (RF) is formed between the first to third light-emitting elements (LD1, LD2, LD3) to complete the display device of FIG. 6. The reflective layer (RF) can reflect light emitted from the light-emitting elements (LD) to improve the light emission efficiency of the display panel (PNL). In addition, the reflective layer (RF) is placed at the boundary of the first to third pixels (PXL1, PXL2, PXL3) to prevent color mixing between adjacent pixels (PXL). The material of the reflective layer (RF) is not particularly limited and can be formed from various reflective materials.

[0190] According to the above-described embodiment, since the first to third light-emitting elements (LD1, LD2, LD3) each include a light-emitting region (EA) that emits light of a different color, a separately provided color conversion layer and / or color filter layer can be omitted, thereby simplifying the manufacturing process and reducing costs. In addition, as previously explained, a porous region (PA) is embedded in the light-emitting elements (LD) to improve the light-emitting efficiency of the display panel (PNL) and simultaneously simplify the manufacturing process.

[0191] Below, an electronic device to which the display device of the above-described embodiments can be applied is described.

[0192] FIGS. 27 to 30 are exemplary drawings illustrating electronic devices according to various embodiments.

[0193] Referring to FIG. 27, a display device according to the embodiments described above can be applied to smart glasses. The smart glasses may include a frame (111) and a lens portion (112). The smart glasses are a wearable electronic device that can be worn on a user's face, and may have a structure in which a part of the frame (111) is folded or unfolded. For example, the smart glasses may be a wearable device for augmented reality (AR).

[0194] The frame (111) may include a housing (111b) that supports the lens portion (112) and a leg portion (111a) for wearing by a user. The leg portion (111a) may be connected to the housing (111b) by a hinge and may be folded or unfolded.

[0195] The frame (111) may have a battery, a touchpad, a microphone, and / or a camera built in. Additionally, the frame (111) may have a projector that outputs light and / or a processor that controls light signals built in.

[0196] The lens portion (112) may be an optical member that transmits or reflects light. The lens portion (112) may include glass and / or a transparent synthetic resin, etc.

[0197] The display device according to the embodiments described above can be applied to the lens unit (112). For example, a user can recognize an image displayed by a light signal transmitted from a projector of a frame (111) through the lens unit (112). For example, the user can recognize information such as time and date displayed on the lens unit (112).

[0198] Referring to FIG. 28, a display device according to the embodiments described above can be applied to a head-mounted display (HMD). The head-mounted display may include a head-mounting band (121) and a display storage case (122). For example, the head-mounted display may be a wearable electronic device that can be worn on a user's head.

[0199] The head mounting band (121) is connected to the display storage case (122) to secure the display storage case (122). As shown in FIG. 28, the head mounting band (121) includes a horizontal band and a vertical band to secure the head-mounted display to the user's head, wherein the horizontal band may surround the side of the user's head and the vertical band may surround the top of the user's head. However, it is not necessarily limited thereto, and the head mounting band (121) may be implemented in the form of eyeglass frames or a helmet.

[0200] The display storage case (122) houses a display device and may include at least one lens. At least one lens may provide an image to a user. For example, the display device according to the embodiments described above may be applied to a left eye lens and a right eye lens implemented in the display storage case (122).

[0201] Referring to FIG. 29, a display device according to the embodiments described above may be applied to a smart watch. The smart watch may include a display unit (131) and a strap unit (132). The smart watch is a wearable electronic device, and the strap unit (132) may be mounted on a user's wrist. A display device according to the embodiments described above may be applied to the display unit (131). For example, the display unit (131) may provide image data including information such as time and date.

[0202] Referring to FIG. 30, the display device according to the embodiments described above can be applied to an automotive display. For example, the automotive display may refer to an electronic device that is provided inside and outside a vehicle and provides image data.

[0203] For example, the display device according to the embodiments described above may be applied to at least one of an infotainment panel (141), a cluster (142), a co-driver display (143), a head-up display (144), a side mirror display (145), and a rear seat display (146) provided in a vehicle.

[0204] Those skilled in the art related to the embodiments will understand that the above-described embodiments may be implemented in modified forms without departing from the essential characteristics of the description. Therefore, the disclosed methods should be considered in an illustrative rather than a restrictive sense. The scope of the invention is defined by the claims, not by the foregoing description, and all variations within the equivalent scope should be interpreted as being included in the invention. Explanation of the symbols

[0205] SUB: Substrate LD: Light-emitting element L1: First semiconductor layer L2: Active layer L3: Second semiconductor layer LP: Porous layer

Claims

Claim 1 A display device comprising: light-emitting elements disposed on a substrate; bank patterns disposed on the substrate and containing the same material as the light-emitting elements; and a color conversion layer disposed on the light-emitting elements, wherein each of the light-emitting elements comprises: a first semiconductor layer; an active layer disposed on the first semiconductor layer; a second semiconductor layer disposed on the active layer; and a porous layer disposed on the second semiconductor layer, wherein each of the light-emitting elements and the color conversion layer are disposed between the bank patterns adjacent in a horizontal direction intersecting the thickness direction of the substrate. Claim 2 In claim 1, the porous layer is a display device comprising nanoscale pores. Claim 3 A display device according to claim 1, wherein the porous layer comprises the same material as the second semiconductor layer. Claim 4 delete Claim 5 delete Claim 6 delete Claim 7 A display device according to claim 1, further comprising a reflective layer disposed between the light-emitting elements. Claim 8 A display device according to claim 7, further comprising an insulating layer disposed between the light-emitting elements and the reflective layer. Claim 9 A display device according to claim 1, wherein the light-emitting elements include a first light-emitting element emitting a first color; a second light-emitting element emitting a second color; and a third light-emitting element emitting a third color. Claim 10 A method for manufacturing a display device comprising: a step of forming a semiconductor layer; a step of forming a porous layer by at least partially etching the semiconductor layer; a step of providing a light-emitting laminate on the porous layer; and a step of forming light-emitting elements and bank patterns by etching the porous layer and the light-emitting laminate. Claim 11 A method for manufacturing a display device according to claim 10, wherein nanoscale voids are formed in the step of etching the semiconductor layer. Claim 12 delete Claim 13 A method for manufacturing a display device according to claim 10, wherein the light-emitting laminate comprises: a first semiconductor layer; a second semiconductor layer formed on the first semiconductor layer; and an active layer formed between the first semiconductor layer and the second semiconductor layer. Claim 14 A method for manufacturing a display device according to claim 13, wherein the second semiconductor layer is formed of the same material as the porous layer. Claim 15 delete Claim 16 In claim 10, the bank patterns are formed simultaneously with the light-emitting elements in a method for manufacturing a display device. Claim 17 A method for manufacturing a display device according to claim 10, wherein the semiconductor layer comprises a second semiconductor layer provided between the porous layer and the light-emitting laminate. Claim 18 A method for manufacturing a display device according to claim 17, wherein the step of providing the light-emitting laminate comprises: providing an active layer on the second semiconductor layer; and providing a first semiconductor layer on the active layer. Claim 19 A method for manufacturing a display device according to claim 10, further comprising the step of forming a planarization layer between the light-emitting elements. Claim 20 A method for manufacturing a display device according to claim 10, further comprising the step of forming a reflective layer between the light-emitting elements.

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