Group III nitride transistor having a back barrier structure and an embedded P-type layer and method thereof

Abstract

An apparatus configured to reduce delay comprises: a substrate; a group 3 nitride back barrier layer on the substrate; a group nitride channel layer on the group nitride back barrier layer; a group nitride barrier layer on the group nitride channel layer having a band gap larger than the band gap of the group nitride channel layer; a source electrically connected to the group nitride barrier layer; a gate on the group nitride barrier layer; a drain electrically connected to the group nitride barrier layer; and a p-region arranged on or below the group nitride barrier layer. Additionally, at least a portion of the p-region is positioned vertically below at least one of the source, the gate, and the region between the gate and the drain.

Description

Technology Field

[0001] The present disclosure relates to a group 3 nitride transistor having a back barrier structure and a buried p-type layer, and a method thereof. The present disclosure also relates to a group 3 nitride transistor having a back barrier structure and a buried p-type layer. The present disclosure also relates to a method associated with a group nitride transistor having a back barrier structure and a buried p-type layer. The present disclosure also relates to a method for manufacturing a group nitride transistor having a back barrier structure and a buried p-type layer. The present disclosure also relates to a method for implementing a group nitride transistor having a back barrier structure and a buried p-type layer. Background Technology

[0002] Group III nitride-based or gallium nitride (GaN)-based high-electron mobility transistors (EMTs) are highly promising candidates for high-power radiofrequency (RF) applications in both discrete and monolithic microwave integrated circuit (MMIC) forms. Current GaN HEMT designs utilize buffer layers containing traps to achieve the desired breakdown. However, these traps induce memory effects that negatively impact performance. In particular, these designs exhibit some trapping associated with "latency effects."

[0003] Therefore, a solution is needed to address the delay effect and / or other negative performance issues of group 3 nitride HEMTs and to improve the performance of such devices.

[0004] One general aspect comprises a substrate; a group 3 nitride back barrier layer on the substrate; a group nitride channel layer on the group nitride back barrier layer; a group nitride barrier layer on the group nitride channel layer — the group nitride barrier layer comprises a band gap larger than the band gap of the group nitride channel layer —; a source electrically connected to the group nitride barrier layer; a gate on the group nitride barrier layer; a drain electrically connected to the group nitride barrier layer; and a p-region arranged on or below the group nitride barrier layer, wherein at least a portion of the p-region is positioned vertically below at least one of the source, the gate, and the region between the gate and the drain.

[0005] One general aspect comprises a method for manufacturing an apparatus comprising the steps of: providing a substrate; providing a group nitride back barrier layer on the substrate; providing a group nitride channel layer on the group nitride back barrier layer; providing a group nitride barrier layer on the group nitride channel layer having a band gap larger than the band gap of the group nitride channel layer; electrically connecting a source to the group nitride barrier layer; placing a gate on the group nitride barrier layer; electrically connecting a drain to the group nitride barrier layer; and providing a p region placed on or below the group nitride barrier layer, wherein at least a portion of the p region is placed vertically below at least one of a source, a gate, and a region between the gate and the drain.

[0006] One general aspect includes a group 3 nitride transistor having at least one back barrier structure and at least one buried p-type layer.

[0007] One general aspect includes a method associated with a group 3 nitride transistor having at least one back barrier structure and at least one buried p-type layer.

[0008] One general aspect includes a method for implementing a group 3 nitride transistor having at least one back barrier structure and at least one buried p-type layer.

[0009] One general aspect includes a method for manufacturing a group 3 nitride transistor having at least one back barrier structure and at least one buried p-type layer.

[0010] Additional features, benefits, and aspects of the present disclosure may be described or become apparent from the following detailed description, drawings, and claims. Furthermore, it should be understood that the foregoing summary of the present disclosure and the following detailed description are all illustrative and intended to provide further explanation without limiting the scope of the present disclosure as claimed. Brief explanation of the drawing

[0011] The accompanying drawings, included to provide further understanding of the present disclosure, are incorporated herein and constitute part of the specification, illustrate aspects of the present disclosure, and serve to explain the principles of the present disclosure together with the detailed description. No attempt is made to show structural details of the present disclosure in greater detail than may be necessary for a fundamental understanding of the present disclosure and the various ways in which it may be practiced. In the drawings: FIG. 1 illustrates a cross-sectional view of one side of a transistor according to the present disclosure. Figure 2 shows a cross-sectional view of the side of the transistor according to Figure 1. Figure 3 shows a cross-sectional view of the side of the transistor according to Figure 1. FIG. 4 illustrates a semiconductor device that may include a plurality of unit cell transistors according to an aspect of the present disclosure. Figure 5 is a schematic cross-sectional view taken along the VV line of Figure 4. Figure 6 illustrates the band diagram of the disclosed transistor compared to a typical transistor at a specific operating value. Figure 7 illustrates the band diagram of the disclosed transistor compared to a typical transistor at a specific operating value. FIG. 8 illustrates a cross-sectional view of another side of a transistor according to the present disclosure. FIG. 9 illustrates a cross-sectional view of another aspect of a transistor according to the present disclosure. FIG. 10 illustrates a cross-sectional view of another aspect of a transistor according to the present disclosure. FIG. 11 illustrates a cross-sectional view of another aspect of a transistor according to the present disclosure. FIG. 12 illustrates a process for manufacturing a transistor according to the present disclosure. Specific details for implementing the invention

[0012] Aspects of the present disclosure and their various features and advantageous details are more fully described by reference to the non-limiting aspects and examples described and / or illustrated in the accompanying drawings and described in detail in the following description. It should be noted that features illustrated in the drawings are not necessarily drawn in a fixed proportion, and that features of one aspect may be used together with other aspects, as will be recognized by those skilled in the art even if not explicitly stated in this specification. Descriptions of well-known components and processing techniques may be omitted to avoid unnecessarily obscuring aspects of the present disclosure. The examples used in this specification are merely intended to facilitate understanding of how the present disclosure may be practiced and to enable those skilled in the art to further practice aspects of the present disclosure. Accordingly, the examples and aspects of this specification should not be construed as limiting the scope of the present disclosure, which is defined solely by the appended claims and applicable laws. Furthermore, the same reference numerals indicate similar parts in various aspects disclosed throughout the various views of the drawings.

[0013] It will be understood that while terms such as first, second, etc. may be used in this specification to describe various elements, these elements should not be limited by such terms. These terms are used solely to distinguish one element from another. For example, without departing from the scope of this disclosure, a first element may be named a second element, and similarly, a second element may be named a first element. The term "and / or" as used in this specification includes any and all combinations of one or more of the associated listed items.

[0014] When an element such as a layer, region, or substrate is referred to as being "on" or extending "on" another element, it will be understood that this may mean it is directly on or extends onto the other element, or that there may be an intervening element. Conversely, when an element is referred to as being "on" or extending "on" another element, there is no intervening element. Likewise, when an element such as a layer, region, or substrate is referred to as being "over" or extending "over" another element, it will be understood that this may mean it is directly on or extends over the other element, or that there may be an intervening element. Conversely, when an element is referred to as being "over" or extending "on" another element, there is no intervening element. Furthermore, when an element is referred to as being "connected" or "coupled" to another element, it will be understood that this may mean it is directly connected to or coupled to the other element, or that there may be an intervening element. In contrast, when an element is described as being 'directly connected' or 'directly coupled' with another element, there is no intervening element.

[0015] Relative terms such as "below," "above," "upper," "lower," "horizontal," or "vertical" may be used herein to describe the relationship between one element, layer, or region and another element, layer, or region as illustrated in the drawings. It will be understood that these terms and the terms discussed above are intended to include various directions of the device in addition to the directions illustrated in the drawings.

[0016] The terms used herein are for the purpose of describing specific aspects only and are not intended to limit the disclosure. As used herein, the singular forms “a,” “an,” and “the” are intended to include the plural forms unless the context clearly indicates otherwise. As used herein, the terms “comprise,” “comprising,” “include,” and / or “including” specify the presence of the mentioned features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0017] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as generally understood by those skilled in the art to which this disclosure pertains. Terms used herein should be interpreted as having a meaning consistent with their meaning in the context of this specification and related technology, and it will also be understood that they should not be interpreted in an idealized or overly formal sense unless explicitly defined in this specification.

[0018] In addition to the structural type, the characteristics of the semiconductor material on which the transistor is formed can also affect operating parameters. Among the characteristics affecting the operating parameters of a transistor, electron mobility, saturation electron drift velocity, electric breakdown field, and thermal conductivity can influence the high-frequency and high-power characteristics of the transistor.

[0019] Electron mobility measures how quickly electrons accelerate to saturation velocity in the presence of an electric field. In the past, semiconductor materials with high electron mobility were preferred because they allowed more current to be generated with less electric field, resulting in faster response times when an electric field was applied. Saturation electron drift velocity is the maximum speed that electrons can achieve in a semiconductor material. Since higher velocities result in shorter travel times from source to drain, materials with higher saturation electron drift velocities are preferred in high-frequency applications.

[0020] The electric breakdown field is the field strength at which the breakdown of a Schottky junction occurs and the current passing through the device's gate suddenly increases. Materials with high electric breakdown fields are generally preferred for high-power, high-frequency transistors because larger electric fields can be supported by materials of a given size. A larger electric field allows for faster transients because electrons can be accelerated more quickly by a larger field than by a smaller field.

[0021] Thermal conductivity is the ability of a semiconductor material to dissipate heat. In general operation, all transistors generate heat. Consequently, high-power and high-frequency transistors generally generate more heat than small-signal transistors. As the temperature of a semiconductor material increases, junction leakage current typically increases, and the current passing through a field-effect transistor generally decreases due to the reduction in carrier mobility associated with rising temperature. Therefore, when heat is dissipated from the semiconductor, the material remains at a lower temperature and can carry a larger current with a lower leakage current.

[0022] The present disclosure includes both extrinsic and intrinsic semiconductors. Intrinsic semiconductors are not doped (pure). Extrinsic semiconductors are doped. This implies that an agent has been introduced to alter the electron and hole carrier concentrations of the semiconductors under thermal equilibrium. Both p-type and n-type semiconductors are disclosed, wherein the p-type has a hole concentration greater than the electron concentration, and the n-type has an electron concentration greater than the hole concentration.

[0023] Silicon carbide (SiC) possesses excellent physical and electronic properties, theoretically enabling the production of electronic devices capable of operating at higher temperatures, higher power, and higher frequencies than those produced on silicon (Si) or gallium arsenide (GaAs) substrates. High electric breakdown of approximately 4×E6 V / cm, high saturation electron drift velocity of approximately 2.0×E7 cm / sec, and approximately 4.9 W / cm- The high thermal conductivity of SiC indicates that it is suitable for high-frequency and high-power applications. In some aspects, the transistor of the present disclosure comprises Si, GaAs, or other suitable substrates.

[0024] GaN-based HEMTs are highly promising candidates for high-power RF applications in both discrete and MMIC forms. GaN HEMT designs can utilize buffer layers containing traps to achieve desired breakdown. However, these traps can cause memory effects that negatively impact performance. To overcome this limitation, substrates with embedded p-layers can be utilized to achieve breakdown with minimal trapping. Such devices demonstrate a reduction and / or elimination of drain delay effects and the associated trapping. However, some trapping associated with "gate delay effects" still appears, particularly at high negative gate voltages.

[0025] More specifically, the total delay of a transistor, such as a GaN-based HEMT, may be a combination of both gate delay effects and drain delay effects. In certain aspects, implementing various approaches to reduce the first type of delay effect may result in the second type of delay effect becoming more widespread, increased, more pronounced, and / or similar. Therefore, to address the overall delay of a transistor, such as a GaN-based HEMT, it may be necessary to implement structures to reduce the first type of delay effect, which in turn causes the second type of delay effect to become more widespread, increased, more pronounced, and / or similar, and additional structures may be required to address the second type of delay effect. In certain aspects, to address the total delay of a transistor, such as a GaN-based HEMT, it may be necessary to implement drain delay reduction structures and / or processes to reduce drain delay effects, and additional gate delay reduction structures and / or processes to reduce gate delay effects.

[0026] The present disclosure includes an apparatus and / or process that provides a systematic approach to reducing delay. More specifically, the present disclosure includes an apparatus and / or process that implements a drain delay reduction structure and / or process for reducing drain delay effects and an additional gate delay reduction structure and / or process for reducing gate delay effects.

[0027] The present disclosure includes an apparatus and / or process having a structure that uses a buried p-layer to reduce trapping in a GaN HEMT. Such apparatus and / or process have been found to significantly reduce and / or eliminate drain delay-associated trapping and gate delay trapping during a limited operating envelope. For example, in a specific implementation of a GaN HEMT, the gate is reverse-biased to a maximum of about -8 V (volts). However, gate delay trapping effects may occur when the operating envelope is exceeded, for example, when the gate voltage drops below -8 V. Since such gate delay may be undesirable in some applications, it must be reduced or eliminated.

[0028] Simulations indicate that these gate delay effects occur due to the injection and trapping of electrons within the buffer at large negative gate voltages when using conventional buffer structures. For example, when using a conventional buffer structure with unintendedly doped GaN, electrons are injected into and trapped in the buffer at large negative gate voltages.

[0029] The present disclosure includes an apparatus and / or process for reducing and / or limiting gate delay effects. For example, the present disclosure includes an apparatus and / or process for using an aluminum gallium nitride (AlGaN) buffer with a low aluminum (Al) concentration to provide a barrier that reduces electron injection into the buffer. For example, an AlGaN buffer with about 4% Al concentration provides a barrier to reduce electron injection into the buffer. Simulations clearly show that gate delay is reduced using the disclosed buffer layer. In particular, in a specific implementation, simulations clearly show that gate delay is reduced using the disclosed buffer layer down to at least -15 V gate bias.

[0030] Furthermore, the present disclosure includes an apparatus and / or process for reducing and / or limiting gate delay effects by implementing epitaxial growth to reduce the incorporation of background impurities such as silicon (Si), oxygen (O), carbon (C), and / or similar ones within a buffer such as the disclosed AlGaN buffer. It has been found that incorporating high concentrations and high levels of background impurities is problematic when using AlGaN back barriers. The disclosed apparatus and / or process can be implemented to significantly reduce impurity incorporation. More specifically, aspects of the present disclosure can implement back barriers having low background impurity levels. In one aspect, the present disclosure can implement AlGaN back barriers with low background impurity levels. In this regard, it has been found that impurities form complexes with dislocations, such as point defects, which act as deep trap levels.

[0031] When growing GaN on SiC, high-density threading dislocations can form due to lattice mismatch. These defects can cause current leakage, low breakdown voltage, and carrier trapping. Another source of defects may be impurities acting as unintentional doping, which can generate trap centers. To prevent deep electron penetration within the GaN buffer, an AlGaN buffer can be used to confine electrons in the GaN channel near the AlGaN barrier.

[0032] The devices and / or processes of the present disclosure may include buried P-layer structures in transistor implementations, such as GaN HEMT devices, and demonstrate very positive results in significantly reduced and / or eliminated drain delay. However, gate delay effects still occur in these devices. For example, these devices still struggle with gate delay effects at elevated negative gate voltages. This delay in response can be caused by traps in the buffer. Simulations show that an AlGaN buffer grown on a buried p-layer substrate with very low levels of background impurities, such as carbon, silicon, and oxygen, can dramatically improve electron confinement, reduce and / or eliminate gate delay, and also reduce and / or eliminate overall delay.

[0033] FIG. 1 illustrates a cross-sectional view of a side of a transistor according to the present disclosure.

[0034] In particular, FIG. 1 illustrates a cross-sectional view of a transistor (100). The transistor (100) may include a substrate layer (102). The substrate layer (102) may be made of silicon carbide (SiC). In some aspects, the substrate layer (102) may be a semi-insulating SiC substrate, a p-type substrate, an n-type substrate, etc. In some aspects, the substrate layer (102) may be very lightly doped. In one aspect, the background impurity level may be low. In one aspect, the background impurity level is 1E15 / cm²3 It may be as follows. In one aspect, the substrate layer (102) may be formed of SiC selected from the group including 6H, 4H, 15R, 3C SiC, etc. In one aspect, the substrate layer (102) may be semi-insulating and doped with vanadium or any other suitable dopant, or may be formed of high-purity undoped SiC having defects that provide semi-insulating properties.

[0035] In another aspect, the substrate layer (102) may be GaAs, GaN, or any other material suitable for the application described herein. In another aspect, the substrate layer (102) may comprise sapphire, spinel, ZnO, silicon, or any other material capable of supporting the growth of group 3 nitride materials. In a particular aspect, the substrate layer (102) may comprise a flat upper surface that is generally parallel to the X-axis and / or generally parallel to the Z-axis (perpendicular to the X-axis and Y-axis), as shown in FIG. 1. In a particular aspect, the substrate layer (102) may comprise a flat lower surface that is generally parallel to the X-axis and / or generally parallel to the Z-axis (perpendicular to the X-axis and Y-axis), as shown in FIG. 1. Here, the upper and lower surfaces are defined along the Y-axis.

[0036] The transistor (100) may include an embedded p-region or p-type material layer (106) that can be formed within a substrate layer (102). The p-type material layer (106) may be configured to at least partially form a drain delay reduction structure, a drain delay removal structure, etc. The p-type material layer (106) may be provided only on the substrate layer (102), may extend from the substrate layer (102) to an epitaxial layer within the transistor (100), and / or may be located only on the epitaxial layer of the transistor (100). A dopant may be incorporated into the epitaxial layer by ion implantation alone, through epitaxial growth, or a combination of both. The p-type material layer (106) may span multiple layers and may include multiple regions of different or graded p-doping. According to another aspect of the present disclosure, the p-type material layer (106) may also be formed below the barrier layer (108) and / or within the substrate layer (102) between the barrier layer (108) and the substrate layer (102).

[0037] According to an aspect of the present disclosure, at least a portion of the substrate layer (102) may comprise a p-type material layer (106). According to an aspect of the present disclosure, the p-type material layer (106) may be formed by ion implantation and annealing of aluminum (Al). In another aspect, the p-type material layer (106) may be formed by ion implantation of boron, gallium, or any other material capable of forming a p-type layer, or a combination thereof. In one aspect, the p-type material layer (106) may be formed by implantation and annealing of Al prior to the growth of any GaN layer. In one aspect, ion implantation may utilize a channeling implant. In one aspect, the channeling implant may include aligning an ion beam to the substrate layer (102). Alignment of the ion beam may increase implantation efficiency. In another aspect, ion implantation may not utilize channeling.

[0038] An aspect of the present disclosure may utilize implant channeling to controllably form an implanted region of a p-type material layer (106) in a silicon carbide implementation of a substrate layer (102) in which the depth is very uniform and lattice damage is reduced. Channeling occurs when ions are implanted along the crystal axis of the substrate layer (102). When the implantation direction is close to the long axis of the crystal lattice, the atoms of the crystal lattice appear to be "aligned" with respect to the implantation direction, and the implanted ions appear to move along the channels created by the crystal structure to form the p-type material layer (106). This reduces the possibility of collision between the implanted ions and the atoms of the crystal lattice. Consequently, the implantation depth of the p-type material layer (106) can be greatly increased.

[0039] Generally, channeling in silicon carbide occurs when the injection direction is within approximately ±2° of the crystal axis of the silicon carbide crystal. In some respects, the injection may be greater than ±2° of the crystal axis of the silicon carbide crystal, but the injection may be less effective. For example, if the injection direction is greater than approximately ±2° of the crystal axis of the silicon carbide crystal, atoms within the lattice may appear to be randomly distributed with respect to the injection direction, which can reduce the channeling effect. As used herein, the term "injection angle" refers to the c-axis of the semiconductor layer into which ions are implanted or <0001> It refers to the angle between the crystal axis, such as the axis, and the injection direction. Therefore, an injection angle of less than about 2° with respect to the c-axis of the silicon carbide layer can be expected to result in channeling. However, other injection angles may also be utilized.

[0040] In one aspect, the p-type material layer (106) has an injection energy E1=100keV and a capacity of 1E13cm at 25°C. 2 to 4H-SiC injected under channeling conditions 27 It can be formed by ion implanting Al. In one aspect, a p-type material layer (106) is formed at 25°C with an implantation energy E2=300 keV and a capacitance 1E13 cm. 2to 4H-SiC injected under channeling conditions 27 It can be formed by ion implanting Al. However, other implantation energies and capacities are also considered. For example, in some aspects, the implantation energy may be 20 keV to 80 keV, 80 keV to 120 keV, 120 keV to 160 keV, 160 keV to 200 keV, 200 keV to 240 keV, 240 keV to 280 keV, 280 keV to 340 keV, 340 keV to 400 keV, 20 keV to 400 keV, and / or 80 keV to 340 keV, and in some aspects, the implantation capacity may be 0.6E13 cm 2 Inner .8E13cm 2 , .8E13cm 2 Up to 1.2E13cm 2 , 1.2E13cm 2 Up to 1.6E13cm 2 , 1.6E13cm 2 to 2E13cm 2 , .6E13cm 2 to 2E13cm 2 and / or .8E13cm 2 Up to 1.2E13cm 2 It may be possible. In addition, the p-type material layer (106) may be formed by injecting other materials such as boron (B), gallium (Ga), etc., and high-temperature annealing may be performed afterwards.

[0041] In one aspect, the p-type material layer (106) may become a deep layer due to ion implantation. In one aspect, the p-type material layer (106) may have a thickness of 1 μm or less due to ion implantation. In one aspect, the p-type material layer (106) may have a thickness of 0.7 μm or less due to ion implantation. In one aspect, the p-type material layer (106) may have a thickness of 0.5 μm or less due to ion implantation. In one aspect, the p-type material layer (106) may have a thickness of 0.3 μm to 0.5 μm due to ion implantation. In one aspect, the p-type material layer (106) may have a thickness of 0.2 μm to 0.6 μm due to ion implantation. In one aspect, the p-type material layer (106) may have a thickness of 0.4 μm to 0.6 μm due to ion implantation. In one aspect, the p-type material layer (106) may have a thickness of 0.6 μm to 0.8 μm due to ion implantation. In one aspect, the p-type material layer (106) may have a thickness of 0.6 μm to 1.6 μm due to ion implantation. In one aspect, the p-type material layer (106) may have a thickness of 0.6 μm to 2.1 μm due to ion implantation. In one aspect, the p-type material layer (106) may have a thickness of 1 μm to 5 μm due to ion implantation. In one aspect, the implantation and / or doping of the p-type material layer (106) is cm 3 It can be within the range of 5E15 to 5E17 and can be extended up to a maximum depth of 5μm.

[0042] In one aspect, due to ion implantation, the p-type material layer (106) may have a thickness of 0.05% to 0.3% of the thickness of the substrate layer (102). In one aspect, due to ion implantation, the p-type material layer (106) may have a thickness of 0.05% to 0.1% of the thickness of the substrate layer (102). In one aspect, due to ion implantation, the p-type material layer (106) may have a thickness of 0.1% to 0.15% of the thickness of the substrate layer (102). In one aspect, due to ion implantation, the p-type material layer (106) may have a thickness of 0.15% to 0.2% of the thickness of the substrate layer (102). In one aspect, due to ion implantation, the p-type material layer (106) may have a thickness of 0.2% to 0.25% of the thickness of the substrate layer (102). In one aspect, due to ion implantation, the p-type material layer (106) may have a thickness of 0.25% to 0.3% of the thickness of the substrate layer (102).

[0043] A p-type material layer (106) can be injected into a substrate layer (102) and subsequently annealed. Annealing may allow the injection to be activated. In one aspect, a masking layer material may be utilized during injection. In some aspects, during the annealing of the p-type material layer (106), a capping layer material may be used to cover the wafer surface to prevent dissociation of the substrate at high temperatures. Once the p-type material layer (106) is formed, the masking layer material may be removed. Annealing may be performed for 5 to 30 minutes at a temperature range of 1500 to 1850°C. Other annealing time and temperature profiles are also considered.

[0044] In some aspects, the substrate layer (102) may be made of a p-type material SiC substrate. Additionally, in this aspect, the substrate layer (102), which is a p-type material SiC substrate, may subsequently undergo a process as described herein, including the implantation of an additional p-type layer. In aspects of the transistor (100) of the present disclosure, the p-type material layer (106) may be neutralized to limit the length of the p-type material layer (106). In one aspect, neutralization may include the implantation of impurities. In one aspect, neutralizing the p-type material layer (106) may include absorbing the charge of the p-type material layer (106) into a material of opposite polarity. Another method of limiting the length of the p-type material layer (106) may be to etch the p-type material layer (106). Another method of limiting the length of the p-type material layer (106) may be to use a masking material to limit the implantation area.

[0045] In the aspect of the transistor (100) of the present disclosure, a p-type material layer (106) may be formed by growing the p-type material layer (106). The growth may be, for example, epitaxial. To limit the length of the p-type material layer (106), the p-type material layer (106) may be etched or neutralized. In the aspect of the transistor (100) of the present disclosure, the substrate layer (102) may be etched, and the p-type material layer (106) may be formed by growing the p-type material layer (106). In one aspect, the growth may be epitaxial.

[0046] In an aspect of the transistor (100) of the present disclosure, the p-type material layer (106) may be an epitaxial layer and may be GaN. In some aspects, the p-type material layer (106) may be an epitaxial layer and may be GaN, and the p-type material layer (106) may comprise magnesium (Mg), carbon (C) and / or zinc. In some aspects, the p-type material layer (106) may be an epitaxial layer and may be GaN, and the p-type material layer (106) may comprise the implantation of magnesium (Mg), carbon (C) and / or zinc.

[0047] In an aspect of the transistor (100) of the present disclosure, the substrate layer (102) may be etched, and the p-type material layer (106) may be formed by growing the p-type material layer (106). In one aspect, the growth may be epitaxial. In an aspect of the transistor (100) of the present disclosure, the p-type material layer (106) may be an epitaxial layer formed of SiC. In some aspects, the p-type material layer (106) may be an epitaxial layer and may be SiC, and the p-type material layer (106) may include Al and / or Br. In some aspects, the p-type material layer (106) may be an epitaxial layer and may be SiC, and the p-type material layer (106) may include the implantation of Al and / or Br.

[0048] In some aspects, the p-type material layer (106) may have a thickness of less than 0.6 μm. In some aspects, the p-type material layer (106) may have a thickness of less than 0.5 μm. In some aspects, the p-type material layer (106) may have a thickness of less than 0.4 μm. In some aspects, the p-type material layer (106) may have a thickness of less than 0.3 μm. In some aspects, the p-type material layer (106) may have a thickness of less than 0.2 μm. In some aspects, the p-type material layer (106) may have a thickness of 0.1 to 0.6 μm. In some aspects, the p-type material layer (106) may have a thickness of 0.5 to 0.6 μm. In some aspects, the p-type material layer (106) may have a thickness of 0.4 μm to 0.5 μm. In some aspects, the p-type material layer (106) may have a thickness of 0.3 to 0.4 μm. In some aspects, the p-type material layer (106) may have a thickness of 0.2 μm to 0.3 μm. In some aspects, the p-type material layer (106) may have a thickness of 0.1 to 0.3 μm. In some aspects, the p-type material layer (106) may have a thickness of 0.05 to 0.25 μm. In some aspects, the p-type material layer (106) may have a thickness of 0.15 to 0.25 μm.

[0049] In terms of the transistor (100) of the present disclosure, the p-type material layer (106) may be a graded layer. In one aspect, the p-type material layer (106) may be a stepped graded layer. In one aspect, the p-type material layer (106) may be a multilayer. In a specific aspect, the p-type material layer (106) may include a planar upper surface that is generally parallel to the X-axis and / or generally parallel to the Z-axis (perpendicular to the X-axis and Y-axis), as shown in FIG. 1. In a specific aspect, the p-type material layer (106) may include a planar lower surface that is generally parallel to the X-axis and / or generally parallel to the Z-axis (perpendicular to the X-axis and Y-axis), as shown in FIG. 1. Here, the upper and lower surfaces are defined along the Y-axis.

[0050] Depending on the material of the substrate layer (102), a nucleation layer (136) may be formed on the substrate layer (102) to reduce lattice mismatch between the substrate layer (102) and the next layer of the transistor (100). In one aspect, the nucleation layer (136) may be formed directly on the substrate layer (102). In another aspect, the nucleation layer (136) may be formed on the substrate layer (102) having intermediate layer(s), such as SiC epitaxial layer(s) formed on the SiC implementation of the substrate layer (102). In one aspect, the nucleation layer is aluminum nitride (AlN), such as undoped AlN.

[0051] The nucleation layer (136) may be or may contain other suitable materials, such as group 3 nitride materials. For example, Al x In 1-x-y GaN (where 0<=x<=1, 0<=y<1, x+y<=1), AlGaN, undoped AlGaN and / or others. The nucleation layer (136) can be formed on the substrate layer (102) using known semiconductor growth techniques such as metal oxide chemical vapor deposition (MOCVD), hydrogen vapor phase epitaxy (HVPE), molecular beam epitaxy (MBE), etc.

[0052] In the side view of the transistor (100) of the present disclosure, a back barrier layer (120) may be formed directly above the nucleation layer (136) or on the nucleation layer (136) using intermediate layer(s). In the side view of the transistor (100) of the present disclosure, a back barrier layer (120) may be formed directly above the substrate layer (102) or on the substrate layer (102) using intermediate layer(s). In particular, the back barrier layer (120) may be composed of at least a portion of a gate delay reduction structure, a gate delay removal structure, etc., in combination with a p-type material layer (106) composed at least partially of a drain delay reduction structure, a drag delay removal structure, etc., and the back barrier layer (120) composed at least partially of a gate delay reduction structure, a gate delay removal structure, etc., may work together in a synergistic manner to reduce the overall delay of the transistor (100). As further described in this specification, this synergistic overall delay reduction of the transistor (100) was an unexpected result of the combined structure of the back barrier layer (120) and the p-type material layer (106).

[0053] More specifically, a transistor (100) combined with a p-type material layer (106) and a back barrier layer (120) as disclosed, and their associated structures and / or associated processes, can provide a systematic approach to reducing delay. More specifically, the transistor (100) of the present disclosure may implement the p-type material layer (106) and / or its processes as a drain delay reduction structure and / or a process for reducing drain delay effects, and the transistor (100) of the present disclosure may implement the back barrier layer (120) and / or its processes as a gate delay reduction structure and / or a process for reducing gate delay effects.

[0054] In this regard, it has been determined that impurities such as silicon, oxygen, carbon, etc., within the back barrier layer (120) can increase gate delay. In particular, impurities cause trapping, leakage, etc. More specifically, aspects of the present disclosure may implement a back barrier layer (120) having a low background impurity level. In one aspect, the present disclosure may implement AlGaN for the back barrier layer (120) having a low background impurity level. In this regard, it has been found that impurities form a complex having a potential such as a point defect that acts as a deep trap level.

[0055] More specifically, the present disclosure can implement AlGaN for a back barrier layer (120) having a low background impurity level that can be defined as less than 1E17 per cubic cm (centimeter), less than 5E16 per cubic cm, less than 1E16 per cubic cm, or less than 1E15 per cubic cm. Furthermore, the present disclosure can implement AlGaN for a back barrier layer (120) having a low background impurity level that can be defined as less than 1E17 per cubic cm (centimeter), less than 5E16 per cubic cm, less than 1E16 per cubic cm, or less than 1E15 per cubic cm of silicon, oxygen, carbon, etc.

[0056] Furthermore, the present disclosure may implement AlGaN for a back barrier layer having a low background impurity level of silicon and oxygen, which can be defined as an impurity of silicon, oxygen, and carbon less than 1E17 per cubic cm (centimeter), less than 5E16 per cubic cm, less than 1E16 per cubic cm, or less than 1E15 per cubic cm. In one aspect, the low background impurity level of silicon and oxygen may be defined as an impurity of silicon and oxygen less than 1E16. Furthermore, the present disclosure may implement AlGaN for a back barrier layer (120) having a low background impurity level of carbon, which can be defined as an impurity of silicon, oxygen, and carbon less than 1E17 per cubic cm (centimeter), less than 5E16 per cubic cm, less than 1E16 per cubic cm, or less than 1E15 per cubic cm. In one aspect, the low background impurity level of carbon may be defined as an impurity of carbon less than 5E16.

[0057] Additionally or otherwise, low background impurity levels may be defined as impurities between 1E15 and 1E17 per cubic cm, between 1E15 and 1E16 per cubic cm, between 1E16 and 5E16 per cubic cm, or between 5E16 and 1E17 per cubic cm. In particular, low background impurity levels may be defined as impurities such as silicon, oxygen, carbon, etc., between 1E15 and 1E17 per cubic cm, between 1E15 and 1E16 per cubic cm, between 1E16 and 5E16 per cubic cm, or between 5E16 and 1E17 per cubic cm.

[0058] In particular, low background impurity levels can be defined as silicon and oxygen impurities between 1E15 and 1E17 per cubic cm, between 1E15 and 1E16 per cubic cm, between 1E16 and 5E16 per cubic cm, or between 5E16 and 1E17 per cubic cm.

[0059] In particular, low background impurity levels can be defined as silicon and oxygen impurities between 1E15 and 1E17 per cubic cm, between 1E15 and 1E16 per cubic cm, between 1E16 and 5E16 per cubic cm, or between 5E16 and 1E17 per cubic cm. In particular, low background impurity levels can be defined as carbon impurities between 1E15 and 1E17 per cubic cm, between 1E15 and 1E16 per cubic cm, between 1E16 and 5E16 per cubic cm, or between 5E16 and 1E17 per cubic cm.

[0060] Additionally, the back barrier layer (120) may be configured to provide a sharp interface to the channel layer (104). This interface may function as a barrier to electrons. In terms of the transistor (100) of the present disclosure, the back barrier layer (120) may be a grade layer. In one aspect, the back barrier layer (120) may be a stepped grade layer. In one aspect, the back barrier layer (120) may be a multilayer.

[0061] In a specific aspect, the back barrier layer (120) may be an AlGaN buffer layer with a low Al concentration to provide a barrier that reduces electron injection into the buffer layer. In this regard, the barrier that reduces electron injection into the buffer layer results in a gate delay reduction structure, a gate delay removal structure, etc. For example, the back barrier layer (120) may be implemented with AlGaN with an approximately 4% Al concentration to provide a barrier that reduces electron injection into the buffer. In this regard, it may be approximately 0.5%, 1%, 1.5%, or within 2%. In a specific aspect, the back barrier layer (120) may be implemented with AlGaN having an Al concentration of 1% to 6%, 1% to 1.5%, 1.5% to 2%, 2% to 2.5%, 2.5% to 3%, 3% to 3.5%, 3.5% to 4%, 3.5% to 4.5%, 3.8% to 4.2%, 4% to 4.5%, 4.5% to 5%, 5% to 5.5%, or 5.5% to 6% to provide a barrier that reduces electron injection into a buffer, a gate delay reduction structure, a gate delay removal structure, etc.

[0062] In this aspect, the transistor (100) may have a limited gate delay during a limited operating envelope. For example, for a specific implementation of a GaN HEMT, there is a reverse bias of up to about -8V (volts) on the gate. However, the back barrier layer (120) may be configured as a gate delay reduction, gate delay removal, etc. for implementations outside the limited operating envelope where a gate delay trapping effect may exist. For example, there is an implementation of the transistor (100) where the gate voltage drops below -8V. In particular, the back barrier layer (120), which is composed of at least partially a gate delay reduction structure, gate delay removal structure, etc., combined with a p-type material layer (106) composed of at least partially a drain delay structure, drain delay removal structure, etc., works together synergistically to reduce the overall delay of the transistor (100) during these low gate voltage conditions. As further described in this specification, this synergistic overall reduction in the delay of the transistor (100) was an unexpected result of the combined structure of the back barrier layer (120) and the p-type material layer (106).

[0063] Additionally, the back barrier layer (120) of the transistor (100) may be further configured and / or processed to reduce and / or limit gate delay effects by implementing epitaxial growth. In particular, the back barrier layer (120) of the transistor (100) may be further configured and / or processed to reduce and / or limit gate delay effects by implementing epitaxial growth while reducing the incorporation of background impurities, such as silicon (Si), oxygen (O), carbon (C), etc., into the AlGaN of the implementation of the back barrier layer (120). More specifically, aspects of the present disclosure may implement a back barrier layer (120) with a low background impurity level. In one aspect, the present disclosure may implement AlGaN for a back barrier layer (120) having a low background impurity level. In this regard, it has been found that impurities form complexes having potentials such as point defects that act as deep trap levels. In this regard, it has been found that the incorporation of high levels of background impurities into the back barrier layer (120) at high concentrations is a problem when using AlGaN for the back barrier layer (120). The back barrier layer (120) can be realized through epitaxial growth with significantly reduced impurity incorporation. More specifically, the back barrier layer (120) can be realized through epitaxial growth of AlGaN that reduces the incorporation of background impurities such as silicon (Si), oxygen (O), carbon (C), etc.

[0064] More specifically, the present disclosure can implement AlGaN for a back barrier layer (120) having a low background impurity level that can be defined as less than 1E17 per cubic cm (centimeter), less than 5E16 per cubic cm, less than 1E16 per cubic cm, or less than 1E15 per cubic cm. Furthermore, the present disclosure can implement AlGaN for a back barrier layer (120) having a low background impurity level that can be defined as less than 1E17 per cubic cm (centimeter), less than 5E16 per cubic cm, less than 1E16 per cubic cm, or less than 1E15 per cubic cm, such as silicon, oxygen, carbon, etc.

[0065] Furthermore, the present disclosure may implement AlGaN for a back barrier layer (120) having a low background impurity level of silicon and oxygen, which can be defined as less than 1E17 per cubic cm (centimeter), less than 5E16 per cubic cm, less than 1E16 per cubic cm, or less than 1E15 per cubic cm of silicon, oxygen, and carbon impurities. In one aspect, the low background impurity level of silicon and oxygen can be defined as less than 1E16 of silicon and oxygen impurities. Furthermore, the present disclosure may implement AlGaN for a back barrier layer (180) having a low background impurity level of carbon, wherein the low background impurity level may be defined as an impurity of silicon, oxygen, and carbon of less than 1E17 per cubic cm (centimeter), less than 5E16 per cubic cm, less than 1E16 per cubic cm, or less than 1E15 per cubic cm. In one aspect, the low background impurity level of carbon may be defined as an impurity of carbon of less than 5E16.

[0066] Additionally or otherwise, low background impurity levels may be defined as impurities between 1E15 and 1E17 per cubic cm, between 1E15 and 1E16 per cubic cm, between 1E16 and 5E16 per cubic cm, or between 5E16 and 1E17 per cubic cm. In particular, low background impurity levels may be defined as impurities such as silicon, oxygen, carbon, etc., between 1E15 and 1E17 per cubic cm, between 1E15 and 1E16 per cubic cm, between 1E16 and 5E16 per cubic cm, or between 5E16 and 1E17 per cubic cm.

[0067] In particular, low background impurity levels can be defined as silicon and oxygen impurities between 1E15 and 1E17 per cubic cm, between 1E15 and 1E16 per cubic cm, between 1E16 and 5E16 per cubic cm, or between 5E16 and 1E17 per cubic cm.

[0068] In particular, low background impurity levels can be defined as silicon and oxygen impurities between 1E15 and 1E17 per cubic cm, between 1E15 and 1E16 per cubic cm, between 1E16 and 5E16 per cubic cm, or between 5E16 and 1E17 per cubic cm. In particular, low background impurity levels can be defined as carbon impurities between 1E15 and 1E17 per cubic cm, between 1E15 and 1E16 per cubic cm, between 1E16 and 5E16 per cubic cm, or between 5E16 and 1E17 per cubic cm.

[0069] In this regard, it has been discovered that the cause of the defect may be an impurity that acts as unintentional doping and can create trap centers, etc. in the transistor (100). To prevent deep intrusion of electrons into the GaN buffer of the transistor (100) or into the channel layer (104) of the transistor (100), the back barrier layer (120) may be implemented as an AlGaN buffer as described herein and may be used to confine electrons within the channel layer (104) near the back barrier layer (120). The disclosed implementation and configuration of the back barrier layer (120) has been further demonstrated to improve the breakdown voltage in the transistor (100) and / or the GaN HEMT implementation of the transistor (100).

[0070] Accordingly, the transistor (100) may include a p-type material layer (106) as described herein to significantly reduce and / or eliminate drain delay. However, the transistor (100) may still experience gate delay effects. For example, the transistor (100) may still experience gate delay effects at an elevated negative gate voltage. Traps within the buffer of the transistor (100) may be the cause of these delays. Accordingly, the back barrier layer (120) may be implemented with AlGaN with very low levels of background impurities such as carbon, silicon, and oxygen grown on the p-type material layer (106) to significantly improve electron confinement and reduce and / or eliminate gate delay, as well as reduce and / or eliminate overall delay.

[0071] In a specific aspect, the rear barrier layer (120) may comprise an upper surface of a plane generally parallel to the X-axis and / or generally parallel to the Z-axis (perpendicular to the X-axis and Y-axis), as illustrated in FIG. 1. In a specific aspect, the rear barrier layer (120) may comprise a lower surface of a plane generally parallel to the X-axis and / or generally parallel to the Z-axis (perpendicular to the X-axis and Y-axis), as illustrated in FIG. 1. Here, the upper and lower are defined along the Y-axis.

[0072] In some aspects, the channel layer (104) may be formed directly on the back barrier layer (120) or formed on the back barrier layer (120) using intermediate layer(s). In one aspect, the channel layer (104) is formed of GaN.

[0073] Depending on the side, the channel layer (104) is Al x Ga y In (1-x-y) It may be formed of a different suitable material such as a group 3 nitride such as N (where 0<=x<=1, 0<=y<1, x+y<=1), e.g. GaN, AlGaN, AIN, etc., or other suitable material. The channel layer (104) or part thereof may be doped with a dopant such as Fe and / or C, or otherwise may not be doped wholly or partially.

[0074] In a particular aspect, the channel layer (104) may comprise an upper surface of a plane generally parallel to the X-axis and / or generally parallel to the Z-axis (perpendicular to the X-axis and Y-axis), as illustrated in FIG. 1. In a particular aspect, the channel layer (104) may comprise a lower surface of a plane generally parallel to the X-axis and / or generally parallel to the Z-axis (perpendicular to the X-axis and Y-axis), as illustrated in FIG. 1. Here, the upper and lower are defined along the Y-axis.

[0075] In one aspect, the channel layer (104) may be high-purity GaN. In one aspect, the channel layer (104) may be high-purity GaN that is low-concentration doped n-type. In one aspect, the combined thickness of the channel layer (104) and the back barrier layer (120) may have a thickness defined as the distance between the upper surface of the substrate layer (102) and the lower surface of the barrier layer (108). In one aspect, the combined thickness of the channel layer (104) and the rear barrier layer (120) along the Y-axis between the upper surface of the channel layer (104) and the lower surface of the rear barrier layer (120) may be 10% - 20%, 20% - 30%, 30% - 40%, 40% - 50%, 50% - 60%, 60% - 70%, 70% - 80%, or 80% - 90% of the thickness of the substrate layer (102). In one aspect, the combined thickness of the channel layer (104) and the rear barrier layer (120) may be less than 0.8 microns, less than 0.7 microns, less than 0.6 microns, less than 0.5 microns, or less than 0.4 microns. In one aspect, the combined thickness of the channel layer (104) and the rear barrier layer (120) may range from 0.8 microns to 0.6 microns, 0.7 microns to 0.5 microns, 0.6 microns to 0.4 microns, 0.5 microns to 0.3 microns, 0.4 microns to 0.2 microns, and 0.7 microns to 0.3 microns. In one aspect, the rear barrier layer (120) may be thicker than the channel layer (104) along the Y-axis between the upper surface and the lower surface. In one aspect, the rear barrier layer (120) may be 10%, 20%, 30%, 40%, 50%, 60%, 70%, 80%, 90%, 100%, 120%, 140%, or 160% thicker than the channel layer (104) along the Y-axis between the upper surface and the lower surface.In one aspect, the rear barrier layer (120) may be 10% - 20%, 20% - 30%, 30% - 40%, 40% - 50%, 50% - 60%, 60% - 70%, 70% - 80%, 80% - 90%, 90% - 100%, 100% - 120%, 120% - 140% or 140% - 160% thicker than the channel layer (104) along the Y-axis between the upper surface and the lower surface.

[0076] In one aspect, the transistor (100) may have an intermediate layer(s) thickness defined as the length between the upper surface of the substrate layer (102) and the lower surface of the barrier layer (108). In one aspect, the intermediate layer(s) thickness may be less than 0.8 microns, less than 0.7 microns, less than 0.6 microns, less than 0.5 microns, or less than 0.4 microns. In one aspect, the intermediate layer(s) thickness may have a range of 0.8 microns to 0.6 microns, 0.7 microns to 0.5 microns, 0.6 microns to 0.4 microns, 0.5 microns to 0.3 microns, or 0.4 microns to 0.2 microns.

[0077] A barrier layer (108) can be formed on the channel layer (104). In one aspect, the barrier layer (108) can be formed directly on the channel layer (104), and in another aspect, the barrier layer (108) can be formed on the channel layer (104) using intermediate layer(s). Depending on the aspect, the channel layer (104) is Al x Ga y In (1-x-y)It may be formed of a group 3 nitride such as N (where 0<=x<=1, 0<=y<=1, x+y<=1), other suitable materials such as AlGaN, AlN, or InAlGaN, or another suitable material. In one aspect, the barrier layer (108) may be AlGaN, and in another aspect, the barrier layer (108) may be AlN. In one aspect, the barrier layer (108) may not be doped. In one aspect, the barrier layer (108) may be doped. In one aspect, the barrier layer (108) may be an n-type material. In some aspects, the barrier layer (108) may have multiple layers of n-type materials having different carrier concentrations. In one aspect, the barrier layer (108) may be a group 3 nitride or a combination thereof. In a particular aspect, the barrier layer (108) may include a planar upper surface that is generally parallel to the X-axis and / or generally parallel to the Z-axis (perpendicular to the X-axis and Y-axis), as illustrated in FIG. 1. In a particular aspect, the barrier layer (108) may include a planar lower surface that is generally parallel to the X-axis and / or generally parallel to the Z-axis (perpendicular to the X-axis and Y-axis), as illustrated in FIG. 1. Here, the upper and lower surfaces are defined along the Y-axis.

[0078] In one aspect, the bandgap of the channel layer (104) may be smaller than the bandgap of the barrier layer (108) to form a two-dimensional electron gas (2DEG) at the heterogeneous interface (152) between the channel layer (104) and the barrier layer (108) when biased to an appropriate level. In one aspect, the bandgap of the channel layer (104), which may be GaN, may be smaller than the bandgap of the barrier layer (108), which may be AlGaN, to form a two-dimensional electron gas (2DEG) at the heterogeneous interface (152) between the channel layer (104) and the barrier layer (108) when biased to an appropriate level.

[0079] In an aspect of the present disclosure, the heterogeneous interface (152) may be located between the barrier layer (108) and the channel layer (104). In one aspect, the source (110) and drain (112) electrodes may be formed to form a resistive contact such that current flows between the source (110) and drain (112) electrodes through a two-dimensional electron gas (2DEG) induced at the heterogeneous interface (152) between the channel layer (104) and the barrier layer (108) when the gate (114) electrode is biased to an appropriate level. In one aspect, the heterogeneous interface (152) may be in the range of .005 μm to .007 μm, .007 μm to .009 μm, and .009 μm to .011 μm.

[0080] In one aspect, a source (110), a drain (112), and a gate (114) may be formed on a barrier layer (108). The source (110), drain (112), and / or gate (114) may be placed directly on the barrier layer (108) or may be on an intermediate layer(s) on the barrier layer (108), such as an AlGaN layer on an AlN barrier layer. Other or additional intermediate layers are possible. For example, a spacer layer (116) made of SiN, AlO, SiO2, AlN, etc., or a combination thereof, may be provided on the barrier layer (108) or another intermediate layer. In one aspect, the barrier layer (108) may include a region (164) below the source (110) and / or drain (112), which is an N+ material. In one aspect, the barrier layer (108) may include a region (164) below the Si-doped source (110) and / or drain (112). In one aspect, an n-type dopant is injected into the region (164).

[0081] In one aspect, a source (110), a drain (112), and a gate (114) may be formed on a channel layer (104). The source (110), the drain (112), and / or the gate (114) may be placed directly on the channel layer (104), or may be on an intermediate layer(s) on the channel layer (104), such as an AlGaN layer on an AlN barrier layer. In one aspect, the channel layer (104) may include a region (164) below the source (110) and / or drain (112) which is an N+ material. In one aspect, the channel layer (104) may include a region (164) below the source (110) and / or drain (112) which is doped with Si. In one aspect, an n-type dopant is injected into the region (164).

[0082] In some aspects, the source (110) and drain (112) may be symmetric with respect to the gate (114). In some aspects, the source (110) and drain (112) may be symmetric with respect to the gate (114). In some aspects, the source (110) and drain (112) may be asymmetric with respect to the gate (114). In one aspect, the gate (114) may be a T-shaped gate. In one aspect, the gate (114) may be a non-T-shaped gate.

[0083] To protect and isolate the gate (114) and drain (112), a spacer layer (116) may be placed on a barrier layer (108) on the opposite side of the channel layer (104) adjacent to the gate (114), drain (112), and source (110). The spacer layer (116) may be a passivation layer made of SiN, AlO, SiO, SiO2, AlN, etc., or a combination including a multilayer of these. In one aspect, the spacer layer (116) is a passivation layer made of SiN. In one aspect, the spacer layer (116) may be deposited using MOCVD, plasma chemical vapor deposition (CVD), hot filament CVD, or sputtering. In one aspect, the spacer layer (116) may involve the deposition of Si3N4. In one aspect, the spacer layer (116) forms an insulating layer. In one aspect, the spacer layer (116) forms an insulator. In one aspect, the spacer layer (116) may be a dielectric. In one aspect, the spacer layer (116) may be provided on the barrier layer (108). In one aspect, the spacer layer (116) may comprise a non-conductive material such as a dielectric. In one aspect, the spacer layer (116) may comprise a plurality of different dielectric layers or a combination of dielectric layers. In one aspect, the spacer layer (116) may have various thicknesses, and a suitable thickness range is approximately 0.05 to 2 microns. In one aspect, the spacer layer (116) may comprise a material such as a group 3 nitride material having different group 3 elements such as an alloy of Al, Ga, or In, and a suitable spacer layer material is Al x In y Ga 1-x-y (Here, 0<=x<=1 and 0<=y<=1, x+y<=1).

[0084] In some aspects, the gate (114) may be deposited in a channel formed in the spacer layer (116), and the T-gate may be formed using semiconductor processing techniques understood by those skilled in the art. Other gate configurations are also possible and considered.

[0085] In an aspect of the transistor (100) of the present disclosure, the substrate layer (102) may be silicon carbide and may include a carbon plane. In one aspect, the substrate layer (102) may be silicon carbide and may include a carbon plane disposed adjacent to the channel layer (104). In one aspect, the substrate layer (102) may be silicon carbide and may include a carbon plane, and the substrate layer (102) may be inverted to be disposed adjacent to the channel layer (104). In one aspect, the channel layer (104) may be GaN having a nitrogen plane adjacent to the carbon plane of the substrate layer (102). In one aspect, the channel layer (104) may be GaN having alternating GaN and N layers and / or GaN having a nitrogen plane adjacent to the carbon plane of the substrate layer (102).

[0086] In one aspect of the transistor (100) of the present disclosure, the channel layer (104) may comprise nonpolar GaN. In one aspect, the channel layer (104) may comprise semipolar GaN. In one aspect, the channel layer (104) may comprise hot wall epitaxy. In one aspect, the channel layer (104) may comprise hot wall epitaxy having a thickness in the range of 0.15 microns to 0.25 microns, 0.2 microns to 0.3 microns, 0.25 microns to 0.35 microns, 0.3 microns to 0.35 microns, 0.35 microns to 0.4 microns, 0.4 microns to 0.45 microns, 0.45 microns to 0.5 microns, 0.5 microns to 0.55 microns, or 0.15 microns to 0.55 microns. The p-type material layer (106) can help prevent breakdown and material impurity problems. For example, without the p-type material layer (106), the transistor (100) may require impurities that do not discharge well. The p-type material layer (106) can be formed below the gate (114) and can extend in the direction of the source (110) and drain (112) of the device.

[0087] In terms of the transistor (100) of the present disclosure, the channel layer (104) can be designed to be of a high-purity type where the Fermi level is in the upper half of the band gap, which reduces the slow trapping effect generally observed in GaN HEMTs. In this regard, since traps below the Fermi level are always filled, slow transients can be prevented. In some aspects, the channel layer (104) can be as thin as possible to match achieving good crystalline quality. The applicant has already demonstrated a 0.4 μm layer of excellent quality.

[0088] In terms of the transistor (100) of the present disclosure, Al x In y Ga 1-x-y(Here, 0<=x<=1 and 0<=y<=1, x+y<=1) The nucleation layer (136) or channel layer (104) can be grown on the substrate layer (102) through an epitaxial crystal growth method such as MOCVD (Metalorganic Chemical Vapor Deposition), HVPE (Hydride Vapor Phase Epitaxy), or MBE (Molecular Beam Epitaxy). The formation of the nucleation layer (136) may vary depending on the material of the substrate layer (102).

[0089] In the side view of the transistor (100) of the present disclosure, the channel layer (104) may be formed by lateral epitaxial overgrowth (LEO). For example, LEO can improve the crystal quality of the GaN layer. When the semiconductor layer of the HEMT is epitaxial, the layer on which each epitaxial layer is grown can affect the characteristics of the device. For example, LEO can reduce the dislocation density of the epitaxial GaN layer.

[0090] Referring to the description in FIG. 8, the transistor (100) may include a second spacer layer (117) that can be formed on a spacer layer (116) and a gate (114). Referring to the description in FIG. 9, the transistor (100) may include a field plate (132). Referring to the description in FIG. 10, the transistor (100) may include a connection portion (154) to the field plate (132).

[0091] Figure 2 shows a cross-sectional view of the side of the transistor according to Figure 1.

[0092] In one aspect of the present disclosure, the p-type material layer (106) may not extend over the entire area of ​​the transistor (100). In this regard, the p-type material layer (106) may be optionally disposed as described herein, the p-type material layer (106) may be disposed over the entire length as described herein and optionally removed, and the p-type material layer (106) may be disposed over the entire length as described herein and optionally electrically neutralized. Accordingly, the specific configuration of the p-type material layer (106) described below includes any of these processes for producing the p-type material layer (106) having the operating configuration and placement as described below. That is, the length and / or size of the p-type material layer (106) does not include a portion that is partially electrically neutralized or partially etched. The length and / or size of the p-type material layer (106) may vary depending on the application of the transistor (100), requirements for the transistor (100), etc. Limiting the length of the p-type material layer (106) reduces the gate delay effect and drain delay effect, and prevents adverse effects on RF performance for specific transistor applications, etc.

[0093] As illustrated in FIG. 2, the p-type material layer (106) may exist in a limited area as described in more detail below. In some aspects, the p-type material layer (106) may exist in the gate-source region. In some aspects, the p-type material layer (106) may exist in the gate-source region and may also exist partially below the gate (114). In some aspects, the p-type material layer (106) may be placed at least partially below the gate (114) and / or source (110). In some aspects, the p-type material layer (106) may be placed at least partially below the gate (114) and / or may not be placed below the source (110).

[0094] In one aspect, the p-type material layer (106) may be positioned at least partially vertically along the y-axis below the gate (114) and may extend partially along the x-axis toward the source (110) and drain (112). In this aspect, no part of the p-type material layer (106) may be positioned vertically along the y-axis below the source (110); no part of the p-type material layer (106) may be positioned vertically along the y-axis below the source (110). In this aspect, a part of the substrate layer (102) may not have the p-type material layer (106) on the source side of the transistor (100), and a part of the substrate layer (102) may not have the p-type material layer (106) on the drain side of the transistor (100). In this regard, the source side of the transistor (100) is defined as the side of the transistor (100) extending from the gate (114) toward the source (110) and past the source (110) as shown in FIG. 2, and the drain side of the transistor (100) is defined as the side of the transistor (100) extending from the gate (114) toward the drain (112) and past the drain (112) as shown in FIG. 2.

[0095] In one aspect, the p-type material layer (106) may be positioned at least partially vertically along the y-axis below the gate (114) and may extend partially along the x-axis toward the source (110) and drain (112). In this aspect, only a portion of the p-type material layer (106) may be positioned vertically along the y-axis below the source (110), and no portion of the p-type material layer (106) may be positioned vertically along the y-axis below the source (110). In this aspect, a portion of the substrate layer (102) may not include the p-type material layer (106) positioned vertically along the y-axis below the source (110). In this aspect, a portion of the substrate layer (102) may not have the p-type material layer (106) on the source side of the transistor (100), and a portion of the substrate layer (102) may not have the p-type material layer (106) on the drain side of the transistor (100).

[0096] In one aspect, the p-type material layer (106) may be positioned at least partially vertically along the y-axis below the gate (114) and may extend partially along the x-axis toward the source (110) and drain (112). In this aspect, a portion of the p-type material layer (106) may be positioned entirely vertically along the y-axis below the source (110), and no portion of the p-type material layer (106) may be positioned vertically along the y-axis below the drain (112). In this aspect, a portion of the substrate layer (102) may not include the p-type material layer (106) positioned vertically along the y-axis past the source (110). In this aspect, a portion of the substrate layer (102) may not have the p-type material layer (106) on the source side of the transistor (100), and a portion of the substrate layer (102) may not have the p-type material layer (106) on the drain side of the transistor (100).

[0097] In one aspect, the p-type material layer (106) may be positioned vertically along the y-axis below the gate (114) and may extend partially along the x-axis toward the source (110) and drain (112). In this aspect, a portion of the p-type material layer (106) may be positioned vertically along the y-axis entirely below the source (110), and no portion of the p-type material layer (106) may be positioned vertically along the y-axis below the source (110). In this aspect, a portion of the substrate layer (102) may not include the p-type material layer (106) positioned vertically along the y-axis past the source (110). In this aspect, a portion of the substrate layer (102) may not have the p-type material layer (106) on the source side of the transistor (100), and a portion of the substrate layer (102) may not have the p-type material layer (106) on the drain side of the transistor (100).

[0098] Referring to FIG. 2, various dimensions of the transistor (100) component will be described to define the dimensions of the p-type material layer (106). The gate (114) may have a width (LG) along the lower surface of the gate (114) adjacent to the barrier layer (108) parallel to the X-axis. In particular, the width (LG) may extend from one lower corner of the gate (114) to another lower corner of the gate (114). The definition of the width (LG) is illustrated in FIG. 2. In some aspects, the width (LG) may have a length along the x-axis of 0.05 μm to 0.6 μm, 0.5 μm to 0.6 μm, 0.4 μm to 0.5 μm, 0.3 μm to 0.4 μm, 0.2 μm to 0.3 μm, 0.1 μm to 0.2 μm, or 0.1 μm to 0.05 μm. In some aspects, the width of the gate (114) above the lower surface may be larger than the width (LG) as shown in FIG. 2.

[0099] The distance from the gate (114) to the source (110) can be defined as the distance (LGS). In particular, the distance (LGS) can be defined as the distance from the lower corner of the gate (114) on the source side to the lower corner of the source (110) on the gate side. The definition of the distance (LGS) is illustrated in FIG. 2.

[0100] The distance from the gate (114) to the drain (112) can be defined as the distance (LGD). In particular, the distance (LGD) can be defined as the distance from the lower corner of the gate (114) on the drain side to the lower corner of the drain (112) on the gate side. The definition of the distance (LGD) is illustrated in FIG. 2.

[0101] In one aspect, the p-type material layer (106) may extend laterally along the x-axis by a distance (LGPS) from below the lower corner of the gate (114) on the source side toward the source (110). The definition of the distance (LGPS) is illustrated in FIG. 2. In some aspects, the distance (LGPS) may be a length along the x-axis of 1 μm to 6 μm, 5 μm to 6 μm, 4 μm to 5 μm, 3 μm to 4 μm, 2 μm to 3 μm, or 1 μm to 3 μm.

[0102] In one aspect, the p-type material layer (106) may extend laterally along the x-axis by a distance (LGPD) from below the lower corner of the gate (114) on the drain side toward the drain (112). In some aspects, the distance (LGPD) may be a length along the x-axis of 0.1 μm to 0.6 μm, 0.5 μm to 0.6 μm, 4 μm to 0.5 μm, 0.3 μm to 0.4 μm, 0.2 μm to 0.3 μm, or 0.1 μm to 0.3 μm.

[0103] Accordingly, the length of the p-type material layer (106) can be the sum of the distance (LGPD), width (LG), and distance (LGPS). In this regard, the length of the p-type material layer (106) reduces the gate delay effect and prevents adverse effects on RF performance for specific transistor applications, etc.

[0104] In one aspect, the length (LGPS) may be 100% to 700% of LG, 100% to 200% of LG, 200% to 300% of LG, 300% to 400% of LG, 400% to 500% of LG, 500% to 600% of LG, or 600% to 700% of LG.

[0105] In one aspect, the length (LG) is 10% to 180% of LGPD, 10% to 20% of LGPD, 20% to 30% of LGPD, 30% to 40% of LGPD, 40% to 50% of LGPD, 50% to 60% of LGPD, 60% to 70% of LGPD, 70% to 80% of LGPD, 80% to 90% of LGPD, 90% to 100% of LGPD, 100% to 110% of LGPD, 110% to 120% of LGPD, 110% to 130% of LGPD, 130% to 140% of LGPD, 140% to 150% of LGPD, 150% to 160% of LGPD, 160% to 170% of LGPD, or It can be 170% to 180% of LGPD.

[0106] In one aspect, the length (LGS) is 10% to 180% of LGPS, 10% to 20% of LGPS, 20% to 30% of LGPS, 30% to 40% of LGPS, 40% to 50% of LGPS, 50% to 60% of LGPS, 60% to 70% of LGPS, 70% to 80% of LGPS, 80% to 90% of LGPS, 90% to 100% of LGPS, 100% to 110% of LGPS, 110% to 120% of LGPS, 110% to 130% of LGPS, 130% to 140% of LGPS, 140% to 150% of LGPS, 150% to 160% of LGPS, 160% to 170% of LGPS, Or it may be 170% to 180% of LGPS.

[0107] In one aspect, the length (LG) is 10% to 180% of LGPD, 10% to 20% of LGPD, 20% to 30% of LGPD, 30% to 40% of LGPD, 40% to 50% of LGPD, 50% to 60% of LGPD, 60% to 70% of LGPD, 70% to 80% of LGPD, 80% to 90% of LGPD, 90% to 100% of LGPD, 100% to 110% of LGPD, 110% to 120% of LGPD, 110% to 130% of LGPD, 130% to 140% of LGPD, 140% to 150% of LGPD, 150% to 160% of LGPD, 160% to 170% of LGPD, Or it may be 170% to 180% of LGPD.

[0108] In one or more aspects, a portion of the source side of the substrate layer (102) may not have a p-type material layer (106). In one or more aspects, a portion of the drain side of the substrate layer (102) may not have a p-type material layer (106). In one or more aspects, a portion of the source side of the substrate layer (102) may not have a p-type material layer (106) and a portion of the drain side of the substrate layer may not have a p-type material layer (106). In one or more aspects, the p-type material layer (106) may be disposed below and along the length of the gate (114) and may extend toward the source (110) and drain (112).

[0109] In one or more aspects, the distance (LGD) may be the distance from the lower corner of the gate (114) on the drain (112) side to the lower corner of the drain (112) on the gate side, and the distance (LGS) may be the distance from the lower corner of the gate (114) on the source (110) side to the lower corner of the source (110) on the gate side, and the distance (LGD) may be greater than the distance (LGS). In one or more aspects, the distance (LGPS) may define the length of the portion of the p-type material layer (106) facing the source (110) from the lower corner of the gate (114) on the source (110) side, and the distance (LGPD) may define the length of the portion of the p-type material layer (106) facing the drain (112) from the lower corner of the gate (114) on the drain (112) side, and the distance (LGPS) may be equal to the distance (LGPD). In one or more aspects, the distance (LGPS) may define the length of the portion of the p-type material layer (106) extending from the lower corner of the gate (114) on the source (110) side toward the source (110), and the distance (LGPD) may define the length of the portion of the p-type material layer (106) extending from the lower corner of the gate (114) on the drain (112) side toward the drain (112), and the distance (LGPS) may be greater than the distance (LGPD). In one or more aspects, the distance (LGPS) may define the length of the portion of the p-type material layer (106) extending from the lower corner of the gate (114) on the source (110) side toward the source (110), and the distance (LGPD) may define the length of the portion of the p-type material layer (106) extending from the lower corner of the gate (114) on the drain (112) side toward the drain (112), and the distance (LGPD) may be greater than the distance (LGPS).

[0110] In one or more aspects, the p-type material layer (106) may extend toward the source (110) but may not overlap perpendicularly with the source (110). In one or more aspects, the p-type material layer (106) may overlap perpendicularly with the source (110). In one or more aspects, the p-type material layer (106) may extend toward the drain (112) but may not overlap perpendicularly with the drain (112). In one or more aspects, the p-type material layer (106) may be electrically connected to the gate (114). In one or more aspects, the gate (114) may be electrically connected to any external circuit or voltage. In one or more aspects, the p-type material layer (106) may not have a direct electrical connection. In one or more aspects, the p-type material layer (106) may be electrically connected to the source (110).

[0111] In some aspects, a portion of the voltage from the drain (112) to the source (110) may drop in the region of the p-type material layer (106). This may cause the lateral channel to be depleted. Lateral depletion can reduce the lateral field and increase the breakdown voltage. Alternatively, a more compact structure can be obtained for the required breakdown voltage. The p-type material layer (106) can eliminate the need to have C or Fe doping in the buffer required to maintain the applied drain voltage. Removing C and Fe reduces the current drop under operating conditions (no trapping). Additionally, in some aspects, the p-type material layer (106) can support the field.

[0112] In some aspects, the p-type material layer (106) may be configured to have various doping and / or injection profiles perpendicular to the surface. In some aspects, the p-type material layer (106) may be configured to have various profiles perpendicular to the surface extending from the cross-sectional view of the drawing. The profiles may be configured to achieve a desired breakdown voltage, device size, switching time, etc.

[0113] Figure 3 shows a cross-sectional view of the side of the transistor according to Figure 1.

[0114] In one aspect, the p-type material layer (106) may not extend over the entire area of ​​the substrate layer (102) as indicated by the arrow LENGTH P in FIG. 3. In this regard, the p-type material layer (106) may be optionally positioned as described in detail below, the p-type material layer (106) may be positioned over its entire length and optionally removed as described in detail below, and the p-type material layer (106) may be positioned over its entire length and optionally electrically neutralized as described in detail below. Accordingly, the specific configuration of the p-type material layer (106) described below includes any of these configurations that cause the p-type material layer (106) to have the operational configuration and placement as described below. That is, the length and / or size of the p-type material layer (106) does not include a portion that is partially electrically neutralized or partially etched. The length and / or size of the p-type material layer (106) may vary depending on the application of the transistor (100), requirements for the transistor (100), etc.

[0115] Referring to aspects further described below, the p-type material layer (106) may be extended horizontally along the X-axis parallel to the arrow LENGTH P. Furthermore, the p-type material layer (106) may be extended horizontally parallel to the arrow LENGTH P to a point defined by a line perpendicular to the arrow LENGTH P (parallel to the y-axis) and may be extended through the component of the transistor (100) as illustrated.

[0116] In one aspect of the present disclosure, the p-type material layer (106) may extend laterally from at least below the source (110) to a position below the first edge (124) of the gate (114). In particular, the first edge (124) may be an edge of the gate (114) on the gate (114) side adjacent to the drain (112) and which may be the lowest surface of the gate (114).

[0117] In a specific aspect of the present disclosure, the p-type material layer (106) may extend to a point within about 0 to about 0.7 μm of the first edge (124) of the gate (114). In a specific aspect of the present disclosure, the p-type material layer (106) may extend to a point within about 0 to about 0.5 μm of the first edge (124) of the gate (114). In a specific aspect of the present disclosure, the p-type material layer (106) may extend to a point within about 0 to about 0.3 μm of the first edge (124) of the gate (114).

[0118] In one aspect of the present disclosure, the p-type material layer (106) may extend laterally from at least below the source (110) to a position below the second edge (122) of the gate (114). In particular, the second edge (122) may be an edge of the gate (114) on the gate (114) side adjacent to the source (110) and which may be the lowest surface of the gate (114).

[0119] In a specific aspect of the present disclosure, the p-type material layer (106) may extend to a point within about 0 to about 0.7 μm of the second edge (122) of the gate (114). In a specific aspect of the present disclosure, the p-type material layer (106) may extend to a point within about 0 to about 0.5 μm of the second edge (122) of the gate (114). In a specific aspect of the present disclosure, the p-type material layer (106) may extend to a point within about 0 to about 0.3 μm of the second edge (122) of the gate (114).

[0120] In another aspect, the length (LENGTH P) of the p-type material layer (106) may also be shown in relation to the position and / or length of other components based on the length (SD) as illustrated in FIG. 8. In this case, the length (SD) may be the length between the edge (142) of the source (110) toward the edge (144) of the drain (112) as illustrated in FIG. 8. In particular, the edge (142) may be defined as an edge or surface on the source (110) parallel to the Y-axis on the source (110) side opposite the gate (114), and the edge (114) may be defined as an edge or surface on the drain (112) parallel to the Y-axis on the drain (112) side opposite the gate (114).

[0121] In one aspect, the length of the p-type material layer (106) may be extended to 10% to 20% of the SD length, which means that the p-type material layer (106) may be extended to 10% to 20% of the drain (112) past the edge (142) of the source (110). In one aspect, the length of the p-type material layer (106) may be extended to 20% to 30% of the SD length, which means that the p-type material layer (106) may be extended to 20% to 30% of the drain (112) past the edge (142) of the source (110). In one aspect, the length of the p-type material layer (106) may be extended from 30% to 40% of the SD length, which means that the p-type material layer (106) may be extended from 30% to 40% toward the drain (112) past the edge (142) of the source (110). In one aspect, the length of the p-type material layer (106) may be extended from 40% to 50% of the SD length, which means that the p-type material layer (106) may be extended from 40% to 50% toward the drain (112) past the edge (142) of the source (110). In one aspect, the length of the p-type material layer (106) may be extended to 50% to 60% of the SD length, which means that the p-type material layer (106) may be extended to 50% to 60% of the drain (112) past the edge (142) of the source (110). In one aspect, the length of the p-type material layer (106) may be extended to 60% to 70% of the SD length, which means that the p-type material layer (106) may be extended to 60% to 70% of the drain (112) past the edge (142) of the source (110). In one aspect, the length of the p-type material layer (106) can be extended to 70% to 80% of the SD length, which means that the p-type material layer (106) can be extended to 70% to 80% of the drain (112) past the edge (142) of the source (110).

[0122] FIG. 4 illustrates a semiconductor device that may include a plurality of unit cell transistors according to an aspect of the present disclosure.

[0123] As illustrated in FIG. 4, aspects of the present disclosure may include a semiconductor device (400) that may include a plurality of transistors (100). In particular, the transistor (100) may be one of a plurality of unit cells (430) implemented in the semiconductor device (400).

[0124] In particular, FIG. 4 illustrates a transistor (100) that may include any one or more aspects of the disclosure described herein. In particular, the transistor (100) of FIG. 4 may include a p-type material layer (106) as described above. In this regard, the transistor (100) of FIG. 4 implements a length of the p-type material layer (106) as described herein that reduces the gate delay effect, and the transistor (100) of FIG. 4 implements a back barrier layer (120) as described herein that reduces the gate delay effect.

[0125] The semiconductor device (400) may include a gate bus (402) that can be connected to a plurality of gate fingers (406) that can be extended parallel to a first direction (e.g., the Z direction indicated in FIG. 4) that are connected to or form a part of the gate (114). A source bus (410) may be connected to a plurality of parallel source contacts (416) that are connected to or form a part of the source (110). In some aspects, the source bus (410) may be connected to a ground voltage node at the bottom of the semiconductor device (400). A drain bus (420) may be connected to a portion of the drain (112) or to a plurality of drain contacts (426) that form a part of the drain (112).

[0126] As illustrated in FIG. 4, each gate finger (406) may extend along the Z direction between an adjacent pair of source contacts (416) and drain contacts (426). The semiconductor device (400) may include a plurality of unit cells (430), wherein each of the plurality of unit cells (430) includes an implementation of a transistor (100). One of the plurality of unit cells (430) is illustrated by a dashed box in FIG. 4 and includes a gate finger (406) extending between adjacent cells of source contacts (416) and drain contacts (426).

[0127] "Gate width" refers to the distance at which the gate finger (406) overlaps with the associated source contact (416) and drain contact (426) in the Z direction. That is, the "width" of the gate finger (406) refers to the dimension (distance along the Z direction) of the gate finger (406) that extends parallel and adjacently to the implementation of the source contact (416) and drain contact (426). Each of the plurality of unit cells (430) may share one of the source contact (416) and / or drain contact (426) with one or more adjacent units of the plurality of unit cells (430). Although a specific number of the plurality of unit cells (430) is shown in FIG. 4, it will be understood that the semiconductor device (400) may include more or fewer units of the plurality of unit cells (430).

[0128] Figure 5 is a schematic cross-sectional view taken along the VV line of Figure 4.

[0129] Referring to FIG. 5, the semiconductor device (400) may include a semiconductor structure (440) including a substrate layer (102), a back barrier layer (120), a channel layer (104), a barrier layer (108), etc., as described herein. A source contact (416) and a drain contact (426) may be on the barrier layer (108) as described herein. A gate finger (406) may be on the substrate layer (102) between the source contact (416) and the drain contact (426) as described herein. Although the gate finger (406), the source contact (416), and the drain contact (426) are all schematically depicted in FIG. 4 and FIG. 5 as having similar "dimensions," it will be understood that each may have different shapes and dimensions consistent with the present disclosure.

[0130] Figure 6 illustrates the band diagram of the disclosed transistor compared to a typical transistor at a specific operating value.

[0131] In particular, FIG. 6 illustrates a band diagram (600) of the transistor (100) of the present disclosure and a HEMT transistor implemented without a back barrier layer (120), plotting various major electron energy levels as a function of spatial dimensions having zero gate voltage and zero drain voltage. The vertical axis of the band diagram represents electron energy, and the horizontal axis relates to the spatial dimensions of two different transistors.

[0132] More specifically, the band diagram (600) includes an Ec curve (602) that implements the transistor (100) disclosed herein with a back barrier layer (120) and a p-type material layer (106) placed below the gate, and the band diagram (600) includes an Ec curve (652) that implements a HEMT transistor implemented without the back barrier layer (120).

[0133] Additionally, the band diagram (600) includes an Ev curve (604) for implementing a transistor (100) as disclosed herein, together with a back barrier layer (120) and a p-type material layer (106) placed below the gate, and the band diagram (600) includes an Ev curve (654) for implementing a HEMT transistor without the back barrier layer (120).

[0134] Referring to FIG. 6, the Ec curve (602) illustrates the negative charge lift-up of the Ec curve (602) of the transistor (100) of the present disclosure between the channel layer (104) and the back barrier layer (120). In particular, the Ec curve (602) illustrates a negative charge lift-up to constrain the 2DEG and partially deplete the 2DEG. The Ec curve (652) for implementing a HEMT transistor without the back barrier layer (120) includes a minimum negative charge lift-up.

[0135] Referring further to FIG. 6, the Ev curve (604) illustrates the negative charge lift-up of the Ev curve (604) of the transistor (100) of the present disclosure between the channel layer (104) and the rear barrier layer. The Ev curve (654) for implementing a HEMT transistor without a rear barrier layer (120) includes a minimum negative charge lift-up.

[0136] Figure 7 illustrates the band diagram of the disclosed transistor compared to a typical transistor at a specific operating value.

[0137] In particular, FIG. 7 illustrates a band diagram (700) of the transistor (100) of the present disclosure and a HEMT transistor implemented without a back barrier layer (120), plotting various major electron energy levels as a function of spatial dimensions with a gate voltage of -15 V and a drain voltage of 10 V. The vertical axis of the band diagram represents the electron energy, and the horizontal axis relates to the spatial dimensions of the two different transistors.

[0138] More specifically, the band diagram (700) includes an Ec curve (702) that implements the transistor (100) disclosed herein with a back barrier layer (120) and a p-type material layer (106) placed below the gate, and the band diagram (700) includes an Ec curve (752) that implements a HEMT transistor implemented without the back barrier layer (120).

[0139] Additionally, the band diagram (700) includes an Ev curve (704) for implementing a transistor (100) as disclosed herein, together with a back barrier layer (120) and a p-type material layer (106) placed below the gate, and the band diagram (700) includes an Ev curve (754) for implementing a HEMT transistor without the back barrier layer (120).

[0140] Referring to FIG. 7, the Ec curve (702) illustrates a field near the interface between the channel layer (104) and the back barrier layer (120) that prevents electrons from entering deeper into the back barrier layer (120) of the transistor. The Ec curve (752) for a HEMT transistor implemented without the back barrier layer (120) does not contain such a field. Likewise, the Ev curve (704) illustrates a field near the interface between the channel layer (104) and the back barrier layer (120) that prevents electrons from entering deeper into the back barrier layer (120) of the transistor (100), and the Ev curve (754) for a HEMT transistor implemented without the back barrier layer (120) does not contain such a field.

[0141] Additionally, in a transistor with a conventional buffer, a band such as the Ec curve (752) on the Ev curve (754) bends downward at a large negative voltage. This allows electrons to flow deep into the buffer and become trapped. In the disclosed embodiment of a transistor (100) having a p-type material layer (106) and a back barrier layer (120), there is a flat or slightly upward band of the Ec curve (702) and Ev curve (704) that bends near the channel layer (104). This prevents electron injection and trapping in the buffer of the transistor (100).

[0142] FIG. 8 illustrates a cross-sectional view of another aspect of a transistor according to the present disclosure.

[0143] The transistor (100) of FIG. 8 may be structured to be consistent with the transistor of FIG. 1, the transistor of FIG. 2, and / or the transistor of FIG. 3, and may include any one or more aspects described herein. In particular, the transistor (100) of FIG. 8 combined with the p-type material layer (106) and the back barrier layer (120) as disclosed, and the associated structure and / or the associated process thereof may provide a systematic approach to reducing delay. More specifically, the transistor (100) of the present disclosure may be implemented with the p-type material layer (106) and / or the process thereof as a drain delay reduction structure and / or process for reducing the drain delay effect in the transistor (100), and the transistor (100) of the present disclosure may be implemented with the back barrier layer (120) and / or the process thereof as a gate delay reduction structure and / or process for reducing the gate delay effect in the transistor (100).

[0144] FIG. 8 further illustrates an implementation of a second spacer layer (117). The second spacer layer (117) may be provided below the gate (114) and / or above the spacer layer (116). The second spacer layer (117) may be a passivation layer composed of SiN, AlO, SiO, SiO2, AlN, etc., or a combination comprising multiple layers thereof.

[0145] In one aspect, the second spacer layer (117) is a passivation layer made of SiN. In one aspect, the second spacer layer (117) may be deposited using MOCVD, plasma chemical vapor deposition (CVD), hot filament CVD, or sputtering. In one aspect, the second spacer layer (117) may include the deposition of Si3N4. In one aspect, the second spacer layer (117) forms an insulating layer. In one aspect, the second spacer layer (117) forms an insulator. In one aspect, the second spacer layer (117) may be a dielectric. In one aspect, the second spacer layer (117) may be provided on the spacer layer (116). In one aspect, the second spacer layer (117) may include a non-conductive material such as a dielectric. In one aspect, the second spacer layer (117) may include a plurality of different dielectric layers or a combination of dielectric layers. In one aspect, the second spacer layer (117) may have various thicknesses, and a suitable thickness range is approximately 0.05 to 2 microns. In one aspect, the second spacer layer (117) may comprise a material such as a group 3 nitride material having different group 3 elements, such as an alloy of Al, Ga, or In, and a suitable spacer layer material is Al x In y Ga 1-x-y (Here, 0<=x<=1 and 0<=y<=1, x+y<=1).

[0146] FIG. 9 illustrates a cross-sectional view of another aspect of a transistor according to the present disclosure.

[0147] The transistor (100) of FIG. 9 may be structured to be consistent with the transistor of FIG. 1, the transistor of FIG. 2, and / or the transistor of FIG. 3, and may include any one or more aspects described herein. In particular, the transistor (100) of FIG. 9 combined with the p-type material layer (106) and the back barrier layer (120) as disclosed, and the associated structure and / or the associated process thereof may provide a systematic approach to reducing delay. More specifically, the transistor (100) of the present disclosure may be implemented with the p-type material layer (106) and / or the process thereof as a drain delay reduction structure and / or process for reducing the drain delay effect of the transistor (100), and the transistor (100) of the present disclosure may be implemented with the back barrier layer (120) and / or the process thereof as a gate delay reduction structure and / or process for reducing the gate delay effect in the transistor (100).

[0148] FIG. 9 further illustrates an implementation of the field plate (132). In one aspect, the field plate (132) may be placed on a second spacer layer (117) between the gate (114) and the drain (112). In one aspect, the field plate (132) may be deposited on the second spacer layer (117) between the gate (114) and the drain (112). In one aspect, the field plate (132) may be electrically connected to one or more other components of the transistor (100). In one aspect, the field plate (132) may not be electrically connected to any other component of the transistor (100). In some aspects, the field plate (132) may be adjacent to the gate (114), and the second spacer layer (117) of dielectric material may be at least partially included over the gate (114) to isolate the gate (114) from the field plate (132). In some aspects, the field plate (132) may overlap with the gate (114), and the second space layer (117) of the dielectric material may be at least partially included on the gate (114).

[0149] The field plate (132) may extend from the edge of the gate (114) at different distances, and a suitable distance range is approximately 0.1 to 2 microns. In some aspects, the field plate (132) may comprise various conductive materials having a suitable material, which is a metal or a combination of metals deposited using a standard metallization method. In one aspect, the field plate (132) may comprise titanium, gold, nickel, titanium / gold, nickel / gold, etc.

[0150] In one aspect, the field plate (132) may be formed on a second spacer layer (117) between the gate (114) and the drain (112), and the field plate (132) is close to the gate (114) but does not overlap with the gate (114). In one aspect, the space between the gate (114) and the field plate (132) may be wide enough to isolate the gate (114) from the field plate (132), while being small enough to maximize the electric field effect provided by the field plate (132).

[0151] In certain aspects, the field plate (132) can reduce the maximum operating electric field of the transistor (100). In certain aspects, the field plate (132) can reduce the maximum operating electric field of the transistor (100) and increase the breakdown voltage of the transistor (100). In certain aspects, the field plate (132) can reduce the maximum operating electric field of the transistor (100) and reduce the trapping of the transistor (100). In certain aspects, the field plate (132) can reduce the maximum operating electric field of the transistor (100) and reduce the leakage current of the transistor (100).

[0152] For example, in another aspect, the spacer layer (116) is formed on the barrier layer (108) and the gate (114). In this aspect, the field plate (132) may be formed directly on the spacer layer (116). Other multi-field plate configurations are also possible in which the field plate (132) overlaps with or does not overlap with the gate (114) and / or the multi-field plate (132) used.

[0153] FIG. 10 illustrates a cross-sectional view of another aspect of a transistor according to the present disclosure.

[0154] The transistor (100) of FIG. 10 may be structured to be consistent with the transistor of FIG. 1, the transistor of FIG. 2, and / or the transistor of FIG. 3, and may include any one or more aspects described herein. In particular, the transistor (100) of FIG. 10 combined with the p-type material layer (106) and the back barrier layer (120) as disclosed, and the associated structure and / or the associated process thereof, may provide a systematic approach to reducing delay. More specifically, the transistor (100) of the present disclosure may be implemented with the p-type material layer (106) and / or the process thereof as a drain delay reduction structure and / or process for reducing the drain delay effect in the transistor (100), and the transistor (100) of the present disclosure may be implemented with the back barrier layer (120) and / or the process thereof as a gate delay reduction structure and / or process for reducing the gate delay effect in the transistor (100).

[0155] In one aspect illustrated in FIG. 10, the connection (154) may be formed on a spacer layer (116) and / or a second spacer layer (117) so as to extend between the source (110) and the field plate (132). In some aspects, the connection (154) may comprise a suitable material which is a conductive material, various conductive materials, a metal deposited using a standard metallization method, or a combination of metals. In one aspect, the material may comprise one or more of titanium, gold, nickel, etc.

[0156] In particular, the transistor (100) of FIG. 10 illustrates a field plate (132) connected to a source (110) via a connection (154) (source-field plate interconnect). Additionally or otherwise, the field plate (132) may be connected to a gate (114) via a connection (gate-field plate interconnect (not shown)). In one aspect, the connection (154) may be formed on a spacer layer (116) and / or a second spacer layer (117) so as to extend between the field plate (132) and the source (110). In one aspect, the connection (154) may be formed together with the field plate (132) during the same manufacturing step. In one aspect, a plurality of connections (154) and / or a plurality of gate-field plate interconnects may be used. In one aspect, a plurality of field plates (132) may be used. In one aspect, a plurality of field plates (132) may be used, and each of the plurality of field plates (132) may be stacked with a dielectric material in between. In some aspects, the connection (154) and / or the plurality of gate-field plate interconnections may comprise a suitable material comprising a conductive material, various conductive materials, a metal or a combination of metals deposited using a standard metallization method. In one aspect, the material may comprise one or more of titanium, gold, nickel, etc.

[0157] In one aspect, the gate-field plate interconnect may be formed on a spacer layer (116) and / or a second spacer layer (117) so as to extend between the gate (114) and the field plate (132). In some aspects, the gate-field plate interconnect may comprise a suitable material which is a conductive material, various conductive materials, a metal deposited using a standard metallization method, or a combination of metals. In one aspect, the material may comprise one or more of titanium, gold, nickel, etc.

[0158] In one aspect of the transistor (100) described herein, the gate (114) may be formed of platinum (Pt), nickel (Ni) and / or gold (Au), but other metals known to those skilled in the art may be used to achieve the Schottky effect. In one aspect, the gate (114) may include a Schottky gate contact that may have a three-layer structure. This structure may be advantageous because some materials have high adhesion. In one aspect, the gate (114) may further include an overlayer of a highly conductive metal. In one aspect, the gate (114) may be configured as a T-shaped gate.

[0159] In one aspect of the transistor (100) described herein, one or more metal overlays may be provided over one or more of the source (110), drain (112), and gate (114). The overlays may be gold, silver (Ag), Al, Pt, Ti, Si, Ni, Al, and / or copper (Cu). Other suitable highly conductive metals may also be used for the overlays. In another aspect, the source (110), drain (112), and gate (114) may comprise gold, silver (Ag), Al, Pt, Ti, Si, Ni, Al, and / or copper (Cu). Other suitable highly conductive metals may also be used.

[0160] In one aspect of the transistor (100) described herein, a second channel layer may be deposited or grown on a first embodiment of the channel layer (104) on the side of the first embodiment of the channel layer (104) opposite the substrate layer (102). In one aspect, the second channel layer may be formed directly on the first embodiment of the channel layer (104). In one aspect, the second channel layer may be a high-purity material such as gallium nitride (GaN), AlN, etc. In one aspect, the second channel layer may be high-purity GaN. In one aspect, the second channel layer may be high-purity AlN. The second channel layer may be a p-type material or an n-type material. In another aspect, the second channel layer may not be doped.

[0161] In terms of the transistor (100) of the present disclosure, the contacts of the source (110), gate (114) and / or drain (112) may comprise Al, Ti, Si, Ni and / or Pt. In this respect, utilizing the same material may be advantageous in that manufacturing is easier, simpler, and / or less expensive. In other respects, the materials of the contacts of the source (110), gate (114) and drain (112) may differ.

[0162] FIG. 11 illustrates a cross-sectional view of another aspect of a transistor according to the present disclosure.

[0163] The transistor (100) of FIG. 11 may be structured to be consistent with the transistor of FIG. 1, the transistor of FIG. 2, and / or the transistor of FIG. 3, and may include any one or more aspects described herein. In particular, the transistor (100) of FIG. 11 combined with the p-type material layer (106) and the back barrier layer (120) as disclosed, and the associated structure and / or the associated process thereof, may provide a systematic approach to reducing delay. More specifically, the transistor (100) of the present disclosure may be implemented with the p-type material layer (106) and / or the process thereof as a drain delay reduction structure and / or process for reducing the drain delay effect of the transistor (100), and the transistor (100) of the present disclosure may be implemented with the back barrier layer (120) and / or the process thereof as a gate delay reduction structure and / or process for reducing the gate delay effect in the transistor (100).

[0164] In various aspects of the present disclosure, the p-type material layer (106) of the transistor (100) may be embedded within the substrate layer (102) and otherwise may not be electrically connected to any part of the transistor (100). As illustrated in FIG. 11, in one aspect, the transistor (100) may include a p-type material contact (118) that can be electrically connected to receive an external signal, bias, etc. The p-type material contact (118) may be electrically connected and disposed in the substrate layer (102), the p-type material layer (106), the substrate layer (102), the channel layer (104), the barrier layer (108), etc. The p-type material contact (118) may be formed in a recess (119) of the substrate layer (102), the p-type material layer (106), the substrate layer (102), the channel layer (104), the barrier layer (108), etc. The recess (119) may extend downward to the p-type material layer (106) so that a p-type material contact (118) can be formed. The recess (119) may be formed by etching, or a material defining the recess (119) may be used. The material may be removed after the recess (119) is formed.

[0165] In particular, the recess (119) may expose the p-type material layer (106) on the opposite side of the substrate layer (102) by removing any material on the p-type material layer (106) within a portion of the area associated with the source (110). In another aspect of the disclosure, to create a place for a p-type material contact (118), the recess (119) may be created by removing at least a portion of the substrate layer (102), the p-type material layer (106), the substrate layer (102), the channel layer (104), the barrier layer (108), etc.

[0166] In a specific embodiment, the source (110) may be electrically connected to the p-type material contact (118) through the connection portion (138). In a specific embodiment, the field plate (132) may be electrically connected to the source (110) through the connection portion (154). In a specific embodiment, the field plate (132) may be connected to the source (110), and the source (110) may be connected to the p-type material contact (118) through the connection portion (138).

[0167] In a specific embodiment, the gate (114) may be electrically connected to the p-type material contact (118) through a connection (not shown). In a specific embodiment, the field plate (132) may be electrically connected to the gate (114) through a connection. In a specific embodiment, the field plate (132) may be connected to the gate (114), and the gate (114) may be connected to the p-type material contact (118) through a connection.

[0168] FIG. 11 is intended to broadly illustrate various embodiments of the present invention (e.g., various p-layer and / or field plate configurations), but for clarity, not all embodiments are explicitly illustrated. It should be understood that the rear barrier layer (120) structure of the present invention can be utilized with various p-type material layer (106) structures as described herein. In certain embodiments, the p-type material layer (106) structure may be electrically connected to a separate bias voltage / control signal, electrically connected to a source (110), electrically connected to a gate (114), or may not be electrically connected to a source (110), a gate (114), or a separate bias / control signal. Such electrical connections may be made through vias of the epitaxial material and / or electrical connections at the exterior and / or edges of the epitaxial material. For example, vias may be structured within a recess (119). The p-type material layer (106) may be formed or structured in any other variation described herein. Depending on the embodiment, various field plate (132) configurations are possible. For example, the field plate (132) may be integral with the gate (114), and a single or multiple field plates (132) may have or not have a dielectric spacer layer interposed between the field plates (132). The field plate (132) may be vertically overlapped with the gate (114) or the lower field plate (132) or may not be vertically overlapped. The field plate (132) may be electrically connected to the gate (114) or the source (110) or one or more field plates (132) connected to the gate (114), one or more field plates (132) connected to the source (110), and / or one or more field plates (132) not connected to either the source (110) or the gate (114).

[0169] FIG. 12 illustrates a process for manufacturing a transistor according to the present disclosure.

[0170] In particular, FIG. 12 illustrates an exemplary process (500) for manufacturing a transistor (100) of the present disclosure. The process (500) is merely exemplary and may be modified according to various aspects disclosed herein. In particular, the process (500) may include any one or more aspects of the disclosure described herein.

[0171] In particular, the process (500) may include the step of manufacturing a p-type material layer (106) and a back barrier layer (120) as described above. In this regard, the process (500) implements the p-type material layer (106) and the back barrier layer (120) as disclosed, their associated structures, and / or their associated processes, which can provide a systematic approach to reducing delay. More specifically, the process (500) may implement the p-type material layer (106) as a drain delay reduction structure and / or process for reducing the drain delay effect in the transistor (100), and the process (500) of the present disclosure may implement the back barrier layer (120) as a gate delay reduction structure and / or process for reducing the gate delay effect in the transistor (100).

[0172] The process (500) may begin at step 502 by forming a substrate layer (102). The substrate layer (102) may be formed according to the present disclosure. For example, the substrate layer (102) may be made of silicon carbide (SiC). In some aspects, the substrate layer (102) may be a semi-insulating SiC substrate, a p-type substrate, an n-type substrate, etc. In some aspects, the substrate layer (102) may be very lightly doped. In one aspect, the background impurity level may be low. In one aspect, the background impurity level is 1E15 / cm² 3The substrate layer (102) may be formed of SiC selected from the group including 6H, 4H, 15R, 3C SiC, etc. In another aspect, the substrate layer (102) may be GaAs, GaN, or other materials suitable for the applications described herein. In another aspect, the substrate layer (102) may include sapphire, spinel, ZnO, silicon, or any other material capable of supporting the growth of group 3 nitride materials.

[0173] The process (500) may include a step 504 of forming a p-type material layer (106). The p-type material layer (106) may be formed as described in the present disclosure. This may include a step of implanting Al into the substrate layer (102) to form the p-type material layer (106) on the substrate layer (102). For example, the p-type material layer (106) may be formed by ion implantation and annealing of Al. In one aspect, the p-type material layer (106) may be formed by implantation and annealing of Al prior to the growth of any GaN layer. In one aspect, the ion implementation may utilize a channeling implant. In one aspect, the channeling implant may include a step of aligning an ion beam to the substrate layer (102). Alignment of the ion beam may increase the implantation efficiency. In some aspects, the process (500) may further include the step of injecting Al into the substrate layer (102) to form a p-type material layer (106) within the substrate layer (102). Afterward, the substrate layer (102) may be annealed as defined herein. In one aspect, the p-type material layer (106) has an injection energy E1=100 keV and a capacitance 1E13 cm at 25°C. 2 to 4H-SiC injected under channeling conditions 27 It can be formed by ion implanting Al. In one aspect, a p-type material layer (106) is formed at 25°C with an implantation energy E2=300 keV and a capacitance 1E13 cm. 2 to 4H-SiC injected under channeling conditions 27It can be formed by ion implanting Al. However, other implantation energies and capacities are also considered.

[0174] The process (500) may include step 506 of forming a back barrier layer (120) on a substrate layer (102) and / or a nucleation layer (136). The back barrier layer (120) may be grown or deposited on the substrate layer (102) and / or the nucleation layer (136) as described in the present disclosure. In one aspect, the nucleation layer (136) may be formed on the substrate layer (102), and the back barrier layer (120) may be formed on the nucleation layer (136) in step 506.

[0175] Step 506 of forming a back barrier layer (120) may include forming the back barrier layer (120) to limit and / or avoid impurities such as silicon, oxygen, carbon, etc., in order to reduce gate delay. In particular, impurities provide trapping, leakage, etc. More specifically, aspects of the present disclosure may implement a back barrier layer (120) having a low background impurity level. In one aspect, the present disclosure may implement AlGaN for the back barrier layer (120) having a low background impurity level. In this regard, it has been found that impurities form a complex having a potential such as a point defect acting as a deep trap level. Step 506 of forming the back barrier layer (120) may be configured to provide a sharp interface to the channel layer (104). Such an interface may function as a barrier to electrons. In aspects of the transistor (100) of the present disclosure, the back barrier layer (120) may be a grade layer. In one aspect, the back barrier layer (120) may be a stepped grade layer. In one aspect, the rear barrier layer (120) may be multiple layers.

[0176] Step 506 of forming a back barrier layer (120) may include forming a back barrier layer (120) having an AlGaN buffer layer with a low Al concentration to provide a barrier that reduces electron injection into the buffer layer. In this regard, the barrier that reduces electron injection into the buffer layer may be a gate delay reduction structure, a gate delay removal structure, etc. For example, the back barrier layer (120) may be implemented with AlGaN with an Al concentration of about 4% to provide a barrier that reduces electron injection into the buffer. In this regard, about may be within 0.5%, 1%, 1.5%, or 2%. In a specific aspect, the back barrier layer (120) may be implemented with AlGaN with an Al concentration of 1% to 6%, 1% to 1.5%, 1.5% to 2%, 2% to 2.5%, 2.5% to 3%, 3% to 3.5%, 3.5% to 4%, 3.5% to 4.5%, 3.8% to 4.2%, 4% to 4.5%, 4.5% to 5%, 5% to 5.5%, or 5.5% to 6% to provide a barrier that reduces electron injection into a buffer, a gate delay reduction structure, a gate delay removal structure, etc.

[0177] The process (500) may include step 508 of forming a channel layer (104) on a back barrier layer (120). The channel layer (104) may be grown or deposited on the back barrier layer (120) as described in the present disclosure. In one aspect, the channel layer (104) may be GaN.

[0178] Additionally, as part of step 510 during the process (500), a barrier layer (108) may be formed on the channel layer (104). The barrier layer (108) may be formed as described in the present disclosure. For example, the barrier layer (108) may be an n-type conductive layer or may not be doped. In one aspect, the barrier layer (108) may be AlGaN.

[0179] Additionally, during the process (500), as part of step 512, a recess (119) may be created by removing at least a portion of the barrier layer (108), at least a portion of the channel layer (104), at least a portion of the rear barrier layer (120), etc., to create a place for the p-type material layer (106) and the p-type material contact (118). The process (500) for forming the connection (154) removes any material on the p-type material layer (106) and exposes the p-type material layer (106) on the opposite side of the substrate layer (102). In another aspect of the present disclosure, to create a place for the p-type material layer (106) and the p-type material contact (118), the connection (138) may be created by removing at least a portion of the barrier layer (108), at least a portion of the channel layer (104) and / or the rear barrier layer (120). The recess formation process can expose the p-type material layer (106) on the opposite side of the substrate layer (102) by removing any material on the p-type material layer (106) within a portion of the area associated with the source (110).

[0180] Additionally, as part of step 514 during the process (500), the source (110) may be placed on the barrier layer (108). The source (110) may be a resistant contact of a suitable material that can be annealed. For example, the source (110) may be annealed at a temperature of about 500°C to about 800°C for about 2 minutes. However, other times and temperatures may also be utilized. For example, a time of about 30 seconds to about 10 minutes may be allowed. In some aspects, the source (110) may comprise Al, Ti, Si, Ni, and / or Pt. In one aspect, the region (164) below the source (110), which is an N+ material, may be formed within the barrier layer (108). In one aspect, the region (164) below the drain (112) may be Si-doped.

[0181] Additionally, as part of step 514 during the process (500), the drain (112) may be placed on the barrier layer (108). Like the source (110), the drain (112) may be a resistive contact of Ni or other suitable material and may also be annealed in a similar manner. In one aspect, n+ injection may be used with the barrier layer (108) and the contact is made for injection. In one aspect, the region (164) below the drain (112), which is an N+ material, may be formed within the barrier layer (108). In one aspect, the region (164) below the drain (112) may be Si-doped.

[0182] Additionally, as part of step 514 during the process (500), a gate (114) may be placed on a barrier layer (108) between the source (110) and the drain (112). A layer of Ni, Pt, AU, etc. forms the gate (114) by evaporative deposition or other techniques. Then, the gate structure may be completed by the deposition of Pt and Au or other suitable materials. In some aspects, the contacts of the gate (114) may include Al, Ti, Si, Ni, and / or Pt.

[0183] Additionally, as part of step 514 during the process (500), a spacer layer (116) may be formed. The spacer layer (116) may be a passivation layer such as SiN, AlO, SiO, SiO2, AlN, etc., or a combination including multiple layers thereof, and may be deposited on the exposed surface of the barrier layer (108).

[0184] The source (110) and drain (112) electrodes can form a resistive contact to allow current to flow between the source (110) and drain (112) electrodes through a two-dimensional electron gas (2DEG) induced at the heterogeneous interface (152) between the channel layer (104) and the barrier layer (108) when the gate (114) electrode is biased to an appropriate level. In one aspect, the source (110) can be electrically connected to the barrier layer (108), the drain (112) can be electrically connected to the barrier layer (108), and the gate (114) can be electrically connected to the barrier layer (108) so that current can flow between the source (110) and the drain (112) through a two-dimensional electron gas (2DEG) induced at the heterogeneous interface (152) between the channel layer (104) and the barrier layer (108) when the gate (114) electrode is biased to an appropriate level. In one aspect, the source (110) may be electrically connected to the transistor (100), the drain (112) may be electrically connected to the transistor (100), and the gate (114) may be electrically connected to the transistor (100), so that when the gate (114) is biased to an appropriate level, current may flow between the source (110) and the drain (112) through a two-dimensional electron gas (2DEG) induced at the heterogeneous interface (152) between the channel layer (104) and the barrier layer (108). In various aspects, the gate (114) may control the flow of electrons within the 2DEG based on a signal and / or bias placed on the gate (114). In this regard, depending on the composition of the layer and / or the doping of the layer, the transistor (100) may be normally turned on without bias or a signal on the gate, or the transistor (100) may be normally turned off. In one aspect, the heterogeneous interface (152) may be in the range of .005μm to .007μm, .007μm to .009μm, and .009μm to .011μm.

[0185] The gate (114) may extend over the top of the spacer or spacer layer (116). The spacer layer (116) may be etched and the gate (114) may be deposited so that the bottom of the gate (114) is on the surface of the barrier layer (108). The metal forming the gate (114) may be patterned so that the top of the gate (114) extends across the spacer layer (116) to form a field plate (132).

[0186] Additionally, as part of step 514 during some aspects of the process (500), a second spacer layer (117) may be formed, and a field plate (132) may be placed on top of the second spacer layer (117) and separated from the gate (114). In one aspect, the field plate (132) may be deposited on the second spacer layer (117) between the gate (114) and the drain (112). In some aspects, the field plate (132) may comprise many other conductive materials having a suitable material, which is a metal or a combination of metals deposited using a standard metallization method. In one aspect, the field plate (132) may comprise titanium, gold, nickel, titanium / gold, nickel / gold, etc.

[0187] In one aspect, the connection portion (154) may be formed together with the field plate (132) during the same manufacturing step (see FIG. 10). In one aspect, a plurality of field plates (132) may be used. In one aspect, a plurality of field plates (132) may be used, and each of the plurality of field plates (132) may be stacked with a dielectric in between. In one aspect, the field plate (132) extends toward the edge of the gate (114) toward the drain (112). In one aspect, the field plate (132) extends toward the source (110). In one aspect, the field plate (132) extends toward the drain (112) and toward the gate (114). In another aspect, the field plate (132) does not extend toward the edge of the gate (114). Finally, the structure may be covered with a dielectric spacer layer such as silicon nitride. The dielectric spacer layer may also be implemented similarly to the spacer layer (116). Furthermore, the cross-sectional shape of the gate (114) illustrated in the drawing is exemplary. For example, in some aspects, the cross-sectional shape of the gate (114) may not include a T-shaped extension. Other configurations of the gate (114) may be utilized.

[0188] The steps of the process (500) may be performed in a different order according to the aspects described above. Additionally, the process (500) may be modified to have more or fewer process steps in accordance with the various aspects disclosed herein. In one aspect of the process (500), the transistor (100) may be implemented with only a p-type material layer (106).

[0189] In one aspect of the transistor (100) described herein, the p-type material layer (106) may be doped as highly as possible to achieve the minimum sheet resistance. In one aspect, the p-type material layer (106) is 10 19 It may have an injection concentration of less than 10. In one aspect, the p-type material layer (106) is 10 20It may have an injection concentration of less than 10. In one aspect, the p-type material layer (106) is 10 17 - 10 20 , 10 19 - 10 20 , 10 18 - 10 19 , or 10 17 - 10 18 It can have an injection concentration of. In one aspect, the p-type material layer (106) is 10 19 It can have an injection concentration greater than or equal to this. In one aspect, the p-type material layer (106) is 10 18 - 10 20 , 10 18 - 10 19 , or 10 19 - 10 20 It can have an injection concentration of.

[0190] In one aspect of the transistor (100) described herein, the doping of the p-type material layer (106) is 1E17 cm 3 It may be less than. In one aspect, the doping of the p-type material layer (106) is 2E17 cm 3 It may be less than. In one aspect, the doping of the p-type material layer (106) is 6E17 cm 3 It may be less than. In one aspect, the doping of the p-type material layer (106) is 2E18 cm 3 It may be less than. In one aspect, the doping of the p-type material layer (106) is cm 3 The range may be from 5E15 to 5E17. In this respect, the doping concentration of the p-type material layer (106) may be greater than the doping concentration of the p-type material layer (106).

[0191] One aspect of the transistor (100) may be implemented as a group 3 nitride transistor having at least one back barrier structure and at least one buried p-type layer. One aspect includes a method associated with the transistor (100) which may be implemented as a group 3 nitride transistor having at least one back barrier structure and at least one buried p-type layer. One aspect includes a method of implementing the transistor (100) as a group nitride transistor having at least one back barrier structure and at least one buried p-type layer. One aspect includes a method of manufacturing the transistor (100) as a group nitride transistor having at least one back barrier structure and at least one buried p-type layer.

[0192] Accordingly, the present disclosure provides a solution for resolving the delay effect of a group 3 nitride HEMT and improving the performance of such a device. In addition, the present disclosure provides a solution for resolving traps that cause memory effects that negatively affect performance. In particular, the present disclosure provides an implementation of a transistor (100) combined with a p-type material layer (106) and a back barrier layer (120), and their associated structures and / or their associated processes, which can provide a systematic approach to reducing delay. More specifically, the transistor (100) of the present disclosure may be implemented with the p-type material layer (106) and / or its process as a drain delay reduction structure and / or process for reducing the drain delay effect, and the transistor (100) of the present disclosure may be implemented with the back barrier layer (120) and its process as a gate delay reduction structure and / or process for reducing the gate delay effect.

[0193] In particular, the present disclosure provides an implementation of a transistor (100) with a p-type material layer (106) and a back barrier layer (120), an associated structure thereof, and / or an associated process thereof, which can provide a synergistic overall delay reduction of the transistor (100) as an unexpected result of the combined structure of the back barrier layer (120) and the p-type material layer (106).

[0194] According to aspects of the present disclosure, one or more aspects of the disclosed transistor (100) may be utilized to implement components such as amplifiers, radar amplifiers, radar components, microwave radar amplifiers, power modules, gate drivers, general-purpose broadband components, communication components, L-band components, S-band components, X-band components, C-band components, Ku-band components, satellite communication components, Deherty configurations, etc. The L-band is an IEEE (Institute of Electrical and Electronics Engineers) designation for a radio spectrum frequency range of 1 to 2 gigahertz (GHz). The S-band is an IEEE designation for a portion of the microwave band of the electromagnetic spectrum covering frequencies of 2 to 4 GHz. The X-band is a designation for a frequency band of the microwave radio region of the electromagnetic spectrum vaguely set at approximately 7.0 to 11.2 GHz. The C-band is a designation given for radio frequencies of 500 to 1000 MHz. The Ku band is a part of the electromagnetic spectrum in the microwave range of frequencies from 12 to 18 GHz.

[0195] According to aspects of the present disclosure, one or more aspects of the disclosed transistor (100) may be configured as a package, may be implemented as an RF package, an MMIC RF package, etc., and may accommodate an RF device. In particular, the RF device may implement one or more of a resistor, inductor, capacitor, metal-oxide-silicon (MOS) capacitor, impedance matching circuit, matching circuit, input matching circuit, output matching circuit, intermediate matching circuit, harmonic filter, harmonic termination, coupler, balun, power coupler, power divider, radio frequency (RF) circuit, radial stub circuit, transmission line circuit, fundamental frequency matching circuit, baseband termination circuit, second harmonic termination circuit, integrated passive device (IPD), matching network, etc. A package implemented as an MMIC package may further include the transistor (100). A package implemented as an MMIC package can include, connect, and support a radar transmitter, radar transmitter function, microwave radar transmitter, microwave radar transmitter function, radar receiver, radar receiver function, microwave radar receiver, microwave radar receiver function, etc.

[0196] Although the present disclosure has been described in terms of exemplary aspects, those skilled in the art will recognize that the present disclosure may be practiced with modifications to the spirit and scope of the appended claims. The examples given above are merely illustrative and do not constitute a complete list of all possible designs, aspects, applications, or modifications of the present disclosure.

Claims

Claim 1 As a device, the device comprises: a substrate; a group nitride back barrier layer on the substrate; a group nitride channel layer on the group nitride back barrier layer; a group nitride barrier layer on the group nitride channel layer — the group nitride barrier layer comprises a bandgap larger than the bandgap of the group nitride channel layer —; a source electrically connected to the group nitride barrier layer; a gate on the group nitride barrier layer; a drain electrically connected to the group nitride barrier layer; and a p-region disposed on or below the group nitride barrier layer, wherein at least a portion of the p-region is vertically disposed below at least one of the source, the gate, and the region between the gate and the drain, and the group nitride back barrier layer is composed of low background impurity levels, and the low background impurity levels are 1E15 / cm² 3 A device defined by impurities of less than [amount]. Claim 2 The apparatus of claim 1, wherein the group 3 nitride back barrier layer comprises the low background impurity levels configured at least partially as a gate delay reduction structure, and the group 3 nitride back barrier layer is configured to confine electrons within the group 3 nitride barrier layer on the group nitride channel layer. Claim 3 In claim 1, the p region is configured at least partially as a drain delay reduction structure, and the group 3 nitride rear barrier layer is on the nucleation layer, the device. Claim 4 In claim 1, the group 3 nitride back barrier layer comprises the low background impurity levels configured at least partially as a gate delay reduction structure, the p-region configured at least partially as a drain delay reduction structure, and the group 3 nitride back barrier layer and the p-region reduce the total delay, the apparatus. Claim 5 The apparatus according to claim 1, wherein the group 3 nitride rear barrier layer comprises a thickness defined as the distance between the upper surface of the substrate and the lower surface of the group 3 nitride rear barrier layer. Claim 6 The device according to claim 1, wherein the group 3 nitride rear barrier layer is composed of at least one of silicon, oxygen, and carbon at a low background impurity level. Claim 7 In claim 1, the device is configured such that the group 3 nitride rear barrier layer is formed as a sharp interface to the group 3 nitride channel layer, and the sharp interface is configured to function as a barrier for electrons. Claim 8 In claim 1, the device wherein the group 3 nitride rear barrier layer comprises AlGaN. Claim 9 The apparatus according to claim 1, wherein the group 3 nitride rear barrier layer comprises AlGaN having an Al concentration of 1% to 4.5%. Claim 10 The apparatus according to claim 1, wherein the group 3 nitride back barrier layer is structured by epitaxial growth having a low background impurity level of at least one of silicon (Si), oxygen (O), and carbon (C). Claim 11 An apparatus according to claim 1, further comprising a nucleation layer formed on the substrate, wherein the group 3 nitride rear barrier layer is disposed on the nucleation layer. Claim 12 A device according to claim 1, wherein the source-side portion of the substrate does not have the p-region and the drain-side portion of the substrate does not have the p-region. Claim 13 A device according to claim 1, wherein a portion of the substrate includes a p region positioned vertically below the source, and another portion of the substrate does not include a p region positioned vertically below the source. Claim 14 A device according to claim 1, wherein the substrate does not include a p region vertically positioned below the source, and the substrate does not include a p region vertically positioned below the drain. Claim 15 A device according to claim 1, wherein the p region is structured and arranged so that no part of the p region is positioned vertically below the drain. Claim 16 A device according to claim 1, further comprising a field plate, wherein the p region is injected. Claim 17 A device according to claim 1, further comprising a field plate, wherein the field plate is electrically connected to the source. Claim 18 An apparatus according to claim 17, wherein the p region is structured and arranged to extend a limited length parallel to the group 3 nitride barrier layer so as not to be located vertically below the region passing through the source and the drain. Claim 19 In claim 1, the device, wherein the p region is positioned below the length of the gate and across the length of the gate, and extends toward the source and the drain. Claim 20 A device according to claim 1, wherein the p region extends toward the source but does not overlap perpendicularly with the source. Claim 21 In claim 1, the device, wherein the p region is vertically superimposed with the source. Claim 22 A device according to claim 1, wherein the p region extends toward the drain but does not overlap perpendicularly with the drain. Claim 23 In claim 1, the device, wherein the p region overlaps perpendicularly with the drain. Claim 24 In paragraph 1, the device, wherein the p region does not include a direct electrical connection. Claim 25 A method for manufacturing an apparatus comprises the steps of: providing a substrate; providing a group nitride back barrier layer on the substrate; providing a group nitride channel layer on the group nitride back barrier layer; providing a group nitride barrier layer on the group nitride channel layer having a band gap larger than the band gap of the group nitride channel layer; electrically connecting a source to the group nitride barrier layer; placing a gate on the group nitride barrier layer; electrically connecting a drain to the group nitride barrier layer; and providing a p-region placed on or below the group nitride barrier layer, wherein at least a portion of the p-region is vertically placed below at least one of the source, the gate, and the region between the gate and the drain, and the group nitride back barrier layer is composed of low background impurity levels, and the low background impurity levels are 1E15 / cm² 3 A method for manufacturing a device defined by impurities of less than [amount]. Claim 26 A method for manufacturing a device according to claim 25, wherein the group 3 nitride back barrier layer comprises the low background impurity levels configured at least partially as a gate delay reduction structure, and the group 3 nitride back barrier layer is configured to confine electrons within the group 3 nitride barrier layer on the group nitride channel layer. Claim 27 A method for manufacturing a device according to claim 25, wherein the p region is at least partially configured as a drain delay reduction structure, and the group 3 nitride rear barrier layer is on the nucleation layer. Claim 28 A method for manufacturing an apparatus according to claim 25, wherein the group 3 nitride rear barrier layer comprises low background impurity levels configured at least partially as a gate delay reduction structure, the p-region configured at least partially as a drain delay reduction structure, and the group 3 nitride rear barrier layer and the p-region reduce the total delay. Claim 29 A method for manufacturing an apparatus according to claim 25, wherein the group 3 nitride rear barrier layer comprises a thickness defined as the distance between the upper surface of the substrate and the lower surface of the group 3 nitride rear barrier layer. Claim 30 A method for manufacturing a device according to claim 25, wherein the group 3 nitride rear barrier layer is composed of low background impurity levels of silicon, oxygen, and carbon. Claim 31 A method for manufacturing a device according to claim 25, wherein the group 3 nitride rear barrier layer is configured as a sharp interface to the group 3 nitride channel layer, and the sharp interface is configured to function as a barrier for electrons. Claim 32 A method for manufacturing a device according to claim 25, wherein the group 3 nitride rear barrier layer comprises AlGaN. Claim 33 A method for manufacturing a device according to claim 25, wherein the group 3 nitride rear barrier layer comprises AlGaN having an Al concentration of 1% to 4.5%. Claim 34 A method for manufacturing a device according to claim 25, wherein the group 3 nitride back barrier layer is structured by epitaxial growth having a low background impurity level of at least one of silicon (Si), oxygen (O), and carbon (C). Claim 35 A method for manufacturing an apparatus according to claim 25, further comprising a nucleation layer formed on the substrate, wherein the group 3 nitride rear barrier layer is disposed on the nucleation layer. Claim 36 A method for manufacturing a device according to claim 25, wherein the source-side portion of the substrate does not have the p-region and the drain-side portion of the substrate does not have the p-region. Claim 37 A method for manufacturing a device according to claim 25, wherein a portion of the substrate comprises a p region positioned vertically below the source, and another portion of the substrate does not comprise a p region positioned vertically below the source. Claim 38 A method for manufacturing a device according to claim 25, wherein the substrate does not include a p region positioned vertically below the source, and the substrate does not include a p region positioned vertically below the drain. Claim 39 A method for manufacturing a device according to claim 25, further comprising the step of forming the p region such that no part of the p region is positioned vertically below the drain. Claim 40 A method for manufacturing a device according to claim 25, further comprising the step of injecting the p region. Claim 41 A method for manufacturing a device according to claim 25, further comprising the step of providing a field plate. Claim 42 A method for manufacturing a device according to claim 25, further comprising the step of providing a field plate, wherein the field plate is electrically connected to the source. Claim 43 A method for manufacturing a device according to claim 42, wherein the p region is structured and arranged to extend a limited length parallel to the group 3 nitride barrier layer so as not to be located vertically below the region passing through the source and the drain. Claim 44 A method for manufacturing a device according to claim 25, wherein the p region is positioned below the length of the gate and across the length of the gate, and extends toward the source and the drain. Claim 45 A method for manufacturing a device according to claim 25, wherein the p region extends toward the source but does not overlap perpendicularly with the source. Claim 46 A method for manufacturing a device in which, in paragraph 25, the p region is vertically superimposed with the source. Claim 47 A method for manufacturing a device according to claim 25, wherein the p region extends toward the drain but does not overlap perpendicularly with the drain. Claim 48 A method for manufacturing a device according to claim 25, wherein the p region overlaps perpendicularly with the drain. Claim 49 In paragraph 25, a method for manufacturing a device in which the p region does not include a direct electrical connection. Claim 50 In paragraph 25, a method for manufacturing a device in which the p region is electrically connected to the source.

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