Display apparatus

Abstract

The present invention provides a display device comprising: a substrate including a display area and a pad area; a thin-film transistor and a plurality of auxiliary electrodes formed on the substrate; and a plurality of clad layers formed on the thin-film transistor and the plurality of auxiliary electrodes, wherein the plurality of clad layers comprises: a first clad layer electrically connected to the thin-film transistor; and a second clad layer electrically connected to any one of the plurality of auxiliary electrodes.

Description

Technology Field

[0001] The present invention relates to a display device. Background Technology

[0002] As the information society develops, the demand for display devices for displaying images is increasing in various forms. Accordingly, various display devices such as Liquid Crystal Displays (LCDs), Plasma Display Panels (PDPs), and Electroluminescence Displays (ELDs) are being utilized recently. Furthermore, Electroluminescence Displays may include display devices such as Organic Light Emitting Displays (OLEDs) and Quantum-dot Light Emitting Displays (QLEDs).

[0003] Among display devices, electroluminescent displays are self-emissive types that offer superior viewing angles and contrast ratios compared to liquid crystal displays (LCDs). Furthermore, they do not require a separate backlight, enabling lightweight and thin designs, and offer the advantage of lower power consumption. Additionally, electroluminescent displays can be driven at low DC voltages, feature fast response speeds, and, notably, have the advantage of low manufacturing costs.

[0004] Meanwhile, conventionally, a structure is used to prevent leakage current by forming a blocking layer beneath the thin-film transistor to block light incident on the transistor. In this case, the blocking layer is formed from a metallic material, allowing a storage capacitor to be formed through the blocking layer and the metal layer of the thin-film transistor. However, if the area of ​​the blocking layer and the metal layer of the thin-film transistor is increased to secure the capacity of the storage capacitor, there is a problem in that the area available for forming structures other than the storage capacitor is reduced. The problem to be solved

[0005] The present invention aims to provide a display device with increased capacity per unit area of ​​a storage capacitor. means of solving the problem

[0006] To achieve the objective, the present invention provides a display device comprising: a substrate including a display area and a pad area; a thin-film transistor and a plurality of auxiliary electrodes formed on the substrate; and a plurality of clad layers formed on the thin-film transistor and the plurality of auxiliary electrodes, wherein the plurality of clad layers comprises: a first clad layer electrically connected to the thin-film transistor; and a second clad layer electrically connected to any one of the plurality of auxiliary electrodes. Effects of the invention

[0007] According to the present invention, by forming a plurality of clad layers, corrosion and damage to the metal layer are prevented, and the capacity per unit area of ​​the storage capacitor is increased. Brief explanation of the drawing

[0008] FIG. 1 is a plan view schematically showing a display device according to one embodiment of the present invention. FIG. 2 is a plan view schematically showing one subpixel of a display device according to one embodiment of the present invention. FIG. 3 is a cross-sectional view of a display device according to one embodiment of the present invention. FIG. 4 is a cross-sectional view of a display device according to another embodiment of the present invention. Specific details for implementing the invention

[0009] The advantages and features of the present invention and the methods for achieving them will become clear by referring to the embodiments described below in detail together with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below but may be implemented in various different forms. These embodiments are provided merely to ensure that the disclosure of the present invention is complete and to fully inform those skilled in the art of the scope of the invention, and the present invention is defined only by the scope of the claims.

[0010] Shapes, sizes, ratios, angles, numbers, etc. disclosed in the drawings for explaining embodiments of the present invention are exemplary, and therefore the present invention is not limited to the depicted details. Throughout the specification, the same reference numerals refer to the same components. Furthermore, in describing the present invention, if it is determined that a detailed description of related prior art could unnecessarily obscure the essence of the present invention, such detailed description is omitted. Where terms such as "includes," "has," or "is made up" are used in this specification, other parts may be added unless "only" is used. Where a component is expressed in the singular, it includes cases where it is included in the plural unless specifically stated otherwise.

[0011] In interpreting the components, they are interpreted to include a margin of error even in the absence of a separate explicit statement.

[0012] In the case of describing a positional relationship, for example, when the positional relationship between two parts is described using expressions such as 'on,' 'upper,' 'lower,' or 'next to,' one or more other parts may be located between the two parts unless 'immediately' or 'directly' is used.

[0013] In the case of an explanation of a temporal relationship, for example, when the temporal sequence is explained using 'after', 'following', 'next', 'before', etc., it may include cases where the sequence is not continuous unless 'immediately' or 'directly' is used.

[0014] Although terms such as "first," "second," etc., are used to describe various components, these components are not limited by these terms. These terms are used merely to distinguish one component from another. Accordingly, the first component mentioned below may be the second component within the technical scope of the present invention.

[0015] The features of each of the various embodiments of the present invention may be combined or combined with one another, either partially or wholly, and may technically enable various interlocking and operation. Each embodiment may be implemented independently of one another or may be implemented together in an associated relationship.

[0016] Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the drawings.

[0018] FIG. 1 is a plan view schematically showing a display device (10) according to one embodiment of the present invention.

[0019] Referring to FIG. 1, a display device (10) according to one embodiment of the present invention may include a display area (DA) including a plurality of subpixels (P) and a non-display area (NDA) surrounding the display area (DA).

[0020] The non-display region (DNA) may include a pad region (PA). A plurality of pad electrodes may be formed in the pad region (PA) to apply a power voltage to the thin-film transistor from an external power source. Referring to FIG. 1, the pad region (PA) is positioned below the display region (DA), but is not limited thereto.

[0022] FIG. 2 is a plan view schematically showing one subpixel (P) of a display device (10) according to one embodiment of the present invention.

[0023] Referring to FIG. 2, each of the plurality of subpixels (P) of a display device (10) according to one embodiment of the present invention may include a substrate (100), a power line (VL), a gate line (GL), a data line (DL), a driving thin film transistor (DT), a switching thin film transistor (ST), a blocking layer (200), and a pixel electrode (900).

[0024] The substrate (100) may be made of glass or plastic, but is not necessarily limited thereto, and may also be made of a semiconductor material such as a silicon wafer.

[0025] A plurality of subpixel regions are provided on a substrate (100) by a gate line (GL) arranged in one direction, a data line (DL) arranged perpendicularly to the gate line (GL), and a power line (VL) arranged parallel to the data line (DL). In FIG. 2, one subpixel (P) is illustrated.

[0026] A blocking layer (200) is provided on a substrate (100) and can be formed in an area surrounded by a gate line (GL), a data line (DL), and a power line (VL). Since the blocking layer (200) is not connected to signal lines such as the gate line (GL), the data line (DL), and the power line (VL), it may not perform the function of supplying voltage to other components.

[0027] In order to prevent the semiconductor layers (410, 510) of the driving thin-film transistor (DT) and the switching thin-film transistor (ST) from being affected by external light, a blocking layer (200) may be formed in an area that overlaps with the semiconductor layers (410, 510) of the driving thin-film transistor (DT) and the switching thin-film transistor (ST). Additionally, the blocking layer (200) may overlap with other components of the driving thin-film transistor (DT) and the switching thin-film transistor (ST) in addition to the semiconductor layers (410, 510). Furthermore, the blocking layer (200) may also overlap with the pixel electrode (900).

[0028] The blocking layer (200) may be formed by including a conductive material capable of blocking light. For example, the blocking layer (200) may be formed of an opaque metallic material such as aluminum (Al), silver (Ag), copper (Cu), molybdenum (Mo), titanium (Ti), tungsten (W), or chromium (Cr), or an alloy thereof. Additionally, although the blocking layer (200) is depicted as a single layer, it may be formed as a multilayer. For example, the blocking layer (200) may be formed as a double layer, and the double layer may consist of a lower layer and an upper layer containing different materials. In this case, the lower layer may be made of a molybdenum-titanium alloy (MoTi) and the upper layer may be made of copper (Cu), but is not limited thereto.

[0029] Additionally, the blocking layer (200) can be electrically connected to the gate electrode (430) of the driving thin-film transistor (DT) through the contact hole (H). Accordingly, the driving thin-film transistor (DT) of the present invention can improve the performance of the driving thin-film transistor (DT) by disclosing a double gate electrode structure.

[0030] A switching thin-film transistor (ST) is disposed in the region where the gate line (GL) and the data line (DL) intersect, and may be provided on the blocking layer (200). The switching thin-film transistor (ST) can perform the role of switching to apply a signal to the subpixel (P).

[0031] A switching thin-film transistor (ST) may include a semiconductor layer (510), a gate electrode (530), a source electrode (541), and a drain electrode (542). The switching thin-film transistor (ST) may be connected to a gate line (GL) and a data line (DL). For example, the gate electrode (530) of the switching thin-film transistor (ST) may be connected to the gate line (GL), and the source electrode (541) of the switching thin-film transistor (ST) may be connected to the data line (DL).

[0032] One side of the semiconductor layer (510) of the switching thin film transistor (ST) can be connected to the source electrode (541) of the switching thin film transistor (ST) through a contact hole, and the other side of the semiconductor layer (510) can be connected to the drain electrode (542) of the switching thin film transistor (ST) through a contact hole.

[0033] The switching thin-film transistor (ST) can be turned on or turned off by a scan signal supplied through the gate line (GL). Thus, when a data voltage is provided through the data line (DL), the switching thin-film transistor (ST) can control the application of the data voltage to the subpixel through the scan signal.

[0034] A driving thin-film transistor (DT) is provided on a blocking layer (200) and serves to drive a subpixel (P) based on a signal applied by a switching thin-film transistor (ST). Referring to FIG. 2, the gate electrode (430) of the driving thin-film transistor (DT) can be connected to the drain electrode (542) of the switching thin-film transistor (ST) through a contact hole. Additionally, the source electrode (441) of the driving thin-film transistor (DT) is connected to a power line (VL), and the drain electrode (442) of the driving thin-film transistor (DT) can be connected to a pixel electrode (900) through a contact hole.

[0035] One side of the semiconductor layer (410) of the driving thin film transistor (DT) is connected to the source electrode (441) of the driving thin film transistor (DT) through a contact hole, and the other side of the semiconductor layer (410) of the driving thin film transistor (DT) can be connected to the drain electrode (442) of the driving thin film transistor (DT) through a contact hole.

[0036] Additionally, a plurality of storage capacitors (Cst) may be formed at the bottom of the pixel electrode (900). In FIG. 2, the plurality of storage capacitors (Cst) are shown to overlap with the pixel electrode (900), but this is not limited thereto. The plurality of storage capacitors (Cst) will be described in detail in FIG. 3 and FIG. 4.

[0038] FIG. 3 is a cross-sectional view of a display device (10) according to one embodiment of the present invention.

[0039] Referring to FIG. 3, a display device (10) according to one embodiment of the present invention may include a display area (DA) and a pad area (PA). Additionally, the display area (DA) may include a first area (DA1) in which a driving thin-film transistor (DT) is disposed and a second area (DA2) in which a storage capacitor (Cst) is disposed. In FIG. 3, a cross-sectional view of line II' of FIG. 2 is shown as the display area (DA).

[0040] In the first region (DA1) of the display region (DA), a substrate (100), a blocking layer (200), a buffer layer (300), a driving thin-film transistor (DT), an interlayer insulating layer (600), a passivation layer (650), a first clad layer (710), a flattening layer (800), and a pixel electrode (900) may be formed.

[0041] The substrate (100) may be made of glass or plastic, but is not limited thereto.

[0042] A blocking layer (200) is formed on a substrate (100) and may be made of a conductive material capable of blocking light. For example, the blocking layer (200) may be made of a metallic material such as aluminum (Al), silver (Ag), copper (Cu), molybdenum (Mo), titanium (Ti), tungsten (W), or chromium (Cr), or an alloy thereof. Additionally, although the blocking layer (200) is shown as a single layer, it may be formed as a multilayer. For example, the blocking layer (200) may be formed as a double layer, and the double layer may consist of a lower layer and an upper layer containing different materials. In this case, the lower layer may be made of a molybdenum-titanium alloy (MoTi) and the upper layer may be made of copper (Cu), but is not limited thereto.

[0043] A buffer layer (300) can be formed on a substrate (100) to cover a blocking layer (200). The buffer layer (300) may be made of silicon nitride (SiNx) or silicon oxide (SiOx). Additionally, although the buffer layer (300) is shown as a single layer, it may be formed as a multilayer. The buffer layer (300) insulates the blocking layer (200) and can improve the adhesion between the layers formed on the buffer layer (300) and the substrate (100).

[0044] A driving thin-film transistor (DT) can be formed on a buffer layer (300). Additionally, the driving thin-film transistor (DT) can be positioned overlapping with a blocking layer (200). Accordingly, by placing the blocking layer (200) below the driving thin-film transistor (DT), external light is prevented from affecting the driving thin-film transistor (DT), thereby improving the reliability of the driving thin-film transistor (DT).

[0045] The driving thin-film transistor (DT) may include a semiconductor layer (410), a gate insulating layer (420), a gate electrode (430), a source electrode (441), and a drain electrode (442).

[0046] The semiconductor layer (410) of the driving thin-film transistor (DT) can be formed on the buffer layer (300). The semiconductor layer (410) may include a poly-silicon semiconductor or an oxide semiconductor. And, if the semiconductor layer (410) includes an oxide semiconductor, it may be formed by including at least one oxide selected from IGZO (indium-gallium-zinc-oxide), IZO (indium-zinc-oxide), IGTO (indium-gallium-tin-oxide), and IGO (indium-gallium-oxide).

[0047] The gate insulating layer (420) of the driving thin-film transistor (DT) is formed on the semiconductor layer (410) to insulate the gate electrode (430) from the semiconductor layer (410). The gate insulating layer (420) of the driving thin-film transistor (DT) may be made of silicon nitride (SiNx) or silicon oxide (SiOx). Additionally, although the gate insulating layer (420) is shown as a single layer, it may be formed as a multilayer.

[0048] The gate electrode (430) of the driving thin-film transistor (DT) can be formed on the gate insulating layer (420). The gate electrode (430) can be formed on the gate insulating layer (420) so as to overlap with the channel region of the semiconductor layer (410).

[0049] As described above in FIG. 2, the gate electrode (430) of the driving thin-film transistor (DT) can be electrically connected to the blocking layer (200). Accordingly, the blocking layer (200) made of a conductive material can be electrically stabilized, and the blocking layer (200) can be prevented from interfering with the normal operation of the semiconductor layer (410).

[0050] In addition, since the blocking layer (200) is electrically connected to the gate electrode (430) of the driving thin-film transistor (DT), the driving thin-film transistor (DT) of the present invention can disclose a double gate electrode structure. When the driving thin-film transistor (DT) has a double gate electrode structure, both the upper and lower parts of the channel region of the semiconductor layer (410) of the driving thin-film transistor (DT) can be electrically controlled. Accordingly, leakage current flowing through the semiconductor layer (410) of the driving thin-film transistor (DT) can be minimized, thereby improving the current characteristics of the driving thin-film transistor (DT) and enhancing reliability. Although the present invention discloses a double gate electrode structure for the driving thin-film transistor (DT), a double gate electrode structure can also be disclosed for the switching thin-film transistor (ST) in the same manner.

[0051] An interlayer insulating layer (600) may be formed on the gate insulating layer (420) and the gate electrode (430) of the driving thin-film transistor (DT). The interlayer insulating layer (600) may be formed by including an organic insulating material such as an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, or a polyimide resin.

[0052] A contact hole may be formed in the gate insulating layer (420) and the interlayer insulating layer (600) of the driving thin film transistor (DT) to expose the semiconductor layer (410) of the driving thin film transistor (DT).

[0053] The source electrode (441) and drain electrode (442) of the driving thin-film transistor (DT) may be formed on the interlayer insulating layer (600) facing each other. Additionally, each of the source electrode (441) and drain electrode (442) of the driving thin-film transistor (DT) may be connected to the semiconductor layer (410) through a contact hole formed in the gate insulating layer (420) and the interlayer insulating layer (600).

[0054] The passivation layer (650) is formed on the driving thin-film transistor (DT) and can function to protect the driving thin-film transistor (DT). Additionally, the passivation layer (650) may be formed by including an inorganic insulating material such as silicon oxide (SiOX) or silicon nitride (SiNX), but is not limited thereto.

[0055] The first clad layer (710) may be formed on the passivation layer (650). The first clad layer (710) may be made of a metallic material such as aluminum (Al), silver (Ag), molybdenum (Mo), titanium (Ti), tungsten (W), or chromium (Cr), or an alloy thereof. Additionally, although the first clad layer (710) is shown as a single layer, it may be formed as a multilayer.

[0056] A first contact hole (H1) penetrating the passivation layer (650) may be formed to expose the drain electrode (442) of the driving thin-film transistor (DT). The first clad layer (710) may extend in the direction in which the first contact hole (H1) is formed and may be electrically connected to the drain electrode (442) through the first contact hole (H1). Additionally, the first clad layer (710) may be formed to cover the entire front surface of the drain electrode (442) exposed by the first contact hole (H1).

[0057] The planarization layer (800) is formed on the passivation layer (650) and the first clad layer (710) to compensate for the step difference caused by the driving thin-film transistor (DT) and contact holes. The planarization layer (800) may be formed by including an inorganic insulating material such as silicon oxide (SiOX) or silicon nitride (SiNX). Alternatively, the planarization layer (800) may be formed by including an organic insulating material such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin.

[0058] A pixel electrode (900) may be formed on a planarization layer (800). The pixel electrode (900) may include a transparent conductive material. For example, the pixel electrode (900) may be formed by including a transparent conductive material such as ITO (Indium Tin Oxide) or IZO (Indium Zinc Oxide). Alternatively, the pixel electrode (900) may be formed by including a metallic material such as aluminum (Al), silver (Ag), copper (Cu), molybdenum (Mo), titanium (Ti), tungsten (W), or chromium (Cr), or an alloy thereof. Additionally, although the pixel electrode (900) is shown as a single layer, it may be formed as a multilayer. For example, the pixel electrode (900) may be formed as a triple layer in which a transparent conductive material, a metallic material, and a transparent conductive material are sequentially stacked.

[0059] To expose the first clad layer (710), a second contact hole (H2) penetrating the flattening layer (800) may be formed. The second contact hole (H2) may be formed at a position overlapping with the first contact hole (H1). The pixel electrode (900) may be extended in the direction in which the second contact hole (H2) is formed and may be electrically connected to the first clad layer (710) through the second contact hole (H2). Since the first clad layer (710) is electrically connected to the drain electrode (442) through the first contact hole (H1), the pixel electrode (900) may also be electrically connected to the drain electrode (442).

[0060] Additionally, since the first clad layer (710) is formed to cover the entire front surface of the drain electrode (442) exposed by the first contact hole (H1), the drain electrode (442) may not be exposed to the outside by the first clad layer (710). Accordingly, in the process of forming the second contact hole (H2) in the planarization layer (800), it is possible to prevent the drain electrode (442) from being corroded or damaged by the etching solution used to etch the planarization layer (800).

[0061] The bank (850) may be provided on the flattening layer (800) and formed to cover a portion of the pixel electrode (900).

[0062] The bank (850) may be formed by including organic insulating materials such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin. Alternatively, the bank (850) may be formed by including inorganic insulating materials such as silicon nitride, aluminum nitride, zirconium nitride, titanium nitride, hafnium nitride, tantalum nitride, silicon oxide, aluminum oxide, or titanium oxide. Additionally, the bank (850) may be formed by including a black dye to absorb light incident from the outside.

[0063] In the second region (DA2) of the display region (DA), the first to third auxiliary electrodes (205, 415, 435) and the second clad layer (720) may be formed.

[0064] The first auxiliary electrode (205) can be formed on the substrate (100). The first auxiliary electrode (205) can be formed simultaneously with the blocking layer (200) through the same process and can be made of the same material.

[0065] The buffer layer (300) may be formed extending from the first region (DA1) to the second region (DA2). The buffer layer (300) may be formed to cover the first auxiliary electrode (205) on the substrate (100).

[0066] The second auxiliary electrode (415) may be formed on the buffer layer (300). The second auxiliary electrode (415) may be formed simultaneously through the same process as the semiconductor layer (410) of the driving thin-film transistor (DT) and may be made of the same material. The semiconductor layer (410) of the driving thin-film transistor (DT) may additionally undergo a process of doping both sides of the semiconductor layer (410) to be connected to the source electrode (441) and the drain electrode (442), but the doping process may be omitted for the second auxiliary electrode (415). In addition, the second auxiliary electrode (415) may also undergo a doping process in the same way as the semiconductor layer (410).

[0067] The gate insulating layer (420) may be formed extending from the first region (DA1) to the second region (DA2). The gate insulating layer (420) may be formed to cover the second auxiliary electrode (415) on the buffer layer (300).

[0068] The third auxiliary electrode (435) can be formed on the gate insulating layer (420). The third auxiliary electrode (435) can be formed simultaneously through the same process as the gate electrode (430) of the driving thin-film transistor (DT) and can be made of the same material.

[0069] The interlayer insulating layer (600) and the passivation layer (650) may be formed extending from the first region (DA1) to the second region (DA2). The interlayer insulating layer (600) may be formed to cover the third auxiliary electrode (435) on the gate insulating layer (420), and the passivation layer (650) may be formed on the interlayer insulating layer (600).

[0070] The second clad layer (720) may be formed on the passivation layer (650). The second clad layer (720) may be formed simultaneously with the first clad layer (710) through the same process and may be composed of the same material. The second clad layer (720) may be formed at a position overlapping with the third auxiliary electrode (435). Additionally, the second clad layer (720) may be formed spaced apart from the first clad layer (710).

[0071] To expose the second auxiliary electrode (415), a third contact hole (H3) may be formed penetrating the gate insulating layer (420), the interlayer insulating layer (600), and the passivation layer (650). Through the third contact hole (H3), the second clad layer (720) may be electrically connected to the second auxiliary electrode (415). That is, the second clad layer (720) may be extended in the direction in which the third contact hole (H3) is formed, so as to be electrically connected to the second auxiliary electrode (415) through the third contact hole (H3). Additionally, the second clad layer (720) may be formed to cover the entire front surface of the second auxiliary electrode (415) exposed by the third contact hole (H3).

[0072] Although not shown in the drawing, the first auxiliary electrode (205) and the third auxiliary electrode (435) can be electrically connected.

[0073] At this time, a plurality of storage capacitors (Cst) may be formed by the stacked structure of the first to third auxiliary electrodes (205, 415, 435) and the second clad layer (720). The plurality of storage capacitors (Cst) may include the first to third storage capacitors (Cst1-Cst3).

[0074] Specifically, the first storage capacitor (Cst1) can be formed through a first auxiliary electrode (205), a second auxiliary electrode (415), and a buffer layer (300) formed between the first auxiliary electrode (205) and the second auxiliary electrode (415). That is, the first auxiliary electrode (205) and the second auxiliary electrode (415) act as the lower electrode and the upper electrode of the first storage capacitor (Cst1), and the buffer layer (300) acts as the dielectric layer of the first storage capacitor (Cst1).

[0075] The second storage capacitor (Cst2) can be formed through the second auxiliary electrode (415), the third auxiliary electrode (435), and the gate insulating layer (420) provided between the second auxiliary electrode (415) and the third auxiliary electrode (435). That is, the second auxiliary electrode (415) and the third auxiliary electrode (435) serve as the lower electrode and the upper electrode of the second storage capacitor (Cst2), and the gate insulating layer (420) serve as the dielectric layer of the second storage capacitor (Cst2).

[0076] The third storage capacitor (Cst3) can be formed through the third auxiliary electrode (435), the second clad layer (720), and the interlayer insulating layer (600) and passivation layer (650) provided between the third auxiliary electrode (435) and the second clad layer (720). That is, the third auxiliary electrode (435) and the second clad layer (720) can serve as the lower electrode and upper electrode of the third storage capacitor (Cst3), and the interlayer insulating layer (600) and passivation layer (650) can serve as the dielectric layer of the third storage capacitor (Cst3).

[0077] At this time, the second auxiliary electrode (415) can be simultaneously driven as the upper electrode of the first storage capacitor (Cst1) and the lower electrode of the second storage capacitor (Cst2). Additionally, the third auxiliary electrode (435) can be simultaneously driven as the upper electrode of the second storage capacitor (Cst2) and the lower electrode of the third storage capacitor (Cst3). Accordingly, the present invention can disclose a triple storage capacitor structure in which the first to third storage capacitors (Cst1-Cst3) are sequentially stacked.

[0078] Accordingly, the present invention can disclose a structure in which a plurality of storage capacitors (Cst1-Cst3) are stacked by additionally forming a second clad layer (720) in the area where a conventional storage capacitor is formed. Accordingly, the capacity of the storage capacitor can be increased while maintaining the area of ​​the region where the conventional storage capacitor is formed. That is, by increasing the capacity per area of ​​the storage capacitor, the image quality of the display device can be improved, and an area for designing structures other than the storage capacitor can be secured.

[0079] A substrate (100), a third clad layer (730), and a pad electrode (950) may be formed in the pad region (PA).

[0080] A pad electrode (950) is formed on a substrate (100) to apply a power voltage to a driving thin-film transistor (DT) from an external power source. Although it is illustrated that the pad electrode (950) is formed on the same layer as the gate electrode (430) of the driving thin-film transistor (DT), it is not limited thereto. Additionally, although it is illustrated that the pad electrode (950) is formed on a buffer layer (300), a gate insulating layer (420), and an interlayer insulating layer (600), it is not limited thereto. For example, at least one of the buffer layer (300), the gate insulating layer (420), and the interlayer insulating layer (600) may not be formed in the pad region (PA). Alternatively, none of the buffer layer (300), the gate insulating layer (420), and the interlayer insulating layer (600) may be formed in the pad region (PA).

[0081] The pad electrode (950) may be formed simultaneously through the same process as the source electrode (441) and drain electrode (442) of the driving thin-film transistor (DT), but is not limited thereto. Additionally, the pad electrode (950) may be made of the same material as the source electrode (441) and drain electrode (442) of the driving thin-film transistor (DT), but is not limited thereto.

[0082] A third clad layer (730) may be formed on the pad electrode (950). The third clad layer (730) may be formed simultaneously with the first clad layer (710) or the second clad layer (720) through the same process and may be composed of the same material.

[0083] The third clad layer (730) can be formed to cover the entire front surface of the pad electrode (950). That is, the pad electrode (950) may not be exposed to the outside by the third clad layer (730). Accordingly, in the process of forming the components of the display area (DA), the pad electrode (950) can be prevented from being corroded or damaged by the etching solution used to etch the components of the display area (DA).

[0084] Accordingly, the present invention can prevent corrosion and damage to the metal layer by forming a plurality of clad layers (700) including first to third clad layers (710, 720, 730), and has the effect of increasing the capacity per area of ​​the storage capacitor.

[0086] FIG. 4 is a cross-sectional view of a display device according to another embodiment of the present invention.

[0087] The display device according to FIG. 4 discloses a structure substantially identical to that of the display device according to FIG. 3, except for the structure of the pad area (PA). Accordingly, the same reference numerals are used for components identical to those in the display device shown in FIG. 3, and repetitive descriptions are omitted.

[0088] A substrate (100), a passivation layer (650), a third clad layer (730), and a pad electrode (950) may be formed in the pad region (PA).

[0089] As described above in FIG. 3, the pad electrode (950) is formed on the substrate (100) so that a power voltage can be applied to the driving thin-film transistor (DT) from an external power source. The pad electrode (950) of FIG. 4 may have the same characteristics as the pad electrode (950) described above in FIG. 3.

[0090] The passivation layer (650) may be formed extending from the display area (DA) to the pad area (PA). The passivation layer (650) may be formed on the interlayer insulating layer (600) and the pad electrode (950).

[0091] A third clad layer (730) may be formed on the passivation layer (650). The third clad layer (730) may be formed to overlap with the pad electrode (950).

[0092] To expose the pad electrode (950), a fourth contact hole (H4) penetrating the passivation layer (650) may be formed. The third clad layer (730) may extend in the direction in which the fourth contact hole (H4) is formed and may be electrically connected to the pad electrode (950) through the fourth contact hole (H4). Additionally, the third clad layer (730) may be formed to cover the entire upper surface of the pad electrode (950) exposed by the fourth contact hole (H4).

[0093] That is, the pad electrode (950) may not be exposed to the outside by the third clad layer (730) and the passivation layer (650). Accordingly, in the process of forming the components of the display area (DA), it is possible to prevent the pad electrode (950) from being corroded or damaged by the etching solution used to etch the components of the display area (DA).

[0094] Accordingly, the present invention can further prevent corrosion and damage to the pad electrode (950) by preventing the pad electrode (950) from being exposed to the outside through the third clad layer (730) and the passivation layer (650).

[0096] Although embodiments of the present invention have been described in more detail with reference to the attached drawings, the present invention is not necessarily limited to these embodiments and may be modified in various ways within the scope of the technical spirit of the present invention. Accordingly, the embodiments disclosed in the present invention are intended to explain, not limit, the technical spirit of the present invention, and the scope of the technical spirit of the present invention is not limited by these embodiments. Therefore, the embodiments described above should be understood as illustrative in all respects and not restrictive. The scope of protection of the present invention shall be interpreted by the claims, and all technical spirits within an equivalent scope shall be interpreted as being included within the scope of rights of the present invention. Explanation of the symbols

[0098] 100: Substrate 200: Blocking layer 205: First auxiliary electrode 300: Buffer layer 415: Second auxiliary electrode 435: Third auxiliary electrode 600: Interlayer insulation layer 650: Passivation layer 700: Clad layer 800: Flattening layer 900: Pixel electrode 950: Pad electrode DT: Driving thin-film transistor ST: Switching thin-film transistor

Claims

Claim 1 A display device comprising: a substrate including a display area and a pad area; a blocking layer formed on the substrate and blocking light; a thin-film transistor and a plurality of auxiliary electrodes formed on the substrate; and a plurality of clad layers formed on the thin-film transistor and the plurality of auxiliary electrodes, wherein the plurality of clad layers include a first clad layer electrically connected to the thin-film transistor; and a second clad layer electrically connected to any one of the plurality of auxiliary electrodes, and wherein the plurality of auxiliary electrodes include: a first auxiliary electrode formed on the substrate and formed on the same layer as the blocking layer; a second auxiliary electrode formed on the first auxiliary electrode and formed on the same layer as the semiconductor layer of the thin-film transistor; and a third auxiliary electrode formed on the second auxiliary electrode and formed on the same layer as the gate electrode of the thin-film transistor. Claim 2 In claim 1, the thin-film transistor is formed on the blocking layer and is a display device that overlaps with the blocking layer. Claim 3 In claim 2, the thin-film transistor comprises: the semiconductor layer provided on the blocking layer; the gate insulating layer provided on the semiconductor layer; the gate electrode provided on the gate insulating layer; the source electrode connected to one side of the semiconductor layer and the drain electrode connected to the other side of the semiconductor layer, forming a display device. Claim 4 A display device according to claim 1, further comprising: a planarization layer formed on the plurality of clad layers; and a pixel electrode formed on the planarization layer, wherein the pixel electrode is electrically connected to the first clad layer through a contact hole formed in the planarization layer. Claim 5 A display device according to claim 3, wherein the second clad layer is formed on the third auxiliary electrode and overlaps with the third auxiliary electrode, and an insulating layer is formed between the first auxiliary electrode and the second auxiliary electrode, between the second auxiliary electrode and the third auxiliary electrode, and between the third auxiliary electrode and the second clad layer, respectively. Claim 6 In claim 5, the first auxiliary electrode is electrically connected to the third auxiliary electrode, the display device. Claim 7 In claim 5, the second auxiliary electrode is electrically connected to the second clad layer, the display device. Claim 8 delete Claim 9 A display device according to claim 1, further comprising: a pad electrode formed on the substrate in the pad region; and a third clad layer formed on the pad electrode, wherein the third clad layer is electrically connected to the pad electrode. Claim 10 In claim 9, the display device wherein the third clad layer covers the front surface of the pad electrode. Claim 11 A display device according to claim 9, further comprising a passivation layer formed on the pad electrode, wherein the third clad layer is formed on the passivation layer and the third clad layer is electrically connected to the pad electrode through a contact hole formed in the passivation layer. Claim 12 In claim 9, the display device wherein the first to third clad layers are made of the same material. Claim 13 A display device according to claim 12, wherein the first to third clad layers comprise a metallic material such as aluminum (Al), silver (Ag), molybdenum (Mo), titanium (Ti), tungsten (W), or chromium (Cr) or an alloy thereof.

Images