A vertical structure memory device including a hybrid oxide / semi-ferroelectric blocking layer

Abstract

The present invention relates to a vertical memory device, and more specifically, to a memory device comprising a blocking film comprising an antiferroelectric material.

Description

Technology Field

[0001] The present invention relates to a vertical memory device, and more specifically, to a memory device comprising a blocking film comprising an antiferroelectric material. Background Technology

[0002] 3D vertical structure NAND Flash memory is a non-volatile flash memory that stacks cells vertically to improve storage density. As the miniaturization and integration of 2D planar NAND Flash memory devices have reached their limits, a 3D vertical NAND Flash structure has been proposed.

[0003] Vertical structure NAND flash memory increases integration density by stacking cells vertically, enabling the storage of more data per unit area, which can lead to an increase in storage capacity.

[0004] However, technical limitations resulting from manufacturing process complexity, costs, and the increase in the number of layers require continuous innovation and improvement.

[0005] The vertical NAND flash memory channel layer conducts current and significantly impacts the performance and reliability of the memory device. Two-dimensional materials that are thinner and more flexible than conventional bulk semiconductors (Si-based) are being researched; in particular, due to their thin thickness and unique electrical properties, they are suitable for 3D stacking technology and high-density integrated memory.

[0006] However, technical limitations regarding manufacturing processes, interface quality, and process compatibility exist for commercialization, and research is currently required to develop new process technologies, improve contact resistance, and enhance reliability to address these issues. Prior art literature

[0007] Republic of Korea Published Patent Application No. 10-2024-0037733 The problem to be solved

[0008] The objective of the present invention is to provide a vertical structure memory device with improved reliability through an oxide film / antiferroelectric blocking film in a hybrid double-layer structure. means of solving the problem

[0009] To achieve the above objective, a vertical structure memory device according to one embodiment of the present invention comprises: a substrate; a stacked structure formed on the substrate, wherein a plurality of insulating layers are sequentially formed in a vertical direction; and a vertical channel structure formed in the vertical direction of the stacked structure.

[0010] The vertical channel structure may include a blocking film of a double-layer structure based on an antiferroelectric material, formed on the sidewall of the stacked structure.

[0011] The above-mentioned laminated structure may have an oxide-nitride-oxide (ONO) laminated structure.

[0012] The above antiferroelectric material is PbZrO3, PbHfO3, NaNbO3, AgNbO3, Hf 1-x Zr x O2(0.7 ≤ x ≤ 0.9), Hf 1-xS i x It may be selected from the group consisting of O2 (0.7 ≤ x ≤ 0.9) and HfO2:Si (Si-doped HfO2).

[0013] The blocking film comprises an oxide, and the oxide may be silicon oxide (SiO2) or aluminum oxide (Al2O3).

[0014] The blocking film may be formed such that the oxide is formed on the sidewall of the stacked structure and the antiferroelectric is formed on the oxide.

[0015] The blocking film may be formed such that the antiferroelectric material is formed on the sidewall of the stacked structure and the oxide is formed on the antiferroelectric material.

[0016] Additionally, a vertical structure memory device according to another embodiment of the present invention comprises: a substrate; a stacked structure formed on the substrate, wherein an insulating layer and a gate metal are sequentially formed in a vertical direction; and a vertical channel structure formed in a vertical direction of the stacked structure, wherein the vertical channel structure includes a blocking film formed on the sidewall of the stacked structure, and further comprises an antiferroelectric material disposed between the insulating layer and the gate metal and between the blocking film and the gate metal, wherein the antiferroelectric material and the blocking film are disposed to be in contact with each other to form a double-layer structure.

[0017] The blocking film comprises an oxide, and the oxide may be silicon oxide (SiO2) or aluminum oxide (Al2O3).

[0018] The above antiferroelectric material is PbZrO3, PbHfO3, NaNbO3, AgNbO3, Hf 1-x Zr x O2(0.7 ≤ x ≤ 0.9), Hf 1-xS i x It may be selected from the group consisting of O2 (0.7 ≤ x ≤ 0.9) and HfO2:Si (Si-doped HfO2).

[0019] The gate metal may be tungsten (W), molybdenum (Mo), titanium nitride / tungsten (TiN / W) or molybdenum nitride / molybdenum (MoN / Mo). Effects of the invention

[0020] The present invention has the effect of improving the read disturbance reliability characteristics of a vertical structure memory device through a blocking film having a hybrid double-layer structure of an oxide film / antiferroelectric film. Brief explanation of the drawing

[0021] FIGS. 1A and FIGS. 1B illustrate structural diagrams of a vertical structure memory device according to one embodiment of the present invention. FIGS. 2A and 2B illustrate cross-sections of a vertical structure of a vertical structure memory device according to one embodiment of the present invention. FIGS. 3A and FIGS. 3B illustrate a process diagram of a method for manufacturing a vertical structure memory device according to one embodiment of the present invention. FIG. 4 illustrates a structural diagram of a vertical structure memory device according to another embodiment of the present invention. FIG. 5 illustrates a cross-section of a vertical structure of a vertical structure memory device according to another embodiment of the present invention. FIG. 6 illustrates a process diagram of a method for manufacturing a vertical structure memory device according to another embodiment of the present invention. Specific details for implementing the invention

[0022] Hereinafter, embodiments of the present invention are described in detail so that those skilled in the art can easily implement the invention. However, the present invention may be embodied in various different forms and is not limited to the embodiments described herein.

[0024] Referring to FIG. 1a and FIG. 1b, a vertical structure memory element (10) according to one embodiment of the present invention comprises a substrate (100); a stacked structure (200) formed on the substrate (100); and a vertical structure (300) formed in the vertical direction of the stacked structure (200). The vertical structure memory element (10) according to one embodiment of the present invention may be a vertical NAND flash memory element.

[0026] The substrate (100) may be a silicon substrate, a germanium substrate, a silicon-germanium substrate, a silicon-on-insulator (SOI) substrate, or a germanium-on-insulator (GOI) substrate. The substrate (100) may contain impurities, and the impurities may include p-type impurities (e.g., boron (B)) or n-type impurities (e.g., phosphorus (P), arsenic (As), antimony (Sb), etc.).

[0027] The laminated structure (200) is disposed on the substrate (100), and the surface of the substrate (100) on which the laminated structure (200) is disposed may be referred to as the front side or top surface of the substrate (100).

[0028] The stacked structure (200) may include conductive lines and insulating lines, and may form a memory cell array by alternately forming conductive lines and insulating lines.

[0029] The laminated structure (200) may have a first insulating layer (210) and a second insulating layer (220) sequentially laminated therein. The first insulating layer (210) is intended to block charge to prevent charge leakage and minimize interference between cells, and the second insulating layer (220) may serve as a charge storage layer to provide insulation while trapping electrons and storing data. The second insulating layer (220) may have a relatively higher dielectric constant than the first insulating layer (210). In this case, the first insulating layer (210) and the second insulating layer (220) may be used as insulating lines.

[0030] For example, the first insulating layer (210) may be silicon oxide (SiO2), and the second insulating layer (220) may be silicon nitride (Si3N4). More specifically, the laminated structure (200) may be an ONO (oxide-nitride-oxide) structure in which the silicon oxide (SiO2), which is the first insulating layer (210), is placed at the top and bottom respectively, and the silicon nitride (Si3N4), which is the second insulating layer (220), is placed in the middle.

[0032] Referring to FIGS. 2a and 2b, the vertical structure (300) includes a blocking film (310); a charge storage film (320); a tunneling film (330); a vertical channel film (340); and a filling oxide film (350).

[0033] The blocking film (310) may be disposed on the surface of a vertical sidewall of the stacked structure (200), and may be formed on the surface of one vertical sidewall of the stacked structure (200) and the surface of the other vertical sidewall of the stacked structure (200). As a result, the blocking film (310) may be disposed between the vertical sidewall of the stacked structure (200) and the charge storage film (320).

[0034] The blocking film (310) may be a double-layer structure based on an antiferroelectric material (320), and more specifically, the blocking film (310) may be composed of an oxide (310) and an antiferroelectric material (320), and the arrangement of the oxide (311) and the antiferroelectric material (312) constituting the blocking film (310) can be adjusted with respect to the side wall of the stacked structure (200).

[0035] For example, referring to FIGS. 1a and FIGS. 2a, the blocking film (310) may be formed such that an oxide (311) is formed on the side wall of the stacked structure (200) and an antiferroelectric (312) is formed on the oxide (311). Accordingly, the charge storage film (320) described later may be formed on the antiferroelectric (312).

[0036] As another example, referring to FIGS. 1b and FIGS. 2b, the blocking film (310) may be formed such that an antiferroelectric (312) is formed on the sidewall of the stacked structure (200) and an oxide (311) is formed on the antiferroelectric (312). Accordingly, the charge storage film (320) described later may be formed on the oxide (312).

[0037] The oxide (311) may be silicon oxide (SiO2) or aluminum oxide (Al2O3).

[0038] The antiferroelectric material (312) is PbZrO3, PbHfO3, NaNbO3, AgNbO3, Hf 1-x Zr x O2(0.7 ≤ x ≤ 0.9), Hf 1-xS i x One or more of the group consisting of O2 (0.7 ≤ x ≤ 0.9) and HfO2:Si (Si-doped HfO2) may be selected.

[0039] The charge storage film (320) may be disposed on the surface of the blocking film (310), and more specifically, may be disposed on one vertical side wall of the blocking film (310) and the other vertical side wall of the blocking film (310).

[0040] The charge storage film (320) may be an insulator or a high dielectric material, and may be, for example, silicon nitride (Si3N4), hafnium oxide (HfO₂), aluminum oxide (Al₂O₃) or zirconium oxide (ZrO₂).

[0041] The tunneling film (330) provides a path for electrons to enter or be emitted from the storage layer through a tunneling effect by the gate voltage, thereby preventing electrons from escaping from the storage layer and maintaining data stably. It is designed so that charges are not trapped in the tunneling film itself, thereby increasing reliability in the repetitive program / erase (P / E) cycles of the memory cell.

[0042] The vertical channel membrane (340) may be disposed on the surface of the tunneling membrane (330) and the surface of the substrate (100), and more specifically, may be disposed continuously from one vertical side wall of the tunneling membrane (330) through the surface of the substrate (100) to the other vertical side wall of the tunneling membrane (330), and as an example, may have a “U” shape in cross-section.

[0043] The vertical channel film (340) may include semiconductor materials such as polysilicon (Poly Si), single-crystal silicon, polycrystalline silicon, organic semiconductors, and carbon nanostructures, but is not limited thereto.

[0044] The filling oxide film (350) is intended to fill empty spaces, and the filling oxide film (350) may be an insulating material, and may include silicon oxide, but is not limited thereto.

[0046] Referring to FIG. 3a and FIG. 3b, a method for manufacturing a vertical structure memory device according to one embodiment of the present invention comprises the steps of: forming a stacked structure (200) on a substrate (100) (S110); etching the stacked structure (200) in a vertical direction to form a vertical channel hole (H) (S120); forming a blocking film (310) that is continuous with respect to the sidewall of the stacked structure (200) inside the vertical channel hole (H) and the surface of the substrate (100) (S130); forming a charge storage film (320) on the blocking film (310) (S140); and sequentially depositing a tunneling film (330), a vertical channel film (340), and a filling oxide film (350) on the charge storage film (320) to manufacture a vertical structure (300) (S150).

[0048] S110 is a step of forming a stacked structure (200) on a substrate (100) of a vertical structure memory device.

[0049] In S110, the substrate (100) may be a silicon substrate, a germanium substrate, a silicon-germanium substrate, a silicon-on-insulator (SOI) substrate, or a germanium-on-insulator (GOI) substrate. The substrate (100) may contain impurities, said impurities may include p-type impurities (e.g., boron (B)) or n-type impurities (e.g., phosphorus (P), arsenic (As), antimony (Sb), etc.).

[0050] The laminated structure (200) is disposed on the substrate (100), and the surface of the substrate (100) on which the laminated structure (200) is disposed may be referred to as the front side or top surface of the substrate (100).

[0051] The stacked structure (200) may include conductive lines and insulating lines, and may form a memory cell array by alternately forming conductive lines and insulating lines.

[0052] The laminated structure (200) may have a first insulating layer (210) and a second insulating layer (220) sequentially laminated therein. The first insulating layer (210) is intended to block charge to prevent charge leakage and minimize interference between cells, and the second insulating layer (220) may serve as a charge storage layer to provide insulation while trapping electrons and storing data. The second insulating layer (220) may have a relatively higher dielectric constant than the first insulating layer (210). In this case, the first insulating layer (210) and the second insulating layer (220) may be used as insulating lines.

[0053] For example, the first insulating layer (210) may be silicon oxide (SiO2), and the second insulating layer (220) may be silicon nitride (Si3N4). More specifically, the laminated structure (200) may be an ONO (oxide-nitride-oxide) structure in which the silicon oxide (SiO2), which is the first insulating layer (210), is placed at the top and bottom respectively, and the silicon nitride (Si3N4), which is the second insulating layer (220), is placed in the middle.

[0055] S120 is a step of forming a vertical channel hole (H) through etching on a stacked structure (200) so that a vertical structure (300) can be provided.

[0056] S130 is a step of forming a blocking film (310), wherein the blocking film (310) may be disposed on the surface of a vertical sidewall of a stacked structure (200), and may be continuously formed from the upper surface of one vertical sidewall of the stacked structure (200) through the upper surface of the substrate (100) to the upper surface of the other vertical sidewall of the stacked structure (200), and may have a 'U' shape or a cup shape when observed in cross-section. Accordingly, the blocking film (310) may be disposed between the vertical sidewall of the stacked structure (200) and the charge storage film (320).

[0057] The blocking film (310) may be composed of an oxide (310) and an antiferroelectric (320), and the arrangement of the oxide (311) and the antiferroelectric (312) constituting the blocking film (310) can be adjusted based on the side wall of the stacked structure (200).

[0058] For example, referring to FIG. 3a, the step (S130) of forming the blocking film (310) may be a step (S131) ​​in which an oxide (311) is formed on the side wall of the stacked structure (200) and an antiferroelectric (312) is formed on the oxide (311). Accordingly, the charge storage film (320) described later may be formed (S140) on the antiferroelectric (312).

[0059] As another example, referring to FIG. 3b, the step (S130) of forming the blocking film (310) may be a step (S132) in which an antiferroelectric (312) is formed on the sidewall of the stacked structure (200) and an oxide (311) is formed on the antiferroelectric (312). Accordingly, the charge storage film (320) described later may be formed (S140) on the oxide (312).

[0060] The oxide (311) may be silicon oxide (SiO2) or aluminum oxide (Al2O3).

[0061] The antiferroelectric material (312) is PbZrO3, PbHfO3, NaNbO3, AgNbO3, Hf 1-x Zr x O2(0.7 ≤ x ≤ 0.9), Hf 1-xS i x It may be selected from the group consisting of O2 (0.7 ≤ x ≤ 0.9) and HfO2:Si (Si-doped HfO2).

[0063] S140 is a step of forming a charge storage film (320), wherein the charge storage film (320) may be disposed on the surface of a blocking film (310), and more specifically, may be disposed on one vertical sidewall of the blocking film (310) and the other vertical sidewall of the blocking film (310). As an example, the step of forming the charge storage film (320) (S140) may be formed on the antiferroelectric material (312) among the blocking film (310) formed on S131 (Fig. 3a). Also, as another example, the step of forming the charge storage film (320) (S140) may be formed on the oxide material (311) among the blocking film (310) formed on S132 (Fig. 3b).

[0064] The charge storage film (320) may be an insulator or a high dielectric material, and may be, for example, silicon nitride (Si3N4), hafnium oxide (HfO₂), aluminum oxide (Al₂O₃) or zirconium oxide (ZrO₂).

[0066] S150 is a step of providing a vertical structure (300) in which a blocking film (310); a charge storage film (320); a tunneling film (330); a vertical channel film (340); and a filling oxide film (350) are sequentially formed in a vertical direction by stacking a tunneling film (330); a vertical channel film (340); and a filling oxide film (350) sequentially.

[0067] More specifically, in S150, when a vertical channel film (340) is placed, etching is performed on the area stacked vertically with respect to the surface of the substrate (100) for the blocking film (310); charge storage film (320); and tunneling film (330) placed in the previous step, and after etching the blocking film (310); charge storage film (320); and tunneling film (330) until the surface of the substrate (100) is exposed, a vertical channel film (340) is deposited on the exposed surface of the substrate (100).

[0068] The vertical channel film (340) may include semiconductor materials such as polysilicon (Poly Si), single-crystal silicon, polycrystalline silicon, organic semiconductors, and carbon nanostructures, but is not limited thereto.

[0069] The filling oxide film (350) is intended to fill empty spaces, and the filling oxide film (350) may be an insulating material, and may include silicon oxide, but is not limited thereto.

[0071] The formation or arrangement of each unit configuration in the above-described S110 to S150 may be performed by deposition, and the deposition may be performed by LPCVD (Low Pressure Chemical Vapor Deposition) or ALD (Atomic Layer Deposition). The LPCVD may be performed at 700 to 800 ℃, and the ALD may be performed at 200 to 400 ℃.

[0073] Referring to FIG. 4, a vertical structure memory device (10) according to another embodiment of the present invention comprises a substrate (100); a stacked structure (200) formed on the substrate (100); and a vertical structure (300) formed in the vertical direction of the stacked structure (200). A vertical structure memory device (10) according to one embodiment of the present invention may be a vertical NAND flash memory device.

[0075] The substrate (100) may be a silicon substrate, a germanium substrate, a silicon-germanium substrate, a silicon-on-insulator (SOI) substrate, or a germanium-on-insulator (GOI) substrate. The substrate (100) may contain impurities, and the impurities may include p-type impurities (e.g., boron (B)) or n-type impurities (e.g., phosphorus (P), arsenic (As), antimony (Sb), etc.).

[0076] The laminated structure (200) is disposed on the substrate (100), and the surface of the substrate (100) on which the laminated structure (200) is disposed may be referred to as the front side or top surface of the substrate (100).

[0077] The stacked structure (200) may include conductive lines and insulating lines, and may form a memory cell array by alternately forming conductive lines and insulating lines.

[0078] The laminated structure (200) may have a first insulating layer (210) and a gate metal (230) sequentially laminated.

[0079] The first insulating layer (210) is intended to block charge to prevent charge leakage and minimize interference between cells, and the first insulating layer (210) may be used as an insulating line. As an example, the first insulating layer (210) may be silicon oxide (SiO2).

[0080] The gate metal (230) may serve as a gate electrode and control operations such as programming (Write), erasing (Erase), and reading by transmitting a voltage given from the outside to the transistor channel, and the gate metal (230) may be tungsten (W), titanium nitride (TiN), or tantalum nitride (TaN).

[0081] Referring to FIG. 5, the stacked structure (200) may further include a first insulating layer (210); a gate metal (230); and an antiferroelectric material (240). More specifically, the antiferroelectric material (240) may be disposed between the first insulating layer (210) and the gate metal (230), and simultaneously between the blocking film (310) and the gate metal (230). More specifically, the antiferroelectric material (240) may be disposed such that the gate metal (230) does not come into contact with the oxide (311) as the first insulating layer (210) and the blocking film (310) described later. Accordingly, the antiferroelectric material (240) and the blocking film (310) may be arranged to be in contact with each other to form a double-layer structure, and the antiferroelectric material (240) may be arranged continuously on the surface of the first insulating layer (210) and the surface of the blocking film (310).

[0083] The antiferroelectric material (240) is PbZrO3, PbHfO3, NaNbO3, AgNbO3, Hf 1-x Zr x O2(0.7 ≤ x ≤ 0.9), Hf 1-xS i x It may be selected from the group consisting of O2 (0.7 ≤ x ≤ 0.9) and HfO2:Si (Si-doped HfO2).

[0085] Referring to FIG. 5, the vertical structure (300) includes a blocking film (310); a charge storage film (320); a tunneling film (330); a vertical channel film (340); and a filling oxide film (350).

[0086] The blocking film (310) may be disposed on the surface of a vertical sidewall of the stacked structure (200), and may be formed on the surface of one vertical sidewall of the stacked structure (200) and the surface of the other vertical sidewall of the stacked structure (200). As a result, the blocking film (310) may be disposed between the vertical sidewall of the stacked structure (200) and the charge storage film (320).

[0087] The blocking film (310) may be composed of an oxide (310). The blocking film (310) may be in contact with the first insulating layer (210) and the antiferroelectric material (240), and may be spaced apart from the gate metal (230). The oxide (311) may be silicon oxide (SiO2) or aluminum oxide (Al2O3).

[0088] The charge storage film (320) may be disposed on the surface of the blocking film (310), and more specifically, may be disposed on one vertical side wall of the blocking film (310) and the other vertical side wall of the blocking film (310).

[0089] The charge storage film (320) may be an insulator or a high dielectric material, and may be, for example, silicon nitride (Si3N4), hafnium oxide (HfO₂), aluminum oxide (Al₂O₃) or zirconium oxide (ZrO₂).

[0090] The tunneling film (330) provides a path for electrons to enter or be emitted from the storage layer through a tunneling effect by the gate voltage, thereby preventing electrons from escaping from the storage layer and maintaining data stably. It is designed so that charges are not trapped in the tunneling film itself, thereby increasing reliability in the repetitive program / erase (P / E) cycles of the memory cell.

[0091] The vertical channel membrane (340) may be disposed on the surface of the tunneling membrane (330) and the surface of the substrate (100), and more specifically, may be disposed continuously from one vertical side wall of the tunneling membrane (330) through the surface of the substrate (100) to the other vertical side wall of the tunneling membrane (330), and as an example, may have a “U” shape in cross-section.

[0092] The vertical channel film (340) may include semiconductor materials such as polysilicon (Poly Si), single-crystal silicon, polycrystalline silicon, organic semiconductors, and carbon nanostructures, but is not limited thereto.

[0093] The filling oxide film (350) is intended to fill empty spaces, and the filling oxide film (350) may be an insulating material, and may include silicon oxide, but is not limited thereto.

[0095] Referring to FIG. 6, a method for manufacturing a vertical structure memory device according to an embodiment of the present invention comprises the steps of: forming a stacked structure (200) in which a first insulating layer (210) and a second insulating layer (220) are sequentially stacked on a substrate (100) (S210); etching the stacked structure (200) in a vertical direction to form a vertical channel hole (H) (S220); forming a blocking film (310) that is continuous with respect to the sidewall of the stacked structure (200) inside the vertical channel hole (H) and the surface of the substrate (100) (S230); forming a charge storage film (320) on the blocking film (310) (S240); and sequentially depositing a tunneling film (330), a vertical channel film (340), and a filling oxide film (350) on the charge storage film (320) to manufacture a vertical structure (300) (S250). The method includes the step (S260) of etching a second insulator (220) of a stacked structure (200) to form a gate metal forming portion (230a); the step (S270) of depositing a semiferroelectric material (240) on a first insulator (210) and a blocking film (310) within the gate metal forming portion (230a); and the step (S280) of depositing a gate metal (230) on the gate metal forming portion (230a).

[0097] S210 is a step of forming a stacked structure (200) on a substrate (100) of a vertical structure memory device.

[0098] In S210, the substrate (100) may be a silicon substrate, a germanium substrate, a silicon-germanium substrate, a silicon-on-insulator (SOI) substrate, or a germanium-on-insulator (GOI) substrate. The substrate (100) may contain impurities, and the impurities may include p-type impurities (e.g., boron (B)) or n-type impurities (e.g., phosphorus (P), arsenic (As), antimony (Sb), etc.).

[0099] The laminated structure (200) is disposed on the substrate (100), and the surface of the substrate (100) on which the laminated structure (200) is disposed may be referred to as the front side or top surface of the substrate (100).

[0100] The stacked structure (200) may include conductive lines and insulating lines, and may form a memory cell array by alternately forming conductive lines and insulating lines.

[0101] The laminated structure (200) may have a first insulating layer (210) and a second insulating layer (220) sequentially laminated therein. The first insulating layer (210) is intended to block charge to prevent charge leakage and minimize interference between cells, and the second insulating layer (220) may serve as a charge storage layer to provide insulation while trapping electrons and storing data. The second insulating layer (220) may have a relatively higher dielectric constant than the first insulating layer (210). In this case, the first insulating layer (210) and the second insulating layer (220) may be used as insulating lines.

[0102] For example, the first insulating layer (210) may be silicon oxide (SiO2), and the second insulating layer (220) may be silicon nitride (Si3N4). More specifically, the laminated structure (200) may be an ONO (oxide-nitride-oxide) structure in which the silicon oxide (SiO2), which is the first insulating layer (210), is placed at the top and bottom respectively, and the silicon nitride (Si3N4), which is the second insulating layer (220), is placed in the middle.

[0104] S220 is a step of forming a vertical channel hole (H) through etching on a stacked structure (200) so that a vertical structure (300) can be provided.

[0105] S230 is a step of forming a blocking film (310), wherein the blocking film (310) may be disposed on the surface of a vertical sidewall of a stacked structure (200), and may be formed continuously from the upper surface of one vertical sidewall of the stacked structure (200) through the upper surface of the substrate (100) to the upper surface of the other vertical sidewall of the stacked structure (200), and may have a 'U' shape or a cup shape when observed in cross-section. Accordingly, the blocking film (310) may be disposed between the vertical sidewall of the stacked structure (200) and the charge storage film (320).

[0106] The blocking film (310) may be composed of an oxide (310). The blocking film (310) may be in contact with the first insulating layer (210) and the antiferroelectric material (240), and may be spaced apart from the gate metal (230). The oxide (311) may be silicon oxide (SiO2) or aluminum oxide (Al2O3). The oxide (311) of the blocking film (310) and the antiferroelectric material (240) are in contact, so the blocking film (310) may provide a structure in which the oxide (311) and the antiferroelectric material (240) are in contact.

[0108] S240 is a step of forming a charge storage film (320), wherein the charge storage film (320) may be disposed on the surface of a blocking film (310), and more specifically, may be disposed on one vertical side wall of the blocking film (310) and the other vertical side wall of the blocking film (310).

[0109] The charge storage film (320) may be an insulator or a high dielectric material, and may be, for example, silicon nitride (Si3N4), hafnium oxide (HfO₂), aluminum oxide (Al₂O₃) or zirconium oxide (ZrO₂).

[0111] S250 is a step of providing a vertical structure (300) in which a blocking film (310); a charge storage film (320); a tunneling film (330); a vertical channel film (340); and a filling oxide film (350) are sequentially formed in a vertical direction by sequentially stacking a tunneling film (330); a vertical channel film (340); and a filling oxide film (350).

[0112] More specifically, in S250, when a vertical channel film (340) is placed, etching is performed on the blocking film (310); charge storage film (320); and tunneling film (330) placed in the previous step in a region stacked vertically with respect to the surface of the substrate (100), and after etching the blocking film (310); charge storage film (320); and tunneling film (330) until the surface of the substrate (100) is exposed, a vertical channel film (340) is deposited on the exposed surface of the substrate (100).

[0113] The vertical channel film (340) may include semiconductor materials such as polysilicon (Poly Si), single-crystal silicon, polycrystalline silicon, organic semiconductors, and carbon nanostructures, but is not limited thereto.

[0114] The filling oxide film (350) is intended to fill empty spaces, and the filling oxide film (350) may be an insulating material, and may include silicon oxide, but is not limited thereto.

[0116] S260 is a step of providing a gate metal forming part (230a) by removing the second insulating layer (220) while leaving only the first insulating layer (210) on the stacked structure (200). The gate metal forming part (230a) provides an empty space for the gate metal (230) to be placed or formed, and the surface of the first insulating layer (210) and a portion of the surface of the blocking film (310) may be exposed by the gate metal forming part (230a).

[0118] S270 is a step of forming an antiferroelectric material (240) on the surface of the first insulating layer (210) and the surface of the blocking film (310) exposed by the gate metal forming portion (230a) formed in S260. In S270, the antiferroelectric material (240) may be formed in the form of a layer with a predetermined thickness, and the antiferroelectric material (240) may be formed to provide a space where the gate metal (230) can be disposed in S280, which will be described later. The antiferroelectric material (240) may be PbZrO3, PbHfO3, NaNbO3, AgNbO3, Hf 1-x Zr x O2(0.7 ≤ x ≤ 0.9), Hf 1-xS i x It may be selected from the group consisting of O2 (0.7 ≤ x ≤ 0.9) and HfO2:Si (Si-doped HfO2).

[0119] S280 may be a gate metal (230) placed on a gate metal forming portion (230a) so as to be in contact with the antiferroelectric material (240) formed in S270. Accordingly, the gate metal (230) may be separated from the first insulator (210) and the blocking film (310) by the antiferroelectric material (240). The gate metal (230) may serve as a gate electrode and control operations such as programming (Write), erasing (Erase), and reading data by transmitting a voltage given from an external source to the transistor channel. The gate metal (230) may be tungsten (W), molybdenum (Mo), titanium nitride / tungsten (TiN / W), or molybdenum nitride / molybdenum (MoN / Mo). The titanium nitride / tungsten (TiN / W) may be formed by depositing tungsten (W) after depositing titanium nitride (TiN), and the molybdenum nitride / molybdenum (MoN / Mo) may be formed by depositing molybdenum (Mo) after depositing molybdenum nitride (MoN).

[0121] The formation or arrangement of each unit configuration in the above-described S210 to S280 may be performed by deposition, and the deposition may be performed by LPCVD (Low Pressure Chemical Vapor Deposition) or ALD (Atomic Layer Deposition). The LPCVD may be performed at 700 to 800 ℃, and the ALD may be performed at 200 to 400 ℃.

[0123] The present invention will be described in detail below through examples. The following examples are intended only to aid in understanding the present invention and do not limit the scope of the present invention, and the same

[0125] Example 1. Method for manufacturing a vertical NAND flash memory device

[0126] Referring to FIG. 3a, Example 1 will be described.

[0127] As a substrate (100), a silicon substrate (Si wafer) is sequentially stacked with SiO2 (210) and Si3N4 (220) to form a stacked structure (200). The stacked structure (200) is formed such that SiO2 (210) is placed on the surface of the silicon substrate (Si wafer), Si3N4 (220) is placed on the surface of SiO2 (210), and SiO2 (210) is placed again on the Si3N4 (220), thereby forming an ONO (oxide-nitride-oxide) mold structure in which SiO2-Si3N4-SiO2 are sequentially stacked from the substrate (100) (S110).

[0128] Afterwards, a vertical channel hole (H) is formed through etching (S120), and then an oxide SiO2 (311) is formed along the vertical sidewall of the stacked structure (200) formed along the vertical channel hole (H), and then Hf as an antiferroelectric material is formed on the SiO2 (311). 1-x Zr xO2 (0.7 ≤ x ≤ 0.9) (312) is formed to form a blocking film (310) (S131). Si3N4 (320) is formed as a vertical charge storage film on the surface of the blocking film (310) (S140).

[0129] Subsequently, a SiO2 layer (330) as a tunneling film and a polysilicon (Poly-Si) (340) as a vertical channel film are sequentially deposited on the surface of the vertical charge storage film, and then a filling oxide film (SiO2) (350) is deposited in the empty space formed on the surface of the vertical channel film to fabricate a vertical NAND flash memory device (10) (S150). At this time, when depositing the vertical channel film (340), the charge storage film (320) and the tunneling film (330) are etched on the surface of the substrate (100) to expose the surface of the substrate (100), and then the vertical channel film (340) is deposited so that it comes into contact with the substrate (100).

[0130] In Example 1, SiO2, Si3N4 and Hf 1-x Zr x Deposition of O2 (0.7 ≤ x ≤ 0.9) is performed at 200 to 400 ℃ via ALD (Atomic Layer deposition).

[0132] Example 2. Method for manufacturing a vertical NAND flash memory device

[0133] The procedure is performed in the same manner as in Example 1, except that, with reference to FIG. 3b, a vertical channel hole (H) is formed through etching (S120), and then Hf as an antiferroelectric material is formed along the vertical sidewall of the stacked structure (200) formed along the vertical channel hole (H). 1-x Zr x After forming O2 (0.7 ≤ x ≤ 0.9) (312), a SiO2 (311) phase is formed on the antiferroelectric (312) to form a blocking film (310) (S131).

[0135] Example 3. Method for manufacturing a vertical NAND flash memory device

[0136] Referring to FIG. 6, Example 3 will be described.

[0137] As a substrate (100), a silicon substrate (Si wafer) is sequentially stacked with SiO2 (210) and Si3N4 (220) to form a stacked structure (200). The stacked structure (200) is formed such that SiO2 (210) is placed on the surface of the silicon substrate (Si wafer), Si3N4 (220) is placed on the surface of SiO2 (210), and SiO2 (210) is placed again on the Si3N4 (220), thereby forming an ONO (oxide-nitride-oxide) mold structure in which SiO2-Si3N4-SiO2 are sequentially stacked from the substrate (100) (S210).

[0138] After that, a vertical channel hole (H) is formed through etching (S220), and then an oxide SiO2 (311) is formed as a blocking film along the vertical sidewall of the stacked structure (200) formed along the vertical channel hole (H) (S230). Then, a Si3N4 (320) is formed as a vertical charge storage film on the surface of the SiO2 (311) (S240).

[0139] Afterward, a SiO2 layer (330) as a tunneling film and a polysilicon (Poly-Si) (340) as a vertical channel film are sequentially deposited on the surface of the vertical charge storage film, and then a filling oxide film (SiO2) (350) is deposited in the empty space formed on the surface of the vertical channel film (S250). At this time, when depositing the vertical channel film (340), the charge storage film (320) and the tunneling film (330) are etched on the surface of the substrate (100) so that the surface of the substrate (100) is exposed, and then the vertical channel film (340) is deposited so that it comes into contact with the substrate (100).

[0140] Subsequently, Si3N4 (220) is etched and removed from the stacked structure (200) to form a gate metal forming portion (230a) which is an empty space (S260), and Hf as an antiferroelectric material is applied to the surface of SiO2 (210) of the stacked structure (200) exposed by the gate metal forming portion (230a) and the surface of SiO2 (311) as a blocking film. 1-x Zr xAfter depositing O2 (0.7 ≤ x ≤ 0.9) (240) (S270), a vertical NAND flash memory device (10) is fabricated by depositing TiN / W (230) as a gate metal on a gate metal forming part (230a) so as to be in contact with the antiferroelectric material (240) (S280).

[0141] In Example 3, SiO2, Si3N4, and Hf 1-x Zr x The deposition of O2 (0.7 ≤ x ≤ 0.9) is performed at 200 to 400 ℃ via ALD (Atomic Layer deposition), and the deposition of TiN / W is performed at 700 to 800 ℃ via LPCVD (Low Pressure Chemical Vapor Deposition).

[0143] Although preferred embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements by those skilled in the art using the basic concept of the present invention as defined in the following claims also fall within the scope of the present invention. Explanation of the symbols

[0145] 10: Vertical NAND flash memory device 100 : Substrate 200 : Laminated structure 300 : Vertical structure

Claims

Claim 1 delete Claim 2 delete Claim 3 delete Claim 4 delete Claim 5 delete Claim 6 delete Claim 7 A vertical structure memory device comprising: a substrate; a stacked structure formed on the substrate, wherein an insulating layer and a gate metal are sequentially formed in a vertical direction; and a vertical channel structure formed in a vertical direction of the stacked structure, wherein the vertical channel structure includes a blocking film formed on a side wall of the stacked structure, and wherein the stacked structure includes a first insulating layer; a gate metal and an antiferroelectric material, wherein the antiferroelectric material is disposed between the first insulating layer and the gate metal and simultaneously disposed between the blocking film and the gate metal, and wherein the antiferroelectric material and the blocking film are disposed to be in contact with each other to form a double-layer structure. Claim 8 A vertical structure memory device according to claim 7, wherein the blocking film comprises an oxide, and the oxide is silicon oxide (SiO2) or aluminum oxide (Al2O3). Claim 9 In claim 7, the above antiferroelectric material is PbZrO3, PbHfO3, NaNbO3, AgNbO3, Hf 1-x Zr x O2(0.7 ≤ x ≤ 0.9), Hf 1-xS i x A vertical structure memory device selected from the group consisting of O2 (0.7 ≤ x ≤ 0.9) and HfO2:Si (Si-doped HfO2). Claim 10 A vertical structure memory device according to claim 7, wherein the gate metal is tungsten (W), molybdenum (Mo), titanium nitride / tungsten (TiN / W) or molybdenum nitride / molybdenum (MoN / Mo).

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