Display device and tiled display including the same

Abstract

A display device according to one embodiment includes a first subpixel and a second subpixel emitting different light, wherein the first subpixel comprises a first anode pad electrode and a second anode pad electrode disposed apart from each other on a plane, a first cathode pad electrode disposed apart from the first anode pad electrode and the second anode pad electrode on a plane, and a first light-emitting element comprising a first sub-light-emitting element disposed on the first anode pad electrode and the cathode pad electrode and a second sub-light-emitting element disposed on the second anode pad electrode and the cathode pad electrode. The area of ​​the first cathode pad electrode is larger than the area of ​​the first anode pad electrode or the area of ​​the second anode pad electrode. The first sub-light-emitting element and the second sub-light-emitting element emit light at different times. The first sub-light-emitting element and the second sub-light-emitting element emit the same light.

Description

Technology Field

[0001] The present invention relates to a display device and a tile-type display device including the same. Background Technology

[0002] As the information society develops, the demand for display devices to display images is increasing in various forms. Display devices may be flat panel display devices such as Liquid Crystal Displays, Field Emission Displays, and Light Emitting Displays.

[0003] The light-emitting display device may include an organic light-emitting display device comprising an organic light-emitting diode element as a light-emitting element, or a light-emitting diode display device comprising an inorganic light-emitting diode element such as an LED (Light Emitting Diode) as a light-emitting element. As the temperature of the inorganic light-emitting diode increases due to heat generation by the inorganic light-emitting diode element, the luminous efficiency of the inorganic light-emitting diode element may decrease. The problem to be solved

[0004] The problem that the present invention aims to solve is to provide a display device capable of reducing or preventing the decrease in luminous brightness of an inorganic light-emitting diode device caused by heat generation of the inorganic light-emitting diode device, and a tile-type display device including the same.

[0005] The problems of the present invention are not limited to those mentioned above, and other unmentioned technical problems will be clearly understood by those skilled in the art from the description below. means of solving the problem

[0006] A display device according to one embodiment for solving the above problem includes a first subpixel and a second subpixel emitting different light, wherein the first subpixel comprises a first anode pad electrode and a second anode pad electrode disposed apart from each other on a plane, a first cathode pad electrode disposed apart from the first anode pad electrode and the second anode pad electrode on a plane, and a first light-emitting element comprising a first sub-light-emitting element disposed on the first anode pad electrode and the cathode pad electrode and a second sub-light-emitting element disposed on the second anode pad electrode and the cathode pad electrode. The area of ​​the first cathode pad electrode is larger than the area of ​​the first anode pad electrode or the area of ​​the second anode pad electrode. The first sub-light-emitting element and the second sub-light-emitting element emit light during different periods. The first sub-light-emitting element and the second sub-light-emitting element emit the same light.

[0007] The length of one direction of the first cathode pad electrode may be greater than the length of one direction of the first anode pad electrode or the length of one direction of the second anode pad electrode.

[0008] The second subpixel may include a third anode pad electrode, a second cathode pad electrode disposed apart from the third anode pad electrode, and a second light-emitting element disposed on the third anode pad electrode and the second cathode pad electrode.

[0009] The area of ​​the first cathode pad electrode may be larger than the area of ​​the second cathode pad electrode.

[0010] The length of one direction of the first cathode pad electrode may be greater than the length of one direction of the second cathode pad electrode.

[0011] The apparatus may include a third subpixel emitting light different from the first subpixel and the second subpixel, and the third subpixel may include a fourth anode pad electrode, a third cathode pad electrode disposed apart from the third anode pad electrode on a plane, and a third light-emitting element disposed on the third anode pad electrode and the third cathode pad electrode.

[0012] The area of ​​the first cathode pad electrode may be larger than the area of ​​the third cathode pad electrode.

[0013] The length of one direction of the first cathode pad electrode may be greater than the length of one direction of the third cathode pad electrode.

[0014] The first sub-lighting element and the second sub-lighting element emit a first light, the second light-emitting element emits a second light, and the third light-emitting element can emit a third light.

[0015] The first light may be red light, the second light may be green light, and the third light may be blue light.

[0016] A display device according to one embodiment for solving the above problem comprises a first data line to which a first data voltage is applied, a second data line to which a second data voltage is applied, a first light emission control line to which a first light emission control signal is applied, a second light emission control line to which a second light emission control signal is applied, and a first subpixel connected to the first data line, the second data line, the first light emission control line, and the second light emission control line. The first subpixel comprises a first light-emitting element including a first sub-light-emitting element and a second sub-light-emitting element that emits a first light, a first pixel driving unit that generates a control current according to the first data voltage of the first data line, a second pixel driving unit that generates a driving current applied to the first sub-light-emitting element or the second sub-light-emitting element according to the second data voltage of the second data line, and a third pixel driving unit that controls the period for applying the first driving current to the first sub-light-emitting element or the second sub-light-emitting element according to the control current of the first pixel driving unit. The third pixel driver comprises a first transistor that supplies a first driving current to the first light-emitting element according to the first light-emitting control signal, and a second transistor that supplies the first driving current to the second light-emitting element according to the second light-emitting control signal. The first light-emitting control signal has a gate-on voltage during the Nth frame period and a gate-off voltage during the N+1th frame period. The second light-emitting control signal has the gate-off voltage during the Nth frame period and the gate-on voltage during the N+1th frame period.

[0017] The first initialization signal wiring to which a first initialization signal is applied, and the initialization voltage wiring to which an initialization voltage is applied may be further provided. The first subpixel may further include a third transistor that supplies the initialization voltage to the first electrode of the first sub-light-emitting element according to the first initialization signal, and a fourth transistor that supplies the initialization voltage to the first electrode of the second light-emitting element according to the first initialization signal.

[0018] The device may further comprise a light-emitting signal wiring to which a light-emitting signal is applied, and a second subpixel connected to the light-emitting signal wiring and the first initialization signal wiring. The second subpixel may include a second light-emitting element that emits a second light, a fifth transistor that supplies a second driving current to the second light-emitting element according to the first light-emitting signal, and a sixth transistor that supplies an initialization voltage to the first electrode of the second light-emitting element according to the first initialization signal.

[0019] The first light is red light, and the second light may be green light or blue light.

[0020] A display device according to one embodiment for solving the above problem comprises a first data line to which a first data voltage is applied, a second data line to which a second data voltage is applied, a first light emission control line to which a first light emission control signal is applied, a second light emission control line to which a second light emission control signal is applied, and a first subpixel connected to the first data line, the second data line, the first light emission control line, and the second light emission control line. The first subpixel comprises a first light-emitting element including a first sub-light-emitting element and a second sub-light-emitting element that emits a first light, a first pixel driving unit that generates a control current according to the first data voltage of the first data line, a second pixel driving unit that generates a driving current applied to the first sub-light-emitting element or the second sub-light-emitting element according to the second data voltage of the second data line, and a third pixel driving unit that controls the period for applying the first driving current to the first sub-light-emitting element or the second sub-light-emitting element according to the control current of the first pixel driving unit. The third pixel driver includes a first transistor that supplies a first driving current to the first sub-lighting element according to the first light emission signal, and a second transistor that supplies the first driving current to the second light emission element according to the second light emission signal. A frame period includes a plurality of light emission periods, and the first transistor and the second transistor are turned on during different light emission periods among the plurality of light emission periods.

[0021] The first transistor may be turned on during odd-numbered emission periods among the plurality of emission periods, and the second transistor may be turned on during excellent-numbered emission periods among the plurality of emission periods.

[0022] Among the plurality of light emission periods, during odd light emission periods, the first light emission signal has a gate-on voltage and the second light emission signal has a gate-off voltage, and among the plurality of light emission periods, during even light emission periods, the second light emission signal has the gate-on voltage and the first light emission signal may have the gate-off voltage.

[0023] The first initialization signal wiring to which a first initialization signal is applied, and the initialization voltage wiring to which an initialization voltage is applied may be further provided. The first subpixel may further include a third transistor that supplies the initialization voltage to the first electrode of the first sub-light-emitting element according to the first initialization signal, and a fourth transistor that supplies the initialization voltage to the first electrode of the second light-emitting element according to the first initialization signal.

[0024] A second subpixel connected to the first light-emitting signal wiring and the second light-emitting signal wiring may be further provided. The second subpixel may include a second light-emitting element that emits a second light, a fifth transistor that supplies a second driving current to the second light-emitting element according to the first light-emitting control signal, and a sixth transistor that supplies a second driving current to the second light-emitting element according to the second light-emitting control signal.

[0025] The first initialization signal wiring to which a first initialization signal is applied and the initialization voltage wiring to which an initialization voltage is applied may be further provided. The second subpixel may further include a seventh transistor that supplies the initialization voltage to the first electrode of the second light-emitting element according to the first initialization signal.

[0026] The first light is red light, and the second light may be green light or blue light.

[0027] Specific details of other embodiments are included in the detailed description and drawings. Effects of the invention

[0028] According to the display device and tile-type display device according to the embodiments, a subpixel emitting red light includes a first sub-light-emitting element and a second sub-light-emitting element that emit light for different periods. As a result, the light emission period of the first sub-light-emitting element and the light emission period of the second sub-light-emitting element of the first subpixel emitting red light can be reduced to half compared to the light emission period of the light-emitting element of the subpixel emitting green light or blue light. Therefore, since the amount of heat generated by the first sub-light-emitting element and the second sub-light-emitting element can be reduced, the temperature of the first sub-light-emitting element and the temperature of the second sub-light-emitting element can be lowered. Consequently, it is possible to reduce or prevent the decrease in the luminous brightness of the first sub-light-emitting element and the second sub-light-emitting element caused by the heat generated by the first sub-light-emitting element emitting red light and the heat generated by the second sub-light-emitting element.

[0029] The effects according to the embodiments are not limited to those exemplified above, and a wider variety of effects are included in this specification. Brief explanation of the drawing

[0030] FIG. 1 is a plan view showing a display device according to one embodiment. FIG. 2 is an example drawing showing one example of a pixel of FIG. 1. FIG. 3 is an example drawing showing another example of a pixel of FIG. 1. FIG. 4 is a block diagram showing a display device according to one embodiment. FIG. 5 is a graph showing the luminous efficiency according to temperature of a first light-emitting element, a second light-emitting element, and a third light-emitting element according to one embodiment. FIG. 6 is a circuit diagram showing a first sub-pixel according to one embodiment. FIG. 7 is a circuit diagram showing a second sub-pixel according to one embodiment. FIG. 8 is a circuit diagram showing a third sub-pixel according to one embodiment. FIG. 9 is an example drawing showing the operation of a display device during the N to N+2 frame period. FIG. 10 is another example drawing showing the operation of a display device during the N to N+2 frame period. FIG. 11 is a k-th scan initialization signal, a k-th scan write signal, and a k-th scan control applied to a first sub-pixel placed on a k-th row line during the N and N+1 frame periods according to one embodiment. FIG. 12 is a waveform diagram showing a signal, the k-th PWM light emission signal, the k-th PAM light emission signal, the k-th sweep signal, the voltage of the third node, the light emission timing of the light-emitting element, the first light emission control signal, and the second light emission control signal. FIG. 12 is a timing diagram showing the k-th sweep signal, the voltage of the gate electrode of the first transistor, the turn-on timing of the first transistor, and the turn-on timing of the 15th transistor during the fifth and sixth periods according to one embodiment. FIG. 13 to 16 are circuit diagrams showing the operation of the first subpixel during the first period, the second period, the third period, the fifth period, and the sixth period of the N-th frame period of FIG. 11. FIG. 17 is a circuit diagram showing the operation of the first subpixel during the sixth period of the N+1-th frame period of FIG. 11. FIG. 18 is a circuit diagram showing the operation of the second subpixel during the sixth period of the N-th frame period and the N+1-th frame period of FIG. 11.FIGS. 19 and FIGS. 20 are layout diagrams showing pixels according to one embodiment. FIG. 21 is an enlarged layout diagram showing area A of FIG. 19 in detail. FIG. 22 is an enlarged layout diagram showing area B of FIG. 19 in detail. FIG. 23 is an enlarged layout diagram showing area A of FIG. 20 in detail. FIG. 24 is an enlarged layout diagram showing area C of FIG. 19 in detail. FIG. 25 is an enlarged layout diagram showing area D of FIG. 19 in detail. FIG. 26 is an enlarged layout diagram showing area C of FIG. 20 in detail. FIG. 27 is a cross-sectional view showing an example of a display panel cut along A-A' of FIG. 21. FIG. 28 is a cross-sectional view showing an example of a display panel cut along B-B' of FIG. 21 and FIG. 23. FIG. 29 is a circuit diagram showing a first subpixel according to one embodiment. FIG. 30 is a circuit diagram showing a second subpixel according to one embodiment. FIG. 31 shows a third subpixel according to one embodiment. FIG. 32 is a waveform diagram showing the period during which a k-th scan initialization signal, a k-th scan write signal, a k-th scan control signal, a k-th PWM light emission signal, a k-th PAMA light emission signal, a k-th PAMB light emission signal, and a k-th sweep signal are applied to a first subpixel placed on a k-th row line during an N-th frame period according to one embodiment, and the voltage of a third node and a driving current applied to a light-emitting element are applied. FIG. 33 is an example diagram showing a PAMA light emission signal output unit and a PAMB light emission signal output unit according to one embodiment. FIG. 34 is a waveform diagram showing PAMA clock signals and PAMB clock signals according to one embodiment. FIG. 35 is a perspective view showing a tile-type display device including a plurality of display devices according to one embodiment. FIG. 36 is an enlarged layout diagram showing region E of FIG. 35 in detail. FIG. 37 is a cross-sectional view showing an example of a tile-type display device cut along E-E' of FIG. 36. FIG. 38 is an enlarged layout diagram showing region F of FIG. 35 in detail.FIG. 39 is a cross-sectional view showing an example of a tile-type display device cut along I-I' of FIG. 38. FIG. 40 is a block diagram showing a tile-type display device according to one embodiment. Specific details for implementing the invention

[0031] The advantages and features of the present invention and the methods for achieving them will become clear by referring to the embodiments described below in detail together with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below but may be implemented in various different forms. These embodiments are provided merely to ensure that the disclosure of the present invention is complete and to fully inform those skilled in the art of the scope of the invention, and the present invention is defined only by the scope of the claims.

[0032] When elements or layers are referred to as being "on" another element or layer, this includes cases where another layer or element is interposed directly on or in the middle of another element. Throughout the specification, the same reference numerals refer to the same components. Shapes, sizes, ratios, angles, numbers, etc., disclosed in the drawings for describing embodiments are exemplary and therefore the invention is not limited to the depicted details.

[0033] Although terms such as "first," "second," etc., are used to describe various components, it goes without saying that these components are not limited by these terms. These terms are used merely to distinguish one component from another. Therefore, it goes without saying that the first component mentioned below may also be the second component within the technical scope of the present invention.

[0034] The features of each of the various embodiments of the present invention may be combined or combined with one another, either partially or wholly, and may technically enable various interlocking and operation. Each embodiment may be implemented independently of one another or may be implemented together in an associated relationship.

[0035] Specific embodiments will be described below with reference to the attached drawings.

[0036] FIG. 1 is a plan view showing a display device according to one embodiment. FIG. 2 is an example drawing showing one example of a pixel of FIG. 1. FIG. 3 is an example drawing showing another example of a pixel of FIG. 1.

[0037] Referring to FIGS. 1 to 3, the display device (10) is a device for displaying video or still images and can be used as a display screen for various products such as televisions, laptops, monitors, billboards, and the Internet of Things (IOT), as well as portable electronic devices such as mobile phones, smartphones, tablet PCs, smart watches, watch phones, mobile communication terminals, electronic notebooks, electronic books, PMPs (portable multimedia players), navigation systems, and UMPCs (Ultra Mobile PCs).

[0038] The display panel (100) may be formed as a rectangular plane having a long side in a first direction (DR1) and a short side in a second direction (DR2) that intersects the first direction (DR1). The corner where the long side in the first direction (DR1) and the short side in the second direction (DR2) meet may be formed rounded to have a predetermined curvature or formed at a right angle. The plane shape of the display panel (100) is not limited to a rectangle and may be formed as other polygons, circles, or ellipses. The display panel (100) may be formed flat, but is not limited thereto. For example, the display panel (100) may include curved surfaces formed at the left and right ends that have a constant curvature or a changing curvature. In addition, the display panel (100) may be formed flexibly so that it can be bent, curved, folded, or rolled.

[0039] The display panel (100) may further include pixels (PX), scan lines extending in a first direction (DR1), and data lines extending in a second direction (DR2) to display an image. The pixels (PX) may be arranged in a matrix form in the first direction (DR1) and the second direction (DR2).

[0040] Each of the pixels (PX) may include a plurality of subpixels (RP, GP, BP) as shown in FIGS. 2 and FIGS. 3. FIGS. 2 and FIGS. 3 illustrate that each of the pixels (PX) includes three subpixels (RP, GP, BP), namely a first subpixel (RP), a second subpixel (GP), and a third subpixel (BP), but the embodiments of the present specification are not limited thereto.

[0041] The first subpixel (RP), the second subpixel (GP), and the third subpixel (BP) can be connected to any one of the data lines and at least one of the scan lines.

[0042] Each of the first subpixel (RP), the second subpixel (GP), and the third subpixel (BP) may have a planar shape that is rectangular, square, or rhombus. For example, each of the first subpixel (RP), the second subpixel (GP), and the third subpixel (BP) may have a planar shape that is rectangular, having a short side in the first direction (DR1) and a long side in the second direction (DR2), as shown in FIG. 2. Alternatively, each of the first subpixel (RP), the second subpixel (GP), and the third subpixel (BP) may have a planar shape that is square or rhombus, including sides that have the same length in the first direction (DR1) and the second direction (DR2), as shown in FIG. 3.

[0043] As shown in FIG. 2, the first subpixel (RP), the second subpixel (GP), and the third subpixel (BP) may be arranged in a first direction (DR1). Alternatively, either one of the second subpixel (GP) and the third subpixel (BP) may be arranged with the first subpixel (RP) in the first direction (DR1), and the other one with the first subpixel (RP) may be arranged in a second direction (DR2). For example, as shown in FIG. 3, the first subpixel (RP) and the second subpixel (GP) may be arranged in the first direction (DR1), and the first subpixel (RP) and the third subpixel (BP) may be arranged in the second direction (DR2).

[0044] Alternatively, either one of the first subpixel (RP) and the third subpixel (BP) and the second subpixel (GP) may be arranged in the first direction (DR1), and the other one and the second subpixel (GP) may be arranged in the second direction (DR2). Alternatively, either one of the first subpixel (RP) and the second subpixel (GP) and the third subpixel (BP) may be arranged in the first direction (DR1), and the other one and the third subpixel (BP) may be arranged in the second direction (DR2).

[0045] A first subpixel (RP) may include a first light-emitting element that emits a first light, a second subpixel (GP) may include a second light-emitting element that emits a second light, and a third subpixel (BP) may include a third light-emitting element that emits a third light. Here, the first light may be light in the red wavelength band, the second light may be light in the green wavelength band, and the third light may be light in the blue wavelength band. The red wavelength band may be a wavelength band of approximately 600 nm to 750 nm, the green wavelength band may be a wavelength band of approximately 480 nm to 560 nm, and the blue wavelength band may be a wavelength band of approximately 370 nm to 460 nm, but the embodiments of the present specification are not limited thereto.

[0046] Each of the first subpixel (RP), the second subpixel (GP), and the third subpixel (BP) may include an inorganic light-emitting element having an inorganic semiconductor as a light-emitting element. For example, the inorganic light-emitting element may be a flip-chip type micro LED (Light Emitting Diode), but the embodiments of this specification are not limited thereto.

[0047] As shown in FIGS. 2 and 3, the area of ​​the first subpixel (RP), the area of ​​the second subpixel (GP), and the area of ​​the third subpixel (BP) may be substantially the same, but the embodiments of this specification are not limited thereto. At least one of the area of ​​the first subpixel (RP), the area of ​​the second subpixel (GP), and the area of ​​the third subpixel (BP) may be different from the other. Alternatively, any two of the areas of the first subpixel (RP), the area of ​​the second subpixel (GP), and the area of ​​the third subpixel (BP) may be substantially the same, and the remaining one may be different from the two. Alternatively, the area of ​​the first subpixel (RP), the area of ​​the second subpixel (GP), and the area of ​​the third subpixel (BP) may be different from each other.

[0048] FIG. 4 is a block diagram showing a display device according to one embodiment.

[0049] Referring to FIG. 4, the display device (10) includes a display panel (100), a scan drive unit (110), a source drive unit (200), a timing control unit (300), and a power supply unit (400).

[0050] The display area (DA) of the display panel (100) may include subpixels (RP, GP, BP) for displaying an image, scan write lines (GWL) connected to the subpixels (RP, GP, BP), scan initialization lines (GIL), scan control lines (GCL), sweep signal lines (SWPL), PWM (Pulse Width Modulation) light-emitting lines (PWEL), PAM (Pulse Amplitude Modulation) light-emitting lines (PAEL), PWM data lines (DL), first PAM data lines (RDL), second PAM data lines (GDL), and third PAM data lines (BDL).

[0051] Scan write lines (GWL), scan initialization lines (GIL), scan control lines (GCL), sweep signal lines (SWPL), PWM light-emitting lines (PWEL), and PAM light-emitting lines (PAEL) may be extended in a first direction (DR1) and arranged in a second direction (DR2) that intersects the first direction (DR1). PWM data lines (DL), first PAM data lines (RDL), second PAM data lines (GDL), and third PAM data lines (BDL) may be extended in a second direction (DR2) and arranged in the first direction (DR1). The first PAM data lines (RDL) may be electrically connected to each other, the second PAM data lines (GDL) may be electrically connected to each other, and the third PAM data lines (BDL) may be electrically connected to each other.

[0052] Each of the subpixels (RP, GP, BP) may be connected to any one of the scan write lines (GWL), any one of the scan initialization lines (GIL), any one of the scan control lines (GCL), any one of the sweep signal lines (SWPL), any one of the PWM light emission lines (PWEL), and any one of the PAM light emission lines (PAEL). Additionally, each of the first subpixels (RP) may be connected to any one of the PWM data lines (DL) and any one of the first PAM data lines (RDL). Additionally, each of the second subpixels (GP) may be connected to any one of the PWM data lines (DL) and any one of the second PAM data lines (GDL). Additionally, each of the third subpixels (BP) may be connected to any one of the PWM data lines (DL) and any one of the third PAM data lines (BDL).

[0053] A scan driver (110) for applying signals to scan write wires (GWL), scan initialization wires (GIL), scan control wires (GCL), sweep signal wires (SPWL), PWM light-emitting wires (PWEL), and PAM light-emitting wires (PAEL) may be disposed in the non-display area (NDA) of the display panel (100). In FIG. 4, the scan driver (110) is illustrated as being disposed on one edge of the display panel (100), but is not limited thereto. The scan driver (110) may be disposed on both edges of the display panel (100).

[0054] The scan driving unit (110) may include a first scan signal driving unit (111), a second scan signal driving unit (112), a sweep signal driving unit (113), a light emission signal driving unit (114), and a light emission control signal driving unit (115).

[0055] The first scan signal driver (111) can receive a first scan drive control signal (GDCS1) from the timing control unit (300). The first scan signal driver (111) can output scan initialization signals to the scan initialization wires (GIL) and output scan write signals to the scan write wires (GWL) according to the first scan drive control signal (GDCS1). That is, the first scan signal driver (111) can output two scan signals together, namely scan initialization signals and scan write signals.

[0056] The second scan signal driving unit (112) can receive a second scan driving control signal (GDCS2) from the timing control unit (300). The second scan signal driving unit (112) can output scan control signals to the scan control wires (GCL) according to the second scan driving control signal (GDCS2).

[0057] The sweep signal driver (113) can receive a first light emission control signal (ECS1) and a sweep control signal (SPCS) from the timing control unit (300). The sweep signal driver (113) can output PWM light emission signals to PWM light emission wires (PWEL) and sweep signals to sweep signal wires (SWPL) according to the first light emission control signal (ECS1). That is, the sweep signal driver (113) can output PWM light emission signals and sweep signals together.

[0058] The light emission signal output unit (114) can receive a second light emission control signal (ECS2) from the timing control unit (300). The light emission signal output unit (114) can output PAM light emission signals to the PAM light emission wiring (PAEL) according to the second light emission control signal (ECS2).

[0059] The light emission control signal output unit (115) can receive a third light emission control signal (ECS3) from the timing control unit (300). The light emission control signal output unit (115) can output light emission control signals to the light emission control wires (RCL1, RCL2 in FIG. 6) according to the third light emission control signal (ECS3). The light emission control wires (RCL1, RCL2 in FIG. 6) may be connected to the first subpixel (RP) and may not be connected to the second subpixel (GP) and the third subpixel (BP).

[0060] The timing control unit (300) receives digital video data (DATA) and timing signals (TS). The timing control unit (300) can generate a scan timing control signal (STCS) to control the operation timing of the scan drive unit (110) according to the timing signals (TS). The scan timing control signal (STCS) can generate a first scan drive control signal, a second scan drive control signal (GDSC2), a first light emission control signal (ECS1), a second light emission control signal (ECS2), a third light emission control signal (ECS3), and a sweep control signal (SWCS). Additionally, the timing control unit (300) can generate a source control signal (DCS) to control the operation timing of the source drive unit (200).

[0061] The timing control unit (300) outputs a first scan drive control signal (GDCS1), a second scan drive control signal (GDSC2), a first light emission control signal (ECS1), a second light emission control signal (ECS2), a third light emission control signal (ECS3), and a sweep control signal (SWCS) to the scan drive unit (110). The timing control unit (300) outputs digital video data (DATA) and a PWM control signal (DCS) to the source drive unit (200).

[0062] The source driver (200) converts digital video data (DATA) into analog PWM data voltages and outputs them to PWM data wires (DL). As a result, subpixels (RP, GP, BP) are selected by the scan write signals of the scan driver (110), and PWM data voltages can be supplied to the selected subpixels (RP, GP, BP).

[0063] The power supply unit (400) can output a first PAM data voltage to the first PAM data lines (RDL) in common, output a second PAM data voltage to the second PAM data lines (GDL) in common, and output a third PAM data voltage to the third PAM data lines (BDL) in common. Additionally, the power supply unit (400) can generate a plurality of power voltages and output them to the display panel (100).

[0064] The power supply unit (400) can output a first power voltage (VDD1), a second power voltage (VDD2), a third power voltage (VSS), an initialization voltage (VINT), a gate-on voltage (VGL), and a gate-off voltage (VGH) to the display panel (100). The first power voltage (VDD1) and the second power voltage (VDD2) may be high-potential driving voltages for driving the light-emitting elements of each of the subpixels (RP, GP, BP). The third driving voltage (VINT) may be a low-potential driving voltage for driving the light-emitting elements of each of the subpixels (RP, GP, BP). The initialization voltage (VINT) and the gate-off voltage (VGH) are applied to each of the subpixels (RP, GP, BP), and the gate-on voltage (VGL) and the gate-off voltage (VGH) may be applied to the scan driving unit (110).

[0065] Each of the source driving unit (200), the timing control unit (300), and the power supply unit (400) can be formed as an integrated circuit. Additionally, the source driving unit (200) can be formed as a plurality of integrated circuits.

[0066] FIG. 5 is a graph showing the luminous efficiency of the first light-emitting element and the third light-emitting element according to one embodiment as a function of temperature.

[0067] In Fig. 5, the X-axis represents the temperature of the first light-emitting element and the third light-emitting element, and the Y-axis represents the ratio of the relative luminous brightness of the first light-emitting element and the third light-emitting element. In Fig. 5, the luminous brightness of the first light-emitting element and the third light-emitting element was calculated as 100% when the temperature of the first light-emitting element and the third light-emitting element was 25 degrees.

[0068] Referring to FIG. 5, the first light-emitting element and the third light-emitting element each emit light through a driving current and thereby emit heat. That is, the first light-emitting element and the third light-emitting element each are exposed to heat as they are driven.

[0069] The luminous brightness ratio of the first light-emitting element changes significantly with temperature changes. For example, when the temperature of the first light-emitting element is -20 degrees, the first light-emitting element has a luminous brightness ratio of approximately 160%. In contrast, when the temperature of the first light-emitting element is 120 degrees, the first light-emitting element has a luminous brightness ratio of approximately 40%. That is, even if the same driving current is applied to the first light-emitting element, the luminous brightness ratio of the first light-emitting element differs by approximately 120% in the temperature range of -20 degrees to 120 degrees.

[0070] The luminous brightness ratio of the third light-emitting element changes slightly with temperature change. For example, when the same driving current is applied to the third light-emitting element, the luminous brightness ratio of the third light-emitting element differs little in the temperature range of -20 degrees to 120 degrees.

[0071] In FIG. 5, the first light-emitting element and the third light-emitting element are compared, and the second light-emitting element is not mentioned, but the ratio of the light-emitting brightness of the second light-emitting element to the change in temperature may be smaller than the ratio of the light-emitting brightness of the first light-emitting element to the change in temperature. That is, since the first light-emitting element is more sensitive to changes in temperature than the second light-emitting element and the third light-emitting element, it is necessary to keep the temperature of the first light-emitting element low.

[0072] FIG. 6 is a circuit diagram showing a first subpixel according to another embodiment.

[0073] Referring to FIG. 6, a first subpixel (RP) according to one embodiment may be connected to a k-th (k is a positive integer) scan write wire (GWLk), a k-th scan initialization wire (GILk), a k-th scan control wire (GCLk), a k-th sweep signal wire (SWPLk), a k-th PWM light emission wire (PWELk), a k-th PAM light emission wire (PAELk), a first light emission control wire (RCL1), and a second light emission control wire (RCL2). Additionally, the first subpixel (RP) may be connected to a j-th PWM data wire (DLj) and a first PAM data wire (RDL). Additionally, the first subpixel (RP) may be connected to a first power line (VDL1) to which a first power voltage (VDD1) is applied, a second power line (VDL2) to which a second power voltage (VDD2) is applied, a third power line (VSL) to which a third power voltage (VSS) is applied, an initialization voltage line (VIL) to which an initialization voltage (VINT) is applied, and a gate-off voltage line (VGHL) to which a gate-off voltage (VGH) is applied. Meanwhile, for convenience of explanation, the j-th PWM data line (DLj) may be referred to as the first data line, and the first PAM data line (RDL) may be referred to as the second data line.

[0074] The first subpixel (RP) may include a first light-emitting element (REL) comprising a first sublight-emitting element (REL1) and a second sublight-emitting element (REL2), a first pixel driver (PDU1), a second pixel driver (PDU2), and a third pixel driver (PDU3).

[0075] Each of the first sub-light-emitting element (REL1) and the second sub-light-emitting element (REL2) emits a first light according to the driving current (Ids) generated by the second pixel driver (PDU2). The first sub-light-emitting element (REL1) may be placed between the 19th transistor (T19) and the third power line (VSL), and the second sub-light-emitting element (REL2) may be placed between the 20th transistor (T20) and the third power line (VSL). The first electrode of the first sub-light-emitting element (REL1) may be connected to the second electrode of the 19th transistor (T19), and the second electrode may be connected to the third power line (VSL). The first electrode of the second sub-light-emitting element (REL2) may be connected to the second electrode of the 20th transistor (T20), and the second electrode may be connected to the third power line (VSL).

[0076] The first electrode of each of the first sub-light-emitting element (REL1) and the second sub-light-emitting element (REL2) may be an anode electrode, and the second electrode may be a cathode electrode. Each of the first sub-light-emitting element (REL1) and the second sub-light-emitting element (REL2) may be an inorganic light-emitting element comprising a first electrode, a second electrode, and an inorganic semiconductor disposed between the first electrode and the second electrode. For example, each of the first sub-light-emitting element (REL1) and the second sub-light-emitting element (REL2) may be a micro light-emitting diode made of an inorganic semiconductor, but is not limited thereto.

[0077] The first pixel driver (PDU1) generates a control current (Ic) according to the j-th PWM data voltage of the j-th PWM data line (DLj) and controls the voltage of the third node (N3) of the third pixel driver (PDU3). Since the pulse width of the driving current (Ids) flowing to the first light-emitting element (REL) can be adjusted by the control current (Ic) of the first pixel driver (PDU1), the first pixel driver (PDU1) may be a pulse width modulation unit (PWM unit) that performs pulse width modulation of the driving current (Ids) flowing to the first light-emitting element (REL).

[0078] The first pixel driver (PDU1) may include first to seventh transistors (T1 to T7) and a first capacitor (PC1).

[0079] The first transistor (T1) controls the control current (Ic) flowing between the second electrode and the first electrode according to the PWM data voltage applied to the gate electrode.

[0080] The second transistor (T2) is turned on by the k-th scan write signal of the k-th scan write wire (GWLk) to supply the PWM data voltage of the j-th PWM data wire (DLj) to the first electrode of the first transistor (T1). The gate electrode of the second transistor (T2) is connected to the k-th scan write wire (GWLk), the first electrode is connected to the j-th PWM data wire (DLj), and the second electrode can be connected to the first electrode of the first transistor (T1).

[0081] The third transistor (T3) is turned on by the k-th scan initialization signal of the k-th scan initialization wiring (GILk) to connect the initialization voltage wiring (VIL) to the gate electrode of the first transistor (T1). As a result, during the period when the third transistor (T3) is turned on, the gate electrode of the first transistor (T1) can be discharged to the initialization voltage (VINT) of the initialization voltage wiring (VIL). At this time, the gate-on voltage (VGL) of the k-th scan initialization signal may be different from the initialization voltage (VINT) of the initialization voltage wiring (VIL). In particular, since the difference voltage between the gate-on voltage (VGL) and the initialization voltage (VINT) is greater than the threshold voltage of the third transistor (T3), the third transistor (T3) can be stably turned on even after the initialization voltage (VINT) is applied to the gate electrode of the first transistor (T1). Therefore, when the third transistor (T3) is turned on, an initialization voltage (VINT) can be stably applied to the gate electrode of the first transistor (T1) regardless of the threshold voltage of the third transistor (T3).

[0082] The third transistor (T3) may include a plurality of transistors connected in series. For example, the third transistor (T3) may include a first sub-transistor (T31) and a second sub-transistor (T32). This prevents the voltage of the gate electrode of the first transistor (T1) from leaking through the third transistor (T3). The gate electrode of the first sub-transistor (T31) may be connected to the k-th scan initialization wiring (GILk), the first electrode may be connected to the gate electrode of the first transistor (T1), and the second electrode may be connected to the first electrode of the second sub-transistor (T32). The gate electrode of the second sub-transistor (T32) may be connected to the k-th scan initialization wiring (GILk), the first electrode may be connected to the second electrode of the first sub-transistor (T31), and the second electrode may be connected to the initialization voltage wiring (VIL).

[0083] The fourth transistor (T4) is turned on by the k-th scan write signal of the k-th scan write wiring (GWLk) to connect the gate electrode of the first transistor (T1) and the second electrode. As a result, the first transistor (T1) can operate as a diode during the period when the fourth transistor (T4) is turned on.

[0084] The fourth transistor (T4) may include a plurality of transistors connected in series. For example, the fourth transistor (T4) may include a third sub-transistor (T41) and a fourth sub-transistor (T42). This prevents the voltage of the gate electrode of the first transistor (T1) from leaking through the fourth transistor (T4). The gate electrode of the third sub-transistor (T41) may be connected to the k-th scan write wire (GWLk), the first electrode may be connected to the second electrode of the first transistor (T1), and the second electrode may be connected to the first electrode of the fourth sub-transistor (T42). The gate electrode of the fourth sub-transistor (T42) may be connected to the k-th scan write wire (GWLk), the first electrode may be connected to the second electrode of the third sub-transistor (T41), and the second electrode may be connected to the gate electrode of the first transistor (T1).

[0085] The fifth transistor (T5) is turned on by the k-th PWM light emission signal of the k-th PWM light emission wiring (PWELk) to connect the first electrode of the first transistor (T1) to the first power wiring (VDL1). The gate electrode of the fifth transistor (T5) is connected to the k-th PWM light emission wiring (PWELk), the first electrode is connected to the first power wiring (VDL1), and the second electrode can be connected to the first electrode of the first transistor (T1).

[0086] The sixth transistor (T6) is turned on by the k-th PWM light emission signal of the k-th PWM light emission wiring (PWELk) to connect the second electrode of the first transistor (T1) to the third node (N3) of the third pixel driver (PDU3). The gate electrode of the sixth transistor (T6) is connected to the k-th PWM light emission wiring (PWELk), the first electrode is connected to the second electrode of the first transistor (T1), and the second electrode can be connected to the third node (N3) of the third pixel driver (PDU3).

[0087] The seventh transistor (T7) can be turned on by the k-th scan control signal of the k-th scan control line (GCLk) to supply the gate off voltage (VGH) of the gate off voltage line (VGHL) to the first node (N1) connected to the k-th sweep signal line (SWPLk). As a result, the voltage change of the gate electrode of the first transistor (T1) by the first capacitor (PC1) can be prevented from being reflected in the k-th sweep signal of the k-th sweep signal line (SWPLk) during the period when the initialization voltage (VINT) is applied to the gate electrode of the first transistor (T1) and the period when the PWM data voltage of the j-th PWM data line (DLj) and the threshold voltage (Vth1) of the first transistor (T1) are programmed. The gate electrode of the seventh transistor (T7) is connected to the k-th scan control wiring (GCLk), the first electrode is connected to the gate off voltage wiring (VGHL), and the second electrode can be connected to the first node (N1).

[0088] The first capacitor (PC1) can be placed between the gate electrode of the first transistor (T1) and the first node (N1). One electrode of the first capacitor (PC1) can be connected to the gate electrode of the first transistor (T1), and the other electrode can be connected to the first node (N1).

[0089] The first node (N1) may be the contact of the k-th sweep signal wiring (SWPLk), the second electrode of the seventh transistor (T7), and the other electrode of the first capacitor (PC1).

[0090] The second pixel driver (PDU2) generates a driving current (Ids) applied to the first light-emitting element (REL) according to the first PAM data voltage of the first PAM data wiring (RDL). The second pixel driver (PDU2) may be a pulse amplitude modulation unit (PAM unit) that performs pulse amplitude modulation. The second pixel driver (PDU2) may be a constant current generator that generates a constant driving current (Ids) according to the first PAM data voltage.

[0091] Additionally, the second pixel driver (PDU2) of each of the first subpixels (RP) can receive the same first PAM data voltage regardless of the brightness of the first subpixel (RP) and generate the same driving current (Ids). Similarly, the second pixel driver (PDU2) of each of the second subpixels (GP) can receive the same second PAM data voltage regardless of the brightness of the second subpixel (GP) and generate the same driving current (Ids). The second pixel driver (PDU2) of each of the third subpixels (BP) can receive the same third PAM data voltage regardless of the brightness of the third subpixel (BP) and generate the same driving current (Ids).

[0092] The second pixel driver (PDU2) may include eight to fourteen transistors (T8 to T14) and a second capacitor (PC2).

[0093] The eighth transistor (T8) controls the driving current (Ids) flowing to the first light-emitting element (REL) according to the voltage applied to the gate electrode.

[0094] The ninth transistor (T9) is turned on by the k-th scan write signal of the k-th scan write wiring (GWLk) to supply the first PAM data voltage of the first PAM data wiring (RDL) to the first electrode of the eighth transistor (T8). The gate electrode of the ninth transistor (T9) is connected to the k-th scan write wiring (GWLk), the first electrode is connected to the first PAM data wiring (RDL), and the second electrode can be connected to the first electrode of the eighth transistor (T8).

[0095] The 10th transistor (T10) is turned on by the k-th scan initialization signal of the k-th scan initialization wire (GILk) to connect the initialization voltage wire (VIL) to the gate electrode of the 8th transistor (T8). As a result, during the period when the 10th transistor (T10) is turned on, the gate electrode of the 8th transistor (T8) can be discharged to the initialization voltage (VINT) of the initialization voltage wire (VIL). At this time, the gate-on voltage (VGL) of the k-th scan initialization signal may be different from the initialization voltage (VINT) of the initialization voltage wire (VIL). In particular, since the difference voltage between the gate-on voltage (VGL) and the initialization voltage (VINT) is greater than the threshold voltage of the 10th transistor (T10), the 10th transistor (T10) can be stably turned on even after the initialization voltage (VINT) is applied to the gate electrode of the 8th transistor (T8). Therefore, when the 10th transistor (T10) is turned on, an initialization voltage (VINT) can be stably applied to the gate electrode of the 8th transistor (T8) regardless of the threshold voltage of the 10th transistor (T10).

[0096] The tenth transistor (T10) may include a plurality of transistors connected in series. For example, the tenth transistor (T10) may include a fifth sub-transistor (T101) and a sixth sub-transistor (T102). This prevents the voltage of the gate electrode of the eighth transistor (T8) from leaking through the tenth transistor (T10). The gate electrode of the fifth sub-transistor (T101) may be connected to the k-th scan initialization wiring (GILk), the first electrode may be connected to the gate electrode of the eighth transistor (T8), and the second electrode may be connected to the first electrode of the sixth sub-transistor (T102). The gate electrode of the sixth sub-transistor (T102) may be connected to the k-th scan initialization wiring (GILk), the first electrode may be connected to the second electrode of the fifth sub-transistor (T101), and the second electrode may be connected to the initialization voltage wiring (VIL).

[0097] The 11th transistor (T11) is turned on by the k-th scan write signal of the k-th scan write wiring (GWLk) to connect the gate electrode of the 8th transistor (T8) and the 2nd electrode. As a result, the 8th transistor (T8) can operate as a diode during the period when the 11th transistor (T11) is turned on.

[0098] The eleventh transistor (T11) may include a plurality of transistors connected in series. For example, the eleventh transistor (T11) may include a seventh sub-transistor (T111) and an eighth sub-transistor (T112). This prevents the voltage of the gate electrode of the eighth transistor (T8) from leaking through the eleventh transistor (T11). The gate electrode of the seventh sub-transistor (T111) may be connected to the k-th scan write wire (GWLk), the first electrode may be connected to the second electrode of the eighth transistor (T8), and the second electrode may be connected to the first electrode of the eighth sub-transistor (T112). The gate electrode of the eighth sub-transistor (T112) may be connected to the k-th scan write wire (GWLk), the first electrode may be connected to the second electrode of the seventh sub-transistor (T111), and the second electrode may be connected to the gate electrode of the eighth transistor (T8).

[0099] The 12th transistor (T12) is turned on by the k-th PWM light emission signal of the k-th PWM light emission wiring (PWELk) to connect the first electrode of the 8th transistor (T8) to the second power supply wiring (VDL2). The gate electrode of the 12th transistor (T12) is connected to the k-th PWM light emission wiring (PWELk), the first electrode is connected to the first power supply wiring (VDL1), and the second electrode can be connected to the first electrode of the 8th transistor (T8).

[0100] The 13th transistor (T13) is turned on by the k-th scan control signal of the k-th scan control wire (GCLk) to connect the first power wire (VDL1) to the second node (N2). The gate electrode of the 13th transistor (T13) is connected to the k-th scan control wire (GCLk), the first electrode is connected to the second power wire (VDL2), and the second electrode can be connected to the second node (N2).

[0101] The 14th transistor (T14) is turned on by the k-th PWM light emission signal of the k-th PWM light emission wiring (PWELk) to connect the second power wiring (VDL2) to the second node (N2). As a result, when the 14th transistor (T14) is turned on, the second power voltage (VDD2) of the second power wiring (VDL2) can be supplied to the second node (N2). The gate electrode of the 14th transistor (T14) is connected to the k-th PWM light emission wiring (PWELk), the first electrode is connected to the second power wiring (VDL2), and the second electrode can be connected to the second node (N2).

[0102] The second capacitor (PC2) can be placed between the gate electrode of the eighth transistor (T8) and the second node (N2). One electrode of the second capacitor (PC2) can be connected to the gate electrode of the eighth transistor (T8), and the other electrode can be connected to the second node (N2).

[0103] The second node (N2) may be a contact point between the second electrode of the 13th transistor (T13), the second electrode of the 14th transistor (T14), and the other electrode of the second capacitor (C2).

[0104] The third pixel driver (PDU3) adjusts the period during which the driving current (Ids) is applied to the first light-emitting element (REL) according to the voltage of the third node (N3).

[0105] The third pixel driver (PDU3) may include 15 to 20 transistors (T15 to T20) and a third capacitor (PC3).

[0106] The 15th transistor (T15) is turned on or turned off depending on the voltage of the 3rd node (N3). When the 15th transistor (T15) is turned on, the driving current (Ids) of the 8th transistor (T8) is supplied to the 1st light-emitting element (REL), and when the 15th transistor (T15) is turned off, the driving current (Ids) of the 8th transistor (T8) may not be supplied to the 1st light-emitting element (REL). Therefore, the turn-on period of the 15th transistor (T15) may be substantially the same as the light-emitting period of the 1st light-emitting element (REL). The gate electrode of the 15th transistor (T15) is connected to the 3rd node (N3), the 1st electrode is connected to the 2nd electrode of the 8th transistor (T8), and the 2nd electrode can be connected to the 1st electrode of the 17th transistor (T17). The 16th transistor (T16) is turned on by the k-th scan control signal of the k-th scan control wiring (GCLk) to connect the initialization voltage wiring (VIL) to the 3rd node (N3). As a result, during the period when the 16th transistor (T16) is turned on, the 3rd node (N3) can be discharged to the initialization voltage (VINT) of the initialization voltage wiring (VIL).

[0107] The 16th transistor (T16) may include a plurality of transistors connected in series. For example, the 16th transistor (T16) may include a 9th sub-transistor (T161) and a 10th sub-transistor (T162). This prevents the voltage (V_N3) of the 3rd node (N3) from leaking through the 16th transistor (T16). The gate electrode of the 9th sub-transistor (T161) may be connected to the k-th scan control wiring (GCLk), the first electrode may be connected to the 3rd node (N3), and the second electrode may be connected to the first electrode of the 10th sub-transistor (T162). The gate electrode of the 10th sub-transistor (T162) may be connected to the k-th scan control wiring (GCLk), the first electrode may be connected to the second electrode of the 9th sub-transistor (T161), and the second electrode may be connected to the initialization voltage wiring (VIL).

[0108] delete

[0109] The 17th transistor (T17) is turned on by the k-th PAM light emission signal of the k-th PAM light emission wiring (PAELk) to connect the second electrode of the 15th transistor (T15) to the first electrode of the 19th transistor (T19) and the first electrode of the 20th transistor (T20). The gate electrode of the 17th transistor (T17) is connected to the k-th PAM light emission wiring (PAELk), the first electrode is connected to the second electrode of the 15th transistor (T15), and the second electrode can be connected to the first electrode of the 19th transistor (T19) and the first electrode of the 20th transistor (T20).

[0110] The 18th transistor (T18) may include the 11th sub-transistor (T181) and the 12th sub-transistor (T182).

[0111] The 11th sub-transistor (T181) is turned on by the k-th scan control signal of the k-th scan control wiring (GCLk) to connect the initialization voltage wiring (VIL) to the first electrode of the first sub-light-emitting element (REL1). As a result, during the period when the 11th sub-transistor (T181) is turned on, the first electrode of the first sub-light-emitting element (REL1) can be discharged to the initialization voltage (VINT) of the initialization voltage wiring (VIL). The gate electrode of the 11th sub-transistor (T181) is connected to the k-th scan control wiring (GCLk), the first electrode is connected to the first electrode of the first sub-light-emitting element (REL1), and the second electrode can be connected to the initialization voltage wiring (VIL).

[0112] The 12th sub-transistor (T182) is turned on by the k-th scan control signal of the k-th scan control wiring (GCLk) to connect the initialization voltage wiring (VIL) to the first electrode of the second sub-light-emitting element (REL2). As a result, during the period when the 12th sub-transistor (T182) is turned on, the first electrode of the second sub-light-emitting element (REL2) can be discharged to the initialization voltage (VINT) of the initialization voltage wiring (VIL). The gate electrode of the 12th sub-transistor (T182) is connected to the k-th scan control wiring (GCLk), the first electrode is connected to the first electrode of the second sub-light-emitting element (REL2), and the second electrode can be connected to the initialization voltage wiring (VIL).

[0113] The 19th transistor (T19) is turned on by a first light-emitting control signal of the first light-emitting control wiring (RCL1) to connect the first electrode of the first sub-light-emitting element (REL1) to the second electrode of the 17th transistor (T17). As a result, a driving current (Ids) can be supplied to the first sub-light-emitting element (REL1) during the period when the 19th transistor (T19) is turned on. The gate electrode of the 19th transistor (T19) is connected to the first light-emitting control wiring (RCL1), the first electrode is connected to the second electrode of the 17th transistor (T17), and the second electrode can be connected to the first electrode of the first sub-light-emitting element (REL1).

[0114] The 20th transistor (T20) is turned on by a second light-emitting control signal of the second light-emitting control wiring (RCL2) to connect the first electrode of the second sub-light-emitting element (REL2) to the second electrode of the 17th transistor (T17). As a result, a driving current (Ids) can be supplied to the second sub-light-emitting element (REL2) during the period when the 20th transistor (T20) is turned on. The gate electrode of the 20th transistor (T20) is connected to the second light-emitting control wiring (RCL2), the first electrode is connected to the second electrode of the 17th transistor (T17), and the second electrode can be connected to the first electrode of the second sub-light-emitting element (REL2).

[0115] For each of the first to 20 transistors (T1 to T20), either the first electrode or the second electrode may be a source electrode and the other may be a drain electrode. The active layer of each of the first to 20 transistors (T1 to T20) may be formed from any one of polysilicon, amorphous silicon, and oxide semiconductor. When the active layer of each of the first to 20 transistors (T1 to T20) is polysilicon, it may be formed by a low-temperature polysilicon (LTPS) process.

[0116] In addition, FIG. 6 describes the first to twentieth transistors (T1 to T20) as being formed as P-type MOSFETs (metal oxide semiconductor field effect transistors), but the embodiments of this specification are not limited thereto. For example, each of the first to twentieth transistors (T1 to T20) may be formed as N-type MOSFETs.

[0117] Alternatively, to increase the black expression capability of the first light-emitting element (REL) by blocking leakage current, the first sub-transistor (T31) and second sub-transistor (T32) of the third transistor (T3) in the first sub-pixel (RP), the third sub-transistor (T41) and fourth sub-transistor (T42) of the fourth transistor (T4), the fifth sub-transistor (T101) and sixth sub-transistor (T102) of the tenth transistor (T10), and the seventh sub-transistor (T111) and eighth sub-transistor (T112) of the eleventh transistor (T11) may be formed as N-type MOSFETs. In this case, the first sub-transistor (T31) and second sub-transistor (T32) of the third transistor (T3), the third sub-transistor (T41) and fourth sub-transistor (T42) of the fourth transistor (T4), the fifth sub-transistor (T101) and sixth sub-transistor (T102) of the tenth transistor (T10), and the seventh sub-transistor (T111) and eighth sub-transistor (T112) of the eleventh transistor (T11) can be turned on when a gate-off voltage (VGH) is applied to the gate electrode. Therefore, the gate electrode of the third sub-transistor (T41) of the fourth transistor (T4) and the gate electrode of the fourth sub-transistor (T42), and the gate electrode of the seventh sub-transistor (T111) of the eleventh transistor (T11) and the gate electrode of the eighth sub-transistor (T112) can be connected to the k-th control wiring to which the k-th control signal is applied instead of the k-th scan write wiring (GILk).Additionally, the active layers of the first sub-transistor (T31) and second sub-transistor (T32) of the third transistor (T3), the third sub-transistor (T41) and fourth sub-transistor (T42) of the fourth transistor (T4), the fifth sub-transistor (T101) and sixth sub-transistor (T102) of the tenth transistor (T10), and the seventh sub-transistor (T111) and eighth sub-transistor (T112) of the eleventh transistor (T11) may be formed of oxide semiconductor, and the remaining transistors may be formed of polysilicon.

[0118] Alternatively, either the first sub-transistor (T31) or the second sub-transistor (T32) of the third transistor (T3) may be formed as an N-type MOSFET, and the other as a P-type MOSFET. In this case, among the first sub-transistor (T31) and the second sub-transistor (T32) of the third transistor (T3), the active layer of the transistor formed as an N-type MOSFET may be formed of an oxide semiconductor, and the active layer of the transistor formed as a P-type MOSFET may be formed of polysilicon.

[0119] Alternatively, either the third sub-transistor (T41) or the fourth sub-transistor (T42) of the fourth transistor (T4) may be formed as an N-type MOSFET, and the other as a P-type MOSFET. In this case, among the third sub-transistor (T41) and the fourth sub-transistor (T42) of the fourth transistor (T4), the active layer of the transistor formed as an N-type MOSFET may be formed of an oxide semiconductor, and the active layer of the transistor formed as a P-type MOSFET may be formed of polysilicon.

[0120] Alternatively, either one of the fifth sub-transistor (T101) and the sixth sub-transistor (T102) of the tenth transistor (T10) may be formed as an N-type MOSFET, and the other may be formed as a P-type MOSFET. In this case, among the fifth sub-transistor (T101) and the sixth sub-transistor (T102) of the tenth transistor (T10), the active layer of the transistor formed as an N-type MOSFET may be formed as an oxide semiconductor, and the active layer of the transistor formed as a P-type MOSFET may be formed as polysilicon.

[0121] Alternatively, either the seventh sub-transistor (T111) or the eighth sub-transistor (T112) of the eleventh transistor (T11) may be formed as an N-type MOSFET, and the other as a P-type MOSFET. In this case, among the seventh sub-transistor (T111) and the eighth sub-transistor (T112) of the eleventh transistor (T11), the active layer of the transistor formed as an N-type MOSFET may be formed of an oxide semiconductor, and the active layer of the transistor formed as a P-type MOSFET may be formed of polysilicon.

[0122] FIG. 7 is a circuit diagram showing a second subpixel according to one embodiment.

[0123] The embodiment of FIG. 7 differs from the embodiment of FIG. 6 in that the second subpixel (GP) includes a single light-emitting element (GEL) and does not include the 19th transistor (T19) and the 20th transistor (T20). In FIG. 7, descriptions that overlap with the embodiment of FIG. 6 are omitted.

[0124] Referring to FIG. 7, the second light-emitting element (GEL) emits a second light according to the driving current (Ids) generated by the second pixel driver (PDU2). The second light-emitting element (GEL) may be placed between the 17th transistor (T17) and the third power line (VSL). The first electrode of the second light-emitting element (GEL) may be connected to the second electrode of the 17th transistor (T17), and the second electrode may be connected to the third power line (VSL).

[0125] The first electrode of the second light-emitting element (GEL) may be an anode electrode, and the second electrode may be a cathode electrode. The second light-emitting element (GEL) may be an inorganic light-emitting element comprising a first electrode, a second electrode, and an inorganic semiconductor disposed between the first electrode and the second electrode. For example, the second light-emitting element (GEL) may be a micro light-emitting diode made of an inorganic semiconductor, but is not limited thereto.

[0126] The 17th transistor (T17) is turned on by the k-th PAM light emission signal of the k-th PAM light emission wiring (PAELk) to connect the second electrode of the 15th transistor (T15) to the first electrode of the second light emission element (EL2). The gate electrode of the 17th transistor (T17) is connected to the k-th PAM light emission wiring (PAELk), the first electrode is connected to the second electrode of the 15th transistor (T15), and the second electrode can be connected to the first electrode of the second light emission element (EL2).

[0127] The 18th transistor (T18) is turned on by the k-th scan control signal of the k-th scan control wiring (GCLk) to connect the initialization voltage wiring (VIL) to the first electrode of the second light-emitting element (EL2). As a result, during the period when the 18th transistor (T18) is turned on, the first electrode of the second light-emitting element (EL2) can be discharged to the initialization voltage (VINT) of the initialization voltage wiring (VIL). The gate electrode of the 18th sub-transistor (T18) is connected to the k-th scan control wiring (GCLk), the first electrode is connected to the first electrode of the second light-emitting element (EL2), and the second electrode can be connected to the initialization voltage wiring (VIL).

[0128] FIG. 8 is a circuit diagram showing a third subpixel according to one embodiment.

[0129] The embodiment of FIG. 8 differs from the embodiment of FIG. 6 in that the third subpixel (BP) includes one third light-emitting element (BEL) and does not include the 19th transistor (T19) and the 20th transistor (T20). In FIG. 8, descriptions that overlap with the embodiment of FIG. 6 are omitted.

[0130] Referring to FIG. 8, the third light-emitting element (BEL) emits a third light according to the driving current (Ids) generated by the second pixel driver (PDU2). The third light-emitting element (BEL) may be placed between the 17th transistor (T17) and the third power line (VSL). The first electrode of the third light-emitting element (BEL) may be connected to the second electrode of the 17th transistor (T17), and the second electrode may be connected to the third power line (VSL).

[0131] The first electrode of the third light-emitting element (BEL) may be an anode electrode, and the second electrode may be a cathode electrode. The third light-emitting element (BEL) may be an inorganic light-emitting element comprising a first electrode, a second electrode, and an inorganic semiconductor disposed between the first electrode and the second electrode. For example, the third light-emitting element (BEL) may be a micro light-emitting diode made of an inorganic semiconductor, but is not limited thereto.

[0132] The 17th transistor (T17) and the 18th transistor (T18) are substantially the same as described in conjunction with FIG. 7, except that they are connected to the 3rd light-emitting element (BEL) instead of the 2nd light-emitting element (GEL), so a description of them is omitted.

[0133] FIG. 9 is an example drawing showing the operation of a display device during the Nth to N+2nd frame period.

[0134] Referring to FIG. 9, each of the Nth to N+2nd frame periods may include an active period (ACT) and a blank period (VB). The active period (ACT) may include a data addressing period (ADDR) that supplies a PWM data voltage and a first / second / third PAM data voltage to each of the first to third subpixels (RP, GP, BP), and a plurality of light-emitting periods (EP1, EP2, EP3, EP4, EP5, …, EPn) in which the light-emitting element (EL) of each of the subpixels (RP, GP, BP) emits light. The blank period (VB) may be a period during which the subpixels (RP, GP, BP) of the display panel (100) are idle.

[0135] The address period (ADDR) and the first light emission period (EP1) may be shorter than each of the second to nth light emission periods (EP2, EP3, EP4, EP5, …, EPn). For example, the address period (ADDR) and the first light emission period (EP1) may be approximately 5 horizontal periods, and each of the second to nth light emission periods (EP2, EP3, EP4, EP5, …, EPn) may be approximately 12 horizontal periods, but the embodiments of this specification are not limited thereto. Additionally, the active period (ACT) may include 25 light emission periods, but the number of light emission periods (EP1, EP2, EP3, EP4, EP5, …, EPn) of the active period (ACT) is not limited thereto.

[0136] The subpixels (RP, GP, BP) of the display panel (100) can receive PWM data voltage and first / second / third PAM data voltage sequentially by row line during the address period (ADDR). For example, they can receive PWM data voltage and first / second / third PAM data voltage sequentially from the subpixels (RP, GP, BP) placed on the first row line to the subpixels (RP, GP, BP) placed on the nth row line corresponding to the last row line.

[0137] The subpixels (RP, GP, BP) of the display panel (100) can emit light sequentially by row line in each of the plurality of light emission periods (EP1, EP2, EP3, EP4, EP5, …, EPn). For example, they can emit light sequentially from the subpixels (RP, GP, BP) placed in the first row line to the subpixels (RP, GP, BP) placed in the last row line.

[0138] The address period (ADDR) may overlap with at least one of the light emission periods (EP1, EP2, EP3, EP4, …, EPn). For example, as shown in FIG. 9, the address period (ADDR) may overlap with the first to third light emission periods (EP1, EP2, EP3). In this case, when subpixels (RP, GP, BP) placed on the p-th row line (p is a positive integer) receive a PWM data voltage and a first / second / third PAM data voltage, subpixels (RP, GP, BP) placed on the q-th row line (q is a positive integer smaller than p) may emit light.

[0139] Additionally, each of the light emission periods (EP1, EP2, EP3, EP4, …, EPn) may overlap with an adjacent light emission period. For example, the second light emission period (EP2) may overlap with the first light emission period (EP1) and the third light emission period (EP3). In this case, subpixels (RP, GP, BP) placed on the p-th row line may emit light during the second light emission period (EP2), while subpixels (RP, GP, BP) placed on the q-th row line may emit light during the first light emission period (EP1).

[0140] FIG. 10 is another example drawing showing the operation of a display device during the Nth to N+2nd frame period.

[0141] The embodiment of FIG. 10 differs from the embodiment of FIG. 9 in that the subpixels (RP, GP, BP) of the display panel (100) emit light simultaneously during each of the plurality of light-emitting periods (EP1, EP2, EP3, EP4, EP5, …, EPn).

[0142] Referring to FIG. 10, the address period (ADDR) may not overlap with multiple light emission periods (EP1, EP2, EP3, EP4, …, EPn). The first light emission period (EP1) may occur after the address period (ADDR) has completely ended.

[0143] Multiple light emission periods (EP1, EP2, EP3, EP4, …, EPn) may not overlap each other. In each of the multiple light emission periods (EP1, EP2, EP3, EP4, EP5, …, EPn), subpixels (RP, GP, BP) placed on all row lines may emit light simultaneously.

[0144] FIG. 11 is a waveform diagram showing a k-th scan initialization signal, a k-th scan write signal, a k-th scan control signal, a k-th PWM light emission signal, a k-th PAM light emission signal, a k-th sweep signal, a voltage of a third node, a light emission timing of a light-emitting element, a first light emission control signal, and a second light emission control signal applied to a first subpixel placed on a k-th row line during the N-th and N+1 frame periods according to one embodiment.

[0145] Referring to FIG. 11, a first subpixel (RP) placed on the k-th row line can be connected to the k-th scan initialization wire (GILk), the k-th scan write wire (GWLk), the k-th scan control wire (GCLk), the k-th PWM light emission wire (PWELk), the k-th PAM light emission wire (PAELk), the k-th sweep signal wire (SWPLk), the first light emission control wire (RCL1), and the second light emission control wire (RCL2). The k-th scan initialization signal (GIk) refers to a signal applied to the k-th scan initialization wire (GILk), and the k-th scan write signal (GWk) refers to a signal applied to the k-th scan write wire (GWLk). The k-th scan control signal (GCk) refers to a signal applied to the k-th scan control wire (GCLk), and the k-th PWM light emission signal (PWEMk) refers to a signal applied to the k-th PWM light emission wire (PWELk). The k-th PAM light emission signal (PAEMk) refers to a signal applied to the k-th PAM light emission wiring (PAELk), and the k-th sweep signal (SWPk) refers to a signal applied to the k-th sweep signal wiring (SWPLk). The first light emission control signal (RCS1) refers to a signal applied to the first light emission control wiring (RCL1), and the second light emission control signal (RCS2) refers to a signal applied to the second light emission control wiring (RCL2).

[0146] Scan initialization signals (GIk~GIk+5), scan write signals (GWk~GWk+5), scan control signals (GCk~GCk+5), PWM light emission signals (PWEMk~PAEMk+5), PAM light emission signals (PAEMk~PAEMk+5), and sweep signals (SWPk~SWPk+5) can be sequentially shifted by one horizontal period. The k-th scan write signal (GWk) is a signal in which the k-th scan initialization signal (GIk) is shifted by one horizontal period, and the k+1 scan write signal (GWk+1) may be a signal in which the k+1 scan initialization signal (GIk+1) is shifted by one horizontal period. In this case, since the k+1 scan initialization signal (GIk+1) is a signal in which the k-th scan initialization signal (GIk) is shifted by one horizontal period, the k-th scan write signal (GWk) and the k+1 scan initialization signal (GIk+1) may be substantially the same.

[0147] The k-th scan initialization signal (GIk) is a signal for controlling the turn-on and turn-off of the third and tenth transistors (T3, T10) of each of the subpixels (RP, GP, BP). The k-th scan write signal (GWk) is a signal for controlling the turn-on and turn-off of the second, fourth, ninth, and eleventh transistors (T2, T4, T9, T11) of each of the subpixels (RP, GP, BP). The k-th scan control signal (GCk) is a signal for controlling the turn-on and turn-off of the seventh, thirteenth, sixteenth, and eighteenth transistors (T7, T13, T16, T18) of each of the subpixels (RP, GP, BP). The k-th PWM light emission signal (PWEMk) is a signal for controlling the turn-on and turn-off of the 5th, 6th, 12th, and 14th transistors (T5, T6, T12, T14). The k-th PAM light emission signal (PAEMk) is a signal for controlling the turn-on and turn-off of the 17th transistor (T17). The first light emission control signal (RCS1) is a signal for controlling the turn-on and turn-off of the 19th transistor (T19). The second light emission control signal (RCS2) is a signal for controlling the turn-on and turn-off of the 20th transistor (T20). The k-th scan initialization signal, the k-th scan write signal, the k-th scan control signal, the k-th PWM light emission signal, the k-th PAM light emission signal, and the k-th sweep signal may occur with a period of one frame.

[0148] The address period (ADDR) includes the first to fourth periods (t1 to t4). The first period (t1) and the fourth period (t4) are first initialization periods for initializing the voltage (V_N3) of the first electrode of the light-emitting element (EL) and the third node (N3). The second period (t2) is a second initialization period for initializing the gate electrode of the first transistor (T1) and the gate electrode of the eighth transistor (T8). The third period (t3) is a period for sampling the PWM data voltage (Vdata) of the j-th PWM data line (DLj) and the threshold voltage (Vth1) of the first transistor (T1) at the gate electrode of the first transistor (T1), and sampling the first PAM data voltage (Rdata) of the first PAM data line (RDL) and the threshold voltage (Vth8) of the eighth transistor (T8) at the gate electrode of the eighth transistor (T8).

[0149] The first light emission period (EM1) includes the fifth period (t5) and the sixth period (t6). The first light emission period (EM1) is a period for controlling the turn-on period of the 15th transistor (T15) according to the control current (Ic) and supplying a driving current (Ids) to the light-emitting element (EL).

[0150] Each of the second to nth emission periods (EM2~EMn) includes the seventh to ninth periods (t7~t9). The seventh period (t7) is a third initialization period for initializing the third node (N3), the eighth period (t8) is substantially the same period as the fifth period (t5), and the ninth period (t9) is substantially the same period as the sixth period (t6).

[0151] Among the first to nth luminescence periods (EM1~EMn), adjacent luminescence periods may be spaced apart by approximately several to tens of horizontal periods.

[0152] The k-th scan initialization signal (GIk) may have a gate-on voltage (VGL) during the second period (t2) and a gate-off voltage (VGH) during the remaining periods. That is, the k-th scan initialization signal (GIk) may have a scan initialization pulse that occurs at the gate-on voltage (VGL) during the second period (t2). The gate-off voltage (VGH) may be a voltage level higher than the gate-on voltage (VGL).

[0153] The k-th scan write signal (GWk) may have a gate-on voltage (VGL) during the third period (t3) and a gate-off voltage (VGH) during the remaining periods. That is, the k-th scan write signal (GWk) may have a scan write pulse that occurs at the gate-on voltage (VGL) during the third period (t3).

[0154] The k-th scan control signal (GCk) may have a gate-on voltage (VGL) during the first to fourth periods (t1 to t4) and the seventh period (t7), and a gate-off voltage (VGH) during the remaining periods. That is, the k-th scan control signal (GCk) may have a scan control pulse that occurs at the gate-on voltage (VGL) during the first to fourth periods (t1 to t4) and the seventh period (t7).

[0155] The k-th sweep signal (SWPk) may have a triangular wave-shaped sweep pulse during the sixth period (t6) and the ninth period (t9), and may have a gate-off voltage (VGH) during the remaining periods. For example, the sweep pulse of the k-th sweep signal (SWPk) may have a triangular wave-shaped pulse that decreases linearly from the gate-off voltage (VGH) to the gate-on voltage (VGL) during the sixth period (t6) and the ninth period (t9), respectively, and increases directly from the gate-on voltage (VGL) to the gate-off voltage (Voff) at the end of the sixth period (t6) and the end of the ninth period (t9).

[0156] The k-th PWM light emission signal (PWEMk) may have a gate-on voltage (VGL) during the fifth and sixth periods (t5, t6) and the eighth and ninth periods (t8, t9), and a gate-off voltage (VGH) during the remaining periods. That is, the k-th PWM light emission signal (PWEMk) may include PWM pulses generated at the gate-on voltage (VGL) during the fifth and sixth periods (t5, t6) and the eighth and ninth periods (t8, t9). The PWM pulse width of the k-th PWM light emission signal (PWEMk) may be greater than the sweep pulse width of the k-th sweep signal (SWPk).

[0157] The k-th PAM emission signal (PAEMk) may have a gate-on voltage (VGL) during the sixth period (t6) and the ninth period (t9), and a gate-off voltage (VGH) during the remaining periods. That is, the k-th PAM emission signal (PAEMk) may include PAM pulses generated at the gate-on voltage (VGL) during the sixth period (t6) and the ninth period (t9).

[0158] The first light emission control signal (RCS1) has a gate-on voltage (VGL) during the Nth frame period and may have a gate-off voltage (Voff) during the N+1th frame period. The second light emission control signal (RCS2) has a gate-off voltage (Voff) during the Nth frame period and may have a gate-on voltage (VGL) during the N+1th frame period. That is, the first light emission control signal (RCS1) and the second light emission control signal (RCS2) may have different voltages during the 1st frame period.

[0159] FIG. 12 is a timing diagram showing the k-th sweep signal, the voltage of the gate electrode of the first transistor, the turn-on timing of the first transistor, and the turn-on timing of the 15th transistor during the fifth and sixth periods according to one embodiment. FIG. 13 to 16 are circuit diagrams showing the operation of the first subpixel during the first period, second period, third period, fifth period, and sixth period of the N-frame period of FIG. 11.

[0160] Hereinafter, in conjunction with FIGS. 11 to 16, the operation of a first subpixel (RP) according to one embodiment during the first to ninth periods (t1 to t9) during the Nth frame period will be examined in detail.

[0161] During the Nth frame period, the 19th transistor (T19) is turned on by the first light emission control signal (RCS1) of the gate-on voltage (VGL), and the 20th transistor (T20) is turned off by the second light emission control signal (RCS2) of the gate-off voltage (VGH).

[0162] First, during the first period (t1), as shown in FIG. 13, the 11th sub-transistor (T181) and 12th sub-transistor (T182) of the 7th transistor (T7), 13th transistor (T13), 16th transistor (T16), and 18th transistor (T18) are turned on by the k-th scan control signal (GCk) of the gate-on voltage (VGL).

[0163] Due to the turn-on of the 7th transistor (T7), the gate-off voltage (VGH) of the gate-off voltage wiring (VGHL) is applied to the 1st node (N1). Due to the turn-on of the 13th transistor (T13), the 1st power supply voltage (VDD1) of the 1st power supply wiring (VDL1) is applied to the 2nd node (N2).

[0164] Due to the turn-on of the 16th transistor (T16), the 3rd node (N3) is initialized with the initial voltage (VINT) of the initial voltage wiring (VIL), and the 15th transistor (T15) is turned on by the initial voltage (VINT) of the 3rd node (N3).

[0165] Due to the turn-on of the first sub-transistor (T181) and the second sub-transistor (T182) of the 18th transistor (T18), the first electrode of the first sub-light-emitting element (REL1) and the first electrode of the second sub-light-emitting element (REL2) are initialized to the initial voltage (VINT) of the initial voltage wiring (VIL).

[0166] Secondly, during the second period (t2), as shown in FIG. 14, the first sub-transistor (T181) and the second sub-transistor (T182) of the seventh transistor (T7), the thirteenth transistor (T13), the sixteenth transistor (T16), and the eighteenth transistor (T18) are turned on by the k-th scan control signal (GCk) of the gate-on voltage (VGL). Additionally, during the second period (t2), the third transistor (T3) and the tenth transistor (T10) are turned on by the k-th scan initialization signal (GILk) of the gate-on voltage (VGL).

[0167] The first sub-transistor (T181) and the second sub-transistor (T182) of the seventh transistor (T7), the thirteenth transistor (T13), the fifteenth transistor (T15), the sixteenth transistor (T16), and the eighteenth transistor (T18) are substantially the same as those described in the first period (t1).

[0168] Due to the turn-on of the third transistor (T3), the gate electrode of the first transistor (T1) is initialized to the initial voltage (VINT) of the initial voltage wiring (VIL). Also, due to the turn-on of the tenth transistor (T10), the gate electrode of the eighth transistor (T8) is initialized to the initial voltage (VINT) of the initial voltage wiring (VIL).

[0169] At this time, since the gate off voltage (VGH) of the gate off voltage wiring (VGHL) is applied to the first node (N1), the amount of voltage change of the gate electrode of the first transistor (T1) is reflected in the k-th sweep signal wiring (SWPLk) by the first capacitor (PC1), thereby preventing the gate off voltage (VGH) of the k-th sweep signal (SWPk) from fluctuating.

[0170] Thirdly, during the third period (t3), as shown in FIG. 15, the first sub-transistor (T181) and the second sub-transistor (T182) of the seventh transistor (T7), the thirteenth transistor (T13), the sixteenth transistor (T16), and the eighteenth transistor (T18) are turned on by the k-th scan control signal (GCk) of the gate-on voltage (VGL). Also, during the third period (t3), the second transistor (T2), the fourth transistor (T4), the ninth transistor (T9), and the eleventh transistor (T11) are turned on by the k-th scan write signal (GWk) of the gate-on voltage (VGL).

[0171] The first sub-transistor (T181) and the second sub-transistor (T182) of the seventh transistor (T7), the thirteenth transistor (T13), the fifteenth transistor (T15), the sixteenth transistor (T16), and the eighteenth transistor (T18) are substantially the same as those described in the first period (t1).

[0172] Due to the turn-on of the second transistor (T2), the PWM data voltage (Vdata) of the j-th PWM data line (DLj) is applied to the first electrode of the first transistor (T1). Due to the turn-on of the fourth transistor (T4), the gate electrode of the first transistor (T1) and the second electrode are connected to each other, so the first transistor (T1) is driven as a diode.

[0173] At this time, since the voltage between the gate electrode and the first electrode of the first transistor (T1) (Vgs = VINT - Vdata) is greater than the threshold voltage (Vth1), the first transistor (T1) is turned on and forms a current path until the voltage between the gate electrode and the first electrode (Vgs) reaches the threshold voltage (Vth1). As a result, the voltage of the gate electrode of the first transistor (T1) can rise from "VINT" to "Vdata + Vth1". Since the first transistor (T1) is formed as a P-type MOSFET, the threshold voltage (Vth1) of the first transistor (T1) can be less than 0V.

[0174] In addition, since the gate off voltage (VGH) of the gate off voltage wiring (VGHL) is applied to the first node (N1), the amount of voltage change of the gate electrode of the first transistor (T1) is reflected in the k-th sweep signal wiring (SWPLk) by the first capacitor (PC1), thereby preventing the gate off voltage (VGH) of the k-th sweep signal (SWPk) from fluctuating.

[0175] Due to the turn-on of the ninth transistor (T9), the first PAM data voltage (Rdata) of the first PAM data line (RDL) is applied to the first electrode of the eighth transistor (T8). Due to the turn-on of the ninth transistor (T9), the gate electrode and the second electrode of the eighth transistor (T8) are connected to each other, so the eighth transistor (T8) is driven as a diode.

[0176] At this time, since the voltage (Vgs = VINT - Rdata) between the gate electrode and the first electrode of the eighth transistor (T8) is greater than the threshold voltage (Vth8), the eighth transistor (T8) forms a current path until the voltage (Vgs) between the gate electrode and the first electrode reaches the threshold voltage (Vth8). As a result, the voltage of the gate electrode of the eighth transistor (T8) can rise from "VINT" to "Rdata + Vth8".

[0177] Fourth, during the fourth period (t4), the first sub-transistor (T181) and the second sub-transistor (T182) of the seventh transistor (T7), the thirteenth transistor (T13), the sixteenth transistor (T16), and the eighteenth transistor (T18) are turned on by the k-th scan control signal (GCk) of the gate-on voltage (VGL).

[0178] The first sub-transistor (T181) and the second sub-transistor (T182) of the seventh transistor (T7), the thirteenth transistor (T13), the sixteenth transistor (T16), and the eighteenth transistor (T18) are substantially the same as those described in the first period (t1).

[0179] Fifth, during the fifth period (t5), as shown in FIG. 16, the fifth transistor (T5), the sixth transistor (T6), the twelfth transistor (T12), and the fourteenth transistor (T14) are turned on by the k-th PWM light emission signal (PWEMk) of the gate-on voltage (VGL).

[0180] Due to the turn-on of the fifth transistor (T5), the first power supply voltage (VDD1) is applied to the first electrode of the first transistor (T1). Additionally, due to the turn-on of the sixth transistor (T6), the second electrode of the first transistor (T1) is connected to the third node (N3).

[0181] The control current (Ic) flowing according to the voltage (Vdata+Vth1) of the gate electrode of the first transistor (T1) during the fifth period (t5) may not depend on the threshold voltage (Vth1) of the first transistor (T1) as shown in Equation 1.

[0182]

[0183] In Equation 1, k" represents a proportionality constant determined by the structure and physical characteristics of the first transistor (T1), Vth1 represents the threshold voltage of the first transistor (T1), VDD1 represents the first power supply voltage, and Vdata represents the PWM data voltage. In Equation 1, Vgs represents the voltage between the gate electrode and the first electrode of the first transistor (T1).

[0184] Additionally, due to the turn-on of the 12th transistor (T12), the first electrode of the 8th transistor (T8) can be connected to the 2nd power wiring (VDL2).

[0185] Additionally, due to the turn-on of the 14th transistor (T14), the second power supply voltage (VDD2) of the second power supply wiring (VDL2) is applied to the second node (N2). When the second power supply voltage (VDD2) of the second power supply wiring (VDL2) fluctuates due to voltage drop or the like, the voltage difference (ΔV2) between the first power supply voltage (VDD1) and the second power supply voltage (VDD2) can be reflected to the gate electrode of the 8th transistor (T8) by the second capacitor (PC2).

[0186] Due to the turn-on of the 14th transistor (T14), a driving current (Ids) flowing according to the voltage (Rdata+Vth8) of the gate electrode of the 8th transistor (T8) can be supplied to the 15th transistor (T15). The driving current (Ids) may not depend on the threshold voltage (Vth8) of the 8th transistor (T8) as shown in Equation 2.

[0187]

[0188] In Equation 2, k' represents a proportionality constant determined by the structure and physical characteristics of the eighth transistor (T8), Vth8 represents the threshold voltage of the eighth transistor (T8), VDD2 represents the second power supply voltage, and Rdata represents the first PAM data voltage. In Equation 2, Vgs represents the voltage between the gate electrode and the first electrode of the eighth transistor (T8).

[0189] Sixth, during the sixth period (t6), as shown in FIG. 16, the fifth transistor (T5), the sixth transistor (T6), the twelfth transistor (T12), and the fourteenth transistor (T14) are turned on by the k-th PWM light emission signal (PWEMk) at the gate-on voltage (VGL). During the sixth period (t6), as shown in FIG. 16, the seventeenth transistor (T17) is turned on by the k-th PAM light emission signal (PAEMk) at the gate-on voltage (VGL). During the sixth period (t6), the k-th sweep signal (SWPk) decreases linearly from the gate-off voltage (VGH) to the gate-on voltage (VGL).

[0190] The fifth transistor (T5), the sixth transistor (T6), the twelfth transistor (T12), and the fourteenth transistor (T14) are substantially the same as those described in the fifth period (t5).

[0191] During the Nth frame period, the 19th transistor (T19) is turned on by the first light emission control signal (RCS1) of the gate-on voltage (VGL). As a result, when the 17th transistor (T17) is turned on, the first electrode of the first sub-light emitting element (REL1) can be connected to the second electrode of the 15th transistor (T15).

[0192] During the sixth period (t6), the k-th sweep signal (SWPk) decreases linearly from the gate-off voltage (VGH) to the gate-on voltage (VGL). Since the voltage change amount (ΔV1) of the k-th sweep signal (SWPk) is reflected by the first capacitor (PC1) to the gate electrode of the first transistor (T1), the voltage of the gate electrode of the first transistor (T1) can be Vdata + Vth1 - ΔV1. That is, during the sixth period (t6), the voltage of the gate electrode of the first transistor (T1) can be linearly lowered according to the voltage decrease of the k-th sweep signal (SWPk).

[0193] The period during which the control current (Ic) is applied to the third node (N3) can vary depending on the magnitude of the PWM data voltage (Vdata) applied to the first transistor (T1). As a result, since the voltage (V_N3) of the third node (N3) varies depending on the magnitude of the PWM data voltage (Vdata) applied to the first transistor (T1), the turn-on period of the 15th transistor (T15) can be controlled. Therefore, by controlling the turn-on period of the 15th transistor (T15), the period (SEP) during which the driving current (Ids) is applied to the first sub-emissive element (REL1) during the 6th period (t6) can be controlled.

[0194] First, as shown in FIG. 12, when the PWM data voltage (Vdata) of the gate electrode of the first transistor (T1) is a PWM data voltage of peak black gradation, the voltage (VG_T1) of the gate electrode of the first transistor (T1) may be lower than the first power supply voltage (VDD1), which is the voltage of the first electrode of the first transistor (T1), throughout the sixth period (t6) according to the voltage reduction of the k-th sweep signal (SWPk). Therefore, the first transistor (T1) may be turned on throughout the sixth period (t6). As a result, the control current (Ic) of the first transistor (T1) flows to the third node (N3) throughout the fifth period (t5) and the sixth period (t6), and the voltage (V_N3) of the third node (N3) may rise to a high level (VH) during the fifth period (t5). Therefore, the 15th transistor (T15) can be turned off throughout the 6th period (t6). Thus, since the driving current (Ids) is not applied to the 1st sub-light-emitting element (REL1) during the 6th period (t6), the 1st sub-light-emitting element (REL1) may not emit light during the 6th period (t6).

[0195] Additionally, as shown in FIG. 12, when the PWM data voltage (Vdata) of the gate electrode of the first transistor (T1) is a grayscale PWM data voltage, the voltage (VG_T1) of the gate electrode of the first transistor (T1) may have a level higher than the first power supply voltage (VDD1) during the first sub-period (t61) and a level lower than the first power supply voltage (VDD1) during the second sub-period (t62) according to the voltage reduction of the k-th sweep signal (SWPk). Therefore, the first transistor (T1) may be turned on during the second sub-period (t62) of the sixth period (t6). In this case, the control current (Ic) of the first transistor (T1) flows to the third node (N3) during the second sub-period (t62), so the voltage (V_N3) of the third node (N3) may have a high level (VH) during the second sub-period (t62). Therefore, the 15th transistor (T15) can be turned off during the second sub-period (t62). Accordingly, the driving current (Ids) is applied to the first sub-lighting element (REL1) during the first sub-period (t61) and is not applied to the first sub-lighting element (REL1) during the second sub-period (t62). That is, the first sub-lighting element (REL1) can emit light during the first sub-period (t61), which is part of the sixth period (t6). The closer the first sub-pixel (RP) expresses a gray scale close to the peak black scale, the shorter the light emission period (SET) of the first sub-lighting element (REL1) can be. Also, the closer the first sub-pixel (RP) expresses a gray scale close to the peak white scale, the longer the light emission period (SET) of the first sub-lighting element (REL1) can be.

[0196] Additionally, as shown in FIG. 12, when the PWM data voltage (Vdata) of the gate electrode of the first transistor (T1) is a PWM data voltage of peak white gradation, the voltage (VG_T1) of the gate electrode of the first transistor (T1) may be higher than the first power supply voltage (VDD1) during the sixth period (t6), despite the voltage reduction of the k-th sweep signal (SWPk). As a result, the first transistor (T1) may be turned off throughout the sixth period (t6). In this case, since the control current (Ic) of the first transistor (T1) does not flow to the third node (N3) throughout the sixth period (t6), the voltage of the third node (N3) may maintain the initialization voltage (VINT). Therefore, the fifth transistor (T15) may be turned on throughout the sixth period (t6). Accordingly, the driving current (Ids) is applied to the first sub-luminescent element (REL1) throughout the sixth period (t6), and the first sub-luminescent element (REL1) can emit light throughout the sixth period (t6).

[0197] Additionally, as the k-th sweep signal (SWPk) rises from the gate-on voltage (VGL) to the gate-off voltage (VGH) at the end of the sixth period (t6), the voltage (VG_T1) of the gate electrode of the first transistor (T1) at the end of the sixth period (t6) can rise to be substantially the same as in the fifth period (t5).

[0198] Meanwhile, when the digital video data converted into PWM data voltages is 8 bits, the digital video data of the peak black gradation may be 0, and the digital video data of the peak white gradation may be 255. Additionally, the digital video data of the black gradation region may be 0 to 63, the digital video data of the gray gradation region may be 64 to 191, and the digital video data of the white gradation region may be 192 to 255.

[0199] Additionally, each of the 7th period (t7), 8th period (t8), and 9th period (t9) of the 2nd to 9th light-emitting periods (EP2~EPn) is substantially the same as the 1st period (t1), 5th period (t5), and 6th period (t6) described above. That is, in each of the 2nd to 9th light-emitting periods (EP2~EPn), after initializing the 3rd node (N3), the period for applying the driving current (Ids) generated according to the 1st PAM data voltage (Rdata) written to the gate electrode of the 8th transistor (T8) based on the PWM data voltage (Vdata) written to the gate electrode of the 1st transistor (T1) during the address period (ADDR) can be adjusted.

[0200] FIG. 17 is a circuit diagram showing the operation of the first subpixel during the 6th period of the N+1 frame period of FIG. 11.

[0201] Referring to FIG. 17, during the N+1 frame period, the 19th transistor (T19) is turned off by the first light emission control signal (RCS1) of the gate off voltage (VGH), and the 20th transistor (T20) is turned on by the second light emission control signal (RCS2) of the gate on voltage (VGL). Therefore, when the 17th transistor (T17) is turned on, the first electrode of the second sub-light emitting element (REL2) can be connected to the second electrode of the 15th transistor (T15). Accordingly, during the 6th period (t6), a driving current (Ids) is applied to the second sub-light emitting element (REL2), and the second sub-light emitting element (REL2) can emit light.

[0202] That is, the operation of the first subpixel (RP) during the sixth period (t6) of the N+1 frame period is substantially the same as the operation of the first subpixel (RP) during the sixth period (t6) of the Nth frame period described in conjunction with FIG. 16, except that the second sub-lighting element (REL2) emits light instead of the first sub-lighting element (REL1), so the explanation thereof is omitted.

[0203] As seen above, by adjusting the PWM data voltage applied to the gate electrode of the first transistor (T1), the light emission period (SET) of the first sub-light emitting element (REL1) and the light emission period of the second sub-light emitting element (REL2) can be adjusted. Therefore, rather than adjusting the magnitude of the driving current (Ids), the driving current (Ids) can be kept constant, and the period during which the driving current (Ids) is applied to the first sub-light emitting element (REL1) or the second sub-light emitting element (REL2) can be adjusted, thereby adjusting the gradation that the first sub-pixel (RP) intends to express.

[0204] Additionally, the first subpixel (RP) emits light through the first sub-light-emitting element (REL1) during the Nth frame period and through the second sub-light-emitting element (REL2) during the N+1th frame period. That is, the first sub-light-emitting element (REL1) and the second sub-light-emitting element (REL2) of the first subpixel (RP) emit light during different periods. Therefore, the emission period (SET) of the first sub-light-emitting element (REL1) and the emission period of the second sub-light-emitting element (REL2) can be reduced to half compared to the emission period of the second emission element (GEL) and the emission period of the third emission element (BELBEL), respectively. As a result, the amount of heat generated by the first sub-light-emitting element (REL1) and the second sub-light-emitting element (REL2) can be reduced, thereby allowing the temperature of the first sub-light-emitting element (REL1) and the second sub-light-emitting element (REL2) to be lowered. Therefore, it is possible to reduce or prevent the decrease in the luminous brightness of the first sub-luminous element (REL1) and the second sub-luminous element (REL2) due to the heat generated by the first sub-luminous element (REL1) and the second sub-luminous element (REL2).

[0205] FIG. 18 is a circuit diagram showing the operation of the second subpixel during the sixth period of the Nth frame period and the N+1th frame period of FIG. 11.

[0206] Referring to FIG. 18, the second subpixel (GP) includes a second light-emitting element (GEL), and when the 17th transistor (T17) is turned on, the first electrode of the second light-emitting element (GEL) can be connected to the second electrode of the 15th transistor (T15). Accordingly, during the 6th period (t6), a driving current (Ids) is applied to the second light-emitting element (GEL), and the second light-emitting element (GEL) can emit light.

[0207] That is, the operation of the second subpixel (GP) during the sixth period (t6) is substantially the same as the operation of the first subpixel (RP) during the sixth period (t6) of the Nth frame period described in conjunction with FIG. 16, except that the second light-emitting element (GEL) emits light regardless of the Nth frame period and the N+1th frame period, so the explanation thereof is omitted.

[0208] In addition, the operation of the first to fifth periods (t1 to t5) of the second subpixel (GP) can also operate substantially the same as the operation of the first to fifth periods (t1 to t5) of the first subpixel (RP) described in conjunction with FIGS. 11 to 16, so a description thereof is omitted.

[0209] Meanwhile, since the operation of the third subpixel (BP) is substantially the same as that of the second subpixel (GP), the description of the operation of the third subpixel (BP) during the first to sixth periods (t1 to t6) of the Nth frame period and the N+1st frame period is omitted.

[0210] FIGS. 19 and FIGS. 20 are layout diagrams showing pixels according to one embodiment. FIG. 21 is an enlarged layout diagram showing area A of FIG. 19 in detail. FIG. 22 is an enlarged layout diagram showing area B of FIG. 19 in detail. FIG. 23 is an enlarged layout diagram showing area A of FIG. 20 in detail. FIG. 24 is an enlarged layout diagram showing area C of FIG. 19 in detail. FIG. 25 is an enlarged layout diagram showing area D of FIG. 19 in detail. FIG. 26 is an enlarged layout diagram showing area C of FIG. 20 in detail.

[0211] FIGS. 19, 21, 22, 24, and 25 show the layouts of a pixel according to one embodiment, including a lower metal layer, an active layer, a first gate metal layer, a second gate metal layer, a first source metal layer, and a second source metal layer. FIG. 20 shows the layouts of a third source metal layer and a fourth source metal layer in addition to the layout of FIG. 19, and FIG. 23 shows the layouts of a third source metal layer and a fourth source metal layer in addition to the layout of FIG. 21. FIG. 26 shows the layouts of a third source metal layer and a fourth source metal layer in addition to the layout of FIG. 25.

[0212] Referring to FIGS. 19 through 26, the initialization voltage wires (VIL), the k-th scan initialization wire (GILk), the k-th scan write wire (GWLk), the k-th PWM light emission wire (PWELk), the first horizontal power wire (HVDL), the gate off voltage wire (VGHL), the k-th sweep signal wire (SWPLk), the k-th scan control wire (GCLk), the k-th PAM light emission wire (PAELk), the first light emission control wire (RCL1), and the second light emission control wire (RCL2) can be extended in a first direction (DR1). The initialization voltage wires (VIL), the k-th scan initialization wire (GILk), the k-th scan write wire (GWLk), the k-th PWM light emission wire (PWELk), the first horizontal power wire (HVDL), the gate off voltage wire (VGHL), the k-th sweep signal wire (SWPLk), the k-th scan control wire (GCLk), the k-th PAM light emission wire (PAELk), the test signal wire, and the third power wire (VSL) may be spaced apart in the second direction (DR2).

[0213] The j-th PWM data line (DLj), the first vertical power line (VVDL), and the first PAM data line (RDL) may be extended in a second direction (DR2). Additionally, the second PAM data line (GDL) and the third PAM data line (BDL) shown in FIG. 1 may be extended in a second direction (DR2). The j-th PWM data line (DLj), the first vertical power line (VVDL), the first PAM data line (RDL), the second PAM data line (GDL), and the third PAM data line (BDL) may be spaced apart in a first direction (DR1).

[0214] First, the layout of the first subpixel (RP) will be described in detail with reference to FIGS. 19 to 23.

[0215] Referring to FIGS. 19 to 23, the first subpixel (RP) includes first to 20 transistors (T1 to T20), first to 6 capacitor electrodes (CE1 to CE6), first to 8 gate connection electrodes (GCE1 to GCE8), first and second data connection electrodes (DCE1, DCE2), first to 9 source connection electrodes (CCE1 to CCE9), first to 5 connection electrodes (CNE1 to CNE5), a first anode pad electrode (APD1), a second anode pad electrode (APD2), a cathode pad electrode (CPD), a first sub-emissive element (REL1), and a second sub-emissive element (REL2).

[0216] The first transistor (T1) includes a first channel (CH1), a first gate electrode (G1), a first source electrode (S1), and a first drain electrode (D1). The first channel (CH1) may extend in a first direction (DR1). The first channel (CH1) may overlap with the first gate electrode (G1) in a third direction (DR3). The first gate electrode (G1) may be connected to the first source connection electrode (CCE1) through a first contact hole (CT1). The first gate electrode (G1) may be formed integrally with the first capacitor electrode (CE1). The first gate electrode (G1) may overlap with the second capacitor electrode (CE2) in a third direction (DR3). The first source electrode (S1) may be placed on one side of the first channel (CH1), and the first drain electrode (D1) may be placed on the other side of the first channel (CH1). The first source electrode (S1) can be connected to the second drain electrode (D2) and the fifth drain electrode (D5). The first drain electrode (D1) can be connected to the third sub-source electrode (S41) and the sixth source electrode (S6). The first source electrode (S1) and the first drain electrode (D1) may not overlap with the first gate electrode (G1) in the third direction (DR3). The first source electrode (S1) and the first drain electrode (D1) may overlap with the second capacitor electrode (CE2) in the third direction (DR3).

[0217] The second transistor (T2) includes a second channel (CH2), a second gate electrode (G2), a second source electrode (S2), and a second drain electrode (D2). The second channel (CH2) may overlap with the second gate electrode (G2) in a third direction (DR3). The second gate electrode (G2) may be formed integrally with the first gate connection electrode (GCE1). The second source electrode (S2) may be placed on one side of the second channel (CH2), and the second drain electrode (D2) may be placed on the other side of the second channel (CH2). The second source electrode (S2) may be connected to the first data connection electrode (DCE1) through the first data contact hole (DCT1). The second drain electrode (D2) may be connected to the first source electrode (S1). The second source electrode (S2) and the second drain electrode (D2) may not overlap with the second gate electrode (G2) in the third direction (DR3). The second drain electrode (D2) may extend in the second direction (DR2).

[0218] The first sub-transistor (T31) of the third transistor (T3) includes a first sub-channel (CH31), a first sub-gate electrode (G31), a first sub-source electrode (S31), and a first sub-drain electrode (D31). The first sub-channel (CH31) may overlap with the first sub-gate electrode (G31) in the third direction (DR3). The first sub-gate electrode (G31) may be formed integrally with the second gate connection electrode (GCE2). The first sub-source electrode (S31) may be disposed on one side of the first sub-channel (CH31), and the first sub-drain electrode (D31) may be disposed on the other side of the first sub-channel (CH31). The first sub-source electrode (S31) may be connected to the fourth sub-drain electrode (D42), and the first sub-drain electrode (D31) may be connected to the second sub-source electrode (S32). The first sub-source electrode (S31) and the first sub-drain electrode (D31) may not overlap with the first sub-gate electrode (G31). The first sub-source electrode (S31) may overlap with the k-th scan write wiring (GWLk) in the third direction (DR3). The first sub-drain electrode (S32) may overlap with the initialization voltage wiring (VIL) in the third direction (DR3).

[0219] The second sub-transistor (T32) of the third transistor (T3) includes a second sub-channel (CH32), a second sub-gate electrode (G32), a second sub-source electrode (S32), and a second sub-drain electrode (D32). The second sub-channel (CH32) may overlap with the second sub-gate electrode (G32) in the third direction (DR3). The second sub-gate electrode (G32) may be formed integrally with the second gate connection electrode (GCE2). The second sub-source electrode (S32) may be placed on one side of the second sub-channel (CH32), and the second sub-drain electrode (D32) may be placed on the other side of the second sub-channel (CH32). The second sub-source electrode (S32) is connected to the first sub-drain electrode (D31), and the second sub-drain electrode (D32) may be connected to the initialization voltage wiring (VIL) through the first power contact hole (VCT1). The second sub-source electrode (S32) and the second sub-drain electrode (D32) may not overlap with the second sub-gate electrode (G32). The second sub-source electrode (S32) and the second sub-drain electrode (D32) may overlap with the initialization voltage wiring (VIL) in the third direction (DR3).

[0220] The third sub-transistor (T41) of the fourth transistor (T4) includes a third sub-channel (CH41), a third sub-gate electrode (G41), a third sub-source electrode (S41), and a third sub-drain electrode (D41). The third sub-channel (CH41) may overlap with the third sub-gate electrode (G41) in the third direction (DR3). The third sub-gate electrode (G41) may be formed integrally with the first gate connection electrode (GCE1). The third sub-source electrode (S41) may be disposed on one side of the third sub-channel (CH41), and the third sub-drain electrode (D31) may be disposed on the other side of the third sub-channel (CH41). The third sub-source electrode (S41) may be connected to the first drain electrode (D1), and the third sub-drain electrode (D41) may be connected to the fourth sub-source electrode (S42). The third sub-source electrode (S41) and the third sub-drain electrode (D41) may not overlap with the third sub-gate electrode (G41).

[0221] The fourth sub-transistor (T42) of the fourth transistor (T4) includes a fourth sub-channel (CH42), a fourth sub-gate electrode (G42), a fourth sub-source electrode (S42), and a fourth sub-drain electrode (D42). The fourth sub-channel (CH42) may overlap with the fourth sub-gate electrode (G42) in the third direction (DR3). The fourth sub-gate electrode (G42) may be formed integrally with the second gate connection electrode (GCE2). The fourth sub-source electrode (S42) may be disposed on one side of the fourth sub-channel (CH42), and the fourth sub-drain electrode (D42) may be disposed on the other side of the fourth sub-channel (CH42). The fourth sub-source electrode (S42) may be connected to the third sub-drain electrode (D32), and the fourth sub-drain electrode (D42) may be connected to the first sub-source electrode (S31). The fourth sub-source electrode (S42) and the fourth sub-drain electrode (D42) may not overlap with the fourth sub-gate electrode (G42).

[0222] The fifth transistor (T5) includes a fifth channel (CH5), a fifth gate electrode (G5), a fifth source electrode (S5), and a fifth drain electrode (D5). The fifth channel (CH5) may overlap with the fifth gate electrode (G5) in the third direction (DR3). The fifth gate electrode (G5) may be formed integrally with the sixth gate connection electrode (GCE6). The fifth source electrode (S5) may be placed on one side of the fifth channel (CH5), and the fifth drain electrode (D5) may be placed on the other side of the fifth channel (CH5). The fifth source electrode (S5) may be connected to the first horizontal power wiring (HVDL) through the second power contact hole (VCT2). The fifth drain electrode (D5) may be connected to the first source electrode (S1). The fifth source electrode (S5) and the fifth drain electrode (D5) may not overlap with the fifth gate electrode (G5) in the third direction (DR3). The fifth drain electrode (D5) may overlap with the extension (EX) of the second capacitor electrode (CE2) in the third direction (DR3).

[0223] The sixth transistor (T6) includes a sixth channel (CH6), a sixth gate electrode (G6), a sixth source electrode (S6), and a sixth drain electrode (D6). The sixth channel (CH6) may overlap with the sixth gate electrode (G6) in the third direction (DR3). The sixth gate electrode (G6) may be formed integrally with the sixth gate connection electrode (GCE6). The sixth source electrode (S6) may be placed on one side of the sixth channel (CH6), and the sixth drain electrode (D6) may be placed on the other side of the sixth channel (CH6). The sixth source electrode (S6) may be connected to the first drain electrode (D1). The sixth drain electrode (D6) may be connected to the fourth source connection electrode (CCE4) through the tenth contact hole (CT10). The sixth source electrode (S6) and the sixth drain electrode (D6) may not overlap with the sixth gate electrode (G6) in the third direction (DR3). The sixth drain electrode (D6) may overlap with the second source connection electrode (CCE2) and the first horizontal power wiring (HVDL) in the third direction (DR3).

[0224] The seventh transistor (T7) includes a seventh channel (CH7), a seventh gate electrode (G7), a seventh source electrode (S7), and a seventh drain electrode (D7). The seventh channel (CH7) may overlap with the seventh gate electrode (G7) in the third direction (DR3). The seventh gate electrode (G7) may be formed integrally with the third gate connection electrode (GCE3). The seventh gate electrode (G7) may overlap with the initialization voltage wiring (VIL) in the third direction (DR3). The seventh source electrode (S7) may be placed on one side of the seventh channel (CH7), and the seventh drain electrode (D7) may be placed on the other side of the seventh channel (CH7). The seventh source electrode (S7) may be connected to the gate off voltage wiring (VGHL) through the seventh contact hole (CT7). The seventh drain electrode (D7) can be connected to the k-th sweep signal wiring (SWPLk) through the sixth contact hole (CT6). The seventh source electrode (S7) and the seventh drain electrode (D7) may not overlap with the seventh gate electrode (G7) in the third direction (DR3).

[0225] The eighth transistor (T8) includes an eighth channel (CH8), an eighth gate electrode (G8), an eighth source electrode (S8), and an eighth drain electrode (D8). The eighth channel (CH8) may overlap with the eighth gate electrode (G8) in the third direction (DR3). The eighth gate electrode (G8) may extend in the second direction (DR2). The eighth gate electrode (G8) may be formed integrally with the third capacitor electrode (CE3). The eighth source electrode (S8) may be placed on one side of the eighth channel (CH8), and the eighth drain electrode (D8) may be placed on the other side of the eighth channel (CH8). The eighth source electrode (S8) may be connected to the ninth drain electrode (D9) and the twelfth drain electrode (D12). The eighth drain electrode (D8) may be connected to the seventh sub-source electrode (S111). The 8th source electrode (S8) and the 8th drain electrode (D8) may not overlap with the 8th gate electrode (G8) in the 3rd direction (DR3).

[0226] The ninth transistor (T9) includes a ninth channel (CH9), a ninth gate electrode (G9), a ninth source electrode (S9), and a ninth drain electrode (D9). The ninth channel (CH9) may overlap with the ninth gate electrode (G9) in the third direction (DR3). The ninth gate electrode (G9) may extend in the second direction (DR2). The ninth gate electrode (G9) may be formed integrally with the first gate connection electrode (GCE1). The ninth source electrode (S9) may be placed on one side of the ninth channel (CH9), and the ninth drain electrode (D9) may be placed on the other side of the ninth channel (CH9). The ninth source electrode (S9) may be connected to the second data connection electrode (DCE2) through the third data contact hole (DCT3). The ninth drain electrode (D9) may be connected to the eighth source electrode (D8). The ninth source electrode (S9) and the ninth drain electrode (D9) may not overlap with the ninth gate electrode (G9) in the third direction (DR3).

[0227] The fifth sub-transistor (T101) of the tenth transistor (T10) includes a fifth sub-channel (CH101), a fifth sub-gate electrode (G101), a fifth sub-source electrode (S101), and a fifth sub-drain electrode (D101). The fifth sub-channel (CH101) may overlap with the fifth sub-gate electrode (G101) in the third direction (DR3). The fifth sub-gate electrode (G101) may be formed integrally with the second gate connection electrode (GCE2). The fifth sub-source electrode (S101) may be disposed on one side of the fifth sub-channel (CH101), and the fifth sub-drain electrode (D101) may be disposed on the other side of the fifth sub-channel (CH101). The fifth sub-source electrode (S101) is connected to the eighth sub-drain electrode (D112), and the fifth sub-drain electrode (D101) may be connected to the sixth sub-source electrode (S102). The fifth sub-source electrode (S101) and the fifth sub-drain electrode (D101) may not overlap with the fifth sub-gate electrode (G101). The fifth sub-source electrode (S101) may overlap with the k-th scan write wiring (GWLk) in the third direction (DR3). The fifth sub-drain electrode (D101) may overlap with the initialization voltage wiring (VIL) in the third direction (DR3).

[0228] The sixth sub-transistor (T102) of the tenth transistor (T10) includes a sixth sub-channel (CH102), a sixth sub-gate electrode (G102), a sixth sub-source electrode (S102), and a sixth sub-drain electrode (D102). The sixth sub-channel (CH102) may overlap with the sixth sub-gate electrode (G102) in the third direction (DR3). The sixth sub-gate electrode (G102) may be formed integrally with the second gate connection electrode (GCE2). The sixth sub-source electrode (S102) may be disposed on one side of the sixth sub-channel (CH102), and the sixth sub-drain electrode (D102) may be disposed on the other side of the sixth sub-channel (CH102). The sixth sub-source electrode (S102) is connected to the fifth sub-drain electrode (D101), and the sixth sub-drain electrode (D102) can be connected to the initialization voltage wiring (VIL) through the first power contact hole (VCT1). The sixth sub-source electrode (S102) and the sixth sub-drain electrode (D102) may not overlap with the sixth sub-gate electrode (G102). The sixth sub-source electrode (S102) and the sixth sub-drain electrode (D102) may overlap with the initialization voltage wiring (VIL) in the third direction (DR3).

[0229] The seventh sub-transistor (T111) of the eleventh transistor (T11) includes a seventh sub-channel (CH111), a seventh sub-gate electrode (G111), a seventh sub-source electrode (S111), and a seventh sub-drain electrode (D111). The seventh sub-channel (CH111) may overlap with the seventh sub-gate electrode (G111) in the third direction (DR3). The seventh sub-gate electrode (G111) may be formed integrally with the first gate connection electrode (GCE1). The seventh sub-source electrode (S111) may be disposed on one side of the seventh sub-channel (CH111), and the seventh sub-drain electrode (D111) may be disposed on the other side of the seventh sub-channel (CH111). The seventh sub-source electrode (S111) is connected to the eighth drain electrode (D8), and the seventh sub-drain electrode (D111) can be connected to the eighth sub-source electrode (S112). The seventh sub-source electrode (S111) and the seventh sub-drain electrode (D111) may not overlap with the seventh sub-gate electrode (G111).

[0230] The eighth sub-transistor (T112) of the eleventh transistor (T11) includes an eighth sub-channel (CH112), an eighth sub-gate electrode (G112), an eighth sub-source electrode (S112), and an eighth sub-drain electrode (D112). The eighth sub-channel (CH112) may overlap with the eighth sub-gate electrode (G112) in the third direction (DR3). The eighth sub-gate electrode (G112) may be formed integrally with the first gate connection electrode (GCE1). The eighth sub-source electrode (S112) may be disposed on one side of the eighth sub-channel (CH112), and the eighth sub-drain electrode (D112) may be disposed on the other side of the eighth sub-channel (CH112). The eighth sub-source electrode (S112) is connected to the seventh sub-drain electrode (D111), and the eighth sub-drain electrode (D112) can be connected to the fifth sub-source electrode (S101). The eighth sub-source electrode (S112) and the eighth sub-drain electrode (D112) may not overlap with the eighth sub-gate electrode (G112).

[0231] The 12th transistor (T12) includes a 12th channel (CH12), a 12th gate electrode (G12), a 12th source electrode (S12), and a 12th drain electrode (D12). The 12th channel (CH12) may overlap with the 12th gate electrode (G12) in a third direction (DR3). The 12th gate electrode (G12) may be formed integrally with the 6th gate connection electrode (GCE6). The 12th source electrode (S12) may be disposed on one side of the 12th channel (CH12), and the 12th drain electrode (D12) may be disposed on the other side of the 12th channel (CH12). The 12th source electrode (S12) may be connected to the 5th source connection electrode (CCE5) through the 11th contact holes (CT11). The 12th source electrode (S12) and the 12th drain electrode (D12) may not overlap with the 12th gate electrode (G12) in the 3rd direction (DR3).

[0232] The 13th transistor (T13) includes a 13th channel (CH13), a 13th gate electrode (G13), a 13th source electrode (S13), and a 13th drain electrode (D13). The 13th channel (CH13) may overlap with the 13th gate electrode (G13) in the 3rd direction (DR3). The 13th gate electrode (G13) may be formed integrally with the 3rd gate connection electrode (GCE3). The 13th source electrode (S13) may be placed on one side of the 13th channel (CH13), and the 13th drain electrode (D13) may be placed on the other side of the 13th channel (CH13). The 13th source electrode (S13) may be connected to the 1st horizontal power wiring (HVDL) through the 2nd power contact hole (VCT2). The 13th drain electrode (D13) can be connected to the 2nd source connection electrode (CCE2) through the 3rd contact hole (CT3). The 13th source electrode (S13) and the 13th drain electrode (D13) may not overlap with the 13th gate electrode (G13) in the 3rd direction (DR3).

[0233] The 14th transistor (T14) includes a 14th channel (CH14), a 14th gate electrode (G14), a 14th source electrode (S14), and a 14th drain electrode (D14). The 14th channel (CH14) may overlap with the 14th gate electrode (G14) in the third direction (DR3). The 14th gate electrode (G14) may be formed integrally with the 6th gate connection electrode (GCE6). The 14th source electrode (S14) may be disposed on one side of the 14th channel (CH14), and the 14th drain electrode (D14) may be disposed on the other side of the 14th channel (CH14). The 14th source electrode (S14) may be connected to the 5th source connection electrode (CCE5) through the 11th contact holes (CT11). The 14th drain electrode (D14) can be connected to the 2nd source connection electrode (CCE2) through the 4th contact hole (CT4). The 14th source electrode (S14) and the 14th drain electrode (D14) may not overlap with the 14th gate electrode (G14) in the 3rd direction (DR3).

[0234] The 15th transistor (T15) includes a 15th channel (CH15), a 15th gate electrode (G15), a 15th source electrode (S15), and a 15th drain electrode (D15). The 15th channel (CH15) may overlap with the 15th gate electrode (G15) in the third direction (DR3). The 15th gate electrode (G15) may be formed integrally with the 5th capacitor electrode (CE5). The 15th source electrode (S15) may be placed on one side of the 15th channel (CH15), and the 15th drain electrode (D15) may be placed on the other side of the 15th channel (CH15). The 15th source electrode (S15) may be connected to the 9th drain electrode (D5). The 15th drain electrode (D15) may be connected to the 17th source electrode (S17). The 15th source electrode (S15) and the 15th drain electrode (D15) may not overlap with the 15th gate electrode (G15) in the 3rd direction (DR3).

[0235] The ninth sub-transistor (T161) of the 16th transistor (T16) includes a ninth sub-channel (CH161), a ninth sub-gate electrode (G161), a ninth sub-source electrode (S161), and a ninth sub-drain electrode (D161). The ninth sub-channel (CH161) may overlap with the ninth sub-gate electrode (G161) in the third direction (DR3). The ninth sub-gate electrode (G161) may be formed integrally with the third gate connection electrode (GCE3). The ninth sub-source electrode (S161) may be disposed on one side of the ninth sub-channel (CH161), and the ninth sub-drain electrode (D161) may be disposed on the other side of the ninth sub-channel (CH161). The ninth sub-source electrode (S161) is connected to the fourth source connection electrode (CCE4) through the tenth contact hole (CT10), and the ninth sub-drain electrode (D161) can be connected to the tenth sub-source electrode (S162). The ninth sub-source electrode (S161) and the ninth sub-drain electrode (D161) may not overlap with the ninth sub-gate electrode (G161).

[0236] The 10th sub-transistor (T162) of the 16th transistor (T16) includes a 10th sub-channel (CH162), a 10th sub-gate electrode (G162), a 10th sub-source electrode (S162), and a 10th sub-drain electrode (D162). The 10th sub-channel (CH162) may overlap with the 10th sub-gate electrode (G162) in the third direction (DR3). The 10th sub-gate electrode (G162) may be formed integrally with the third gate connection electrode (GCE3). The 10th sub-source electrode (S162) may be disposed on one side of the 10th sub-channel (CH162), and the 10th sub-drain electrode (D162) may be disposed on the other side of the 10th sub-channel (CH162). The 10th sub-source electrode (S162) is connected to the 9th sub-drain electrode (D161), and the 10th sub-drain electrode (D162) can be connected to the initialization voltage wiring (VIL) through the 9th contact hole (CT9). The 10th sub-source electrode (S162) and the 10th sub-drain electrode (D162) may not overlap with the 10th sub-gate electrode (G162).

[0237] The 17th transistor (T17) includes a 17th channel (CH17), a 17th gate electrode (G17), a 17th source electrode (S17), and a 17th drain electrode (D17). The 17th channel (CH17) may overlap with the 17th gate electrode (G17) in the third direction (DR3). The 17th gate electrode (G17) may be formed integrally with the 5th gate connection electrode (GCE5). The 17th source electrode (S17) may be placed on one side of the 17th channel (CH17), and the 17th drain electrode (D17) may be placed on the other side of the 17th channel (CH17). The 17th source electrode (S17) may be connected to the 15th drain electrode (D15). The 17th drain electrode (D17) may be connected to the 7th source connection electrode (CCE7) through the 16th contact holes (CT16). The 17th source electrode (S17) and the 17th drain electrode (D17) may not overlap with the 17th gate electrode (G17) in the 3rd direction (DR3).

[0238] The 11th sub-transistor (T181) of the 18th transistor (T18) includes a 11th sub-channel (CH181), a 11th sub-gate electrode (G181), a 11th sub-source electrode (S181), and a 11th sub-drain electrode (D181). The 11th sub-channel (CH181) may overlap with the 11th sub-gate electrode (G181) in the third direction (DR3). The 11th sub-gate electrode (G181) may be formed integrally with the third gate connection electrode (GCE3). The 11th sub-source electrode (S181) may be disposed on one side of the 11th sub-channel (CH181), and the 11th sub-drain electrode (D181) may be disposed on the other side of the 11th sub-channel (CH181). The 11th sub-source electrode (S181) can be connected to the initialization voltage wiring (VIL) through the 21st contact hole (CT21). The 11th sub-drain electrode (D181) can be connected to the 8th source connection electrode (CCE8) through the 25th contact hole (CT25). The 11th sub-source electrode (S181) and the 11th sub-drain electrode (D181) may not overlap with the 11th sub-gate electrode (G181) in the 3rd direction (DR3).

[0239] The 12th sub-transistor (T182) of the 18th transistor (T18) includes a 12th sub-channel (CH182), a 12th sub-gate electrode (G182), a 12th sub-source electrode (S182), and a 12th sub-drain electrode (D182). The 12th sub-channel (CH182) may overlap with the 12th sub-gate electrode (G182) in a third direction (DR3). The 12th sub-gate electrode (G182) may be formed integrally with the third gate connection electrode (GCE3). The 12th sub-source electrode (S182) may be disposed on one side of the 12th sub-channel (CH182), and the 12th sub-drain electrode (D182) may be disposed on the other side of the 12th sub-channel (CH182). The 12th sub-source electrode (S182) can be connected to the initial voltage wiring (VIL) through the 21st contact hole (CT21). The 12th sub-drain electrode (D182) can be connected to the 9th source connection electrode (CCE9) through the 26th contact hole (CT26). The 12th sub-source electrode (S182) and the 12th sub-drain electrode (D182) may not overlap with the 12th sub-gate electrode (G182) in the 3rd direction (DR3).

[0240] The 19th transistor (T19) includes a 19th channel (CH19), a 19th gate electrode (G19), a 19th source electrode (S19), and a 19th drain electrode (D19). The 19th channel (CH19) may overlap with the 19th gate electrode (G19) in the third direction (DR3). The 19th gate electrode (G19) may be formed integrally with the 7th gate connection electrode (GCE7). The 19th source electrode (S19) may be disposed on one side of the 19th channel (CH19), and the 19th drain electrode (D19) may be disposed on the other side of the 19th channel (CH19). The 19th source electrode (S19) may be connected to the 3rd source connection electrode (CCE3) through the 24th contact hole (CT24). The 19th drain electrode (D19) can be connected to the 8th source connection electrode (CCE8) through the 25th contact hole (CT25). The 19th source electrode (S19) and the 19th drain electrode (D19) may not overlap with the 19th gate electrode (G19) in the 3rd direction (DR3).

[0241] The 20th transistor (T20) includes a 20th channel (CH20), a 20th gate electrode (G20), a 20th source electrode (S20), and a 20th drain electrode (D20). The 20th channel (CH20) may overlap with the 20th gate electrode (G20) in the third direction (DR3). The 20th gate electrode (G20) may be formed integrally with the 8th gate connection electrode (GCE8). The 20th source electrode (S20) may be disposed on one side of the 20th channel (CH20), and the 20th drain electrode (D20) may be disposed on the other side of the 20th channel (CH20). The 20th source electrode (S20) may be connected to the 3rd source connection electrode (CCE3) through the 24th contact hole (CT24). The 20th drain electrode (D20) can be connected to the 9th source connection electrode (CCE9) through the 26th contact hole (CT26). The 20th source electrode (S20) and the 20th drain electrode (D20) may not overlap with the 20th gate electrode (G20) in the 3rd direction (DR3).

[0242] The first capacitor electrode (CE1) can be formed integrally with the first gate electrode (G1). The second capacitor electrode (CE2) can overlap with the first capacitor electrode (CE1) in the third direction (DR3). The first capacitor electrode (CE1) may be one electrode of the first capacitor (PC1), and the second capacitor electrode (CE2) may be the other electrode of the first capacitor (PC1).

[0243] The second capacitor electrode (CE2) includes a hole that exposes the first gate electrode (G1), and the first source connection electrode (CCE1) can be connected to the first gate electrode (G1) through the first contact hole (CT1) in the hole.

[0244] The second capacitor electrode (CE2) may include an extension (EX) extending in the second direction (DR2). The extension (EX) of the second capacitor electrode (CE2) may intersect with the k-th PWM light-emitting wiring (PWELk) and the first horizontal voltage wiring (HVDL). The extension (EX) of the second capacitor (CE2) may be connected to the k-th sweep signal wiring (SWPLk) through the fifth contact hole (CT5).

[0245] The third capacitor electrode (CE3) can be formed integrally with the eighth gate electrode (G8). The fourth capacitor electrode (CE4) can overlap with the third capacitor electrode (CE3) in the third direction (DR3). The third capacitor electrode (CE3) may be one electrode of the second capacitor (PC2), and the fourth capacitor electrode (CE4) may be the other electrode of the second capacitor (PC2).

[0246] The fourth capacitor electrode (CE4) includes a hole that exposes the eighth gate electrode (G8), and the sixth source connection electrode (CCE6) can be connected to the eighth gate electrode (G8) through the 12th contact hole (CT12) in the hole.

[0247] The fifth capacitor electrode (CE5) may be formed integrally with the fourth gate connection electrode (GCE4) and the fifth gate electrode (G15). The sixth capacitor electrode (CE6) may overlap with the fifth capacitor electrode (CE5) in the third direction (DR3). The fifth capacitor electrode (CE5) may be one electrode of the third capacitor (PC3), and the sixth capacitor electrode (CE6) may be the other electrode of the third capacitor (PC3). The sixth capacitor electrode (CE6) may be connected to the initialization voltage wiring (VIL) through the eighteenth contact hole (CT18).

[0248] The first gate connection electrode (GCE1) can be connected to the k-th scan write wire (GWLk) through the first gate contact hole (GCT1) and the third gate contact hole (GCT3). The second gate connection electrode (GCE2) can be connected to the k-th scan initialization wire (GILk) through the second gate contact hole (GCT2). The third gate connection electrode (GCE3) can be connected to the k-th scan control wire (GCLk) through the eighth contact hole (CT8). The fourth gate connection electrode (GCE4) can be connected to the fourth source connection electrode (CCE4) through the seventeenth contact hole (CT17). The fifth gate connection electrode (GCE5) can be connected to the k-th PAM light emission wire (PAELk) through the nineteenth contact hole (CT19). The 6th gate connection electrode (GCE6) can be connected to the kth PWM light emission wiring (PWELk) through the 14th contact hole (CT14). The 7th gate connection electrode (GCE7) can be connected to the 1st light emission control wiring (RCL1) through the 22nd contact hole (CT22). The 8th gate connection electrode (GCE8) can be connected to the 2nd light emission control wiring (RCL2) through the 23rd contact hole (CT23).

[0249] The first data connection electrode (DCE1) can be connected to the second source electrode (S2) through the first data contact hole (DCT1) and to the j-th PWM data wiring (DLj) through the second data contact hole (DCT2). The second data connection electrode (DCE2) can be connected to the ninth source electrode (S9) through the third data contact hole (DCT3) and to the first PAM data wiring (RDL) through the fourth data contact hole (DCT4).

[0250] The first source connection electrode (CCE1) can be extended in a second direction (DR2). The first source connection electrode (CCE1) can be connected to the first gate electrode (G1) through the first contact hole (CT1) and to the first sub-source electrode (S31) and the fourth sub-drain electrode (D42) through the second contact hole (CT2).

[0251] The second source connection electrode (CCE2) can be extended in the first direction (DR1). The second source connection electrode (CCE2) can be connected to the 12th drain electrode (D12) through the third contact hole (CT3), connected to the 14th drain electrode (D14) through the fourth contact hole (CT4), and connected to the 4th capacitor electrode (CE4) through the 15th contact hole (CT15).

[0252] The third source connection electrode (CCE3) can be connected to the 19th source electrode (S19) and the 20th source electrode (S20) through the 24th contact hole (CT24), and can be connected to the first connection electrode (CNE1) through the 27th contact hole (CT27).

[0253] The fourth source connection electrode (CCE4) can be extended in the first direction (DR1). The fourth source connection electrode (CCE4) can be connected to the sixth drain electrode (D6) and the ninth sub-source electrode (S161) through the tenth contact hole (CT10), and can be connected to the fourth gate connection electrode (GCE4) through the seventh contact hole (CT17).

[0254] The fifth source connection electrode (CCE5) can be extended in the first direction (DR1). The fifth source connection electrode (CCE5) is connected to the 12th source electrode (S12) and the 14th source electrode (S14) through the 11th contact holes (CT11), and can be connected to the 4th capacitor electrode (CE4) through the 4th power contact hole (VCT4).

[0255] The sixth source connection electrode (CCE6) can be extended in the second direction (DR2). The sixth source connection electrode (CCE6) can be connected to the third capacitor electrode (CE3) through the twelfth contact hole (CT12) and to the fifth sub-source electrode (S101) and the eighth sub-drain electrode (D112) through the thirteenth contact hole (CT13).

[0256] The seventh source connection electrode (CCE7) can be connected to the seventh drain electrode (D17) and the eighth drain electrode (D18) through the sixth contact holes (CT16). The seventh source connection electrode (CCE7) can be connected to the first connection electrode (CNE1) through the twentieth contact hole (CT20).

[0257] The 8th source connection electrode (CCE8) can be connected to the 11th sub-drain electrode (D181) of the 11th sub-transistor (T181) of the 18th transistor (T18) and the 19th drain electrode (D19) of the 19th transistor (T19) through the 25th contact hole (CT25). The 8th source connection electrode (CCE8) can be connected to the 2nd connection electrode (CNE2) through the 28th contact hole (CT28).

[0258] The ninth source connection electrode (CCE9) can be connected to the 12th sub-drain electrode (D182) of the 12th sub-transistor (T182) of the 18th transistor (T18) and the 20th drain electrode (D20) of the 20th transistor (T20) through the 26th contact hole (CT26). The ninth source connection electrode (CCE9) can be connected to the third connection electrode (CNE3) through the 29th contact hole (CT29).

[0259] The first connecting electrode (CNE1) can be extended in the second direction (DR2). The first connecting electrode (CNE1) can be connected to the seventh source connecting electrode (CCE7) through the 20th contact hole (CT20) and to the third source connecting electrode (CCE3) through the 27th contact hole (CT27).

[0260] The second connecting electrode (CNE2) can be connected to the eighth source connecting electrode (CCE8) through the 28th contact hole (CT28) and to the fourth connecting electrode (CNE4) through the 30th contact hole (CT30).

[0261] The third connecting electrode (CNE3) can be connected to the ninth source connecting electrode (CCE9) through the 29th contact hole (CT29) and to the fifth connecting electrode (CNE5) through the 31st contact hole (CT31).

[0262] The fourth connecting electrode (CNE4) can be connected to the second connecting electrode (CNE2) through the 30th contact hole (CT30) and to the first anode pad electrode (APD1) through the 32nd contact hole (CT32).

[0263] The fifth connecting electrode (CNE5) can be connected to the third connecting electrode (CNE3) through the third contact hole (CT31) and to the second anode pad electrode (APD2) through the third contact hole (CT33).

[0264] The first anode pad electrode (APD1), the second anode pad electrode (APD2), and the cathode pad electrode (CPD) may be extended in a second direction (DR2). The length of the first anode pad electrode (APD1) in the second direction (DR2) may be smaller than the length of the cathode pad electrode (CPD) in the second direction (DR2). The length of the second anode pad electrode (APD2) in the second direction (DR2) may be smaller than the length of the cathode pad electrode (CPD) in the second direction (DR2). The area of ​​the cathode pad electrode (CPD) may be larger than the area of ​​the first anode pad electrode (APD1) or the area of ​​the second anode pad electrode (APD2).

[0265] The first anode pad electrode (APD1) and the second anode pad electrode (APD2) can be positioned in the second direction (DR2). The first anode pad electrode (APD1) and the cathode pad electrode (CPD) can be positioned in the first direction (DR1). The second anode pad electrode (APD2) and the cathode pad electrode (CPD) can be positioned in the second direction (DR1). The first anode pad electrode (APD1) and the second anode pad electrode (APD2) can be positioned on one side of the cathode pad electrode (CPD), for example, on the left side.

[0266] Some regions of the first anode pad electrode (APD1) and the cathode pad electrode (CPD) overlap in the first direction (DR1), and another region of the second anode pad electrode (APD2) and the cathode pad electrode (CPD) may overlap in the first direction (DR1).

[0267] The first anode pad electrode (APD1) can be connected to the fourth connecting electrode (CNE4) through the 32nd contact hole (CT32). The second anode pad electrode (APD2) can be connected to the fifth connecting electrode (CNE5) through the 33rd contact hole (CT33).

[0268] The second power connection electrode (VDCE) can be extended in the second direction (DR2). The second power connection electrode (VDCE) can be connected to the fifth source connection electrode (CCE5) through the fourth power contact hole (VCT4).

[0269] A first sub-luminescent element (REL1) may be placed on a first anode pad electrode (APD1) and a cathode pad electrode (CPD). A first electrode of the first sub-luminescent element (REL1) may be connected to the first anode pad electrode (APD1), and a second electrode may be connected to the cathode pad electrode (CPD). A second sub-luminescent element (REL2) may be placed on a second anode pad electrode (APD2) and a cathode pad electrode (CPD). A first electrode of the second sub-luminescent element (REL2) may be connected to the second anode pad electrode (APD2), and a second electrode may be connected to the cathode pad electrode (CPD).

[0270] delete

[0271] Secondly, with reference to FIGS. 19, FIGS. 20, and FIGS. 24 through 26, the layout of the second subpixel (GP) will be described in detail.

[0272] Referring to FIGS. 19, 20, and FIGS. 24 to 26, the second subpixel (GP) includes first to eighth transistors (T1 to T18), first to sixth capacitor electrodes (CE1 to CE6), first to sixth gate connection electrodes (GCE1 to GCE6), first and second data connection electrodes (DCE1, DCE2), first to seventh source connection electrodes (CCE1 to CCE7), first and second connection electrodes (CNE1, CNE2), an anode pad electrode (APD), a cathode pad electrode (CPD), and a second light-emitting element (GEL).

[0273] In the embodiments of the second subpixel (GP) of FIGS. 19, 20, and FIGS. 24 to 26, descriptions that overlap with the embodiments of the first subpixel (RP) associated with FIGS. 19 to 23 are omitted, and the differences are explained in detail.

[0274] Referring to FIGS. 19, 20, and FIGS. 24 through 26, the 18th transistor (T18) includes an 18th channel (CH18), an 18th gate electrode (G18), an 18th source electrode (S18), and an 18th drain electrode (D18). The 18th channel (CH18) may overlap with the 18th gate electrode (G18) in a third direction (DR3). The 18th gate electrode (G18) may be formed integrally with the third gate connection electrode (GCE3). The 18th source electrode (S18) may be disposed on one side of the 18th channel (CH18), and the 18th drain electrode (D18) may be disposed on the other side of the 18th channel (CH18). The 18th source electrode (S18) may be connected to an initialization voltage wiring (VIL) through a 9th contact hole (CT9). The 18th drain electrode (D18) can be connected to the 7th source connection electrode (CCE7) through the 16th contact holes (CT16). The 18th source electrode (S18) and the 18th drain electrode (D18) may not overlap with the 18th gate electrode (G18) in the 3rd direction (DR3).

[0275] The second connecting electrode (CNE2') can be connected to the third source connecting electrode (CCE3) through the 28th contact hole (CT28'). The anode pad electrode (APD) can be placed on the other side of the cathode pad electrode (CPD), for example, to the right. The anode pad electrode (APD) can be connected to the second connecting electrode (CNE2') through the 29th contact hole (CT29'). The area of ​​the cathode pad electrode (CPD) of the second subpixel (GP) may be smaller than the area of ​​the cathode pad electrode (CPD) of the first subpixel (RP). For example, referring to FIG. 23 and FIG. 26, the length of the cathode pad electrode (CPD) of the second subpixel (GP) in the second direction (DR2) may be smaller than the length of the cathode pad electrode (CPD) of the first subpixel (RP) in the second direction (DR2).

[0276] The second light-emitting element (GEL) can be placed on the anode pad electrode (APD) and the cathode pad electrode (CPD). The first electrode of the second light-emitting element (GEL) can be connected to the anode pad electrode (APD), and the second electrode can be connected to the cathode pad electrode (CPD).

[0277] Meanwhile, since the layout of the third subpixel (BP) is substantially identical to the layout of the second subpixel (GP), a description thereof is omitted.

[0278] FIG. 27 is a cross-sectional view showing an example of a display panel cut along A-A' of FIG. 21. FIG. 28 is a cross-sectional view showing an example of a display panel cut along B-B' of FIG. 21 and FIG. 24.

[0279] Referring to FIGS. 27 and 28, a buffer film (BF) may be disposed on a substrate (SUB). The substrate (SUB) may be made of an insulating material such as glass or a polymer resin. For example, if the substrate (SUB) is made of a polymer resin, it may include polyimide. The substrate (SUB) may be a flexible substrate capable of bending, folding, rolling, etc.

[0280] The buffer film (BF) may be composed of a plurality of inorganic films that are alternately stacked. For example, the buffer film (BF) may be formed as a multilayer in which one or more inorganic films selected from a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, and an aluminum oxide layer are alternately stacked. The buffer film (BF) may be omitted.

[0281] An active layer may be disposed on the buffer film (BF). The active layer includes channels, source electrodes, and drain electrodes of the first to twentieth transistors (T1 to T20). The active layer may include polycrystalline silicon, single-crystal silicon, low-temperature polycrystalline silicon, amorphous silicon, or an oxide semiconductor.

[0282] The channels of the first to twentieth transistors (T1 to T20) may each overlap with the gate electrodes in the third direction (DR3). The source electrodes and drain electrodes of the first to twentieth transistors (T1 to T20) may not overlap with the gate electrodes in the third direction (DR3). The source electrodes and drain electrodes of the first to twentieth transistors (T1 to T20) may be regions that have conductivity by doping ions or impurities into a silicon semiconductor or an oxide semiconductor.

[0283] A gate insulating film (130) may be disposed on the active layer. The gate insulating film (130) may be formed of an inorganic film, for example, a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer.

[0284] A first gate metal layer may be disposed on the gate insulating film (130). The first gate metal layer includes gate electrodes of the first to 20 transistors (T1 to T20), a first capacitor electrode (CE1), a third capacitor electrode (CE3), a fifth capacitor electrode (CE5), and first to sixth gate connecting electrodes (GCE1 to GCE6). The gate electrodes of the first to 20 transistors (T1 to T20), the first capacitor electrode (CE1), the third capacitor electrode (CE3), the fifth capacitor electrode (CE5), and the first to sixth gate connecting electrodes (GCE1 to GCE6) may be formed as a single layer or a multilayer made of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof.

[0285] A first interlayer insulating film (141) may be disposed on the first gate metal layer. The first interlayer insulating film (141) may be formed of an inorganic film, for example, a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer.

[0286] A second gate metal layer may be disposed on the first interlayer insulating film (141). The second gate metal layer may include a second capacitor electrode (CE2), a fourth capacitor electrode (CE4), and a sixth capacitor electrode (CE6). The second gate metal layer may be formed as a single layer or a multilayer composed of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof.

[0287] The second capacitor electrode (CE2) may overlap with the first capacitor electrode (CE1) in the third direction (DR3), the fourth capacitor electrode (CE4) may overlap with the third capacitor electrode (CE3) in the third direction (DR3), and the sixth capacitor electrode (CE6) may overlap with the fifth capacitor electrode (CE5) in the third direction (DR3). Since the first interlayer insulating film (141) has a predetermined dielectric constant, the first capacitor (PC1) can be formed by the first capacitor electrode (CE1), the second capacitor electrode (CE2), and the first interlayer insulating film (141) disposed between them. Additionally, the second capacitor (PC2) can be formed by the third capacitor electrode (CE3), the fourth capacitor electrode (CE4), and the first interlayer insulating film (141) disposed between them. A third capacitor (PC3) can be formed by a fifth capacitor electrode (CE5), a sixth capacitor electrode (CE6), and a first interlayer insulating film (141) disposed between them.

[0288] A second interlayer insulating film (142) may be disposed on the second gate metal layer. The second interlayer insulating film (142) may be formed of an inorganic film, for example, a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer.

[0289] A first source metal layer may be disposed on the second interlayer insulating film (142). The first source metal layer may include initialization voltage lines (VIL), k-th scan initialization lines (GILk), k-th scan write lines (GWLk), k-th PWM light emission lines (PWELk), a first horizontal power line (HVDL), a gate off voltage line (VGHL), a k-th sweep signal line (SWPLk), a k-th scan control line (GCLk), a k-th PAM light emission line (PAELk), a first light emission control line (RCL1), a second light emission control line (RCL2), and a third power line (VSL). Additionally, the first source metal layer may include first and second data connection electrodes (DCE1, DCE2) and first to ninth source connection electrodes (CCE1 to CCE9). The first source metal layer may be formed as a single layer or multiple layers composed of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof.

[0290] The k-th scan writing wiring (GWLk) can be connected to the first gate connection electrode (GCE1) through the first gate contact hole (GCT1) and the third gate contact hole (GCT3) penetrating the first interlayer insulating film (141) and the second interlayer insulating film (142). The k-th scan initialization wiring (GILk) can be connected to the second gate connection electrode (GCE2) through the second gate contact hole (GCT2) penetrating the first interlayer insulating film (141) and the second interlayer insulating film (142). The k-th scan control wiring (GCLk) can be connected to the third gate connection electrode (GCE3) through the eighth contact hole (CT8) penetrating the first interlayer insulating film (141) and the second interlayer insulating film (142). The k-th PAM light-emitting wiring (PAELk) can be connected to the fifth gate connection electrode (GCE5) through a 19th contact hole (CT19) penetrating the first interlayer insulating film (141) and the second interlayer insulating film (142). The k-th PWM light-emitting wiring (PWELk) can be connected to the sixth gate connection electrode (GCE6) through a 14th contact hole (CT14) penetrating the first interlayer insulating film (141) and the second interlayer insulating film (142).

[0291] The initial voltage wiring (VIL) can be connected to the second sub-drain electrode (D32) and the sixth sub-drain electrode (D102) through a first power contact hole (VCT1) penetrating the gate insulating film (130), the first interlayer insulating film (141), and the second interlayer insulating film (142). The initial voltage wiring (VIL) can be connected to the tenth sub-drain electrode (D162) and the eighteenth drain electrode (D18) through a ninth contact hole (CT9) penetrating the gate insulating film (130), the first interlayer insulating film (141), and the second interlayer insulating film (142). The initial voltage wiring (VIL) can be connected to the sixth capacitor electrode (CE6) through an eighteenth contact hole (CT18) penetrating the second interlayer insulating film (142). The first horizontal power wiring (HVDL) can be connected to the fifth source electrode (S5) and the thirteenth source electrode (S13) through a second power contact hole (VCT2) penetrating the gate insulating film (130), the first interlayer insulating film (141), and the second interlayer insulating film (142). The gate off voltage wiring (VGHL) can be connected to the seventh source electrode (S7) through a seventh contact hole (CT7) penetrating the gate insulating film (130), the first interlayer insulating film (141), and the second interlayer insulating film (142). The test signal wiring can be connected to the ninth gate electrode (G19) through a thirteenth contact hole (CT23) penetrating the first interlayer insulating film (141) and the second interlayer insulating film (142). The third power line (VSL) can be connected to the 19th drain electrode (D19) through a 24th contact hole (CT24) that penetrates the gate insulating film (130), the first interlayer insulating film (141), and the second interlayer insulating film (142).

[0292] The first data connection electrode (DCE1) can be connected to the second source electrode (S2) through a first data contact hole (DCT1) penetrating the gate insulating film (130), the first interlayer insulating film (141), and the second interlayer insulating film (142). The second data connection electrode (DCE2) can be connected to the ninth source electrode (S9) through a third data contact hole (DCT3) penetrating the gate insulating film (130), the first interlayer insulating film (141), and the second interlayer insulating film (142).

[0293] The first source connection electrode (CCE1) is connected to the first gate electrode (G1) through a first contact hole (CT1) penetrating the first interlayer insulating film (141) and the second interlayer insulating film (142), and can be connected to the first sub-source electrode (S31) and the fourth sub-drain electrode (D42) through a second contact hole (CT2) penetrating the gate insulating film (130), the first interlayer insulating film (141), and the second interlayer insulating film (142).

[0294] The second source connection electrode (CCE2) can be connected to the 17th drain electrode (D17) through a third contact hole (CT3) penetrating the gate insulating film (130), the first interlayer insulating film (141), and the second interlayer insulating film (142), connected to the 14th drain electrode (D14) through a fourth contact hole (CT4) penetrating the gate insulating film (130), the first interlayer insulating film (141), and the second interlayer insulating film (142), and connected to the 4th capacitor electrode (CE4) through a 15th contact hole (CT15) penetrating the second interlayer insulating film (142).

[0295] The third source connection electrode (CCE3) can be connected to the 19th source electrode (S19) through a 21st contact hole (CT21) that penetrates the gate insulating film (130), the first interlayer insulating film (141), and the second interlayer insulating film (142).

[0296] The fourth source connection electrode (CCE4) is connected to the sixth drain electrode (D6) through a tenth contact hole (CT10) penetrating the gate insulating film (130), the first interlayer insulating film (141), and the second interlayer insulating film (142), and can be connected to the fourth gate connection electrode (GCE4) through a seventeenth contact hole (CT17) penetrating the first interlayer insulating film (141) and the second interlayer insulating film (142).

[0297] The fifth source connection electrode (CCE5) can be connected to the 12th source electrode (S12) and the 14th source electrode (S14) through 11 contact holes (CT11) penetrating the gate insulating film (130), the first interlayer insulating film (141), and the second interlayer insulating film (142).

[0298] The sixth source connection electrode (CCE6) is connected to the eighth gate electrode (G8) through a twelfth contact hole (CT12) penetrating the first interlayer insulating film (141) and the second interlayer insulating film (142), and can be connected to the fifth sub-source electrode (S101) and the eighth sub-drain electrode (D112) through a thirteenth contact hole (CT13) penetrating the gate insulating film (130), the first interlayer insulating film (141), and the second interlayer insulating film (142).

[0299] The 7th source connection electrode (CCE7) can be connected to the 17th drain electrode (D17) and the 18th drain electrode (D18) through 16 contact holes (CT16) penetrating the gate insulating film (130), the 1st interlayer insulating film (141), and the 2nd interlayer insulating film (142).

[0300] The 8th source connection electrode (CCE8) can be connected to the 11th sub-drain electrode (D181) and the 19th drain electrode (D19) through a 25th contact hole (CT25) that penetrates the gate insulating film (130), the 1st interlayer insulating film (141), and the 2nd interlayer insulating film (142).

[0301] The ninth source connection electrode (CCE9) can be connected to the 12th sub-drain electrode (D182) and the 20th drain electrode (D20) through a 26th contact hole (CT26) that penetrates the gate insulating film (130), the first interlayer insulating film (141), and the second interlayer insulating film (142).

[0302] A first planarization film (160) may be disposed on the first source metal layer. The first planarization film (160) may be formed from an organic film such as an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, or a polyimide resin.

[0303] A first inorganic insulating film (161) may be disposed on the first planarization film (160). The first inorganic insulating film (161) may be formed of an inorganic film, for example, a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer.

[0304] A second source metal layer may be disposed on the first inorganic insulating film (161). The second source metal layer may include a j-th PWM data line (DLj), a first vertical power line (VVDL), and a first PAM data line (RDL). Additionally, the second source metal layer may include first to third connection electrodes (CNE1, CNE2, CNE3) and a second power connection electrode (VDCE). The second source metal layer may be formed as a single layer or a multilayer composed of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof.

[0305] The j-th PWM data wiring (DLj) can be connected to the first data connection electrode (DCE1) through a second data contact hole (DCT2) penetrating the first flattening film (160) and the first inorganic insulating film (161). The first PAM data wiring (RDL) can be connected to the second data connection electrode (DCE2) through a fourth data contact hole (DCT4) penetrating the first flattening film (160) and the first inorganic insulating film (161). The first vertical power wiring (VVDL) can be connected to the first horizontal power wiring (HVDL) through a third power contact hole (VCT3) penetrating the first flattening film (160) and the first inorganic insulating film (161). The third power contact hole (VCT3) can overlap with the second power contact hole (VCT2) in the third direction (DR3). The area of ​​the third power contact hole (VCT3) may be larger than the area of ​​the second power contact hole (VCT2).

[0306] The first connecting electrode (CNE1) can be connected to the seventh source connecting electrode (CCE7) through a 20th contact hole (CT20) penetrating the first flattening film (160) and the first inorganic insulating film (161), and can be connected to the third source connecting electrode (CCE3) through a 27th contact hole (CT27) penetrating the first flattening film (160) and the first inorganic insulating film (161).

[0307] The second connecting electrode (CNE2) can be connected to the 11th sub-drain electrode (D181) and the 19th drain electrode (D19) through a 25th contact hole (CT25) that penetrates the first flattening film (160) and the first inorganic insulating film (161).

[0308] The third connecting electrode (CNE3) can be connected to the 12th sub-drain electrode (D182) and the 20th drain electrode (D20) through the 26th contact hole (CT26) penetrating the first flattening film (160) and the first inorganic insulating film (161).

[0309] The second power connection electrode (VDCE) can be connected to the fifth source connection electrode (CCE5) through a fourth power contact hole (VCT4) that penetrates the first flattening film (160) and the first inorganic insulating film (161).

[0310] A second planarization film (180) may be disposed on the second source metal layer. The second planarization film (180) may be formed from an organic film such as an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, or a polyimide resin.

[0311] A second inorganic insulating film (181) may be disposed on the second planarization film (180). The second inorganic insulating film (181) may be formed of an inorganic film, for example, a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer.

[0312] A third source metal layer may be disposed on the second inorganic insulating film (181). The third source metal layer may include a first sub-power wiring (VDL21), a fourth connecting electrode (CNE4), and a fifth connecting electrode (CNE5). The third source metal layer may be formed as a single layer or a multilayer composed of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof.

[0313] The first sub-power wiring (VDL21) can be connected to the second power connection electrode (VDCE) through a fifth power contact hole penetrating the second flattening film (180) and the second inorganic insulating film (181). The fourth connection electrode (CNE4) can be connected to the second connection electrode (CNE2) through a 28th contact hole (CT28) penetrating the second flattening film (180) and the second inorganic insulating film (181). The fifth connection electrode (CNE5) can be connected to the third connection electrode (CNE3) through a 29th contact hole (CT29) penetrating the second flattening film (180) and the second inorganic insulating film (181).

[0314] A third planarization film (190) may be disposed on the third source metal layer. The third planarization film (190) may be formed from an organic film such as an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, or a polyimide resin. The third planarization film (190) may be referred to as a fifth insulating film.

[0315] A third inorganic insulating film (191) may be disposed on the third planarization film (190). The third inorganic insulating film (191) may be formed of an inorganic film, for example, a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer. The second interlayer insulating film (141) may be referred to as the third insulating film.

[0316] A fourth source metal layer may be disposed on the third inorganic insulating film (191). The fourth source metal layer may include a first anode pad electrode (APD1), a second anode pad electrode (APD2), and a cathode pad electrode (CPD). The first anode pad electrode (APD1), the second anode pad electrode (APD2), and the cathode pad electrode (CPD) may be formed as a single layer or a multilayer composed of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof.

[0317] The first anode pad electrode (APD1) can be connected to the fourth connecting electrode (CNE4) through a 32nd contact hole (CT32) that penetrates the third flattening film (190) and the third inorganic insulating film (191). The second anode pad electrode (APD2) can be connected to the fifth connecting electrode (CNE5) through a 33rd contact hole (CT33) that penetrates the third flattening film (190) and the third inorganic insulating film (191).

[0318] Although not shown, the cathode pad electrode (CPD) can be connected to the cathode wiring of the fourth source metal layer. Since the third power supply voltage (VSS) is applied to the cathode wiring, the third power supply voltage (VSS) can be applied to the cathode pad electrode (CPD).

[0319] A transparent metal layer may be disposed on the fourth source metal layer. The transparent metal layer may include pad electrodes. The pad electrodes may be disposed on the first anode pad electrode (APD1), the second anode pad electrode (APD2), and the cathode pad electrode (CPD), respectively. The transparent metal layer may be formed of a transparent conductive material (TCO) such as indium tin oxide (ITO) or indium zinc oxide (IZO) that can transmit light.

[0320] FIG. 28 illustrates that each of the light-emitting elements (REL1, REL2, GEL, BEL) is a flip-chip type micro-LED in which the first contact electrode (CTE1) faces the anode pad electrode (APD1 / APD2 / APD) and the second contact electrode (CTE2) faces the cathode pad electrode (CPD). Each of the light-emitting elements (REL1, REL2, GEL, BEL) may be formed from an inorganic material such as GaN. The first sub-light-emitting element (REL1) may have a length in the first direction (DR1), a length in the second direction (DR2), and a length in the third direction (DR3), each of which may be several to several hundred μm. For example, each of the light-emitting elements (REL1, REL2, GEL, BEL) may have a length in the first direction (DR1), a length in the second direction (DR2), and a length in the third direction (DR3), each of which may be approximately 100 μm or less.

[0321] Each of the light-emitting elements (REL1, REL2, GEL, BEL) can be formed by growing on a semiconductor substrate such as a silicon wafer. Each of the light-emitting elements (REL1, REL2, GEL, BEL) can be transferred directly from the silicon wafer onto the anode pad electrodes (APD1 / APD2 / APD) and cathode pad electrodes (CPD) of the substrate (SUB). Alternatively, each of the light-emitting elements (REL1, REL2, GEL, BEL) can be transferred onto the anode pad electrodes (APD1 / APD2 / APD) and cathode pad electrodes (CPD) of the substrate (SUB) via an electrostatic method using an electrostatic head or a stamping method using an elastic polymer material such as PDMS (polydimethylsiloxane) or silicon as a transfer substrate.

[0322] Each of the light-emitting elements (REL1, REL2, GEL, BEL) may be a light-emitting structure comprising a base substrate (SSUB), an n-type semiconductor (NSEM), an active layer (MQW), a p-type semiconductor (PSEM), a first contact electrode (CTE1), and a second contact electrode (CTE2).

[0323] The base substrate (SPUB) may be a sapphire substrate, but the embodiments of this specification are not limited thereto.

[0324] The n-type semiconductor (NSEM) can be placed on one side of the base substrate (SPUB). For example, the n-type semiconductor (NSEM) can be placed on the lower side of the base substrate (SPUB). The n-type semiconductor (NSEM) can be made of GaN doped with n-type conductive dopants such as Si, Ge, Se, Sn, etc.

[0325] The active layer (MQW) may be disposed on a portion of one surface of an n-type semiconductor (NSEM). The active layer (MQW) may include a material having a single or multiple quantum well structure. When the active layer (MQW) includes a material having a multiple quantum well structure, it may have a structure in which multiple well layers and barrier layers are alternately stacked. In this case, the well layers may be formed of InGaN, and the barrier layers may be formed of GaN or AlGaN, but are not limited thereto. Alternatively, the active layer (MQW) may have a structure in which semiconductor materials with large band gap energy and semiconductor materials with small band gap energy are alternately stacked, or it may include different Group 3 to Group 5 semiconductor materials depending on the wavelength of the emitted light.

[0326] A p-type semiconductor (PSEM) can be disposed on one side of an active layer (MQW). The p-type semiconductor (PSEM) can be made of GaN doped with p-type conductive dopants such as Mg, Zn, Ca, Ba, etc.

[0327] A first contact electrode (CTE1) is disposed on a p-type semiconductor (PSEM), and a second contact electrode (CTE2) may be disposed on another part of one side of an n-type semiconductor (NSEM). The other part of the side of the n-type semiconductor (NSEM) on which the second contact electrode (CTE2) is disposed may be disposed apart from the part of the side of the n-type semiconductor (NSEM) on which the active layer (MQW) is disposed.

[0328] The first contact electrode (CTE1) and the anode pad electrodes (APD1 / APD2 / APD) can be bonded to each other through a conductive adhesive member such as an anisotropic conductive film (ACF) or anisotropic conductive paste (ACP). Alternatively, the first contact electrode (CTE1) and the anode pad electrodes (APD1 / APD2 / APD) can be bonded to each other through a soldering process.

[0329] The second contact electrode (CTE2) and the cathode pad electrode (CPD) can be bonded to each other through a conductive adhesive member such as an anisotropic conductive film (ACF) or anisotropic conductive paste (ACP). Alternatively, the second contact electrode (CTE2) and the cathode pad electrode (CPD) can be bonded to each other through a soldering process.

[0330] As described above, the first sub-pixel (RP) can reduce the light emission period (SET) of the first sub-light emission element (REL1) and the light emission period (SET) of the second sub-light emission element (REL2) by connecting two light-emitting elements, namely the first sub-light emission element (REL1) and the second sub-light emission element (REL2), to a single pixel circuit. As a result, the amount of heat generated by the first sub-light emission element (REL1) and the second sub-light emission element (REL2) can be reduced, thereby lowering the temperature of the first sub-light emission element (REL1) and the second sub-light emission element (REL2). Therefore, it is possible to reduce or prevent the decrease in the light emission brightness of the first sub-light emission element (REL1) and the second sub-light emission element (REL2) caused by the heat generated by the first sub-light emission element (REL1) and the second sub-light emission element (REL2).

[0331] FIG. 29 is a circuit diagram showing a first subpixel according to one embodiment.

[0332] The embodiment of FIG. 29 differs from the embodiment of FIG. 6 in that the 17th transistor (T17) of the 1st subpixel (RP) includes the 13th subpixel (T171) and the 14th subpixel (T172), and the 19th transistor (T19) and the 20th transistor (T20) are omitted. In FIG. 30, descriptions that overlap with the embodiment of FIG. 6 are omitted.

[0333] Referring to FIG. 29, the 17th transistor (T17) may include a 13th sub-transistor (T171) and a 14th sub-transistor (T172).

[0334] The 13th sub-transistor (T171) is turned on by the k-th PAMA light emission signal of the k-th PAMA light emission wiring (PAALk) to connect the second electrode of the 15th transistor (T15) to the first electrode of the first sub-light emission element (REL1). The gate electrode of the 13th sub-transistor (T171) is connected to the k-th PAMA light emission wiring (PAALk), the first electrode is connected to the second electrode of the 15th transistor (T15), and the second electrode can be connected to the first electrode of the first sub-light emission element (REL1).

[0335] The 14th sub-transistor (T172) is turned on by the k-th PAMB light emission signal of the k-th PAMB light emission wiring (PABLk) to connect the second electrode of the 15th transistor (T15) to the first electrode of the second sub-light emission element (REL2). The gate electrode of the 14th sub-transistor (T172) is connected to the k-th PAMB light emission wiring (PABLk), the first electrode is connected to the second electrode of the 15th transistor (T15), and the second electrode can be connected to the first electrode of the second sub-light emission element (REL2).

[0336] FIG. 30 is a circuit diagram showing a second subpixel according to one embodiment. The embodiment of FIG. 30 differs from the embodiment of FIG. 29 in that the second subpixel (GP) includes one second light-emitting element (GEL). In FIG. 30, descriptions that overlap with the embodiment of FIG. 29 are omitted.

[0337] Referring to FIG. 30, the second light-emitting element (GEL) emits a second light according to the driving current (Ids) generated by the second pixel driver (PDU2). The second light-emitting element (GEL) may be positioned between the 13th sub-transistor (T171) of the 17th transistor (T17) and the third power line (VSL), and between the 14th sub-transistor (T172) of the 17th transistor (T17) and the third power line (VSL). The first electrode of the second light-emitting element (GEL) is connected to the second electrode of the 13th sub-transistor (T171) of the 17th transistor (T17) and the second electrode of the 14th sub-transistor (T172), and the second electrode may be connected to the third power line (VSL).

[0338] The 18th transistor (T18) is turned on by the k-th scan control signal of the k-th scan control wiring (GCLk) to connect the initialization voltage wiring (VIL) to the first electrode of the second light-emitting element (EL2). As a result, during the period when the 18th transistor (T18) is turned on, the first electrode of the second light-emitting element (EL2) can be discharged to the initialization voltage (VINT) of the initialization voltage wiring (VIL). The gate electrode of the 18th sub-transistor (T18) is connected to the k-th scan control wiring (GCLk), the first electrode is connected to the first electrode of the second light-emitting element (EL2), and the second electrode can be connected to the initialization voltage wiring (VIL).

[0339] FIG. 31 is a circuit diagram showing a third subpixel according to one embodiment.

[0340] The embodiment of FIG. 31 differs from the embodiment of FIG. 29 in that the third subpixel (BP) includes a third light-emitting element (BEL). In FIG. 31, descriptions that overlap with the embodiment of FIG. 29 are omitted.

[0341] Referring to FIG. 31, the third light-emitting element (BEL) emits a third light according to the driving current (Ids) generated by the third pixel driver (PDU3). The third light-emitting element (BEL) may be positioned between the 13th sub-transistor (T171) of the 17th transistor (T17) and the third power line (VSL), and between the 14th sub-transistor (T172) of the 17th transistor (T17) and the third power line (VSL). The first electrode of the third light-emitting element (BEL) is connected to the second electrode of the 13th sub-transistor (T171) of the 17th transistor (T17) and the second electrode of the 14th sub-transistor (T172), and the second electrode may be connected to the third power line (VSL).

[0342] The 18th transistor (T18) is substantially the same as described in conjunction with FIG. 30, except that it is connected to the 3rd light-emitting element (BEL) instead of the 2nd light-emitting element (GEL), so a description of these is omitted.

[0343] FIG. 32 is a waveform diagram showing the period during which a k-th scan initialization signal, a k-th scan write signal, a k-th scan control signal, a k-th PWM light emission signal, a k-th PAMA light emission signal, a k-th PAMB light emission signal, and a k-th sweep signal are applied to a first subpixel placed on a k-th row line during an N-frame period according to one embodiment, and a driving current applied to a third node and a light-emitting element.

[0344] The embodiment of FIG. 32 differs from the embodiment of FIG. 11 in that the k-th PAM emission signal (PAEMk) is deleted and the k-th PAMA emission signal (PAAMk) and the k-th PAMB emission signal (PAMBk) are added.

[0345] Referring to FIG. 32, the k-th PAMA light-emitting signal (PAAMk) indicates a signal applied to the k-th PAMA light-emitting wiring (PAALk), and the k-th PAMB light-emitting signal (PAMBk) indicates a signal applied to the k-th PAMB light-emitting wiring (PABLk).

[0346] The k-th PAMA light emission signal (PAAMk) is a signal for controlling the turn-on and turn-off of the 13th sub-transistor (T171) of the 17th transistor (T17). The k-th PAMB light emission signal (PAMBk) is a signal for controlling the turn-on and turn-off of the 14th sub-transistor (T172) of the 17th transistor (T17). The k-th PAMA light emission signal (PAAMk) and the k-th PAMA light emission signal (PAAMk) can occur with a period of one frame.

[0347] The k-th PAMA light emission signal (PAAMk) may have a gate-on voltage (VGL) during odd-numbered light emission periods (EP1, EP3, ?, EPn-1) among a plurality of light emission periods (EP1~EPn) of one frame period, and may have a gate-off voltage (VGH) during the remaining periods. The k-th PAMA light emission signal (PAAMk) may include PAM pulses that occur at the gate-on voltage (VGL) during the 6th period (t6) or the 9th period (t9) of each of the odd-numbered light emission periods (EP1, EP3, ?, EPn-1).

[0348] The k-th PAMB light emission signal (PAMBk) may have a gate-on voltage (VGL) during the superior light emission periods (EP2, EP4, ⪋, EPn) among the plurality of light emission periods (EP1~EPn) of a frame period, and may have a gate-off voltage (VGH) during the remaining periods. The k-th PAMB light emission signal (PAMBk) may include PAM pulses that occur at the gate-on voltage (VGL) during the 6th period (t6) or the 9th period (t9) of each of the superior light emission periods (EP2, EP4, ⪋, EPn).

[0349] Referring to FIGS. 29 and 32, the 13th sub-transistor (T171) and the 14th transistor (T172) can be turned on during different light emission periods among a plurality of light emission periods (EP1 to EPn) of one frame period. Therefore, the first sub-light emitting element (REL1) can be supplied with a driving current (Ids) through the 13th sub-transistor (T171) during odd light emission periods (EP1, EP3, EPn-1) among a plurality of light emission periods (EP1 to EPn) of one frame period, and the second sub-light emitting element (REL2) can be supplied with a driving current (Ids) through the 14th sub-transistor (T172) during even light emission periods (EP2, EP4, EPn).

[0350] Additionally, referring to FIGS. 30 to 32, each of the second light-emitting element (GEL) and the third light-emitting element (BEL) can receive a driving current (Ids) through the 13th sub-transistor (T171) during odd-numbered light-emitting periods (EP1, EP3, EPn-1) among multiple light-emitting periods (EP1 to EPn) of one frame period, and receive a driving current (Ids) through the 14th sub-transistor (T172) during even-numbered light-emitting periods (EP2, EP4, EPn). Therefore, each of the second light-emitting element (GEL) and the third light-emitting element (BEL) can emit light throughout multiple light-emitting periods (EP1 to EPn) of one frame period.

[0351] As shown in FIGS. 29 to 32, that is, the first sub-emissive element (REL1) and the second sub-emissive element (REL2) of the first sub-pixel (RP) emit light during different periods. Therefore, the light emission period of the first sub-emissive element (REL1) and the light emission period of the second sub-emissive element (REL2) can be reduced to half compared to the light emission period of the second light emission element (GEL) and the light emission period of the third light emission element (BEL), respectively. As a result, the amount of heat generated by the first sub-emissive element (REL1) and the second sub-emissive element (REL2) can be reduced, and thus the temperature of the first sub-emissive element (REL1) and the second sub-emissive element (REL2) can be lowered. Accordingly, the decrease in the luminous brightness of the first sub-emissive element (REL1) and the second sub-emissive element (REL2) due to the heat generated by the first sub-emissive element (REL1) and the second sub-emissive element (REL2) can be reduced or prevented.

[0352] FIG. 33 is an exemplary drawing showing a PAMA light emission signal output unit and a PAMB light emission signal output unit according to one embodiment.

[0353] In FIG. 33, for convenience of explanation, the k-th to k+6 PAMA stages (PASTk~PASTk+6) of the PAMA light emission signal output unit (1151) and the k-th to k+6 PAMB stages (PBSTk~PBSTk+6) of the PAMB light emission signal output unit (1152) are exemplified.

[0354] In the following description, "pre-stage" refers to a stage located before a reference stage. For example, the pre-stage of the k+1 stage refers to the 1st through kth stages, and the pre-stages of the k+2 stage refer to the 1st through k+1st stages.

[0355] Referring to FIG. 33, the light emission control signal driving unit (115) includes a PAMA light emission signal output unit (1151) and a PAMB light emission signal output unit (1152). Although the PAMA light emission signal output unit (1151) is exemplified as being positioned on one side of the display area (DA), for example, on the left, and the PAMB light emission signal output unit (1152) is exemplified as being positioned on the other side of the display area (DA), for example, on the right, the embodiments of the present specification are not limited thereto. For example, both the PAMA light emission signal output unit (1151) and the PAMB light emission signal output unit (1152) may be positioned on one side of the display area (DA) or on both sides of the display area (DA).

[0356] PAMA clock wirings (PACL1~PACL6) to which PAMA clock signals with sequentially delayed phases are applied may be arranged on one side, for example, the left side, of the k to k+6 PAMA stages (PASTk~PASTk+6). PAMB clock wirings (PBCL1~PBCL6) to which PAMB clock signals with sequentially delayed phases are applied may be arranged on one side, for example, the right side, of the k to k+6 PAMB stages (PBSTk~PBSTk+6).

[0357] In FIG. 33, six PAMA clock wires (PACL1~PACL6) and six PAMB clock wires (PBCL1~PBCL6) are exemplified, but the number of PAMA clock wires (PACL1~PACL6) and PBMA clock wires (PBCL1~PBCL6) is not limited thereto.

[0358] Each of the k to k+6 PAMA stages (PASTk to PASTk+6) can be connected to any one of the six PAMA clock wires (PACL1 to PACL6) and any one of the k to k+6 PAMA light-emitting wires (PAALk to PAALk+6). The k to k+6 PAMA stages (PASTk to PASTk+6) can be alternately connected to the six PAMA clock wires (PACL1 to PACL6). For example, the k-th PAMA stages (PASTk) may be connected to the first PAMA clock wire (PACL1), the k+1-th PAMA stages (PASTk+1) may be connected to the second PAMA clock wire (PACL2), the k+2-th PAMA stages (PASTk+2) may be connected to the third PAMA clock wire (PACL3), and the k+3-th PAMA stages (PASTk+3) may be connected to the fourth PAMA clock wire (PACL4). Additionally, the k+4-th PAMA stages (PASTk+4) may be connected to the fifth PAMA clock wire (PACL5), the k+5-th PAMA stages (PASTk+5) may be connected to the sixth PAMA clock wire (PACL6), and the k+7-th PAMA stages (PASTk+7) may be connected to the first PAMA clock wire (PACL1). Similarly, the k to k+6 PAMB stages (PBSTk to PBSTk+6) can be connected to any one of the six PAMB clock wires (PBCL1 to PBCL6) and any one of the k to k+6 PAMB light-emitting wires (PABLk to PABLk+6).

[0359] Figure 34 is a waveform diagram showing PAMA clock signals and PAMB clock signals.

[0360] Referring to FIG. 34, the first to sixth PAMA clock signals (PACK1 to PACK6) refer to signals applied to the first to sixth PAMA clock wires (PACL1 to PACL6), respectively. The first to sixth PAMB clock signals (PBCK1 to PBCK6) refer to signals imprinted on the first to sixth PAMB clock wires (PBCL1 to PBCL6), respectively.

[0361] The first to sixth PAMA clock signals (PACK1 to PACK6) and the first to sixth PAMB clock wires (PBCL1 to PBCL6) may be signals with sequentially delayed phases. For example, the second PAMA clock signal (PACK2) may be delayed in phase by one horizontal period compared to the first PAMA clock signal (PACK1), the third PAMA clock signal (PACK3) may be delayed in phase by one horizontal period compared to the second PAMA clock signal (PACK2), the fourth PAMA clock signal (PACK4) may be delayed in phase by one horizontal period compared to the third PAMA clock signal (PACK3), the fifth PAMA clock signal (PACK5) may be delayed in phase by one horizontal period compared to the fourth PAMA clock signal (PACK4), and the sixth PAMA clock signal (PACK6) may be delayed in phase by one horizontal period compared to the fifth PAMA clock signal (PACK5).

[0362] Additionally, the first PAMB clock signal (PBCK1) may be phase-delayed by one horizontal period compared to the sixth PAMB clock signal (PACK6), the second PAMB clock signal (PBCK2) may be phase-delayed by one horizontal period compared to the first PAMB clock signal (PBCK1), the third PAMB clock signal (PBCK3) may be phase-delayed by one horizontal period compared to the second PAMB clock signal (PBCK2), the fourth PAMB clock signal (PBCK4) may be phase-delayed by one horizontal period compared to the third PAMB clock signal (PBCK3), the fifth PAMB clock signal (PBCK5) may be phase-delayed by one horizontal period compared to the fourth PAMB clock signal (PBCK4), and the sixth PAMB clock signal (PBCK6) may be phase-delayed by one horizontal period compared to the fifth PAMB clock signal (PBCK5).

[0363] Referring to FIGS. 33 and 34, each of the k to k+6 PAMA stages (PASTk to PASTk+6) can output PAM pulses of a PAMA clock signal applied through a PAMA clock wiring connected thereto to a corresponding PAMA light-emitting wiring. For example, the k PAMA stage (PASTk) can output PAM pulses of the gate-on voltage (VGL) of the first PAMA clock signal (PACK1) of the first PAMA clock wiring (PACL1) to the k PAMA light-emitting wiring (PAALk). The k+1 PAMA stage (PASTk+1) can output PAM pulses of the gate-on voltage (VGL) of the second PAMA clock signal (PACK2) of the second PAMA clock wiring (PACL2) to the k+1 PAMA light-emitting wiring (PAALk+1). The k+2 PAMA stages (PASTk+2) can output PAM pulses of the gate-on voltage (VGL) of the third PAMA clock signal (PACK3) of the third PAMA clock wiring (PACL3) to the k+2 PAMA light-emitting wiring (PAALk+2). The k+3 PAMA stages (PASTk+3) can output PAM pulses of the gate-on voltage (VGL) of the fourth PAMA clock signal (PACK4) of the fourth PAMA clock wiring (PACL4) to the k+3 PAMA light-emitting wiring (PAALk+3). Similarly, each of the k to k+6 PAMB stages (PBSTk to PBSTk+6) can output PAM pulses of the PAMB clock signal applied through the PAMB clock wiring connected thereto to the corresponding PAMB light-emitting wiring.

[0364] Additionally, the k+4th PAMA stages (PASTk+4) can output PAM pulses of the gate-on voltage (VGL) of the 5th PAMA clock signal (PACK4) of the 5th PAMA clock wiring (PACL5) to the k+4th PAMA light-emitting wiring (PAALk+4). The k+5th PAMA stages (PASTk+5) can output PAM pulses of the gate-on voltage (VGL) of the 6th PAMA clock signal (PACK6) of the 6th PAMA clock wiring (PACL6) to the k+5th PAMA light-emitting wiring (PAALk+5). The k+6th PAMA stages (PASTk+6) can output PAM pulses of the gate-on voltage (VGL) of the 1st PAMA clock signal (PACK1) of the 1st PAMA clock wiring (PACL1) to the k+6th PAMA light-emitting wiring (PAALk+6).

[0365] FIG. 35 is a perspective view showing a tile-type display device including a plurality of display devices according to one embodiment.

[0366] Referring to FIG. 35, the tile-type display device (TD) may include a plurality of display devices (11, 12, 13, 14) and a joint (SM). For example, the tile-type display device (TD) may include a first display device (11), a second display device (12), a third display device (13), and a fourth display device (14).

[0367] Multiple display devices (11, 12, 13, 14) may be arranged in a grid form. Multiple display devices (11, 12, 13, 14) may be arranged in a matrix form with M (M is a positive integer) rows and N (N is a positive integer) columns. For example, the first display device (11) and the second display device (12) may be adjacent to each other in the first direction (DR1). The first display device (11) and the third display device (13) may be adjacent to each other in the second direction (DR2). The third display device (13) and the fourth display device (14) may be adjacent to each other in the first direction (DR1). The second display device (12) and the fourth display device (14) may be adjacent to each other in the second direction (DR2).

[0368] However, the number and arrangement of multiple display devices (11, 12, 13, 14) in the tile-type display device (TD) are not limited to those shown in FIG. 35. The number and arrangement of display devices (11, 12, 13, 14) in the tile-type display device (TD) may be determined according to the size of each of the display device (10) and the tile-type display device (TD) and the shape of the tile-type display device (TD).

[0369] Multiple display devices (11, 12, 13, 14) may have the same size as each other, but are not limited thereto. For example, multiple display devices (11, 12, 13, 14) may have different sizes.

[0370] Each of the plurality of display devices (11, 12, 13, 14) may have a rectangular shape including a long side and a short side. The plurality of display devices (11, 12, 13, 14) may be arranged such that their long sides or short sides are connected to one another. Some or all of the plurality of display devices (11, 12, 13, 14) may be placed at the edge of the tile-type display device (TD) and may form one side of the tile-type display device (TD). At least one of the plurality of display devices (11, 12, 13, 14) may be placed at at least one corner of the tile-type display device (TD) and may form two adjacent sides of the tile-type display device (TD). At least one of the plurality of display devices (11, 12, 13, 14) may be surrounded by other display devices.

[0371] Each of the plurality of display devices (11, 12, 13, 14) may be substantially identical to the display device (100) described in conjunction with FIG. 1. Therefore, a description of each of the plurality of display devices (11, 12, 13, 14) is omitted.

[0372] The joint (SM) may include a connecting member or an adhesive member. In this case, a plurality of display devices (11, 12, 13, 14) may be connected to each other through the connecting member or adhesive member of the joint (SM). The joint (SM) may be positioned between the first display device (11) and the second display device (12), between the first display device (11) and the third display device (13), between the second display device (12) and the fourth display device (14), and between the third display device (13) and the fourth display device (14).

[0373] Fig. 36 is an enlarged layout diagram showing the area E of Fig. 35 in detail.

[0374] Referring to FIG. 36, the joint (SM) may have a planar shape of a column cross, a cross, or an addition sign in the central area of ​​a tiled display device (TD) where the first display device (11), the second display device (12), the third display device (13), and the fourth display device (14) are adjacent. The joint (SM) may be positioned between the first display device (11) and the second display device (12), between the first display device (11) and the third display device (13), between the second display device (12) and the fourth display device (14), and between the third display device (13) and the fourth display device (14).

[0375] The first display device (11) may include first pixels (PX1) arranged in a matrix form in a first direction (DR1) and a second direction (DR2) to display an image. The second display device (12) may include second pixels (PX2) arranged in a matrix form in a first direction (DR1) and a second direction (DR2) to display an image. The third display device (13) may include third pixels (PX3) arranged in a matrix form in a first direction (DR1) and a second direction (DR2) to display an image. The fourth display device (14) may include fourth pixels (PX4) arranged in a matrix form in a first direction (DR1) and a second direction (DR2) to display an image.

[0376] The minimum distance between adjacent first pixels (PX1) in the first direction (DR1) is defined as the first horizontal separation distance (GH1), and the minimum distance between adjacent second pixels (PX2) in the first direction (DR1) can be defined as the second horizontal separation distance (GH2). The first horizontal separation distance (GH1) and the second horizontal separation distance (GH2) may be substantially the same.

[0377] A joint (SM) may be disposed between adjacent first pixel (PX1) and second pixel (PX2) in the first direction (DR1). The minimum distance (GM12) between adjacent first pixel (PX1) and second pixel (PX2) in the first direction (DR1) may be the sum of the minimum distance (GHS1) between the first pixel (PX1) and the joint (SM) in the first direction (DR1), the minimum distance (GHS2) between the second pixel (PX2) and the joint (SM) in the first direction (DR1), and the width (GSM1) of the joint (SM) in the first direction (DR1).

[0378] In the first direction (DR1), the minimum distance (GM12), the first horizontal separation distance (GH1), and the second horizontal separation distance (GH2) between adjacent first pixels (PX1) and second pixels (PX2) may be substantially the same. To this end, in the first direction (DR1), the minimum distance (GHS1) between the first pixel (PX1) and the joint (SM) may be smaller than the first horizontal separation distance (GH1), and the minimum distance (GHS2) between the second pixel (PX2) and the joint (SM) in the first direction (DR1) may be smaller than the second horizontal separation distance (GH2). Additionally, in the first direction (DR1), the width (GSM1) of the joint (SM) may be smaller than the first horizontal separation distance (GH1) or the second horizontal separation distance (GH2).

[0379] The minimum distance between adjacent third pixels (PX3) in the first direction (DR1) is defined as the third horizontal separation distance (GH3), and the minimum distance between adjacent fourth pixels (PX4) in the first direction (DR1) can be defined as the fourth horizontal separation distance (GH4). The third horizontal separation distance (GH3) and the fourth horizontal separation distance (GH4) may be substantially the same.

[0380] A joint (SM) may be disposed between adjacent third pixels (PX3) and fourth pixels (PX4) in the first direction (DR1). The minimum distance (GM34) between adjacent third pixels (PX3) and fourth pixels (PX4) in the first direction (DR1) may be the sum of the minimum distance (GHS3) between the third pixel (PX3) and the joint (SM) in the first direction (DR1), the minimum distance (GHS4) between the fourth pixel (PX4) and the joint (SM) in the first direction (DR1), and the width (GSM1) of the joint (SM) in the first direction (DR1). The minimum distance (GM34), the third horizontal separation distance (GH3), and the fourth horizontal separation distance (GH4) between adjacent third pixels (PX3) and fourth pixels (PX4) in the first direction (DR1) may be substantially the same. To this end, the minimum distance (GHS3) between the third pixel (PX3) and the joint (SM) in the first direction (DR1) may be smaller than the third horizontal separation distance (GH3), and the minimum distance (GHS4) between the fourth pixel (PX4) and the joint (SM) in the first direction (DR1) may be smaller than the fourth horizontal separation distance (GH4). Additionally, the width (GSM1) of the joint (SM) in the first direction (DR1) may be smaller than the third horizontal separation distance (GH3) or the fourth horizontal separation distance (GH4).

[0381] The minimum distance between neighboring first pixels (PX1) in the second direction (DR2) is defined as the first vertical separation distance (GV1), and the minimum distance between neighboring third pixels (PX3) in the second direction (DR2) can be defined as the third vertical separation distance (GV3). The first vertical separation distance (GV1) and the third vertical separation distance (GV3) may be substantially the same.

[0382] delete

[0383] A joint (SM) may be disposed between adjacent first pixel (PX1) and third pixel (PX3) in the second direction (DR2). The minimum distance (GM13) between adjacent first pixel (PX1) and third pixel (PX3) in the second direction (DR2) may be the sum of the minimum distance (GVS1) between the first pixel (PX1) and the joint (SM) in the second direction (DR2), the minimum distance (GVS3) between the third pixel (PX3) and the joint (SM) in the second direction (DR2), and the width (GSM2) of the joint (SM) in the second direction (DR2).

[0384] In the second direction (DR2), the minimum distance (GM13), the first vertical separation distance (GV1), and the third vertical separation distance (GV3) between adjacent first pixel (PX1) and third pixel (PX3) may be substantially the same. To this end, in the second direction (DR2), the minimum distance (GVS1) between the first pixel (PX1) and the joint (SM) may be smaller than the first vertical separation distance (GV1), and the minimum distance (GVS3) between the third pixel (PX3) and the joint (SM) in the second direction (DR2) may be smaller than the third vertical separation distance (GV3). Additionally, in the second direction (DR2), the width (GSM2) of the joint (SM) may be smaller than the first vertical separation distance (GV1) or the third vertical separation distance (GV3).

[0385] The minimum distance between adjacent second pixels (PX2) in the second direction (DR2) is defined as the second vertical separation distance (GV2), and the minimum distance between adjacent fourth pixels (PX4) in the second direction (DR2) can be defined as the fourth vertical separation distance (GV4). The second vertical separation distance (GV2) and the fourth vertical separation distance (GV4) may be substantially the same.

[0386] A joint (SM) may be disposed between adjacent second pixels (PX2) and fourth pixels (PX4) in the second direction (DR2). The minimum distance (GM24) between adjacent second pixels (PX2) and fourth pixels (PX4) in the second direction (DR2) may be the sum of the minimum distance (GVS2) between the second pixel (PX2) and the joint (SM) in the second direction (DR2), the minimum distance (GVS4) between the fourth pixel (PX4) and the joint (SM) in the second direction (DR2), and the distance (GSM4) of the joint (SM) in the second direction (DR2).

[0387] In the second direction (DR2), the minimum distance (GM24), the second vertical separation distance (GV2), and the fourth vertical separation distance (GV4) between adjacent second pixels (PX2) and fourth pixels (PX4) may be substantially the same. To this end, in the second direction (DR2), the minimum distance (GVS2) between the second pixel (PX2) and the joint (SM) may be smaller than the second vertical separation distance (GV2), and the minimum distance (GVS4) between the fourth pixel (PX4) and the joint (SM) in the second direction (DR2) may be smaller than the fourth vertical separation distance (GV4). Additionally, in the second direction (DR2), the width (GSM2) of the joint (SM) may be smaller than the second vertical separation distance (GV2) or the fourth vertical separation distance (GV4).

[0388] As shown in FIG. 36, in order to prevent a seam (SM) from being visible between images displayed by a plurality of display devices (11, 12, 13, 14), the minimum distance between pixels of adjacent display devices may be substantially the same as the minimum distance between pixels of each display device.

[0389] FIG. 37 is a cross-sectional view showing an example of a tile-type display device cut along E-E' of FIG. 36.

[0390] Referring to FIG. 37, the first display device (11) includes a first display module (DPM1) and a first front cover (COV1). The second display device (12) includes a second display module (DPM2) and a second front cover (COV2).

[0391] Each of the first display module (DPM1) and the second display module (DPM2) includes a substrate (SUB), a thin-film transistor layer (TFTL), and a light-emitting element layer (EML). The thin-film transistor layer (TFTL) and the light-emitting element layer (EML) have already been described in detail in conjunction with FIGS. 27 and FIGS. 28. In FIGS. 37, descriptions that overlap with the embodiments of FIGS. 27 and FIGS. 28 are omitted.

[0392] A substrate (SUB) may include a first surface (41) on which a thin-film transistor layer (TFTL) is disposed, a second surface (42) facing the first surface, and a first side surface (43) disposed between the first surface (41) and the second surface (42). The first surface (41) may be the front or top surface of the substrate (SUB), and the second surface (42) may be the back or bottom surface of the substrate (SUB).

[0393] Additionally, the substrate (SUB) may further include a chamfer surface (44) disposed between the first surface (41) and the first side (43) and between the second surface (42) and the first side (43). A thin-film transistor layer (TFTL) and a light-emitting element layer (EML) may not be disposed on the chamfer surface (44). Due to the chamfer surface (44), it is prevented that the substrate (SUB) of the first display device (10) and the substrate of the second display device (10) collide and are damaged.

[0394] The chamfer surface (44) may be positioned between each of the other sides excluding the first side (41) and the first side (43), and between each of the other sides excluding the second side (42) and the first side (43). For example, if the first display device (11) and the second display device (12) have a rectangular planar shape as in FIG. 35, the chamfer surface (44) may be positioned between each of the first side (41) and the second side, the third side, and the fourth side, and between each of the second side (42) and the second side, the third side, and the fourth side.

[0395] The first front cover (COV1) can be placed on the chamfered surface (44) of the substrate (SUB). That is, the first front cover (COV1) can protrude beyond the substrate (SUB) in the first direction (DR1) and the second direction (DR2). Therefore, the distance (GSUB) between the substrate (SUB) of the first display device (11) and the substrate (SUB) of the second display device (12) can be greater than the distance (GCOV) between the first front cover (COV1) and the second front cover (COV2).

[0396] Each of the first front cover (COV1) and the second front cover (COV2) may include an adhesive member (51), a light transmittance control layer (52) disposed on the adhesive member (51), and an anti-glare layer (53) disposed on the light transmittance control layer (52).

[0397] The adhesive member (51) of the first front cover (COV1) serves to attach the first front cover (COV1) to the light-emitting element layer (EML) of the first display module (DPM1). The adhesive member (51) of the second front cover (COV2) serves to attach the second front cover (COV2) to the light-emitting element layer (EML) of the second display module (DPM2). The adhesive member (51) may be a transparent adhesive member capable of transmitting light. For example, the adhesive member (51) may be an optically clear adhesive film or an optically clear resin.

[0398] The anti-glare layer (53) can be designed to diffusely reflect external light to prevent the external light from being reflected as is and to prevent a decrease in the visibility of the image. Accordingly, due to the anti-glare layer (53), the contrast ratio of the image displayed by the first display device (10) and the second display device (20) can be increased.

[0399] The light transmittance control layer (52) can be designed to reduce the transmittance of external light or light reflected from the first display module (DPM1) and the second display module (DPM2). As a result, the gap (GSUB) between the substrate (SUB) of the first display module (DPM1) and the substrate (SUB) of the second display module (DPM2) can be prevented from being visible from the outside.

[0400] The anti-glare layer (53) may be implemented as a polarizing plate, and the light transmittance control layer (52) may be implemented as a phase delay layer, but the embodiments of the present specification are not limited thereto.

[0401] Meanwhile, since an example of a tile-type display device (TD) cut along F-F', G-G', and H-H' in FIG. 36 is substantially the same as an example of a tile-type display device (TD) cut along E-E' described in conjunction with FIG. 37, a description thereof is omitted.

[0402] Fig. 38 is an enlarged layout diagram showing the F region of Fig. 35 in detail.

[0403] FIG. 38 shows pads (PADs) placed on the upper side of the first display device (10) and second subpixels (GPs) of the first pixel (PX1).

[0404] Referring to FIG. 38, pads (PADs) may be placed on the upper edge of the first display device (10). When the PWM data lines (DL) of the first display device (10) extend in a second direction (DR2), pads (PADs) may be placed on the upper and lower edges of the first display device (10). Alternatively, when the PWM data lines (DL) of the first display device (10) extend in a first direction (DR1), pads (PADs) may be placed on the left and right edges of the first display device (10).

[0405] Each of the pads (PAD) can be connected to the PWM data line (DL). Additionally, each of the pads (PAD) can be connected to the side line (SSL). The side line (SSL) can be placed on one side and the bottom (or back) of the board (SUB). The side line (SSL) can be connected to the connection line (CCL in FIG. 37) on the bottom of the board (SUB).

[0406] FIG. 39 is a cross-sectional view showing an example of a tile-type display device cut along I-I' of FIG. 38. In FIG. 39, descriptions that overlap with the embodiments of FIG. 27 and FIG. 28 are omitted.

[0407] Referring to FIG. 39, a pad (PAD) may be placed on a first insulating film (161). The pad (PAD) may be exposed without being covered by the second insulating film (181) and the third insulating film (191). Although the pad (PAD) is exemplified as being contained in the second data metal layer, embodiments of this specification are not limited thereto. For example, the pad (PAD) may be contained in the third data metal layer. The pad (PAD) may be connected to a PWM data wiring (DL) through a first side pad contact hole (SCT1) that penetrates the first flattening film (160) and the first insulating film (161).

[0408] The connecting wiring (CCL) may be disposed on the lower surface of the substrate (SUB). The connecting wiring (CCL) may be a single layer or a multilayer composed of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof.

[0409] The third flattening film (170) may be placed on a part of the connecting wiring (CCL). The third flattening film (170) may be formed from an organic film such as an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, or a polyimide resin.

[0410] The fourth insulating film (171) may be disposed on the third planarization film (170). The fourth insulating film (171) may be formed of an inorganic film, for example, a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer.

[0411] Side wiring (SSL) can be placed on the lower edge, side, and upper edge of the substrate (SUB). One end of the side wiring (SSL) can be connected to the connecting wiring (CCL). One end of the side wiring (SSL) can be in contact with the side and lower surface of the connecting wiring (CCL). The other end of the side wiring (SSL) can be connected to the pad portion (PAD). The other end of the side wiring (SSL) can be connected to the pad portion (PAD) through a second side pad contact hole (SCT2) that penetrates the second insulating film (181) and the third insulating film (191).

[0412] Side wiring (SSL) can be placed on the side of the substrate (SUB), the side of the buffer film (BF), the side of the gate insulating film (130), the side of the first interlayer insulating film (141), the side of the second interlayer insulating film (142), the side of the first insulating film (161), the side of the second insulating film (181), and the side of the third insulating film (191).

[0413] A flexible film (FPCB) may be disposed on the lower surface of the fourth insulating film (171). The flexible film (FPCB) may be connected to a connecting wire (CCL) through a back contact hole (BCT) penetrating the third planarization film (170) and the third insulating film (171) using a conductive adhesive member (CAM). A source driving circuit (SIC) for supplying data voltages to PWM data wires (DL) may be disposed on the lower surface of the flexible film (FPCB). The conductive adhesive member (CAM) may be an anisotropic conductive film or anisotropic conductive paste.

[0414] As shown in FIGS. 38 and 39, the source driving circuit (SIC) of the flexible film (FPCB) of the first display device (11) placed on the lower part of the substrate (SUB) can be connected to the data wiring (DL) through the connection wiring (CCL), side wiring (SSL), and pad (PAD). That is, since the source driving circuit (SIC) is placed on the substrate (SUB), the non-display area (NDA) can be eliminated, so pixels (PX) can be formed even on the edges of the substrate (SUB).

[0415] FIG. 40 is a block diagram showing a tile-type display device according to one embodiment.

[0416] In FIG. 40, the first display device (11) and the host system (HOST) are illustrated for convenience of explanation.

[0417] Referring to FIG. 40, a tile-type display device (TD) according to one embodiment may include a host system (HOST), a broadcast tuning unit (210), a signal processing unit (220), a display unit (230), a speaker (240), a user input unit (250), an HDD (260), a network communication unit (270), a UI generation unit (280), and a control unit (290).

[0418] The host system (HOST) can be implemented as any one of a television system, home theater system, set-top box, navigation system, DVD player, Blu-ray player, personal computer (PC), mobile phone system, or tablet.

[0419] User commands can be input to the host system in various formats. For example, the host system may receive commands via user touch input. Alternatively, the host system may receive user commands via keyboard input or button input from a remote controller.

[0420] The host system (HOST) can receive original video data corresponding to the original image from an external source. The host system (HOST) can divide the original video data into as many parts as there are display devices. For example, the host system (HOST) can divide the original video data into first video data corresponding to the first image, second video data corresponding to the second image, third video data corresponding to the third image, and fourth video data corresponding to the fourth image, corresponding to the first display device (11), the second display device (12), the third video data corresponding to the third image, and the fourth video data corresponding to the fourth image. The host system (HOST) can transmit the first video data to the first display device (11), transmit the second video data to the second display device (12), transmit the third video data to the third display device (13), and transmit the fourth video data to the fourth display device (14).

[0421] The first display device (11) can display a first image according to the first video data, the second display device (12) can display a second image according to the second video data, the third display device (13) can display a third image according to the third video data, and the fourth display device (14) can display a fourth image according to the fourth video data. Accordingly, the user can view an original image in which the first to fourth images displayed on the first to fourth display devices (11, 12, 13, 14) are combined.

[0422] The first display device (11) may include a broadcast tuning unit (210), a signal processing unit (220), a display unit (230), a speaker (240), a user input unit (250), an HDD (260), a network communication unit (270), a UI generation unit (280), and a control unit (290).

[0423] The broadcast tuning unit (210) can receive a broadcast signal of a corresponding channel by tuning a predetermined channel frequency according to the control of the control unit (290). The broadcast tuning unit (210) may include a channel detection module and an RF demodulation module.

[0424] The broadcast signal demodulated by the broadcast tuning unit (210) is processed by the signal processing unit (220) and output to the display unit (230) and speaker (240). Here, the signal processing unit (220) may include a demultiplexer (221), a video decoder (222), a video processing unit (223), an audio decoder (224), and an additional data processing unit (225).

[0425] The demultiplexer (221) separates the demodulated broadcast signal into a video signal, an audio signal, and additional data. The separated video signal, audio signal, and additional data are restored by a video decoder (222), an audio decoder (224), and an additional data processing unit (225), respectively. At this time, the video decoder (222), the audio decoder (224), and the additional data processing unit (225) restore the data into a decoding format corresponding to the encoding format used during broadcast signal transmission.

[0426] Meanwhile, the decoded video signal is converted by the video processing unit (223) to match the vertical frequency, resolution, aspect ratio, etc., that match the output specifications of the display unit (230), and the decoded audio signal is output to the speaker (240).

[0427] The display unit (230) includes a display panel (100) on which an image is displayed and a panel driving unit that controls the driving of the display panel (100). A detailed block diagram of the display panel (100) and the panel driving unit has already been described in detail above in conjunction with FIG. 4.

[0428] The user input unit (250) can receive signals transmitted by the host system (HOST). The user input unit (250) can be configured to receive data regarding the selection and operation of the channel transmitted by the host system (HOST), as well as data regarding commands regarding communication with other display devices, as well as data regarding the selection and input of commands by the user.

[0429] The storage unit (260) stores various software programs including OS programs, recorded broadcast programs, videos, photos, and other data, and may be made of a storage medium such as a hard disk or non-volatile memory.

[0430] The network communication unit (270) is for short-range communication with a host system (HOST) and other display devices, and can be implemented as a communication module including an antenna pattern capable of implementing mobile communication, data communication, Bluetooth, RF, Ethernet, etc.

[0431] The network communication unit (270) may transmit and receive wireless signals with at least one of a base station, an external terminal, and a server on a mobile communication network built according to technical standards or communication methods for mobile communication (e.g., GSM (Global System for Mobile communication), CDMA (Code Division Multi Access), CDMA2000 (Code Division Multi Access 2000), EV-DO (Enhanced Voice-Data Optimized or Enhanced Voice-Data Only), WCDMA (Wideband CDMA), HSDPA (High Speed ​​Downlink Packet Access), HSUPA (High Speed ​​Uplink Packet Access), LTE (Long Term Evolution), LTE-A (Long Term Evolution-Advanced), 5G, etc.) through an antenna pattern described later.

[0432] The network communication unit (270) may transmit and receive wireless signals in a communication network according to wireless internet technologies through an antenna pattern described later. Examples of wireless internet technologies include WLAN (Wireless LAN), Wi-Fi (Wireless-Fidelity), Wi-Fi (Wireless Fidelity) Direct, DLNA (Digital Living Network Alliance), WiBro (Wireless Broadband), WiMAX (World Interoperability for Microwave Access), HSDPA (High Speed ​​Downlink Packet Access), HSUPA (High Speed ​​Uplink Packet Access), LTE (Long Term Evolution), LTE-A (Long Term Evolution-Advanced), etc., and the antenna pattern transmits and receives data according to at least one wireless internet technology within a range that includes internet technologies not listed above.

[0433] The UI generation unit (280) generates a UI menu for communication with a host system (HOST) and other display devices, and can be implemented by algorithm code and an OSD IC. The UI menu for communication with a host system (HOST) and other display devices may be a menu for specifying a corresponding digital TV to communicate with and selecting a desired function.

[0434] The control unit (290) is responsible for overall control of the first display device (11) and for communication control of the host system (HOST) and the second to fourth display devices (12, 13, 14), and can be implemented by an MCU (Micro Controller Unit) in which the corresponding algorithm code for control is stored and the stored algorithm code is executed.

[0435] The control unit (290) controls the transmission of corresponding control commands and data to the host system (HOST) and the second to fourth display devices (12, 13, 14) via the network communication unit (270) according to the input and selection of the user input unit (250). Of course, when a predetermined control command and data are input from the host system (HOST) and the second to fourth display devices (12, 13, 14), an operation is performed according to the corresponding control command.

[0436] Meanwhile, the block diagram of the second display device (12), the block diagram of the third display device (13), and the block diagram of the fourth display device (14) are substantially identical to the block diagram of the first display device (11) described in conjunction with FIG. 4, so the description of these is omitted.

[0437] Although embodiments of the present invention have been described above with reference to the attached drawings, those skilled in the art will understand that the present invention may be implemented in other specific forms without changing the technical concept or essential features thereof. Therefore, the embodiments described above should be understood as illustrative in all respects and not restrictive. Explanation of the symbols

[0438] 10: Display device 100: Display panel 110: Scan driver 200: Source driver 300: Timing control unit 400: Power supply unit

Claims

Claim 1 A first subpixel and a second subpixel emitting different light, wherein the first subpixel comprises a first anode pad electrode and a second anode pad electrode disposed apart from each other on a plane; and a first cathode pad electrode disposed apart from the first anode pad electrode and the second anode pad electrode on a plane; A display device comprising a first light-emitting element including a first sub-light-emitting element disposed on the first anode pad electrode and the cathode pad electrode and a second sub-light-emitting element disposed on the second anode pad electrode and the cathode pad electrode, wherein the area of ​​the first cathode pad electrode is larger than the area of ​​the first anode pad electrode or the area of ​​the second anode pad electrode, the first sub-light-emitting element and the second sub-light-emitting element emit light at different periods, and the first sub-light-emitting element and the second sub-light-emitting element emit the same light, and the second sub-pixel includes a third anode pad electrode; a second cathode pad electrode disposed apart from the third anode pad electrode; and a second light-emitting element disposed on the third anode pad electrode and the second cathode pad electrode, wherein the area of ​​the first cathode pad electrode is larger than the area of ​​the second cathode pad electrode. Claim 2 A display device according to claim 1, wherein the length in one direction of the first cathode pad electrode is greater than the length in one direction of the first anode pad electrode or the length in one direction of the second anode pad electrode. Claim 3 delete Claim 4 delete Claim 5 A display device according to claim 1, wherein the length in one direction of the first cathode pad electrode is greater than the length in one direction of the second cathode pad electrode. Claim 6 A display device according to claim 1, comprising a third subpixel emitting light different from the first subpixel and the second subpixel, wherein the third subpixel comprises: a fourth anode pad electrode; a third cathode pad electrode disposed apart from the third anode pad electrode on a plane; and a third light-emitting element disposed on the fourth anode pad electrode and the third cathode pad electrode. Claim 7 In claim 6, a display device in which the area of ​​the first cathode pad electrode is larger than the area of ​​the third cathode pad electrode. Claim 8 In claim 7, a display device in which the length in one direction of the first cathode pad electrode is greater than the length in one direction of the third cathode pad electrode. Claim 9 A display device according to claim 8, wherein the first sub-luminescent element and the second sub-luminescent element emit a first light, the second light-emitting element emits a second light, and the third light-emitting element emits a third light. Claim 10 A display device according to claim 9, wherein the first light is red light, the second light is green light, and the third light is blue light. Claim 11 A first data wiring to which a first data voltage is applied; a second data wiring to which a second data voltage is applied; a first light emission control wiring to which a first light emission control signal is applied; a second light emission control wiring to which a second light emission control signal is applied; a first initialization signal wiring to which a first initialization signal is applied; an initialization voltage wiring to which an initialization voltage is applied; and a first subpixel connected to the first data wiring, the second data wiring, the first light emission control wiring, and the second light emission control wiring, the first initialization signal wiring, and the initialization voltage wiring, wherein the first subpixel comprises: a first light-emitting element including a first sub-light-emitting element and a second sub-light-emitting element that emit a first light; a first pixel driving unit that generates a control current according to the first data voltage of the first data wiring; and a second pixel driving unit that generates a first driving current applied to the first sub-light-emitting element or the second sub-light-emitting element according to the second data voltage of the second data wiring. and includes a third pixel driver that controls the period for applying the first driving current to the first sub-light-emitting element or the second sub-light-emitting element according to the control current of the first pixel driver, wherein the third pixel driver comprises: a first transistor that supplies the first driving current to the first sub-light-emitting element according to the first light-emitting control signal; a second transistor that supplies the first driving current to the second sub-light-emitting element according to the second light-emitting control signal; and a third transistor that supplies the initialization voltage to the first electrode of the first sub-light-emitting element according to the first initialization signal.A display device comprising a fourth transistor that supplies the initialization voltage to the first electrode of the second sub-luminescent element according to the first initialization signal, wherein the first light emission control signal has a gate-on voltage during the Nth frame period and a gate-off voltage during the N+1 frame period, and the second light emission control signal has the gate-off voltage during the Nth frame period and the gate-on voltage during the N+1 frame period. Claim 12 delete Claim 13 A display device according to claim 11, further comprising: a light-emitting signal wiring to which a light-emitting signal is applied; and a second subpixel connected to the light-emitting signal wiring and the first initialization signal wiring, wherein the second subpixel comprises: a second light-emitting element that emits a second light; a fifth transistor that supplies a second driving current to the second light-emitting element according to the light-emitting signal; and a sixth transistor that supplies an initialization voltage to the first electrode of the second light-emitting element according to the first initialization signal. Claim 14 A display device according to claim 13, wherein the first light is red light and the second light is green light or blue light. Claim 15 A first data wiring to which a first data voltage is applied; a second data wiring to which a second data voltage is applied; a first light emission signal wiring to which a first light emission signal is applied; a second light emission signal wiring to which a second light emission signal is applied; a first subpixel connected to the first data wiring, the second data wiring, the first light emission signal wiring, and the second light emission signal wiring; and a second subpixel connected to the first light emission signal wiring and the second light emission signal wiring, wherein the first subpixel comprises: a first light-emitting element including a first sub-light-emitting element and a second sub-light-emitting element that emit a first light; a first pixel driver that generates a control current according to the first data voltage of the first data wiring; and a second pixel driver that generates a first driving current applied to the first sub-light-emitting element or the second sub-light-emitting element according to the second data voltage of the second data wiring. A display device comprising a third pixel driver that controls the period for applying the first driving current to the first sub-light-emitting element or the second sub-light-emitting element according to the control current of the first pixel driver, wherein the third pixel driver comprises: a first transistor that supplies the first driving current to the first sub-light-emitting element according to the first light-emitting signal; and a second transistor that supplies the first driving current to the second sub-light-emitting element according to the second light-emitting signal, wherein one frame period comprises a plurality of light-emitting periods, and the first transistor and the second transistor are turned on during different light-emitting periods among the plurality of light-emitting periods, and the second sub-pixel comprises: a second light-emitting element that emits a second light; a fifth transistor that supplies the second driving current to the second light-emitting element according to the first light-emitting signal; and a sixth transistor that supplies the second driving current to the second light-emitting element according to the second light-emitting signal. Claim 16 A display device according to claim 15, wherein the first transistor is turned on during odd-numbered light-emitting periods among the plurality of light-emitting periods, and the second transistor is turned on during excellent-numbered light-emitting periods among the plurality of light-emitting periods. Claim 17 A display device according to claim 15, wherein during odd-numbered light-emitting periods among the plurality of light-emitting periods, the first light-emitting signal has a gate-on voltage and the second light-emitting signal has a gate-off voltage, and during excellent-numbered light-emitting periods among the plurality of light-emitting periods, the second light-emitting signal has the gate-on voltage and the first light-emitting signal has the gate-off voltage. Claim 18 A display device according to claim 15, further comprising: a first initialization signal wiring to which a first initialization signal is applied; and an initialization voltage wiring to which an initialization voltage is applied, wherein the third pixel driver further comprises: a third transistor that supplies the initialization voltage to a first electrode of the first sub-light-emitting element according to the first initialization signal; and a fourth transistor that supplies the initialization voltage to a first electrode of the second sub-light-emitting element according to the first initialization signal. Claim 19 delete Claim 20 A display device according to claim 15, further comprising: a first initialization signal wiring to which a first initialization signal is applied; and an initialization voltage wiring to which an initialization voltage is applied, wherein the second subpixel further comprises a seventh transistor that supplies the initialization voltage to a first electrode of the second light-emitting element according to the first initialization signal. Claim 21 A display device according to claim 15, wherein the first light is red light and the second light is green light or blue light. Claim 22 In claim 6, the first sub-luminescent element, the second sub-luminescent element, the second luminescent element, and the third luminescent element are each flip-chip type micro-luminescent diode elements in the display device. Claim 23 In claim 13, the first sub-luminescent element, the second sub-luminescent element, and the second luminescent element are each flip-chip type micro-luminescent diode elements in a display device. Claim 24 In claim 15, the first sub-luminescent element, the second sub-luminescent element, and the second luminescent element are each flip-chip type micro-luminescent diode elements in a display device. Claim 25 A plurality of display devices; and a joint disposed between the plurality of display devices, wherein one of the plurality of display devices includes a plurality of subpixels, and the display device comprises: a first anode pad electrode and a second anode pad electrode disposed apart from each other on a plane; and a first cathode pad electrode disposed apart from the first anode pad electrode and the second anode pad electrode on a plane. A tile-type display device comprising a first light-emitting element including a first sub-light-emitting element disposed on the first anode pad electrode and the cathode pad electrode and a second sub-light-emitting element disposed on the second anode pad electrode and the cathode pad electrode, wherein the area of ​​the first cathode pad electrode is larger than the area of ​​the first anode pad electrode or the area of ​​the second anode pad electrode, the first sub-light-emitting element and the second sub-light-emitting element emit light at different periods, and the first sub-light-emitting element and the second sub-light-emitting element emit the same light, and the display device comprises a third anode pad electrode; a second cathode pad electrode disposed apart from the third anode pad electrode; and a second light-emitting element disposed on the third anode pad electrode and the second cathode pad electrode, wherein the length in one direction of the first cathode pad electrode is larger than the length in one direction of the second cathode pad electrode. Claim 26 In claim 25, the tile-type display device wherein each of the first sub-light-emitting element and the second sub-light-emitting element is a flip-chip type micro light-emitting diode element. Claim 27 In claim 25, the display device comprises: a substrate; a pad disposed on a first surface of the substrate; and a side wiring disposed on a first surface of the substrate, a second surface opposite to the first surface, and a side wiring connected to the pad. Claim 28 In claim 27, the substrate is a tile-type display device made of glass. Claim 29 In claim 27, the display device further comprises: a connecting wire disposed on a second surface of the substrate; and a flexible film connected to the connecting wire through a conductive adhesive member, wherein the side wiring is connected to the connecting wire, forming a tile-type display device. Claim 30 In claim 25, the plurality of display devices are tile-type display devices arranged in a matrix form with M (M is a positive integer) rows and N (N is a positive integer) columns.

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