Display device

Abstract

The present invention relates to a display device. A display device according to one embodiment comprises a substrate, an insulating film disposed on the substrate, a first sub-power wiring disposed on the insulating film to which a first power supply voltage is applied, a first organic film disposed on the first sub-power wiring, a second sub-power wiring disposed on the first organic film and connected to the first sub-power wiring through a first power hole penetrating the first organic film, a third sub-power wiring disposed on the second sub-power wiring, a pixel electrode disposed on the first organic film, a light-emitting element disposed on the pixel electrode, a planarization film disposed on the side of the light-emitting element, and a common electrode disposed on the light-emitting element and the planarization film. The planarization film is disposed on the third sub-power wiring.

Description

Technology Field

[0001] The present invention relates to a display device. Background Technology

[0002] As the information society develops, the demand for display devices to display images is increasing in various forms. Display devices may be flat panel display devices such as Liquid Crystal Displays, Field Emission Displays, and Light Emitting Displays.

[0003] The light-emitting display device may be implemented as an organic light-emitting display device including an organic light-emitting diode element as a light-emitting element, an inorganic light-emitting display device including an inorganic semiconductor element as a light-emitting element, or a micro light-emitting diode display device including a micro light-emitting diode element (or micro light-emitting diode element) as a light-emitting element. In this case, since the micro light-emitting diode element is bonded to the pixel electrode in the micro light-emitting diode display device, it is necessary to reduce the resistance of the pixel electrode. The problem to be solved

[0004] The problem that the present invention aims to solve is to provide a display device capable of reducing the resistance of a pixel electrode joined to a micro-sized light-emitting diode element.

[0005] The problems of the present invention are not limited to those mentioned above, and other unmentioned technical problems will be clearly understood by those skilled in the art from the description below. means of solving the problem

[0006] A display device according to one embodiment for solving the above problem comprises a substrate, an insulating film disposed on the substrate, a first sub-power wiring disposed on the insulating film to which a first power supply voltage is applied, a first organic film disposed on the first sub-power wiring, a second sub-power wiring disposed on the first organic film and connected to the first sub-power wiring through a first power hole penetrating the first organic film, a third sub-power wiring disposed on the second sub-power wiring, a pixel electrode disposed on the first organic film, a light-emitting element disposed on the pixel electrode, a planarization film disposed on the side of the light-emitting element, and a common electrode disposed on the light-emitting element and the planarization film. The planarization film is disposed on the third sub-power wiring.

[0007] The pixel electrode and the third sub-power wiring may be made of the same material.

[0008] The pixel electrode and the third sub-power wiring may be made of a material different from the first sub-power wiring, and the pixel electrode and the third sub-power wiring may be made of a material different from the second sub-power wiring.

[0009] The pixel electrode and the third sub-power wiring are made of copper, and the first sub-power wiring and the second sub-power wiring may include a first layer made of titanium, a second layer made of aluminum, and a third layer made of titanium.

[0010] The upper surface of the second sub-power wiring can come into contact with the lower surface of the third sub-power wiring.

[0011] The apparatus may further comprise a fourth sub-power wiring disposed on the insulating film and to which a second power supply voltage is applied, a fifth sub-power wiring disposed on the first organic film and connected to the fourth sub-power wiring through a second power hole penetrating the first organic film, and a sixth sub-power wiring disposed on the fifth sub-power wiring.

[0012] The above first power supply voltage can be supplied to the common electrode.

[0013] The above flattening film can be placed on the above 6th sub-power wiring.

[0014] The pixel electrode and the sixth sub-power wiring may be made of the same material.

[0015] The above-mentioned sixth sub-power wiring is made of a material different from the above-mentioned fourth sub-power wiring, and the above-mentioned sixth sub-power wiring may be made of a material different from the above-mentioned fifth sub-power wiring.

[0016] The above third sub-power wiring and the above sixth sub-power wiring may be made of the same material.

[0017] The first sub-power wiring and the fourth sub-power wiring are made of the same material, and the second sub-power wiring and the fifth sub-power wiring may be made of the same material.

[0018] The upper surface of the above-mentioned fifth sub-power wiring can come into contact with the lower surface of the above-mentioned sixth sub-power wiring.

[0019] A display device according to one embodiment for solving the above problem comprises a substrate, a scan line disposed on the substrate, a first insulating film disposed on the scan lines, a first sub-clock line disposed on the first insulating film to which a clock signal is applied, a first organic film disposed on the clock line, a second sub-clock line disposed on the first organic film and connected to the first sub-clock line through a first contact hole penetrating the first organic film, a third sub-clock line disposed on the second sub-clock line, a pixel electrode disposed on the first organic film, a light-emitting element disposed on the pixel electrode, a planarization film disposed on the side of the light-emitting element, and a common electrode disposed on the light-emitting element and the planarization film. The planarization film is disposed on the third sub-clock line.

[0020] A scan driving unit that applies a scan signal to the scan wiring according to the above clock signal may be further provided.

[0021] The pixel electrode and the third sub-clock wiring may be made of the same material.

[0022] The pixel electrode and the third sub-clock wiring may be made of a material different from the first sub-clock wiring, and the pixel electrode and the third sub-clock wiring may be made of a material different from the second sub-clock wiring.

[0023] A display device according to one embodiment for solving the above problem comprises a substrate, an insulating film disposed on the substrate, a pad disposed on the insulating film, a first organic film disposed on the pad, a pad protection electrode disposed on the first organic film and connected to the pad through a pad hole penetrating the first organic film, a pixel electrode disposed on the first organic film, a light-emitting element disposed on the pixel electrode, a planarization film disposed on the side of the light-emitting element, and a common electrode disposed on the light-emitting element and the planarization film.

[0024] The apparatus may further comprise a first sub-power wiring disposed on the insulating film and to which a first power supply voltage is applied, a second sub-power wiring disposed on the first organic film and connected to the first sub-power wiring through a first power hole penetrating the first organic film, and a third sub-power wiring disposed on the second sub-power wiring. The first sub-power wiring may be made of the same material as the pad.

[0025] The above pad protection electrode may be made of a transparent conductive oxide.

[0026] Specific details of other embodiments are included in the detailed description and drawings. Effects of the invention

[0027] According to the display device of the embodiments, the pixel electrodes serve to be joined with the first light-emitting element, the second light-emitting element, or the third light-emitting element, so they can be made of copper (Cu) with low sheet resistance. As a result, the contact resistance between the pixel electrodes and the first light-emitting element, the second light-emitting element, or the third light-emitting element can be reduced.

[0028] In addition, according to the display device of the embodiments, the area of ​​the first power wiring is increased by including a first sub-power wiring, a second sub-power wiring, and a third sub-power wiring, which are respectively arranged in three layers. In addition, the third sub-power wiring is made of a metal material with low sheet resistance, for example, copper (Cu). Therefore, the resistance of the first power wiring can be lowered. Accordingly, the width of the first power wiring arranged in the non-display area can be reduced, and thus the width of the non-display area can be reduced. In addition, the ripple caused by the first power wiring being affected by voltage changes of other wiring that overlap with it can be minimized.

[0029] Furthermore, according to the display device of the embodiments, each of the clock connection lines includes a first sub-clock line, a second sub-clock line, and a third sub-clock line, each disposed on a plurality of layers, thereby increasing the area of ​​each of the clock connection lines. Additionally, the third sub-clock line is made of a metal material with low sheet resistance, for example, copper (Cu). Therefore, since the resistance of each of the scan clock lines can be lowered, the load of the scan signal output to the scan lines, i.e., the RC delay, can be reduced.

[0030] The effects according to the embodiments are not limited to those exemplified above, and a wider variety of effects are included in this specification. Brief explanation of the drawing

[0031] FIG. 1 is a perspective view showing a display device according to one embodiment. FIGS. 2 and FIGS. 3 are plan views showing a display device according to one embodiment. FIG. 4 is a circuit diagram showing a subpixel of a display panel according to one embodiment. FIG. 5 is a circuit diagram showing a subpixel of a display panel according to another embodiment. FIG. 6 is a layout diagram showing subpixels of a display area of ​​a display panel according to one embodiment. FIG. 7 is a cross-sectional view showing an example of a display panel cut along A-A' of FIG. 6. FIG. 8 is an exemplary drawing showing a pixel electrode, a light-emitting element, a common electrode, and a third planarization film according to one embodiment. FIG. 9 is a layout diagram showing the first power wiring and the second power wiring of the non-display area of ​​a display panel according to one embodiment. Figure 10 is a layout diagram showing area B of Figure 9 in detail. FIG. 11 is a cross-sectional view showing an example of a display panel cut along B-B' of FIG. 9. FIG. 12 is a cross-sectional view showing an example of a display panel cut along C-C' of FIG. 9. FIG. 13 is a cross-sectional view showing an example of a pad of the display panel of FIG. 8. FIG. 14 is a layout diagram showing the first power wiring and the second power wiring of the non-display area of ​​a display panel according to another embodiment. FIG. 15 is a cross-sectional view showing an example of a display panel cut along H-H' of FIG. 14. FIG. 16 is a cross-sectional view showing an example of a display panel cut along I-I' of FIG. 14. FIG. 17 is a layout diagram showing an example of a first scan driving unit in a non-display area of ​​a display panel according to one embodiment. FIG. 18 is a cross-sectional view showing an example of a display panel cut along J-J' of FIG. 17. FIG. 19 is a layout diagram showing an example of a first scan driving unit in a non-display area of ​​a display panel according to one embodiment. FIG. 20 is a cross-sectional view showing another example of a display panel cut along K-K' of FIG. 19. FIG. 21 is an example drawing showing a smart device including a display device according to one embodiment. FIG. 22 is an exemplary drawing showing a virtual reality device including a display device according to one embodiment. FIG. 23 is an exemplary drawing showing an automobile instrument panel and center fascia including a display device according to one embodiment. FIG. 24 is an exemplary drawing showing a transparent display device including a display device according to one embodiment. FIG. 25 is a perspective view showing a display device according to another embodiment. FIG. 26 is an example drawing showing a smart device including a display device according to another embodiment. Specific details for implementing the invention

[0032] The advantages and features of the present invention and the methods for achieving them will become clear by referring to the embodiments described below in detail together with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below but may be implemented in various different forms. These embodiments are provided merely to ensure that the disclosure of the present invention is complete and to fully inform those skilled in the art of the scope of the invention, and the present invention is defined only by the scope of the claims.

[0033] When elements or layers are referred to as being "on" another element or layer, this includes cases where another layer or element is interposed directly on or in the middle of another element. Throughout the specification, the same reference numerals refer to the same components. Shapes, sizes, ratios, angles, numbers, etc., disclosed in the drawings for describing embodiments are exemplary and therefore the invention is not limited to the depicted details.

[0034] Although terms such as "first," "second," etc., are used to describe various components, it goes without saying that these components are not limited by these terms. These terms are used merely to distinguish one component from another. Therefore, it goes without saying that the first component mentioned below may also be the second component within the technical scope of the present invention.

[0035] The features of each of the various embodiments of the present invention may be combined or combined with one another, either partially or wholly, and may technically enable various interlocking and operation. Each embodiment may be implemented independently of one another or may be implemented together in an associated relationship.

[0036] Specific embodiments will be described below with reference to the attached drawings.

[0037] FIG. 1 is a perspective view showing a display device according to one embodiment.

[0038] Referring to FIG. 1, the display device (10) is a device for displaying video or still images and can be used as a display screen for various products such as televisions, laptops, monitors, billboards, and the Internet of Things (IOT), as well as portable electronic devices such as mobile phones, smartphones, tablet PCs, smart watches, watch phones, mobile communication terminals, electronic notebooks, electronic books, PMPs (portable multimedia players), navigation systems, and UMPCs (Ultra Mobile PCs).

[0039] The display device (10) may be a light-emitting display device such as an organic light-emitting display device using an organic light-emitting diode, a quantum dot light-emitting display device including a quantum dot light-emitting layer, an inorganic light-emitting display device including an inorganic semiconductor, and a micro light-emitting display device using a micro or nano light-emitting diode (micro LED or nano LED). In the following description, the display device (10) is described with an emphasis on being a micro light-emitting display device, but the present invention is not limited thereto. Meanwhile, for convenience of explanation, the micro light-emitting diode is described as a micro light-emitting diode.

[0040] The display device (10) includes a display panel (100), a display driving circuit (200), and a circuit board (300).

[0041] The display panel (100) may be formed as a rectangular plane having a short side in a first direction (DR1) and a long side in a second direction (DR2) that intersects the first direction (DR1). The corner where the short side in the first direction (DR1) and the long side in the second direction (DR2) meet may be formed rounded to have a predetermined curvature or formed at a right angle. The plane shape of the display panel (100) is not limited to a rectangle and may be formed as other polygons, circles, or ellipses. The display panel (100) may be formed flat, but is not limited thereto. For example, the display panel (100) may include curved surfaces formed at the left and right ends that have a constant curvature or a changing curvature. In addition, the display panel (100) may be formed flexibly so that it can be bent, curved, folded, or rolled.

[0042] The substrate (SUB) of the display panel (100) may include a main area (MA) and a sub area (SBA).

[0043] The main area (MA) may include a display area (DA) that displays an image and a non-display area (NDA) which is a surrounding area of ​​the display area (DA). The display area (DA) may include a plurality of subpixels (SPX1, SPX2, SPX3 of FIG. 6) that display an image. For example, the display area (DA) may include a first subpixel (SPX1) that emits a first light, a second subpixel (SPX2) that emits a second light, and a third subpixel (SPX3) that emits a third light.

[0044] A sub-region (SBA) may protrude in a second direction (DR2) from one side of a main region (MA). Although FIG. 1 illustrates a sub-region (SBA) unfolded, the sub-region (SBA) may be bent, in which case it may be placed on the lower surface of the display panel (100). When the sub-region (SBA) is bent, it may overlap with the main region (MA) in a third direction (DR3), which is the thickness direction of the display panel (100). A display driving circuit (200) may be placed in the sub-region (SBA).

[0045] The display driving circuit (200) can generate signals and voltages to drive the display panel (100). The display driving circuit (200) may be formed as an integrated circuit (IC) and attached to the display panel (100) using a COG (chip on glass) method, a COP (chip on plastic) method, or an ultrasonic bonding method, but is not limited thereto. For example, the display driving circuit (200) may be attached to the circuit board (300) using a COF (chip on film) method.

[0046] A circuit board (300) can be attached to one end of a sub-region (SBA) of a display panel (100). As a result, the circuit board (300) can be electrically connected to the display panel (100) and the display driving circuit (200). The display panel (100) and the display driving circuit (200) can receive digital video data, timing signals, and driving voltages through the circuit board (300). The circuit board (300) may be a flexible printed circuit board, a printed circuit board, or a flexible film such as a chip-on-film.

[0047] FIGS. 2 and FIGS. 3 are plan views showing a display device according to one embodiment. FIG. 2 illustrates a sub-region (SBA) unfolded without being bent. FIG. 3 illustrates a sub-region (SBA) bent.

[0048] Referring to FIGS. 2 and FIGS. 3, the display panel (100) may include a main area (MA) and a sub area (SBA).

[0049] The main area (MA) may include a display area (DA) for displaying an image and a non-display area (NDA) which is the surrounding area of ​​the display area (DA). The display area (DA) may occupy most of the main area (MA). The display area (DA) may be positioned in the center of the main area (MA).

[0050] The non-display area (NDA) may be positioned adjacent to the display area (DA). The non-display area (NDA) may be an outer area of ​​the display area (DA). The non-display area (NDA) may be positioned to surround the display area (DA). The non-display area (NDA) may be an edge area of ​​the display panel (100).

[0051] The first scan driver (SDC1) and the second scan driver (SDC2) may be placed in a non-display area (NDA). The first scan driver (SDC1) may be placed on one side (e.g., the left side) of the display panel (100), and the second scan driver (SDC2) may be placed on the other side (e.g., the right side) of the display panel, but is not limited thereto. Each of the first scan driver (SDC1) and the second scan driver (SDC2) may be electrically connected to the display driving circuit (200) through scan fan-out wiring (SFLs in FIG. 10). Each of the first scan driver (SDC1) and the second scan driver (SDC2) may receive a scan control signal from the display driving circuit (200), generate scan signals according to the scan control signal, and output them to the scan wiring.

[0052] A sub-region (SBA) may protrude in a second direction (DR2) from one side of a main region (MA). The length of the second direction (DR2) of the sub-region (SBA) may be shorter than the length of the second direction (DR2) of the main region (MA). The length of the first direction (DR1) of the sub-region (SBA) may be shorter than the length of the first direction (DR1) of the main region (MA) or substantially equal to the length of the first direction (DR1) of the main region (MA). The sub-region (SBA) may be bent and may be positioned at the bottom of the display panel (100). In this case, the sub-region (SBA) may overlap with the main region (MA) in a third direction (DR3).

[0053] The sub-region (SBA) may include a connection region (CA), a pad region (PA), and a bending region (BA).

[0054] The connection area (CA) is an area protruding in a second direction (DR2) from one side of the main area (MA). One side of the connection area (CA) is in contact with the non-display area (NDA) of the main area (MA), and the other side of the connection area (CA) may be in contact with the bending area (BA).

[0055] The pad area (PA) is an area where pads (PDs) and a display driving circuit (200) are placed. The display driving circuit (200) can be attached to the driving pads of the pad area (PA) using a conductive adhesive member such as an anisotropic conductive film. The circuit board (300) can be attached to the pads (PDs) of the pad area (PA) using a conductive adhesive member such as an anisotropic conductive film. One side of the pad area (PA) may be in contact with the bending area (BA).

[0056] The bending area (BA) is a bending area. When the bending area (BA) is bent, the pad area (PA) may be positioned below the connecting area (CA) and below the main area (MA). The bending area (BA) may be positioned between the connecting area (CA) and the pad area (PA). One side of the bending area (BA) is in contact with the connecting area (CA), and the other side of the bending area (BA) may be in contact with the pad area (PA).

[0057] FIG. 4 is a circuit diagram showing a first subpixel of a display panel according to one embodiment.

[0058] Referring to FIG. 4, a first subpixel (SPX1) according to one embodiment may be connected to scan lines (GWL, GIL, GCL, GBL), light-emitting lines (EL), and data lines (DL). For example, the first subpixel (SPX1) may be connected to write scan lines (GWL), initial scan lines (GIL), control scan lines (GCL), bias scan lines (GBL), light-emitting lines (EL), and data lines (DL).

[0059] A first subpixel (SPX1) according to one embodiment includes a driving transistor (DT), switching elements, a capacitor (C1), and a first light-emitting element (LE1). The switching elements include first to sixth transistors (ST1, ST2, ST3, ST4, ST5, ST6).

[0060] The driving transistor (DT) includes a gate electrode, a first electrode, and a second electrode. The driving transistor (DT) controls the drain-source current (Ids, hereinafter referred to as "driving current") flowing between the first electrode and the second electrode according to the data voltage applied to the gate electrode.

[0061] The first light-emitting element (LE1) may be an organic light-emitting diode comprising an anode electrode (or pixel electrode), a cathode electrode (or common electrode), and an organic light-emitting layer disposed between the anode electrode and the cathode electrode. Alternatively, the first light-emitting element (LE1) may be an inorganic light-emitting element comprising an anode electrode, a cathode electrode, and an inorganic semiconductor disposed between the anode electrode and the cathode electrode. Alternatively, the first light-emitting element (LE1) may be a quantum dot light-emitting element comprising an anode electrode, a cathode electrode, and a quantum dot light-emitting layer disposed between the anode electrode and the cathode electrode. Alternatively, the first light-emitting element (LE1) may be a micro light-emitting diode. For convenience of explanation, the following description focuses on the light-emitting element (LE) being a micro light-emitting diode.

[0062] The first light-emitting element (LE1) emits light according to the driving current (Ids). The amount of light emitted by the first light-emitting element (LE1) may be proportional to the driving current (Ids). The anode electrode of the first light-emitting element (LE1) is connected to the first electrode of the fourth transistor (ST4) and the second electrode of the sixth transistor (ST6), and the cathode electrode may be connected to the second power wiring (VSL) to which the second power supply voltage is applied.

[0063] A capacitor (C1) is formed between the second electrode of a driving transistor (DT) and a first power line (VDL) to which a first power supply voltage is applied. The first power supply voltage may be a voltage level higher than the second power supply voltage. One electrode of the capacitor (C1) may be connected to the second electrode of the driving transistor (DT), and the other electrode may be connected to the first power line (VDL).

[0064] As shown in FIG. 4, the first to sixth transistors (ST1, ST2, ST3, ST4, ST5, ST6) and the driving transistor (DT) can all be formed as p-type MOSFETs. In this case, the active layer of each of the first to sixth transistors (ST1, ST2, ST3, ST4, ST5, ST6) and the driving transistor (DT) can be formed of polysilicon or oxide semiconductor.

[0065] The gate electrode of the second transistor (ST2) may be connected to the write scan line (GWL), and the gate electrode of the first transistor (ST1) may be connected to the control scan line (GCL). The gate electrode of the third transistor (ST3) may be connected to the initial scan line (GIL), and the gate electrode of the fourth transistor (ST4) may be connected to the bias scan line (GBL). Since the first to sixth transistors (ST1, ST2, ST3, ST4, ST5, ST6) are formed as p-type MOSFETs, they can be turned on when a scan signal of gate low voltage and a light emission signal are applied to the control scan line (GCL), the initial scan line (GIL), the write scan line (GWL), the bias scan line (GBL), and the light emission line (EL), respectively. One electrode of the third transistor (ST3) and one electrode of the fourth transistor (ST4) may be connected to the initial voltage line (VIL).

[0066] FIG. 5 is a circuit diagram showing a first subpixel of a display panel according to another embodiment.

[0067] Referring to FIG. 5, the driving transistor (DT), the second transistor (ST2), the fourth transistor (ST4), the fifth transistor (ST5), and the sixth transistor (ST6) may be formed as p-type MOSFETs, and the first transistor (ST1) and the third transistor (ST3) may be formed as n-type MOSFETs. The active layer of each of the driving transistor (DT), the second transistor (ST2), the fourth transistor (ST4), the fifth transistor (ST5), and the sixth transistor (ST6) formed as p-type MOSFETs may be formed of polysilicon, and the active layer of each of the first transistor (ST1) and the third transistor (ST3) formed as n-type MOSFETs may be formed of an oxide semiconductor. In this case, the transistors formed of polysilicon and the transistors formed of oxide semiconductors may be placed on different layers.

[0068] Since the first transistor (ST1) and the third transistor (ST3) are formed as n-type MOSFETs, the first transistor (ST1) can be turned on when a control scan signal of gate high voltage is applied to the control scan line (GCL), and the third transistor (ST3) can be turned on when an initial scan signal is applied to the initial scan line (GIL). In contrast, the second transistor (ST2), the fourth transistor (ST4), the fifth transistor (ST5), and the sixth transistor (ST6) are formed as p-type MOSFETs, so they can be turned on when a scan signal of gate low voltage and a light emission signal are applied to the write scan line (GWL), the bias scan line (GBL), and the light emission line (EL), respectively.

[0069] Alternatively, the fourth transistor (ST4) in FIG. 4 may be formed as an n-type MOSFET. In this case, the active layer of each of the fourth transistors (ST4) may be formed as an oxide semiconductor. When the fourth transistor (ST4) is formed as an n-type MOSFET, it may be turned on when a bias scan signal of gate high voltage is applied to the bias scan wiring (GBL).

[0070] Alternatively, although not shown in FIGS. 4 and 5, the first to sixth transistors (ST1, ST2, ST3, ST4, ST5, ST6) and the driving transistor (DT) may all be formed as n-type MOSFETs.

[0071] Meanwhile, the circuit diagram of the second subpixel (SPX2 in FIG. 6) and the circuit diagram of the third subpixel (SPX3 in FIG. 6) according to one embodiment are substantially identical to the circuit diagram of the first subpixel (SPX1) described in conjunction with FIG. 4 and FIG. 5, so a description thereof is omitted.

[0072] FIG. 6 is a layout diagram showing subpixels of a display area of ​​a display panel according to one embodiment.

[0073] Referring to FIG. 6, the display area (DA) may include a plurality of pixels (PX). Each of the plurality of pixels (PX) may include a first subpixel (SPX1), a second subpixel (SPX2), and a third subpixel (SPX3).

[0074] The first subpixel (SPX1) may include a pixel electrode (PXE) and first light-emitting elements (LE1) that emit a first light. The first light may be light in the red wavelength band. The red wavelength band may be approximately 600 nm to 750 nm, but the embodiments of the present specification are not limited thereto.

[0075] The second subpixel (SPX2) may include a pixel electrode (PXE) and second light-emitting elements (LE2) that emit second light. The second light may be light in the green wavelength band. The green wavelength band may be approximately 480 nm to 560 nm, but the embodiments of this specification are not limited thereto.

[0076] The third subpixel (SPX3) may include a pixel electrode (PXE) and third light-emitting elements (LE3) that emit third light. The third light may be light in the blue wavelength band. The blue wavelength band may be approximately 370 nm to 460 nm, but the embodiments of this specification are not limited thereto.

[0077] In each of the pixels (PX), the first subpixel (SPX1), the second subpixel (SPX2), and the third subpixel (SPX3) can be arranged in a first direction (DR1). Additionally, the first subpixels (SPX1) can be arranged in a second direction (DR2), the second subpixels (SPX2) can be arranged in a second direction (DR2), and the third subpixels (SPX3) can be arranged in a second direction (DR2).

[0078] Although the pixel electrode (PXE) has been exemplified as having a rectangular planar shape, the embodiments of this specification are not limited thereto.

[0079] The first light-emitting elements (LE1) can be arranged in a first direction (DR1) and a second direction (DR2) on the pixel electrode (PXE) of the first subpixel (SPX1). For example, the first light-emitting elements (LE1) can be arranged in a matrix form in 5 rows and 2 columns on the pixel electrode (PXE) of the first subpixel (SPX1). That is, 10 first light-emitting elements (LE1) can be placed on the pixel electrode (PXE) of the first subpixel (SPX1).

[0080] The second light-emitting elements (LE2) can be arranged in a first direction (DR1) and a second direction (DR2) on the pixel electrode (PXE) of the second subpixel (SPX2). For example, the second light-emitting elements (LE2) can be arranged in a matrix form in 5 rows and 2 columns on the pixel electrode (PXE) of the second subpixel (SPX1). That is, 10 second light-emitting elements (LE2) can be placed on the pixel electrode (PXE) of the second subpixel (SPX2).

[0081] The third light-emitting elements (LE3) can be arranged in a first direction (DR1) and a second direction (DR2) on the pixel electrode (PXE) of the third subpixel (SPX3). For example, the third light-emitting elements (LE3) can be arranged in a matrix form in 5 rows and 2 columns on the pixel electrode (PXE) of the third subpixel (SPX3). That is, 10 third light-emitting elements (LE3) can be placed on the pixel electrode (PXE) of the second subpixel (SPX2).

[0082] FIG. 7 is a cross-sectional view showing an example of a display panel cut along A-A' of FIG. 6. FIG. 8 is an exemplary drawing showing a pixel electrode, a light-emitting element, a common electrode, and a third planarization film according to one embodiment. FIG. 8 shows an enlarged cross-sectional view of region B of FIG. 7.

[0083] Referring to FIGS. 7 and 8, a barrier film (BR) may be disposed on a substrate (SUB). The substrate (SUB) may be made of an insulating material such as a polymer resin. For example, the substrate (SUB) may be made of polyimide. The substrate (SUB) may be a flexible substrate capable of bending, folding, rolling, etc.

[0084] The barrier film (BR) is a film for protecting the transistors of the thin-film transistor layer (TFTL) and the light-emitting layer (172) of the light-emitting element layer (EML) from moisture penetrating through a substrate (SUB) that is vulnerable to moisture permeability. The barrier film (BR) may be composed of a plurality of inorganic films that are alternately stacked. For example, the barrier film (BR) may be formed as a multilayer film in which one or more inorganic films selected from a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, and an aluminum oxide layer are alternately stacked.

[0085] A first thin-film transistor (TFT1) may be disposed on the barrier film (BR). The first thin-film transistor (TFT1) may be either the fourth transistor (ST4) or the sixth transistor (ST6) shown in FIG. 5. The first thin-film transistor (TFT1) may include a first active layer (ACT1) and a first gate electrode (G1).

[0086] A first active layer (ACT1) of a first thin-film transistor (TFT1) may be disposed on a barrier film (BR). The first active layer (ACT1) of the first thin-film transistor (TFT1) may include polycrystalline silicon, single-crystal silicon, low-temperature polycrystalline silicon, or amorphous silicon.

[0087] The first active layer (ACT1) may include a first channel region (CHA1), a first source region (S1), and a first drain region (D1). The first channel region (CHA1) may be a region that overlaps with the first gate electrode (G1) in the third direction (DR3), which is the thickness direction of the substrate (SUB). The first source region (S1) may be disposed on one side of the first channel region (CHA1), and the first drain region (D1) may be disposed on the other side of the first channel region (CHA1). The first source region (S1) and the first drain region (D1) may be regions that do not overlap with the first gate electrode (G1) in the third direction (DR3). The first source region (S1) and the first drain region (D1) may be regions that have conductivity by doping ions into a silicon semiconductor or an oxide semiconductor.

[0088] A first gate insulating film (131) may be disposed on the first active layer (ACT1) of the first thin-film transistor (TFT1). The first gate insulating film (131) may be formed of an inorganic film, for example, a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer.

[0089] A first gate metal layer (GTL1) may be disposed on the first gate insulating film (131). The first gate metal layer (GTL1) may include a first gate electrode (G1) and a first capacitor electrode (CAE1) of the first thin-film transistor (TFT1). The first gate electrode (G1) may overlap with the first active layer (ACT1) in the third direction (DR3). Although the first gate electrode (G1) and the first capacitor electrode (CAE1) are shown as being separated from each other in FIG. 7, the first gate electrode (G1) and the first capacitor electrode (CAE1) may be connected to each other. The first gate metal layer (GTL1) may be formed as a single layer or a multilayer made of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof.

[0090] A second gate insulating film (132) may be disposed on the first gate electrode (G1) and the first capacitor electrode (CAE1) of the first thin-film transistor (TFT1). The second gate insulating film (132) may be formed of an inorganic film, for example, a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer.

[0091] A second gate metal layer (GTL2) may be disposed on the second gate insulating film (132). The second gate metal layer (GTL2) may include a second capacitor electrode (CAE2). The second capacitor electrode (CAE2) may overlap with the first capacitor electrode (CAE1) of the first thin-film transistor (TFT1) in the third direction (DR3). Since the second gate insulating film (132) has a predetermined dielectric constant, a capacitor (C1 in FIG. 5) may be formed by the first capacitor electrode (CAE1), the second capacitor electrode (CAE2), and the second gate insulating film (132) disposed between them. The second gate metal layer (GTL2) may be formed as a single layer or a multilayer made of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof.

[0092] A first interlayer insulating film (141) may be disposed on the second capacitor electrode (CAE2). The first interlayer insulating film (141) may be formed of an inorganic film, for example, a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer.

[0093] A second thin-film transistor (TFT2) may be disposed on the first interlayer insulating film (141). The second thin-film transistor (TFT2) may be either the first transistor (ST1) or the third transistor (ST3) shown in FIG. 5. The second thin-film transistor (TFT2) may include a second active layer (ACT2) and a second gate electrode (G2).

[0094] A second active layer (ACT2) of a second thin-film transistor (TFT2) may be disposed on the first interlayer insulating film (141). The second active layer (ACT2) may include an oxide semiconductor. For example, the second active layer (ACT2) may include IGZO (Indium (In), Gallium (Ga), Zinc (Zn) and Oxygen (O)), IGZTO (Indium (In), Gallium (Ga), Zinc (Zn), Tin (Sn) and Oxygen (O)), or IGTO (Indium (In), Gallium (Ga), Tin (Sn) and Oxygen (O)).

[0095] The second active layer (ACT2) may include a second channel region (CHA2), a second source region (S2), and a second drain region (D2). The second channel region (CHA2) may be a region that overlaps with the second gate electrode (G2) in the third direction (DR3). The second source region (S2) may be disposed on one side of the second channel region (CHA2), and the second drain region (D2) may be disposed on the other side of the second channel region (CHA2). The second source region (S2) and the second drain region (D2) may be regions that do not overlap with the second gate electrode (G2) in the third direction (DR3). The second source region (S2) and the second drain region (D2) may be regions that have conductivity by doping ions into an oxide semiconductor.

[0096] A third gate insulating film (133) may be disposed on the second active layer (ACT2) of the second thin-film transistor (TFT2). The third gate insulating film (133) may be formed of an inorganic film, for example, a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer.

[0097] A third gate metal layer (GTL3) may be disposed on the third gate insulating film (133). The third gate metal layer (GTL3) may include a second gate electrode (G2) of the second thin-film transistor (TFT2). The second gate electrode (G2) may overlap with the second active layer (ACT2) in the third direction (DR3). The third gate metal layer (GTL3) may be formed as a single layer or a multilayer composed of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof.

[0098] A second interlayer insulating film (142) may be disposed on the second gate electrode (G2) of the second thin-film transistor (TFT2). The second interlayer insulating film (142) may be formed of an inorganic film, for example, a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer.

[0099] A first data metal layer (DTL1) may be disposed on the second interlayer insulating film (142). The first data metal layer (DTL1) may include a first pixel connection electrode (CE1), a first connection electrode (BE1), and a second connection electrode (BE2). The first pixel connection electrode (CE1) may be connected to a first drain region (D) of the first active layer (ACT1) through a first pixel connection hole (PCT1) penetrating the first gate insulating film (131), the second gate insulating film (132), the first interlayer insulating film (141), the third gate insulating film (133), and the second interlayer insulating film (142). The first connection electrode (BE1) may be connected to a second source region (S2) of the second active layer (ACT2) through a first connection contact hole (BCT1) penetrating the second interlayer insulating film (142). The second connecting electrode (BE2) can be connected to the second drain region (D2) of the second active layer (ACT2) through a second connecting contact hole (BCT2) penetrating the second interlayer insulating film (142). The first data metal layer (DTL1) can be formed as a single layer or a multilayer made of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof. For example, the first data metal layer (DTL1) may include a first layer made of titanium (Ti), a second layer made of aluminum (Al), and a third layer made of titanium (Ti).

[0100] A first organic film (160) for flattening the step difference caused by the first thin-film transistor (TFT1) and the second thin-film transistor (TFT2) may be disposed on the first pixel connection electrode (CE1), the first connection electrode (BE1), and the second connection electrode (BE2). The first organic film (160) may be formed from an organic film such as an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, or a polyimide resin.

[0101] A second data metal layer (DTL2) may be disposed on the first organic film (160). The second data metal layer (DTL2) may include a second pixel connection electrode (CE2). The second pixel connection electrode (CE2) may be connected to the first pixel connection electrode (CE1) through a second pixel connection hole (PCT2) penetrating the first organic film (160). The second data metal layer (DTL2) may be formed as a single layer or a multilayer composed of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof. For example, the second data metal layer (DTL2) may include a first layer made of titanium (Ti), a second layer made of aluminum (Al), and a third layer made of titanium (Ti).

[0102] A second organic film (180) may be disposed on the second pixel connection electrode (CE2). The second organic film (180) may be formed from an organic film such as an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, or a polyimide resin.

[0103] A light-emitting element layer (EML) may be disposed on the second organic film (180). The light-emitting element layer (EML) may include pixel electrodes (PXE), light-emitting elements (LE1, LE2, LE3), a common electrode (CE), and a planarization film (190).

[0104] A pixel electrode layer (PXL) may be disposed on the second organic film (180). The pixel electrode layer (PXL) may include pixel electrodes (PXE). Each of the pixel electrodes (PXE) may be connected to a second pixel connection electrode (PCE2) through a third pixel connection hole (CT3) penetrating the second organic film (180). As a result, each of the pixel electrodes (PXE) may be connected to a first electrode (S1) or a second electrode (D1) of a thin-film transistor (TFT) through a first pixel connection electrode (PCE1) and a second pixel connection electrode (PCE2). Therefore, a pixel voltage or an anode voltage controlled by the thin-film transistor (TFT) may be applied to the pixel electrodes (PXE).

[0105] The pixel electrode layer (PXL) may be formed as a single layer or a multilayer composed of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof. Since the pixel electrodes (PXE) serve to be bonded to the first light-emitting element (LE1), the second light-emitting element (LE2), or the third light-emitting element (LE3), it is desirable to lower the sheet resistance of the pixel electrodes (PXE) in order to reduce the contact resistance between the pixel electrodes (PXE) and the first light-emitting element (LE1), the second light-emitting element (LE2), or the third light-emitting element (LE3). For example, the pixel electrode layer (PXL) may be made of copper (Cu), which has low sheet resistance.

[0106] Each of the first light-emitting element (LE1), the second light-emitting element (LE2), and the third light-emitting element (LE3) can be placed on the pixel electrode (PXE). Each of the first light-emitting element (LE1), the second light-emitting element (LE2), and the third light-emitting element (LE3) is exemplified as a vertical micro LED extending in a third direction (DR3).

[0107] Each of the first light-emitting element (LE1), the second light-emitting element (LE2), and the third light-emitting element (LE3) may be formed of an inorganic material such as GaN. Each of the first light-emitting element (LE1), the second light-emitting element (LE2), and the third light-emitting element (LE3) may have a length in the first direction (DR1), a length in the second direction (DR2), and a length in the third direction (DR3) of each of each of the first light-emitting element (LE1), the second light-emitting element (DR2), and the third light-emitting element (LE3) of each of the third direction (DR3) of approximately 100 μm or less.

[0108] Each of the first light-emitting element (LE1), the second light-emitting element (LE2), and the third light-emitting element (LE3) can be formed by growing on a semiconductor substrate such as a silicon wafer. Each of the first light-emitting element (LE1), the second light-emitting element (LE2), and the third light-emitting element (LE3) can be transferred directly from the silicon wafer onto the pixel electrodes (PXE) of the substrate (SUB). Alternatively, each of the first light-emitting element (LE1), the second light-emitting element (LE2), and the third light-emitting element (LE3) can be transferred onto the pixel electrodes (PXE) of the substrate (SUB) via an electrostatic method using an electrostatic head or a stamping method using an elastic polymer material such as PDMS or silicon as a transfer substrate.

[0109] Each of the first light-emitting element (LE1), the second light-emitting element (LE2), and the third light-emitting element (LE3) may each include a contact electrode (CTE), a first semiconductor layer (SEM1), an electron blocking layer (EBL), an active layer (MQW), a superlattice layer (SLT), and a second semiconductor layer (SEM2).

[0110] A contact electrode (CTE) can be placed on a pixel electrode (PXE). The contact electrode (CTE) and the pixel electrode (PXE) can be bonded to each other through a conductive adhesive member such as an anisotropic conductive film (ACF) or anisotropic conductive paste (ACP). Alternatively, the contact electrode (CTE) and the pixel electrode (PXE) can be bonded to each other through a soldering process. For example, the contact electrode (CTE) may comprise at least one of gold (Au), copper (Cu), aluminum (Al), and tin (Sn).

[0111] The first semiconductor layer (SEM1) can be disposed on the contact electrode (CTE). The first semiconductor layer (SEM1) can be made of GaN doped with a p-type conductivity dopant such as Mg, Zn, Ca, Se, Ba, etc.

[0112] An electron blocking layer (EBL) may be placed on the first semiconductor layer (SEM1). The electron blocking layer (EBL) may be a layer for suppressing or preventing too many electrons from flowing into the active layer (MQW). For example, the electron blocking layer (EBL) may be p-AlGaN doped with p-type Mg. The electron blocking layer (EBL) may be omitted.

[0113] The active layer (MQW) can be placed on the electron blocking layer (EBL). The active layer (MQW) can emit light by the coupling of electron-hole pairs according to an electric signal applied through the first semiconductor layer (SEM1) and the second semiconductor layer (SEM2).

[0114] The active layer (MQW) may include a material having a single or multiple quantum well structure. When the active layer (MQW) includes a material having a multiple quantum well structure, it may have a structure in which multiple well layers and barrier layers are alternately stacked. In this case, the well layers may be formed of InGaN, and the barrier layers may be formed of GaN or AlGaN, but are not limited thereto. Alternatively, the active layer (MQW) may have a structure in which semiconductor materials with large band gap energy and semiconductor materials with small band gap energy are alternately stacked, or it may include different Group 3 to Group 5 semiconductor materials depending on the wavelength of the emitted light.

[0115] When the active layer (MQW) contains InGaN, the color of the emitted light may vary depending on the content of indium (In). For example, as the content of indium (In) increases, the wavelength band of the light emitted by the active layer shifts toward the red wavelength band, and as the content of indium (In) decreases, the wavelength band of the light emitted by the active layer shifts toward the blue wavelength band. Therefore, the content of indium (In) in the active layer (MQW) of the first light-emitting element (LE1) that emits the first light, which is light in the red wavelength band, is higher than the content of indium (In) in the active layer (MQW) of the second light-emitting element (LE2), and the content of indium (In) in the active layer (MQW) of the second light-emitting element (LE2) may be higher than the content of indium (In) in the active layer (MQW) of the third light-emitting element (LE3). For example, the indium (In) content of the active layer (MQW) of the first light-emitting element (LE1) may be approximately 30 wt% to 40 wt%, the indium (In) content of the active layer (MQW) of the second light-emitting element (LE2) may be approximately 20 wt% to 30 wt%, and the indium (In) content of the third light-emitting element (LE3) may be approximately 10 wt% to 20 wt%. In this case, the active layer (MQW) of the first light-emitting element (LE1) may emit a first light, the active layer (MQW) of the second light-emitting element (LE2) may emit a second light, and the active layer (MQW) of the third light-emitting element (LE3) may emit a third light.

[0116] A superlattice layer (SLT) may be disposed on an active layer (MQW). The superlattice layer (SLT) may be a layer for relieving stress between the second semiconductor layer (SEM2) and the active layer (MQW). For example, the superlattice layer (SLT) may be formed of InGaN or GaN. The superlattice layer (SLT) may be omitted.

[0117] The second semiconductor layer (SEM2) may be disposed on the superlattice layer (SLT). The second semiconductor layer (SEM2) may be doped with a second conductivity type dopant such as Si, Ge, Sn, etc. For example, the second semiconductor layer (SEM2) may be n-GaN doped with n-type Si.

[0118] A planarization film (190) may be disposed on the side of each of the first light-emitting elements (LE1), the second light-emitting elements (LE2), and the third light-emitting elements (LE3). The planarization film (190) may be a layer for flattening the step difference caused by the first light-emitting elements (LE1), the second light-emitting elements (LE2), and the third light-emitting elements (LE3). The upper surfaces of the first light-emitting elements (LE1), the upper surfaces of the second light-emitting elements (LE2), the upper surfaces of the third light-emitting elements (LE3), and the upper surface of the planarization film (190) may be flatly connected. The planarization film (190) may be formed from an organic film such as an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, or a polyimide resin.

[0119] A common electrode (CE) may be disposed on the upper surfaces of the first light-emitting elements (LE1), the upper surfaces of the second light-emitting elements (LE2), the upper surfaces of the third light-emitting elements (LE3), and the upper surface of the planarization film (190). The common electrode (CE) may be a common layer formed in common on the first subpixel (SPX1), the second subpixel (SPX2), and the third subpixel (SPX3). The common electrode (CE) may be made of a transparent conductive material (TCO) such as Indium Tin Oxide (ITO) and Indium Zinc Oxide (IZO) that can transmit light.

[0120] As shown in FIGS. 7 and 8, since the pixel electrodes (PXE) serve to be joined to the first light-emitting element (LE1), the second light-emitting element (LE2), or the third light-emitting element (LE3), if they are made of copper (Cu) which has low sheet resistance, the contact resistance between the pixel electrodes (PXE) and the first light-emitting element (LE1), the second light-emitting element (LE2), or the third light-emitting element (LE3) can be reduced.

[0121] FIG. 9 is a layout diagram showing the first power wiring and the second power wiring of the non-display area of ​​a display panel according to one embodiment.

[0122] Referring to FIG. 9, a first power line (VDL), a second power line (VSL), first power connection lines (VDCL), second power connection lines (VSCL), a first power pad line (VDPL), and a second power pad line (VSPL) are illustrated.

[0123] The first power wiring (VDL) may be placed in the non-display area (NDA) and the connection area (CA). The first power wiring (VDL) may be placed in the non-display area (NDA) located on the left, bottom, and right sides of the display panel (100). The first power wiring (VDL) may extend in the first direction (DR1) from the non-display area (NDA) located on the bottom side of the display panel (100). The first power wiring (VDL) may extend in the second direction (DR2) from the connection area (CA). The first power wiring (VDL) may be bent from the second direction (DR2) to the first direction (DR1) from the non-display area (NDA) located on the bottom side of the display panel (100).

[0124] Additionally, the first power wiring (VDL) may be placed in the lower side, left side, and non-display area (NDA) of the corner where the lower side and left side meet of the display panel (100). Additionally, the first power wiring (VDL) may be placed in the lower side, right side, and non-display area (NDA) of the corner where the lower side and right side meet of the display panel (100). Additionally, the first power wiring (VDL) may be placed in the upper side, the corner where the upper side and left side meet, and the non-display area (NDA) of the corner where the upper side and right side meet of the display panel (100).

[0125] The second power line (VSL) may be placed in the non-display area (NDA) and the connection area (CA). The second power line (VSL) may be placed in the non-display area (NDA) located on the left, bottom, and right sides of the display panel (100). The second power line (VSL) may extend in the first direction (DR1) from the non-display area (NDA) located on the bottom side of the display panel (100). The second power line (VSL) may extend in the second direction (DR2) from the connection area (CA). The second power line (VSL) may be bent from the second direction (DR2) to the first direction (DR1) from the non-display area (NDA) located on the bottom side of the display panel (100).

[0126] Additionally, the second power line (VSL) may be placed in the lower side, left side, and non-display area (NDA) of the corner where the lower side and left side meet of the display panel (100). Additionally, the second power line (VSL) may be placed in the lower side, right side, and non-display area (NDA) of the corner where the lower side and right side meet of the display panel (100). Additionally, the second power line (VSL) may be placed in the upper side, the corner where the upper side and left side meet, and the non-display area (NDA) of the corner where the upper side and right side meet of the display panel (100).

[0127] In the non-display area (NDA), the second power line (VSL) may be positioned adjacent to the edge of the display panel (100) relative to the first power line (VDL). In the non-display area (NDA), the width of the second power line (VSL) may be wider than the width of the first power line (VDL).

[0128] The first power connection wires (VDCL) can be placed in the bending area (BA). Each of the first power connection wires (VDCL) can be connected to the first power wire (VDL) in the connection area (CA). Each of the first power connection wires (VDCL) can be connected to the first power pad wire (VDPL) in the pad area (PA). That is, to prevent cracking of the wires during bending in the bending area (BA), the first power wire (VDL) and the first power pad wire (VDPL) can be connected to the first power connection wires (VDCL) having a thin width in the bending area (BA).

[0129] The second power connection wires (VSCL) can be placed in the bending area (BA). Each of the second power connection wires (VSCL) can be connected to the second power wire (VSL) in the connection area (CA). Each of the second power connection wires (VSCL) can be connected to the second power pad wire (VSPL) in the pad area (PA). That is, to prevent cracking of the wires during bending in the bending area (BA), the second power wire (VSL) and the second power pad wire (VSPL) can be connected to the second power connection wires (VSCL) having a thin width in the bending area (BA).

[0130] The first power pad wiring (VDPL) may be placed in the pad area (PA). The first power pad wiring (VDPL) may be connected to the pads (PDs) at the lower edge of the pad area (PA).

[0131] The second power pad wiring (VSPL) may be placed in the pad area (PA). The second power pad wiring (VSPL) may be connected to the pads (PDs) at the lower edge of the pad area (PA). The second power pad wiring (VSPL) may be placed adjacent to the left edge of the display panel (100) relative to the first power pad wiring (VDPL). The second power pad wiring (VSPL) may be placed to bypass the display driving circuit (200).

[0132] Figure 10 is a layout diagram showing area B of Figure 9 in detail.

[0133] Referring to FIG. 10, scan fan-out lines (SFLs), data fan-out lines (DFLs), a first power line (VSL), and a second power line (VDL) may be placed in a connection area (CA). Scan connection lines (SCLs), data connection lines (DCLs), a first power connection line (VDCL), and a second power connection line (VSCL) may be placed in a bending area (BA). Scan pad lines (SPLs), data pad lines (DPLs), a first power pad line (VSPL), and a second power pad line (VDPL) may be placed in a pad area (PA).

[0134] The first power wiring (VDL) may include first to third sub-power wirings (VDL1, VDL2, VDL3). The first to third sub-power wirings (VDL1, VDL2, VDL3) may overlap each other in a third direction (DR3). The second sub-power wiring (VDL2) may be connected to the first sub-power wiring (VDL1) through a first power contact hole (VPH1). The third sub-power wiring (VDL3) may be placed on the second sub-power wiring (VDL2).

[0135] The first power pad wiring (VDPL) may include first to third sub-power pad wirings (VDPL1, VDPL2, VDPL3). The first to third sub-power pad wirings (VDPL1, VDPL2, VDPL3) may overlap each other in a third direction (DR3). The second sub-power pad wiring (VDPL2) may be connected to the first sub-power pad wiring (VDPL1) through a first pad contact hole (VPT1). The third sub-power pad wiring (VDPL3) may be placed on the second sub-power pad wiring (VDPL2).

[0136] The first power connection wires (VDCL) may extend from one end of the second sub-power wire (VDL2) of the first power wire (VDL) in the connection area (CA). The first power connection wires (VDCL) may extend from one end of the second sub-power pad wire (VDPL2) of the first power pad wire (VDPL) in the pad area (PA). That is, the first power connection wires (VDCL), the second sub-power wire (VDL2), and the second sub-power pad wire (VDPL2) may be formed integrally.

[0137] The second power line (VDL) may include fourth to sixth sub-power lines (VSL1, VSL2, VSL3). The fourth to sixth sub-power lines (VSL1, VSL2, VSL3) may overlap each other in the third direction (DR3). The fifth sub-power line (VSL2) may be connected to the fourth sub-power line (VSL1) through the second power contact hole (VPH2). The sixth sub-power line (VSL3) may be placed on the fifth sub-power line (VSL2).

[0138] The second power pad wiring (VSPL) may include fourth to sixth sub-power pad wirings (VSPL1, VSPL2, VSPL3). The fourth to sixth sub-power pad wirings (VSPL1, VSPL2, VSPL3) may overlap each other in the third direction (DR3). The fifth sub-power pad wiring (VSPL2) may be connected to the fourth sub-power pad wiring (VSPL1) through the first pad contact hole (VPT1). The sixth sub-power pad wiring (VSPL3) may be placed on the fifth sub-power pad wiring (VSPL2).

[0139] The second power connection wires (VSCL) may extend from one end of the fifth sub-power wire (VSL2) of the second power wire (VSL) in the connection area (CA). The second power connection wires (VSCL) may extend from one end of the fifth sub-power pad wire (VSPL2) of the second power pad wire (VSPL) in the pad area (PA). That is, the second power connection wires (VSCL), the fifth sub-power wire (VSL2), and the second sub-power pad wire (VSPL2) may be formed integrally.

[0140] Scan fan-out lines (SFLs) may overlap with the second power line (VSL) in the connection area (CA). Data fan-out lines (DFLs) may not overlap with the first power line (VDL) and the second power line (VSL) in the connection area (CA).

[0141] Each of the scan fan-out wirings (SFL) may include a first scan fan-out wiring (SFL1) and a second scan fan-out wiring (SFL2) that overlap each other in a third direction (Z-axis direction). The second scan fan-out wiring (SFL2) may be connected to the first scan fan-out wiring (SFL1) through a first scan connection hole (SCH1).

[0142] Each of the scan pad wirings (SPL) may include a first scan pad wiring (SPL1) and a second scan pad wiring (SPL2) that overlap each other in a third direction (Z-axis direction). The second scan pad wiring (SPL2) may be connected to the second scan fan-out wiring (SFL2) through a second scan connection hole (SCH2).

[0143] The scan connection wiring (SCL) can be connected to the first scan fan-out wiring (SFL1) through the third scan connection hole (SCH3) in the connection area (CA). The scan connection wiring (SCL) can be connected to the first scan pad wiring (SPL1) through the fourth scan connection hole (SCH4) in the pad area (PA).

[0144] The data connection wiring (DCL) can be connected to the data fan-out wiring (DFL) through the first data connection hole (DCH1) in the connection area (CA). The data connection wiring (DCL) can be connected to the data pad wiring (DPL) through the second data connection hole (DCH2) in the pad area (PA).

[0145] FIG. 11 is a cross-sectional view showing an example of a display panel cut along B-B' of FIG. 9.

[0146] Referring to FIG. 11, the first sub-power wiring (VDL1) of the first power wiring (VDL) is placed on the second interlayer insulating film (142), the second sub-power wiring (VDL2) is placed on the first organic film (160), and the third sub-power wiring (VDL3) can be placed on the second sub-power wiring (VDL2). The second sub-power wiring (VDL2) can be connected to the first sub-power wiring (VDL1) through a first power hole (VPH1) penetrating the first organic film (160). The first sub-power wiring (VDL1), the second sub-power wiring (VDL2), and the third sub-power wiring (VDL3) can overlap each other in a third direction (DR3).

[0147] The first sub-power pad wiring (VDPL1) of the first power pad wiring (VDPL) is disposed on the second interlayer insulating film (142), the second sub-power pad wiring (VDPL2) is disposed on the first organic film (160), and the third sub-power pad wiring (VDPL3) can be disposed on the second sub-power pad wiring (VDPL2). The second sub-power pad wiring (VDPL2) can be connected to the first sub-power pad wiring (VDPL1) through a third power hole (VPH3) penetrating the first organic film (160). The first sub-power pad wiring (VDPL1), the second sub-power pad wiring (VDPL2), and the third sub-power wiring (VDPL3) can overlap each other in a third direction (DR3).

[0148] The first power connection wiring (VDCL) can be placed on the first organic film (160). The first power connection wiring (VDCL) can be formed integrally with the second sub-power wiring (VDL2) and the second sub-power pad wiring (VDPL2).

[0149] That is, the first data metal layer (DTL1) may include a first sub-power wiring (VDL1) and a first sub-power pad wiring (VDPL1). The second data metal layer (DTL2) may include a second sub-power wiring (VDL2), a second sub-power pad wiring (VDPL2), and a first power connection wiring (VDCL). The pixel electrode layer (PXL) may include a third sub-power wiring (VDL3) and a third sub-power pad wiring (VDPL3).

[0150] Since the micro-light-emitting element of the micro-light-emitting diode display device is made of an inorganic material, there is no need for a sealing film to encapsulate the organic light-emitting layer in the organic light-emitting diode display device. Therefore, in the micro-light-emitting diode display device, there is no need for a dam to prevent the organic film of the sealing film from overflowing. As a result, in the micro-light-emitting diode display device, the second organic film (180) may be placed in the display area (DA), but the second organic film (180) may not be placed in the non-display area (NDA). Accordingly, the third sub-power wiring (VDL3) is placed on the second sub-power wiring (VDL2), and the upper surface of the second sub-power wiring (VDL2) and the lower surface of the third sub-power wiring (VDL3) can come into contact with each other. Additionally, the third sub-power pad wiring (VDPL3) is placed on the second sub-power pad wiring (VDPL2), and the upper surface of the second sub-power pad wiring (VDPL2) and the lower surface of the third sub-power pad wiring (VDPL3) can come into contact with each other. Additionally, since the flattening film (190) is placed in both the display area (DA) and the non-display area (NDA), it can be placed on the third sub-power wiring (VDL3) and the third sub-power pad wiring (VDPL3). The flattening film (190) can be removed from the bending area (BA).

[0151] As shown in FIG. 11, the area of ​​the first power wiring (VDL) is increased by including a first sub-power wiring (VDL1), a second sub-power wiring (VDL2), and a third sub-power wiring (VDL3) that are respectively placed in three layers. Additionally, the third sub-power wiring (VDL3) is made of a metal material with low sheet resistance, such as copper (Cu). Therefore, the resistance of the first power wiring (VDL) can be lowered, so the width of the first power wiring (VDL) placed in the non-display area (NDA) can be reduced, and as a result, the width of the non-display area (NDA) can be reduced. Furthermore, the ripple caused by the first power wiring (VDL) being affected by voltage changes of other wiring that overlap with it can be minimized.

[0152] In addition, the first power pad wiring (VDPL) includes a first sub-power pad wiring (VDPL1), a second sub-power pad wiring (VDPL2), and a third sub-power pad wiring (VDPL3) that are respectively placed in three layers, thereby increasing the area of ​​the first power pad wiring (VDPL). Furthermore, the third sub-power pad wiring (VDPL3) can be made of a metal material with low sheet resistance, such as copper (Cu). Therefore, since the resistance of the first power pad wiring (VDPL) can be lowered, the width of the first power pad wiring (VDPL) placed in the non-display area (NDA) can be reduced, and consequently, the width of the non-display area (NDA) can be reduced. In addition, the ripple caused by the first power pad wiring (VDPL) being affected by voltage changes of other wiring that overlap with it can be minimized.

[0153] FIG. 12 is a cross-sectional view showing an example of a display panel cut along C-C' of FIG. 9.

[0154] Referring to FIG. 12, the fourth sub-power wiring (VSL1) of the second power wiring (VSL) is placed on the second interlayer insulating film (142), the fifth sub-power wiring (VSL2) is placed on the first organic film (160), and the sixth sub-power wiring (VSL3) can be placed on the fifth sub-power wiring (VSL2). The fifth sub-power wiring (VSL2) can be connected to the fourth sub-power wiring (VSL1) through a second power hole (VPH2) penetrating the first organic film (160). The fourth sub-power wiring (VSL1), the fifth sub-power wiring (VSL2), and the sixth sub-power wiring (VSL3) can overlap each other in a third direction (DR3).

[0155] The fourth sub-power pad wiring (VSPL1) of the second power pad wiring (VSPL) is disposed on the second interlayer insulating film (142), the fifth sub-power pad wiring (VSPL2) is disposed on the first organic film (160), and the sixth sub-power pad wiring (VSPL3) can be disposed on the fifth sub-power pad wiring (VSPL2). The fifth sub-power pad wiring (VSPL2) can be connected to the fourth sub-power pad wiring (VSPL1) through a fourth power hole (VPH4) penetrating the first organic film (160). The fourth sub-power pad wiring (VSPL1), the second sub-power pad wiring (VSPL2), and the third sub-power wiring (VSPL3) can overlap each other in the third direction (DR3).

[0156] The second power connection wiring (VSCL) can be placed on the first organic film (160). The second power connection wiring (VSCL) can be formed integrally with the second sub-power wiring (VDL2) and the second sub-power pad wiring (VDPL2).

[0157] That is, the first data metal layer (DTL1) may include a fourth sub-power wiring (VSL1) and a fourth sub-power pad wiring (VSPL1). The second data metal layer (DTL2) may include a fifth sub-power wiring (VSL2), a fifth sub-power pad wiring (VSPL2), and a second power connection wiring (VSCL). The pixel electrode layer (PXL) may include a sixth sub-power wiring (VSL3) and a sixth sub-power pad wiring (VSPL3).

[0158] In a micro light-emitting diode display device, a second organic film (180) is disposed in the display area (DA), but the second organic film (180) may not be disposed in the non-display area (NDA). Therefore, the sixth sub-power wiring (VSL3) is disposed on the fifth sub-power wiring (VSL2), and the upper surface of the fifth sub-power wiring (VSL2) and the lower surface of the sixth sub-power wiring (VSL3) can come into contact with each other. Additionally, the sixth sub-power pad wiring (VSPL3) is disposed on the fifth sub-power pad wiring (VSPL2), and the upper surface of the fifth sub-power pad wiring (VSPL2) and the lower surface of the sixth sub-power pad wiring (VSPL3) can come into contact with each other. Furthermore, since the flattening film (190) is disposed in both the display area (DA) and the non-display area (NDA), it can be disposed on the sixth sub-power wiring (VSL3) and the sixth sub-power pad wiring (VSPL3). The flattening film (190) can be removed from the bending region (BA).

[0159] As shown in FIG. 12, the area of ​​the second power wiring (VSL) is increased by including a fourth sub-power wiring (VSL1), a fifth sub-power wiring (VSL2), and a sixth sub-power wiring (VSL3) that are respectively placed in three layers. The sixth sub-power wiring (VSL3) is made of a metal material with low sheet resistance, for example, copper (Cu). Therefore, the resistance of the second power wiring (VSL) can be lowered, so the width of the second power wiring (VSL) placed in the non-display area (NDA) can be reduced, and as a result, the width of the non-display area (NDA) can be reduced. In addition, the ripple caused by the second power wiring (VSL) being affected by voltage changes of other wiring that overlap with it can be minimized.

[0160] In addition, the second power pad wiring (VSPL) includes a fourth sub-power pad wiring (VSPL1), a fifth sub-power pad wiring (VSPL2), and a sixth sub-power pad wiring (VSPL3) that are respectively placed in three layers, thereby increasing the area of ​​the second power pad wiring (VSPL), and the sixth sub-power pad wiring (VSPL3) may be made of a metal material with low sheet resistance, such as copper (Cu). Therefore, since the resistance of the second power pad wiring (VSPL) can be lowered, the width of the second power pad wiring (VSPL) placed in the non-display area (NDA) can be reduced, and as a result, the width of the non-display area (NDA) can be reduced. In addition, the ripple caused by the second power pad wiring (VSPL) being affected by voltage changes of other wiring that overlap with it can be minimized.

[0161] FIG. 13 is a cross-sectional view showing an example of a pad of the display panel of FIG. 8.

[0162] Referring to FIG. 13, a pad (PD) can be disposed on the first organic film (160). That is, the second data metal layer (DTL2) can include the pad (PD).

[0163] A pad protection electrode (PPE) can be placed on the first organic film (160). The pad protection electrode (PPE) can be connected to the pad (PD) through a pad contact hole (PDH) that penetrates the first organic film (160).

[0164] The pad protection electrode (PPE) is a layer designed to prevent the pad (PD) exposed by the pad contact hole (PDH) from being etched or removed by the wet etching solution during the wet etching process for forming pixel electrodes (PXE). Therefore, the pad protection electrode (PPE) may be made of a material that does not react with the wet etching solution during the wet etching process for forming pixel electrodes (PXE). For example, the pad protection electrode (PPE) may be a transparent conductive oxide such as Indium Tin Oxide (ITO). In this case, the pad protection electrode (PPE) may be made of poly-ITO, but may also be made of amorphous ITO if it does not react with the wet etching solution.

[0165] FIG. 14 is a layout diagram showing the first power wiring and the second power wiring of the non-display area of ​​a display panel according to another embodiment.

[0166] The embodiment of FIG. 14 differs from the embodiment of FIG. 9 in that, in the non-display area (NDA), the first power line (VDL) includes a first bottleneck area (VDL_BN) and the second power line (VSL) includes a second bottleneck area (VSL_BN). FIG. 14 will be explained primarily in terms of the differences from the embodiment of FIG. 9.

[0167] Referring to FIG. 14, according to the design of the first power line (VDL) and the second power line (VSL), the first power line (VDL) may include a first bottleneck section (VDL_BN) in which the width of the first power line (VDL) is reduced, and the second power line (VSL) may include a second bottleneck section (VSL_BN) in which the width of the second power line (VSL) is reduced. The first bottleneck section (VDL_BN) may be an area in the non-display area (NDA) where the first power line (VDL) is bent from the first direction (DR1) to the second direction (DR2). The second bottleneck section (VSL_BN) may be an area in the non-display area (NDA) where the second power line (VSL) is bent from the first direction (DR1) to the second direction (DR2).

[0168] FIG. 15 is a cross-sectional view showing an example of a display panel cut along H-H' of FIG. 14. FIG. 16 is a cross-sectional view showing an example of a display panel cut along I-I' of FIG. 14.

[0169] Referring to FIGS. 15 and 16, a first power line (VDL) according to one embodiment includes first to third sub-power lines (VDL1 to VDL3) to prevent a decrease in resistance as the width of the first power line (VDL) decreases in a first bottleneck section (VDL_BN), and may include first and second sub-power lines (VDL1, VDL2) in a region other than the first bottleneck section (VDL_BN). Since the first to third sub-power lines (VDL1 to VDL3) are substantially the same as those described in conjunction with FIG. 11, a description thereof is omitted.

[0170] Additionally, according to one embodiment, the second power line (VSL) includes fourth to sixth sub-power lines (VSL1 to VSL3) to prevent a decrease in resistance as the width of the second power line (VSL) decreases in the second bottleneck section (VSL_BN), and may include fourth and fifth sub-power lines (VSL1, VSL2) in areas other than the second bottleneck section (VSL_BN). Since the fourth to sixth sub-power lines (VSL1 to VSL3) are substantially the same as those described in conjunction with FIG. 12, a description thereof is omitted.

[0171] FIG. 17 is a layout diagram showing an example of a first scan driving unit in a non-display area of ​​a display panel according to one embodiment.

[0172] Referring to FIG. 17, the first scan drive unit (SDC1) may include a plurality of stages (STAk to STAk+3). FIG. 17 illustrates the k to k+3 stages (STAk to STAk+3) connected to the k to k+3 write scan lines (GWLk to GWLk+3).

[0173] The k to k+3 stages (STAk to STAk+3) are dependently connected to sequentially output write scan signals to the k to k+3 write scan lines (GWLk to GWLk+3). Each of the k to k+3 stages (STAk to STAk+3) can output a write scan signal according to the scan clock signals input from the scan clock lines (CKL1, CKL2).

[0174] Each of the first scan clock wiring (CKL1) and the second scan clock wiring (CKL2) may include a first sub-clock wiring (SCKL1) and a second sub-clock wiring (SCKL2). The first sub-clock wiring (SCKL1) and the second sub-clock wiring (SCKL2) may overlap each other in a third direction (DR3). The second sub-clock wiring (SCKL2) may be connected to the first sub-clock wiring (SCKL1) through a connection hole (CCT). The first scan clock wiring (CKL1) and the second scan clock wiring (CKL2) may be some of the scan fan-out wirings (SFL) shown in FIG. 10.

[0175] Each of the k to k+3 stages (STAk to STAk+3) may be alternately connected to the first scan clock wiring (CKL1) and the second scan clock wiring (CKL2) through the first clock connection wiring (CKC1) and the second clock connection wiring (CKC2). For example, the k stage (STAk) may be connected to the first scan clock wiring (CKL1) through the first clock connection wiring (CKC1) and to the second scan clock wiring (CKL2) through the second clock connection wiring (CKC2). The k+1 stage (STAk+1) may be connected to the second scan clock wiring (CKL2) through the first clock connection wiring (CKC1) and to the first scan clock wiring (CKL1) through the second clock connection wiring (CKC2). The k+2 stage (STAk+2) can be connected to the first scan clock wiring (CKL1) through the first clock connection wiring (CKC1) and to the second scan clock wiring (CKL2) through the second clock connection wiring (CKC2). The k+3 stage (STAk+3) can be connected to the second scan clock wiring (CKL2) through the first clock connection wiring (CKC1) and to the first scan clock wiring (CKL1) through the second clock connection wiring (CKC2).

[0176] The first clock connection wiring (CKC1) can be connected to the first scan clock wiring (CKL1) or the second scan clock wiring (CKL2) through the first clock connection hole (CKCT1). The second clock connection wiring (CKC2) can be connected to the first scan clock wiring (CKL1) or the second scan clock wiring (CKL2) through the second clock connection hole (CKCT2).

[0177] FIG. 18 is a cross-sectional view showing an example of a display panel cut along J-J' of FIG. 17.

[0178] Referring to FIG. 18, the first sub-clock wiring (SCKL1) may be placed on the second interlayer insulating film (142), and the second sub-clock wiring (SCKL2) may be placed on the first organic film (160). The second sub-clock wiring (SCKL2) may be connected to the first sub-clock wiring (SCKL1) through a connection hole (CCT) penetrating the first organic film (160).

[0179] A first clock connection wire (CKC1) may be placed on a first gate insulating film (131). A first sub-clock wire (SCKL1) may be connected to the first clock connection wire (CKC1) through a first clock connection hole (CKCT1) penetrating a second gate insulating film (132), a first interlayer insulating film (141), a third gate insulating film (133), and a second interlayer insulating film (142).

[0180] The first gate metal layer (GTL1) may include a first clock connection wiring (CKC1). The first data metal layer (DTL1) may include a first sub-clock wiring (SCKL1). The pixel electrode layer (PXL) may include a second sub-clock wiring (SCKL2).

[0181] In a micro light-emitting diode display device, a second organic film (180) is disposed in the display area (DA), but the second organic film (180) may not be disposed in the non-display area (NDA). Accordingly, the second sub-clock wiring (SCKL2) may be disposed on the first organic film (160). Additionally, since the planarization film (190) is disposed in both the display area (DA) and the non-display area (NDA), it may be disposed on the second sub-clock wiring (SCKL2).

[0182] As shown in FIG. 18, the first clock connection wiring (CKC1) and the second clock connection wiring (CKC2) each include a first sub-clock wiring (SCKL1) and a second sub-clock wiring (SCKL2) that are respectively placed in two layers, thereby increasing the area of ​​each of the first clock connection wiring (CKC1) and the second clock connection wiring (CKC2). Additionally, the second sub-power wiring (SCKL2) is made of a metal material with low sheet resistance, for example, copper (Cu). Therefore, since the resistance of each of the first scan clock wiring (CKL1) and the second scan clock wiring (CKL2) can be lowered, the load of the write scan signal output to the write scan wirings (GWLk~GWLk+3), i.e., the RC delay, can be reduced.

[0183] FIG. 19 is a layout diagram showing an example of a first scan driving unit in a non-display area of ​​a display panel according to one embodiment. FIG. 20 is a cross-sectional view showing another example of a display panel cut along K-K' of FIG. 19.

[0184] The embodiments of FIGS. 19 and 20 differ from the embodiments of FIGS. 17 and 18 in that the first scan clock wiring (CKL1) and the second scan clock wiring (CKL2) each include the first to third sub-clock wirings (SCKL1, SCKL2, SCKL3).

[0185] Referring to FIGS. 19 and 20, the first scan clock wiring (CKL1) and the second scan clock wiring (CKL2) may each include a first sub-clock wiring (SCKL1), a second sub-clock wiring (SCKL2), and a third sub-clock wiring (SCKL3). The first sub-clock wiring (SCKL1), the second sub-clock wiring (SCKL2), and the third sub-clock wiring (SCKL3) may overlap each other in a third direction (DR3). The second sub-clock wiring (SCKL2) may be connected to the first sub-clock wiring (SCKL1) through a connection hole (CCT). The third sub-clock wiring (SCKL3) may be placed on the second sub-clock wiring (SCKL1).

[0186] A first sub-clock wiring (SCKL1) is disposed on a second interlayer insulating film (142), a second sub-clock wiring (SCKL2) is disposed on a first organic film (160), and a third sub-clock wiring (SCKL3) can be disposed on the second sub-clock wiring (SCKL2). The second sub-clock wiring (SCKL2) can be connected to the first sub-clock wiring (SCKL1) through a connection hole (CCT) penetrating the first organic film (160).

[0187] The first data metal layer (DTL1) may include a first sub-clock wiring (SCKL1). The second data metal layer (DTL2) may include a second sub-clock wiring (SCKL2). The pixel electrode layer (PXL) may include a third sub-clock wiring (SCKL3).

[0188] In a micro light-emitting diode display device, a second organic film (180) is disposed in the display area (DA), but the second organic film (180) may not be disposed in the non-display area (NDA). Accordingly, the third sub-clock wiring (SCKL3) is disposed on the first organic film (160), and the upper surface of the second sub-clock wiring (SCKL2) and the lower surface of the third sub-clock wiring (SCKL3) may come into contact with each other. Additionally, since the planarization film (190) is disposed in both the display area (DA) and the non-display area (NDA), it may be disposed on the third sub-clock wiring (SCKL3).

[0189] As shown in FIGS. 19 and 20, the first clock connection wiring (CKC1) and the second clock connection wiring (CKC2) each include a first sub-clock wiring (SCKL1), a second sub-clock wiring (SCKL2), and a third sub-clock wiring (SCKL3) which are respectively placed in three layers, thereby increasing the area of ​​each of the first clock connection wiring (CKC1) and the second clock connection wiring (CKC2). Additionally, the third sub-clock wiring (SCKL3) is made of a metal material with low sheet resistance, for example, copper (Cu). Therefore, since the resistance of each of the first scan clock wiring (CKL1) and the second scan clock wiring (CKL2) can be lowered, the load of the write scan signal output to the write scan wirings (GWLk~GWLk+3), i.e., the RC delay, can be reduced.

[0190] FIG. 21 is an example drawing showing a smart device including a display device according to one embodiment.

[0191] Referring to FIG. 21, a display device (10_2) according to one embodiment can be applied to a smart watch (2), which is one of the smart devices. FIG. 21 illustrates that the smart watch (2) has a rectangular shape on a flat surface, excluding the wristwatch strap. That is, the flat shape of the watch display portion of the smart watch (2) can follow the flat shape of the display device (10_2).

[0192] FIG. 22 is an exemplary drawing showing a virtual reality device including a display device according to one embodiment. FIG. 22 shows a virtual reality device (1) to which a display device (10_1) according to one embodiment is applied.

[0193] Referring to FIG. 22, a virtual reality device (1) according to one embodiment may be a device in the form of glasses. A virtual reality device (1) according to one embodiment may have a display device (10_1), a left eye lens (10a), a right eye lens (10b), a support frame (20), eyeglass frame legs (30a, 30b), a reflective member (40), and a display device housing (50).

[0194] Although FIG. 22 illustrates a virtual reality device (1) including eyeglass frame temples (30a, 30b), the virtual reality device (1) according to one embodiment may be applied to a head-mounted display that includes a head-mounting band that can be mounted on the head instead of the eyeglass frame temples (30a, 30b). That is, the virtual reality device (1) according to one embodiment is not limited to that shown in FIG. 22 and can be applied in various forms to various other electronic devices.

[0195] The display device housing (50) may include a display device (10_1) and a reflective member (40). An image displayed on the display device (10_1) may be reflected from the reflective member (40) and provided to the user's right eye through the right eye lens (10b). As a result, the user can view the virtual reality image displayed on the display device (10_1) through their right eye.

[0196] FIG. 22 illustrates that the display device housing (50) is positioned at the right end of the support frame (20), but the embodiments of this specification are not limited thereto. For example, the display device housing (50) may be positioned at the left end of the support frame (20), in which case the image displayed on the display device (10_1) may be reflected from the reflective member (40) and provided to the user's left eye through the left eye lens (10a). As a result, the user can view the virtual reality image displayed on the display device (10_1) through the left eye. Alternatively, the display device housing (50) may be positioned at both the left end and the right end of the support frame (20), in which case the user can view the virtual reality image displayed on the display device (10_1) through both the left eye and the right eye.

[0197] FIG. 23 is an exemplary drawing showing an automobile instrument panel and a center fascia including a display device according to one embodiment. FIG. 23 shows an automobile with display devices (10_a, 10_b, 10_c, 10_d, 10_e) according to one embodiment applied.

[0198] Referring to FIG. 23, display devices (10_a, 10_b, 10_c) according to one embodiment may be applied to an instrument panel of a vehicle, to a center fascia of a vehicle, or to a Center Information Display (CID) placed on the dashboard of a vehicle. Additionally, display devices (10_d, 10_e) according to one embodiment may be applied to a room mirror display that replaces a side mirror of a vehicle.

[0199] FIG. 24 is an exemplary drawing showing a transparent display device including a display device according to one embodiment.

[0200] Referring to FIG. 24, a display device (10_3) according to one embodiment can be applied to a transparent display device. The transparent display device can display an image (IM) and transmit light simultaneously. Therefore, a user located in front of the transparent display device can not only view the image (IM) displayed on the display device (10_3) but also see an object (RS) or background located on the back of the transparent display device. When the display device (10_3) is applied to a transparent display device, the substrate (SUB) of the display device (10_3) may include a light-transmitting portion capable of transmitting light or be formed of a material capable of transmitting light.

[0201] FIG. 25 is a perspective view showing a display device according to another embodiment.

[0202] The embodiment of FIG. 25 differs from the embodiment of FIG. 1 only in that the display area (DA) and the main area (MA) of the display panel (100) have a planar circular shape, so the description of the embodiment of FIG. 25 is omitted.

[0203] FIG. 26 is an example drawing showing a smart device including a display device according to another embodiment.

[0204] Referring to FIG. 26, the smart watch (2) is exemplified as having a circular shape on a flat surface, excluding the wrist strap. That is, the flat shape of the watch display portion of the smart watch (2) can follow the flat shape of the display device (10_2).

[0205] Although embodiments of the present invention have been described above with reference to the attached drawings, those skilled in the art will understand that the present invention may be implemented in other specific forms without changing the technical concept or essential features thereof. Therefore, the embodiments described above should be understood as illustrative in all respects and not restrictive. Explanation of the symbols

[0206] 10: Display device 100: Display panel 200: Display driving circuit 300: Circuit board

Claims

Claim 1 A display device comprising: a substrate; an insulating film disposed on the substrate; a first sub-power wiring disposed on the insulating film to which a first power supply voltage is applied; a first organic film disposed on the first sub-power wiring; a second sub-power wiring disposed on the first organic film and connected to the first sub-power wiring through a first power hole penetrating the first organic film; a third sub-power wiring disposed on the second sub-power wiring; a pixel electrode disposed on the first organic film; a light-emitting element disposed on the pixel electrode; a planarization film disposed on the side of the light-emitting element; and a common electrode disposed on the light-emitting element and the planarization film, wherein the planarization film is disposed on the third sub-power wiring and is in direct contact with the third sub-power wiring. Claim 2 In claim 1, the pixel electrode and the third sub-power wiring are made of the same material in the display device. Claim 3 A display device according to claim 1, wherein the pixel electrode and the third sub-power wiring are made of a material different from the first sub-power wiring, and the pixel electrode and the third sub-power wiring are made of a material different from the second sub-power wiring. Claim 4 A display device according to claim 3, wherein the pixel electrode and the third sub-power wiring are made of copper, and the first sub-power wiring and the second sub-power wiring comprise a first layer made of titanium, a second layer made of aluminum, and a third layer made of titanium. Claim 5 In claim 1, the upper surface of the second sub-power wiring is in contact with the lower surface of the third sub-power wiring. Claim 6 A display device according to claim 1, further comprising: a fourth sub-power wiring disposed on the insulating film and to which a second power supply voltage is applied; a fifth sub-power wiring disposed on the first organic film and connected to the fourth sub-power wiring through a second power hole penetrating the first organic film; and a sixth sub-power wiring disposed on the fifth sub-power wiring. Claim 7 In claim 6, the first power supply voltage is a display device supplied to the common electrode. Claim 8 In claim 6, the flattening film is a display device disposed on the sixth sub-power wiring. Claim 9 In claim 6, the pixel electrode and the 6th sub-power wiring are made of the same material in a display device. Claim 10 A display device according to claim 6, wherein the sixth sub-power wiring is made of a material different from the fourth sub-power wiring, and the sixth sub-power wiring is made of a material different from the fifth sub-power wiring. Claim 11 In claim 6, the third sub-power wiring and the sixth sub-power wiring are a display device made of the same material. Claim 12 A display device according to claim 6, wherein the first sub-power wiring and the fourth sub-power wiring are made of the same material, and the second sub-power wiring and the fifth sub-power wiring are made of the same material. Claim 13 In claim 6, the upper surface of the fifth sub-power wiring is in contact with the lower surface of the sixth sub-power wiring. Claim 14 A display device comprising: a substrate; a scan line disposed on the substrate; a first insulating film disposed on the scan lines; a first sub-clock line disposed on the first insulating film and to which a clock signal is applied; a first organic film disposed on the clock line; a second sub-clock line disposed on the first organic film and connected to the first sub-clock line through a first contact hole penetrating the first organic film; a third sub-clock line disposed on the second sub-clock line; a pixel electrode disposed on the first organic film; a light-emitting element disposed on the pixel electrode; a planarization film disposed on the side of the light-emitting element; and a common electrode disposed on the light-emitting element and the planarization film, wherein the planarization film is disposed on the third sub-clock line. Claim 15 A display device according to claim 14, further comprising a scan driving unit that applies a scan signal to a scan wiring according to the clock signal. Claim 16 In claim 14, the pixel electrode and the third sub-clock wiring are made of the same material in a display device. Claim 17 A display device according to claim 14, wherein the pixel electrode and the third sub-clock wiring are made of a material different from the first sub-clock wiring, and the pixel electrode and the third sub-clock wiring are made of a material different from the second sub-clock wiring. Claim 18 A display device comprising: a substrate; an insulating film disposed on the substrate; a pad disposed on the insulating film; a first organic film disposed on the pad; a pad protection electrode disposed on the first organic film and connected to the pad through a pad hole penetrating the first organic film; a pixel electrode disposed on the first organic film; a light-emitting element disposed on the pixel electrode; a planarization film disposed on the side of the light-emitting element; and a common electrode disposed on the light-emitting element and the planarization film. Claim 19 In claim 18, a display device further comprising: a first sub-power wiring disposed on the insulating film and to which a first power supply voltage is applied; a second sub-power wiring disposed on the first organic film and connected to the first sub-power wiring through a first power hole penetrating the first organic film; and a third sub-power wiring disposed on the second sub-power wiring, wherein the first sub-power wiring is made of the same material as the pad. Claim 20 In claim 19, the pad protection electrode is a display device made of a transparent conductive oxide.

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