Semiconductor devices

Abstract

A semiconductor device comprises lower electrodes on a substrate; a support pattern provided between the lower electrodes in a planar view; an upper electrode covering the lower electrodes and the support pattern; a dielectric film provided between the lower electrodes and the upper electrode and between the support pattern and the upper electrode; and a capping pattern interposed between the lower electrodes and the dielectric film and between the support pattern and the dielectric film. The capping pattern covers at least a portion of the side of the support pattern and extends onto the upper surface of the support pattern and the upper surfaces of the lower electrodes.

Description

Technology Field

[0001] The present invention relates to a semiconductor device, and more specifically, to a semiconductor memory device including a capacitor. Background Technology

[0002] Due to characteristics such as miniaturization, multifunctionality, and / or low manufacturing costs, semiconductor devices are gaining prominence as important elements in the electronics industry. Semiconductor devices can be classified into semiconductor memory devices that store logic data, semiconductor logic devices that process logic data, and hybrid semiconductor devices that include both memory and logic elements.

[0003] Recently, with the increasing speed and low power consumption of electronic devices, embedded semiconductor devices are also required to have fast operating speeds and / or low operating voltages. To meet these requirements, more highly integrated semiconductor devices are necessary. However, as the integration of semiconductor devices intensifies, their electrical characteristics and production yield may decrease. Accordingly, much research is being conducted to improve the electrical characteristics and production yield of semiconductor devices. The problem to be solved

[0004] The technical problem that the present invention aims to solve is to provide a semiconductor device with improved electrical characteristics.

[0005] Another technical objective of the present invention is to provide a semiconductor device with improved production yield.

[0006] The problems that the present invention aims to solve are not limited to those mentioned above, and other unmentioned problems will be clearly understood by those skilled in the art from the description below. means of solving the problem

[0007] A semiconductor device according to the present invention may include lower electrodes on a substrate; a support pattern provided between the lower electrodes in a planar view; an upper electrode covering the lower electrodes and the support pattern; a dielectric film provided between the lower electrodes and the upper electrode and between the support pattern and the upper electrode; and a capping pattern interposed between the lower electrodes and the dielectric film and between the support pattern and the dielectric film. The capping pattern may cover at least a portion of the side surface of the support pattern and may extend onto the upper surface of the support pattern and the upper surfaces of the lower electrodes.

[0008] A semiconductor device according to the present invention may include lower electrodes on a substrate; a support pattern provided between the lower electrodes in a planar view; an upper electrode covering the lower electrodes and the support pattern; a dielectric film provided between the lower electrodes and the upper electrode and between the support pattern and the upper electrode; and a capping pattern interposed between the lower electrodes and the dielectric film and between the support pattern and the dielectric film. The upper surfaces of the lower electrodes may be located at a height lower than the upper surface of the support pattern.

[0009] A semiconductor device according to the present invention may include: a substrate having an active pattern; an impurity region provided within the active pattern; a word line disposed within the substrate and extending across the active pattern; a bit line disposed on the substrate and extending in a direction intersecting the word line; a storage node contact disposed on the substrate and electrically connected to the impurity region; a landing pad electrically connected to the storage node contact; a lower electrode electrically connected to the landing pad; an upper support pattern and a lower support pattern provided between the lower electrode and an adjacent lower electrode in a planar view; an upper electrode covering the lower electrode and the upper support pattern; a dielectric film provided between the lower electrode and the upper electrode and between the upper support pattern and the upper electrode; and a capping pattern interposed between the upper surface of the lower electrode and the dielectric film and between the upper surface of the upper support pattern and the dielectric film. The capping pattern may cover at least a portion of the side of the upper support pattern and may extend onto the upper surface of the upper support pattern and the upper surface of the lower electrode. Effects of the invention

[0010] According to the concept of the present invention, when a process of etching a mold film is performed, the capping pattern can prevent damage to the lower electrodes. As a result, the electrical characteristics of the semiconductor device can be improved.

[0011] Furthermore, even if the upper surfaces of the lower electrodes are located below the bottom surface of the upper support pattern, the capping pattern can support the lower electrodes together with the upper support pattern. Accordingly, process defects such as the lower electrodes falling over can be reduced, and as a result, the production yield of the semiconductor device can be improved. Brief explanation of the drawing

[0012] FIG. 1 is a plan view showing a semiconductor device according to embodiments of the present invention. Figures 2 and 3 are cross-sectional views corresponding to A-A' in Figure 1. FIGS. 4 to 16 are drawings illustrating a method for manufacturing a semiconductor device according to embodiments of the present invention, FIGS. 4 to 11 are cross-sectional views illustrating a method for manufacturing a semiconductor device of FIG. 2, and FIGS. 12 to 16 are cross-sectional views illustrating a method for manufacturing a semiconductor device of FIG. 3. FIG. 17 is a block diagram showing a semiconductor device according to embodiments of the present invention. Figure 18 is an enlarged view corresponding to part P1 of Figure 17. FIG. 19 is a cross-sectional view corresponding to A-A' in FIG. 18. Specific details for implementing the invention

[0013] Hereinafter, in order to explain the present invention more specifically, embodiments according to the present invention will be described in more detail with reference to the accompanying drawings.

[0015] FIG. 1 is a plan view showing a semiconductor device according to embodiments of the present invention. FIG. 2 is a cross-sectional view corresponding to A-A' of FIG. 1.

[0016] Referring to FIGS. 1 and FIGS. 2, a substrate (10) may be provided. The substrate (10) may be a semiconductor substrate. The substrate (10) may be, for example, a silicon substrate, a germanium substrate, or a silicon-germanium substrate.

[0017] An interlayer insulating film (12) may be disposed on the substrate (10). The interlayer insulating film (12) may cover at least a portion of the upper surface of the substrate (10). For example, the interlayer insulating film (12) may include at least one of silicon nitride, silicon oxide, or silicon oxynitride. For another example, the interlayer insulating film (12) may include an empty region.

[0018] Conductive contacts (14) may be disposed within the interlayer insulating film (12). The conductive contacts (14) may be spaced apart in a first direction (D1) and a second direction (D2) that are parallel to and intersect each other (e.g., orthogonal) the upper surface of the substrate (10). Each of the conductive contacts (14) may comprise at least one of an impurity-doped semiconductor material (e.g., polycrystalline silicon), a metal-semiconductor compound (e.g., tungsten silicide), a conductive metal nitride (e.g., titanium nitride, tantalum nitride, or tungsten nitride, etc.), or a metal (e.g., titanium, tungsten, or tantalum, etc.). The conductive contacts (14) may be electrically connected to impurity regions (e.g., source / drain terminals) formed within the substrate (10).

[0019] An etch stop pattern (420) may be disposed on the interlayer insulating film (12). The etch stop pattern (420) may cover the interlayer insulating film (12) and expose the conductive contacts (14). The etch stop pattern (420) may include at least one of silicon oxide, SiCN, or SiBN.

[0020] Lower electrodes (BE) may be disposed on the conductive contacts (14). The lower electrodes (BE) may penetrate the etching stop pattern (420) and may be electrically connected to each of the conductive contacts (14). For example, each of the lower electrodes (BE) may have a pillar shape. As another example, although not illustrated, each of the lower electrodes (BE) may have a cylinder shape with a closed bottom surface.

[0021] The lower electrodes (BE) may be spaced apart from each other in the first direction (D1) and the second direction (D2). In a planar view, for example, the lower electrodes (BE) may be arranged to have a honeycomb shape. In detail, with one lower electrode (BE) at the center, six lower electrodes (BE) may be arranged to surround the one lower electrode (BE) in a hexagon. The lower electrodes (BE) may include a conductive material. For example, the lower electrodes (BE) may comprise at least one of a metallic material (e.g., cobalt, titanium, nickel, tungsten, and molybdenum), a metal nitride (e.g., titanium nitride (TiN), titanium silicon nitride (TiSiN), titanium aluminum nitride (TiAlN), tantalum nitride (TaAlN), and tungsten nitride (WN)), a precious metal (e.g., platinum (Pt), ruthenium (Ru), and iridium (Ir)), a conductive oxide (PtO, RuO2, IrO2, SRO (SrRuO3), BSRO ((Ba,Sr)RuO3), CRO (CaRuO3), LSCo) or a metal silicide.

[0022] An upper support pattern (US) and a lower support pattern (LS) may be provided on the substrate (10). The upper support pattern (US) and the lower support pattern (LS) may be spaced apart from each other in a third direction (D3) perpendicular to the upper surface of the substrate (10). The upper support pattern (US) may be located at a higher height than the lower support pattern (LS). Although not illustrated, additional support patterns spaced apart from each other in the third direction (D3) may be provided, and the support pattern provided on the top layer may be referred to as the upper support pattern (US). The upper support pattern (US) and the lower support pattern (LS) may be provided between the lower electrodes (BE). The upper support pattern (US) and the lower support pattern (LS) may be in contact with the sides of the lower electrodes (BE) and may wrap around the sides of the lower electrodes (BE). The upper support pattern (US) and the lower support pattern (LS) can physically support the lower electrodes (BE). The upper support pattern (US) and the lower support pattern (LS) can come into contact with the sidewalls of adjacent lower electrodes (BE). The thickness of the upper support pattern (US) along the third direction (D3) and the thickness of the lower support pattern (LS) along the third direction (D3) may differ from each other. Each of the upper support pattern (US) and the lower support pattern (LS) may comprise, for example, at least one of silicon nitride, SiBN, or SiCN.

[0023] The upper surfaces (BEu) of the lower electrodes (BE) may be located at a lower height than the upper surface (USu) of the upper support pattern (US). For example, the upper surfaces (BEu) of the lower electrodes (BE) may be located at a height lower than the upper surface (USu) of the upper support pattern (US) and higher than the bottom surface of the upper support pattern (US). A portion of the side surface (USs) of the upper support pattern (US) may be exposed by the lower electrodes (BE). Another portion of the side surface (USs) of the upper support pattern (US) may be in contact with the sides of the lower electrodes (BE). The upper surfaces (BEu) of the lower electrodes (BE) may be located at a higher height than the upper surface of the lower support pattern (LS).

[0024] A capping pattern (CP) may be provided on the upper support pattern (US) and the lower electrodes (BE). The capping pattern (CP) may cover the portion of the side (USs) of the upper support pattern (US) that is exposed by the lower electrodes (BE). The capping pattern (CP) may further cover the upper surface (USu) of the upper support pattern (US) and the upper surfaces (BEu) of the lower electrodes (BE). That is, the capping pattern (CP) may cover the exposed portion of the side (USs) of the upper support pattern (US) and extend onto the upper surface (USu) of the upper support pattern (US) and the upper surfaces (BEu) of the lower electrodes (BE). In a planar view, the lower electrodes (BE) and the upper support pattern (US) may overlap perpendicularly with the capping pattern (CP).

[0025] The capping pattern (CP) may include a material having etch selectivity with respect to the lower electrodes (BE). The capping pattern (CP) may include a material having etch selectivity with respect to the mold film (e.g., silicon oxide) described with reference to FIG. 4. For example, the capping pattern (CP) may include at least one of silicon nitride, polysilicon, or SiCN. The thickness (T1) of the capping pattern (CP) along the third direction (D3) may be 1 nm or more and 50 nm or less.

[0026] Through holes (PH) may be placed between adjacent lower electrodes (BE). For example, one through hole (PH) may be placed in a circular shape between three adjacent lower electrodes (BE) and may expose a portion of the side of each of the three lower electrodes (BE). However, it is not limited thereto, and the through holes (PH) may be placed between multiple lower electrodes (BE) in various forms. Each of the through holes (PH) may penetrate the capping pattern (CP), the upper support pattern (US), and the lower support pattern (LS). Each of the through holes (PH) may expose the etching stop pattern (420).

[0027] A dielectric film (DL) may be provided on the upper support pattern (US), the lower support pattern (LS), the lower electrodes (BE), the etch stop pattern (420), and the capping pattern (CP). The dielectric film (DL) may conformally cover the upper support pattern (US), the lower support pattern (LS), the lower electrodes (BE), the etch stop pattern (420), and the capping pattern (CP). The capping pattern (CP) may be interposed between the upper surfaces (BEu) of the lower electrodes (BE) and the dielectric film (DL). The capping pattern (CP) may be further interposed between the exposed portion of the side surface (USs) of the upper support pattern (US) and the dielectric film (DL), and between the upper surface (USu) of the upper support pattern (US) and the dielectric film (DL). The dielectric film (DL) may fill a portion of the through holes (PH). The dielectric film (DL) in contact with the lower electrodes (BE) may have a crystal structure identical to the crystal structure of the lower electrodes (BE). For example, the dielectric film (DL) may have a tetragonal structure. The dielectric film (DL) may be formed as a single film selected from a combination of films, for example, metal oxides such as HfO2, ZrO2, Al2O3, La2O3, Ta2O3, and TiO2, and dielectric materials with perovskite structures such as SrTiO3 (STO), (Ba,Sr)TiO3 (BST), BaTiO3, PZT, and PLZT, or as a combination of these films.

[0028] An upper electrode (TE) may be provided on the dielectric film (DL). The upper electrode (TE) may cover the lower electrodes (BE), the upper support pattern (US), and the lower support pattern (LS). The upper electrode (TE) may fill the remainder of the through holes (PH), the space between the upper support pattern (US) and the lower support pattern (LS), and the space between the lower support pattern (LS) and the etch stop pattern (420). The dielectric film (DL) may be interposed between the lower electrodes (BE) and the upper electrode (TE), between the upper support pattern (US) and the upper electrode (TE), between the lower support pattern (LS) and the upper electrode (TE), and between the capping pattern (CP) and the upper electrode (TE).

[0029] The upper electrode (TE) may comprise at least one of titanium nitride, impurity-doped polysilicon, and impurity-doped silicon germanium. The upper electrode (TE) may be a single film or a multi-film. The lower electrodes (BE), the dielectric film (DL), and the upper electrode (TE) may form a capacitor (CA). For example, the capacitor (CA) may perform the function of an information storage element for the semiconductor device according to the present invention to operate as a memory device.

[0031] FIG. 3 is a cross-sectional view corresponding to A-A' in FIG. 1, showing a semiconductor device according to other embodiments of the present invention. For the sake of simplicity, descriptions of content that overlap with the foregoing are omitted, and the description focuses on features that differentiate it from the foregoing.

[0032] Referring to FIGS. 1 and 3, an upper support pattern (US) and a lower support pattern (LS) may be provided on the substrate (10). In a planar view, the upper support pattern (US) and the lower support pattern (LS) may be provided between the lower electrodes (BE). The upper surfaces (BEu) of the lower electrodes (BE) may be located at a height lower than the bottom surface of the upper support pattern (US) and at a height higher than the upper surface of the lower support pattern (LS). That is, the upper support pattern (US) may be vertically spaced apart from the lower electrodes (BE) and may not be in contact with the sides of the lower electrodes (BE).

[0033] A capping pattern (CP) may cover the entire area of ​​the side (USs) of the upper support pattern (US). The capping pattern (CP) may extend from the side (USs) of the upper support pattern (US) onto the upper surfaces (BEu) of the lower electrodes (BE) that are vertically spaced apart from the upper support pattern (US). The capping pattern (CP) on the side (USs) of the upper support pattern (US) may be interposed between the upper support pattern (US) and the dielectric film (DL). The capping pattern (CP) provided between the upper support pattern (US) and the lower electrodes (BE) may be surrounded by the dielectric film (DL). The capping pattern (CP) may further extend onto the upper surface (USu) of the upper support pattern (US). The capping pattern (CP) may come into contact with the side surface (USs) of the upper support pattern (US) and the upper surface (BEu) of the lower electrodes (BE). Through this, the capping pattern (CP) can transmit a supporting force from the upper support pattern (US), which is spaced apart from the lower electrodes (BE), to the lower electrodes (BE).

[0035] FIGS. 4 to 11 are cross-sectional views illustrating a method for manufacturing a semiconductor device of FIG. 2. The method for manufacturing a semiconductor device according to FIG. 2 will be explained below through FIGS. 4 to 11. For the sake of simplicity, descriptions of content that overlap with the previously mentioned content will be omitted.

[0036] Referring to FIG. 4, a substrate (10) may be provided. An interlayer insulating film (12) may be formed on the substrate (10). Conductive contacts (14) may be formed within the interlayer insulating film (12). An etch stop layer (420L) may be formed on the substrate (10). The etch stop layer (420L) may be formed to cover the upper surface of the interlayer insulating film (12) and the upper surfaces of the conductive contacts (14).

[0037] A mold structure (MS) may be formed on the etch stop layer (420L). The mold structure (MS) may be formed by alternately stacking mold films and support films. For example, the mold structure (MS) may be formed by stacking a first mold film (20), a lower support film (22), a second mold film (24), and an upper support film (26) in sequence. The lower support film (22) may include a material having etch selectivity with respect to the first mold film (20). The upper support film (26) may include a material having etch selectivity with respect to the second mold film (24). The first mold film (20) and the second mold film (24) may include the same material. For example, the first mold film (20) and the second mold film (24) may include silicon oxide. The lower support film (22) and the upper support film (26) may each contain the same material. For example, the lower support film (22) and the upper support film (26) may include at least one of silicon nitride, SiBN, or SiCN.

[0038] A first mask film (40) and a second mask pattern (42) may be formed sequentially on the mold structure (MS). The first mask film (40) may cover the upper support film (26). The first mask film (40) may include, for example, at least one of polysilicon, silicon nitride, or silicon oxynitride. The second mask pattern (42) may be formed on the first mask film (40) and may have first openings (OP1). A portion of the upper surface of the first mask film (40) may be exposed through the first openings (OP1). The second mask pattern (42) may include, for example, at least one of a Spin On Hardmask (SOH) or an Amorphous Carbon Layer (ACL).

[0039] Referring to FIG. 5, the first mask film (40), the mold structure (MS), and the etch stop film (420L) can be anisotropically etched using the second mask pattern (42) as an etching mask. Accordingly, conductive holes (CH) having a shape similar to the first openings (OP1) can be formed planarly. The conductive holes (CH) can penetrate the mold structure (MS) and the etch stop film (420L) in the third direction (D3) and expose the upper surfaces of the conductive contacts (14). After the etching process, the remainder of the etch stop film (420L) that is not etched can form an etch stop pattern (420). For example, the first mask film (40) and the second mask pattern (42) can be removed through the etching process. As another example, the first mask film (40) and the second mask pattern (42) can be removed through a separate removal process after the etching process.

[0040] Referring to FIG. 6, a lower electrode film (50) can be formed on the mold structure (MS) and fill the conductive holes (CH). The lower electrode film (50) can cover the exposed upper surfaces of the conductive contacts (14) and the upper support film (26). The lower electrode film (50) can be formed through a deposition technique with excellent step coverage. For example, the lower electrode film (50) can be formed through a chemical vapor deposition (CVD) or atomic layer deposition (ALD) process.

[0041] For example, the lower electrode film (50) may be formed to completely fill the conductive holes (CH). For another example, although not illustrated, the lower electrode film (50) may be formed to conformally cover the inner wall of each of the conductive holes (CH) and the upper surface of the mold structure (MS). The lower electrode film (50) may comprise at least one of a metal material (e.g., cobalt, titanium, nickel, tungsten and molybdenum), a metal nitride (e.g., titanium nitride (TiN), titanium silicon nitride (TiSiN), titanium aluminum nitride (TiAlN), tantalum nitride (TaAlN) and tungsten nitride (WN)), a precious metal (e.g., platinum (Pt), ruthenium (Ru) and iridium (Ir)), a conductive oxide (PtO, RuO2, IrO2, SRO (SrRuO3), BSRO ((Ba,Sr)RuO3), CRO (CaRuO3), LSCo) or a metal silicide.

[0042] Referring to FIG. 7, the upper portion of the lower electrode film (50) may be removed. The lower electrode film (50) may be separated into lower electrodes (BE) that fill each of the conductive holes (CH). Removing the upper portion of the lower electrode film (50) may, for example, include performing an etch-back process. The lower electrodes (BE) may penetrate the mold structure (MS) in the third direction (D3) and may be electrically connected to each of the conductive contacts (14). For example, as shown in FIG. 6, when the lower electrode film (50) is formed to completely fill the conductive holes (CH), each of the lower electrodes (BE) may be formed to have a pillar shape. In another example, although not illustrated, if the lower electrode film (50) is formed to conformally cover the inner wall of each of the conductive holes (CH) and the upper surface of the mold structure (MS), each of the lower electrodes (BE) may be formed to have a cylinder shape with a closed bottom surface.

[0043] The upper surfaces (BEu) of the lower electrodes (BE) may be located at a height lower than the upper surface of the upper support membrane (26). For example, the upper surfaces (BEu) of the lower electrodes (BE) may be located at a height lower than the upper surface of the upper support membrane (26) and higher than the bottom surface of the upper support membrane (26). A portion of the side of the upper support membrane (26) may be exposed by the lower electrodes (BE). Another portion of the side of the upper support membrane (26) may be in contact with the sides of the lower electrodes (BE). The upper surfaces (BEu) of the lower electrodes (BE) may be located at a height higher than the upper surface of the lower support membrane (22).

[0044] Referring to FIG. 8, a capping film (CPa) may be formed on the lower electrodes (BE) and the upper support film (26). The capping film (CPa) may cover the upper surfaces (BEu) of the lower electrodes (BE), the upper surface of the upper support film (26), and the exposed portion of the side surface. The upper surfaces (BEu) of the lower electrodes (BE) may not be exposed to the outside by the capping film (CPa). The capping film (CPa) may comprise a material having etch selectivity for the lower electrodes (BE), the first mold film (20), and the second mold film (24). The capping film (CPa) may comprise, for example, at least one of silicon nitride, polysilicon, or SiCN. The capping film (CPa) may be formed through a chemical vapor deposition (CVD) or atomic layer deposition (ALD) process.

[0045] Referring to FIG. 9, a third mask film (60) and a fourth mask pattern (62) may be formed sequentially on the capping film (CPa). The third mask film (60) may cover the capping film (CPa). The fourth mask pattern (62) may be formed on the third mask film (60) and may have second openings (OP2). A portion of the upper surface of the third mask film (60) may be exposed through the second openings (OP2). The third mask film (60) may include, for example, polysilicon. The fourth mask pattern (62) may include, for example, photoresist.

[0046] Referring to FIG. 10, the third mask film (60), the capping film (CPa), and the upper support film (26) can be anisotropically etched using the fourth mask pattern (62) as an etching mask. Accordingly, a portion of the third mask film (60), a portion of the capping film (CPa), and a portion of the upper support film (26) that overlap vertically with the second openings (OP2) can be removed. The remainder of the capping film (CPa) can form a capping pattern (CP), and the remainder of the upper support film (26) can form an upper support pattern (US). Through holes (PH) that penetrate the capping pattern (CP) and the upper support pattern (US) in sequence can be formed. The through holes (PH) can overlap vertically with the second openings (OP2). A portion of the upper surface of the second mold film (24) may be exposed by the above through holes (PH).

[0047] Subsequently, the second mold film (24) may be removed. Accordingly, the bottom surface of the upper support pattern (US), parts of the sides of the lower electrodes (BE), and the top surface of the lower support film (22) may be exposed. The removal process of the second mold film (24) may include an isotropic etching process. When the isotropic etching process is performed, the capping pattern (CP), the upper support pattern (US), and the lower support film (22), which have etch selectivity with respect to the second mold film (24), may not be removed. The capping pattern (CP) may prevent the upper surface of the lower electrodes (BE) from being removed or damaged by the isotropic etching process. Phosphoric acid (H3PO4) may be used to perform the isotropic etching process. For example, the remainder of the third mask film (60) may be removed before the removal of the second mold film (24), but is not limited thereto.

[0048] Referring to FIG. 11, a portion of the lower support film (22) that overlaps vertically with the through holes (PH) can be etched, and a portion of the upper surface of the first mold film (20) can be exposed. The remainder of the lower support film (22) can form a lower support pattern (LS). The through holes (PH) can extend into the lower support pattern (LS) and can further penetrate the lower support pattern (LS).

[0049] Subsequently, the first mold film (20) may be removed. Accordingly, the bottom surface of the lower support pattern (LS), the remainder of the sides of the lower electrodes (BE), and the top surface of the etching prevention pattern (420) may be exposed. The removal process of the first mold film (20) may include an isotropic etching process. When the isotropic etching process is performed, the capping pattern (CP), upper support pattern (US), and lower support pattern (LS), which have etching selectivity with respect to the first mold film (20), may not be removed. The capping pattern (CP) may prevent the lower electrodes (BE) from being removed or damaged by the isotropic etching process. Phosphoric acid (H3PO4) may be used to perform the isotropic etching process.

[0050] Referring again to FIG. 2, a dielectric film (DL) may be formed on the upper support pattern (US), the lower support pattern (LS), the lower electrodes (BE), the etch stop pattern (420), and the capping pattern (CP). The dielectric film (DL) may conformally cover the upper support pattern (US), the lower support pattern (LS), the lower electrodes (BE), the etch stop pattern (420), and the capping pattern (CP). The dielectric film (DL) may fill a portion of the through holes (PH). By forming the dielectric film (DL), the capping pattern (CP) may be interposed between the upper surfaces (BEu) of the lower electrodes (BE) and the dielectric film (DL), between the upper surface (USu) of the upper support pattern (US) and the dielectric film (DL), and between an exposed portion of the side surface (USs) of the upper support pattern (US) and the dielectric film (DL).

[0051] The dielectric film (DL) in contact with the lower electrodes (BE) can be formed to have the same crystal structure as the lower electrodes (BE). For example, the dielectric film (DL) can be formed to have a tetragonal structure. The dielectric film (DL) can be formed using a deposition technique with excellent step coverage, such as chemical vapor deposition (CVD) or atomic layer deposition (ALD).

[0052] An upper electrode (TE) may be formed on the dielectric film (DL). The upper electrode (TE) may fill the remainder of the through holes (PH) and cover the upper surfaces (BEu) of the lower electrodes (BE). The upper electrode (TE) may fill the space between the lower electrodes (BE), between the upper support pattern (US) and the lower support pattern (LS), and between the lower support pattern (LS) and the etch stop pattern (420). By forming the upper electrode (TE), the dielectric film (DL) may be interposed between the lower electrodes (BE) and the upper electrode (TE). The lower electrodes (BE), the dielectric film (DL), and the upper electrode (TE) may form a capacitor (CA).

[0054] FIGS. 12 to 16 are cross-sectional views illustrating a method for manufacturing a semiconductor device of FIG. 3. The method for manufacturing a semiconductor device according to FIG. 3 will be explained below through FIGS. 12 to 16. For the sake of simplicity, descriptions of content that overlap with the previously mentioned content will be omitted.

[0055] Referring to FIG. 12, the upper portion of the lower electrode film (50) of FIG. 6 can be removed. The lower electrode film (50) can be separated into lower electrodes (BE) that fill each of the conductive holes (CH). The upper surfaces (BEu) of the lower electrodes (BE) can be formed to be located at a height lower than the bottom surface of the upper support film (26). That is, the lower electrodes (BE) can be formed to be vertically spaced apart from the upper support film (26). The entire side area of ​​the upper support film (26) and a portion of the side of the second mold film (24) can be exposed by the lower electrodes (BE). The upper surfaces (BEu) of the lower electrodes (BE) can be formed to be located at a height higher than the upper surface of the lower support film (22).

[0056] Referring to FIG. 13, a capping film (CPa) may be formed on the lower electrodes (BE) and the upper support film (26). The capping film (CPa) may cover the exposed portion of the side of the upper support film (26) and the side of the second mold film (24), and may extend over the upper surface of the upper support film (26) and the upper surfaces of the lower electrodes (BE). The upper surfaces (BEu) of the lower electrodes (BE) may not be exposed to the outside by the capping film (CPa).

[0057] Referring to FIG. 14, a third mask film (60) and a fourth mask pattern (62) may be formed sequentially on the capping film (CPa). The third mask film (60) may cover the capping film (CPa). The fourth mask pattern (62) may be formed on the third mask film (60) and may have second openings (OP2).

[0058] Referring to FIG. 15, the third mask film (60), the capping film (CPa), and the upper support film (26) can be anisotropically etched using the fourth mask pattern (62) as an etching mask. The remainder of the capping film (CPa) can form a capping pattern (CP), and the remainder of the upper support film (26) can form an upper support pattern (US). Through holes (PH) that pass through the capping pattern (CP) and the upper support pattern (US) in sequence can be formed.

[0059] Subsequently, the second mold film (24) may be removed. Accordingly, the bottom surface of the upper support pattern (US), parts of the sides of the lower electrodes (BE), and the top surface of the lower support film (22) may be exposed. The removal process of the second mold film (24) may include an isotropic etching process. The capping pattern (CP) may prevent the upper surface of the lower electrodes (BE) from being removed or damaged by the isotropic etching process.

[0060] Referring to FIG. 16, a portion of the lower support film (22) that overlaps vertically with the through holes (PH) can be etched, and a portion of the upper surface of the first mold film (20) can be exposed. The remainder of the lower support film (22) can form a lower support pattern (LS).

[0061] Subsequently, the first mold film (20) may be removed. Accordingly, the bottom surface of the lower support pattern (LS), the remainder of the sides of the lower electrodes (BE), and the top surface of the etching prevention pattern (420) may be exposed. The removal process of the first mold film (20) may include an isotropic etching process. The capping pattern (CP) may prevent the lower electrodes (BE) from being removed or damaged by the isotropic etching process.

[0062] The lower electrodes (BE) can be supported without falling over by the capping pattern (CP) and the lower support pattern (LS). Specifically, the capping pattern (CP) can support the upper portion of the lower electrodes (BE), and the lower support pattern (LS) can support the lower portion of the lower electrodes (BE). The capping pattern (CP) can simultaneously come into contact with the upper support pattern (US) spaced apart from the lower electrodes (BE), thereby transmitting a supporting force from the upper support pattern (US) to the lower electrodes (BE).

[0063] Referring again to FIG. 3, the dielectric film (DL) can conformally cover the upper support pattern (US), the lower support pattern (LS), the lower electrodes (BE), the etch stop pattern (420), and the capping pattern (CP). The dielectric film (DL) can fill a portion of the through holes (PH). The dielectric film (DL) can be formed to surround the capping pattern (CP) provided between the upper support pattern (US) and the lower electrodes (BE).

[0064] An upper electrode (TE) may be formed on the dielectric film (DL). The upper electrode (TE) may fill the remainder of the through holes (PH) and cover the upper surfaces (BEu) of the lower electrodes (BE). The upper electrode (TE) may fill the space between the lower electrodes (BE), between the upper support pattern (US) and the lower support pattern (LS), and between the lower support pattern (LS) and the etch stop pattern (420).

[0066] FIG. 17 is a block diagram showing a semiconductor device according to embodiments of the present invention. FIG. 18 is an enlarged view corresponding to part P1 of FIG. 17. FIG. 19 is a cross-sectional view corresponding to A-A' of FIG. 18. For the sake of simplicity, descriptions of content that overlap with the foregoing are omitted.

[0067] Referring to FIG. 17, the semiconductor device may include cell blocks (CB) and a surrounding block (PB) that surrounds each of the cell blocks (CB). The semiconductor device may be a memory device, and each of the cell blocks (CB) may include a cell circuit such as a memory integrated circuit. The cell blocks (CB) may be spaced apart from each other in a first direction (D1) and a second direction (D2) that intersects (e.g., orthogonally) the first direction (D1).

[0068] The peripheral block (PB) may include various peripheral circuits necessary for the operation of the cell circuit, and the peripheral circuits may be electrically connected to the cell circuit. The peripheral block (PB) may include sense amplifier circuits (SA) and sub-wordline driver circuits (SWD). For example, the sense amplifier circuits (SA) may face each other with the cell blocks (CB) in between, and the sub-wordline driver circuits (SWD) may face each other with the cell blocks (CB) in between. The peripheral block (PB) may further include power supply and ground driver circuits for driving the sense amplifier, but the concept of the present invention is not limited thereto.

[0069] Referring to FIGS. 18 and 19, a substrate (10) including a cell region may be provided. The cell region may be a region of the substrate (10) in which each cell block (CB) of FIG. 17 is provided. The substrate (10) may be, for example, a silicon substrate, a germanium substrate, or a silicon-germanium substrate.

[0070] Active patterns (ACTs) may be disposed on the cell region of the substrate (10). In a planar view, the active patterns (ACTs) may be spaced apart from each other along the first direction (D1) and the second direction (D2). The active patterns (ACTs) may have a bar shape extending in a fourth direction (D4) that is parallel to the upper surface of the substrate (10) and intersects the first direction (D1) and the second direction (D2). Any end of the active patterns (ACTs) may be arranged to be adjacent to the center of another active pattern (ACT) immediately adjacent in the second direction (D2). Each of the active patterns (ACTs) may be a part of the substrate (10) protruding from the substrate (10) along the third direction (D3).

[0071] Device isolation films (120) may be disposed between the active patterns (ACT). The device isolation films (120) may be disposed within the substrate (10) to define the active patterns (ACT). The device isolation films (120) may include, for example, silicon oxide, silicon nitride, and / or silicon oxynitride.

[0072] Word lines (WL) may be disposed within the substrate (10) and may cross the active patterns (ACT) and the device isolation films (120). The word lines (WL) may be disposed within grooves formed in the active patterns (ACT) and the device isolation films (120). The word lines (WL) may extend in the second direction (D2) and be spaced apart from each other along the first direction (D1). The word lines (WL) may be embedded within the substrate (10).

[0073] Impurity regions may be provided within the active patterns (ACT). The impurity regions may include first impurity regions (110a) and second impurity regions (110b). The second impurity regions (110b) may be provided adjacent to each of the two ends within each active pattern (ACT). Each of the first impurity regions (110a) may be provided between the second impurity regions (110b) within each active pattern (ACT). The first impurity regions (110a) may contain impurities of the same conductivity type (e.g., N-type) as the second impurity regions (110b).

[0074] A buffer pattern (305) may be disposed on the cell region of the substrate (10). The buffer pattern (305) may cover the active patterns (ACT), the device isolation films (120), and the word lines (WL). The buffer pattern (305) may include, for example, silicon oxide, silicon nitride, and / or silicon oxynitride.

[0075] Bit lines (BL) may be disposed on the substrate (10). The bit lines (BL) may extend along the first direction (D1) and may be spaced apart from each other along the second direction (D2). Each of the bit lines (BL) may include a first ohmic pattern (331) and a metal-containing pattern (330) stacked in sequence. For example, the first ohmic pattern (331) may include a metal silicide. For example, the metal-containing pattern (330) may include a metal (tungsten, titanium, tantalum, etc.).

[0076] Polysilicon patterns (310) may be interposed between the bit lines (BL) and the buffer pattern (305).

[0077] Bitline contacts (DC) may be interposed between the bitlines (BL) and the first impurity regions (110a), respectively. The bitlines (BL) may be electrically connected to the first impurity regions (110a) by the bitline contacts (DC). The bitline contacts (DC) may comprise polysilicon that is doped with or undoped with impurities.

[0078] The bitline contacts (DC) may be placed within a recess region (RE). The recess region (RE) may be provided above the first impurity regions (110a) and above the adjacent device isolation films (120). The first buried insulation pattern (314) and the second buried insulation pattern (315) may fill the remainder within the recess region (RE).

[0079] A bitline capping pattern (350) may be provided on the upper surface of each of the bitlines (BL). The bitline capping pattern (350) may extend along the first direction (D1) on each of the bitlines (BL) and may be spaced apart from adjacent bitline capping patterns (350) along the second direction (D2). The bitline capping pattern (350) may include a first bitline capping pattern (351), a second bitline capping pattern (352), and a third bitline capping pattern (353). The bitline capping pattern (350) may include a silicon nitride film. For example, the first bitline capping pattern (351), the second bitline capping pattern (352), and the third bitline capping pattern (353) may include a silicon nitride film.

[0080] Each side of the polysilicon patterns (310), each upper side of the bitline contacts (DC), each side of the bitlines (BL), and the side of the bitline capping pattern (350) may be covered by a bitline spacer (SP). The bitline spacer (SP) may extend along the first direction (D1) on each of the bitlines (BL).

[0081] The bitline spacer (SP) may include a first sub-spacer (321) and a second sub-spacer (325) spaced apart from each other. For example, the first sub-spacer (321) and the second sub-spacer (325) may be spaced apart by an air gap (AG). The first sub-spacer (321) may be in contact with each side of the bitlines (BL) and may extend along the side of the bitline capping pattern (350). The second sub-spacer (325) may be provided along the side of the first sub-spacer (321). The first sub-spacer (321) and the second sub-spacer (325) may have a single-layer or multi-layer structure among at least one silicon nitride film, silicon oxide film, or silicon oxynitride film. The first sub-spacer (321) and the second sub-spacer (325) may contain the same material.

[0082] The fourth capping pattern (360) may cover the side of the first sub-spacer (321) and extend to the upper surface of the second sub-spacer (325). The fourth capping pattern (360) may further cover the air gap (AG).

[0083] Storage node contacts (BC) may be interposed between adjacent bit lines (BL) on the substrate (10). A bit line spacer (SP) may be interposed between the storage node contacts (BC) and the adjacent bit lines (BL). The storage node contacts (BC) may be spaced apart from each other in the first direction (D1) and the second direction (D2). Each of the storage node contacts (BC) may be electrically connected to a corresponding one of the second impurity regions (110b). The storage node contacts (BC) may comprise polysilicon that is impurity-doped or undoped.

[0084] A second ohmic pattern (341) may be placed on each of the storage node contacts (BC). The second ohmic pattern (341) may include a metal silicide.

[0085] The diffusion prevention pattern (342) may conformally cover the second ohmic pattern (341), the bitline spacer (SP), and the bitline capping pattern (350). The diffusion prevention pattern (342) may include a metal nitride such as a titanium nitride film or a tantalum nitride film. The second ohmic pattern (341) may be interposed between the diffusion prevention pattern (342) and each of the storage node contacts (BC).

[0086] Landing pads (LP) may be placed on each of the storage node contacts (BC). Each of the landing pads (LP) may be electrically connected to a corresponding one of the storage node contacts (BC). The landing pads (LP) may comprise a metal-containing material such as tungsten. The upper portion of the landing pads (LP) may be shifted from the storage node contacts (BC) in the second direction (D2). In a planar view, the landing pads (LP) may be spaced apart from each other in the first direction (D1) and the second direction (D2). For example, the landing pads (LP) may be spaced apart from each other in the first direction (D1) and the second direction (D2) in a zigzag pattern. The landing pads (LP) may correspond to the conductive contacts (14) of FIGS. 2 and FIGS. 3.

[0087] A filling pattern (400) may wrap around each of the landing pads (LP). The filling pattern (400) may be interposed between adjacent landing pads (LP). For example, the filling pattern (400) may include at least one of silicon nitride, silicon oxide, or silicon oxynitride. For another example, the filling pattern (400) may include an empty region. The filling pattern (400) may correspond to the interlayer insulating film (12) of FIGS. 2 and 3.

[0088] An etching stop pattern (420) may be disposed on the filling pattern (400). The etching stop pattern (420) may expose the upper surfaces of the landing pads (LP), and lower electrodes (BE) may be disposed on each of the upper surfaces of the landing pads (LP). Each of the lower electrodes (BE) may be electrically connected to a corresponding one of the landing pads (LP).

[0089] A support pattern may be provided on the substrate (10). The support pattern may include an upper support pattern (US) and a lower support pattern (LS) spaced apart from each other in the third direction (D3). In a planar view, the support pattern may be interposed between any one of the lower electrodes (BE) and an adjacent lower electrode (BE). The upper surfaces (BEu) of the lower electrodes (BE) may be located at a lower height than the upper surface (USu) of the upper support pattern (US). For example, as shown in FIG. 19, the upper surfaces (BEu) of the lower electrodes (BE) may be located at a higher height than the bottom surface of the upper support pattern (US). For another example, as shown in FIG. 3, the upper surfaces (BEu) of the lower electrodes (BE) may be located at a lower height than the bottom surface of the upper support pattern (US).

[0090] An upper electrode (TE) may cover the lower electrodes (BE) and the support pattern. A dielectric film (DL) may be interposed between the lower electrodes (BE) and the upper electrode (TE), and between the support pattern and the upper electrode (TE). A capping pattern (CP) may be interposed between the upper surfaces (BEu) of the lower electrodes (BE) and the dielectric film (DL), and between the upper support pattern (US) and the dielectric film (DL). The capping pattern (CP) may cover at least a portion of the side surface (USs) of the upper support pattern (US) and may extend onto the upper surface (USu) of the upper support pattern (US) and the upper surfaces (BEu) of the lower electrodes (BE). The lower electrodes (BE), the dielectric film (DL), and the upper electrode (TE) may form a capacitor (CA).

[0091] The description of the etching stop pattern (420), the lower electrodes (BE), the upper support pattern (US), the lower support pattern (LS), the capping pattern (CP), the dielectric film (DL), and the upper electrode (TE) may be substantially the same as described above with reference to FIGS. 1 to 3.

[0093] According to the concept of the present invention, when an isotropic etching process is performed on the first mold film (20) and the second mold film (24), the capping pattern (CP) can prevent the upper portion of the lower electrodes (BE) from being damaged by the isotropic etching process. As a result, the deterioration of the capacitor (CA) performance can be prevented, and as a result, the electrical characteristics of the semiconductor device can be improved.

[0094] In addition, generally, when forming the lower electrodes (BE), if the upper surfaces (BEu) of the lower electrodes (BE) are located at a height lower than the bottom surface of the upper support pattern (US), the lower electrodes (BE) may not be supported by the upper support pattern (US). Accordingly, after the first mold film (20) and the second mold film (24) are removed, defects such as bending or falling of the lower electrodes (BE) having a high aspect ratio may occur. According to the concept of the present invention, even if the upper surfaces (BEu) of the lower electrodes (BE) are located at a height lower than the bottom surface of the upper support pattern (US), the capping pattern (CP) can support the lower electrodes (BE) by contacting the lower electrodes (BE) and the upper support pattern (US). Accordingly, process defects of the lower electrodes (BE) can be reduced, and as a result, the production yield of the semiconductor device can be improved.

[0096] The above description of the embodiments of the present invention provides examples for explaining the present invention. Accordingly, the present invention is not limited to the above embodiments, and it is evident that many modifications and changes are possible within the technical scope of the present invention, such as combining the above embodiments by those skilled in the art. Explanation of the symbols

[0097] BE: Lower electrode DL: Dielectric film TE: Upper electrode US, LS: Upper and lower support patterns CP: Capping pattern

Claims

Claim 1 A semiconductor device comprising: lower electrodes on a substrate; a support pattern provided between the lower electrodes in a planar view; an upper electrode covering the lower electrodes and the support pattern; a dielectric film provided between the lower electrodes and the upper electrode and between the support pattern and the upper electrode; and a capping pattern interposed between the lower electrodes and the dielectric film and between the support pattern and the dielectric film, wherein the capping pattern covers at least a portion of the side of the support pattern and extends onto the upper surface of the support pattern and the upper surfaces of the lower electrodes. Claim 2 In claim 1, the capping pattern comprises a material having etch selectivity for the lower electrodes. Claim 3 In claim 1, the capping pattern comprises a semiconductor device having etch selectivity for silicon oxide. Claim 4 In claim 1, the semiconductor device wherein the lower electrodes and the support pattern are vertically superimposed with the capping pattern. Claim 5 A semiconductor device according to claim 1, wherein the upper surfaces of the lower electrodes are located at a height lower than the upper surface of the support pattern. Claim 6 In claim 1, the capping pattern is a semiconductor device interposed between the dielectric film and the upper surface of the support pattern, and between the dielectric film and the upper surfaces of the lower electrodes. Claim 7 In claim 1, the capping pattern is a semiconductor device that covers the entire area of ​​the side of the support pattern. Claim 8 In claim 7, the semiconductor device wherein the upper surfaces of the lower electrodes are located at a height lower than the bottom surface of the support pattern. Claim 9 A semiconductor device comprising: lower electrodes on a substrate; a support pattern provided between the lower electrodes in a planar view; an upper electrode covering the lower electrodes and the support pattern; a dielectric film provided between the lower electrodes and the upper electrode and between the support pattern and the upper electrode; and a capping pattern provided between the upper surfaces of the lower electrodes and the dielectric film and between the upper surface of the support pattern and the dielectric film, wherein the upper surfaces of the lower electrodes are located at a height lower than the upper surface of the support pattern, and the capping pattern is spaced apart from the sides of each of the lower electrodes. Claim 10 In claim 9, the semiconductor device wherein the upper surfaces of the lower electrodes are located at a height lower than the bottom surface of the support pattern.

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