Semiconductor device and method for manufacturing the same

Abstract

A method for manufacturing a semiconductor device according to the concept of the present invention comprises: designing a layout, wherein the layout includes a first gate pattern, a second gate pattern, a first dummy gate pattern, a second dummy gate pattern, a third gate pattern, and a fourth gate pattern arranged sequentially in a first direction; forming first to fourth sacrificial patterns corresponding to each of the first to fourth gate patterns and first and second dummy sacrificial patterns corresponding to each of the first and second dummy gate patterns on a substrate using a first photomask manufactured using the layout; and performing optical proximity correction on the layout, wherein the performing optical proximity correction may include: measuring distances between the first to fourth sacrificial patterns and the first and second dummy sacrificial patterns that are adjacent to each other in the first direction; calculating the difference by comparing the average value of the measured distances with the average value of preset target distances, wherein the difference is a first distance; and reducing the distance between the first dummy gate pattern and the second dummy gate pattern by the first distance.

Description

Technology Field

[0001] The present invention relates to a semiconductor device and a method for manufacturing the same, and more specifically, to a semiconductor device including a field-effect transistor and a method for manufacturing the same. Background Technology

[0002] Due to characteristics such as miniaturization, multifunctionality, and / or low manufacturing costs, semiconductor devices are gaining prominence as important elements in the electronics industry. Semiconductor devices can be classified into semiconductor memory devices that store logical data, semiconductor logic devices that process logical data, and hybrid semiconductor devices that include both memory and logic elements. As the electronics industry advances, demands regarding the characteristics of semiconductor devices are steadily increasing. For example, there is a growing demand for high reliability, high speed, and / or multifunctionality. To meet these requirements, the internal structures of semiconductor devices are becoming increasingly complex, and semiconductor devices are becoming more highly integrated. The problem to be solved

[0003] The problem that the present invention aims to solve is to provide a semiconductor device including a field-effect transistor with improved electrical characteristics and reliability, and a method for manufacturing the same. means of solving the problem

[0004] A method for manufacturing a semiconductor device according to the concept of the present invention comprises: designing a layout, wherein the layout includes a first gate pattern, a second gate pattern, a first dummy gate pattern, a second dummy gate pattern, a third gate pattern, and a fourth gate pattern arranged sequentially in a first direction; forming first to fourth sacrificial patterns corresponding to each of the first to fourth gate patterns and first and second dummy sacrificial patterns corresponding to each of the first and second dummy gate patterns on a substrate using a first photomask manufactured using the layout; and performing optical proximity correction on the layout, wherein the performing optical proximity correction may include: measuring distances between the first to fourth sacrificial patterns and the first and second dummy sacrificial patterns that are adjacent to each other in the first direction; calculating the difference by comparing the average value of the measured distances with the average value of preset target distances, wherein the difference is a first distance; and reducing the distance between the first dummy gate pattern and the second dummy gate pattern by the first distance.

[0005] A method for manufacturing a semiconductor device according to another concept of the present invention comprises: designing a layout, wherein the layout includes a first standard cell and a second standard cell adjacent to each other in a first direction, wherein a first gate pattern, a second gate pattern, and a first dummy gate pattern are arranged sequentially in the first direction on the first standard cell, and a second dummy gate pattern, a third gate pattern, and a fourth gate pattern are arranged sequentially in the first direction on the second standard cell; forming first to fourth sacrificial patterns corresponding to each of the first to fourth gate patterns and first and second dummy sacrificial patterns corresponding to each of the first and second dummy gate patterns on a substrate using a photomask manufactured using the layout; and performing optical proximity correction on the layout, wherein the first dummy gate pattern and the second dummy gate pattern are adjacent to each other in the first direction, and the performing optical proximity correction comprises: measuring distances between the first to fourth sacrificial patterns and the first and second dummy sacrificial patterns adjacent to each other in the first direction. The method may include comparing the average value of the measured distances with the average value of preset target distances to determine the difference, wherein the difference is a first distance; and biasing the first dummy gate pattern toward the second dummy gate pattern by half of the first distance and biasing the second dummy gate pattern toward the first dummy gate pattern by half of the first distance.

[0006] According to another concept of the present invention, a semiconductor device comprises: a first logic cell and a second logic cell on a substrate, wherein the first logic cell and the second logic cell are spaced apart from each other in a first direction; a separation region between the first and second logic cells; a first active pattern on the first logic cell and a second active pattern on the second logic cell; a trench defined on the separation region to separate the first active pattern and the second active pattern, wherein the trench includes a first sidewall and a second sidewall facing each other; a first dummy gate electrode extending in a second direction intersecting the first direction adjacent to the first sidewall of the trench; a second dummy gate electrode extending in the second direction adjacent to the second sidewall of the trench; and a first gate electrode provided on the first active pattern spaced apart from the first dummy gate electrode. and a second gate electrode provided on the second active pattern spaced apart from the second dummy gate electrode, wherein the pitch between the first dummy gate electrode and the second dummy gate electrode may be smaller than the pitch between the first gate electrode and the first dummy gate electrode. Effects of the invention

[0007] According to the present invention, after photographing the manufactured sacrifice patterns over a large area, a large number of distances (e.g., millions to tens of millions) between adjacent sacrifice patterns and dummy sacrifice patterns near the area corresponding to the cutting pattern can be measured. Accordingly, more precise optical proximity correction can be achieved compared to photographing only a specific area of ​​the layout to measure a small number of distances (e.g., tens to hundreds) between adjacent sacrifice patterns and dummy sacrifice patterns.

[0008] In addition, according to embodiments of the present invention, the distance between adjacent dummy gate patterns can be reduced using an optical proximity correction procedure. Accordingly, a short circuit between the dummy gate electrode and the adjacent active contact can be prevented even when the finally manufactured dummy gate electrode is tilted. Furthermore, as the distance between the dummy sacrifice pattern and the sacrifice pattern decreases, the recess formed between them is formed shallowly, thereby preventing a short circuit between the dummy gate electrode and the gate electrode. Consequently, the electrical characteristics and reliability of the semiconductor device can be improved. Brief explanation of the drawing

[0009] FIG. 1 is a block diagram showing a computer system for performing semiconductor design according to embodiments of the present invention. FIG. 2 is a flowchart showing a method for designing and manufacturing a semiconductor device according to embodiments of the present invention. Figure 3 is a layout of a standard cell designed through the semiconductor device design method of Figure 2. Figure 4 is a plan view showing sacrificial patterns manufactured using the layout of Figure 3. Figure 5 is a cross-sectional view along the line A-A' of Figure 4. FIG. 6 is a flowchart for specifically explaining the second optical proximity correction step of FIG. 2. FIG. 7 shows the normal distribution graphs of the distance between sacrifice patterns and the target distance, respectively, measured according to embodiments of the present invention. Figure 8 is a layout of a standard cell designed through the semiconductor device design method of Figure 2. Figure 9 is a plan view showing sacrificial patterns manufactured using the layout of Figure 8. Figure 10 is a cross-sectional view along the line A-A' of Figure 9. FIG. 11 is a plan view for illustrating a semiconductor device according to embodiments of the present invention. FIGS. 12a to 12d are cross-sectional views along the lines A-A', B-B', C-C', and D-D' of FIG. 11, respectively. FIG. 13 is a cross-sectional view along line A-A' of FIG. 11, intended to explain a semiconductor device according to a comparative example of the present invention. FIGS. 14, FIGS. 16, FIGS. 18, FIGS. 20, FIGS. 22, and FIGS. 24 are plan views for explaining a method for manufacturing a semiconductor device according to embodiments of the present invention. FIGS. 15, FIGS. 17a, FIGS. 19a, FIGS. 21a, FIGS. 23a, and FIGS. 25a are cross-sectional views along the line A-A' of FIGS. 14, FIGS. 16, FIGS. 18, FIGS. 20, FIGS. 22, and FIGS. 24, respectively. FIGS. 17b, FIGS. 19b, FIGS. 21b, FIGS. 23b, and FIGS. 25b are cross-sectional views along the line B-B' of FIGS. 16, FIGS. 18, FIGS. 20, FIGS. 22, and FIGS. 24, respectively. FIGS. 21c, FIGS. 23c, and FIGS. 25c are cross-sectional views along the C-C' line of FIGS. 20, FIGS. 22, and FIGS. 24, respectively. FIGS. 21d, FIGS. 23d, and FIGS. 25d are cross-sectional views along the line D-D' of FIGS. 20, FIGS. 22, and FIGS. 24, respectively. FIGS. 26a to 26d are cross-sectional views along the lines A-A', B-B', C-C', and D-D' of FIG. 4, respectively. Specific details for implementing the invention

[0010] FIG. 1 is a block diagram showing a computer system for performing semiconductor design according to embodiments of the present invention. Referring to FIG. 1, the computer system may include a CPU (10), a working memory (30), an input / output device (50), and an auxiliary storage device (70). Here, the computer system may be provided as a dedicated device for layout design of the present invention. Furthermore, the computer system may be equipped with various design and verification simulation programs.

[0011] The CPU (10) can execute software (applications, operating systems, device drivers) to be executed in a computer system. The CPU (10) can execute an operating system loaded into working memory (30). The CPU (10) can execute various applications to be run on the operating system. For example, the CPU (10) can execute a layout design tool (32), a placement and routing tool (34), and / or an OPC tool (36) loaded into working memory (30).

[0012] The operating system or the application programs may be loaded into the working memory (30). When booting the computer system, the operating system image (not shown) stored in the auxiliary storage device (70) may be loaded into the working memory (30) according to the boot sequence. The various input / output operations of the computer system may be supported by the operating system. Likewise, the application programs may be loaded into the working memory (30) for selection by the user or for providing basic services.

[0013] A layout design tool (32) for designing a layout can be loaded into working memory (30) from auxiliary storage (70). A placement and routing tool (34) for placing designed standard cells and routing the placed standard cells can be loaded into working memory (30) from auxiliary storage (70). An OPC tool (36) for performing Optical Proximity Correction (OPC) on the designed layout data can be loaded into working memory (30) from auxiliary storage (70).

[0014] The layout design tool (32) may be equipped with a bias function that can change the shape and position of specific layout patterns differently from what is defined by design rules. The layout design tool (32) may perform a Design Rule Check (DRC) under the changed bias data conditions. The working memory (30) may be a volatile memory such as SRAM (Static Random Access Memory) or DRAM (Dynamic Random Access Memory), or a non-volatile memory such as PRAM, MRAM, ReRAM, FRAM, or NOR flash memory.

[0015] The input / output device (50) controls user input and output from user interface devices. For example, the input / output device (50) may be equipped with a keyboard or a monitor to receive information from the designer. Using the input / output device (50), the designer may receive information regarding semiconductor regions or data paths that require adjusted operating characteristics. Additionally, the processing process and processing results of the OPC tool (36) may be displayed through the input / output device (50).

[0016] An auxiliary storage device (70) is provided as a storage medium for a computer system. The auxiliary storage device (70) can store application programs, operating system images, and various data. The auxiliary storage device (70) may be provided as a memory card (MMC, eMMC, SD, MicroSD, etc.) or a hard disk drive (HDD). The auxiliary storage device (70) may include NAND-type Flash memory having a large storage capacity. Alternatively, the auxiliary storage device (70) may include next-generation non-volatile memory such as PRAM, MRAM, ReRAM, FRAM, or NOR Flash memory.

[0017] The system interconnect (90) may be a system bus for providing a network within a computer system. Through the system interconnect (90), the CPU (10), working memory (30), input / output device (50), and auxiliary storage device (70) can be electrically connected and exchange data with each other. However, the configuration of the system interconnect (90) is not limited to the description above and may further include arbitration means for efficient management.

[0019] FIG. 2 is a flowchart showing a method for designing and manufacturing a semiconductor device according to embodiments of the present invention.

[0020] Referring to FIG. 2, a high-level design of a semiconductor integrated circuit can be performed using the computer system described with reference to FIG. 1 (S10). High-level design can mean describing the integrated circuit to be designed in a high-level computer language. For example, a high-level language such as C can be used. Circuits designed by the high-level design can be expressed more specifically through Register Transfer Level (RTL) coding or simulation. Furthermore, the code generated by Register Transfer Level coding can be converted into a netlist and synthesized into a complete semiconductor device. The synthesized schematic circuit is verified by a simulation tool, and an adjustment process may be performed based on the verification results.

[0021] A layout design for implementing a logically completed semiconductor contact circuit on a silicon substrate can be performed (S20). For example, the layout design can be performed by referring to a schematic circuit synthesized in a higher-level design or a corresponding netlist.

[0022] Cell libraries for layout design may also include information regarding the operation, speed, and power consumption of standard cells. Cell libraries for representing specific gate-level circuits as layouts are defined in most layout design tools. Layout can be a procedure for defining the shape or size of patterns to constitute the transistors and metal wiring to be actually formed on a silicon substrate. For example, to actually form an inverter circuit on a silicon substrate, layout patterns such as PMOS, NMOS, N-WELL, gate electrodes, and metal wiring to be placed thereon can be appropriately arranged. To do this, a suitable one can first be searched for and selected from among the inverters already defined in the cell library.

[0023] Placement and routing of various standard cells stored in the Cell Library can be performed (S30). Specifically, standard cells can be placed two-dimensionally. Upper wiring (routing wiring) can be placed on the placed standard cells. By performing routing, the placed standard cells can be connected to each other according to the design. Placement and routing of standard cells can be performed automatically by a placement and routing tool (34).

[0024] After routing, verification of the layout can be performed to check for any violations of design rules. Verification items may include Design Rule Check (DRC) to verify that the layout is properly aligned with design rules, Electronic Rule Check (ERC) to verify that there are no electrical interruptions internally, and Layout vs Schematic (LVS) to check that the layout matches the gate-level netlist.

[0025] A first Optical Proximity Correction (OPC) procedure may be performed (S40). Layout patterns obtained through layout design can be implemented on a silicon substrate using a photolithography process. At this time, optical proximity correction may be a technique for correcting distortion phenomena that may occur during the photolithography process. That is, through optical proximity correction, distortion phenomena such as refraction or process effects caused by light characteristics during exposure using the laid-out patterns can be corrected. While performing optical proximity correction, the shape and position of the designed layout patterns may be slightly changed (biased).

[0026] A preliminary photomask can be fabricated based on the layout modified by the first optical proximity correction (S50). Generally, the preliminary photomask can be fabricated by using a chrome film applied on a glass substrate to depict layout patterns.

[0027] Sacrificial patterns and dummy sacrificial patterns can be manufactured using the generated preliminary photomask (S60). In the manufacturing process of a semiconductor device using the preliminary photomask, various types of exposure and etching processes can be repeated. Through these processes, the shapes of the sacrificial patterns configured during the layout design can be sequentially formed on the silicon substrate.

[0028] A second optical proximity correction procedure may be performed (S70). The second optical proximity correction procedure may be a procedure that measures the distance between the manufactured sacrifice patterns and dummy sacrifice patterns, creates a graph in the form of a normal distribution, and then compares this with the target distance to change (bias) the shape and position of the designed layout patterns. The second optical proximity correction procedure will be described in more detail later with reference to FIGS. 6 and FIGS. 7.

[0029] A photomask can be fabricated based on a layout modified by a second optical proximity correction (S80). Generally, the photomask can be fabricated by using a chrome film applied on a glass substrate to depict layout patterns.

[0030] A semiconductor device can be manufactured using the generated photomask (S90). In the manufacturing process of the semiconductor device using the photomask, various types of exposure and etching processes can be repeated. Through these processes, the shapes of patterns configured during the layout design can be sequentially formed on a silicon substrate.

[0032] FIG. 3 is a layout of a standard cell designed through the semiconductor device design method of FIG. 2. Specifically, FIG. 3 may be a layout before the second optical proximity correction procedure (S70) is performed.

[0033] Referring to FIG. 3, the layout of the designed standard cell may include a first standard cell (STD1) and a second standard cell (STD2) spaced apart from each other in a second direction (D2). Each of the first standard cell (STD1) and the second standard cell (STD2) may include gate patterns (GEa) and dummy gate patterns (DGEa). The layout may further include a first active region (PRa) and a second active region (NRa) traversing the first standard cell (STD1) and the second standard cell (STD2). The layout may further include cutting patterns (CPa) placed between the first standard cell (STD1) and the second standard cell (STD2). Furthermore, the layout may further include other layout patterns (e.g., wiring patterns, via patterns, active contact patterns, etc.). For the sake of simplification of the drawing, other layout patterns within the standard cells shown in FIG. 3 (e.g., wiring patterns, via patterns, active contact patterns, etc.) have been omitted.

[0034] The first active region (PRa) may extend in the second direction (D2) to cross the first standard cell (STD1) and the second standard cell (STD2). The second active region (NRa) may extend in the second direction (D2) to cross the first standard cell (STD1) and the second standard cell (STD2). The first active region (PRa) and the second active region (NRa) may be spaced apart from each other in the first direction (D1). The first active region (PRa) and the second active region (NRa) may define the PMOSFET region (PR) and the NMOSFET region (NR) to be described later.

[0035] Gate patterns (GEa) extend in a first direction (D1) and may be arranged along a second direction (D2) that intersects the first direction (D1). Gate patterns (GEa) may be arranged with a first pitch (P1). The term “pitch” as used in the present invention may be the distance between the center line of the first pattern and the center line of the second pattern adjacent to the first pattern. Gate patterns (GEa) may define the sacrificial patterns (PP) and gate electrodes (GE) described later.

[0036] Dummy gate patterns (DGEa) extend in a first direction (D1) and can be arranged along a second direction (D2) that intersects the first direction (D1). Dummy gate patterns (DGEa) on a first standard cell (STD1) can be adjacent to dummy gate patterns (DGEa) on a second standard cell (STD2). Dummy gate patterns (DGEa) can be arranged at a first pitch (P1). Adjacent dummy gate patterns (DGEa) and gate patterns (GEa) can be arranged at a first pitch (P1). Dummy gate patterns (DGEa) can define dummy sacrifice patterns (DPP) and dummy gate electrodes (DGE) to be described later.

[0037] A cutting pattern (CPa) may be placed between the first standard cell (STD1) and the second standard cell (STD2). The first standard cell (STD1) and the second standard cell (STD2) may be separated from each other by the cutting pattern (CPa). The cutting pattern (CPa) may define the third trench (TR3) to be described later. A portion of the dummy gate pattern (DGEa) may overlap vertically with the cutting pattern (CPa).

[0038] The distance between adjacent gate patterns (GEa), the distance between adjacent dummy gate patterns (DGEa), and the distance between adjacent gate patterns (GEa) and dummy gate patterns (DGEa) can each be defined as a first distance (DI1). The width of each of the gate patterns (GEa) and dummy gate patterns (DGEa) can be defined as a second distance (DI2). The width of the cutting pattern (CPa) can be defined as a third distance (DI3). The first pitch (P1) can be substantially equal to the sum of the first distance (DI1) and the second distance (DI2). The first pitch (P1) can be substantially equal to the third distance (DI3).

[0039] FIG. 4 is a plan view showing sacrificial patterns manufactured using the layout of FIG. 3. FIG. 5 is a cross-sectional view along the line A-A' of FIG. 4. Specifically, FIG. 4 and FIG. 5 show sacrificial patterns manufactured using the layout of FIG. 3.

[0040] Referring to FIGS. 4 and 5, a first logic cell (LC1) and a second logic cell (LC2) may be provided on a substrate (100). The first logic cell (LC1) and the second logic cell (LC2) may be arranged in a second direction (D2). The substrate (100) may include a PMOSFET region (PR) and an NMOSFET region (NR). Each of the first logic cell (LC1) and the second logic cell (LC2) may include a PMOSFET region (PR) and an NMOSFET region (NR) extending in the second direction (D2).

[0041] A separation region (IR) may be disposed between the first and second logic cells (LC1, LC2). A third trench (TR3) may be formed on the substrate (100) on the separation region (IR). The third trench (TR3) may separate the first logic cell (LC1) and the second logic cell (LC2) from each other. The third trench (TR3) may separate the second logic cell (LC2) from the first logic cell (LC1) in a second direction (D2).

[0042] Sacrificial layers (SAL) and active layers (ACL) may be provided alternately stacked on a substrate (100). The sacrificial layers (SAL) may include one of silicon (Si), germanium (Ge), and silicon-germanium (SiGe), and the active layers (ACL) may include the other of silicon (Si), germanium (Ge), and silicon-germanium (SiGe).

[0043] A first active pattern (AP1) may be provided on a PMOSFET region (PR). A second active pattern (AP2) may be provided on an NMOSFET region (NR). Each of the first active pattern (AP1) and the second active pattern (AP2) may include sacrificial layers (SAL) and active layers (ACL) alternately stacked on top of each other.

[0044] The third trench (TR3) can separate a first active pattern (AP1) into a pair of first active patterns (AP1) adjacent to each other in the second direction (D2). The third trench (TR3) can separate a second active pattern (AP2) into a pair of second active patterns (AP2) adjacent to each other in the second direction (D2). The third trench (TR3) may include a first sidewall (SW1) adjacent to a first logic cell (LC1) and a second sidewall (SW2) adjacent to a second logic cell (LC2). The first sidewall (SW1) and the second sidewall (SW2) may face each other.

[0045] On the substrate (100), sacrifice patterns (PP) and dummy sacrifice patterns (DPP) can be formed across the first and second active patterns (AP1, AP2). Each of the sacrifice patterns (PP) and dummy sacrifice patterns (DPP) can be formed in a line shape or a bar shape extending in a first direction (D1). The sacrifice patterns (PP) and dummy sacrifice patterns (DPP) can be arranged along a second direction (D2) with a first pitch (P1).

[0046] Dummy sacrifice patterns (DPP) may be adjacent to the first sidewall (SW1) and the second sidewall (SW2) of the third trench (TR3), respectively. Dummy sacrifice patterns (DPP) may be positioned adjacent to the separation region (IR). The dummy sacrifice pattern (DPP) may include a body portion (UP) on the substrate (100) and a vertical portion (VP) extending vertically downward from the body portion (UP) along the first sidewall (SW1) or the second sidewall (SW2) of the third trench (TR3).

[0047] The body portion (UP) may be tilted in a direction away from the third trench (TR3). The body portion (UP) may be tilted in a direction toward the adjacent sacrificial pattern (PP). The angle formed by the side wall of the body portion (UP) and the upper surface of the substrate (100) may be a first angle (θ1). The first angle (θ1) may be an acute angle. For example, the first angle (θ1) may be 60° to 85°.

[0048] The distance between the body portions (UP) of adjacent dummy sacrifice patterns (DPP) can be defined as a fourth distance (DI4). The fourth distance (DI4) may increase as it moves toward the third direction (D3). The fourth distance (DI4) may be greater than the first distance (DI1). The distance between the vertical portions (VP) of adjacent dummy sacrifice patterns (DPP) may be substantially the same as the first distance (DI1). The maximum distance between adjacent sacrifice patterns (PP) and the body portions (UP) of adjacent dummy sacrifice patterns (DPP) may be substantially the same as the first distance (DI1).

[0049] FIG. 6 is a flowchart for specifically explaining the second optical proximity correction step of FIG. 2.

[0050] The second optical proximity correction (S70) may include the step of measuring the distances between the sacrifice patterns and dummy sacrifice patterns manufactured using a preliminary photomask (S71). Near the third trench (TR3), the distance between adjacent sacrifice patterns (PP), the distance between adjacent dummy sacrifice patterns (DPP), and the distance between adjacent sacrifice patterns (PP) and dummy sacrifice patterns (DPP) can be measured in large quantities and represented as a graph in the form of a normal distribution.

[0051] For the sake of simplification of the drawing, only two cutting patterns (CPa) are shown in FIG. 3, but the layout may include a large number of cutting patterns (CPa). After photographing the manufactured sacrifice patterns (PP) using the layout over a large area, a large number of distances (e.g., millions to tens of millions) between adjacent sacrifice patterns (PP) and dummy sacrifice patterns (DPP) near the area corresponding to the cutting pattern (CPa) can be measured. Accordingly, more precise optical proximity correction may be possible compared to photographing only a specific area of ​​the layout to measure a small number of distances (e.g., tens to hundreds) between adjacent sacrifice patterns (PP) and dummy sacrifice patterns (DPP).

[0052] A procedure to compare the measured distances with the target distance may be performed (S72). FIG. 7 shows the normal distribution graphs of the distance between sacrifice patterns and the target distance, respectively, measured according to embodiments of the present invention.

[0053] Referring to FIG. 7, it can be seen that the average value of the distances between adjacent sacrifice patterns (PP) and dummy sacrifice patterns (PP) measured in the normal distribution graph differs from the average value of the target distances by a fifth distance (DI5). Here, the target distances represent the distance values ​​between the ideal sacrifice patterns (PP) and dummy sacrifice patterns (DPP) targeted during manufacturing. Specifically, the target distances represent the distance values ​​in the case where the problem described with reference to FIG. 13, as described below, does not occur.

[0054] A procedure to correct the layout by the difference between the average value of the distances between adjacent sacrifice patterns and the average value of the target distances may be performed (S73). FIG. 8 is a layout of a standard cell designed through the semiconductor device design method of FIG. 2. Specifically, FIG. 8 may be a layout designed by applying the second optical proximity correction procedure (S70).

[0055] Referring to FIG. 8, the distance between adjacent dummy gate patterns (DGEa) can be reduced by a fifth distance (DI5). That is, through a second optical proximity correction procedure, the distance between dummy gate patterns (DGEa) can be reduced by a fifth distance (DI5), which is the difference value from the target distance from the layout described with reference to FIG. 3. Accordingly, the distance between dummy gate patterns (DGEa) can be biased by DI1-DI5. The distance between a dummy gate pattern (DGEa) and an adjacent gate pattern (GEa) can be biased by DI1+DI5 / 2. In other words, a dummy gate pattern (DGEa) placed on the first standard cell (STD1) can be biased by half of the fifth distance (DI5 / 2) in the direction toward the second standard cell (STD2). A dummy gate pattern (DGEa) placed on the second standard cell (STD2) can be biased by half of the fifth distance (DI5 / 2) in the direction toward the first standard cell (STD1).

[0056] The pitch between dummy gate patterns (DGEa) can be biased to a second pitch (P2). The pitch between a dummy gate pattern (DGEa) and an adjacent gate pattern (GEa) can be biased to a third pitch (P3). The second pitch (P2) can be smaller than the first pitch (P1). The third pitch (P3) can be larger than the first pitch (P1). The second pitch (P2) can be smaller than the first pitch (P1) by a fifth distance (DI5). The third pitch (P3) can be larger than the first pitch (P1) by half of the fifth distance (DI5 / 2). That is, P2 + 2 X P3 = 3 X P1.

[0057] FIG. 9 is a plan view showing sacrificial patterns manufactured using the layout of FIG. 8. FIG. 10 is a cross-sectional view along the line A-A' of FIG. 9. Specifically, FIG. 9 and FIG. 10 show sacrificial patterns manufactured using the layout of FIG. 8.

[0058] Referring to FIGS. 9 and 10, as described with reference to FIG. 8, the distance between adjacent dummy sacrifice patterns (DPP) is reduced by a fifth distance (DI5), and the distance between a dummy sacrifice pattern (DPP) and an adjacent sacrifice pattern (PP) can be increased by half of the fifth distance (DI5) (DI5 / 2). At this time, the distance between the body portions (UP) of adjacent dummy sacrifice patterns (DPP) is DI4-DI5, and the maximum value of DI4-DI5 may be similar to or the same as the first distance (DI1).

[0059] According to embodiments of the present invention, the distance between adjacent dummy gate patterns (DGEa) in the layout can be reduced using an optical proximity correction procedure. Accordingly, a short circuit between the active contact and the dummy gate electrode that may occur when the body portion (UP) of the dummy sacrifice patterns (DPP) is tilted and the distance to the adjacent sacrifice pattern (PP) is reduced can be prevented. In addition, as the distance between the dummy sacrifice pattern (DPP) and the sacrifice pattern (PP) is reduced, the recess formed between them is formed shallowly, thereby preventing a short circuit between the dummy gate electrode and the gate electrode (see FIG. 13). As a result, the electrical characteristics and reliability of the semiconductor device can be improved.

[0061] FIG. 11 is a plan view illustrating a semiconductor device according to embodiments of the present invention. FIG. 12a to 12d are cross-sectional views along lines A-A', B-B', C-C', and D-D' of FIG. 11, respectively. Specifically, the semiconductor devices of FIG. 11 and FIG. 12a to 12d are semiconductor devices manufactured using the layout of FIG. 8.

[0062] Referring to FIGS. 11 and FIGS. 12a through 12d, a first logic cell (LC1) and a second logic cell (LC2) may be provided on a substrate (100). The first logic cell (LC1) and the second logic cell (LC2) may be arranged in a second direction (D2). Each of the first and second logic cells (LC1, LC2) may form a logic circuit. For example, logic transistors forming a logic circuit may be disposed on each of the first and second logic cells (LC1, LC2). In this embodiment, the first and second logic cells (LC1, LC2) may include the same or different logic circuits.

[0063] The substrate (100) may include a PMOSFET region (PR) and an NMOSFET region (NR). Each of the first logic cell (LC1) and the second logic cell (LC2) may include a PMOSFET region (PR) and an NMOSFET region (NR) extending in a second direction (D2). The substrate (100) may be a semiconductor substrate. For example, the substrate (100) may be a silicon substrate or a germanium substrate, or a Silicon On Insulator (SOI) substrate.

[0064] A PMOSFET region (PR) and an NMOSFET region (NR) can be defined by a second trench (TR2) formed on the upper part of the substrate (100). In other words, the second trench (TR2) can be located between the PMOSFET region (PR) and the NMOSFET region (NR). The PMOSFET region (PR) and the NMOSFET region (NR) can be spaced apart from each other in a first direction (D1) with the second trench (TR2) in between.

[0065] A first active pattern (AP1) and a second active pattern (AP2) can be defined by a first trench (TR1) formed on the upper surface of the substrate (100). The first active pattern (AP1) and the second active pattern (AP2) can be provided on the PMOSFET region (PR) and the NMOSFET region (NR), respectively. The first trench (TR1) may be shallower than the second trench (TR2). The first and second active patterns (AP1, AP2) may extend in a second direction (D2). The first and second active patterns (AP1, AP2) may be vertically protruding portions as part of the substrate (100).

[0066] The substrate (100) may include a separation region (IR) between the first and second logic cells (LC1, LC2). A third trench (TR3) may be formed on the substrate (100) on the separation region (IR). The third trench (TR3) may separate the first logic cell (LC1) and the second logic cell (LC2) from each other. The third trench (TR3) may separate the second logic cell (LC2) from the first logic cell (LC1) in a second direction (D2).

[0067] The third trench (TR3) can separate a single first active pattern (AP1) into a pair of first active patterns (AP1) adjacent to each other in the second direction (D2). The third trench (TR3) can separate a single second active pattern (AP2) into a pair of second active patterns (AP2) adjacent to each other in the second direction (D2). The third trench (TR3) may include a first sidewall (SW1) adjacent to the first logic cell (LC1) and a second sidewall (SW2) adjacent to the second logic cell (LC2). The first sidewall (SW1) and the second sidewall (SW2) may face each other in the second direction (D2) with the third trench (TR3) in between.

[0068] The device isolation layer (ST) can fill the first to third trenches (TR1, TR2, TR3). The device isolation layer (ST) may comprise silicon oxide. The upper portions of the first and second active patterns (AP1, AP2) may protrude vertically over the device isolation layer (ST). The device isolation layer (ST) may not cover the upper portions of the first and second active patterns (AP1, AP2). The device isolation layer (ST) may cover the lower sidewalls of the first and second active patterns (AP1, AP2). The device isolation layer (ST) may directly cover the lower portions of the first sidewall (SW1) and the second sidewall (SW2) of the third trench (TR3).

[0069] The first active pattern (AP1) may include a first channel pattern (CH1) on its upper surface. The second active pattern (AP2) may include a second channel pattern (CH2) on its upper surface. Each of the first channel pattern (CH1) and the second channel pattern (CH2) may include a first semiconductor pattern (SP1), a second semiconductor pattern (SP2), and a third semiconductor pattern (SP3) that are sequentially stacked. The first to third semiconductor patterns (SP1, SP2, SP3) may be spaced apart from each other in a vertical direction (i.e., a third direction (D3)).

[0070] Each of the first to third semiconductor patterns (SP1, SP2, SP3) may comprise silicon (Si), germanium (Ge), or silicon-germanium (SiGe). Preferably, each of the first to third semiconductor patterns (SP1, SP2, SP3) may comprise crystalline silicon.

[0071] A plurality of first recesses (RS1) may be formed on the upper portion of a first active pattern (AP1). First source / drain patterns (SD1) may be provided within each of the first recesses (RS1). The first source / drain patterns (SD1) may be impurity regions of a first conductivity type (e.g., p-type). A first channel pattern (CH1) may be interposed between a pair of first source / drain patterns (SD1). In other words, stacked first to third semiconductor patterns (SP1, SP2, SP3) may connect a pair of first source / drain patterns (SD1) to each other.

[0072] A plurality of second recesses (RS2) may be formed on the upper portion of the second active pattern (AP2). Second source / drain patterns (SD2) may be provided within each of the second recesses (RS2). The second source / drain patterns (SD2) may be impurity regions of a second conductivity type (e.g., n-type). A second channel pattern (CH2) may be interposed between a pair of second source / drain patterns (SD2). In other words, stacked first to third semiconductor patterns (SP1, SP2, SP3) may connect a pair of second source / drain patterns (SD2) to each other.

[0073] The first and second source / drain patterns (SD1, SD2) may be epitaxial patterns formed by an optional epitaxial growth (SEG) process. For example, the upper surface of each of the first and second source / drain patterns (SD1, SD2) may be located at substantially the same level as the upper surface of the third semiconductor pattern (SP3). For another example, the upper surface of each of the first and second source / drain patterns (SD1, SD2) may be higher than the upper surface of the third semiconductor pattern (SP3).

[0074] The first source / drain patterns (SD1) may include a semiconductor element (e.g., SiGe) having a lattice constant greater than that of the semiconductor element of the substrate (100). Thus, a pair of first source / drain patterns (SD1) can provide compressive stress to the first channel pattern (CH1) between them. The second source / drain patterns (SD2) may include the same semiconductor element (e.g., Si) as the substrate (100).

[0075] Dummy gate electrodes (DGE) may be provided adjacent to the first sidewall (SW1) and the second sidewall (SW2) of the third trench (TR3), respectively. The dummy gate electrode (DGE) may extend in a first direction (D1) and cross the first active pattern (AP1) and the second active pattern (AP2). The dummy gate electrode (DGE) may be positioned adjacent to the isolation region (IR). The dummy gate electrode (DGE) may not be connected to the gate contact (GC) described later.

[0076] A dummy gate electrode (DGE) may include a body portion (UP) on the substrate (100), a vertical portion (VP) extending vertically downward from the body portion (UP) along the first sidewall (SW1) or the second sidewall (SW2) of the third trench (TR3), and protrusions (PT) protruding from the vertical portion (VP) toward an adjacent first source / drain pattern (SD1) or second source / drain pattern (SD2). The protrusions (PT) of the dummy gate electrode (DGE) adjacent to the PMOSFET region (PR) may be adjacent to the first source / drain pattern (SD1). The protrusions (PT) of the dummy gate electrode (DGE) adjacent to the NMOSFET region (NR) may be adjacent to an inner spacer (IP) to be described later.

[0077] Dummy gate spacers (DGS) may be provided on both sidewalls of the dummy gate electrode (DGE). The dummy gate spacers (DGS) may comprise the same material as the gate spacers (GS) described later. Any one of the dummy gate spacers (DGS) on the dummy gate electrode (DGE) may extend vertically along either the first sidewall (SW1) or the second sidewall (SW2) of the third trench (TR3) and come into contact with the upper surface of the device isolation film (ST).

[0078] A dummy gate insulating film (DGI) may be interposed between the dummy gate electrode (DGE) and the first channel pattern (CH1), and between the dummy gate electrode (DGE) and the second channel pattern (CH2). The dummy gate insulating film (DGI) may contain the same material as the gate insulating film (GI) described later.

[0079] Gate electrodes (GE) extending in a first direction (D1) across the first and second active patterns (AP1, AP2) may be provided. Each gate electrode (GE) may be vertically overlapped with the first and second channel patterns (CH1, CH2). The gate electrodes (GE) may be spaced apart from a dummy gate electrode (DGE) in the first direction (D1).

[0080] The gate electrode (GE) may include a first portion (PO1) interposed between the substrate (100) and the first semiconductor pattern (SP1), a second portion (PO2) interposed between the first semiconductor pattern (SP1) and the second semiconductor pattern (SP2), a third portion (PO3) interposed between the second semiconductor pattern (SP2) and the third semiconductor pattern (SP3), and a fourth portion (PO4) on the third semiconductor pattern (SP3).

[0081] Referring again to FIG. 2a, the first to third portions (PO1, PO2, PO3) of the gate electrode (GE) on the PMOSFET region (PR) may have different widths. For example, the maximum width of the third portion (PO3) in the second direction (D2) may be greater than the maximum width of the second portion (PO2) in the second direction (D2). The maximum width of the first portion (PO1) in the second direction (D2) may be greater than the maximum width of the third portion (PO3) in the second direction (D2).

[0082] Referring again to FIG. 2d, the gate electrode (GE) may be provided on the top surface (TS), bottom surface (BS), and both sidewalls (SIW) of each of the first to third semiconductor patterns (SP1, SP2, SP3). In other words, the logic transistor according to the present embodiment may be a three-dimensional field effect transistor (e.g., MBCFET (Multi Bridge Channel Field Effect Transistor)) in which the gate electrode (GE) surrounds the channel three-dimensionally.

[0083] Referring again to FIGS. 1 and FIGS. 2a through 2d, a pair of gate spacers (GS) may be disposed on both sidewalls of the fourth portion (PO4) of the gate electrode (GE). The gate spacers (GS) may extend along the gate electrode (GE) in a first direction (D1). The upper surfaces of the gate spacers (GS) may be higher than the upper surface of the gate electrode (GE). The upper surfaces of the gate spacers (GS) may co-plane with the upper surface of the first interlayer insulating film (110) to be described later. The gate spacers (GS) may include at least one of SiCN, SiCON, and SiN. As another example, the gate spacers (GS) may include a multi-layer composed of at least two of SiCN, SiCON, and SiN.

[0084] A gate capping pattern (GP) may be provided on the gate electrode (GE) and the dummy gate electrode (DGE), respectively. The gate capping pattern (GP) may extend in a first direction (D1) along the gate electrode (GE) or the dummy gate electrode (DGE). The gate capping pattern (GP) may include a material that is etch selective with respect to the first and second interlayer insulating films (110, 120) described later. Specifically, the gate capping pattern (GP) may include at least one of SiON, SiCN, SiCON, and SiN.

[0085] A gate insulating film (GI) may be interposed between the gate electrode (GE) and the first channel pattern (CH1) and between the gate electrode (GE) and the second channel pattern (CH2). The gate insulating film (GI) may cover the top surface (TS), bottom surface (BS), and both sidewalls (SIW) of each of the first to third semiconductor patterns (SP1, SP2, SP3). The gate insulating film (GI) may cover the top surface of the device isolation film (ST) below the gate electrode (GE) (see FIG. 2d).

[0086] In one embodiment of the present invention, the gate insulating film (GI) and the dummy gate insulating film (DGI) may each include a silicon oxide film, a silicon oxynitride film and / or a high dielectric film. The high dielectric film may include a high dielectric constant material having a higher dielectric constant than that of the silicon oxide film. As an example, the high dielectric constant material may include at least one of hafnium oxide, hafnium silicon oxide, hafnium zirconium oxide, hafnium tantalum oxide, lanthanum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, lithium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate.

[0087] In another embodiment, the semiconductor device of the present invention may include a negative capacitance (NC) FET using a negative capacitor. For example, the gate insulating film (GI) and the dummy gate insulating film (DGI) may each include a ferroelectric material film having ferroelectric properties and a paraelectric material film having paraelectric properties.

[0088] Ferroelectric material films can have negative capacitance. Paraelectric material films can have positive capacitance. For example, if two or more capacitors are connected in series and the capacitance of each capacitor is positive, the total capacitance decreases compared to the capacitance of each individual capacitor. Conversely, if at least one of the capacitances of the two or more capacitors connected in series has a negative value, the total capacitance can have a positive value and be greater than the absolute value of each individual capacitance.

[0089] When a ferroelectric material film with negative capacitance and a paraelectric material film with positive capacitance are connected in series, the total capacitance value of the series-connected ferroelectric material film and paraelectric material film can increase. By utilizing the increase in the total capacitance value, a transistor containing a ferroelectric material film can have a subthreshold swing (SS) of less than 60 mV / decade at room temperature.

[0090] Ferroelectric material films may have ferroelectric properties. Ferroelectric material films may include, for example, at least one of hafnium oxide, hafnium zirconium oxide, barium strontium titanium oxide, barium titanium oxide, and lead zirconium titanium oxide. Here, as an example, hafnium zirconium oxide may be a material in which zirconium (Zr) is doped into hafnium oxide. As another example, hafnium zirconium oxide may be a compound of hafnium (Hf), zirconium (Zr), and oxygen (O).

[0091] The ferroelectric material film may further include a doped dopant. For example, the dopant may include at least one of aluminum (Al), titanium (Ti), niobium (Nb), lanthanum (La), yttrium (Y), magnesium (Mg), silicon (Si), calcium (Ca), cerium (Ce), dysprosium (Dy), erbium (Er), gadolinium (Gd), germanium (Ge), scandium (Sc), strontium (Sr), and tin (Sn). Depending on which ferroelectric material the ferroelectric material film contains, the type of dopant included in the ferroelectric material film may vary.

[0092] When the ferroelectric material film contains hafnium oxide, the dopant included in the ferroelectric material film may include, for example, at least one of gadolinium (Gd), silicon (Si), zirconium (Zr), aluminum (Al), and yttrium (Y).

[0093] When the dopant is aluminum (Al), the ferroelectric material film may contain 3 to 8 at% (atomic %) of aluminum. Here, the ratio of the dopant may be the ratio of aluminum to the sum of hafnium and aluminum.

[0094] When the dopant is silicon (Si), the ferroelectric material film may contain 2 to 10 at% silicon. When the dopant is yttrium (Y), the ferroelectric material film may contain 2 to 10 at% yttrium. When the dopant is gadolinium (Gd), the ferroelectric material film may contain 1 to 7 at% gadolinium. When the dopant is zirconium (Zr), the ferroelectric material film may contain 50 to 80 at% zirconium.

[0095] The paraelectric material film may have paraelectric properties. The paraelectric material film may include, for example, at least one of silicon oxide and a metal oxide having a high dielectric constant. The metal oxide included in the paraelectric material film may include, for example, at least one of hafnium oxide, zirconium oxide, and aluminum oxide, but is not limited thereto.

[0096] Ferroelectric and paraelectric film layers may contain the same material. Ferroelectric film layers possess ferroelectric properties, whereas paraelectric film layers may not. For example, if both ferroelectric and paraelectric film layers contain hafnium oxide, the crystal structure of the hafnium oxide contained in the ferroelectric film layer is different from the crystal structure of the hafnium oxide contained in the paraelectric film layer.

[0097] The ferroelectric material film may have a thickness that exhibits ferroelectric properties. The thickness of the ferroelectric material film may be, for example, 0.5 to 10 nm, but is not limited thereto. Since the critical thickness at which ferroelectric properties are exhibited may vary for each ferroelectric material, the thickness of the ferroelectric material film may vary depending on the ferroelectric material.

[0098] For example, the gate insulating film (GI) and the dummy gate insulating film (DGI) may each include a single ferroelectric material film. For another example, the gate insulating film (GI) and the dummy gate insulating film (DGI) may each include a plurality of ferroelectric material films spaced apart from each other. The gate insulating film (GI) and the dummy gate insulating film (DGI) may each have a stacked film structure in which a plurality of ferroelectric material films and a plurality of paraelectric material films are alternately stacked.

[0099] The gate electrode (GE) may include a first metal pattern and a second metal pattern on the first metal pattern. The first metal pattern may be provided on a gate insulating film (GI) and may be adjacent to first to third semiconductor patterns (SP1, SP2, SP3). The first metal pattern may include a work function metal that controls the threshold voltage of the transistor. By controlling the thickness and composition of the first metal pattern, a desired threshold voltage of the transistor can be achieved. For example, the first to third portions (PO1, PO2, PO3) of the gate electrode (GE) may be composed of the first metal pattern which is a work function metal. The dummy gate electrode (DGE) may also have a structure substantially identical or similar to that of the gate electrode (GE).

[0100] The first metal pattern may include a metal nitride film. For example, the first metal pattern may include at least one metal selected from the group consisting of titanium (Ti), tantalum (Ta), aluminum (Al), tungsten (W), and molybdenum (Mo), and nitrogen (N). Furthermore, the first metal pattern may further include carbon (C). The first metal pattern may include a plurality of stacked work function metal films.

[0101] The second metal pattern may include a metal having lower resistance than the first metal pattern. For example, the second metal pattern may include at least one metal selected from the group consisting of tungsten (W), aluminum (Al), titanium (Ti), and tantalum (Ta). For example, the fourth portion (PO4) of the gate electrode (GE) may include the first metal pattern and the second metal pattern on the first metal pattern.

[0102] The pitch between adjacent gate electrodes (GE) may be a first pitch (P1). The pitch between adjacent dummy gate electrodes (DGE) may be a second pitch (P2). The pitch between a gate electrode (GE) and an adjacent dummy gate electrode (DGE) may be a third pitch (P3). The second pitch (P2) may be smaller than the first pitch (P1). The third pitch (P3) may be larger than the first pitch (P1). Here, P2 + 2 X P3 = 3 X P1. The first to third pitches (P1, P2, P3) may be substantially the same as those described with reference to FIGS. 8 to 10.

[0103] The width between adjacent gate electrodes (GE) may be a first width (W1). The width of the gate electrode (GE) may be a second width (W2). The width of the third trench (TR3) may be a third width (W3). The width between adjacent dummy gate electrodes (DGE) may be a fourth width (W4). The maximum width between adjacent gate electrodes (GE) and dummy gate electrodes (DGE) may be a fifth width (W5).

[0104] The fifth width (W5) may be larger than the first width (W1). The third width (W3) may be substantially the same as the first pitch (P1). The fourth width (W4) may be smaller than the first width (W1).

[0105] The width of the body portion (UP) of the dummy gate electrode (DGE) may be substantially the same as the second width (W2). The width of the vertical portion (VP) of the dummy gate electrode (DGE) may be the sixth width (W6). The sixth width (W6) may be smaller than the second width (W2). Specifically, the sixth width (W6) may be greater than half of the second width (W2) and smaller than the second width (W2).

[0106] The body portion (UP) of the dummy gate electrode (DGE) may be tilted toward an adjacent first source / drain pattern (SD1) or second source / drain pattern (SD2). The angle formed by the side wall of the body portion (UP) and the upper surface of the substrate (100) may be a first angle (θ1). The first angle (θ1) may be an acute angle. For example, the first angle (θ1) may be 60° to 85°.

[0107] Referring again to FIG. 2b, inner spacers (IP) may be provided on the NMOSFET region (NR). The inner spacers (IP) may be interposed between the first to third portions (PO1, PO2, PO3) of the gate electrode (GE) and the second source / drain pattern (SD2), respectively. The inner spacers (IP) may be in direct contact with the second source / drain pattern (SD2). Each of the first to third portions (PO1, PO2, PO3) of the gate electrode (GE1) may be spaced apart from the second source / drain pattern (SD2) by the inner spacers (IP).

[0108] The inner spacer (IP) may include a low dielectric constant material. The low dielectric constant material may include silicon oxide or a material having a dielectric constant lower than that of silicon oxide. For example, the low dielectric constant material may include at least one of silicon oxide, silicon oxide doped with fluorine or carbon, porous silicon oxide, and an organic polymeric dielectric.

[0109] A first interlayer insulating film (110) may be provided on a substrate (100). The first interlayer insulating film (110) may cover gate spacers (GS), dummy gate spacers (DGS), and first and second source / drain patterns (SD1, SD2). The upper surface of the first interlayer insulating film (110) may be substantially co-planar with the upper surface of the gate capping pattern (GP), the upper surface of the dummy gate spacer (DGS), and the upper surface of the gate spacer (GS). A second interlayer insulating film (120) covering the gate capping pattern (GP) may be disposed on the first interlayer insulating film (110). In one example, the first and second interlayer insulating films (110, 120) may comprise a silicon oxide film.

[0110] Active contacts (AC) may be provided that are electrically connected to the first and second source / drain patterns (SD1, SD2), respectively, by penetrating the first and second interlayer insulating films (110, 120). A pair of active contacts (AC) may be provided on each side of the gate electrode (GE). In a planar view, the active contact (AC) may have a bar shape extending in the first direction (D1). The active contact (AC) may be a self-aligned contact. That is, the active contact (AC) may be formed self-aligned using the gate capping pattern (GP) and the gate spacer (GS). For example, the active contact (AC) may cover at least a portion of the sidewall of the gate spacer (GS). Although not illustrated, the active contact (AC) may cover a portion of the upper surface of the gate capping pattern (GP).

[0111] Silicide patterns (SC) may be interposed between the active contact (AC) and the first source / drain pattern (SD1), and between the active contact (AC) and the second source / drain pattern (SD2), respectively. The active contact (AC) may be electrically connected to the source / drain patterns (SD1, SD2) through the silicide pattern (SC). The silicide pattern (SC) may include metal-silicide, and may include, for example, at least one of titanium-silicide, tantalum-silicide, tungsten-silicide, nickel-silicide, and cobalt-silicide.

[0112] A gate contact (GC) that is electrically connected to a gate electrode (GE) by penetrating the second interlayer insulating film (120) and the gate capping pattern (GP) may be provided. For example, referring to FIG. 2b, the upper portion of each active contact (AC) adjacent to the gate contact (GC) may be filled with an upper insulating pattern (UIP). This prevents process defects in which a short circuit occurs when the gate contact (GC) contacts the adjacent active contact (AC).

[0113] Each of the active contact (AC) and the gate contact (GC) may include a conductive pattern (FM) and a barrier pattern (BM) surrounding the conductive pattern (FM). For example, the conductive pattern (FM) may include at least one metal selected from aluminum, copper, tungsten, molybdenum, and cobalt. The barrier pattern (BM) may cover the sidewalls and bottom surface of the conductive pattern (FM). The barrier pattern (BM) may include a metal film / metal nitride film. The metal film may include at least one selected from titanium, tantalum, tungsten, nickel, cobalt, and platinum. The metal nitride film may include at least one selected from titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), nickel nitride (NiN), cobalt nitride (CoN), and platinum nitride (PtN).

[0114] A first metal layer (M1) may be provided within the third interlayer insulating film (130). The first metal layer (M1) may include first wires (M1_I) and first vias (VI1). Each of the first wires (M1_I) may have a line or bar shape extending in a second direction (D2). The first vias (VI1) may be provided below the first wires (M1_I). The first vias (VI1) may be interposed between the active contacts (AC) and the first wires (M1_I), respectively. The first vias (VI1) may be interposed between the gate contacts (GC) and the first wires (M1_I), respectively.

[0115] The first wirings (M1_I) of the first metal layer (M1) and the first via (VI1) below them can each be formed by separate processes. In other words, the first wirings (M1_I) and the first via (VI1) can each be formed by a single damascene process. The semiconductor device according to the present embodiment may be formed using a process of less than 20 nm.

[0116] A second metal layer (M2) may be provided within the fourth interlayer insulating film (140). The second metal layer (M2) may include second wires (M2_I). Each of the second wires (M2_I) may have a line or bar shape extending in a first direction (D1).

[0117] The second metal layer (M2) may further include second vias (VI2). The second vias (VI2) may be provided below the second wiring (M2_I). The second vias (VI2) may be interposed between the first wiring (M1_I) and the second wiring (M2_I), respectively.

[0118] The second wiring (M2_I) of the second metal layer (M2) and the second via (VI2) below it can be integrally formed by the same process. In other words, the second wiring (M2_I) and the second via (VI2) of the second metal layer (M2) can be formed together by a dual damascene process.

[0119] The first wirings (M1_I) of the first metal layer (M1) and the second wirings (M2_I) of the second metal layer (M2) may include the same or different conductive materials. For example, the first wirings (M1_I) and the second wirings (M2_I) may include at least one metal material selected from aluminum, copper, tungsten, molybdenum, and cobalt.

[0120] In one embodiment of the present invention, metal layers (e.g., M3, M4, M5, etc.) stacked on the fourth interlayer insulating film (140), although not illustrated, may be additionally provided. Each of the stacked metal layers may include routing wires.

[0122] FIG. 13 is a cross-sectional view along line A-A' of FIG. 11, intended to explain a semiconductor device according to a comparative example of the present invention. In this comparative example, details that overlap with those explained with reference to FIG. 11 and FIG. 12a to FIG. 12d are omitted, and differences are explained in detail. Specifically, FIG. 13 may be a semiconductor device designed with a layout described with reference to FIG. 3.

[0123] Referring to FIGS. 11 and 13, the width between adjacent gate electrodes (GE) may be a first width (W1'). The width of the gate electrode (GE) may be a second width (W2'). The width of the third trench (TR3) may be a third width (W3'). The width between adjacent dummy gate electrodes (DGE) may be a fourth width (W4'). The width between adjacent dummy gate electrodes (DGE) and gate electrode (GE) may be a fifth width (W5').

[0124] The first width (W1') of FIG. 13 may be substantially the same as the first width (W1) of FIG. 12a. The second width (W2') of FIG. 13 may be substantially the same as the second width (W2) of FIG. 12a. The third width (W3') of FIG. 13 may be substantially the same as the third width (W3) of FIG. 12a. The fourth width (W4') of FIG. 13 may be larger than the fourth width (W4) of FIG. 12a. The fifth width (W5') of FIG. 13 may be smaller than the fifth width (W5) of FIG. 12a. That is, the semiconductor device of FIG. 13 may have a smaller width between the dummy gate electrode (DGE) and the adjacent gate electrode (GE) compared to the semiconductor device of FIG. 12a.

[0125] As the size of the semiconductor device decreases, the aspect ratio of the sacrifice pattern (PP) and the dummy sacrifice pattern (DPP) increases, which causes the dummy sacrifice pattern (DPP) adjacent to the third trench (TR3) to tilt (see FIG. 5). As the dummy sacrifice pattern (DPP) tilts, the dummy gate electrode (DGE) that is finally manufactured also tilts, which can cause a short circuit between the dummy gate electrode (DGE) and the adjacent active contact (AC).

[0126] Additionally, the thickness of the first source / drain pattern (SD1) adjacent to the third trench (TR3) may be smaller than that of other first source / drain patterns (SD1). This is because, as the dummy sacrifice pattern (DPP) adjacent to the third trench (TR3) tilts, the exposed area when forming the first recess (RS1) is reduced, and thus the desired depth of the first recess (RS1) is not achieved. Consequently, adjacent gate electrodes (GE) may remain connected without being separated, which can cause malfunctions and defects in the semiconductor device. As a result, the reliability and electrical characteristics of the semiconductor device may deteriorate.

[0127] According to embodiments of the present invention, the distance between adjacent dummy gate patterns can be reduced by using an optical proximity correction procedure through comparison with preset target distances during layout design. Accordingly, a short circuit between the dummy gate electrode and the adjacent active contact can be prevented even when the finally manufactured dummy gate electrode is tilted. In addition, as the distance between the dummy sacrifice pattern and the sacrifice pattern decreases, the recess formed between them is formed shallowly, thereby preventing a short circuit between the dummy gate electrode and the gate electrode. As a result, the electrical characteristics and reliability of the semiconductor device can be improved.

[0129] FIGS. 14, 16, 18, 20, 22, and 24 are plan views for explaining a method for manufacturing a semiconductor device according to embodiments of the present invention. FIGS. 15, 17a, 19a, 21a, 23a, and 25a are cross-sectional views along line A-A' of FIGS. 14, 16, 18, 20, 22, and 24, respectively. FIGS. 17b, 19b, 21b, 23b, and 25b are cross-sectional views along line B-B' of FIGS. 16, 18, 20, 22, and 24, respectively. FIGS. 21c, 23c, and 25c are cross-sectional views along line C-C' of FIGS. 20, 22, and 24, respectively. FIGS. 21d, FIGS. 23d, and FIGS. 25d are cross-sectional views along the line D-D' of FIGS. 20, FIGS. 22, and FIGS. 24, respectively.

[0130] Referring to FIGS. 14 and 15, sacrificial layers (SAL) and active layers (ACL) can be formed alternately stacked on a substrate (100). The sacrificial layers (SAL) may include one of silicon (Si), germanium (Ge), and silicon-germanium (SiGe), and the active layers (ACL) may include the other of silicon (Si), germanium (Ge), and silicon-germanium (SiGe). For example, the sacrificial layers (SAL) may include silicon-germanium (SiGe), and the active layers (ACL) may include silicon (Si).

[0131] The sacrificial layers (SAL) and active layers (ACL) can be formed by an epitaxial growth process using the substrate (100) as a seed layer. The sacrificial layers (SAL) and active layers (ACL) can be formed conformally on the entire surface of the substrate (100).

[0132] Referring to FIGS. 16, FIGS. 17a and FIGS. 17b, mask patterns can be formed on the PMOSFET region (PR) and NMOFSET region (NR) of the substrate (100), respectively. The mask pattern may have a line shape or a bar shape extending in a second direction (D2).

[0133] A first patterning process can be performed using the above mask patterns as etching masks to form a first trench (TR1) defining a first active pattern (AP1) and a second active pattern (AP2). The first active pattern (AP1) and the second active pattern (AP2) can be formed on the PMOSFET region (PR) and the NMOSFET region (NR), respectively. Each of the first active pattern (AP1) and the second active pattern (AP2) may include sacrificial layers (SAL) and active layers (ACL) alternately stacked on top of each other.

[0134] A second patterning process may be performed on the substrate (100) to form a second trench (TR2) that defines a PMOSFET region (PR) and an NMOSFET region (NR). The second trench (TR2) may be formed deeper than the first trench (TR1).

[0135] A cutting process may be performed on a substrate (100) to separate a first active pattern (AP1) into a pair of adjacent first active patterns (AP1) and a second active pattern (AP2) into a pair of adjacent second active patterns (AP2), thereby forming a third trench (TR3). The third trench (TR3) may correspond to an area where the cutting pattern (CPa) described with reference to FIG. 8 is placed. The width of the third trench (TR3) may correspond to a third distance (DI3). The third trench (TR3) may include a first sidewall (SW1) adjacent to a first logic cell (LC1) and a second sidewall (SW2) adjacent to a second logic cell (LC2).

[0136] A device isolation layer (ST) can be formed on a substrate (100) to fill first to third trenches (TR1, TR2, TR3). The device isolation layer (ST) may include silicon oxide. The upper portions of the first and second active patterns (AP1, AP2) may protrude vertically over the device isolation layer (ST). The device isolation layer (ST) may directly cover the lower portion of the first sidewall (SW1) and the lower portion of the second sidewall (SW2) of the third trench (TR3).

[0137] Referring again to FIGS. 9 and FIGS. 10, sacrifice patterns (PP) and dummy sacrifice patterns (DPP) can be formed across first and second active patterns (AP1, AP2) on a substrate (100). Each of the sacrifice patterns (PP) and dummy sacrifice patterns (DPP) can be formed in a line shape or a bar shape extending in a first direction (D1).

[0138] Specifically, forming sacrifice patterns (PP) and dummy sacrifice patterns (DPP) may include forming a sacrifice film on the front surface of a substrate (100), forming masks on the sacrifice film, and patterning the sacrifice film using the masks as etching masks. The sacrifice film may include polysilicon.

[0139] Referring to FIGS. 18, 19a, and 19b, the upper portions of the sacrifice patterns (PP) and dummy sacrifice patterns (DPP) can be etched. Here, the maximum value of the distance (DI4-DI5) between the dummy sacrifice patterns (DPP) can be substantially the same as or similar to the first distance (DI1).

[0140] Referring to FIG. 20 and FIG. 21a through 21d, hard mask patterns (MK) may be formed on the upper surface of each of the sacrifice patterns (PP) and dummy sacrifice patterns (DPP). A pair of gate spacers (GS) may be formed on both sidewalls of each of the sacrifice patterns (PP) and dummy sacrifice patterns (DPP). Forming the gate spacers (GS) may include conformally forming a gate spacer film on the front surface of the substrate (100) and anisotropically etching the gate spacer film. The gate spacer film may include at least one of SiCN, SiCON, and SiN. As another example, the gate spacer film may be a multi-layer film including at least two of SiCN, SiCON, and SiN.

[0141] First recesses (RS1) may be formed on the upper surface of the first active pattern (AP1). Second recesses (RS2) may be formed on the upper surface of the second active pattern (AP2). While forming the first and second recesses (RS1, RS2), the device isolation film (ST) on both sides of each of the first and second active patterns (AP1, AP2) may be recessed (see FIG. 21c).

[0142] Specifically, first recesses (RS1) can be formed by etching the upper portion of a first active pattern (AP1) using hard mask patterns (MK) and gate spacers (GS) as an etching mask. The first recesses (RS1) can be formed between a pair of sacrifice patterns (PP) and between a dummy sacrifice pattern (DPP) and an adjacent sacrifice pattern (PP). Second recesses (RS2) on the upper portion of a second active pattern (AP2) can be formed in the same way as the first recesses (RS1).

[0143] First source / drain patterns (SD1) may each be formed within the first recesses (RS1). Specifically, the first source / drain pattern (SD1) may be formed by performing an SEG process in which the inner wall of the first recess (RS1) serves as a seed layer. The first source / drain pattern (SD1) may be grown using the first to third semiconductor patterns (SP1, SP2, SP3) exposed by the first recess (RS1) and the substrate (100) as seeds. As the first source / drain patterns (SD1) are formed, a first channel pattern (CH1) may be defined between a pair of first source / drain patterns (SD1). For example, the SEG process may include a Chemical Vapor Deposition (CVD) process or a Molecular Beam Epitaxy (MBE) process. The first source / drain patterns (SD1) may include a semiconductor element (e.g., SiGe) having a lattice constant greater than the lattice constant of the semiconductor element of the substrate (100). Each of the first source / drain patterns (SD1) may be formed of multiple semiconductor layers.

[0144] For example, during the SEG process for forming the first source / drain patterns (SD1), impurities may be injected in-situ. For another example, impurities may be injected into the first source / drain pattern (SD1) after the first source / drain pattern (SD1) has been formed. The first source / drain pattern (SD1) may be doped to have a first conductivity type (e.g., p-type).

[0145] After removing a portion of the sacrificial layers (SAL) exposed by the second recesses (RS2), inner spacers (IP) can be formed. Second source / drain patterns (SD2) can be formed within the second recesses (RS2). Specifically, the second source / drain pattern (SD2) can be formed by performing an SEG process in which the inner wall of the second recess (RS2) is used as a seed layer. As an example, the second source / drain pattern (SD2) may contain the same semiconductor element (e.g., Si) as the substrate (100). The second source / drain pattern (SD2) may be doped to have a second conductivity type (e.g., n-type). As the second source / drain patterns (SD2) are formed, a second channel pattern (CH2) may be defined between a pair of second source / drain patterns (SD2).

[0146] Referring to FIGS. 22 and FIGS. 23a through 23d, a first interlayer insulating film (110) covering first and second source / drain patterns (SD1, SD2), hard mask patterns (MK), and gate spacers (GS) may be formed. As an example, the first interlayer insulating film (110) may include a silicon oxide film.

[0147] The first interlayer insulating film (110) can be flattened until the upper surfaces of the sacrificial patterns (PP) and dummy sacrificial patterns (DPP) are exposed. The flattening of the first interlayer insulating film (110) can be performed using an etch back or chemical mechanical polishing (CMP) process. During the flattening process, all hard mask patterns (MK) can be removed. Consequently, the upper surface of the first interlayer insulating film (110) can be co-planar with the upper surfaces of the sacrificial patterns (PP) and dummy patterns (DPP) and the upper surfaces of the gate spacers (GS).

[0148] By removing the sacrifice patterns (PP) and dummy sacrifice patterns (DPP), first empty spaces (ET1) that expose the first and second active patterns (AP1, AP2) can be formed. Through the first empty spaces (ET1), the sacrifice layers (SAL) of each of the first and second active patterns (AP1, AP2) can be exposed.

[0149] The sacrificial layers (SAL) exposed through the first empty space (ET1) can be selectively removed. Specifically, by performing an etching process that selectively etches the sacrificial layers (SAL), only the sacrificial layers (SAL) can be removed while the first to third semiconductor patterns (SP1, SP2, SP3) remain intact. In this process, the occurrence of defects in the second source / drain pattern (SD2) can be prevented by the inner spacers (IP).

[0150] Only the first to third semiconductor patterns (SP1, SP2, SP3) may remain on each of the first and second active patterns (AP1, AP2). Second empty spaces (ET2) may be formed through regions from which the sacrificial layers (SAL) have been removed. The second empty spaces (ET2) may be defined between the first to third semiconductor patterns (SP1, SP2, SP3).

[0151] Referring to FIGS. 24 and FIGS. 25a through 25d, a gate insulating film (GI) may be conformally formed within first and second empty spaces (ET1, ET2). A gate electrode (GE) may be formed on the gate insulating film (GI). The gate electrode (GE) may be formed to fill the first and second empty spaces (ET1, ET2). Specifically, the gate electrode (GE) may include first to third portions (PO1, PO2, PO3) that fill the second empty spaces (ET2). The gate electrode (GE) may further include a fourth portion (PO4) that fills the first empty space (ET1). A gate capping pattern (GP) may be formed on the gate electrode (GE).

[0152] A dummy gate electrode (DGE) adjacent to the third trench (TR3) may be formed. A gate spacer (GS) provided on the sidewall of the dummy gate electrode (DGE) may be named a dummy gate spacer (DGS). A gate insulating film (GI) interposed between the dummy gate electrode (DGE) and the first channel pattern (CH1), and between the dummy gate electrode (DGE) and the second channel pattern (CH2), may be named a dummy gate insulating film (DGI).

[0153] Referring again to FIGS. 11 and FIGS. 12a through 12d, a second interlayer insulating film (120) may be formed on a first interlayer insulating film (110). The second interlayer insulating film (120) may include a silicon oxide film. Active contacts (AC) electrically connected to first and second source / drain patterns (SD1, SD2) may be formed through the second interlayer insulating film (120) and the first interlayer insulating film (110). A gate contact (GC) electrically connected to a gate electrode (GE) may be formed through the second interlayer insulating film (120) and a gate capping pattern (GP).

[0154] A third interlayer insulating film (130) may be formed on active contacts (AC) and gate contacts (GC). A first metal layer (M1) may be formed within the third interlayer insulating film (130). A fourth interlayer insulating film (140) may be formed on the third interlayer insulating film (130). A second metal layer (M2) may be formed within the fourth interlayer insulating film (140).

[0156] FIGS. 26a to 26d are cross-sectional views along lines A-A', B-B', C-C', and D-D' of FIG. 11, respectively. In this embodiment, details that overlap with those described with reference to FIGS. 11 and FIGS. 12a to 12d are omitted, and the differences are described in detail.

[0157] Referring to FIG. 11 and FIG. 26a through 26d, a PMOSFET region (PR) and an NMOSFET region (NR) may be defined by a second trench (TR2) formed on the upper surface of the substrate (100). A first trench (TR1) may be defined between adjacent first active patterns (AP1) and between adjacent second active patterns (AP2). The first trench (TR1) may be shallower than the second trench (TR2). A third trench (TR3) may separate the first logic cell (LC1) and the second logic cell (LC2) from each other.

[0158] The device isolation layer (ST) can fill the first to third trenches (TR1, TR2, TR3). The upper portion of each of the first and second active patterns (AP1, AP2) can protrude vertically over the device isolation layer (ST). The upper portion of each of the first and second active patterns (AP1, AP2) can have a fin shape. The device isolation layer (ST) may not cover the upper portion of each of the first and second active patterns (AP1, AP2). The device isolation layer (ST) can cover the lower sidewall of each of the first and second active patterns (AP1, AP2).

[0159] First source / drain patterns (SD1) may be provided on top of first active patterns (AP1). The first source / drain patterns (SD1) may be impurity regions of a first conductivity type (e.g., p-type). A first channel pattern (CH1) may be interposed between a pair of first source / drain patterns (SD1). Second source / drain patterns (SD2) may be provided on top of second active patterns (AP2). The second source / drain patterns (SD2) may be impurity regions of a second conductivity type (e.g., n-type). A second channel pattern (CH2) may be interposed between a pair of second source / drain patterns (SD2).

[0160] The first and second source / drain patterns (SD1, SD2) may be epitaxial patterns formed by an optional epitaxial growth process. For example, the upper surfaces of the first and second source / drain patterns (SD1, SD2) may co-plane with the upper surfaces of the first and second channel patterns (CH1, CH2). For another example, the upper surfaces of the first and second source / drain patterns (SD1, SD2) may be higher than the upper surfaces of the first and second channel patterns (CH1, CH2).

[0161] Gate electrodes (GE) extending in a first direction (D1) across the first and second active patterns (AP1, AP2) may be provided. The gate electrodes (GE) may overlap perpendicularly with the first and second channel patterns (CH1, CH2). Each gate electrode (GE) may surround the top surface and both side walls of each of the first and second channel patterns (CH1, CH2).

[0162] Referring again to FIG. 26d, the gate electrode (GE) may be provided on the first upper surface (TS1) of the first channel pattern (CH1) and at least one first sidewall (SIW1). The gate electrode (GE) may be provided on the second upper surface (TS2) of the second channel pattern (CH2) and at least one second sidewall (SIW2) of the second channel pattern (CH2). In other words, the transistor according to the present embodiment may be a three-dimensional field-effect transistor (e.g., FinFET) in which the gate electrode (GE) surrounds the channels (CH1, CH2) in three dimensions.

[0163] Unlike the dummy gate electrode (DGE) described with reference to FIGS. 11 and FIGS. 12a through 12d, in this embodiment, the dummy gate electrode (DGE) may not include protrusions (PT). The gate electrode (GE), gate contact (GC), active contact (AC), first metal layer (M1), and second metal layer (M2) may be substantially the same as those described with reference to FIGS. 11 and FIGS. 12a through 12d.

[0165] Although embodiments of the present invention have been described above with reference to the attached drawings, those skilled in the art will understand that the present invention may be implemented in other specific forms without changing its technical concept or essential features. Therefore, the embodiments described above should be understood as illustrative in all respects and not restrictive.

Claims

Claim 1 A method for manufacturing a semiconductor device comprising: designing a layout, wherein the layout includes a first gate pattern, a second gate pattern, a first dummy gate pattern, a second dummy gate pattern, a third gate pattern, and a fourth gate pattern arranged sequentially in a first direction; forming first to fourth sacrifice patterns corresponding to each of the first to fourth gate patterns and first and second dummy sacrifice patterns corresponding to each of the first and second dummy gate patterns on a substrate using a first photomask manufactured using the layout; and performing optical proximity correction on the layout, wherein the performing optical proximity correction comprises: measuring distances between the first to fourth sacrifice patterns and the first and second dummy sacrifice patterns that are adjacent to each other in the first direction; comparing the average value of the measured distances with the average value of preset target distances to obtain the difference, wherein the difference is a first distance; and reducing the distance between the first dummy gate pattern and the second dummy gate pattern by the first distance. Claim 2 A method for manufacturing a semiconductor device according to claim 1, wherein the layout further includes a cutting pattern disposed between the first dummy gate pattern and the second dummy gate pattern. Claim 3 A method for manufacturing a semiconductor device according to paragraph 2, wherein each of the first dummy gate pattern portion and the second dummy gate pattern portion is vertically superimposed with the cutting pattern. Claim 4 A method for manufacturing a semiconductor device according to claim 2, wherein the upper portion of the substrate comprises a trench, and the trench is formed in an area corresponding to the cutting pattern; and each of the first and second dummy sacrifice patterns comprises: a body portion disposed on the substrate; and a vertical portion extending vertically from the body portion along the side wall of the trench. Claim 5 A method for manufacturing a semiconductor device according to paragraph 2, wherein the width of the cutting pattern is the same as the pitch between the first gate pattern and the second gate pattern. Claim 6 A method for manufacturing a semiconductor device according to claim 1, wherein in the layout in which the optical proximity correction is performed, the pitch between the first dummy gate pattern and the second dummy gate pattern is smaller than the pitch between the first gate pattern and the second gate pattern. Claim 7 A method for manufacturing a semiconductor device according to claim 1, wherein in the layout in which the optical proximity correction is performed, the pitch between the second gate pattern and the first dummy gate pattern is larger than the pitch between the first gate pattern and the second gate pattern. Claim 8 A method for manufacturing a semiconductor device according to claim 1, wherein reducing the distance between the first dummy gate pattern and the second dummy gate pattern comprises: biasing the first dummy gate pattern toward the second dummy gate pattern by half of the first distance and biasing the second dummy gate pattern toward the first dummy gate pattern by half of the first distance. Claim 9 A method for manufacturing a semiconductor device according to claim 1, wherein the layout comprises a first standard cell and a second standard cell adjacent to each other in the first direction, wherein the first gate pattern, the second gate pattern and the first dummy gate pattern are disposed on the first standard cell, and the second dummy gate pattern, the third gate pattern and the fourth gate pattern are disposed on the second standard cell, and the pitch between the first gate pattern and the second gate pattern and the pitch between the third gate pattern and the fourth gate pattern are the same. Claim 10 A method for manufacturing a semiconductor device, further comprising: manufacturing a second photomask based on the layout in which the optical proximity correction is performed in claim 1; and performing a semiconductor process on a substrate using the second photomask.

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