Display device and display panel

Abstract

Embodiments of the present disclosure relate to a display device and a display panel, and more specifically, may provide a display panel comprising a plurality of subpixels disposed in an area where a plurality of gate lines and a plurality of data lines intersect, a plurality of gate-in-panel (GIP) circuits that supply a plurality of scan signals to the plurality of subpixels through the plurality of gate lines, and a plurality of scan clock lines that supply a plurality of scan clocks corresponding to the plurality of scan signals to the plurality of gate-in-panel (GIP) circuits, wherein the arrangement order of adjacent scan clock lines is determined according to the overlap interval between adjacent scan clocks or the number of scan signals output from each gate-in-panel (GIP) circuit.

Description

Technology Field

[0001] The embodiments of the present disclosure relate to a display device and a display panel, and more specifically, to a display device and a display panel capable of reducing image defects caused by clock line coupling. Background Technology

[0003] Representative display devices that display images using digital data include Liquid Crystal Displays (LCDs) using liquid crystals and Organic Light Emitting Diodes (OLEDs).

[0004] Among these display devices, organic light-emitting display devices utilize self-emissive light-emitting diodes, offering advantages such as fast response speed, contrast ratio, luminous efficiency, brightness, and viewing angle. In this case, the light-emitting diodes can be implemented using inorganic or organic materials.

[0005] This organic light-emitting display device includes a light-emitting diode placed in each of a plurality of subpixels arranged on a display panel, and can display an image by controlling the brightness represented by each subpixel by emitting light through voltage control flowing through the light-emitting diode.

[0006] Such a display device includes a gate driving circuit and a data driving circuit capable of driving a display panel.

[0007] Among these, the gate driving circuit includes multiple gate driving integrated circuits that output multiple scan signals, but due to coupling between clock lines applied to the gate driving integrated circuits, a problem may occur in which horizontal line defects occur on the display panel. The problem to be solved

[0009] Accordingly, the inventors of the present disclosure have invented a display device and a display panel capable of reducing image defects caused by coupling of clock lines.

[0010] The embodiments of the present disclosure can provide a display device and a display panel capable of improving image quality by arranging clock lines so that coupling effects can be minimized.

[0011] In addition, embodiments of the present disclosure can provide a display device and a display panel capable of improving image quality by arranging clock lines to minimize coupling effects, taking into account the horizontal period of the clock applied to the gate driving integrated circuit and the number of scan signals output from the gate driving integrated circuit. means of solving the problem

[0013] Embodiments of the present disclosure may provide a display panel comprising a plurality of subpixels disposed in an area where a plurality of gate lines and a plurality of data lines intersect, a plurality of gate-in-panel (GIP) circuits that supply a plurality of scan signals to the plurality of subpixels through the plurality of gate lines, and a plurality of scan clock lines that supply a plurality of scan clocks corresponding to the plurality of scan signals to the plurality of gate-in-panel (GIP) circuits, wherein the arrangement order of adjacent scan clock lines is determined according to the overlap interval between adjacent scan clocks or the number of scan signals output from each gate-in-panel (GIP) circuit.

[0014] Embodiments of the present disclosure may provide a display device comprising a display panel having a plurality of subpixels arranged thereon, a gate driving circuit including a plurality of gate driving integrated circuits configured to supply a plurality of scan signals to the display panel through a plurality of gate lines, a data driving circuit configured to supply a plurality of data voltages to the display panel through a plurality of data lines, a timing controller configured to control the gate driving circuit and the data driving circuit, and a plurality of scan clock lines supplying a plurality of scan clocks corresponding to the plurality of scan signals to the plurality of gate driving integrated circuits, wherein the arrangement order of the adjacent scan clock lines is determined according to the overlap interval between adjacent scan clocks or the number of scan signals output from each gate driving integrated circuit. Effects of the invention

[0016] According to the embodiments of the present disclosure, there is an effect of reducing image defects caused by clock line coupling.

[0017] In addition, according to the embodiments of the present disclosure, by arranging the clock lines so that the coupling effect can be minimized, the image quality can be improved.

[0018] In addition, according to the embodiments of the present disclosure, by arranging clock lines to minimize coupling effects by considering the horizontal period of the clock applied to the gate driving integrated circuit and the number of scan signals output from the gate driving integrated circuit, the effect of improving image quality is achieved. Brief explanation of the drawing

[0020] FIG. 1 is a diagram showing the schematic configuration of a display device according to embodiments of the present disclosure. FIG. 2 is a system example diagram of a display device according to embodiments of the present disclosure. FIG. 3 is a diagram of one example of a circuit constituting a subpixel in a display device according to embodiments of the present disclosure. FIG. 4 is a diagram illustrating an example of a display panel in which a gate driving circuit is implemented as a GIP type in a display device according to embodiments of the present disclosure. FIG. 5 is a block diagram showing the schematic configuration of a gate driving integrated circuit in a display device according to embodiments of the present disclosure. FIG. 6 is a diagram showing a plurality of stage circuit configurations constituting a gate driving circuit according to embodiments of the present disclosure. FIG. 7 is a diagram illustrating an example of a stage circuit constituting a gate driving circuit in a display driving circuit according to embodiments of the present disclosure. FIG. 8 is a diagram illustrating an example in which 12-phase scan clock lines are arranged sequentially when four scan signals are output from a single gate driving integrated circuit. Figure 9 is a diagram showing an example of a signal waveform when 12-phase scan clock lines are arranged sequentially. FIG. 10 is a diagram illustrating, as an example, parasitic capacitance between scan clocks and distortion of the scan signal caused by this in the structure of FIG. 8 and FIG. 9. FIG. 11 is a diagram illustrating an example of a scan clock line arrangement that can reduce parasitic capacitance in a display device according to embodiments of the present disclosure. FIG. 12 is a diagram illustrating, as an example, a signal waveform diagram according to the arrangement of the scan clock line of FIG. 11 in a display device according to embodiments of the present disclosure. FIG. 13 is a diagram illustrating an example in which image defects are improved by preventing distortion of scan clocks and scan signals in a display device according to embodiments of the present disclosure. Specific details for implementing the invention

[0021] Hereinafter, some embodiments of the present disclosure will be described in detail with reference to the exemplary drawings. In assigning reference numerals to the components of each drawing, the same components may have the same reference numeral as much as possible, even if they are shown in different drawings. Furthermore, in describing the present disclosure, if it is determined that a detailed description of related known components or functions may obscure the essence of the present disclosure, such detailed description may be omitted. Where terms such as "comprising," "having," or "consisting of" are used in this specification, other parts may be added unless "only" is used. Where a component is expressed in the singular, it may include a plural unless there is a special explicit description otherwise.

[0022] Additionally, terms such as first, second, A, B, (a), (b), etc., may be used to describe the components of the present disclosure. These terms are used merely to distinguish the components from other components, and the nature, order, sequence, or number of the components are not limited by such terms.

[0023] In describing the positional relationship of components, where it is stated that two or more components are "connected," "combined," or "joined," it should be understood that while the two or more components may be directly "connected," "combined," or "joined," they may also be "connected," "combined," or "joined" with other components "intervened." Here, the other components may be included in one or more of the two or more components that are "connected," "combined," or "joined" with one another.

[0024] In describing the temporal flow relationship regarding components, methods of operation, or methods of production, for example, when the temporal or sequential relationship is described using "after," "following," "next," or "before," it may include cases where the relationship is not continuous unless "immediately" or "directly" is used.

[0025] Meanwhile, where numerical values ​​or corresponding information regarding a component (e.g., levels, etc.) are mentioned, even without separate explicit notation, the numerical values ​​or corresponding information may be interpreted as including a range of error that may occur due to various factors (e.g., process factors, internal or external shocks, noise, etc.).

[0026] FIG. 1 is a diagram showing the schematic configuration of a display device according to embodiments of the present disclosure.

[0027] Referring to FIG. 1, a display device (100) according to one embodiment of the present specification may include a display panel (110) in which a plurality of gate lines (GL) and data lines (DL) are connected and a plurality of subpixels (SP) are arranged in a matrix form, a gate driving circuit (120) for driving a plurality of gate lines (GL), a data driving circuit (130) for supplying a data voltage through a plurality of data lines (DL), a timing controller (140) for controlling the gate driving circuit (120) and the data driving circuit (130), and a power management circuit (150).

[0028] The display panel (110) displays an image based on a scan signal transmitted from a gate driving circuit (120) through a plurality of gate lines (GL) and a data voltage transmitted from a data driving circuit (130) through a plurality of data lines (DL).

[0029] In the case of a liquid crystal display, the display panel (110) includes a liquid crystal layer formed between two substrates and may operate in any known mode, such as a TN (Twisted Nematic) mode, a VA (Vertical Alignment) mode, an IPS (In Plane Switching) mode, or an FFS (Fringe Field Switching) mode. On the other hand, in the case of an organic light-emitting display, the display panel (110) may be implemented in a top emission method, a bottom emission method, or a dual emission method.

[0030] A display panel (110) may have a plurality of pixels arranged in a matrix form, and each pixel may consist of subpixels (SP) of different colors, for example, a white subpixel, a red subpixel, a green subpixel, and a blue subpixel, and each subpixel (SP) may be defined by a plurality of data lines (DL) and a plurality of gate lines (GL).

[0031] A single subpixel (SP) may include a thin film transistor (TFT) formed in the region where a data line (DL) and a gate line (GL) intersect, a light-emitting element such as an organic light-emitting diode that charges the data voltage, and a storage capacitor electrically connected to the light-emitting element to maintain the voltage.

[0032] For example, if a display device (100) having a resolution of 2,160 X 3,840 is composed of four subpixels (SP) of white (W), red (R), green (G), and blue (B), a total of 3,840 X 4 = 15,360 data lines (DL) may be provided by 2,160 gate lines (GL) and 3,840 data lines (DL) connected to each of the four subpixels (WRGB), and each subpixel (SP) will be placed at the point where the gate lines (GL) and data lines (DL) intersect.

[0033] The gate driving circuit (120) is controlled by a controller (140) and controls the driving timing for a plurality of subpixels (SP) by sequentially outputting scan signals to a plurality of gate lines (GL) arranged on a display panel (110).

[0034] In a display device (100) having a resolution of 2,160 x 3,840, a case in which a scan signal is output sequentially from the first gate line to the 2,160th gate line for 2,160 gate lines (GL) can be called 2,160-phase driving. Alternatively, a case in which a scan signal is output sequentially in units of 4 gate lines (GL), such as sequentially outputting a scan signal from the first gate line to the 4th gate line and then sequentially outputting a scan signal from the 5th gate line to the 8th gate line, is called 4-phase driving. That is, a case in which a scan signal is output sequentially for every N gate lines (GL) can be called N-phase driving.

[0035] At this time, the gate driving circuit (120) may include one or more gate driving integrated circuits (GDICs), and depending on the driving method, it may be located on only one side of the display panel (110) or on both sides. Alternatively, the gate driving circuit (120) may be embedded in the bezel area of ​​the display panel (110) and implemented in the form of a gate in panel (GIP).

[0036] The data driving circuit (130) receives image data (DATA) from the timing controller (140) and converts the received image data (DATA) into an analog data voltage. Then, by outputting the data voltage to each data line (DL) in accordance with the timing at which a scan signal is applied through the gate line (GL), each subpixel (SP) connected to the data line (DL) displays a light emission signal of brightness corresponding to the data voltage.

[0037] Likewise, the data driving circuit (130) may include one or more source driving integrated circuits (SDICs), and the source driving integrated circuits (SDICs) may be connected to the bonding pads of the display panel (110) or placed directly on the display panel (110) using a tape-automated bonding (TAB) method or a chip-on-glass (COG) method.

[0038] In some cases, each source driving integrated circuit (SDIC) may be integrated and placed on the display panel (110). Additionally, each source driving integrated circuit (SDIC) may be implemented using a COF (Chip On Film) method, in which case each source driving integrated circuit (SDIC) may be mounted on a circuit film and electrically connected to the data line (DL) of the display panel (110) through the circuit film.

[0039] The timing controller (140) supplies various control signals to the gate driving circuit (120) and the data driving circuit (130) and controls the operation of the gate driving circuit (120) and the data driving circuit (130). That is, the timing controller (140) controls the gate driving circuit (120) to output a scan signal according to the timing implemented in each frame, and on the other hand, transmits image data (DATA) received from the outside to the data driving circuit (130).

[0040] At this time, the timing controller (140) receives various timing signals, including a vertical synchronization signal (Vsync), a horizontal synchronization signal (Hsync), a data enable signal (Data Enable; DE), and a main clock (MCLK), along with video data (DATA) from an external host system (200).

[0041] The host system (200) can be any one of a TV (Television) system, a set-top box, a navigation system, a personal computer (PC), a home theater system, a mobile device, or a wearable device.

[0042] Accordingly, the timing controller (140) generates a control signal using various timing signals received from the host system (200) and transmits it to the gate driving circuit (120) and the data driving circuit (130).

[0043] For example, the timing controller (140) outputs various gate control signals, including a Gate Start Pulse (GSP), a Gate Clock (GCLK), and a Gate Output Enable signal (GOE), to control the gate driving circuit (120). Here, the Gate Start Pulse (GSP) controls the timing at which one or more Gate Driving Integrated Circuits (GDICs) constituting the gate driving circuit (120) begin operation. Additionally, the Gate Clock (GCLK) is a signal commonly input to one or more Gate Driving Integrated Circuits (GDICs) and controls the shift timing of the scan signal. Additionally, the Gate Output Enable signal (GOE) specifies the timing information of one or more Gate Driving Integrated Circuits (GDICs).

[0044] Additionally, the timing controller (140) outputs various data control signals, including a Source Start Pulse (SSP), a Source Sampling Clock (SCLK), and a Source Output Enable Signal (SOE), to control the data driving circuit (130). Here, the Source Start Pulse (SSP) controls the timing at which one or more source driving integrated circuits (SDICs) constituting the data driving circuit (130) begin data sampling. The Source Sampling Clock (SCLK) is a signal that controls the timing of data sampling by the source driving integrated circuit (SDIC). The Source Output Enable Signal (SOE) controls the output timing of the data driving circuit (130).

[0045] Such a display device (100) may include a power management circuit (150) that supplies various voltages or currents to a display panel (110), a gate driving circuit (120), a data driving circuit (130), etc., or controls various voltages or currents to be supplied.

[0046] The power management circuit (150) adjusts the DC input voltage (Vin) supplied from the host system (200) to generate the power required to drive the display panel (100), the gate driving circuit (120), and the data driving circuit (130).

[0047] Meanwhile, a subpixel (SP) is located at the point where the gate line (GL) and the data line (DL) intersect, and a light-emitting element may be placed in each subpixel (SP). For example, an organic light-emitting display device includes a light-emitting element, such as an organic light-emitting diode, in each subpixel (SP), and can display an image by controlling the current flowing through the light-emitting element according to the data voltage.

[0048] These display devices (100) can be of various types, such as liquid crystal displays, organic light-emitting displays, and plasma display panels.

[0049] FIG. 2 is a system example diagram of a display device according to embodiments of the present disclosure.

[0050] Referring to FIG. 2, the display device (100) according to embodiments of the present disclosure shows a case in which the source driving integrated circuit (SDIC) included in the data driving circuit (130) is implemented in a COF (Chip On Film) manner among various methods (TAB, COG, COF, etc.) and the gate driving circuit (120) is implemented in a GIP (Gate In Panel) form among various methods (TAB, COG, COF, GIP, etc.).

[0051] When the gate driving circuit (120) is implemented in the form of a GIP, a plurality of gate driving integrated circuits (GDICs) included in the gate driving circuit (120) can be directly formed in the bezel area of ​​the display panel (110). At this time, the gate driving integrated circuits (GDICs) can receive various signals (clock, gate high voltage, gate low voltage, etc.) required for generating a scan signal through gate driving related signal wiring placed in the bezel area.

[0052] Likewise, one or more source driving integrated circuits (SDICs) included in the data driving circuit (130) may each be mounted on a source film (SF), and one side of the source film (SF) may be electrically connected to a display panel (110). Additionally, wiring for electrically connecting the source driving integrated circuit (SDIC) and the display panel (110) may be arranged on the upper side of the source film (SF).

[0053] The display device (100) may include at least one source printed circuit board (SPCB) and a control printed circuit board (CPCB) for mounting control components and various electrical devices for circuit connection between a plurality of source driving integrated circuits (SDIC) and other devices.

[0054] At this time, the other side of the source film (SF) on which the source driving integrated circuit (SDIC) is mounted can be connected to at least one source printed circuit board (SPCB). That is, one side of the source film (SF) on which the source driving integrated circuit (SDIC) is mounted can be electrically connected to the display panel (110), and the other side can be electrically connected to the source printed circuit board (SPCB).

[0055] A timing controller (140) and a power management circuit (150) may be mounted on a control printed circuit board (CPCB). The timing controller (140) can control the operation of a data driving circuit (130) and a gate driving circuit (120). The power management circuit (150) may supply driving voltage or current to a display panel (110), a data driving circuit (130), and a gate driving circuit (120), and may control the supplied voltage or current.

[0056] At least one source printed circuit board (SPCB) and a control printed circuit board (CPCB) may be circuitously connected through at least one connecting member, and the connecting member may be, for example, a flexible printed circuit (FPC), a flexible flat cable (FFC), etc. In addition, at least one source printed circuit board (SPCB) and a control printed circuit board (CPCB) may be implemented by integrating them into a single printed circuit board.

[0057] The display device (100) may further include a set board (170) electrically connected to a control printed circuit board (CPCB). In this case, the set board (170) may also be referred to as a power board. A main power management circuit (160) that manages the total power of the display device (100) may be present on this set board (170). The main power management circuit (160) may be linked with a power management circuit (150).

[0058] In the case of a display device (100) configured as above, the driving voltage is generated at the set board (170) and transmitted to the power management circuit (150) within the control printed circuit board (CPCB). The power management circuit (150) transmits the driving voltage required for display driving or characteristic value sensing to the source printed circuit board (SPCB) via the flexible printed circuit (FPC) or flexible flat cable (FFC). The driving voltage transmitted to the source printed circuit board (SPCB) is supplied to emit light or sense a specific subpixel (SP) within the display panel (110) via the source driving integrated circuit (SDIC).

[0059] At this time, each subpixel (SP) arranged in the display panel (110) within the display device (100) may be composed of a light-emitting element and a circuit element such as a driving transistor for driving it.

[0060] The types and number of circuit elements constituting each subpixel (SP) can be determined in various ways depending on the provided functions and design methods.

[0061] FIG. 3 is a diagram of one example of a circuit constituting a subpixel in a display device according to embodiments of the present disclosure.

[0062] Referring to FIG. 3, in a display device (100) according to embodiments of the present disclosure, a subpixel (SP) may include one or more transistors and capacitors, and a light-emitting element may be disposed therein.

[0063] For example, a subpixel (SP) may include a driving transistor (DRT), a switching transistor (SWT), a sensing transistor (SENT), a storage capacitor (Cst), and a light-emitting diode (ED).

[0064] The driving transistor (DRT) has a first node (N1), a second node (N2), and a third node (N3). The first node (N1) of the driving transistor (DRT) may be a gate node to which a data voltage (Vdata) is applied from the data driving circuit (130) through the data line (DL) when the switching transistor (SWT) is turned on.

[0065] The second node (N2) of the driving transistor (DRT) can be electrically connected to the anode electrode of the light-emitting diode (ED) and can be a source node or a drain node.

[0066] The third node (N3) of the driving transistor (DRT) is electrically connected to the driving voltage line (DVL) to which the subpixel driving voltage (EVDD) is applied, and may be a drain node or a source node.

[0067] At this time, during the display driving period, the subpixel driving voltage (EVDD) required to display the image can be supplied through the driving voltage line (DVL), for example, the subpixel driving voltage (EVDD) required to display the image can be 27V.

[0068] The switching transistor (SWT) is electrically connected between the first node (N1) of the driving transistor (DRT) and the data line (DL), and the gate line (GL) is connected to the gate node and operates according to the first scan signal (SCAN1) supplied through the gate line (GL). In addition, when the switching transistor (SWT) is turned on, the operation of the driving transistor (DRT) is controlled by transmitting the data voltage (Vdata) supplied through the data line (DL) to the gate node of the driving transistor (DRT).

[0069] The sensing transistor (SENT) is electrically connected between the second node (N2) of the driving transistor (DRT) and the reference voltage line (RVL), and operates according to the second scan signal (SCAN2) supplied through the gate line (GL). When the sensing transistor (SENT) is turned on, the reference voltage (Vref) supplied through the reference voltage line (RVL) is delivered to the second node (N2) of the driving transistor (DRT).

[0070] That is, by controlling the switching transistor (SWT) and the sensing transistor (SENT), the voltage at the first node (N1) and the voltage at the second node (N2) of the driving transistor (DRT) are controlled, thereby enabling the supply of current to drive the light-emitting diode (ED).

[0071] The gate nodes of the switching transistor (SWT) and the sensing transistor (SENT) may be connected together to a single gate line (GL) or to different gate lines (GL). Here, a structure in which the switching transistor (SWT) and the sensing transistor (SENT) are connected to different gate lines (GL) is shown as an example, and in this case, the switching transistor (SWT) and the sensing transistor (SENT) can be independently controlled by a first scan signal (SCAN1) and a second scan signal (SCAN2) transmitted through different gate lines (GL).

[0072] On the other hand, when the switching transistor (SWT) and the sensing transistor (SENT) are connected to a single gate line (GL), the switching transistor (SWT) and the sensing transistor (SENT) can be simultaneously controlled by a first scan signal (SCAN1) or a second scan signal (SCAN2) transmitted through the single gate line (GL), and the aperture ratio of the subpixel (SP) can be increased.

[0073] Meanwhile, the transistors placed in the subpixel (SP) can consist of not only n-type transistors but also p-type transistors; however, the case composed of n-type transistors is shown here as an example.

[0074] The storage capacitor (Cst) is electrically connected between the first node (N1) and the second node (N2) of the driving transistor (DRT) and maintains the data voltage (Vdata) for one frame.

[0075] These storage capacitors (Cst) may be connected between the first node (N1) and the third node (N3) of the driving transistor (DRT) depending on the type of driving transistor (DRT). The anode electrode of the light-emitting diode (ED) may be electrically connected to the second node (N2) of the driving transistor (DRT), and a base voltage (EVSS) may be applied to the cathode electrode of the light-emitting diode (ED).

[0076] Here, the base voltage (EVSS) may be a ground voltage or a voltage higher or lower than the ground voltage. Additionally, the electromotive force voltage (EVSS) may vary depending on the driving state, for example, the base voltage (EVSS) at the time of display driving and the base voltage (EVSS) at the time of sensing driving may be set differently from each other.

[0077] The switching transistor (SWT) and the sensing transistor (SENT) can be described as scan transistors controlled by scan signals (SCAN1, SCAN2).

[0078] The structure of these subpixels (SPs) may include one or more additional transistors, or in some cases, one or more additional capacitors.

[0079] The display device (100) of the present disclosure may use a method of measuring the current flowing by the voltage charged to the storage capacitor (Cst) during the characteristic value sensing period of the driving transistor (DRT) in order to effectively sense the characteristic value of the driving transistor (DRT), for example, threshold voltage or mobility, and this is called current sensing.

[0080] That is, by measuring the current flowing due to the voltage charged in the storage capacitor (Cst) during the characteristic value sensing period of the driving transistor (DRT), the characteristic value of the driving transistor (DRT) within the subpixel (SP) or the change in the characteristic value can be determined.

[0081] In this case, since the reference voltage line (RVL) not only serves to transmit the reference voltage (Vref) but also acts as a sensing line to sense the characteristic value of the driving transistor (DRT) within the subpixel, the reference voltage line (RVL) may also be referred to as a sensing line or a sensing channel.

[0082] More specifically, the characteristic value or change in the characteristic value of the driving transistor (DRT) can correspond to the difference between the gate node voltage and the source node voltage of the driving transistor (DRT).

[0083] Compensation of the characteristic value of such driving transistors (DRT) can be performed as internal compensation, which senses and compensates the characteristic value of the driving transistors (DRT) within the subpixel (SP) without using additional external configuration, or as external compensation, which senses and compensates the characteristic value of the driving transistors (DRT) using an external compensation circuit.

[0084] At this time, external compensation may be performed before shipment of the display device (100), and internal compensation may be performed after shipment of the display device (100), but internal compensation and external compensation may also be performed together after shipment of the display device (100).

[0085] FIG. 4 is a diagram illustrating an example of a display panel in which a gate driving circuit is implemented as a GIP type in a display device according to embodiments of the present disclosure.

[0086] Referring to FIG. 4, in a display device (100) according to embodiments of the present disclosure, 2n gate lines (GL(1) ~ GL(2n), n is a natural number) may be arranged in a display area (A / A) that displays an image on a display panel (110).

[0087] At this time, the gate driving circuit (120) is embedded in a non-display area corresponding to the outer edge of the display area (A / A) of the display panel (110) and may include 2n gate lines (GL(1) ~ GL(2n)) and 2n GIP circuits (GIPC) corresponding to each other.

[0088] Therefore, 2n GIP circuits (GIPC) can output a scan signal (SCAN) with 2n gate lines (GL(1) to GL(2n)).

[0089] In this way, when the gate driving circuit (120) is implemented as a GIP type, there is no need to manufacture a separate integrated circuit with a gate driving function and bond it to the display panel (110), so the number of integrated circuits can be reduced and the process of connecting the integrated circuits to the display panel (110) can be omitted. In addition, the size of the bezel area for bonding the integrated circuits to the display panel (110) can be reduced.

[0090] 2n GIP circuits (GIPC) can be distinguished from each other and identified as GIPC (1), GIPC (2), … GIPC (2n) in order to identify the correspondence with 2n gate lines (GL (1) ~ GL (2n)).

[0091] Here, a case is illustrated in which 2n GIP circuits (GIPC(1) to GIPC(2n)) are divided and arranged on both sides of a display area (A / A). For example, among the 2n GIP circuits (GIPC(1) to GIPC(2n)), the odd-numbered GIP circuits (GIPC(1), GIPC(3), …, GIPC(2n-1)) can drive the odd-numbered gate lines (GL(1), GL(3), …, GL(2n-1)). Among the 2n GIP circuits (GIPC(1) to GIPC(2n)), the even-numbered GIP circuits (GIPC(2), GIPC(4), …, GIPC(2n)) can drive the even-numbered gate lines (GL(2), GL(4), …, GL(2n)).

[0092] Alternatively, 2n GIP circuits (GIPC (1) to GIPC (2n)) may be placed on only one side of the display area (A / A).

[0093] In the non-display area corresponding to the outer edge of the display area (A / A) of the display panel (110), a plurality of clock lines (CL) may be arranged to transmit a gate clock required for the generation and output of a scan signal (SCAN) to a gate driving circuit (120).

[0094] FIG. 5 is a block diagram showing the schematic configuration of a gate driving integrated circuit in a display device according to embodiments of the present disclosure.

[0095] Referring to FIG. 5, in a display device (100) according to embodiments of the present disclosure, one it driving integrated circuit may include a shift register (122) and a buffer circuit (124).

[0096] The gate driver integrated circuit starts operating according to the gate start pulse (GSP) and outputs a scan signal (SCAN) according to the gate clock (GCLK). The scan signal (SCAN) output from the gate driver integrated circuit is sequentially shifted and supplied sequentially through the gate line (GL).

[0097] The buffer circuit (124) has two nodes (Q, QB) important for the gate driving state and may include a pull-up transistor (TU) and a pull-down transistor (TD). Here, the gate node of the pull-up transistor (TU) may correspond to the Q node, and the gate node of the pull-down transistor (TD) may correspond to the QB node.

[0098] The shift register (122) can also be called a shift logic circuit and can be used to generate a scan signal (SCAN) synchronized with the gate clock (GCLK).

[0099] The shift register (122) can control the Q node and QB node connected to the buffer circuit (124) so ​​that the buffer circuit (124) can output a scan signal (SCAN), and for this purpose, it may include a plurality of transistors.

[0100] The shift register (122) starts generating a scan signal (SCAN) and the output of the shift register (122) is turned on sequentially according to the gate clock (GCLK). That is, by controlling the output time of the shift register (122) using the gate clock (GCLK), the logic state determining the on / off of the gate line (GL) can be transmitted to the buffer circuit (124).

[0101] According to this shift register (122), the voltage state of each of the Q node and QB node of the buffer circuit (124) may change. Accordingly, the buffer circuit (124) may output a voltage to turn on the corresponding gate line (GL) (e.g., corresponding to a high level voltage or a low level voltage, and may be a signal having a gate high voltage (VGH), for example) to the corresponding gate line (GL), or output a voltage to turn off the corresponding gate line (GL) (e.g., corresponding to a low level voltage or a high level voltage, and may be a base voltage (VSS) having a gate low voltage (VGL), for example) to the corresponding gate line (GL).

[0102] Meanwhile, a gate driving integrated circuit may further include a level shifter in addition to the shift register (122) and buffer circuit (124).

[0103] At this time, the shift register (122) and buffer circuit (124) constituting the gate driving integrated circuit can be connected in various structures.

[0104] FIG. 6 is a diagram showing a plurality of stage circuit configurations constituting a gate driving circuit according to embodiments of the present disclosure.

[0105] Referring to FIG. 6, a gate driving circuit (120) according to another embodiment of the present specification includes a first stage circuit (ST(1)) to a k-th stage circuit (ST(k)) (k is a positive integer), a gate driving voltage line (131), a clock line (132), a line sensing signal line (133), a reset signal line (134), and a panel on signal line (135).

[0106] Here, each stage circuit (ST) may correspond to a gate driving integrated circuit (GDIC) or GIP circuit that constitutes the gate driving circuit (120).

[0107] Additionally, the gate driving circuit (120) may further include a front dummy stage circuit (DST1) placed at the front end of the first stage circuit (ST(1)) and a rear dummy stage circuit (DST2) placed at the rear end of the k-th stage circuit (ST(k)).

[0108] The gate driving voltage line (131) supplies a high potential gate voltage (GVDD) and a low potential gate voltage (GVSS) supplied from the power management circuit (150) to the first to k-th stage circuits (ST(1) to ST(k)), the front dummy stage circuit (DST1), and the rear dummy stage circuit (DST2), respectively.

[0109] The gate driving voltage line (131) may include a plurality of high-potential gate voltage lines supplying a plurality of high-potential gate voltages having different voltage levels and a plurality of low-potential gate voltage lines supplying a plurality of low-potential gate voltages having different voltage levels.

[0110] For example, the gate driving voltage line (131) may include three high-potential gate voltage lines supplying a first high-potential gate voltage (GVDD1), a second high-potential gate voltage (GVDD2), and a third high-potential gate voltage (GVDD3) having different voltage levels, respectively, and three low-potential gate voltage lines supplying a first low-potential gate voltage (GVSS1), a second low-potential gate voltage (GVSS2), and a third low-potential gate voltage (GVSS3) having different voltage levels, respectively. However, this is only one example, and the number of lines included in the gate driving voltage line (131) may vary depending on the embodiment.

[0111] The clock line (132) supplies a plurality of clocks (CLKs), such as a carry clock or a gate clock, supplied from the timing controller (140) to the first to k-th stage circuits (ST(1) to ST(k)), the front dummy stage circuit (DST1), and the rear dummy stage circuit (DST2), respectively.

[0112] The line sensing signal line (133) supplies a line sensing signal (LSP) supplied from the timing controller (140) to the first to k-th stage circuits (ST(1) to ST(k)). Optionally, the line sensing signal line (133) may be additionally connected to the front dummy stage circuit (DST1).

[0113] The reset signal line (134) supplies a reset signal (RESET) supplied from the timing controller (140) to the first to k-th stage circuits (ST(1) to ST(k)), the front dummy stage circuit (DST1), and the rear dummy stage circuit (DST2), respectively.

[0114] The panel on signal line (135) supplies the panel on signal (POS) supplied from the timing controller (140) to the first to k-th stage circuits (ST(1) to ST(k)), the front dummy stage circuit (DST1), and the rear dummy stage circuit (DST2), respectively.

[0115] In addition, lines for supplying other signals other than the lines shown herein (131, 132, 133, 134, 135) may be additionally connected to the first to k-th stage circuits (ST(1) to ST(k)), the front dummy stage circuit (DST1), and the rear dummy stage circuit (DST2). For example, a line for supplying a gate start pulse (GSP) to the front dummy stage circuit (DST1) may be additionally connected to the front dummy stage circuit (DST1).

[0116] The shear dummy stage circuit (DST1) outputs a shear carry signal (Cd1) in response to the input of a gate start pulse (GSP) supplied from the timing controller (140).

[0117] The front-end carry signal (Cd1) can be supplied to any one of the first to k-th stage circuits (ST(1) to ST(k)).

[0118] The rear dummy stage circuit (DST2) outputs a rear carry signal (Cd2). The rear carry signal (Cd2) can be supplied to any one of the first to k-th stage circuits (ST(1) to ST(k)).

[0119] The first to k-th stage circuits (ST(1) to ST(k)) can be connected to each other in a stepped or cascaded manner.

[0120] The first to k-th stage circuits (ST(1) to ST(k)) each output n scan signals (SCAN) and one carry signal (C) (n is a positive integer). That is, any stage circuit outputs the first to n-th scan signals and one carry signal (C).

[0121] For example, each stage circuit outputs four scan signals (SCAN) and one carry signal (C). For example, the first stage circuit (ST(1)) outputs a first scan signal (SCAN(1)), a second scan signal (SCAN(2)), a third scan signal (SCAN(3)), a fourth scan signal (SCAN(4)), and a first carry signal (C(1)), and the second stage circuit (ST(2)) outputs a fifth scan signal (SCAN(5)), a sixth scan signal (SCAN(6)), a seventh scan signal (SCAN(7)), an eighth scan signal (SCAN(8)), and a second carry signal (C(2)). Thus, in the embodiment here, j is 4.

[0122] The number of scan signals output by the first to k-th stage circuits (ST(1) to ST(k)) corresponds to the number of gate lines (GL) (GN) placed on the display panel (110). As previously mentioned, each of the k stage circuits outputs n scan signals. Therefore, the relationship n×k=GN is established.

[0123] For example, when n=4, the number of stage circuits (k) is 1 / 4 of the number of gate lines (GL) (GN). However, the number of scan signals output by each stage circuit is not limited to this. That is, in the embodiments of the present disclosure, each stage circuit may output one, two, or three scan signals, or may output five or more scan signals. The number of stage circuits may vary depending on the number of scan signals output by each stage circuit.

[0124] The scan signal (SCAN) output by the first to k-th stage circuits (ST(1) to ST(k)) may be a scan signal for sensing the threshold voltage of a driving transistor (DRT) or a gate signal for image display. Additionally, the carry signal (C) output by the first to k-th stage circuits (ST(1) to ST(k)) may be supplied to different stage circuits. Here, the carry signal supplied to any stage circuit from the front stage circuit is referred to as the front carry signal, and the carry signal supplied from the rear stage circuit is referred to as the rear carry signal.

[0125] FIG. 7 is a diagram illustrating an example of a stage circuit constituting a gate driving circuit in a display driving circuit according to embodiments of the present disclosure.

[0126] Referring to FIG. 7, the stage circuit according to embodiments of the present disclosure includes an M node, a Q node, and a QB node, and includes a line selection unit (502), a Q node control unit (504), a Q node stabilization unit (506), an inverter unit (508), a QB node stabilization unit (510), a carry signal output unit (512), and a scan signal output unit (514).

[0127] The line selector (502) charges the M node based on the front-end carry signal (C(k-2)) in response to the input of the line sensing signal (LSP). Additionally, the line selector (502) charges the Q node to the level of the first high-potential gate voltage (GVDD1) based on the charging voltage of the M node in response to the input of the reset signal (RESET). Additionally, the line selector (502) discharges or resets the Q node to the level of the third low-potential gate voltage (GVSS3) in response to the input of the panel-on signal (POS).

[0128] The line selection unit (502) includes 11th to 17th transistors (T11 to T17) and a pre-charging capacitor (CA).

[0129] The 11th transistor (T11) and the 12th transistor (T12) are connected between the first high-potential gate voltage line, which carries the first high-potential gate voltage (GVDD1), and the M node. Additionally, the 11th transistor (T11) and the 12th transistor (T12) are connected in series with each other.

[0130] The 11th transistor (T11) outputs a front-end carry signal (C(k-2)) to the first connection node (NC1) in response to the input of the line sensing signal (LSP).

[0131] The 12th transistor (T12) electrically connects the first connection node (NC1) to the M node in response to the input of a line sensing signal (LSP). For example, when a high voltage line sensing signal (LSP) is input to the 11th transistor (T11) and the 12th transistor (T12), the 11th transistor (T11) and the 12th transistor (T12) are turned on simultaneously, and the M node is charged to the level of the first high potential gate voltage (GVDD1).

[0132] The 13th transistor (T13) is turned on when the voltage level of the M node is high, and supplies the first high potential gate voltage (GVDD1) to the first connection node (NC1). When the first high potential gate voltage (GVDD1) is supplied to the first connection node (NC1), the voltage difference between the gate voltage of the 11th transistor (T11) and the first connection node (NC1) increases.

[0133] Accordingly, when a low-level line sensing signal (LSP) is input to the gate node of the 11th transistor (T11) and the 11th transistor (T11) is turned off, the 11th transistor (T11) can be kept in a completely turned-off state due to the voltage difference between the gate voltage of the 11th transistor (T11) and the first connection node (NC1). Accordingly, current leakage of the 11th transistor (T11) and the resulting voltage drop of the M node are prevented, so the voltage of the M node can be maintained stably.

[0134] A pre-charging capacitor (CA) is connected between the first high-potential gate voltage line that delivers the first high-potential gate voltage (GVDD1) and the M node to store the difference between the first high-potential gate voltage (GVDD1) and the voltage charged at the M node.

[0135] When the 11th transistor (T11), the 12th transistor (T12), and the 13th transistor (T13) are turned on, the pre-charging capacitor (CA) stores the high voltage of the front-end carry signal (C(k-2)). When the 11th transistor (T11), the 12th transistor (T12), and the 13th transistor (T13) are turned off, the pre-charging capacitor (CA) maintains the voltage of the M node for a certain period of time with the stored voltage.

[0136] The 14th transistor (T14) and the 15th transistor (T15) are connected between the first high-potential gate voltage line, which carries the first high-potential gate voltage (GVDD1), and the Q node. The 14th transistor (T14) and the 15th transistor (T15) are connected in series with each other.

[0137] The 14th transistor (T14) and the 15th transistor (T15) charge the Q node to the first high potential gate voltage (GVDD1) in response to the voltage of the M node and the input of the reset signal (RESET).

[0138] The 14th transistor (T14) is turned on when the voltage of the M node is at a high level to deliver the first high potential gate voltage (GVDD1) to the shared node of the 14th transistor (T14) and the 15th transistor (T15).

[0139] The 15th transistor (T15) is turned on by a high-level reset signal (RESET) to supply the voltage of the shared node to the Q node. Thus, when the 14th transistor (T14) and the 15th transistor (T15) are turned on simultaneously, the Q node is charged to the first high-potential gate voltage (GVDD1).

[0140] The 16th transistor (T16) and the 17th transistor (T17) are connected between the Q node and the third low-potential gate voltage line that carries the third low-potential gate voltage (GVSS3). The 16th transistor (T16) and the 17th transistor (T17) are connected in series with each other.

[0141] The 16th transistor (T16) and the 17th transistor (T17) discharge the Q node to the third low-potential gate voltage (GVSS3) in response to the input of the panel-on signal (POS). Discharging the Q node to the third low-potential gate voltage (GVSS3) can also be expressed as the Q node being reset.

[0142] The 17th transistor (T17) is turned on by the input of a high-level panel-on signal (POS) to supply a third low-potential gate voltage (GVSS3) to the QH node.

[0143] The 16th transistor (T16) is turned on upon input of a high-level panel-on signal (POS) to electrically connect the Q node and the QH node. Thus, when the 16th transistor (T16) and the 17th transistor (T17) are turned on simultaneously, the Q node is discharged or reset to the third low-potential gate voltage (GVSS3).

[0144] The Q node control unit (504) charges the Q node to the level of the first high potential gate voltage (GVDD1) in response to the input of the front carry signal (C(k-2)), and discharges the Q node to the level of the third low potential gate voltage (GVSS3) in response to the input of the rear carry signal (C(k+2)).

[0145] The Q node control unit (504) includes 21 to 28 transistors (T21 to T28).

[0146] The 21st transistor (T21) and the 22nd transistor (T22) are connected between the first high-potential gate voltage line and the Q node, which transmits the first high-potential gate voltage (GVDD1). The 21st transistor (T21) and the 22nd transistor (T22) are connected in series with each other.

[0147] The 21st transistor (T21) and the 22nd transistor (T22) charge the Q node to the first high potential gate voltage (GVDD1) level in response to the input of the front-end carry signal (C(k-2)).

[0148] The 21st transistor (T21) is turned on upon input of the front-end carry signal (C(k-2)) to supply the first high-potential gate voltage (GVDD1) to the second connection node (NC2).

[0149] The 22nd transistor (T22) is turned on upon input of the front-end carry signal (C(k-2)) to electrically connect the 2nd connection node (NC2) and the Q node. Thus, when the 21st transistor (T21) and the 22nd transistor (T22) are turned on simultaneously, the 1st high-potential gate voltage (GVDD1) is supplied to the Q node.

[0150] The 25th transistor (T25) and the 26th transistor (T26) are connected to a third high-potential gate voltage line that delivers a third high-potential gate voltage (GVDD3). The 25th transistor (T25) and the 26th transistor (T26) supply the third high-potential gate voltage (GVDD3) to the second connection node (NC2) in response to the third high-potential gate voltage (GVDD3).

[0151] The 25th transistor (T25) and the 26th transistor (T26) are simultaneously turned on by the third high potential gate voltage (GVDD3) to continuously supply the third high potential gate voltage (GVDD3) to the second connection node (NC2), thereby increasing the voltage difference between the gate voltage of the 21st transistor (T21) and the second connection node (NC2). Therefore, when a low-level front-end carry signal (C(k-2)) is input to the gate node of the 21st transistor (T21) and the 21st transistor (T21) is turned off, the 21st transistor (T21) can be kept in a completely turned-off state due to the voltage difference between the gate voltage of the 21st transistor (T21) and the second connection node (NC2).

[0152] Accordingly, current leakage of the 21st transistor (T21) and the resulting voltage drop of the Q node are prevented, so the voltage of the Q node can be maintained stably.

[0153] For example, when the threshold voltage of the 21st transistor (T21) is negative (-), the gate-source voltage (Vgs) of the 21st transistor (T21) is maintained as negative (-) by the third high potential gate voltage (GVDD3) supplied to the drain electrode.

[0154] Therefore, when a low-level front-end carry signal (C(k-2)) is input to the gate node of the 21st transistor (T21) and the 21st transistor (T21) is turned off, the 21st transistor (T21) remains in a completely turned-off state, thereby preventing the occurrence of leakage current.

[0155] Here, the third high potential gate voltage (GVDD3) is set to a voltage level lower than the first high potential gate voltage (GVDD1).

[0156] The 23rd transistor (T23) and the 24th transistor (T24) are connected between the Q node and the third low-potential gate voltage line that carries the third low-potential gate voltage (GVSS3). The 23rd transistor (T23) and the 24th transistor (T24) are connected in series with each other.

[0157] The 23rd transistor (T23) and the 24th transistor (T24) discharge the Q node and QH node to the 3rd low potential gate voltage (GVSS3) level in response to the input of the rear carry signal (C(k+2)).

[0158] The 24th transistor (T24) is turned on upon input of the subsequent carry signal (C(k+2)) to discharge the QH node to the level of the third low potential gate voltage (GVSS3). The 23rd transistor (T23) is turned on upon input of the subsequent carry signal (C(k+2)) to electrically connect the Q node and the QH node. Therefore, when the 23rd transistor (T23) and the 24th transistor (T24) are turned on simultaneously, the Q node and the QH node are discharged or reset to the level of the third low potential gate voltage (GVSS3), respectively.

[0159] The 27th transistor (T27) and the 28th transistor (T28) are connected between the first high-potential gate voltage line carrying the first high-potential gate voltage (GVDD1) and the Q node, and between the first high-potential gate voltage line carrying the first high-potential gate voltage (GVDD1) and the QH node. The 27th transistor (T27) and the 28th transistor (T28) are connected in series with each other.

[0160] The 27th transistor (T27) and the 28th transistor (T28) supply a first high potential gate voltage (GVDD1) to the QH node in response to the voltage of the Q node. The 27th transistor (T27) is turned on when the voltage of the Q node is at a high level and supplies the first high potential gate voltage (GVDD1) to the shared node of the 27th transistor (T27) and the 28th transistor (T28).

[0161] The 28th transistor (T28) is turned on when the voltage of the Q node is at a high level to electrically connect the shared node and the QH node. Thus, the 27th transistor (T27) and the 28th transistor (T28) are turned on simultaneously when the voltage of the Q node is at a high level to supply the first high potential gate voltage (GVDD1) to the QH node.

[0162] When the first high potential gate voltage (GVDD1) is supplied to the QH node, the voltage difference between the gate node of the 23rd transistor (T23) and the QH node increases. Therefore, when a low-level rear carry signal (C(k+2)) is input to the gate node of the 23rd transistor (T23) and the 23rd transistor (T23) is turned off, the 23rd transistor (T23) can be kept in a completely turned-off state due to the voltage difference between the gate voltage of the 23rd transistor (T23) and the QH node. Accordingly, current leakage of the 23rd transistor (T23) and the resulting voltage drop of the Q node are prevented, and the voltage of the Q node can be maintained stably.

[0163] The Q node stabilization unit (506) discharges the Q node and QH node to the level of the third low potential gate voltage (GVSS3) in response to the voltage of the QB node. The Q node stabilization unit (506) includes a 31st transistor (T31) and a 32nd transistor (T32). The 31st transistor (T31) and the 32nd transistor (T32) are connected between the Q node and the third low potential gate voltage line that transmits the third low potential gate voltage (GVSS3). The 31st transistor (T31) and the 32nd transistor (T32) are connected in series with each other.

[0164] The 31st transistor (T31) and the 32nd transistor (T32) discharge the Q node and the QH node to the level of the third low potential gate voltage (GVSS3) in response to the voltage of the QB node. The 32nd transistor (T32) is turned on when the voltage of the QB node is at a high level to supply the third low potential gate voltage (GVSS3) to the shared node of the 31st transistor (T31) and the 32nd transistor (T32).

[0165] The 31st transistor (T31) is turned on when the voltage of the QB node is at a high level, electrically connecting the Q node and the QH node. Thus, when the 31st transistor (T31) and the 32nd transistor (T32) are turned on simultaneously in response to the voltage of the QB node, the Q node and the QH node are discharged or reset to the level of the third low potential gate voltage (GVSS3), respectively.

[0166] The inverter section (508) changes the voltage level of the QB node according to the voltage level of the Q node. The inverter section (508) includes the 41st to 45th transistors (T41 to T45).

[0167] The 42nd transistor (T42) and the 43rd transistor (T43) are connected between the second high-potential gate voltage line, which carries the second high-potential gate voltage (GVDD2), and the third connection node (NC3). The 42nd transistor (T42) and the 43rd transistor (T43) are connected in series with each other.

[0168] The 42nd transistor (T42) and the 43rd transistor (T43) supply the 2nd high-potential gate voltage (GVDD2) to the 3rd connection node (NC3) in response to the 2nd high-potential gate voltage (GVDD2). The 42nd transistor (T42) is turned on by the 2nd high-potential gate voltage (GVDD2) to supply the 2nd high-potential gate voltage (GVDD2) to the shared node of the 42nd transistor (T42) and the 43rd transistor (T43).

[0169] The 43rd transistor (T43) is turned on by the second high potential gate voltage (GVDD2) to electrically connect the shared node of the 42nd transistor (T42) and the 43rd transistor (T43) with the third connection node (NC3). Thus, when the 42nd transistor (T42) and the 43rd transistor (T43) are turned on simultaneously by the second high potential gate voltage (GVDD2), the third connection node (NC3) is charged to the level of the second high potential gate voltage (GVDD2).

[0170] The 44th transistor (T44) is connected between the 3rd connection node (NC3) and the 2nd low-potential gate voltage line that carries the 2nd low-potential gate voltage (GVSS2).

[0171] The 44th transistor (T44) supplies a second low-potential gate voltage (GVSS2) to the third connection node (NC3) in response to the voltage of the Q node. The 44th transistor (T44) is turned on when the voltage of the Q node is at a high level to discharge or reset the third connection node (NC3) to the second low-potential gate voltage (GVSS2).

[0172] The 41st transistor (T41) is connected between the second high-potential gate voltage line, which carries the second high-potential gate voltage (GVDD2), and the QB node.

[0173] The 41st transistor (T41) supplies a second high-potential gate voltage (GVDD2) to the QB node in response to the voltage of the third connection node (NC3). The 41st transistor (T41) is turned on when the voltage of the third connection node (NC3) is at a high level to charge the QB node to the level of the second high-potential gate voltage (GVDD2).

[0174] The 45th transistor (T45) is connected between the QB node and the third low-potential gate voltage line that carries the third low-potential gate voltage (GVSS3).

[0175] The 45th transistor (T45) supplies a third low potential voltage (GVSS3) to the QB node in response to the voltage of the Q node. The 45th transistor (T45) is turned on when the voltage of the Q node is at a high level to discharge or reset the QB node to the third low potential gate voltage (GVSS3) level.

[0176] The QB node stabilization unit (510) discharges the QB node to the level of the third low potential gate voltage (GVSS3) in response to the input of the rear carry signal (C(k-2)), the input of the reset signal (RESET), and the charging voltage of the M node. The QB node stabilization unit (510) includes the 51st to 53rd transistors (T51 to T53).

[0177] The 51st transistor (T51) is connected between the QB node and the third low-potential gate voltage line that carries the third low-potential gate voltage (GVSS3).

[0178] The 51st transistor (T51) supplies a third low-potential gate voltage (GVSS3) to the QB node in response to the input of the rear carry signal (C(k-2)).

[0179] The 52nd transistor (T52) and the 53rd transistor (T53) are connected between the QB node and the third low-potential gate voltage line that carries the third low-potential gate voltage (GVSS3). The 52nd transistor (T52) and the 53rd transistor (T53) are connected in series with each other.

[0180] The 52nd transistor (T52) and the 53rd transistor (T53) discharge the QB node to the 3rd low potential gate voltage (GVSS3) level in response to the input of the reset signal (RESET) and the charging voltage of the M node.

[0181] The 53rd transistor (T53) is turned on when the voltage of the M node is at a high level and supplies a third low-potential gate voltage (GVSS3) to the shared node of the 52nd transistor (T52) and the 53rd transistor (T53).

[0182] The 52nd transistor (T52) is turned on by the input of a reset signal (RESET) to electrically connect the shared node of the 52nd transistor (T52) and the 53rd transistor (T53) with the QB node. Therefore, when a reset signal (RESET) is input while the voltage of the M node is at a high level, the 52nd transistor (T52) and the 53rd transistor (T53) are turned on simultaneously, and the QB node is discharged or reset to the level of the third low potential gate voltage (GVSS2).

[0183] The carry signal output unit (512) outputs a carry signal (C(k)) based on the voltage level of the carry clock (CRCLK(k)) or the third low potential gate voltage (GVSS3) level according to the voltage level of the Q node or the voltage level of the QB node.

[0184] The carry signal output section (512) includes a 61st transistor (T61), a 62nd transistor (T62), and a boosting capacitor (CC).

[0185] The 61st transistor (T61) is connected between the clock line that carries the carry clock (CRCLK(k)) and the first output node (NO1). A boosting capacitor (CC) is connected between the gate node and the source node of the 61st transistor (T61).

[0186] The 61st transistor (T61) outputs a high-level carry signal (C(k)) through the first output node (NO1) based on the carry clock (CRCLK(k)) in response to the voltage of the Q node. The 61st transistor (T61) is turned on when the voltage of the Q node is at a high level and supplies the high-level carry clock (CRCLK(k)) to the first output node (NO1). Accordingly, a high-level carry signal (C(k)) is output.

[0187] When the carry signal (C(k)) is output, the boosting capacitor (CC) bootstraps the voltage of the Q node to a boosting voltage level higher than the level of the first high potential gate voltage (GVDD1) in synchronization with the high level carry clock (CRCLK(k)). When the voltage of the Q node is bootstrapped, the high level carry clock (CRCLK(k)) can be output as the carry signal (C(k)) quickly and without distortion.

[0188] The 62nd transistor (T62) is connected between the first output node (NO1) and the third low-potential gate voltage line that carries the third low-potential gate voltage (GVSS3).

[0189] The 62nd transistor (T62) outputs a low-level carry signal (C(k)) through the first output node (NO1) based on the third low-potential gate voltage (GVSS3) in response to the voltage of the QB node. The 62nd transistor (T62) is turned on when the voltage of the QB node is at a high level and supplies the third low-potential voltage (GVSS3) to the first output node (NO1). Accordingly, a low-level carry signal (C(k)) is output.

[0190] The scan signal output unit (514) outputs a plurality of scan signals (SCAN(i), SCAN(i+1), SCAN(i+2), SCAN(i+3)) based on the voltage levels of a plurality of scan clocks (SCCLK(i), SCCLK(i+1), SCCLK(i+2), SCCLK(i+3)) or the first low potential gate voltage (GVSS1) level, depending on the voltage level of the Q node or the voltage level of the QB node. (i is a positive integer)

[0191] Here, multiple scan clocks (SCCLK(i), SCCLK(i+1), SCCLK(i+2), SCCLK(i+3)) are signals corresponding to the gate clock (GCLK), and may vary depending on the number of scan signals (SCAN(i), SCAN(i+1), SCAN(i+2), SCAN(i+3)) output from the gate driving integrated circuit (GDIC).

[0192] The scan signal output unit (514) includes the 71st to 78th transistors (T71 to T78) and boosting capacitors (CS1, CS2, CS3, CS4).

[0193] The 71st transistor (T71), the 73rd transistor (T73), the 75th transistor (T75), and the 77th transistor (T77) are each connected between a clock line that transmits a scan clock (SCCLK(i), SCCLK(i+1), SCCLK(i+2), SCCLK(i+3)) and the 2nd to 5th output nodes (NO2 to NO5).

[0194] Boosting capacitors (CS1, CS2, CS3, CS4) are connected between the gate node and the source node of the 71st transistor (T71), the 73rd transistor (T73), the 75th transistor (T75), and the 77th transistor (T77), respectively.

[0195] The 71st transistor (T71), the 73rd transistor (T73), the 75th transistor (T75), and the 77th transistor (T77) each output a high-level scan signal (SCAN(i), SCAN(i+1), SCAN(i+2), SCAN(i+3)) through the 2nd output node (NO2), the 3rd output node (NO3), the 4th output node (NO4), and the 5th output node (NO5) based on the scan clock (SCCLK(i), SCCLK(i+1), SCCLK(i+2), SCCLK(i+3)) in response to the voltage of the Q node.

[0196] The 71st transistor (T71), the 73rd transistor (T73), the 75th transistor (T75), and the 77th transistor (T77) are turned on when the voltage of the Q node is at a high level, and supply high-level scan clocks (SCCLK(i), SCCLK(i+1), SCCLK(i+2), SCCLK(i+3)) to the 2nd output node (NO2), the 3rd output node (NO3), the 4th output node (NO4), and the 5th output node (NO5), respectively. Accordingly, high-level scan signals (SCAN(i), SCAN(i+1), SCAN(i+2), SCAN(i+3)) are output, respectively.

[0197] The 71st transistor (T71), the 73rd transistor (T73), the 75th transistor (T75), and the 77th transistor (T77) each correspond to pull-up transistors.

[0198] When a scan signal (SCAN(i), SCAN(i+1), SCAN(i+2), SCAN(i+3)) is output, the boosting capacitors (CS1, CS2, CS3, CS4) bootstrap or increase the voltage of the Q node to a boosting voltage level higher than the first high potential gate voltage (GVDD1) level in synchronization with the high level scan clock (SCCLK(i), SCCLK(i+1), SCCLK(i+2), SCCLK(i+3)). When the voltage of the Q node is bootstrapped, the high level scan clock (SCCLK(i), SCCLK(i+1), SCCLK(i+2), SCCLK(i+3)) can be output as a scan signal (SCAN(i), SCAN(i+1), SCAN(i+2), SCAN(i+3)) quickly and without distortion.

[0199] The 72nd transistor (T72), the 74th transistor (T74), the 76th transistor (T76), and the 78th transistor (T78) each output a low-level scan signal (SCAN(i), SCAN(i+1), SCAN(i+2), SCAN(i+3)) through the 2nd output node (NO2), the 3rd output node (NO3), the 4th output node (NO4), and the 5th output node (NO5) respectively, based on the 1st low-potential gate voltage (GVSS1) in response to the voltage of the QB node.

[0200] The 72nd transistor (T72), the 74th transistor (T74), the 76th transistor (T76), and the 78th transistor (T78) are turned on when the voltage of the QB node is at a high level, and supply the 1st low potential gate voltage (GVSS1) to the 2nd output node (NO2), the 3rd output node (NO3), the 4th output node (NO4), and the 5th output node (NO5), respectively. Accordingly, low-level scan signals (SCAN(i), SCAN(i+1), SCAN(i+2), SCAN(i+3)) are output.

[0201] The 72nd transistor (T72), the 74th transistor (T74), the 76th transistor (T76), and the 78th transistor (T78) each correspond to a pull-down transistor.

[0202] Here, a case is illustrated in which three high-potential gate voltages (GVDD1, GVDD2, GVDD3) set to different levels and three low-potential gate voltages (GVSS1, GVSS2, GVSS3) set to different levels are supplied to each stage circuit. For example, the first high-potential gate voltage (GVDD1) may be set to 20V, the second high-potential gate voltage (GVDD2) to 16V, and the third high-potential gate voltage (GVDD3) to 14V, and the first low-potential gate voltage (GVSS1) may be set to -6V, the second low-potential gate voltage (GVSS2) to -10V, and the third low-potential gate voltage (GVSS3) to -12V. These figures are merely examples, and the levels of the high-potential gate voltages and low-potential gate voltages may be set differently depending on the embodiment.

[0203] FIG. 8 is a diagram illustrating an example in which 12-phase scan clock lines are sequentially arranged when four scan signals are output from a single gate driving integrated circuit, and FIG. 9 is a diagram illustrating an example of a signal waveform in which 12-phase scan clock lines are sequentially arranged.

[0204] Referring to FIGS. 8 and 9, a plurality of gate driving integrated circuits (GDIC (1), GDIC (2), GDIC (3), GDIC (4), …) constituting the gate driving circuit (120) may have 12 scan clocks (SCCLK (1)-SCCLK (12)) with different phases applied to correspond to scan signals (SCAN (1)-SCAN (16)).

[0205] Here, the case of 12-phase driving in which 12 scan clocks (SCCLK(1)-SCCLK(12)) are applied sequentially is shown as an example, and it can be changed to various structures such as 8-phase or 16-phase scan clocks.

[0206] The 12-phase scan clocks (SCCLK(1)-SCCLK(12)) may be pulse signals with different phases. The phases of the 12-phase scan clocks (SCCLK(1)-SCCLK(12)) are predetermined according to the clock order, and the phase is faster as the clock number decreases. Therefore, among the 12-phase scan clocks (SCCLK(1)-SCCLK(12)), the phase of the 1st scan clock (SCCLK(1)) is the fastest, and the phase of the 12th scan clock (SCCLK(12)) is the slowest.

[0207] All 12 phase scan clocks (SCCLK(1)-SCCLK(12)) have the same pulse width, but here it shows a case where they have a pulse width of 2 horizontal periods (2H).

[0208] Additionally, the 12-phase scan clocks (SCCLK(1)-SCCLK(12)) can be delayed in phase at regular time intervals, for example, at intervals of 1 horizontal period (1H). Thus, the 12-phase scan clocks (SCCLK(1)-SCCLK(12)) can overlap with adjacent scan clocks by 1 horizontal period (1H).

[0209] Meanwhile, the gate driving integrated circuits (GDIC (1), GDIC (2), GDIC (3), GDIC (4), …) can each output one or more scan signals, and here, a case is shown in which four scan signals are output from one gate driving integrated circuit.

[0210] The display panel (110) is designed with a narrow spacing between the 12-phase scan clocks (SCCLK(1)-SCCLK(12)) to narrow the bezel width, in which case the parasitic capacitance between the scan clocks (SCCLK(1)-SCCLK(12)) may increase.

[0211] At this time, the influence of parasitic capacitance between scan clocks (SCCLK(1)-SCCLK(12)) may vary depending on signal overlap between adjacent scan clocks (SCCLK(1)-SCCLK(12)) and the number of scan signals output from a single gate driving integrated circuit (GDIC(1), GDIC(2), GDIC(3), GDIC(4), …). As a result, the pulse width of the scan signals (SCAN(1)-SCAN(16)) output from the gate driving integrated circuit (GDIC(1), GDIC(2), GDIC(3), GDIC(4), …) may change, and image quality may be degraded.

[0212] For example, if 12-phase scan clocks (SCCLK(1)-SCCLK(12)) overlap with adjacent scan clocks by 1 horizontal period (1H), parasitic capacitance may be significantly present between scan clocks located at intervals of 1 horizontal period (1H).

[0213] In addition, when four scan signals are output from a single gate-driven integrated circuit, parasitic capacitance caused between four adjacent scan clocks can affect the scan signals.

[0214] FIG. 10 is a diagram illustrating, as an example, parasitic capacitance between scan clocks and distortion of the scan signal caused by this in the structure of FIG. 8 and FIG. 9.

[0215] Referring to FIG. 10, 12-phase scan clocks (SCCLK (1)-SCCLK (12)) can be transmitted at intervals of 1 horizontal period (1H) with a pulse width of 2 horizontal periods (2H). In this case, because adjacent scan clocks overlap by 1 horizontal period (1H), ripple may occur due to parasitic capacitance between scan clocks located at intervals of 1 horizontal period (1H).

[0216] As a result, the scan signal, which has ripple due to parasitic capacitance, may have a time delay greater than 2 horizontal periods (2H).

[0217] For example, when the first scan signal (SCAN (1)) to the fourth scan signal (SCAN (4)) are output from the first gate driving integrated circuit (GDIC (1)), the second scan clock (SCCLK (2)) and the third scan clock (SCCLK (3)) overlap by one horizontal period (1H), so the time delay of the second scan signal (SCAN (2)) and the third scan signal (SCAN (3)) increases, but the time delay of the first scan signal (SCAN (1)) and the fourth scan signal (SCAN (4)) may not increase.

[0218] As a result, the pulse width (WS(3)) of the third scan signal (SCAN(3)) and the pulse width (WS(4)) of the fourth scan signal are different, and a horizontal line defect may occur in the display panel (110).

[0219] Therefore, it is necessary to position the scan clock lines so as to reduce the parasitic capacitance occurring between scan clocks.

[0220] FIG. 11 is a diagram illustrating an example of a scan clock line arrangement that can reduce parasitic capacitance in a display device according to embodiments of the present disclosure, and FIG. 12 is a diagram illustrating an example of a signal waveform according to the scan clock line arrangement of FIG. 11.

[0221] Referring to FIG. 11 and FIG. 12, in a display device (100) according to embodiments of the present disclosure, a plurality of gate driving integrated circuits (GDIC (1), GDIC (2), GDIC (3), GDIC (4), …) constituting a gate driving circuit (120) may be provided with 12 scan clocks (SCCLK (1)-SCCLK (12)) having different phases to correspond to scan signals (SCAN (1)-SCAN (16)).

[0222] All 12 phase scan clocks (SCCLK(1)-SCCLK(12)) have the same pulse width, but here it shows a case where they have a pulse width of 2 horizontal periods (2H).

[0223] Additionally, the 12-phase scan clocks (SCCLK(1)-SCCLK(12)) can be delayed in phase at regular time intervals, for example, at intervals of 1 horizontal period (1H). Thus, the 12-phase scan clocks (SCCLK(1)-SCCLK(12)) can overlap with adjacent scan clocks by 1 horizontal period (1H).

[0224] Additionally, the gate driving integrated circuits (GDIC(1), GDIC(2), GDIC(3), GDIC(4), …) can each output four scan signals. Specifically, the first gate driving integrated circuit (GDIC(1)) can output a first scan signal (SCAN(1)) to a fourth scan signal (SCAN(4)), and the second gate driving integrated circuit (GDIC(2)) can output a fifth scan signal (SCAN(5)) to an eighth scan signal (SCAN(8)). Additionally, the third gate driving integrated circuit (GDIC(3)) can output a ninth scan signal (SCAN(9)) to a twelfth scan signal (SCAN(12)), and the fourth gate driving integrated circuit (GDIC(4)) can output a thirteenth scan signal (SCAN(13)) to a sixteenth scan signal (SCAN(16)).

[0225] At this time, in order to reduce parasitic capacitance caused between scan clocks (SCCLK(1)-SCCLK(12)), it is desirable to arrange the scan clock lines so as to have an overlap interval between the scan clocks (SCCLK(1)-SCCLK(12)) and a spacing greater than the number of scan signals output from a single gate driving integrated circuit (GDIC(1), GDIC(2), GDIC(3), GDIC(4), …).

[0226] For example, if 12-phase scan clocks (SCCLK(1)-SCCLK(12)) have a pulse width of 2 horizontal periods (2H) and overlap with adjacent scan clocks by 1 horizontal period (1H), the overlap interval of the scan clocks (SCCLK(1)-SCCLK(12)) can be 2.

[0227] In this case, it is preferable that consecutive scan clock lines be arranged at intervals of two or more. That is, a third scan clock line is placed on the side of the first scan clock line, and a fifth scan clock line is placed on the side of the third scan clock line.

[0228] In addition, when four scan signals are output from a single gate driving integrated circuit, it is desirable to arrange consecutive scan clock lines at intervals of four or more to reduce the effect of parasitic capacitance caused between four adjacent scan clocks. That is, a fifth scan clock line is placed on the side of a first scan clock line, and a ninth scan clock line is placed on the side of a fifth scan clock line.

[0229] At this time, when considering the overlap interval of the scan clocks, it is effective to arrange the order of adjacent scan clock lines with a spacing of 2 or more, and when considering the number of scan signals (4) output from one gate driving integrated circuit, it is effective to arrange the order of adjacent scan clock lines with a spacing of 4 or more. Therefore, by simultaneously considering the overlap interval of the scan clocks and the number of scan signals output from one gate driving integrated circuit, it will be effective to arrange the order of adjacent scan clock lines with a spacing of 4 or more.

[0230] FIG. 13 is a diagram illustrating an example in which image defects are improved by preventing distortion of scan clocks and scan signals in a display device according to embodiments of the present disclosure.

[0231] Referring to FIG. 13, in a display device (100) according to embodiments of the present disclosure, 12-phase scan clocks (SCCLK (1)-SCCLK (12)) can be transmitted at intervals of 1 horizontal period (1H) with a pulse width of 2 horizontal periods (2H). At this time, since adjacent scan clocks overlap by 1 horizontal period (1H), the order of adjacent scan clock lines can be arranged at intervals greater than 1 horizontal period (1H).

[0232] In addition, when four scan signals are output from a single gate-driven integrated circuit, the order of adjacent scan clock lines can be arranged with a spacing of four or more to reduce the effect of parasitic capacitance caused between four adjacent scan clocks.

[0233] As a result, the influence of parasitic capacitance caused by adjacent scan clocks is reduced, and the pulse width of the scan signal output from the gate driving integrated circuit can be maintained constant.

[0234] For example, when the first scan signal (SCAN (1)) to the fourth scan signal (SCAN (4)) are output from the first gate driving integrated circuit (GDIC (1)), the second scan clock (SCCLK (2)) and the third scan clock (SCCLK (3)) do not overlap with each other because the numbers of adjacent scan clock lines are spaced apart by four or more.

[0235] Accordingly, the pulse widths of the first scan signal (SCAN(1)) to the fourth scan signal (SCAN(4)) output from the first gate driving integrated circuit (GDIC(1)) are maintained identically. As a result, the pulse width (WS(3)) of the third scan signal (SCAN(3)) and the pulse width (WS(4)) of the fourth scan signal become identical, so that no horizontal line defects occur in the display panel (110).

[0236] The embodiments of the present disclosure described above are briefly explained as follows.

[0237] The display panel (110) of the present disclosure comprises a plurality of subpixels (SP) disposed in an area where a plurality of gate lines (GL) and a plurality of data lines (DL) intersect, a plurality of gate-in-panel circuits (GIPC) that supply a plurality of scan signals (SCAN) to the plurality of subpixels (SP) through the plurality of gate lines (GL), and a plurality of scan clock lines that supply a plurality of scan clocks (SCCLK) corresponding to the plurality of scan signals (SCAN) to the plurality of gate-in-panel circuits (GIPC). The arrangement order of the adjacent scan clock lines may be determined according to the overlap interval between adjacent scan clocks or the number of scan signals (SCAN) output from each gate-in-panel circuit (GIPC).

[0238] The overlap interval between the adjacent scan clocks can be determined by the pulse width of the scan clock (SCCLK) and the phase difference between the adjacent scan clocks.

[0239] When the pulse width of the scan clock (SCCLK) is 2 horizontal periods (2H) and the adjacent scan clocks have a phase difference of 1 horizontal period (1H), the overlap interval between the adjacent scan clocks is 2, and the arrangement order of the adjacent scan clock lines can be determined with a spacing of 2 or more.

[0240] When the number of scan signals (SCAN) output from each gate-in-panel circuit (GIPC) is 4, the arrangement order of the adjacent scan clock lines can be determined with a spacing of 4 or more.

[0241] The arrangement order of the adjacent scan clock lines can be set as the larger value between the overlap interval between the adjacent scan clocks and the number of scan signals (SCAN) output from each gate-in-panel circuit (GIPC) as the spacing interval.

[0242] The plurality of gate-in-panel circuits (GIP) comprises a line selection unit (502) configured to charge an M node based on a front-end carry signal in response to the input of a line sensing signal and to discharge a Q node to the level of a third low-potential gate voltage in response to the input of a panel-on signal; a Q node control unit (504) configured to charge the Q node to the level of a first high-potential gate voltage in response to the front-end carry signal and to discharge the Q node to the level of the third low-potential gate voltage in response to the input of a rear-end carry signal; a Q node stabilization unit (506) configured to discharge the Q node and QH node to the level of the third low-potential gate voltage in response to the voltage of the QB node; an inverter unit (508) configured to change the voltage level of the QB node according to the second low-potential gate voltage and the voltage level of the Q node; and to discharge the QB node to the level of the third low-potential gate voltage in response to the rear-end carry signal, the reset signal, and the charging voltage of the M node. It may include a QB node stabilization unit (510) configured to discharge, a carry signal output unit (512) configured to output a carry signal based on the voltage level of a carry clock or the level of a third low-potential gate voltage according to the voltage level of the Q node or the voltage level of the QB node, and a scan signal output unit (514) configured to output a plurality of scan signals based on the voltage level of a plurality of scan clocks or the level of a first low-potential gate voltage according to the voltage level of the Q node or the voltage level of the QB node.

[0243] Additionally, the display device (100) of the present disclosure comprises a display panel (110) having a plurality of subpixels (SP) arranged thereon, a gate driving circuit (120) including a plurality of gate driving integrated circuits (GDIC) configured to supply a plurality of scan signals (SCAN) to the display panel (110) through a plurality of gate lines (GL), a data driving circuit (130) configured to supply a plurality of data voltages to the display panel (110) through a plurality of data lines (DL), a timing controller (140) configured to control the gate driving circuit (120) and the data driving circuit (130), and a plurality of scan clock lines that supply a plurality of scan clocks (SCCLK) corresponding to the plurality of scan signals (SCAN) to the plurality of gate driving integrated circuits (GDIC), wherein the arrangement order of the adjacent scan clock lines may be determined according to the overlap interval between adjacent scan clocks or the number of scan signals output from each gate driving integrated circuit.

[0244] The gate driving integrated circuit (GDIC) may be a gate-in-panel circuit (GIPC) embedded in the bezel area of ​​the display panel (110).

[0245] The foregoing description is merely an illustrative explanation of the technical concept of the present disclosure, and those skilled in the art to which the present disclosure pertains may make various modifications and variations within the scope of the essential characteristics of the present disclosure. Furthermore, the embodiments disclosed in the present disclosure are intended to explain, not limit, the technical concept of the present disclosure, and thus the scope of the technical concept of the present disclosure is not limited by these embodiments. Explanation of the symbols

[0247] 100: Display device 110: Display panel 120: Gate driving circuit 130: Data driving circuit 131: Gate driving voltage line 132: Clock line 133: Line sensing signal line 134: Reset signal line 140: Timing Controller 150: Power management circuit 160: Main Power Management Circuit 170: Set Board 502: Line selection section 504: Q Node Control Unit 506: Q Node Stabilization Section 508: Inverter section 510: QB Node Stabilization Unit 512: Carry signal output section 514: Scan signal output section

Claims

Claim 1 A display panel comprising: a plurality of subpixels disposed in an area where a plurality of gate lines and a plurality of data lines intersect; a plurality of gate-in-panel (GIP) circuits that supply a plurality of scan signals to the plurality of subpixels through the plurality of gate lines; and a plurality of scan clock lines that supply a plurality of scan clocks corresponding to the plurality of scan signals to the plurality of gate-in-panel (GIP) circuits, wherein the arrangement order of adjacent scan clock lines is determined between the scan clock line to which the Nth (N is a natural number)-th scan signal is applied and the scan clock line to which the N+1-th scan signal is applied, depending on the overlap interval between adjacent scan clocks or the number of scan signals output from each gate-in-panel (GIP) circuit. Claim 2 In claim 1, the display panel in which the overlap interval between adjacent scan clocks is determined by the pulse width of the scan clock and the phase difference between adjacent scan clocks. Claim 3 A display panel according to claim 1, wherein the pulse width of the scan clock is 2 horizontal periods and the adjacent scan clocks have a phase difference of 1 horizontal period, the overlap interval between the adjacent scan clocks is 2, and the arrangement order of the adjacent scan clock lines is determined by a spacing of 2 or more. Claim 4 In claim 1, when the number of scan signals output from each gate-in-panel (GIP) circuit is 4, the arrangement order of adjacent scan clock lines is determined by a spacing of 4 or more. Claim 5 In claim 1, the arrangement order of the adjacent scan clock lines is a display panel in which the larger value between the overlap interval between the adjacent scan clocks and the number of scan signals output from each gate-in-panel (GIP) circuit is used as the spacing interval. Claim 6 In claim 1, the plurality of gate-in-panel (GIP) circuits comprises: a line selector configured to charge an M node based on a front-end carry signal in response to the input of a line sensing signal and to discharge a Q node to the level of a third low-potential gate voltage in response to the input of a panel-on signal; a Q node control unit configured to charge the Q node to the level of a first high-potential gate voltage in response to the front-end carry signal and to discharge the Q node to the level of the third low-potential gate voltage in response to the input of a rear-end carry signal; a Q node stabilization unit configured to discharge the Q node and the QH node to the level of the third low-potential gate voltage in response to the voltage of the QB node; an inverter unit configured to change the voltage level of the QB node according to the second low-potential gate voltage and the voltage level of the Q node; a QB node stabilization unit configured to discharge the QB node to the level of the third low-potential gate voltage in response to the rear-end carry signal, a reset signal, and the charging voltage of the M node; and the voltage level of the Q node or the QB A display panel comprising: a carry signal output unit configured to output a carry signal based on the voltage level of a carry clock or the level of a third low-potential gate voltage according to the voltage level of a node; and a scan signal output unit configured to output a plurality of scan signals based on the voltage level of a plurality of scan clocks or the level of a first low-potential gate voltage according to the voltage level of the Q node or the voltage level of the QB node. Claim 7 A display device comprising: a display panel having a plurality of subpixels arranged thereon; a gate driving circuit including a plurality of gate driving integrated circuits configured to supply a plurality of scan signals to the display panel through a plurality of gate lines; a data driving circuit configured to supply a plurality of data voltages to the display panel through a plurality of data lines; a timing controller configured to control the gate driving circuit and the data driving circuit; and a plurality of scan clock lines supplying a plurality of scan clocks corresponding to the plurality of scan signals to the plurality of gate driving integrated circuits, wherein the arrangement order of adjacent scan clock lines located between the scan clock line to which the N (N is a natural number)th scan signal is applied and the scan clock line to which the N+1th scan signal is applied is determined according to the overlap interval between adjacent scan clocks or the number of scan signals output from each gate driving integrated circuit. Claim 8 In claim 7, the gate driving integrated circuit is a display device that is a gate-in-panel (GIP) circuit embedded in the bezel area of ​​the display panel. Claim 9 A display device according to claim 7, wherein the overlap interval between adjacent scan clocks is determined by the pulse width of the scan clock and the phase difference between adjacent scan clocks. Claim 10 A display device according to claim 7, wherein the pulse width of the scan clock is 2 horizontal periods and the adjacent scan clocks have a phase difference of 1 horizontal period, the overlap interval between the adjacent scan clocks is 2, and the arrangement order of the adjacent scan clock lines is determined by a spacing of 2 or more. Claim 11 A display device according to claim 7, wherein when the number of scan signals output from each gate driving integrated circuit is 4, the arrangement order of adjacent scan clock lines is determined by a spacing of 4 or more. Claim 12 In claim 7, the arrangement order of the adjacent scan clock lines is a display device in which the larger value between the overlap interval between the adjacent scan clocks and the number of scan signals output from each gate driving integrated circuit is used as the spacing interval. Claim 13 In claim 7, the plurality of gate driving integrated circuits comprises: a line selector configured to charge an M node based on a front-end carry signal in response to the input of a line sensing signal and to discharge a Q node to the level of a third low-potential gate voltage in response to the input of a panel-on signal; a Q node control unit configured to charge the Q node to the level of a first high-potential gate voltage in response to the front-end carry signal and to discharge the Q node to the level of the third low-potential gate voltage in response to the input of a rear-end carry signal; a Q node stabilization unit configured to discharge the Q node and the QH node to the level of the third low-potential gate voltage in response to the voltage of the QB node; an inverter unit configured to change the voltage level of the QB node according to the second low-potential gate voltage and the voltage level of the Q node; a QB node stabilization unit configured to discharge the QB node to the level of the third low-potential gate voltage in response to the rear-end carry signal, a reset signal, and the charging voltage of the M node; and the voltage level of the Q node or the voltage of the QB node A display device comprising: a carry signal output unit configured to output a carry signal based on a voltage level of a carry clock or a level of a third low-potential gate voltage according to a level; and a scan signal output unit configured to output a plurality of scan signals based on a voltage level of a plurality of scan clocks or a level of a first low-potential gate voltage according to a voltage level of the Q node or a voltage level of the QB node.

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