Global Integrated Circuit Power Control

Abstract

In one embodiment, the system may include a plurality of component circuits. The plurality of component circuits may include rate control circuits that control power consumption in the component circuits based on indications of power assigned to the component circuits. In one embodiment, the rate control circuits may transmit power requests for the component circuits and a minimum request indicating a minimum amount of power capable of ensuring reliable operation.

Description

Background Technology

[0001] Technology field

[0002] The embodiments described herein relate to hardware-based mechanisms for power control of digital systems, more specifically, global power control.

[0003] Background Technology

[0004] As the complexity and performance of digital systems continue to increase, the complexity required to stably and reliably deliver power to the system's component circuits also increases. In modern systems, integrated circuits containing processors and other component circuits on a single semiconductor substrate or chip can draw hundreds of amperes of current at supply voltages ranging from ~1 to 2 volts. These integrated circuits (e.g., systems on a chip or SOC) also often have multiple independent voltage domains within the integrated circuit, which can simultaneously have different supply voltages and represent different loads (e.g., current drawn from a given load). Brief explanation of the drawing

[0005] For the following detailed description, please refer to the attached drawings, which are now briefly described. FIG. 1 is a block diagram of an embodiment of a system including power splitter circuits and rate control circuits for various component circuits of the system. FIG. 2 is a block diagram illustrating an embodiment of a component circuit having a local power control circuit, a rate control circuit, and a power divider circuit, and an embodiment of interfaces between them. FIG. 3 is a block diagram illustrating another embodiment of a component circuit having a local power control circuit, a rate control circuit, and a power divider circuit, and another embodiment of the interfaces between them. FIG. 4 is a block diagram of one embodiment of cascaded rate control circuits. FIG. 5 is a more detailed block diagram of one embodiment of a power divider circuit. FIG. 6 is a more detailed block diagram of one embodiment of a rate control circuit. FIG. 7 is a flowchart illustrating the operation of one embodiment of a power divider circuit. FIG. 8 is a flowchart illustrating the operation of one embodiment of a rate control circuit. FIG. 9 is a block diagram of one embodiment of SOC. FIG. 10 is a block diagram of one embodiment of a system including a plurality of SOCs. FIG. 11 is a flowchart illustrating one embodiment of the method. FIG. 12 is a flowchart illustrating another embodiment of the method. FIG. 13 is a block diagram of various embodiments of systems that can employ SOC(s). Fig. 14 is a computer-accessible medium. The embodiments described in this disclosure may take various modifications and alternative forms, but specific embodiments are illustrated in the drawings by way of example and will be described in detail herein. However, the drawings and the detailed description thereof are not intended to limit the embodiments to the specific forms disclosed, but on the contrary, they are intended to encompass all modifications, equivalents, and alternatives that fall within the spirit and scope of the appended claims. The headings used herein are for configuration purposes only and are not intended to be used to limit the scope of the description. Specific details for implementing the invention

[0006] In some cases, a multi-level power delivery network is provided. The first level voltage regulator(s) can supply a first amount of load current to the second level voltage regulators. The second level voltage regulators can deliver power to various independent power networks of the SOC. Various consumers (e.g., processors forming the central processing unit (CPU) of the SOC, graphics processing unit (GPU), various peripheral component circuits ("peripherals"), etc.) may be located in independent power domains. Local power estimation and power control within the power domains may be used to avoid overloading a given second level voltage regulator. However, providing a first level regulator capable of supplying the second level regulators at the same time during peak loads is not cost-effective because such loads are rare. Therefore, other power management mechanisms may be implemented to produce the first level voltage regulator.

[0007] In one embodiment, the system includes a power divider circuit configured to distribute a power budget for the system among a plurality of component circuits. The power divider circuit may be programmable with a power distribution policy and may distribute a power budget based on the policy. The power divider circuit may be configured to transmit respective indications of the allocated power to the component circuits. The component circuits may include rate control circuits that manage power consumption based on the indications of the allocated power. Although various component circuits may be included in different independent power domains, the total power consumption may be controlled through the power divider circuit. The power budget may be determined, for example, based on the ability of a top-level voltage controller to power the voltage controllers supplying power to the independent power domains, and may help protect the top-level voltage controller from overload.

[0008] In one embodiment, the component circuits may include power estimator circuits (e.g., digital power estimator (DPE) circuits). The DPE circuits may be configured to estimate the power consumed by each component circuit and to provide the power estimates to corresponding rate control circuits. The rate control circuits may be configured to transmit each power request to a power divider circuit based on the power estimates. Additionally, in one embodiment, the rate control circuits may be configured to transmit each floor request. Floor requests may represent the minimum power that ensures the correct operation of the component circuits. For example, the floor power may be sufficient to supply the maximum amount of power that a given component circuit can consume even when all power consumption controls of a given component circuit are active (or "engaged"). In one embodiment, the floor request may describe the leakage current of a given component circuit and the behavior that may occur in a given component circuit (e.g., the minimum forward advance that a given component circuit can make in the presence of reduced power consumption controls) even when reduced power consumption is enabled. In one embodiment, the rate control circuit of a given component circuit may have multiple levels of power reduction requests to control the power consumed by the given component circuit, and the lowest request may be based on the requested maximum reduction. Alternatively, the given component circuit may implement one or more power reduction mechanisms, and the floor may be based on the power that can be consumed when each power reduction mechanism is in use simultaneously. In some embodiments, it is possible for the component circuit to consume less than the floor request (e.g., when the work(s) performed by the component circuit require less activity than that provided by the minimum forward progression).The power divider circuit can ensure that each component circuit receives a power allocation equal to at least the minimum request and the minimum value of the power request, and can distribute the remaining power among the component circuits based on power requests and power policies.

[0009] Component circuits may include any hardware components that may be included in the system. A given component circuit may include a power control circuit that implements one or more power management mechanisms within the component circuit as a whole. That is, the component circuit may be a power entity managed as a unit by the power control circuit. For example, a central processing unit (CPU) processor cluster may be a component circuit. A CPU processor cluster may include one or more processors and an interface circuit for interfacing with the rest of the system (e.g., via a system communication fabric). A CPU processor cluster may additionally include one or more caches in a cache hierarchy shared by the processors (in addition to caches implemented by the processors). Alternatively, individual CPU processors may be component circuits. Other examples of component circuits may include graphics processing units (GPUs) or memory controllers. Peripheral component circuits (or more simply peripheral devices), such as display controllers, image signal processors, audio processors, video or audio encoder / decoder circuits, bridges for various types of external interconnects, and input / output devices, may also be examples of component circuits.

[0010] FIG. 1 is a block diagram of one embodiment of a system. In the embodiment of FIG. 1, the system includes a plurality of component circuits (12A to 12F) coupled to a power divider circuit (10). Each of the plurality of component circuits (12A to 12F) includes a respective rate control circuit (20A to 20F). Additionally, in the illustrated embodiment, the plurality of component circuits include a respective digital power estimator (DPE) / power control (PC) circuit (14A to 14F) coupled to each rate control circuit (20A to 20F). The power divider circuit (10) includes a plurality of power policy registers (18A to 18N). The system may further include a die-to-die (D2D) interface circuit (24) coupled to the power divider circuit (10).

[0011] A given component circuit among a plurality of component circuits (12A to 12F) is included in one of a plurality of independent power domains separated by the dotted lines (16) shown in FIG. 1. A given component circuit (12A to 12F) may be in one power domain, and more than one component circuit (12A to 12F) may be in a given power domain. In the illustrated embodiment, merely as an example, component circuits (12A and 12B) are in a power domain, component circuit (12C) is in another power domain, and component circuits (12D to 12F) are in their respective power domains. A power divider circuit (10) is also in a power domain that may be shared with or separated from one or more component circuits (12A to 12F).

[0012] Power domains can be independent if they are controlled separately from other power domains. For example, an independent power domain may have dedicated voltage inputs to the system, which can be controlled, for instance, by a separate voltage controller. Therefore, power management within a power domain may be sufficient to protect the stability of the voltage controller supplying power to that domain. However, since system-wide power management can be used to manage power across power domains, it can protect higher-level voltage controllers in the system.

[0013] As previously mentioned, the power distribution circuit (10) may be configured to allocate power to a plurality of component circuits (12A to 12F) from a power budget for the system. The power budget may be based on the ability of a voltage controller to supply power to the system as a whole (e.g., a top-level voltage controller that supplies to voltage controllers and, in turn, to various power domains). For example, available power (e.g., the product of the voltage nominally provided by the top-level voltage controller and the maximum current that the top-level voltage controller can reliably supply) may be represented in a plurality of credits, wherein a given credit represents a specific amount of power. The power distribution circuit (10) may be configured to provide a number of credits to each of the plurality of component circuits (12A to 12F) to represent the amount of power allocated to the corresponding component circuit. By measuring credits in terms of power (e.g., watts), the power divider circuit (10) can provide indications of an allocated amount in a common format that translates across different power domains capable of operating at different voltages at a given point in time. The power divider circuit (10) can be configured to transmit each indication of the allocated power to each rate control circuit (20A to 20F). Each rate control circuit (20A to 20F) can be configured to manage the power consumption of the corresponding component circuits based on each indication of the allocated power provided to each rate control circuit (20A to 20F).

[0014] More specifically, the component circuits (12A to 12F) may each include power control circuits (e.g., PCs shown in FIG. 1, part of reference numerals 14A to 14F). Generally, the power control circuit may implement one or more power management mechanisms, each of which is designed to reduce the power consumption of the component circuits (12A to 12F) when the mechanism is in use compared to when the mechanism is not in use. For example, if the component circuits (12A to 12F) include multiple pipelines, the power management mechanism may reduce the number of pipelines in active use so that operations performed by the component circuits (12A to 12F) are performed by a reduced number of pipelines, and power is saved through the deactivation of one or more pipelines. Other power management mechanisms may include reducing the issue rate of operations to the pipelines and introducing a "bubble" into the pipelines where deactivation occurs. Another power management mechanism may include periodic stalling of one or more pipelines or temporarily reducing the clock frequency of the clocks supplied to the pipelines. Additionally, clock manipulation techniques such as clock dithering, clock dividers, and clock throttling may be used.

[0015] In one embodiment, a given component circuit, such as component circuit (12A), may have sub-component circuits (e.g., sub-component circuits (22A to 22M) of FIG. 1, more simply "sub-components"). Since the sub-components (22A to 22M) may be relatively independent, the power control circuit (14A) may disable one or more of the sub-components without interfering with the operation of the remaining components. For example, a CPU processor cluster may have multiple CPU processors, and one or more CPU processors may be disabled (e.g., stalling, clock gating, or even power gating) without interfering with other CPU processors continuing to execute instructions. In a GPU, there may be multiple symmetric units, such as shaders, rasterizers, etc., and the symmetric units may be sub-components. The pipelines of the component circuit may be sub-components. In such component circuits, power control circuits (14A to 14F) may be configured to disable or reduce the performance of a subset of subcomponents while allowing other subcomponents to operate without interference.

[0016] In one embodiment, the power divider circuit (10) may be programmable with a power distribution policy of registers (18A to 18N). In this embodiment, there may be a top-level policy (register (18A)) that distributes a power budget among groups of component circuits (12A to 12F). The component circuits (12A to 12F) may be grouped in any desired manner. For example, the component circuits (12A to 12F) may be grouped by type, and the top-level policy may allocate power by type (e.g., various percentages of the power budget for various types). The top-level policy may change from time to time, such as when a change in the system's workload characteristics occurs. Examples of types may include CPU clusters, GPUs, and peripherals. Various subsets of peripherals may be types of components such as audio peripherals, video peripherals, networking peripherals, storage peripherals, etc. In another embodiment, the component circuits (12A to 12F) may be grouped by power domain. Any grouping of the component circuits (12A to 12F) may be used.

[0017] Within each grouping, a second level of power distribution can be specified in the registers (18B to 18N). For example, the registers (18B to 18N) may have a policy for each group. Thus, components of the same type may be allocated power based on a corresponding policy and top-level power allocation from one of the registers (18B to 18N).

[0018] In one embodiment, the system shown in FIG. 1 may be implemented on a single semiconductor substrate, or "chip." In one embodiment, the system may be part of a larger system that includes additional chips similar to the chip shown in FIG. 1. The D2D interface circuit (24) may be configured to communicate between the chips. In one embodiment, one or more of these chips may share a top-level voltage controller with the system of FIG. 1. The power divider circuit (10) may share power credits not used by the component circuits (12A to 12F) with other power divider circuits on other chips and / or receive power credits from other power divider circuits for consumption in the component circuits (12A to 12F).

[0019] Note that while the example of FIG. 1 includes a specific number of component circuits (12A to 12F), other embodiments may implement any number of component circuits (12A to 12F) as desired.

[0020] Now, referring to FIG. 2, a block diagram of one embodiment of a component circuit (12A) having a rate control circuit (20A) and a DPE / PC circuit (12A) coupled to a power divider circuit (10) is shown, and one embodiment of the interfaces between them is shown. Other component circuits (12B to 12F) may be similar.

[0021] The DPE / PC circuit (14A) may be configured to use power management mechanisms based on one or more inputs to the PC portion of the circuit (14A) to limit power consumption within the component circuit (12A). For example, the rate control circuit (20A) of FIG. 2 may provide reduce0 and reduce1 inputs. Each input may request a different amount of reduced power consumption (e.g., one amount of reduced power consumption may be greater than another). In one embodiment, the DPE portion of the DPE / PC circuit (14A) may provide one or more local limits based on inputs to the PC portion and a power budget for the power domain, for example, based on estimated power consumption to manage power consumption of the component circuit (12A). In another embodiment, the DPE portion may provide power estimates and the PC portion may receive inputs only from the rate control circuit (20A). The rate control circuit (20A) can request a first level of reduced power consumption using a first input (e.g., decrease 0) among one or more inputs and a second level of reduced power consumption using a second input (e.g., decrease 1) among one or more inputs, wherein the second level specifies a greater reduction than the first level.

[0022] The DPE / PC circuit (14A) may be configured to report a DPE power estimate to the rate control circuit (20A). The rate control circuit (20A) may receive a DPE power estimate (e.g., current power consumption estimate) as well as an indication of the allocated power from the power circuit (10) (assigned in FIG. 2), and the rate control circuit (20A) may be configured to manage the power of the component circuit (12A) based on the DPE power estimate and the allocated power. The DPE estimate and the allocated power indication may be measured in terms of credits. Based on the estimate, the allocated power, and any remaining allocated power from previous unconsumed allocations, the rate control circuit (20A) may generate decrement 0 and decrement 1 inputs to the power control circuit. For example, allocated power credits may be added to the remaining credits, and the DPE estimate may be subtracted from the credits to generate the remaining amount of allocated power. If the remaining amount of allocated power falls below a first threshold (which may be programmable in the rate control circuit (20A)), the rate control circuit (20A) may assert a decrease 0 input, and the power control circuit (14A) may be using one or more power management mechanisms. The mechanisms in use may reduce power consumption and, possibly, degrade performance. However, if additional power management mechanisms are in use or the power management mechanisms in use are applied more strongly, the performance loss may be smaller than that performance loss. If the remaining amount of allocated power falls below a second threshold lower than the first threshold, the rate control circuit (20A) may assert a decrease 1 input, and the power control circuit (14A) may be using one or more additional power management mechanisms and / or applying the mechanisms already in use more strongly, thereby further reducing power consumption and further degrading performance.In the illustrated embodiment, two inputs are shown and two levels of reduced power consumption are implemented, but in other embodiments, more than two levels may be used. The number of power reduction control signals may be increased and / or the encoding of the signals may be used to specify different levels of reduced power consumption. When the highest level of reduced power consumption is requested (e.g., via an assertion or reduction 1 in this embodiment), the power control circuit (14A) may be using the maximum level of reduction supported by each power management mechanism it implements and the mechanism.

[0023] In addition to requesting reduced power consumption, the rate control circuit (20A) may be configured to report that reduced power consumption is in use (e.g., through a "reduced" output to the power divider circuit (10)). In one embodiment, the power divider circuit (10) may be configured to record claims of reduced outputs from various component circuits (12A to 12F) for potential analysis by software to determine whether the power distribution policy needs to be modified (e.g., because a given component circuit operates more frequently under reduced power consumption than desired). In another embodiment, the power divider circuit (10) may be configured to automatically adjust the power distribution policy in hardware based on the frequency of reduced signal claims.

[0024] In one embodiment, the rate control circuit (20A) may be configured to generate a power request (the "Request" in FIG. 2) and a floor request (the "Floor" in FIG. 2) and transmit them to the power distributor (10). The power request may be based, for example, on previously allocated and consumed power as well as an estimate of DPE power from the DPE / PC circuit (14A). The DPE / PC circuit (14A) may also provide a floor indicating a minimum amount of power to ensure the correct operation of the corresponding component circuit (12A). The rate control circuit (20A) may transmit the floor request provided by the DPE / PC circuit (14A) as a floor request to the power distributor circuit (10). The power distribution circuit (10) can be configured to ensure that a plurality of component circuits (12A to 12F) receive an allocation of power equal to at least the minimum value of each minimum request and each power request, and can be configured to allocate the remaining power budget based on the power distribution policy and each power request.

[0025] The minimum request may depend on various factors such as supply voltage and temperature for the component circuit (12A). Temperature, for example, may affect the leakage current of the component circuit (12A). In one embodiment, the minimum request may be based on the maximum amount of reduced power consumption that the DPE / PC circuit (14A) can cause. For example, in the embodiment of FIG. 2, the minimum request may be based on the power consumed when the reduced1 input is asserted. Alternatively, the minimum request may be based on the power that can be consumed when each of the power management mechanisms implemented by the DPE / PC circuit (14A) / component circuit (12A) is in full use. The activity level of the component circuit (12A) may be lower than the total amount of potential activity that can occur when each of the power management mechanisms is in full use, in which case the minimum request may be higher than strictly necessary. However, providing the minimum request can ensure that sufficient power is provided when the full activity level is being performed. In one embodiment, the minimum request may be further based on the leakage power consumed by the component circuit (12A) (e.g., the value obtained by multiplying the supply voltage for the component circuit (12A) by the leakage current experienced by the inactive transistors while in use by the component circuit (12A)).

[0026] In one embodiment, if the amount of activity actually occurring in the component circuit (12A) is less than the total possible amount of activity when the reduction1 input is asserted, the power request may be less than the minimum request. In one embodiment, if the power request is less than the minimum request, the power distributor circuit (10) may be configured to assign the power request instead of the minimum request. In another embodiment, as protection against the power request being too low (e.g., if the power estimate from the DPE portion of the circuit (14A) is inaccurate), the minimum request may still be assigned even if it is higher than the power request.

[0027] In one embodiment, the minimum request may change relatively infrequently. For example, the minimum request may change with temperature changes, which may occur relatively slowly compared to the frequency at which power is requested and allocated. The minimum request may change when a change in power state occurs for the component circuit (12A), which may increase or decrease the supply voltage and clock frequency of the component circuit (12A). Because the minimum request changes infrequently, the physical interconnection (e.g., wiring) between each rate control circuit (20A to 20N) and the power divider circuit (10) may be reduced by sharing the same physical interconnection to transmit the power request and the minimum request. That is, the physical interconnection may include a shared bus for transmitting the power request and the minimum request. In this case, each rate control circuit (20A to 20F) may be configured to select one of the respective power request and the respective minimum request to transmit on the shared bus at a given time.

[0028] FIG. 3 is a block diagram illustrating an example of a shared physical interconnection for transmitting power requests and minimum requests to a rate control circuit (20A) / component circuit (12A). Other rate control circuits (20B to 20F) / component circuits (12B to 12F) may be similar. In the illustrated embodiment, the DPE / PC circuit (14A) may provide DPE power estimates and minimum requests, and may receive reduction 0 and reduction 1 inputs from the rate control circuit (20A), similar to what was discussed above in relation to FIG. 2. The rate control circuit (20A) may receive an indication of the allocated power and report a power reduction through a reduced output, similar to what was discussed above in relation to FIG. 2. The component circuit (12A) may include a multiplexer (mux) circuit (30) to select between a minimum request and a power request from the rate control circuit (20A), and may transmit the selected request on the shared request / minimum bus (floor bus) to the power distributor circuit (10). The rate control circuit (20A) may generate a mux selection control for the mux (30), which may be provided as an additional bit / signal on the request / minimum bus (or next to the request / minimum bus) to identify whether a power request or a minimum request has been transmitted.

[0029] The rate control circuit (20A) may employ any mechanism for selecting between a power request and a minimum request for transmission to the power distributor circuit (10). For example, the rate control circuit (20A) may be configured to select the minimum request based on a change in the minimum request since the most recent transmission of the minimum request. The rate control circuit (20A) may be configured to select the power request based on a change in the power request since the most recent transmission of the power request. The rate control circuit (20A) may be configured to select the least recently transmitted of the minimum request and the power request based on the fact that there is no change in the power request since the most recent transmission of the power request and no change in the minimum request since the most recent transmission of the minimum request. The power distributor circuit (10) may be configured to use a previously received request as the latest request for which the power request and the minimum request were not selected (for example, based on a selection indication provided by the rate control circuit (20A) indicating which of the minimum request and the power request has been selected).

[0030] In one embodiment, the system may support cascading of two or more component circuits (12A to 12F) that share the same power and minimum requests. FIG. 4 is an example illustrating one embodiment in which component circuits (12A and 12B) are cascaded. An embodiment similar to FIG. 3 having a shared bus for requests and minimums may support cascading in a similar manner. Since the component circuit (12A) may be a primary circuit, it may have an interface to the power divider circuit (10) (e.g., minimum request and power request, and allocated power indication). The rate control circuit (20A) may also be configured to control the decrease0 and decrease1 outputs to the DPE / PC circuit (14A), which may also be provided to the DPE / PC circuit (14B) of the component circuit (12B). The DPE / PC circuit (14B) can provide a DPE power estimate to the rate control circuit (20B), which can then transmit the DPE power estimate to the rate control circuit (20A). Alternatively, the DPE / PC circuit (14B) can provide the DPE power estimate directly to the rate control circuit (20A). The rate control circuit (20A) can generate a power request based on DPE power estimates from both the DPE / PC circuit (14A) and the DPE / PC circuit (14B). In one embodiment, since the component circuits (12A and 12B) may be instances of the same basic design, the minimum request generated by the rate control circuit (20A) may be twice the minimum request from the DPE / PC (14A). Alternatively, the DPE / PC circuit (14B) can provide the minimum request to the rate control circuit (20A) or directly to the rate control circuit (20A) through the rate control circuit (20B).Cascading the component circuits (12A and 12B) can reduce the number of interfaces to the power divider circuit (10) and reduce the complexity of wiring physical interfaces to potentially different locations on the semiconductor die implementing the system.

[0031] FIG. 5 is a block diagram of one embodiment of a power divider circuit (10) illustrated in more detail. In the illustrated embodiment, the power divider circuit (10) may include a budget generation circuit (40), a top-level distribution control circuit (42), a second-level distribution control circuit (44), a residual distribution circuit (46), a transmission circuit (48), a telemetry accumulation circuit (50), and a D2D sharing control circuit (52). The budget generation circuit (40) is coupled to the D2D sharing control circuit (52), the top-level distribution control circuit (42), and one or more power state inputs. The top-level distribution control circuit is coupled to a register (18A) and a second-level distribution control circuit (44), which is coupled to power requests and minimum requests from component circuits (12A to 12F) (and more specifically to rate control circuits (20A to 20F)), registers (18B to 18N), and a residual distribution circuit (46). The residual distribution circuit (46) is coupled to the transmission circuit (48), which is coupled to the components (12A to 12F) (and more specifically to the rate control circuits (20A to 20F)) to provide allocated power indications. The D2D shared control circuit (52) is coupled to the D2D interface circuit (24), and the telemetry accumulation circuit (50) is coupled to the reduced signal from the components (12A to 12F) (and more specifically to the rate control circuits (20A to 20F)).

[0032] Power status inputs can provide information indicating the amount of power available from various power sources of the system. For example, the power manager circuit may be one of the component circuits (12A to 12F) and may indicate the amount of power available based on inputs from voltage regulators and / or other parts of an external power management unit controlling voltage regulators, as well as various power states managed by the power manager. The inputs may provide information regarding the load of the regulators when any low voltage events are detected due to overload of the voltage regulators, etc. Based on these inputs and programmable configuration data, the budget generation circuit may be configured to generate an indication of the amount of power available, for example, as the number of power credits, each of which represents a specific amount of power (e.g., watts). The budget generation circuit (40) may provide the available budget to the top-level distribution control circuit (42).

[0033] The top distribution control circuit (42) may be configured to distribute power budgets among various groups of component circuits, for example, by component circuit type. The top distribution policy from the register (18A) controls the distribution to specify, for example, percentages of available power allocated to CPU processors, GPU processors, certain peripherals, and the rest of the system. While significant flexibility may be available to specify the top distribution policy, at least the minimum amount of power for each component circuit (12A to 12F) must be available through the policy to ensure correct operation. In one embodiment, the power distributor circuit (10) may be configured to ignore the policy to provide the minimum amount of power. That is, if a given group of component circuits is allocated too little power according to the policy to provide the minimum amount of power to the members of the group, the power distributor circuit (10) may ensure that the component circuits receive the minimum (or the requested amount if it is less than the minimum).

[0034] The second level control circuit (44) can receive top level power allocations from the top distribution control circuit (42) and can allocate each top level allocation among each group of component circuits based on the component policies of the registers (18B to 18N) and power requests and minimum requests from each component circuit.

[0035] Since the second level power distribution is determined at least partially based on the power requests of various component circuits, it is possible for there to be a remainder of unallocated power from one or more top-level groups. The unallocated power can be distributed by the residual distribution circuit (46). In one embodiment, if a group has remaining power credits and another group cannot meet all power requests due to a lack of credits, the remaining power credits can be distributed as additional credits to the component circuits of the group that lacks power credits. Alternatively, the remaining credits can be distributed and transferred as additional credits to various unrequested component circuits. In another embodiment, the remaining credits can be distributed to the D2D sharing control circuit (52) for sharing with other dies. Combinations of the above distribution strategies can also be implemented (e.g., distributing a portion of the remainder as unrequested credits and another portion of the remainder as shared credits to other dies via the D2D sharing control circuit (52).

[0036] Allocated power credits may be provided to a transmission circuit (48) which may be configured to transmit the allocated power credits to component circuits (12A to 12F). In one embodiment, the transmission circuit (48) may implement delay matching so that a component circuit physically closer to the power divider circuit (10) receives the power allocation approximately simultaneously with component circuits (12A to 12F) physically farther from the power divider circuit (10). For example, each power allocation may be delayed by the difference between the actual transport delay for the corresponding component circuits (12A to 12F) and the transport delay for the component circuits (12A to 12F) furthest away (e.g., in the granularity of the clock cycle).

[0037] The telemetry accumulating circuit (50) may be configured to accumulate reduced indications from each component circuit (12A to 12F) for comparison and other analysis to potentially modify the distribution policies of the registers (18A to 18N), for example. The telemetry accumulating circuit (50) may include counters for counting reduced signal assertions, and the counters may be software-readable.

[0038] The D2D sharing control circuit (52) can be coupled to the D2D interface (24). If the power distributor circuit (10) determines that there are unused credits that can be shared with another die, the D2D sharing control circuit (52) can be configured to transfer the credits to the D2D interface circuit (24). Additionally, if another die shares credits with the current die, the D2D sharing control circuit (52) can be configured to receive the shared credits from the D2D interface circuit (24) and provide them to the budget generation circuit (40) to be added to the power budget.

[0039] FIG. 6 is a block diagram of one embodiment of a rate control circuit (20A) in more detail. Other rate control circuits (20B to 20F) may be similar. In the illustrated embodiment, the rate control circuit (20A) includes a DPE processing circuit (60), a reduction control circuit (62), and a proportional / integral (PI) control circuit (64). The DPE processing circuit (60) is coupled to the reduction control circuit (62) and the PI control circuit (64).

[0040] The DPE processing circuit (60) may be configured to receive DPE power estimates from the DPE / PC circuit (20A) and optionally receive DPE power estimates from other DPE / PC circuits in a cascaded configuration (dotted line in FIG. 6). The DPE / PC circuit (20A) may be configured to add the received DPE power estimates (and DPE power estimates from other component circuits are 0 if not used) (adder circuit (66)) and generate DPE power estimates served by the rate control circuit (20A). For example, if the component circuit (12A) is cascaded to other component circuits (12B to 12F) which are primary circuits, the DPE power estimates may be output for possible use by other rate control circuits. The DPE processing circuit (60) may also receive an allocated power indication from the power divider circuit (10) and may be configured to subtract the DPE power estimate output by the adder (64) from the allocated power (adder circuit (68)). The difference may be a measure of the remaining power credits along with the DPE power from the adder (66) and may be provided to the PI control circuit (64) and the reduction control circuit (62). In one embodiment, the remaining power credits may be added to a set of power credits accumulated from previous allocations, and the result may be the total number of power credits available for use by the corresponding component circuit. The accumulated credits may protect against the depletion of power credits when a sudden increase in the workload of the corresponding component circuit occurs, and may potentially allocate more credits to support the increased workload by causing a round-trip delay from the rate control circuit to the power divider. If there are not enough available credits for the allocation of the increased workload, reduced power consumption can subsequently be implemented by the reduction control circuit (62).In embodiments where credits are accumulated, the accumulated credits may also be provided to the PI control circuit (64) in place of the remaining power credits.

[0041] The reduction control circuit (62) can provide the remaining power credit to comparator circuits (70 and 72) capable of comparing the remaining power credit to thresholds 1 and 0, respectively. When the remaining power credit falls below threshold 0 (comparator (72)), the reduction control circuit can be configured to assert reduction 0. When the remaining power credit falls below threshold 1 (comparator (70)), the reduction control circuit can be configured to assert reduction 1. In one embodiment, the reduction control circuit (62) can be configured to apply hysteresis to the comparator results so that the reduction signals are not rapidly consecutively asserted / deasserted (e.g., to smooth the reduction results). The reduction control circuit (62) can further assert a reduced output to the power divider circuit (10) when one or both of the reduction 0 and reduction 1 signals are asserted. The minimum request can also be received by the rate control circuit (20A) according to the embodiment and transmitted to the multiplexer (30) or power divider circuit (10).

[0042] The PI control circuit (64) may be configured to operate on the DPE power from the adder circuit (66) and / or the difference from the adder (68) (or accumulated credits as mentioned above) to generate a power request from the rate control circuit (20A). In the example, a proportional / integral control function may be used. Proportional control may be applied to the DPE power estimate, and integral control may be applied to the difference provided from the DPE processing circuit (60), or vice versa. The result of the control operation may be a power request. Although PI control is provided in this embodiment, other embodiments may implement other control operands and combinations thereof including one or more of proportional, integral, and / or derivative control as well as other control options.

[0043] Note that in one embodiment, the DPE processing circuit (60) and the reduction control circuit (62) may operate in the clock domain of the component circuit (12A), and the PI control circuit (64) may operate in the clock domain of the power divider circuit (10). For example, in one embodiment, the power divider circuit (10) may operate at a generally slower clock than the component circuits (12A to 12F) (e.g., tens of megahertz (MHz) for the power divider circuit (10) versus gigahertz (GHz) for the component circuits (12A to 12F). Thus, there may be an intersecting clock domain within the rate control circuit (20A) (e.g., at the boundary between the PI control circuit (64) and the DPE processing circuit (60) / reduction control circuit (62). Accordingly, power allocations by the power divider circuit (10) may be power allocated during one clock cycle of the power divider clock, and power requests and minimum requests may be for the next clock cycle.

[0044] FIG. 7 is a flowchart illustrating a simplified view of the operation of one embodiment of a power divider circuit (10). The blocks are shown in a specific order for ease of understanding, but other orders may be used. The blocks may be executed in parallel by combination logic within the power divider circuit (10). The blocks, combinations of blocks, and / or the flowchart as a whole may be pipelined over multiple clock cycles. The power divider circuit (10) may be configured to implement the operation illustrated in FIG. 7.

[0045] The power divider circuit (10) can be configured to determine the power budget to be allocated (block 80). For example, the power budget can be based on various power state inputs, as discussed above. The power budget can be based on various programmable values ​​(e.g., an initial budget) that can be modified based on the power state inputs. For example, the power state inputs may indicate that a power reduction is requested by external hardware (for the integrated circuit), such as a power management unit, even though the on-system hardware has not yet detected a problem. In this case, the power divider circuit (10) can reduce the budget. In one embodiment, the first level voltage regulator may operate with fewer than the maximum number of active phases (e.g., single-phase mode), and the power divider circuit (10) may reduce the budget based on the load current that the reduced number of phases can support (e.g., the reduced budget may be provided to correspond to the reduced number of phases, and the power divider circuit may switch to the reduced budget based on an input indicating that the reduced phase mode is active). In one embodiment, the initial budget may be programmed to different values ​​by controlling the software during use (e.g., within a predefined range known to be tested and safe, the predefined range may be enforced by the power divider circuit (10) hardware). Software control may modify the budget to reduce or eliminate the occurrence of power state inputs that cause budget reduction, which can improve overall efficiency.

[0046] The power distributor circuit (10) can allocate credits to satisfy the lowest requests (Block 82). As previously mentioned, in some embodiments, the lowest request may be ignored by lower power requests and instead lower power request credits may be allocated. The power budget credits remaining after the lowest allocation may be allocated based on the highest level distribution priority (Block 84), and then allocated to various component circuits based on the second level policy and power requests (Block 86).

[0047] Note that the credit allocation described above is somewhat simplified and may be implemented as described or in different ways. For example, credits may be allocated according to the top-level distribution and then allocated to minimum and power requests at the second level. If there are insufficient credits to allocate at the second level for all minimum requests, additional credits may be added to satisfy the minimum requests (e.g., from a reserve pool, or borrowed from future credits up to a predetermined maximum amount). Any mechanism may be used.

[0048] If there are no remaining credits from the allocation indicated by blocks (80, 82, 84, and 86) (decision block 88, "No" interval), the allocation may be completed for this iteration. If there are remaining credits (decision block 88, "Yes" interval), the power divider circuit (10) may be configured to attempt to distribute the remaining credits. If D2D sharing is enabled (e.g., the system is a multi-die system and in some cases D2D sharing can be optionally enabled via a programmable configuration) (decision block 90, "Yes" interval), the power divider circuit (10) may push credits to another die (block 92). In some cases, less than the total number of remaining credits may be shared. For example, there may be a programmable limit on the number of credits that can be shared, or a certain percentage of the remaining credits may be shared. Any mechanism may be used to determine the number of credits to be shared.

[0049] If present, the remaining credits may be accumulated along with any credits shared from other dies for use in subsequent allocations (Block 94). The number of remaining credits that can be accumulated may be limited (e.g., a programmable limit). Any credits exceeding the limit will then be "outflowed" (e.g., lost due to no allocation or accumulation of credits). When credits are outflowed (Decision Block 96, "Yes" section), the power divider circuit (10) may potentially be useful and therefore push the credits to the unrequested rate control circuits (20A through 20F) (Block 98). If the rate control circuits (20A through 20F) are unable to allocate the credits, the credits may be outflowed.

[0050] FIG. 8 is a flowchart illustrating a simplified view of the operation of one embodiment of a given rate control circuit (20A to 20F). The blocks are shown in a specific order for ease of understanding, but other orders may be used. The blocks may be executed in parallel by combination logic within the given rate control circuit (20A to 20F). The blocks, combinations of blocks, and / or the flowchart as a whole may be pipelined over multiple clock cycles. The given rate control circuit (20A to 20F) may be configured to implement the operation illustrated in FIG. 8. In one embodiment, each rate control circuit (20A to 20F) may implement the operation illustrated in FIG. 8 in parallel based on each allocated power credit from the power divider circuit (10). Accordingly, the description of FIG. 8 will simply refer to "rate control circuit".

[0051] The rate control circuit may be configured to subtract the DPE power estimate (including any cascade-type component circuits, where applicable) from the allocated power indication received from the power divider circuit (10) (Block 100). The rate control circuit may be configured to compare the result with thresholds and to generate decrement 0, decrement 1, and decrement signals (Block 102). The rate control circuit may be configured to apply PI control to the DPE power estimate and the remainder to generate a power request (Block 104). If the flow request has changed since the most recent time the lowest request was sent to the power divider circuit (Decision Block 106, "Yes" interval), the rate control circuit may be configured to select the lowest request and send the lowest request to the power divider circuit (Block 108). If the lowest request has not changed since the most recent time the lowest request was transmitted (decision block 106, "No" interval) and the power request has changed since the most recent time the power request was transmitted (decision block 110, "Yes" interval), the rate control circuit may be configured to select the power request and transmit the power request to the power distributor circuit (10) (block 112). If neither has changed (decision blocks 106 and 110, "No" interval), the rate control circuit may select the most recently transmitted one of the lowest request and the power request and transmit the selected request to the power distributor circuit (10) (block 114). The operations exemplified by blocks (106, 108, 110, 112, and 114) may be implemented for a shared power request / lowest request interface. Embodiments having separate buses for power requests and minimum requests can eliminate the operation of blocks (106, 108, 110, 112, and 114).

[0052] FIG. 9 is a block diagram of one embodiment of a system comprising a system-on-chip (SOC) (120) coupled to a memory (122) and a power management unit (PMU) (124). The PMU (124) may be configured to supply power to other components that may be included in the system, such as the SOC (120) and the memory (122). For example, the PMU (124) may be configured to generate one or more supply voltages to supply power to the SOC (120) and may be further configured to generate supply voltages for other components of the system not shown in FIG. 9. More specifically, the PMU (124) may include one or more first-level voltage controllers that supply second-level voltage controllers that supply various independent voltage domains of the SOC (120).

[0053] As the name implies, the components of the SOC (120) can be integrated on a single semiconductor substrate as an integrated circuit "chip." In the illustrated embodiment, the components of the SOC (120) include at least one processor cluster (148), a plurality of graphics processing units (GPUs) (136), one or more peripheral components such as peripheral components (138) (more simply "peripherals"), a memory controller (142), a power management circuit (PMGR) (144), and a communication fabric (147). The components (148, 136, 138, 142, and 144) can all be coupled to the communication fabric (147). The memory controller (142) can be coupled to the memory (122) in use. In some embodiments, there may be more than one memory controller coupled to the corresponding memory. In these embodiments, the memory address space can be mapped across the memory controllers in any desired manner. In the illustrated embodiment, the processor cluster (148) may include a plurality of processors (P) (150). The processors (150) may form the central processing units (CPU(s)) of the SOC (120). The processor cluster (148) may further include one or more coprocessors (e.g., the coprocessor (152) of FIG. 9) that can be optimized for a subset of the processor instruction set and used by the processors (150) to execute the instructions of the subset. For example, the coprocessor (152) may be a matrix engine optimized to perform vector and matrix operations.

[0054] In these embodiments, the memory controller(s) (142), communication fabric (147), peripheral devices (138), GPU (136), and processor cluster (148) may all be instances of component circuits (12A through 12F). Accordingly, as illustrated, the memory controller(s) (142), communication fabric (147), peripheral devices (138), GPUs (136), and processor cluster (148) each include instances of the DPE / PC circuit (14) and the rate control circuit (20). Any subset of the memory controller(s) (142), communication fabric (147), peripheral devices (138), GPUs (136), and processor cluster (148) may be component circuits in other embodiments. The PMGR (144) may include a power divider circuit (10), and the D2D interface circuit (24) may be part of the communication fabric (147).

[0055] The various component circuits of FIG. 9 may be different types of component circuits, and thus the power management mechanisms implemented may vary. For example, the DPE / PC (14) of the processor cluster (148) may employ mechanisms such as disabling / disabling one or more processors (150) or disabling one or more pipelines of the processor (150). Instruction issue rates may be reduced by inserting bubbles into the pipelines so that the corresponding circuit does not actively evaluate each cycle. Any set of one or more power management mechanisms may be used. Similarly, GPUs (136) may reduce the number of active pipelines, limit / restrict instruction issue rates, or implement any other power management mechanisms such as clock manipulation (clock dithering, clock distribution, etc.).

[0056] The PMGR (144) may be configured to control supply voltage magnitudes requested from an external PMU (124). For various independent power domains, there may be multiple supply voltages generated by the PMU (124) for the SOC (120). The PMGR (144) may be under direct software control and / or may be configured to monitor the SOC (120) and determine when various components are powered on or off (e.g., software may directly request the power-on and / or power-off of components). Various power states within a component (e.g., power state of the processor (150)), as well as the sequence of power state changes, different requested voltages and frequencies, etc., may also be controlled through the PMGR (144).

[0057] As mentioned above, the processor cluster (148) may include one or more processors (150) capable of acting as the CPU of the SOC (120). The CPU of the system includes processor(s) that execute the main control software of the system, such as an operating system. Generally, the software executed by the CPU during use can control other components of the system to realize the desired functions of the system. Processors can also execute other software, such as application programs. Application programs can provide user functions and may rely on the operating system for low-level device control, scheduling, memory management, etc. Therefore, processors may also be referred to as application processors.

[0058] Generally, a processor may include any circuitry and / or microcode configured to execute instructions defined in an instruction set architecture implemented by the processor. Processors may include processor cores implemented on an integrated circuit together with other components as a system-on-chip (SOC (120)) or other levels of integration. Processors may further include individual microprocessors, processor cores and / or microprocessors integrated in a multi-chip module implementation, processors implemented as multiple integrated circuits, etc.

[0059] The memory controller (142) may generally include circuitry for receiving memory operations from other components of the SOC (120) and accessing the memory (122) to complete the memory operations. The memory controller (142) may be configured to access any type of memory (122). For example, the memory (122) may be dynamic RAM (DRAM), such as static random-access memory (SRAM), synchronous DRAM (SDRAM), and double data rate (DDR, DDR2, DDR3, DDR4, etc.) DRAM. Low-power / mobile versions of DDR DRAM may be supported (e.g., LPDDR, mDDR, etc.). The memory controller (142) may include queues for memory operations to align (and potentially reorder) the operations and present the operations to the memory (122). The memory controller (142) may additionally include data buffers for storing write data waiting to be written to memory and read data waiting to be returned to the source of the memory operation. In some embodiments, the memory controller (142) may include a memory cache for storing recently accessed memory data. For example, in SOC implementations, the memory cache may reduce the power consumption of the SOC by avoiding data re-access from memory (122) when it is expected to be accessed again soon. In some cases, the memory cache may be referred to as a system cache, unlike private caches such as L2 caches or processor caches that serve only specific components. Additionally, in some embodiments, the system cache does not need to be located within the memory controller (142).

[0060] Peripheral devices (138) may be any set of additional hardware functions for the SOC (120). For example, peripheral devices (138) may include video peripheral devices such as image signal processors configured to process image capture data from a camera or other image sensor, video encoders / decoders, scalers, rotators, blenders, display controllers, etc. Peripheral devices may include audio peripheral devices such as microphones, speakers, interfaces for microphones and speakers, audio processors, digital signal processors, mixers, etc. Peripheral devices may include interface controllers for various interfaces outside the SOC (120), such as Universal Serial Bus (USB), peripheral component interconnects (PCI) including PCI Express (PCIe), serial and parallel ports, etc. Interconnections to external devices extending outside the SOC (120) are illustrated by dashed lines in FIG. 9. Peripheral devices may include networking peripherals such as media access controllers (MACs). Any set of hardware may be included.

[0061] The communication fabric (147) may be any communication interconnection and protocol for communicating between components of the SOC (120). The communication fabric (147) may be bus-based, including shared bus configurations, crossbar configurations, and hierarchical buses having bridges. The communication fabric (147) may also be packet-based and may be hierarchical with bridges, crossbars, point-to-point, or other interconnections.

[0062] Note that the number of components of the SOC (120) (and the number of sub-components, such as the processors (150) of each processor cluster (148) as illustrated in FIG. 9) may vary from embodiment to embodiment. Additionally, the number of processors (150) of one processor cluster (148) may differ from the number of processors (150) of other processor clusters (148) when multiple processor clusters are included. There may be more or fewer of each component / sub-component than the number illustrated in FIG. 9.

[0063] According to the above, one embodiment of the integrated circuit may include a power manager circuit comprising a power divider circuit; a plurality of component circuits; and one or more processor clusters. A given processor cluster may include a plurality of processors, a digital power estimation (DPE) circuit coupled to the plurality of processors and configured to estimate the power consumed by the plurality of processors, and a rate control circuit coupled to the plurality of processors. The power divider circuit may be configured to allocate power to the plurality of component circuits and one or more processor clusters from a power budget for the integrated circuit. The power divider circuit may be configured to transmit an indication of the power allocated to a given processor cluster to the rate control circuit. The rate control circuit may be configured to manage the power consumption of the corresponding component circuits based on the indication of the allocated power and the power consumption estimated from the DPE circuit. A given processor cluster may further include a power control circuit configured to limit power consumption by the plurality of processors based on one or more inputs requesting reduced power consumption. The rate control circuit may be configured to manage power consumption using one or more inputs.

[0064] FIG. 10 is a block diagram of an embodiment of a system comprising a plurality of illustrated SOCs (120A to 120D). Each SOC (120A to 120D) includes a power divider circuit (10) and a D2D interface circuit (24). SOCs (120A and 120B) are supplied by a first level voltage regulator (VR) (160) (through second level voltage regulators, not shown in FIG. 10), and SOCs (120C and 120D) are supplied through a first level voltage regulator (162) (through second level voltage regulators, not shown in FIG. 10). Because the SOCs (120A and 120B) share the same first-level voltage regulator (160), the power divider circuits (10) can share credits and still protect the capacity of the first-level voltage regulator (160). Likewise, the SOCs (120C and 120D) share the same first-level voltage regulator, and the power divider circuits (10) can share credits and still protect the capacity of the first-level voltage regulator (162). Possible sharing is illustrated by the dashed lines (164 and 166) in FIG. 10, but as discussed above, communication can actually be made through D2D interface circuits (24). The SOCs (120A and 120B) can also communicate with the SOCs (120C and 120D) through D2D interfaces, but in one embodiment, they may not share power credits. Note that although two SOCs (120A and 120B or 120C and 120D) are shown as shared credits, in other embodiments, more than two SOCs may share credits. For example, if more than two SOCs share the same first-level voltage regulator, those SOCs may share credits.

[0065] Accordingly, in one embodiment, the system may include a plurality of integrated circuits implemented on each semiconductor substrate (e.g., SOCs). The plurality of integrated circuits may be coupled via chip-to-chip interconnects. Each of the plurality of integrated circuits includes a plurality of component circuits, wherein each component circuit of the plurality of component circuits includes a respective rate control circuit. Each integrated circuit may further include a power divider circuit coupled to the plurality of component circuits. The power divider circuit may be configured to allocate power to the plurality of component circuits based on a power budget for each integrated circuit. Each rate control circuit may be configured to generate respective power requests and respective minimum requests, wherein each minimum request represents the minimum amount of power to be consumed by the corresponding component circuits. The power divider circuit may be configured to ensure that the plurality of component circuits receive at least the same power allocation as their respective minimum requests and to allocate the remaining power budget based on a power distribution policy and each power request. A power divider circuit may be configured to transmit an indication of an unallocated portion of the remaining power budget to a power divider circuit of another integrated circuit among a plurality of integrated circuits via a chip-to-chip interconnect. In one embodiment, the power divider circuit of each integrated circuit is configured to receive a second indication of an unallocated portion of the remaining power budget from the power divider circuit of another integrated circuit among the plurality of integrated circuits, wherein the power divider circuit may be configured to include a portion not allocated to subsequent power allocation. In one embodiment, the system may include a plurality of voltage regulators, wherein a given voltage regulator among the plurality of voltage regulators is configured to supply power to a subset of the plurality of integrated circuits.The power divider circuits of each integrated circuit in the subset can be configured to transmit indications of the unassigned portion of the subset.

[0066] Referring now to FIG. 11, a flowchart illustrating one embodiment of the method is shown. In one embodiment, the method may include the step of allocating power to a plurality of component circuits by a power divider circuit (Block 170). Among the plurality of component circuits, a given component circuit is included in one of a plurality of independent power domains, and the plurality of component circuits each include a rate control circuit. The method may further include the step of transmitting each indication of the power allocated from the power divider circuit to each rate control circuit (Block 172). The method may also further include the step of managing the power consumption of the plurality of component circuits by each rate control circuit based on each indication of the allocated power provided to each rate control circuit (Block 174). In one embodiment, a given component circuit may include a power control circuit configured to limit power consumption by one or more circuits within the given component circuit based on one or more inputs requesting reduced power consumption. The step of managing power consumption in the plurality of component circuits may include the step of using one or more inputs by each rate control circuit. In one embodiment, the step of using one or more inputs may include: a step of requesting a first level of reduced power consumption using a first input among one or more inputs; and a step of requesting a second level of reduced power consumption using a second input among one or more inputs, wherein the second level is further reduced than the first level. In one embodiment, the step of requesting a first level of reduced power consumption may be based on the remaining amount of allocated power that falls below a first threshold. In one embodiment, the step of requesting a second level of reduced power consumption may be based on the remaining amount of allocated power that falls below a second threshold.

[0067] FIG. 12 is a flowchart illustrating another embodiment of the method. In one embodiment, the method may include the step (block 180) of generating respective power requests and respective minimum requests for a power divider circuit of a system by respective rate control circuits of respective component circuits of a plurality of component circuits of a system. Each minimum request may represent minimum amounts of power that can be consumed by the corresponding component circuits. The method may further include the step (block 182) of allocating power to a plurality of component circuits by a power divider circuit. The allocating step may include the step of ensuring that a plurality of component circuits receive an allocation of power equal to at least the minimum value of each minimum request and each power request; and the step of allocating a remaining power budget based on a power distribution policy and each power request. In one embodiment, among a plurality of component circuits, a given component circuit may include a power control circuit configured to cause reduced power consumption in the given component circuit, and each minimum request for the given component circuit may be based on the maximum amount of reduced power consumption that the power control circuit can cause. In one embodiment, a given component circuit may experience leakage current in inactive transistors during use, and each minimum request for the given component circuit may additionally be based on leakage power consumed through the leakage current. In one embodiment, the physical interconnection between the power divider circuit of a given component circuit and each rate control circuit among a plurality of component circuits may include a shared bus for transmitting each power request and each minimum request, and the method may further include the step of selecting one of each power request and each minimum request to transmit on the shared bus.In one embodiment, the step of selecting one of each power request and each lowest request to transmit on a shared bus may include: selecting each lowest request based on a change in each lowest request since the most recent transmission of each lowest request; selecting each power request based on a change in each power request since the most recent transmission of each power request; and selecting the least recently transmitted one of each lowest request and each power request based on the fact that there is no change in each power request since the most recent transmission of each power request and no change in each lowest request since the most recent transmission of each power request.

[0068] computer system

[0069] Next, referring to FIG. 13, a block diagram of one embodiment of a system (700) is illustrated. In the illustrated embodiment, the system (700) includes at least one instance of a system-on-chip (SOC) (706) coupled to one or more peripheral devices (704) and an external memory (702). A power supply unit (PMU) (708) is provided to supply a supply voltage to the SOC (706) as well as supply one or more supply voltages to the memory (702) and / or peripheral devices (704). In some embodiments, more than one instance of the SOC may be included (and more than one memory (702) may also be included). In one embodiment, the memory (702) may include the memory (122) illustrated in FIG. 9. In one embodiment, the SOC (706) may be an instance of the SOC (120) illustrated in FIG. 9. The PMU (708) may include the PMU (124) shown in FIG. 9 in one embodiment and the voltage regulators (160 and 162) shown in FIG. 10 in one embodiment.

[0070] Peripheral devices (704) may include any desired circuitry depending on the type of system (700). For example, in one embodiment, the system (704) may be a mobile device (e.g., a personal digital assistant (PDA), a smartphone, etc.) and the peripheral devices (704) may include devices for various types of wireless communication such as Wi-Fi, Bluetooth, cellular, a global positioning system, etc. The peripheral devices (704) may also include additional storage including RAM storage, solid-state storage, or disk storage. The peripheral devices (704) may include user interface devices such as display screens including touch display screens or multi-touch display screens, keyboards or other input devices, microphones, speakers, etc. In other embodiments, the system (700) may be any type of computing system (e.g., a desktop personal computer, a laptop, a workstation, a nettop, etc.).

[0071] The external memory (702) may include any type of memory. For example, the external memory (702) may be SRAM, dynamic RAM (DRAM) such as synchronous DRAM (SDRAM), double data rate (DDR, DDR2, DDR3, etc.) SDRAM, RAMBUS DRAM, low-power versions of DDR DRAM (e.g., LPDDR, mDDR, etc.). The external memory (702) may include one or more memory modules on which memory devices are mounted, such as single inline memory modules (SIMM), dual inline memory modules (DIMM), etc. Alternatively, the external memory (702) may include one or more memory devices mounted on the SOC (706) in a chip-on-chip or package-on-package implementation.

[0072] As illustrated, the system (700) is depicted as being applicable to a wide range of areas. For example, the system (700) may be used as part of chips, circuits, components, etc. of a desktop computer (710), a laptop computer (720), a tablet computer (730), a cellular or mobile phone (740), or a television (750) (or a set-top box coupled to the television). Also illustrated are a smartwatch and a health monitoring device (760). In some embodiments, the smartwatch may include various general-purpose computing-related functions. For example, the smartwatch may provide access to email, cell phone services, user calendars, etc. In various embodiments, the health monitoring device may be a dedicated medical device or may otherwise include dedicated health-related functions. For example, the health monitoring device may monitor the user's vital signs, track the user's proximity to other users for the purpose of epidemiological social distancing, perform contact tracing, and provide communication to emergency services in the event of a health crisis. In various embodiments, the smartwatch mentioned above may or may not include some or any of the health monitoring related functions. Other wearable devices, such as devices worn around the neck, devices implantable in the human body, and glasses designed to provide augmented and / or virtual reality experiences, are also considered.

[0073] The system (700) may additionally be used as part of a cloud-based service(s) (770). For example, the previously mentioned devices and / or other devices may access computing resources in the cloud (i.e., remotely located hardware and / or software resources). Additionally, the system (700) may be used in one or more devices in the home other than those previously mentioned. For example, devices in the home may monitor and detect conditions requiring attention. For example, various devices in the home (e.g., refrigerator, cooling system, etc.) may monitor the status of the device and provide a warning to the homeowner (or, for example, a repair facility) if a specific event is detected. Alternatively, a thermostat may monitor the temperature of the home and automate adjustments to the heating / cooling system based on the homeowner's history of responses to various conditions. Additionally, FIG. 13 illustrates the application of the system (700) to various modes of transport. For example, the system (700) may be used in control and / or entertainment systems for aircraft, trains, buses, rental cars, private cars, watercraft ranging from private boats to cruise ships, scooters (rental or owned), etc. In various cases, the system (700) may be used to provide automated guidance (e.g., autonomous vehicles), general system control, etc. Any many other such embodiments are possible and considered. It should be noted that the devices and applications illustrated in FIG. 13 are merely illustrative and are not intended to be limiting. Other devices are also possible and considered.

[0074] computer-readable storage media

[0075] Now, referring to FIG. 14, a block diagram of one embodiment of a computer-readable storage medium (800) is illustrated. Generally speaking, a computer-readable storage medium may include any storage medium that is accessible by a computer during use to provide instructions and / or data to the computer. For example, a computer-readable storage medium may include magnetic or optical media, such as a disk (fixed or removable), tape, CD-ROM, DVD-ROM, CD-R, CD-RW, DVD-R, DVD-RW, or Blu-ray. The storage medium may further include volatile or non-volatile memory media such as RAM (e.g., synchronous dynamic RAM (SDRAM), Rambus RDRAM (RDRAM), static RAM (SRAM), etc.), ROM, or flash memory. The storage medium may be physically contained within the computer to which the storage medium provides instructions / data. Alternatively, the storage medium may be connected to the computer. For example, the storage medium may be connected to the computer via a wireless link, such as a network or network-attached storage. The storage medium can be connected via a peripheral interface such as a Universal Serial Bus (USB). Generally, the computer-accessible storage medium (800) can store data in a non-transient manner, where non-transient in this context may refer to not transmitting commands / data over a signal. For example, the non-transient storage may be volatile (and may lose stored commands / data in response to a power outage) or non-volatile.

[0076] The computer-accessible storage medium (800) of FIG. 14 may store a database (804) representing an SOC (120). Generally, the database (804) may be a database that can be read by a program and used directly or indirectly to manufacture hardware containing the SOC (120). For example, the database may be a behavior-level description or register-transfer level (RTL) description of hardware functions in a high-level design language (HDL), such as Verilog or VHDL. The description may be read by a synthesis tool capable of synthesizing the description to generate a netlist containing a list of gates from a synthesis library. The netlist contains a set of gates that also represent the functions of the hardware containing the SOC (120). The netlist may then be placed and routed to generate a data set describing geometric shapes to be applied to masks. The masks may then be used in various semiconductor manufacturing steps to create semiconductor circuits or circuits corresponding to the SOC (120). Alternatively, the database (804) on the computer-accessible storage medium (800) may be a netlist (with or without a synthetic library) or a dataset as desired.

[0077] While a computer-accessible storage medium (800) stores a representation of the SOC (10), other embodiments may convey a representation of any part of the SOC (120), including any subset of the components illustrated in FIG. 9 as desired. A database (804) may represent any part of the above.

[0078] ***

[0079] The present disclosure includes references to groups of “examples” or “examples” (e.g., “some embodiments” or “various embodiments”). The embodiments are different implementations or instances of the disclosed concepts. Designations such as “example,” “one embodiment,” “a specific embodiment,” etc., do not necessarily refer to the same embodiment. A number of possible embodiments are considered, including modifications or alternatives that fall within the spirit or scope of the present disclosure as well as those specifically disclosed.

[0080] This disclosure may discuss potential benefits that may arise from the disclosed embodiments. Not all implementations of these embodiments necessarily represent any or all of the potential benefits. Whether benefits for a particular implementation are realized depends on many factors, some of which are outside the scope of this disclosure. In fact, there are many reasons why an implementation within the scope of the claims may not represent some or all of the disclosed benefits. For example, a particular implementation may include other circuitry outside the scope of this disclosure that nullifies or reduces one or more of the benefits disclosed in relation to one of the disclosed embodiments. Additionally, design practices of a suboptimal implementation (e.g., implementation techniques or tools) may also nullify or reduce the disclosed benefits. Even assuming a skilled implementation, the realization of benefits may still depend on other factors, such as the environmental circumstances in which the implementation is deployed. For example, inputs supplied to a particular implementation may prevent one or more of the problems addressed in this disclosure from occurring in certain cases, and as a result, the benefits of the solution may not be realized. Given the existence of possible factors outside of this disclosure, it is expressly intended that any potential benefits described herein should not be interpreted as claims that must be satisfied to prove infringement. Rather, the identification of such potential benefits is intended to exemplify the type of improvement(s) available to designers who have the benefits of this disclosure. The fact that these benefits are described permissively (e.g., referring to a particular benefit as “may occur”) is not intended to convey doubt as to whether such benefits can actually be realized, but rather to acknowledge the technical reality that the realization of such benefits often depends on additional factors.

[0081] Unless otherwise stated, the embodiments are not limiting. That is, the disclosed embodiments are not intended to limit the scope of the claims based on this disclosure, even if only one example is described with respect to a particular feature. The disclosed embodiments are intended to be illustrative rather than limiting, and there are no statements contrary to the disclosure. Accordingly, this application is intended to allow claims covering not only the disclosed embodiments but also such alternatives, modifications, and equivalents that are obvious to a person skilled in the art having the advantage of this disclosure.

[0082] For example, the features of the present application may be combined in any suitable manner. Accordingly, new claims may be formed during the course of the present application (or the application claiming priority thereto) for any combination of such features. In particular, with reference to the appended claims, features of dependent claims may be combined with features of other dependent claims where appropriate, including claims dependent on other independent claims. Likewise, features of each independent claim may be combined where appropriate.

[0083] Accordingly, the appended dependent claims may each be drafted to be dependent on one other claim, but additional dependencies are also considered. Any combination of features in dependencies consistent with the present disclosure may be considered and claimed in this application or other applications. In short, the combinations are not limited to those specifically enumerated in the appended claims.

[0084] Where appropriate, claims written in one format or statutory type (e.g., device) are also considered to be intended to support corresponding claims in another format or statutory type (e.g., method).

[0085] ***

[0086] Because this disclosure is a legal document, various terms and phrases may be subject to administrative and judicial interpretation. Notice provided herein is that the following paragraphs, as well as the definitions provided throughout this disclosure, should be used to determine how to interpret the claims drafted based on this disclosure.

[0087] References to the singular form of an item (i.e., a noun or noun phrase preceded by "a," "an," or "the") are intended to mean "one or more" unless the context clearly indicates otherwise. Accordingly, a reference to "item" in a claim does not exclude additional instances of the item without context. "Plural" items refer to two or more sets of items.

[0088] The word "may" is used here not in an obligatory sense (i.e., must) but in a permissive sense (i.e., having the possibility, being able to).

[0089] The terms and forms "comprising" and "including" are open-ended and mean "including but not limited to."

[0090] Where the term “or” is used in this disclosure in relation to a list of options, it shall be understood to be used in a generally inclusive sense unless otherwise provided by the context. Thus, referring to “x or y” is equivalent to “x or y, or both,” and thus encompasses 1) x but not y, 2) y but not x, and 3) both x and y. On the other hand, phrases such as “either x or y but not both” make it clear that “or” is used in an exclusive sense.

[0091] References to “w, x, y, or z, or any combination thereof” or “...at least one of w, x, y, and z” are intended to encompass all possibilities related to a single element up to the total number of elements in the set. For example, given the set [w, x, y, z], these expressions encompass any single element of the set (e.g., w but not x, y, or z), any two elements (e.g., w and x but not y or z), any three elements (e.g., w, x, and y but not z), and all four elements. Thus, the phrase “...at least one of w, x, y, and z” refers to at least one element of the set [w, x, y, z] and thereby encompasses all possible combinations in the list of such elements. This phrase should not be interpreted as requiring the existence of at least one instance of w, at least one instance of x, at least one instance of y, and at least one instance of z.

[0092] In this disclosure, various "labels" may precede nouns or noun phrases. Unless otherwise provided by the context, different labels used in the feature (e.g., "first circuit," "second circuit," "specific circuit," "given circuit," etc.) refer to different instances of the feature. Additionally, when applied to the feature, the labels "first," "second," and "third" do not imply any type of order (e.g., spatial, temporal, logical, etc.) unless otherwise specified.

[0093] The phrase "based on" is used to describe one or more factors that influence a decision. This term does not exclude the possibility that additional factors may influence the decision. That is, the decision may be based on specific factors alone, or on specific factors as well as other unspecified factors. Consider the phrase "determine A based on B." This phrase specifies that B is used to determine A or is a factor that influences the determination of A. This phrase does not exclude that the determination of A may be based on some other factors, such as C. This phrase is also intended to encompass embodiments where A is determined based solely on B. As used herein, the phrase "based on" is synonymous with the phrase "at least partially based on."

[0094] The phrases “in response to” and “responding to” describe one or more factors that trigger an effect. These phrases do not exclude the possibility that additional factors may influence or trigger the effect, either jointly with the specified factors or independently of the specified factors. That is, the effect may respond only to the relevant factors, or it may respond to the specific factors as well as other unspecified factors. Consider the phrase “perform A in response to B.” This phrase specifies that B is a factor that triggers the performance of A or triggers a specific result for A. This phrase does not exclude that performing A may also be a response to some other factor, such as C. This phrase also does not exclude that performing A may respond jointly to B and C. This phrase is also intended to encompass embodiments where A is performed in response only to B. As used herein, the phrase “responding to” is synonymous with the phrase “at least partially responding to.” Likewise, the phrase “in response to” is synonymous with the phrase “at least partially responding to.”

[0095] ***

[0096] Within this disclosure, different entities (which may be variously referred to as “units,” “circuits,” other component circuits, etc.) may be described or claimed to be “configured” to perform one or more tasks or operations. The formula “entity configured to perform [one or more tasks]” is used herein to refer to a structure (i.e., a physical one). More specifically, this formula is used to indicate that such a structure is arranged to perform one or more tasks during operation. Even if the structure is not currently operating, it may be said that the structure is “configured” to perform some tasks. Accordingly, an entity described or referred to as being “configured” to perform some tasks refers to a physical thing, such as a device, circuit, or system having memory and processor units that store executable program instructions to implement the tasks, etc. Such phrases are not used herein to refer to intangible things.

[0097] In some cases, various units / circuits / component circuits may be described herein as performing a set of tasks or operations. Such entities are understood to be "configured" to perform such tasks / operations unless specifically mentioned otherwise.

[0098] The term "configured" is not intended to mean "configurable." For example, an unprogrammed FPGA would not be considered "configured" to perform a specific function. However, such an unprogrammed FPGA can be "configurable" to perform that function. After proper programming, the FPGA can be said to be "configured" to perform a specific function.

[0099] For the purposes of U.S. patent applications based on the present disclosure, references in claims that a structure is "configured" to perform one or more operations are expressly intended not to explicitly invoke 35 USC §112(f) for the relevant claim elements. If the applicant wishes to invoke Section 112(f) during the course of a U.S. patent application based on the present disclosure, the claim elements will be referred to using the configuration of "means for [performing] a function."

[0100] Different “circuits” may be described in this disclosure. These circuits or “circuitry” constitute hardware comprising various types of circuit elements, such as combinational logic, clocked storage devices (e.g., flip-flops, registers, latches, etc.), finite state machines, memory (e.g., random-access memory, inserted dynamic random-access memory), programmable logic arrays, etc. Circuitry may be custom-designed or taken from standard libraries. In various embodiments, circuitry may appropriately include digital component circuits, analog component circuits, or a combination of both. Specific types of circuits may generally be referred to as “units” (e.g., decode unit, arithmetic logic unit (ALU), function unit, memory management unit (MMU), etc.). These units also refer to circuits or circuitry.

[0101] Accordingly, the disclosed circuits / units / component circuits and other elements illustrated in the drawings and described herein include hardware elements such as those described in the preceding paragraph. In many cases, the internal arrangement of hardware elements within a particular circuit can be specified by describing the function of the circuit. For example, a particular "decode unit" may be described as performing the function of "processing the opcode of an instruction and routing the instruction to one or more of a plurality of function units," which implies that the decode unit is "configured" to perform this function. Specification of such function is sufficient to suggest to those skilled in the art of computer technology a set of possible structures for the circuit.

[0102] In various embodiments, as discussed in the previous paragraph, circuits, units, and other elements are defined by functions or operations configured to be implemented. The arrangement of these circuits / units / component circuits relative to one another and the manner in which they interact form the microarchitecture definition of hardware that is ultimately manufactured in an integrated circuit or programmed into an FPGA to form a physical implementation of the microarchitecture definition. Accordingly, the microarchitecture definition is recognized by those skilled in the art as a structure from which many physical implementations can be derived, all of which belong to the broader structure described by the microarchitecture definition. That is, a person skilled in the art who receives the microarchitecture definition provided according to this disclosure can implement the structure by coding a description of the circuits / units / component circuits in a hardware description language (HDL), such as Verilog or VHDL, without excessive experimentation and by applying the ordinary art. The HDL description is often expressed in a manner that may appear functional. However, to a person skilled in the art, such HDL descriptions are a method used to translate the structure of a circuit, unit, or component circuit into the next level of implementation details. Such HDL descriptions may take the form of behavioral code (typically unsynthesizable), Register Transfer Language (RTL) code (typically synthesizable, unlike behavioral code), or structural code (e.g., netlists specifying logic gates and their connectivity). The HDL descriptions can subsequently be synthesized against a library of cells designed for a given integrated circuit manufacturing technology, modified for timing, power, and other reasons to generate masks, and ultimately become the final design database transmitted to a foundry to produce the integrated circuit.Some hardware circuits or parts thereof may also be custom-designed in a schematic editor and captured in the integrated circuit design along with the synthesized circuit parts. Integrated circuits may include transistors and other circuit elements (passive elements such as capacitors, resistors, inductors, etc.), and transistors and circuit elements may be interconnected. Some embodiments may implement multiple integrated circuits coupled to each other to implement the hardware circuit, and / or in some embodiments, individual elements may be used. Alternatively, the HDL design may be synthesized into a programmable logic array, such as a field programmable gate array (FPGA), and may be implemented on the FPGA. This separation between the design of a group of circuits and the subsequent low-level implementation of these circuits generally results in a scenario where the circuit or logic designer does not specify a particular set of structures for the low-level implementation, going beyond a description of what the circuit is configured to do, as these processes are typically performed at different stages of the circuit implementation process.

[0103] The fact that many different low-level combinations of circuit elements can be used to implement the same specifications of a circuit results in multiple equivalent structures for that circuit. As mentioned, these low-level circuit implementations can vary depending on changes in manufacturing technology, the foundry selected to manufacture the integrated circuit, the library of cells provided for a specific project, etc. In many cases, the choices made by different design tools or methodologies to generate these different implementations can be arbitrary.

[0104] Furthermore, for a given embodiment, it is common for a single implementation of a specific functional specification of the circuit to involve a large number of devices (e.g., millions of transistors). Consequently, the immense volume of such information makes it impractical to provide a full description of the low-level structure used to implement a single embodiment, as well as an extensive array of equivalent possible implementations. For this reason, the present disclosure describes the structure of the circuit using functional abbreviations commonly used in the industry.

[0105] Additional embodiments are considered based on one or more of the numbered examples below.

[0106] 1. As a system,

[0107] A plurality of component circuits, wherein each of the plurality of component circuits includes a respective rate control circuit; and

[0108] It includes a power divider circuit coupled to a plurality of component circuits, and

[0109] The power distributor circuit is configured to allocate power to multiple component circuits based on the power budget for the system;

[0110] Each rate control circuit is configured to generate respective minimum requests and respective power requests for the power divider circuit, and each minimum request represents the minimum amount of power that can be consumed by the corresponding component circuits;

[0111] The power divider circuit is configured to ensure that multiple component circuits receive an allocation of power equal to at least the minimum value of each minimum request and each power request;

[0112] The power distribution circuit is configured to allocate the remaining power budget based on the power distribution policy and each power request.

[0113] 2. In the system of Example 1, among the plurality of component circuits, a given component circuit includes a power control circuit configured to cause reduced power consumption in the given component circuit, and each minimum request for the given component circuit is based on the maximum amount of reduced power consumption that the power control circuit can cause.

[0114] 3. In the system of Example 2, the given component circuit experiences leakage current in the inactive transistors during use, and each minimum requirement for the given component circuit is additionally based on the leakage power consumed through the leakage current.

[0115] 4. In the system of Example 1, the given component circuit further includes a digital power estimation (DPE) circuit configured to estimate the power consumption of the given component circuit, and each power request is based on the estimated power consumption from the DPE circuit.

[0116] 5. In the system of Example 4, the DPE circuit is further configured to estimate leakage power and provide each minimum request based on the maximum amount of leakage power and reduced power consumption.

[0117] 6. In any one of the systems of Examples 1 to 5, the physical interconnection between each rate control circuit and the power divider circuit of a given component circuit among a plurality of component circuits comprises a shared bus for transmitting each power request and each minimum request, and each rate control circuit is configured to select one of each power request and each minimum request to transmit on the shared bus.

[0118] 7. In the system of Example 6, each rate control circuit is configured to select each lowest request based on the change in each lowest request after the most recent transmission of each lowest request.

[0119] 8. In the system of Example 6 or Example 7, each rate control circuit is configured to select each power request based on the change in each power request since the most recent transmission of each power request.

[0120] 9. In any one of the systems of Examples 6 to 8, each rate control circuit is configured to select the least recently transmitted of each lowest request and each power request based on the fact that there is no change in each power request since the most recent transmission of each power request and no change in each lowest request since the most recent transmission of each lowest request.

[0121] 10. In any one of the systems of Examples 6 through 9, the power divider circuit is configured to use a previously received request as the latest request for each power request and for each lowest request that is not selected.

[0122] 11. In any one of the systems of Examples 1 to 10, the power distribution policy includes a first-level policy that specifies the distribution of the remaining power budget among the component circuits of each type.

[0123] 12. In the system of Example 11, the power distribution policy includes a second-level policy that specifies the distribution of the amount among the component circuits of a given type for the amount allocated to the component circuit of a given type.

[0124] 13. As a system,

[0125] A plurality of integrated circuits implemented on respective semiconductor substrates, wherein the plurality of integrated circuits are coupled through inter-chip interconnections, and each of the plurality of integrated circuits is,

[0126] A plurality of component circuits, wherein each of the plurality of component circuits includes a respective rate control circuit; and

[0127] It includes a power divider circuit coupled to a plurality of component circuits, and

[0128] The power divider circuit is configured to allocate power to multiple component circuits based on the power budget for each integrated circuit;

[0129] Each rate control circuit is configured to generate each power request and each minimum request, and each minimum request represents the minimum amount of power that can be consumed by the corresponding component circuits;

[0130] The power divider circuit is configured to ensure that multiple component circuits receive an allocation of power equal to at least the minimum value of each minimum request and each power request;

[0131] The power distribution circuit is configured to allocate the remaining power budget based on the power distribution policy and each power request;

[0132] The power divider circuit is configured to transmit an indication of the unallocated portion of the remaining power budget to the power divider circuit of another integrated circuit among multiple integrated circuits via chip-to-chip interconnects.

[0133] 14. In the system of Example 13, the power divider circuit of each integrated circuit is configured to receive a second indication of the unallocated portion of the remaining power budget from the power divider circuit of another integrated circuit among the multiple integrated circuits, and the power divider circuit is configured to include the unallocated portion in the subsequent power allocation.

[0134] 15. In the system of Example 13 or Example 14, a plurality of voltage regulators are further included, wherein a given voltage regulator among the plurality of voltage regulators is configured to supply power to a subset of a plurality of integrated circuits, and power divider circuits of each integrated circuit of the subset are configured to transmit indications of an unassigned portion of the subset.

[0135] 16. As a method,

[0136] A step of generating each power request and each minimum request for a power distributor circuit of a system by a rate control circuit of each component circuit of a plurality of component circuits of a system, wherein each minimum request represents a minimum amount of power that can be consumed by the corresponding component circuits; and

[0137] It includes the step of allocating power to a plurality of component circuits by a power divider circuit, and

[0138] The allocation step is,

[0139] A step of ensuring that a plurality of component circuits receive an allocation of power equal to at least the minimum value of each minimum request and each power request; and

[0140] It includes a step of allocating the remaining power budget based on power distribution policies and each power request.

[0141] 17. In the method of Example 16, among a plurality of component circuits, a given component circuit includes a power control circuit configured to cause reduced power consumption in the given component circuit, and each minimum request for the given component circuit is based on the maximum amount of reduced power consumption that the power control circuit can cause.

[0142] 18. In the method of Example 16 or Example 17, the given component circuit experiences leakage current in inactive transistors during use, and each minimum requirement for the given component circuit is additionally based on the leakage power consumed through the leakage current.

[0143] 19. In any one of the methods of Examples 16 to 18, the physical interconnection between each rate control circuit and the power divider circuit of a given component circuit among a plurality of component circuits comprises a shared bus for transmitting each power request and each minimum request, and the method further comprises the step of selecting one of each power request and each minimum request to transmit on the shared bus.

[0144] 20. In the method of Example 19, the step of selecting one of each power request and each lowest request to transmit on a shared bus is,

[0145] A step of selecting each lowest request based on the change in each lowest request after the most recent transmission of each lowest request;

[0146] A step of selecting each power request based on the change in each power request after the most recent transmission of each power request; and

[0147] It includes a step of selecting the least recently transmitted of each lowest request and each power request based on the fact that there is no change in each power request since the most recent transmission of each power request and no change in each lowest request since the most recent transmission of each lowest request.

[0148] Once the foregoing disclosure is fully understood, various variations and modifications will be apparent to a person skilled in the art. The following claims are intended to be interpreted to include all such variations and modifications.

Claims

Claim 1 A system comprising a plurality of component circuits, wherein a given component circuit among the plurality of component circuits is included in one of a plurality of independent power domains, and the plurality of component circuits each comprise a rate control circuit and a power control circuit; and a power splitter circuit coupled to the plurality of component circuits, wherein the power splitter circuit is configured to allocate power to the plurality of component circuits from a power budget for the system; wherein the power splitter circuit is configured to transmit each indication of the allocated power to each of the rate control circuits; and wherein each of the rate control circuits is configured to manage power consumption in the corresponding component circuits based on each indication of the allocated power provided to each of the rate control circuits; and each of the power control circuits is configured to limit power consumption within the corresponding component circuits based on one or more respective inputs received from each of the rate control circuits, and a first power control circuit among the power control circuits is configured to implement a first set of power management mechanisms specific to the first component circuit among the component circuits, and a second power control circuit among the power control circuits is configured to implement a second different set of power management mechanisms specific to the second component circuit among the component circuits; and the component circuits and the power divider circuits are included in a system-on-chip (SOC) integrated on one or more co-packaged semiconductor dies, system. Claim 2 A system according to claim 1, wherein the allocated power is expressed in terms of a plurality of credits, a given credit represents a specific amount of power, and each indication of the allocated power includes the number of the plurality of credits. Claim 3 delete Claim 4 In claim 1, each rate control circuit of the given component circuit is configured to request a first level of reduced power consumption using a first input among the one or more inputs and to request a second level of reduced power consumption using a second input among the one or more inputs, wherein the second level is further reduced than the first level, a system. Claim 5 In paragraph 4, the system is configured such that each rate control circuit requests the first level of reduced power consumption based on the remaining amount of the allocated power that falls below the first threshold. Claim 6 A system according to claim 5, wherein each rate control circuit is configured to request the second level of reduced power consumption based on the remaining amount of the allocated power that falls below the second threshold. Claim 7 A system according to any one of claims 4 to 6, wherein the second level engages each of one or more power reduction mechanisms implemented by the corresponding component circuit. Claim 8 A system according to any one of claims 4 to 6, wherein each rate control circuit of the given component circuit is configured to indicate that reduced power consumption through the power control circuit was in use. Claim 9 A system according to any one of claims 4 to 6, wherein the given component circuit comprises a digital power estimation (DPE) circuit configured to estimate the power consumption of the given component circuit and report the estimated power consumption to each of the rate control circuits of the given component circuit, and each of the rate control circuits configured to manage the power consumption of the given component circuit based further on the estimated power consumption. Claim 10 A system according to claim 9, wherein the digital power estimation (DPE) circuit is coupled to the power control circuit and configured such that the power control circuit reduces the power consumption of the given component circuit. Claim 11 A system according to claim 1, wherein at least one of the plurality of component circuits is a processor cluster comprising a plurality of processors. Claim 12 A system according to claim 1, wherein at least one of the plurality of component circuits is a graphics processing unit (GPU). Claim 13 A system according to claim 1, wherein at least one of the plurality of component circuits is a peripheral component circuit. Claim 14 A system according to claim 1, wherein each rate control circuit is configured to generate each power request and each floor request for the power divider circuit, and each floor request represents a minimum amount of power that can be consumed by the corresponding component circuits; the power divider circuit is configured to ensure that the plurality of component circuits receive an allocation of power equal to at least the minimum value of each floor request and each power request; and the power divider circuit is configured to allocate a remaining power budget based on a power distribution policy and each power request. Claim 15 In paragraph 14, the system, wherein each of the minimum requests for the given component circuits is based on the maximum amount of reduced power consumption that the power control circuit can cause. Claim 16 In paragraph 15, the given component circuit experiences leakage current in inactive transistors during use, and each of the given minimum requirements for the given component circuit is additionally based on the leakage power consumed through the leakage current, a system. Claim 17 A system according to any one of claims 14 to 16, wherein the physical interconnection between each rate control circuit of the given component circuit and the power divider circuit comprises a shared bus for transmitting each power request and each minimum request, and each rate control circuit is configured to select one of each power request and each minimum request to transmit on the shared bus. Claim 18 In paragraph 17, a system wherein each rate control circuit of the given component circuit is configured to select each lowest request based on a change in each lowest request after the most recent transmission of each lowest request. Claim 19 In claim 17, a system wherein each rate control circuit of the given component circuit is configured to select each power request based on a change in each power request since the most recent transmission of each power request. Claim 20 A system according to claim 17, wherein each rate control circuit of the given component circuit is configured to select the least recently transmitted of each lowest request and each power request based on the fact that there is no change in each power request since the most recent transmission of each power request and no change in each lowest request since the most recent transmission of each lowest request. Claim 21 In paragraph 17, the power divider circuit is configured to use a previously received request as the latest request for each of the power requests and for each of the lowest requests that are not selected, in a system. Claim 22 A method comprising: a step of allocating power to a plurality of component circuits by means of a power divider circuit, wherein a given component circuit among the plurality of component circuits is included in one of a plurality of independent power domains, and the plurality of component circuits each include a rate control circuit and a power control circuit; a step of transmitting each indication of the allocated power from the power divider circuit to each rate control circuit; a step of managing the power consumption of the plurality of component circuits by each rate control circuit based on each indication of the allocated power provided to each rate control circuit; and a step of limiting the power consumption within the corresponding component circuits by each power control circuit based on one or more respective inputs received from each rate control circuit, wherein the limiting step comprises: a step of implementing a first set of power management mechanisms specified for the first component circuit among the component circuits by a first power control circuit among the power control circuits; A method comprising the step of implementing a second different set of power management mechanisms specified in a second component circuit among the component circuits by means of a second power control circuit among the power control circuits, wherein the component circuits and the power divider circuit are included in a system-on-chip (SOC) integrated on one or more co-packaged semiconductor dies. Claim 23 delete Claim 24 A method according to claim 22, wherein the step of using one or more inputs comprises: a step of requesting a first level of reduced power consumption using a first input among the one or more inputs; and a step of requesting a second level of reduced power consumption using a second input among the one or more inputs, wherein the second level is further reduced than the first level. Claim 25 In paragraph 24, the step of requesting the first level of reduced power consumption is based on the remaining amount of the allocated power that falls below the first threshold. Claim 26 In paragraph 25, the step of requesting the second level of reduced power consumption is based on the remaining amount of the allocated power that falls below the second threshold. Claim 27 As an integrated circuit, a power manager circuit including a power divider circuit; a plurality of component circuits; and includes one or more processor clusters, wherein a given processor cluster among the one or more processor clusters comprises a plurality of processors, a Digital Power Estimation (DPE) circuit coupled to the plurality of processors and configured to estimate power consumed by the plurality of processors, a rate control circuit coupled to the plurality of processors, and a power control circuit coupled to the rate control circuit; wherein: the power divider circuit is configured to allocate power to the plurality of component circuits and the one or more processor clusters from a power budget for the integrated circuit; the power divider circuit is configured to transmit an indication of power allocated to the given processor cluster to the rate control circuit; the rate control circuit is configured to manage power consumption in the corresponding component circuits based on the indication of the allocated power and based on the estimated power consumption from the DPE circuit; the power control circuit is configured to limit power consumption by the plurality of processors based on one or more inputs received from the rate control circuit, and the power control circuit is configured to implement a first set of power management mechanisms specific to the plurality of processors, and to one of the plurality of component circuits An integrated circuit comprising a second power control circuit configured to implement a second different set of power management mechanisms specific to the component circuit, wherein the power manager circuit, the component circuits, and the one or more processor clusters are included in a system-on-chip (SOC) integrated on one or more co-packaged semiconductor dies. Claim 28 delete

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