Thin film Transistor array substrate including oxide semiconductor pattern and display device including thereof

Abstract

The present invention relates to an array substrate of a thin-film transistor comprising an oxide semiconductor pattern and a display device using the same, comprising: a substrate including a display area and a non-display area disposed around the display area; and a first thin-film transistor disposed on the substrate, wherein the first thin-film transistor may include: a first oxide semiconductor pattern disposed on the substrate; a first gate electrode disposed below the first oxide semiconductor pattern and overlapping with the first oxide semiconductor pattern; a first source electrode and a first drain electrode connected to the first oxide semiconductor pattern on the first oxide semiconductor pattern; and a first light-blocking pattern that overlaps with the first oxide semiconductor pattern above the first oxide semiconductor pattern and is connected to either the first source electrode or the first drain electrode. Additionally, the first gate electrode and the first light-blocking pattern may include a conductive semiconductor material layer.

Description

Technology Field

[0001] The present invention relates to an array substrate for thin-film transistors comprising an oxide semiconductor pattern, and more particularly to a thin-film transistor array substrate in which thin-film transistors located on the substrate are capable of low-gradation expression, leakage current is blocked, and the threshold voltage is increased, and to a display device including the same. In particular, the invention relates to a display device capable of realizing a wide range of gradation expression and fast on-off operation by increasing the aspect (S-factor) of the thin-film transistors. Background Technology

[0002] Recently, the importance of flat-panel displays has been increasing alongside the development of multimedia. In response to this, flat-panel displays such as liquid crystal displays, plasma displays, and organic light-emitting diodes (OLEDs) are being commercialized. Among these flat-panel displays, OLEDs are currently widely used due to their high response speed, high brightness, and wide viewing angles.

[0003] In such an organic light-emitting display device, a plurality of pixels are arranged in a matrix shape, and each pixel is equipped with a light-emitting device part represented by an organic light-emitting layer and a pixel circuit part represented by a thin film transistor (hereinafter TFT). The pixel circuit part includes a driving thin film transistor (driving TFT) that operates the organic light-emitting device by supplying a driving current and a switching thin film transistor (switching TFT) that supplies a gate signal to the driving thin film transistor.

[0004] In addition, a gate driving circuit that provides a gate signal to a pixel may be disposed in the non-display area of ​​the organic light-emitting display device.

[0005] Thus, the invention relates to an array substrate of thin-film transistors disposed in a pixel circuit portion within a pixel, particularly a sub-pixel, in which leakage current is blocked in the off state and grayscale expression is free in low grayscale, and a display device including the same. The problem to be solved

[0006] The present invention aims to provide a thin-film transistor disposed within a pixel that has a large effect of blocking leakage current in the off state. In addition, the present invention aims to provide a thin-film transistor using an oxide semiconductor pattern as an active layer to secure a high threshold voltage or higher and to freely express gradation at low gradations. Furthermore, the present invention aims to provide an array substrate of a thin-film transistor with a high s-factor value and a display device including the same. means of solving the problem

[0007] To achieve the above objective, the thin film transistor array substrate of the present invention comprises a substrate including a display area and a non-display area disposed around the display area; and a first thin film transistor disposed on the substrate, wherein the first thin film transistor may include a first oxide semiconductor pattern disposed on the substrate; a first gate electrode disposed below the first oxide semiconductor pattern and overlapping with the first oxide semiconductor pattern; a first source electrode and a first drain electrode connected to the first oxide semiconductor pattern on the first oxide semiconductor pattern; and a first light-blocking pattern that overlaps with the first oxide semiconductor pattern above the first oxide semiconductor pattern and is connected to either the first source electrode and the first drain electrode.

[0008] Additionally, a second thin-film transistor may be further disposed on a substrate, and the second thin-film transistor may include a second oxide semiconductor pattern disposed on the substrate; a second gate electrode overlapping with the second oxide semiconductor pattern below the second oxide semiconductor pattern; a second source electrode and a second drain electrode connected to the second oxide semiconductor pattern on the second oxide semiconductor pattern; and a second light-blocking pattern overlapping with the second oxide semiconductor pattern on the second oxide semiconductor pattern.

[0009] In addition, at least one of the first gate electrode and the first light-blocking pattern may include a semiconductor material layer.

[0010] In addition, at least one of the second gate electrode and the second light-blocking pattern may include a semiconductor material layer.

[0011] In addition, at least one of the second gate electrode and the second light-blocking pattern may include a semiconductor material layer.

[0012] Additionally, a third thin-film transistor is further disposed on a substrate, and the third thin-film transistor may include a polycrystalline semiconductor pattern disposed on the substrate; a third gate electrode that overlaps with the polycrystalline semiconductor pattern on the polycrystalline semiconductor pattern; and a third source electrode and a third drain electrode connected to the polycrystalline semiconductor pattern on the polycrystalline semiconductor pattern.

[0013] Meanwhile, the first thin-film transistor is a driving thin-film transistor that drives a pixel in a display area, and the second thin-film transistor may be a switching thin-film transistor placed within the pixel.

[0014] In addition, the third thin-film transistor may be a switching thin-film transistor placed in at least one of a display area and a non-display area.

[0015] In addition, the semiconductor material layer may be a P-type semiconductor material, and the first oxide semiconductor pattern and the second oxide semiconductor pattern may be an n-type semiconductor material.

[0016] In addition, the polycrystalline semiconductor pattern and the semiconductor material layer may be p-type semiconductor materials, and the first oxide semiconductor pattern and the second oxide semiconductor pattern may be n-type semiconductor materials.

[0017] Meanwhile, at least one of the first gate electrode, the first light-blocking pattern, the second gate electrode, and the second light-blocking pattern may be a stacked structure of a metal pattern and a semiconductor material layer.

[0018] The light reflectance of the above semiconductor material layer is smaller than the light reflectance of the metal pattern.

[0019] Additionally, a storage capacitor is further disposed on the substrate, and the storage capacitor includes a first electrode of the storage capacitor disposed on the same layer as the third gate electrode and a second electrode of the storage capacitor disposed on the same layer as the first light-blocking pattern.

[0020] Meanwhile, the polycrystalline semiconductor pattern, the first gate electrode, and the second gate electrode can be placed on the same layer.

[0021] In addition, the first gate electrode, the second gate electrode, and the third gate electrode may be placed on the same layer.

[0022] Meanwhile, the second gate electrode and the second light-blocking pattern can be electrically connected to each other to form a double gate.

[0023] Meanwhile, the parasitic capacitance occurring between the first oxide semiconductor pattern and the first light-blocking pattern may be larger than the parasitic capacitance occurring between the first oxide semiconductor pattern and the first gate electrode.

[0024] And the distance between the first oxide semiconductor pattern and the first light-blocking pattern may be smaller than the distance between the first oxide semiconductor pattern and the first gate electrode.

[0025] Meanwhile, the polycrystalline semiconductor pattern and the semiconductor material layer can be composed of the same type of semiconductor material.

[0026] And the first gate electrode and the second gate electrode have a structure in which a metal pattern and a semiconductor material layer are stacked in sequence, and the first light-blocking pattern and the second light-blocking pattern may have a structure in which a semiconductor material layer and a metal pattern are stacked in sequence.

[0027] In addition, the present invention may further include a light-emitting element portion connected to a first thin-film transistor, and the light-emitting element portion may be a display device comprising an anode electrode connected to a first drain electrode, a cathode electrode corresponding to the anode electrode, and an organic light-emitting layer disposed between the anode electrode and the cathode electrode. Effects of the invention

[0028] The present invention can reduce power consumption by blocking leakage current in the off state by including a driving thin-film transistor including an oxide semiconductor pattern and a switching thin-film transistor including an oxide semiconductor pattern within a pixel. Furthermore, the driving thin-film transistor of the present invention provides a thin-film transistor array substrate that allows for free grayscale expression at low grayscale levels by providing a structure that increases the S-factor value. Additionally, the present invention provides a thin-film transistor capable of raising the threshold voltage value of the driving thin-film transistor within the pixel above a predetermined target value. Moreover, the present invention can impart characteristics corresponding to the role of each switching thin-film transistor by enabling a plurality of switching thin-film transistors disposed within the pixel to have different threshold voltages. Brief explanation of the drawing

[0029] FIG. 1 is a schematic block diagram of a display device according to the present invention. FIG. 2 is a schematic block diagram of a sub-pixel of a display device according to the present invention. FIG. 3 is a circuit diagram of a sub-pixel of a display device according to the present invention. FIG. 4a is a cross-sectional view of a storage capacitor and a driving thin-film transistor and a switching thin-film transistor, comprising a gate driving circuit portion disposed in a non-display area and a gate electrode disposed in a display area and composed of a semiconductor material layer, as a first embodiment of the present invention. Figure 4b is a cross-sectional view of only the driving thin-film transistor in Figure 4a. Figure 4c is a circuit diagram showing the relationship between the parasitic capacitances occurring in Figure 4b. FIG. 4d is a cross-sectional view illustrating the process of the first gate electrode and the second gate electrode becoming conductive in the first embodiment. FIG. 5 is a cross-sectional view of a storage capacitor and a driving thin-film transistor and a switching thin-film transistor, as a second embodiment of the present invention, comprising a single thin-film transistor disposed in a gate driving circuit portion of a non-display area, a gate electrode disposed in a display area and having a stacked structure of a metal material layer and a semiconductor material layer. FIG. 6 is a cross-sectional view of a storage capacitor and a driving thin-film transistor and a switching thin-film transistor, which are disposed in a display area and include a light-blocking pattern composed of a semiconductor material layer, as a third embodiment of the present invention. FIG. 7 is a cross-sectional view of a storage capacitor and a driving thin-film transistor and a switching thin-film transistor, which are disposed in a display area and have a stacked structure of a metal pattern and a semiconductor material layer, as a fourth embodiment of the present invention. Specific details for implementing the invention

[0030] The advantages and features of the present invention and the methods for achieving them will become clear by referring to the embodiments described below in detail together with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below but may be implemented in various different forms, and these embodiments are provided merely to complete the disclosure of the present invention and to fully inform those skilled in the art of the scope of the invention.

[0031] Shapes, sizes, ratios, angles, numbers, etc. disclosed in the drawings for explaining embodiments of the present invention are exemplary, and therefore the present invention is not limited to the depicted details. Throughout the specification, the same reference numerals refer to the same components. Furthermore, in describing the present invention, if it is determined that a detailed description of related prior art could unnecessarily obscure the essence of the present invention, such detailed description is omitted. Where terms such as "includes," "has," or "is made up" are used in this specification, other parts may be added unless "only" is used. Where a component is expressed in the singular, it includes cases where it is included in the plural unless specifically stated otherwise.

[0032] When interpreting components, they are interpreted to include a margin of error even in the absence of separate explicit notation.

[0033] In the case of describing a positional relationship, for example, when the positional relationship between two parts is described using expressions such as 'on,' 'upper,' 'lower,' or 'next to,' one or more other parts may be located between the two parts unless 'immediately' or 'directly' is used.

[0034] In the case of an explanation of a temporal relationship, for example, when a temporal sequence is explained using 'after', 'following', 'next', 'before', etc., it may include cases where the sequence is not continuous unless 'immediately' or 'directly' is used.

[0035] Although terms such as "first," "second," etc., are used to describe various components, these components are not limited by these terms. These terms are used merely to distinguish one component from another. Accordingly, the first component mentioned below may be the second component within the technical scope of the present invention.

[0036] The features of each of the various embodiments of the present invention may be combined or combined with one another, either partially or wholly, and may technically enable various interlocking and driving mechanisms. Each embodiment may be implemented independently of one another or may be implemented together in an interlocking relationship.

[0038] Hereinafter, a first embodiment of the present invention will be described in detail with reference to the attached drawings.

[0039] FIG. 1 is a schematic block diagram of a display device (100) according to the present invention.

[0040] Figure 2 is a schematic block diagram of a sub-pixel (SP) shown in Figure 1.

[0041] As illustrated in FIG. 1, the display device (100) is configured to include a display panel (PAN) in which an image processing unit (110), a degradation compensation unit (150), a memory (160), a timing control unit (120), a data driving unit (140), a power supply unit (180), and a gate driving unit (130) are formed within the display panel (PAN). In particular, a non-display area (NA) of the display panel (PAN) includes a bending area (BA). The display panel (PAN) can be folded at the bending area (BA) to reduce the bezel.

[0042] The image processing unit (110) outputs a driving signal for driving various devices along with image data supplied from the outside.

[0043] The degradation compensation unit (150) modulates the input image data (Idata) of each sub-pixel (SP) of the current frame based on the sensing voltage (Vsen) supplied from the data driving unit (140), and then supplies the modulated image data (Mdata) to the timing control unit (120).

[0044] The timing control unit (120) generates and outputs a gate timing control signal (GDC) for controlling the operation timing of the gate driving unit (130) and a data timing control signal (DDC) for controlling the operation timing of the data driving unit (140) based on a driving signal input from the image processing unit (110).

[0045] The gate driver (130) outputs a scan signal to a display panel (PAN) in response to a gate timing control signal (GDC) supplied from the timing control unit (120). The gate driver (130) outputs a scan signal through a plurality of gate lines (GL1~GLm). In particular, the gate driver (130) may be configured as a GIP (Gate In Panel) structure formed by directly stacking thin-film transistors on a substrate inside the organic electroluminescent display device (100). The GIP may include a plurality of circuits such as a shift register and a level shifter.

[0046] The data driving unit (140) outputs a data voltage to a display panel (PAN) in response to a data timing control signal (DDC) input from the timing control unit (120). The data driving unit (140) outputs the data voltage through a plurality of data lines (DL1~DLn).

[0047] The power supply unit (180) outputs a high-potential driving voltage (EVDD) and a low-potential driving voltage (EVSS), etc., and supplies them to the display panel (PAN). The high-potential driving voltage (VDD) and the low-potential driving voltage (EVSS) are supplied to the display panel (PAN) through the power line.

[0048] The display panel (PAN) displays an image in response to the data voltage and scan signal supplied from the data driver (140) and gate driver (130) which can be placed in the non-display area (NA), and the power supplied from the power supply unit (180).

[0049] The display area (AA) of the display panel (PAN) is composed of a plurality of sub-pixels (SP) to display an actual image. The sub-pixels (SP) include red, green, and blue sub-pixels, or include white (W), red (R), green (G), and blue (B) sub-pixels. In this case, the W, R, G, and B sub-pixels (SP) may all be formed with the same area, but may also be formed with different areas.

[0050] In the memory (160), not only is a lookup table for the degradation compensation gain stored, but the degradation compensation time of the organic light-emitting element of the sub-pixel (SP) is also stored. At this time, the degradation compensation time of the organic light-emitting element may be the number of driving cycles or driving time of the organic light-emitting display panel.

[0051] Meanwhile, as shown in FIG. 2, one sub-pixel (SP) can be connected to a gate line (GL1), a data line (DL1), a sensing voltage read-out line (SRL1), and a power line (PL1). The number of transistors and capacitors and, of course, the driving method of the sub-pixel (SP) are determined according to the circuit configuration.

[0052] FIG. 3 is a circuit diagram showing a sub-pixel (SP) of a display device (100) according to the present invention.

[0053] As illustrated in FIG. 3, the display device (100) according to the present invention includes a gate line (GL), a data line (DL), a power line (PL), and a sensing line (SL) that intersect to define a sub-pixel (SP), and the sub-pixel (SP) includes a driving thin-film transistor (DT), a light-emitting element (D), a storage capacitor (Cst), a first switching thin-film transistor (ST), and a second switching thin-film transistor (ST2).

[0054] The light-emitting element (D) may include an anode electrode connected to a second node (N2), a cathode electrode connected to an input terminal of a low potential driving voltage (EVSS), and an organic light-emitting layer located between the anode electrode and the cathode electrode.

[0055] The driving thin-film transistor (DT) controls the current (Id) flowing through the light-emitting element (D) according to the gate-source voltage (Vgs). The driving thin-film transistor (DT) comprises a gate electrode connected to a first node (N1), a drain electrode connected to a power line (PL) to provide a high potential driving voltage (EVDD), and a source electrode connected to a second node (N2).

[0056] The above storage capacitor (Cst) is connected between the first node (N1) and the second node (N2).

[0057] The first switch thin-film transistor (ST1) responds to a gate signal (SCAN) when driving a display panel (PAN) and applies a data voltage (Vdata) charged in the data line (DL) to the first node (N1) to turn on the driving thin-film transistor (DT). At this time, the first switch thin-film transistor (ST1) is equipped with a gate electrode connected to the gate line (GL) to receive the scan signal (SCAN), a drain electrode connected to the data line (DL) to receive the data voltage (Vdata), and a source electrode connected to the first node (N1). The first switch thin-film transistor (ST1) is known to operate more sensitively than other switch thin-film transistors within the pixel. Therefore, the first switch thin-film transistor (ST1) needs to increase its threshold voltage to facilitate control.

[0058] The second switch thin-film transistor (ST2) stores the source voltage of the second node (N2) in the sensing capacitor (Cx) of the sensing voltage read-out line (SRL) by switching the current between the second node (N2) and the sensing voltage read-out line (SRL) in response to the sensing signal (SEN). When driving the display panel (PAN), the second switch thin-film transistor (ST2) resets the source voltage of the driving thin-film transistor (DT) to the initialization voltage (Vpre) by switching the current between the second node (N2) and the sensing voltage read-out line (SRL) in response to the sensing signal (SEN). At this time, the gate electrode of the second switch thin-film transistor (ST2) is connected to the sensing line (SL), the drain electrode is connected to the second node (N2), and the source electrode is connected to the sensing voltage read-out line (SRL).

[0059] Meanwhile, although the drawing describes a display device with a 3T1C structure including three thin-film transistors and one storage capacitor, the display device of the present invention is not limited to this structure and can be applied to various pixel structures such as 4T1C, 5T1C, 6T1C, 7T1C, and 8T1C.

[0061] Meanwhile, FIG. 4a is a cross-sectional view illustrating, as a first embodiment of the present invention, a thin-film transistor (GT) for a gate driving circuit comprising a polycrystalline semiconductor pattern as a representative thin-film transistor disposed in a non-display area (NA), particularly in a GIP area, a driving thin-film transistor (DT) comprising an oxide semiconductor pattern disposed within a sub-pixel in a display area (AA) and driving a light-emitting element, a first switch thin-film transistor (ST-1) comprising an oxide semiconductor pattern, and a storage capacitor (Cst).

[0062] As shown in FIG. 4a, a driving thin-film transistor (DT) and a first switching thin-film transistor (ST-1) are disposed within a sub-pixel on a substrate (410). At this time, FIG. 4a shows only the driving thin-film transistor (DT) and one switching thin-film transistor (ST-1), but this is for convenience of explanation only, and multiple switching thin-film transistors may be disposed on the actual substrate (410).

[0063] Additionally, a plurality of thin-film transistors (GT) for gate driving circuits constituting a gate driving unit may be disposed in a non-display area (NA), particularly a GIP area, on the substrate (410). The thin-film transistors (GT) for gate driving circuits may use a polycrystalline semiconductor pattern as an active layer.

[0064] In the first embodiment, a case is described where a gate driving thin film transistor (GT) including a polycrystalline semiconductor pattern is placed in a non-display area (NA), but a switching thin film transistor having the same structure as the gate driving circuit thin film transistor (GT) may be placed within a sub-pixel of the display area.

[0065] However, the thin-film transistor (GT) for the gate driving circuit placed in the non-display area and the switching thin-film transistor placed in the display area may be configured differently, such as an N-TYPE thin-film transistor or a P-TYPE thin-film transistor, because the types of impurities doped in them are different.

[0066] Meanwhile, it is also possible for a plurality of thin-film transistors placed in the gate driving section to be composed of a CMOS in which a thin-film transistor for a gate driving circuit having a polycrystalline semiconductor pattern and a switching thin-film transistor having an oxide semiconductor pattern form a pair with each other.

[0067] Below, a thin-film transistor for a gate driving circuit using a polycrystalline semiconductor pattern as the active layer is described as an example placed in a non-display area (NA).

[0068] A thin-film transistor (GT) for a gate driving circuit comprises a polycrystalline semiconductor pattern (414) disposed on a lower buffer layer (411) formed on a substrate (410), a first gate insulating layer (442) insulating the polycrystalline semiconductor pattern (414), a first gate electrode (416) disposed on the first gate insulating layer (442) and overlapping with the polycrystalline semiconductor pattern (414), a plurality of insulating layers formed on the first gate electrode (416), and a first source electrode (417S) and a first drain electrode (417D) disposed on the plurality of insulating layers.

[0069] The substrate (410) may be composed of a multi-layer in which an organic film and an inorganic film are alternately stacked. For example, the substrate (410) may be composed of an organic film such as polyimide and an inorganic film such as silicon oxide (SiO2) stacked alternately.

[0070] A lower buffer layer (411) is formed on a substrate (410). The lower buffer layer (411) is intended to block moisture and the like that may penetrate from the outside, and can be formed by depositing at least one layer of an inorganic insulating layer such as silicon oxide (SiO2).

[0071] A polycrystalline semiconductor pattern (414) is formed on the lower buffer layer (411). The polycrystalline semiconductor pattern (414) is used as an active layer of a thin-film transistor. The polycrystalline semiconductor pattern (414) includes a first channel region (414C) and a first source region (414S) and a first drain region (414D) facing each other with the first channel region (414C) in between.

[0072] The polycrystalline semiconductor pattern (414) is insulated by a first gate insulating layer (442). The first gate insulating layer (442) is formed by depositing at least one layer of an inorganic insulating layer, such as silicon oxide (SiO2), on the entire surface of the substrate (410) on which the polycrystalline semiconductor pattern (414) is formed. The first gate insulating layer (442) protects and insulates the polycrystalline semiconductor pattern (414) from the outside.

[0073] A first gate electrode (416) is formed on the first gate insulating layer (442) that overlaps with the first channel region (414C) of the polycrystalline semiconductor pattern (414).

[0074] The first gate electrode (416) may be composed of a metallic material. For example, the first gate electrode (416) may be a single layer or multiple layers made of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof, but is not limited thereto.

[0075] A plurality of insulating layers may be formed between the first gate electrode (416), the first source electrode (417S), and the first drain electrode (417D).

[0076] Referring to FIG. 4a, the plurality of insulating layers may include an upper buffer layer (443) in contact with the upper surface of the first gate electrode (416), a second interlayer insulating layer (444) and a third interlayer insulating layer (445) sequentially stacked thereon.

[0077] The first source electrode (417S) and the first drain electrode (417D) are disposed on the third interlayer insulating layer (445). The first source electrode (417S) and the first drain electrode (417D) are connected to the polycrystalline semiconductor pattern (414) through the first contact hole (CH1) and the second contact hole (CH2), respectively. The first contact hole (CH1) and the second contact hole (CH2) penetrate the first gate insulating layer (442), the upper buffer layer (443), the second interlayer insulating layer (444), and the third interlayer insulating layer (445) to expose the first source region (414b) and the first drain region (414c) of the polycrystalline semiconductor pattern (414).

[0078] Meanwhile, a driving thin-film transistor (DT), a first switching thin-film transistor (ST-1), and a storage capacitor (Cst) are disposed in the sub-pixel of the display area (AA).

[0079] In the first embodiment, the driving thin-film transistor (DT) and the first switch thin-film transistor (ST-1) use an oxide semiconductor pattern as the active layer.

[0080] The driving thin-film transistor (DT) includes a first oxide semiconductor pattern (474), a second gate electrode (478) that overlaps with the first oxide semiconductor pattern (474), a second source electrode (479S), and a second drain electrode (479D).

[0081] Oxide semiconductors can be composed of oxides of metals such as zinc (Zn), indium (In), gallium (Ga), tin (Sn), and titanium (Ti), or combinations of metals such as zinc (Zn), indium (In), gallium (Ga), tin (Sn), and titanium (Ti) and their oxides. More specifically, oxide semiconductors may include zinc oxide (ZnO), zinc-tin oxide (ZTO), zinc-indium oxide (ZIO), indium oxide (InO), titanium oxide (TiO), indium-gallium-zinc oxide (IGZO), indium-zinc-tin oxide (IZTO), etc.

[0082] Generally, polycrystalline semiconductor patterns advantageous for high-speed operation are used as the active layer of driving thin-film transistors. However, driving thin-film transistors containing polycrystalline semiconductor patterns may experience power consumption issues due to leakage current occurring in the off state. In particular, the problem of leakage current occurring in the off state becomes more problematic during low-speed operation when a display device displays a still image, such as a document screen. Accordingly, the first embodiment of the present invention proposes a driving thin-film transistor that uses an oxide semiconductor pattern as the active layer, which is advantageous for blocking the occurrence of leakage current.

[0083] However, when a thin-film transistor uses an oxide semiconductor pattern as the active layer, due to the material properties of the oxide semiconductor, the current variation value relative to the voltage variation value is large, and defects often occur in the low-gradation region where precise current control is required. Therefore, in the first embodiment, a structure of a driving thin-film transistor is proposed in which the current variation value relative to the voltage variation value applied to the gate electrode is relatively insensitive.

[0084] Referring to FIGS. 4a to 4c, the structure of the driving thin-film transistor is examined. FIG. 4b is an enlarged cross-sectional view of only the driving thin-film transistor (DT) in FIG. 4a, and FIG. 4c is a circuit diagram showing the relationship between parasitic capacitances occurring inside the driving thin-film transistor (DT).

[0085] The driving thin-film transistor (DT) comprises a first oxide semiconductor pattern (474) located on an upper buffer layer (443), a second gate electrode (478) overlapping with the first oxide semiconductor pattern (474) below the first oxide semiconductor pattern (474), a second interlayer insulating layer (444) covering the first oxide semiconductor pattern (474), a first light-blocking pattern (BSM-1) formed on the second interlayer insulating layer (444) and overlapping with the first oxide semiconductor pattern (474), a third interlayer insulating layer (445) covering the first light-blocking pattern (BSM-1), and a second source electrode (479S) and a second drain electrode (479D) disposed on the third interlayer insulating layer (445).

[0086] In particular, the second gate electrode (478) may include a conductive semiconductor material layer. That is, the second gate electrode (478) can be used as the second gate electrode (478) by doping the semiconductor material layer with impurity ions to make it conductive and then patterning it.

[0087] In the first embodiment, the semiconductor material layer may be made conductive by injecting P-type impurities, such as boron ions, into the semiconductor material.

[0088] Additionally, the second gate electrode (478) may be composed of a single layer of conductive semiconductor material as shown in FIG. 4a, but may be a plurality of layers in which a conductive material layer, such as a metal pattern, and a conductive semiconductor material layer are stacked in sequence as shown in FIG. 5.

[0089] Generally, oxide semiconductors are N-type semiconductor materials. Therefore, if P-type impurity ions are injected into the second gate electrode (478) placed below the first N-type oxide semiconductor pattern (474) to form a P-type semiconductor pattern, the Fermi level of the second gate electrode (478) is lowered, and thus the Fermi level of the first oxide semiconductor pattern (474) is also lowered to achieve Fermi level equilibrium in a thermal equilibrium state. Consequently, the threshold voltage of the driving thin-film transistor (DT) using the first oxide semiconductor pattern (474) as the active layer increases.

[0090] Conversely, if N-type impurities are injected into the second gate electrode (478) to form a gate electrode containing an N-type semiconductor pattern, the threshold voltage of the driving thin-film transistor (DT) is lowered. Using this principle, in the first embodiment of the present invention, the threshold voltage of the driving thin-film transistor (DT) can be increased due to the second gate electrode (478) containing a P-type semiconductor material layer.

[0091] The semiconductor material layer included in the second gate electrode (478) can be a semiconductor material layer of various types, such as an amorphous semiconductor material, a polycrystalline semiconductor material, or an oxide semiconductor material.

[0092] The driving thin-film transistor (DT) requires a very high threshold voltage in design compared to other switching thin-film transistors in the pixel. While a typical switching thin-film transistor has a threshold voltage close to 0 volts, the driving thin-film transistor (DT) requires a threshold voltage of 1 volt or higher. Therefore, the driving thin-film transistor (DT) of the present invention has the advantage of being able to increase the threshold voltage by having a second gate electrode (478) comprising a P-type doped semiconductor material layer under the first oxide semiconductor pattern (474).

[0093] In the first embodiment of the present invention with reference to FIG. 4a, the manufacturing process can be shortened by having the second gate electrode (478) include a semiconductor material layer and be placed on the same layer as the polycrystalline semiconductor pattern (414). Accordingly, in the first embodiment of the present invention, the second gate electrode (478) may be composed of the same semiconductor material as the polycrystalline semiconductor pattern (414) and may be doped with p-type impurities.

[0094] FIG. 4d is a cross-sectional view illustrating the process in which a second gate electrode (478) is formed simultaneously on the same layer as a polycrystalline semiconductor pattern (414) and becomes conductive, and is composed of a single layer of semiconductor material.

[0095] Referring to FIG. 4d, a polycrystalline semiconductor layer is deposited on a lower buffer layer (411), and then a polycrystalline semiconductor pattern (414) and a second gate electrode (478) and a third gate electrode (433) composed of a polycrystalline semiconductor material are formed. Subsequently, a first gate insulating layer (442) is deposited on the entire surface of the substrate, and then a metal material layer is deposited and patterned thereon to form a first gate electrode (416) and a first electrode (450A) of a storage capacitor. Then, the first gate electrode (416) is used as a self-align mask for ion implantation to conduct the first source region (414S) and the first drain region (414D), while simultaneously conducting the second gate electrode (478) and the third gate electrode (433) composed of a polycrystalline semiconductor material. Therefore, in the first embodiment, the gate driving thin film transistor (GT) may be a P-type thin film transistor.

[0096] As another embodiment, the second gate electrode (478) may be composed of a stack of a metal pattern layer and a semiconductor material layer, rather than a single layer composed of a semiconductor material layer.

[0097] Referring to FIG. 5, the second gate electrode (478) may be in the form of a stack of a first layer (478a) of a metal pattern and a second layer (478b) of a semiconductor material layer.

[0098] Even if the second gate electrode (478) is in the form of a stack of the first layer (478a) of the metal pattern and the second layer (478b) of the semiconductor material layer, if a halftone mask is used, the second gate electrode (478) can be formed simultaneously on the same layer as the polycrystalline semiconductor pattern (414).

[0099] For reference, in FIGS. 4a and FIGS. 5, the first light-blocking pattern (BSM-1) may be in the form of a stack of a semiconductor material layer and a metal pattern, but for convenience of explanation, it is shown as a single layer of the metal pattern.

[0100] Meanwhile, a first light-blocking pattern (BSM-1) is formed on the upper portion of the first oxide semiconductor pattern (474). The first light-blocking pattern (BSM-1) prevents light entering from the outside from being irradiated onto the first oxide semiconductor pattern (474), thereby preventing the first oxide semiconductor pattern (474), which is sensitive to external light, from malfunctioning.

[0101] The first light-blocking pattern (BSM-1) is placed on the first oxide semiconductor pattern (474) and is positioned to partially overlap with the first oxide semiconductor pattern (474). Additionally, the first light-blocking pattern (BSM-1) is electrically connected to either the second source electrode (479S) or the second drain electrode (479D).

[0102] The first light-blocking pattern (BSM-1) protects the first oxide semiconductor pattern (474) from hydrogen particles that may enter from the top of the first oxide semiconductor pattern (474). Accordingly, the first light-blocking pattern (BSM-1) may include a titanium (Ti) material that has the ability to capture hydrogen particles. For example, the first light-blocking pattern (BSM-1) may be a titanium single layer, a multilayer of molybdenum (Mo) and titanium (Ti), or an alloy of molybdenum (Mo) and titanium (Ti). However, it is not limited thereto, and other metal layers containing titanium (Ti) are also possible.

[0103] When the first light-blocking pattern (BSM-1) is connected to either the second source electrode (479S) or the second drain electrode (479D), the following additional effects can be obtained. (For convenience of explanation, it is described as being connected to the second source electrode (479S).)

[0104] This will be explained with reference to FIGS. 4b and FIGS. 4c.

[0105] FIG. 4b is a cross-sectional view showing only the driving thin-film transistor (DT) separated from FIG. 4a. FIG. 4c is a circuit diagram showing the relationship between the parasitic capacitance occurring in the driving thin-film transistor (DT) and the applied voltage.

[0106] Referring to FIG. 4b, as the second source region (474S) and the second drain region (474D) of the first oxide semiconductor pattern (474) become conductive, the parasitic capacitance C within the first oxide semiconductor pattern (474) act It occurs. And Parasitic capacitance C between the second gate electrode (478) and the first oxide semiconductor pattern (474) gi A parasitic capacitance C occurs between the first light-blocking pattern (BSM-1) and the first oxide semiconductor pattern (474). buf It occurs.

[0107] The first oxide semiconductor pattern (474) and the first light-blocking pattern (BSM-1) are electrically connected by the second source electrode (479S) so that the parasitic capacitance C act and parasitic capacitance C buf They are connected in parallel with each other, and the parasitic capacitance C act and parasitic capacitance C gi are connected in series. Also, V on the second gate electrode (478) gat of When a gate voltage is applied, the effective voltage V applied to the actual first oxide semiconductor pattern (474) eff Formula 1 below holds true.

[0108] [Formula 1]

[0109]

[0111] Accordingly, the effective voltage applied to the channel of the first oxide semiconductor pattern (474) is the parasitic capacitance C buf Parasitic capacitance C in an inverse relationship with buf The effective voltage applied to the first oxide semiconductor pattern (474) can be controlled by adjusting it.

[0112] That is, by placing the first light-blocking pattern (BSM-1) near the first oxide semiconductor pattern (474), the parasitic capacitance C buf Increasing the value can reduce the actual current flowing through the first oxide semiconductor pattern (474).

[0113] The reduction in the effective current value flowing through the first oxide semiconductor pattern (474) means that the voltage V applied to the actual second gate electrode (478) is reduced. gat This means that the control range of the driving thin-film transistor (DT) that can be controlled through this is widened. In addition, this means an increase in the s-factor. For reference, the s-factor is the reciprocal of the change in current due to the change in gate voltage in the on-off transition region of the thin-film transistor.

[0114] Accordingly, in the first embodiment of the present invention, if the first light-blocking pattern (BSM-1) is positioned closer to the first oxide semiconductor pattern (474), the range in which the driving thin-film transistor (DT) controls the gradation is widened. As a result, the light-emitting element can be precisely controlled even at low gradations, thereby solving the problem of screen stains that frequently occur at low gradations.

[0115] Therefore, in this embodiment, the parasitic capacitance C buf The value is parasitic capacitance C gi It can be larger than the value.

[0116] Accordingly, the driving thin-film transistor (DT) of the present invention can provide a driving thin-film transistor that allows for free expression of gradation even at low gradations due to the first light-blocking pattern (BSM-1), and can implement a driving thin-film transistor with a higher threshold voltage due to the second gate electrode (478) which is conducted in a P-type.

[0117] Meanwhile, with reference to FIGS. 4a and FIGS. 5, the advantages that can be obtained when the first light-blocking pattern (BSM-1) is a metal pattern and is electrically connected to the second source electrode (479S) have been explained.

[0118] However, as another embodiment, as shown in FIG. 6, the same effect as above can be obtained even if the first light-blocking pattern (BSM-1) is not a metal pattern but a semiconductor material layer that is doped with impurities and made conductive.

[0119] FIG. 6 discloses a case where the first light-blocking pattern (BSM-1) is a conductive semiconductor material layer rather than a metal pattern. Along with the first light-blocking pattern (BSM-1), the second light-blocking pattern (BSM-2) disposed on the same layer as the first light-blocking pattern (BSM-1) and the second electrode (450B) of the storage capacitor may also be conductive semiconductor material layers.

[0120] Furthermore, when the first light-blocking pattern (BSM-1) is a semiconductor material layer that is P-type conductive, the Fermi level of the first light-blocking pattern decreases, and the Fermi level of the first oxide semiconductor pattern (474) corresponding to it also decreases to achieve equilibrium in a thermal equilibrium state with the first light-blocking pattern (BSM-1). As a result, the threshold voltage for turning on the first switching thin-film transistor can be increased.

[0121] Although the first light-blocking pattern (BSM-1) disclosed in FIG. 6 is shown as a single layer of semiconductor material, with reference to FIG. 7, the first light-blocking pattern (BSM-1) may be in a stacked form of a metal material layer and a semiconductor material layer. When the first light-blocking pattern (BSM-1) is composed of multiple layers, the first light-blocking pattern (BSM-1) may have a structure in which a first layer (BSM-1a) of the first light-blocking pattern composed of a semiconductor material layer and a second layer (BSM-1b) of the first light-blocking pattern composed of a metal material are stacked in sequence so that the semiconductor material layer is positioned close to the first oxide semiconductor pattern (474).

[0122] Referring to FIG. 7, the second light-blocking pattern (BSM-2) formed of the same material on the same layer as the first light-blocking pattern (BSM-1) and the second electrode (450B) of the storage capacitor may also be configured such that a semiconductor material layer and a metal material layer are stacked in sequence.

[0123] Additionally, referring to FIG. 7, if the second gate electrode (478) and the third gate electrode (433) are formed as a single layer of metal material, the number of mask processes can be reduced by simultaneously forming them with the same material on the same layer as the first gate electrode (416).

[0125] Meanwhile, referring to FIG. 4a, the first switching thin film transistor (ST-1) includes a second oxide semiconductor pattern (432) formed on an upper buffer layer (443), a third gate electrode (433) disposed below the second oxide semiconductor pattern (432), a second light-blocking pattern (BSM-2) disposed above the second oxide semiconductor pattern (432), a second interlayer insulating layer (444) interposed between the second oxide semiconductor pattern (432) and the second light-blocking pattern (BSM-2), a third interlayer insulating layer (445) covering the second light-blocking pattern (BSM-2), and a third source electrode (434S) and a third drain electrode (434D) formed on the third interlayer insulating layer (445).

[0126] The second oxide semiconductor pattern (432) includes a third channel region (432C) and a third source region (432S) and a third drain region (432D) disposed on both sides of the third channel region (432C).

[0127] The third source electrode (434S) and the third drain electrode (434D) are connected to the third source region (432S) and the third drain region (432D) respectively through the sixth contact hole (CH6) and the seventh contact hole (CH7).

[0128] In particular, the second gate electrode (433) and the second light-blocking pattern (BSM-2) are each placed below and above the second oxide semiconductor pattern (432) to protect the oxide semiconductor pattern from light that may enter the oxide semiconductor pattern, as well as to increase the threshold voltage of the first switching thin film transistor (ST-1).

[0129] The third gate electrode (433) may include a semiconductor material layer that is conductive in the P-type. Accordingly, as the third gate electrode (433) is conductive by the injection of P-type impurities, the Fermi level is lowered, and the Fermi level of the corresponding second oxide semiconductor pattern (432) is also lowered, and as a result, the threshold voltage of the first switching thin film transistor (ST-1) is raised. In particular, referring to FIG. 3, a significant effect can be achieved when the first switching thin film transistor (ST-1) is a sampling transistor connected to the gate node of the driving thin film transistor (DT). The sampling transistor serves to provide a data voltage to one electrode of the storage capacitor during the sampling interval.

[0130] Sampling transistors are known to be highly sensitive transistors with a low threshold voltage, allowing the channel to open even at low voltages. In the first embodiment of the present invention, the first switching thin film transistor (ST-1) has a third gate electrode (433) comprising a semiconductor material layer doped with P-type ions placed below the second oxide semiconductor pattern (432), which has the advantage of increasing the threshold voltage of the first switching thin film transistor (ST-1) and, as a result, increasing the degree of freedom in configuring the internal compensation circuit.

[0131] Additionally, referring to FIG. 5, the third gate electrode (433) may be a plurality of layers including a semiconductor material layer that is P-type conductive. For example, the third gate electrode (433) may be composed of a plurality of layers in which a first layer (433a), which is a conductive metal material layer, and a second layer (433b), which is a semiconductor material layer that is P-type conductive, are stacked in sequence.

[0132] In addition, the second light-blocking pattern (BSM-2) may also be composed of a single layer of conductive semiconductor material or a plurality of layers, such as a stack of a semiconductor material layer and a metal material layer. That is, referring to FIG. 6, the second light-blocking pattern (BSM-2) may be a single layer of conductive semiconductor material, or, as disclosed in FIG. 7, a plurality of layers in which a single layer of conductive semiconductor material (BSM-2a) and a second layer of conductive metal material (BSM-2b) are stacked in sequence.

[0133] In order to lower the Fermi level of the second oxide semiconductor pattern (432), it is preferable that the semiconductor material layers of the third gate electrode (433) and the second light-blocking pattern (BSM-2) are each stacked close to the second oxide semiconductor pattern (432). Accordingly, the third gate electrode (433) may have a configuration in which a metal material layer and a semiconductor material layer are stacked in sequence, and the second light-blocking pattern (BSM-2) may have a configuration in which a semiconductor material layer and a metal material layer are stacked in sequence.

[0134] Meanwhile, the third gate electrode (433) and the second light-blocking pattern (BSM-2) are electrically connected to each other, so that the first switching thin film transistor (ST-1) may be a switching thin film transistor with a double gate structure.

[0135] In addition, the polycrystalline semiconductor pattern (414), the second gate electrode (478), and the third gate electrode (433) can be placed on the same layer and formed simultaneously using a single mask. That is, there is an advantage in that the mask process can be reduced.

[0136] Additionally, the first source electrode (417S), the first drain electrode (417D), the second source electrode (479S), the second drain electrode (479D), the third source electrode (434S), and the third drain electrode (434D) can be disposed on the same layer. That is, the source electrodes and the drain electrodes can all be disposed on the third interlayer insulating layer (445). Accordingly, the source electrodes and the drain electrodes can be formed simultaneously using a single mask, which has the advantage of reducing the mask process.

[0138] Meanwhile, referring to FIG. 4a, the sub-pixel includes a storage capacitor (Cst).

[0139] The storage capacitor (Cst) stores the data voltage applied through the data line for a certain period and then provides it to the organic light-emitting diode.

[0140] A storage capacitor (Cst) comprises two corresponding electrodes and a dielectric placed between them. The storage capacitor (Cst) includes a first electrode (450A) of the storage capacitor placed on the same layer as the first gate electrode (416) and a second electrode (450B) of the storage capacitor that overlaps with the first electrode (450A) of the storage capacitor and may be composed of the same material on the same layer as the first light-blocking pattern (BSM-1).

[0141] An upper buffer layer (443) and a second interlayer insulating layer (444) may be interposed between the first electrode (450A) of the storage capacitor and the second electrode (450B) of the storage capacitor.

[0142] The second electrode (450B) of the storage capacitor can be electrically connected to the second source electrode (479S) through the eighth contact hole (CH8).

[0144] Meanwhile, referring to FIG. 4a, a first planarization layer (PLN1) may be formed on a substrate (410) on which a driving thin film transistor (DT) and a first switch thin film transistor (ST-1) are placed.

[0145] Although not disclosed in the drawings, a passivation layer of the inorganic film may be further deposited before the first planarization layer (PLN1) is deposited.

[0146] The first planarization layer (PLN1) may be formed of an organic material such as photoacrylic, but may also be composed of multiple layers consisting of an inorganic layer and an organic layer. A connecting electrode (445) is formed on the first planarization layer (PLN1). The connecting electrode (445) electrically connects the anode electrode (456), which is a component of the light-emitting element part (460), and the driving thin-film transistor (DT) through a ninth contact hole (CH9) formed within the first planarization layer (PLN1).

[0147] Additionally, the conductive film used to form the connecting electrode (455) can constitute part of the various link wirings placed in the bending region (BA).

[0148] A second flattening layer (PLN2) may be formed on the connecting electrode (455). The second flattening layer (PLN2) may be formed from an organic material such as photoacrylic, like the first flattening layer (PLN1), but may also be composed of multiple layers consisting of an inorganic layer and an organic layer.

[0149] An anode electrode (456) is formed on the second flattening layer (PLN2). The anode electrode (456) is electrically connected to a connecting electrode (455) through a tenth contact hole (CH10) formed within the second flattening layer (PLN2).

[0150] The above anode electrode (456) is made of a single layer or multiple layers of metals such as Ca, Ba, Mg, Al, Ag, etc. or alloys thereof, and is connected to the second drain electrode (479D) of the driving thin-film transistor (DT) so that an image signal is applied from the outside.

[0151] In addition to the anode electrode (456), the non-display area (NA) may further be provided with an anode connecting electrode (457) that electrically connects the common voltage wiring (VSS) and the cathode electrode (463).

[0152] A bank layer (461) is formed on the second flattening layer (PLN2). The bank layer (461) acts as a partition to divide each sub-pixel, thereby preventing light of a specific color output from adjacent sub-pixels from being mixed and output.

[0153] An organic light-emitting layer (462) is formed on the surface of the anode electrode (456) and on a portion of the inclined surface of the bank layer (461). The organic light-emitting layer (462) may be an R-organic light-emitting layer that emits red light, a G-organic light-emitting layer that emits green light, and a B-organic light-emitting layer that emits blue light, formed in each sub-pixel. Additionally, the organic light-emitting layer (461) may be a W-organic light-emitting layer that emits white light.

[0154] The above organic light-emitting layer (462) may include not only a light-emitting layer but also an electron injection layer and a hole injection layer that respectively inject electrons and holes into the light-emitting layer, and an electron transport layer and a hole transport layer that respectively transport the injected electrons and holes into the organic layer.

[0155] A cathode electrode (463) is formed on the organic light-emitting layer (462). The cathode electrode (463) may be made of a transparent conductive material such as ITO (Indium Tin Oxide) or IZO (Indium Zinc Oxide) or a thin metal that transmits visible light, but is not limited thereto.

[0156] A sealing layer portion (470) is formed on the cathode electrode (463). The sealing layer (470) may be composed of a single layer of an inorganic layer, a two-layer structure of an inorganic layer and an organic layer, or a three-layer structure of an inorganic layer, an organic layer, and an inorganic layer. The inorganic layer may be composed of inorganic materials such as SiNx and SiX, but is not limited thereto. Additionally, the organic layer may be composed of organic materials such as polyethylene terephthalate, polyethylene naphthalate, polycarbonate, polyimide, polyethylene sulfonate, polyoxymethylene, and polyarylate, or a mixture thereof, but is not limited thereto.

[0157] In FIG. 4a, as an example of the bag layer portion (470), it is disclosed that it is composed of three layers: an inorganic layer (471), an organic layer (472), and an inorganic layer (473).

[0158] A cover glass (not shown) is placed on the above-mentioned bag layer portion (470) and can be attached by an adhesive layer (not shown in the drawing). Any material with good adhesion, heat resistance, and water resistance can be used as the adhesive layer, but in the present invention, a thermosetting resin such as an epoxy compound, an acrylate compound, or an acrylic rubber can be used. Additionally, a photocurable resin may be used as the adhesive, in which case the adhesive layer is cured by irradiating the adhesive layer with light such as ultraviolet light.

[0159] The adhesive layer can not only bond the substrate (410) and the cover glass (not shown) but also serve as a sealant to prevent moisture from penetrating into the organic electroluminescent display device.

[0160] The above cover glass (not shown) is an encapsulation cap for encapsulating an organic light-emitting display device, and may use a protective film such as a PS (Polystyrene) film, PE (Polyethylene) film, PEN (Polyethylene Naphthalate) film or PI (Polyimide) film, or may use glass.

[0161] The foregoing description and the attached drawings are merely illustrative of the technical concept of the present invention, and those skilled in the art to which the present invention pertains will be able to make various modifications or variations, such as combining, separating, substituting, and changing the components, within the scope of the essential characteristics of the present invention. Accordingly, the embodiments disclosed in the present invention are intended to explain, not limit, the technical concept of the present invention, and the scope of the technical concept of the present invention is not limited by such embodiments. The scope of protection of the present invention shall be interpreted by the claims below, and all technical concepts within an equivalent scope shall be interpreted as being included within the scope of rights of the present invention. Explanation of the symbols

[0162] GT: Thin-film transistor for gate driving DT: Driving thin-film transistor ST-1, ST-2: Switch thin-film transistors BSM-1. BSM-2: Light-blocking patterns 416, 478, 433: Gate electrodes 474, 432: Oxide semiconductor patterns 417S, 479S, 434S: Source electrode 417D, 479D, 434D: Drain electrodes 456: Anode electrode 462: Organic light-emitting layer 463: Cathode electrode 430: Pixel circuit part 460: Light-emitting element part 470: Bag layer part

Claims

Claim 1 A substrate comprising a display area and a non-display area disposed around the display area; and a first thin-film transistor, a third thin-film transistor, and a storage capacitor disposed on the substrate, wherein the first thin-film transistor comprises: a first oxide semiconductor pattern disposed on the substrate; a first gate electrode disposed below the first oxide semiconductor pattern and overlapping with the first oxide semiconductor pattern; and a first source electrode and a first drain electrode connected to the first oxide semiconductor pattern on the first oxide semiconductor pattern. A thin film transistor array substrate comprising: a first light-blocking pattern that overlaps with the first oxide semiconductor pattern on the upper surface of the first oxide semiconductor pattern and is connected to either the first source electrode and the first drain electrode; wherein the third thin film transistor comprises a polycrystalline semiconductor pattern disposed on the substrate; a third gate electrode that overlaps with the polycrystalline semiconductor pattern on the polycrystalline semiconductor pattern; and a third source electrode and a third drain electrode connected to the polycrystalline semiconductor pattern on the polycrystalline semiconductor pattern; and wherein the storage capacitor comprises a first electrode of the storage capacitor disposed on the same layer as the third gate electrode and a second electrode of the storage capacitor disposed on the same layer as the first light-blocking pattern. Claim 2 A thin film transistor array substrate according to claim 1, wherein a second thin film transistor is further disposed on the substrate, and the second thin film transistor comprises: a second oxide semiconductor pattern disposed on the substrate; a second gate electrode overlapping with the second oxide semiconductor pattern below the second oxide semiconductor pattern; a second source electrode and a second drain electrode connected to the second oxide semiconductor pattern on the second oxide semiconductor pattern; and a second light-blocking pattern overlapping with the second oxide semiconductor pattern on the second oxide semiconductor pattern. Claim 3 In paragraph 2, at least one of the first gate electrode and the first light-blocking pattern comprises a semiconductor material layer, forming a thin-film transistor array substrate. Claim 4 In paragraph 2, at least one of the second gate electrode and the second light-blocking pattern comprises a semiconductor material layer, forming a thin-film transistor array substrate. Claim 5 In paragraph 3, at least one of the second gate electrode and the second light-blocking pattern comprises a semiconductor material layer, forming a thin-film transistor array substrate. Claim 6 delete Claim 7 A thin film transistor array substrate, wherein the first thin film transistor is a driving thin film transistor that drives a pixel of the display area, and the second thin film transistor is a switching thin film transistor disposed within the pixel. Claim 8 In claim 1, the thin film transistor array substrate is a switching thin film transistor disposed in at least one of the display area and the non-display area. Claim 9 A thin-film transistor array substrate according to any one of claims 3 to 5, wherein the semiconductor material layer is a P-type semiconductor material and the first oxide semiconductor pattern and the second oxide semiconductor pattern are n-type semiconductor materials. Claim 10 A thin-film transistor array substrate according to any one of claims 3 to 5, wherein the polycrystalline semiconductor pattern and the semiconductor material layer are p-type semiconductor materials, and the first oxide semiconductor pattern and the second oxide semiconductor pattern are n-type semiconductor materials. Claim 11 In paragraphs 3 to 5, at least one of the first gate electrode, the first light-blocking pattern, the second gate electrode, and the second light-blocking pattern is a thin-film transistor array substrate having a stacked structure of a metal pattern and a semiconductor material layer. Claim 12 In claim 11, a thin film transistor array substrate in which the light reflectance of the semiconductor material layer is smaller than the light reflectance of the metal pattern. Claim 13 delete Claim 14 In paragraph 2, the polycrystalline semiconductor pattern, the first gate electrode, and the second gate electrode are disposed on the same layer of a thin-film transistor array substrate. Claim 15 In paragraph 2, the first gate electrode, the second gate electrode, and the third gate electrode are arranged on the same layer of a thin-film transistor array substrate. Claim 16 In paragraph 2, the second gate electrode and the second light-blocking pattern are electrically connected to each other to form a double gate, forming a thin-film transistor array substrate. Claim 17 A thin film transistor array substrate according to claim 1, wherein the parasitic capacitance occurring between the first oxide semiconductor pattern and the first light-blocking pattern is greater than the parasitic capacitance occurring between the first oxide semiconductor pattern and the first gate electrode. Claim 18 A thin film transistor array substrate according to claim 1, wherein the distance between the first oxide semiconductor pattern and the first light-blocking pattern is smaller than the distance between the first oxide semiconductor pattern and the first gate electrode. Claim 19 In claim 10, the polycrystalline semiconductor pattern and the semiconductor material layer are composed of the same type of semiconductor material, forming a thin-film transistor array substrate. Claim 20 A thin film transistor array substrate according to claim 11, wherein the first gate electrode and the second gate electrode have a structure in which the metal pattern and the semiconductor material layer are stacked in sequence, and the first light-blocking pattern and the second light-blocking pattern have a structure in which the semiconductor material layer and the metal pattern are stacked in sequence. Claim 21 A display device comprising a thin film transistor array substrate according to any one of claims 1 to 5, 7 to 12, and 14 to 20, further comprising a light-emitting element portion connected to the first thin film transistor, wherein the light-emitting element portion comprises an anode electrode connected to the first drain electrode, a cathode electrode corresponding to the anode electrode, and an organic light-emitting layer disposed between the anode electrode and the cathode electrode.

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