Display Device and Driving Method of the same

Abstract

The present invention may provide a display device comprising: a first type subpixel emitting light and a second type subpixel not emitting light; a high potential voltage line connected to the first type subpixel and the second type subpixel and transmitting a high potential voltage; a low potential voltage line connected to the first type subpixel and the second type subpixel and transmitting a low potential voltage; and a circuit unit connected to the low potential voltage line, wherein the circuit unit senses the low potential voltage line when the second type subpixel operates and compensates a data signal to be supplied to the first type subpixel based on a sense value acquired through the sense.

Description

Technology Field

[0001] The present invention relates to a display device and a method for driving the same. Background Technology

[0002] As information technology advances, the market for display devices, which serve as a medium connecting users and information, is growing. Consequently, the use of display devices such as Light Emitting Display Devices (LEDs), Quantum Dot Display Devices (QDDs), and Liquid Crystal Display Devices (LCDs) is increasing.

[0003] The display devices described above include a display panel containing subpixels, a driving unit that outputs a driving signal for driving the display panel, and a power supply unit that generates power to be supplied to the display panel or the driving unit.

[0004] When driving signals, such as scan signals and data signals, are supplied to subpixels formed on a display panel, the selected subpixel transmits light or emits light directly, thereby displaying an image. The problem to be solved

[0005] The present invention senses the current or voltage flowing through a low-potential voltage line and compensates the data signal based on this to standardize the display quality across the entire display panel, while also minimizing the problem of display quality degradation that may be caused by resistance deviation. means of solving the problem

[0006] The present invention may provide a display device comprising: a first type subpixel emitting light and a second type subpixel not emitting light; a high potential voltage line connected to the first type subpixel and the second type subpixel and transmitting a high potential voltage; a low potential voltage line connected to the first type subpixel and the second type subpixel and transmitting a low potential voltage; and a circuit unit connected to the low potential voltage line, wherein the circuit unit senses the low potential voltage line when the second type subpixel operates and compensates a data signal to be supplied to the first type subpixel based on a sense value acquired through the sense.

[0007] The above-mentioned second type subpixel may have a structure in which the anode electrode layer and the cathode electrode layer included in the organic light-emitting diode are short-circuited.

[0008] The driving transistor of the above-mentioned second type subpixel can be turned on in response to a sensing data voltage and a dummy scan signal.

[0009] When the driving transistor included in the second type subpixel is turned on, the high potential voltage applied through the high potential voltage line can be transmitted to the low potential voltage line.

[0010] The above-mentioned second type subpixel is located on the non-display area of ​​the display panel and can be arranged in a line shape along the direction of the gate line.

[0011] The above circuit section can compensate the data signal in response to the change in the low potential voltage due to the influence of IR (current resistance) at each location of the display panel, based on the sensing value acquired through the low potential voltage line.

[0012] When the above circuit section is in a sensing operation, the low voltage applied through the low voltage line is blocked, and instead, the high voltage applied through the second type subpixel can be transmitted through the low voltage line.

[0013] In another aspect, the present invention may provide a method for driving a display device comprising a display panel including a first type subpixel that emits light and a second type subpixel that does not emit light, and a circuit unit that senses a low potential voltage line connected to the first type subpixel and the second type subpixel. The method for driving the display device may include the steps of: applying a sensing data voltage and a dummy scan signal to the second type subpixel; sensing the low potential voltage line connected to the first type subpixel and the second type subpixel; and compensating a data signal to be supplied to the first type subpixel based on a sensing value obtained through the low potential voltage line.

[0014] When the above circuit section is in a sensing operation, the low potential voltage applied through the low potential voltage line is blocked, and instead, the high potential voltage applied through the second type subpixel can be transmitted through the low potential voltage line.

[0015] The step of compensating the above data signal can compensate the data signal in response to the amount of change in the low potential voltage due to the influence of IR (current resistance) at each location of the display panel based on the above sensing value. Effects of the invention

[0016] The present invention has the effect of uniformizing the display quality of the entire display panel by detecting the amount of change in low-potential voltage due to the influence of IR (current resistance) at each location through a sensing method in which a high-potential voltage is applied to a low-potential voltage line through a subpixel that cannot emit light, and then compensating the data signal based on this. In addition, the present invention has the effect of minimizing the problem of display quality degradation that may be caused by resistance deviations due to process deviations, etc., by sensing the current or voltage flowing through the low-potential voltage line based on this. Brief explanation of the drawing

[0017] FIG. 1 is a block diagram schematically showing a light-emitting display device, FIG. 2 and FIG. 3 are drawings for explaining the configuration of a gate-in-panel type scan driving unit, and FIG. 4 is a module configuration diagram of the light-emitting display device. FIG. 5 is an example diagram of the circuit configuration of a subpixel according to the first embodiment of the present invention, and FIG. 6 is a configuration diagram of a subpixel of a display panel according to the first embodiment of the present invention. FIGS. 7 and 8 are drawings for explaining a sensing method of a low potential voltage line using a first type subpixel, a second type subpixel, and a sensing circuit unit according to a first embodiment of the present invention, FIG. 9 is a drawing for explaining the data voltage output sequence for sensing of a data driving unit according to a first embodiment of the present invention, and FIG. 10 is a drawing for explaining the sensing sequence of a low potential voltage line according to a first embodiment of the present invention. FIG. 11 is a drawing for explaining a data driving unit having a sensing circuit and a timing control unit having a compensation circuit according to a first embodiment of the present invention, and FIG. 12 and FIG. 13 are drawings for explaining the advantages of the first embodiment of the present invention. FIG. 14 is a drawing specifically showing a sensing circuit section according to a second embodiment of the present invention, FIG. 15 is a waveform diagram for explaining the operation of the sensing circuit section shown in FIG. 14 according to a second embodiment of the present invention, and FIG. 16 and FIG. 17 are drawings for explaining the sensing and compensation of a display panel according to a second embodiment of the present invention. FIGS. 18 to 20 are exemplary drawings showing the cross-sectional structure of a first type subpixel and a second type subpixel according to a third embodiment of the present invention. Specific details for implementing the invention

[0018] The display device according to the present specification may be implemented as a television, video player, personal computer (PC), home theater, automotive electrical system, smartphone, etc., but is not limited thereto. The display device according to the present specification may be implemented as a light-emitting display device (LED), a quantum dot display device (QDD), a liquid crystal display device (LCD), etc. However, for convenience of explanation, a light-emitting display device that directly emits light based on an inorganic light-emitting diode or an organic light-emitting diode is used as an example below.

[0019] In addition, the thin-film transistor described below may be implemented as an n-type thin-film transistor, a p-type thin-film transistor, or in a form where both n-type and p-type exist together. A thin-film transistor is a three-electrode device comprising a gate, a source, and a drain. The source is the electrode that supplies carriers to the transistor. Within the thin-film transistor, carriers begin to flow from the source. The drain is the electrode from which carriers exit the thin-film transistor. In other words, the flow of carriers in the thin-film transistor flows from the source to the drain.

[0020] In the case of a p-type thin-film transistor, since the carrier is a hole, the source voltage is higher than the drain voltage to allow holes to flow from the source to the drain. Because holes flow from the source to the drain in a p-type thin-film transistor, current flows from the source to the drain. In contrast, in the case of an n-type thin-film transistor, since the carrier is an electron, the source voltage is lower than the drain voltage to allow electrons to flow from the source to the drain. Because electrons flow from the source to the drain in an n-type thin-film transistor, the direction of the current flows from the drain to the source. However, the source and drain of a thin-film transistor can change depending on the applied voltage. Reflecting this, in the following description, either the source or the drain is described as the first electrode, and the other is described as the second electrode.

[0021] FIG. 1 is a block diagram schematically showing a light-emitting display device, FIG. 2 and FIG. 3 are drawings for explaining the configuration of a gate-in-panel type scan driving unit, and FIG. 4 is a module configuration diagram of the light-emitting display device.

[0022] As illustrated in FIG. 1, the light-emitting display device may include an image supply unit (110), a timing control unit (120), a scan driving unit (130), a data driving unit (140), a display panel (150), and a power supply unit (180), etc.

[0023] The video supply unit (set or host system) (110) can output various driving signals along with video data signals supplied from the outside or video data signals stored in internal memory. The video supply unit (110) can supply the data signals and various driving signals to the timing control unit (120).

[0024] The timing control unit (120) can output a gate timing control signal (GDC) for controlling the operation timing of the scan drive unit (130), a data timing control signal (DDC) for controlling the operation timing of the data drive unit (140), and various synchronization signals (Vsync, a vertical synchronization signal, Hsync, a horizontal synchronization signal). The timing control unit (120) can supply a data signal (DATA) supplied from the image supply unit (110) to the data drive unit (140) along with the data timing control signal (DDC). The timing control unit (120) may be formed in the form of an IC (Integrated Circuit) and mounted on a printed circuit board, but is not limited thereto.

[0025] The scan driver (130) can output a scan signal (or scan voltage) in response to a gate timing control signal (GDC) supplied from the timing control unit (120). The scan driver (130) can supply a scan signal to subpixels included in the display panel (150) through gate lines (GL1 to GLm). The scan driver (130) can be formed in the form of an IC or formed directly on the display panel (150) in a gate-in-panel manner, but is not limited thereto.

[0026] The data driver (140) can sample and latch a data signal (DATA) in response to a data timing control signal (DDC) supplied from the timing control unit (120), and convert the digital data signal into an analog data voltage based on a gamma reference voltage and output it. The data driver (140) can supply the data voltage to subpixels included in the display panel (150) through data lines (DL1 to DLn). The data driver (140) can be formed in the form of an IC and mounted on the display panel (150) or mounted on a printed circuit board, but is not limited thereto.

[0027] The power supply unit (180) can generate high voltage and low voltage based on an external input voltage supplied from the outside and output them through the high voltage line (EVDD) and the low voltage line (EVSS). The power supply unit (180) can generate and output not only the high voltage and low voltage, but also voltages required for driving the scan drive unit (130) (e.g., gate high voltage and gate low voltage) or voltages required for driving the data drive unit (140) (e.g., drain voltage and half-drain voltage).

[0028] The display panel (150) can display an image based on a driving signal including a scan signal and a data voltage, a high potential voltage, and a low potential voltage. The subpixels of the display panel (150) can emit light directly. The display panel (150) can be manufactured based on a substrate having rigidity or flexibility, such as glass, silicon, or polyimide. The subpixels emitting light can be composed of pixels including red, green, and blue, or pixels including red, green, blue, and white. For example, one subpixel (SP) can be connected to a first data line (DL1), a first gate line (GL1), a high potential voltage line (EVDD), and a low potential voltage line (EVSS).

[0029] Meanwhile, in the above description, the timing control unit (120), scan driving unit (130), and data driving unit (140) were described as being separate components. However, depending on the implementation method of the light-emitting display device, one or more of the timing control unit (120), scan driving unit (130), and data driving unit (140) may be integrated into a single IC.

[0030] As illustrated in FIGS. 2 and 3, the gate-in-panel type scan drive unit (130) may include a shift register (131) and a level shifter (135). The level shifter (135) can generate scan clock signals (Clks) and start signals (Vst), etc., based on signals and voltages output from the timing control unit (120) and the power supply unit (180).

[0031] The shift register (131) operates based on signals (Clks, Vst), etc., output from the level shifter (135) and can output scan signals (Scan[1] ~ Scan[m]) that can turn on or turn off the transistor formed on the display panel. The shift register (131) can be formed in the form of a thin film on the display panel by a gate-in-panel method.

[0032] Unlike the shift register (131), the level shifter (135) may be formed independently in the form of an IC or included inside the power supply (180). However, this is only one example and is not limited thereto.

[0033] As illustrated in FIG. 4, the display panel (150) may include a display area (AA) for displaying an image and a non-display area (NA) for not displaying an image. Subpixels (SP) may be located in the display area (AA). In the non-display area (NA), shift registers (131a, 131b) that output scan signals from a gate-in-panel type scan driver may be located.

[0034] The display panel (150) may be configured as a module by a plurality of data driving units (140a to 140n) mounted on a plurality of first circuit boards (141a to 141n) and a timing control unit (120) mounted on a single control board (125). The plurality of data driving units (140a to 140n) and the single timing control unit (120) may be electrically connected by at least two second circuit boards (145a to 145b) and at least two cables (121a to 121b), etc. The plurality of first circuit boards (141a to 141n) may be selected as flexible circuit boards, and at least two second circuit boards (145a to 145b) may be selected as printed circuit boards. However, the module configuration diagram shown in FIG. 4 is for illustrative purposes only and the present invention is not limited thereto.

[0035] FIG. 5 is an example diagram of the circuit configuration of a subpixel according to the first embodiment of the present invention, and FIG. 6 is a configuration diagram of a subpixel of a display panel according to the first embodiment of the present invention.

[0036] As shown in FIG. 5, the subpixel (SP) according to the first embodiment may include a switching transistor (SW), a capacitor (CST), a driving transistor (DT), and an organic light-emitting diode (OLED).

[0037] The switching transistor (SW) may have its gate electrode connected to the first gate line (GL1), its first electrode connected to the Nth data line (DLn), and its second electrode connected to the gate electrode of the driving transistor (DT). The switching transistor (SW) can serve to transmit the data voltage applied through the first data line (DL1) to the first electrode of the capacitor (CST).

[0038] The capacitor (CST) may have its first electrode connected to the gate electrode of the driving transistor (DT) and its second electrode connected to the second electrode of the driving transistor (DT) and the low potential voltage line (EVSS). The capacitor (CST) may serve to store a data voltage for driving the driving transistor (DT).

[0039] The driving transistor (DT) may have its gate electrode connected to the first electrode of the capacitor (CST), its first electrode connected to the cathode electrode of the organic light-emitting diode (OLED), and its second electrode connected to the low potential voltage line (EVSS). The driving transistor (DT) can generate a driving current in response to the data voltage stored in the capacitor (CST).

[0040] The organic light-emitting diode (OLED) may have its anode electrode connected to the high potential voltage line (EVDD) and its cathode electrode connected to the first electrode of the driving transistor (DT). The organic light-emitting diode (OLED) can emit light in response to the operation (driving current) of the driving transistor (DT).

[0041] As illustrated in FIG. 6, the display panel (150) according to the first embodiment may include two types of subpixels (SPA, SPB). The first type of subpixel (SPA) includes an organic light-emitting diode (OLED) and is a subpixel capable of emitting light. The second type of subpixel (SPB) does not include an organic light-emitting diode (OLED) and is a subpixel capable of emitting light. Thus, the first type of subpixel (SPA) and the second type of subpixel (SPB) may be configured similarly, but there is a difference depending on whether or not an organic light-emitting diode (OLED) is included.

[0042] Type 1 subpixels (SPA) can be arranged in multiple numbers in the display area (AA) (e.g., arranged in a matrix form), and Type 2 subpixels (SPB) can be arranged in multiple numbers in the non-display area (NA) (e.g., arranged in a line form). Type 2 subpixels (SPB) can be arranged one by one horizontally along the scan line. Type 2 subpixels (SPB) can be arranged only in one side of the non-display area (NA).

[0043] FIGS. 7 and 8 are drawings for explaining a sensing method of a low potential voltage line using a first type subpixel, a second type subpixel, and a sensing circuit unit according to a first embodiment of the present invention, FIG. 9 is a drawing for explaining the data voltage output sequence for sensing of a data driving unit according to a first embodiment of the present invention, and FIG. 10 is a drawing for explaining the sensing sequence of a low potential voltage line according to a first embodiment of the present invention.

[0044] As shown in FIG. 7, a first type subpixel (SPA) connected to a first gate line (GL1) to a second gate line (GLm) may be located in the display area (AA). And a second type subpixel (SPB) connected to a dummy gate line (GLd) may be located in the non-display area (NA).

[0045] The second type subpixel (SPB) connected to the dummy gate line (GLd) can receive a scan signal before the first type subpixel (SPA) connected to the first gate line (GL1). Therefore, when scan signals are applied sequentially, the second type subpixel (SPB) connected to the dummy gate line (GLd) can operate first, and then the first type subpixel (SPA) connected to the first gate line (GL1) can operate. After that, the operation of the first type subpixel (SPA) connected to the second gate line to the M gate line (GLm) can be performed sequentially.

[0046] The second type subpixel (SPB) and a plurality of first type subpixels (SPA) shown in FIG. 7 are arranged in a vertical direction and can all be commonly connected to the first data line (DL1) and the first low voltage line (EVSS1).

[0047] As shown in FIG. 8, when a dummy scan signal is applied through the dummy gate line (GLd) and a sensing data voltage is applied through the first data line (DL1), the driving transistor (DT) of the second type subpixel (SPB) can be turned on.

[0048] However, since the second type subpixel (SPB) does not contain an organic light-emitting diode, the high potential voltage applied through the high potential voltage line (EVDD) can be transmitted to the first low potential voltage line (EVSS1) via the driving transistor (DT). Also, the driving current generated in response to the turn-on operation of the driving transistor (DT) can also be transmitted to the first low potential voltage line (EVSS1). Accordingly, the sensing circuit (160) can sense the voltage or current transmitted to the first low potential voltage line (EVSS1).

[0049] A first low voltage line (EVSS1) wired in a vertical direction may have wiring resistances at different locations. For example, a first low voltage line (EVSS1) adjacent to a second type subpixel (SPB) may have a dummy wiring resistance (Rd), and a first low voltage line (EVSS1) adjacent to a plurality of first type subpixels (SPA) may have a first wiring resistance (Rp1) to an M-wiring resistance (Rpm).

[0050] The sensing circuit (160) can sense a voltage or current that has changed in response to a wiring resistance through the first low-potential voltage line (EVSS1). The voltage or current transmitted to the first low-potential voltage line (EVSS1) is output through the second type subpixel (SPB), and its influence is minimal. Therefore, the sensing circuit (160) can be defined as excluding the influence of the dummy wiring resistance (Rd) and sensing a voltage or current that has changed in response to the first wiring resistance (Rp1) to the M wiring resistance (Rpm).

[0051] Meanwhile, the first wiring resistor (Rp1) to the M-wiring resistor (Rpm) can ideally all have the same resistance value, but resistance variations may occur due to process variations, etc. A structure such as the first type subpixel (SPA) can uniformize display quality as long as the low potential voltage applied through the first low potential voltage line (EVSS1) is constant at all locations. However, the low potential voltage applied through the first low potential voltage line (EVSS1) may vary by location (or area) in correspondence with the first wiring resistor (Rp1) to the M-wiring resistor (Rpm) and their resistance variations. Additionally, the low potential voltage applied through the first low potential voltage line (EVSS1) may increase as it moves further away from the input side where the low potential voltage is applied.

[0052] The sensing circuit (160) can determine the amount of change in low potential voltage according to the influence of IR (current resistance) at each location of the first type subpixel (SPA) by sensing the voltage or current applied through the first low potential voltage line (EVSS1), in response to the first wiring resistance (Rp1) to the M wiring resistance (Rpm) and the resistance deviation thereof. The sensing circuit (160) can supply a sensing value (SEN) corresponding to the change in low potential voltage according to the influence of IR at each location of the first type subpixel (SPA) to the timing control unit (120). The timing control unit (120) can compensate and output a data signal in response to the change in low potential voltage according to the influence of IR at each location of the first type subpixel (SPA) based on the sensing value (SEN). That is, the timing control unit (120) can compensate the data signal by considering that the low potential voltage increases as it moves further away from the input side where the low potential voltage is applied, based on the sensing value (SEN).

[0053] As illustrated in FIGS. 8 to 10, the data driving unit (140) may include a first data channel (CH1) to a Nth data channel (CHn). As described with reference to FIG. 6, the first embodiment of the present invention can compensate for a data signal in response to a change in low potential voltage due to the IR influence at each position of the first type subpixel (SPA) based on the linkage between the sensing circuit unit (160) and the timing control unit (120).

[0054] However, resistance deviation may not occur only in a single low-potential voltage line but may occur throughout the entire display panel. Therefore, it is preferable to sense all low-potential voltage lines arranged vertically across the entire display panel or to sense them by region. FIGS. 9 and 10 illustrate the sequential driving of Type 2 subpixels (SPB) arranged in a line shape on a non-display area, along with the sequential output of sensing data voltages (Sdata) through all channels (CH1 ~ CHn) and subsequent sensing.

[0055] For example, when the first second type subpixel (SPB) is activated by the sensing data voltage (Sdata) output through the first data channel (CH1) during the first time (t1), the sensing circuit unit (160) can sense the first low potential voltage line (EVSS1) and acquire the change in low potential voltage by position for the first subpixel group (SPG1) arranged in the vertical direction.

[0056] Next, when the second type 2 subpixel (SPB) is activated by the sensing data voltage (Sdata) output through the second data channel (CH2) during the second time (t2), the sensing circuit (160) can sense the second low potential voltage line (EVSS2) and acquire the change in low potential voltage by position for the second subpixel group (SPG2) arranged in the vertical direction.

[0057] Subsequently, when the last second type subpixel (SPB) is operated by the sensing data voltage (Sdata) output through the Nth data channel (CHn) during the Nth time (tn) in this order, the sensing circuit unit (160) can sense the Nth low potential voltage line (EVSSn) and acquire the change in low potential voltage by position for the Nth subpixel group (SPGn) arranged in the vertical direction.

[0058] As can be seen from the description above, the sensing circuit (160) can sense one low-potential voltage line at a time. However, when all low-potential voltage lines on the display panel (150) are separated, a specific number of low-potential voltage lines can be sensed in a time-division manner when configured together with a circuit such as a multiplexer.

[0059] FIG. 11 is a drawing for explaining a data driving unit having a sensing circuit and a timing control unit having a compensation circuit according to a first embodiment of the present invention, and FIG. 12 and FIG. 13 are drawings for explaining the advantages of the first embodiment of the present invention.

[0060] As illustrated in FIG. 11, the sensing circuit (160) may be included in the data driving unit (140). The sensing value (SEN) corresponding to the change in low potential voltage due to the IR influence at the position of the first type subpixel (SPA) may be supplied to the timing control unit (120). The compensation circuit (170) that compensates the data signal in response to the change in low potential voltage due to the IR influence at the position of the first type subpixel (SPA) based on the sensing value (SEN) may be included in the timing control unit (120). The timing control unit (120) may supply the data signal (DATA) or the compensated data signal (CDATA), etc., to the data driving unit (140) depending on whether compensation is present.

[0061] As illustrated in FIG. 12, the display device according to the experimental example cannot compensate for changes in low potential voltage due to the IR influence at each position of the subpixels included in the display panel (150). As a result, when the display device according to the experimental example supplies an input image of Full White to the display panel (150), it can display an output image having a brightness deviation in the form of a gradient, unlike the input.

[0062] As illustrated in FIG. 13, the display device according to the first embodiment can compensate for changes in low potential voltage due to the IR influence at each position of the subpixels included in the display panel (150). As a result, when the display device according to the first embodiment supplies an input image of full white to the display panel (150), it can display an output image having full white that is similar or identical to the input. That is, the display device according to the first embodiment can compensate for changes in low potential voltage due to the IR influence at each position of the subpixels to equalize the display quality across the entire display panel (150).

[0063] FIG. 14 is a drawing specifically showing a sensing circuit section according to a second embodiment of the present invention, FIG. 15 is a waveform diagram for explaining the operation of the sensing circuit section shown in FIG. 14 according to a second embodiment of the present invention, and FIG. 16 and FIG. 17 are drawings for explaining the sensing and compensation of a display panel according to a second embodiment of the present invention.

[0064] As illustrated in FIGS. 14 and 15, the sensing circuit section (160) may include a first switch (SIO), a second switch (RST), an amplifier (CI), a sensing capacitor (CFB), a third switch (SAM), a fourth switch (EVSS_SW), and an output circuit (OUTC). In the sensing circuit section (160), the first switch (SIO), the second switch (RST), the amplifier (CI), and the sensing capacitor (CFB) may be defined as an integrating circuit capable of integrating the sensed current. Although the fourth switch (EVSS_SW) is illustrated as being included in the sensing circuit section (160) as an example, it may also be included in a display panel, a printed circuit board, or a power supply unit.

[0065] The first switch (SIO) may have its first electrode connected to the common low voltage line (EVSSC), its second electrode connected to the inverting terminal (-) of the amplifier (CI), and its control electrode connected to the first control signal line. The first switch (SIO) may be turned on when a first control signal (SIO) of high voltage (H) is applied to the first control signal line, and may be turned off when a first control signal (SIO) of low voltage (L) is applied. When the first switch (SIO) is turned on, the integration circuit can integrate the current sensed based on the sensing capacitor (CFB).

[0066] The second switch (RST) may have its first electrode connected to the inverting terminal (-) of the amplifier (CI), its second electrode connected to the output terminal of the amplifier (CI), and its control electrode connected to the second control signal line. The second switch (RST) may be turned on when a second control signal (Rst) of high voltage (H) is applied to the second control signal line, and may be turned off when a second control signal (Rst) of low voltage (L) is applied. When the second switch (RST) is turned on, the integration circuit can initialize the current integrated in the sensing capacitor (CFB).

[0067] The third switch (SAM) may have a first electrode connected to the output terminal of the amplifier (CI), a second electrode connected to the output circuit (OUTC), and a control electrode connected to the third control signal line. The third switch (SAM) may be turned on when a third control signal (Sam) of high voltage (H) is applied to the third control signal line, and may be turned off when a third control signal (Sam) of low voltage (L) is applied. When the third switch (SAM) is turned on, the current integrated in the integration circuit may be delivered to the output circuit (OUTC).

[0068] The fourth switch (EVSS_SW) may have a first electrode connected to the low potential voltage common line (EVSSC), a second electrode connected to the low potential voltage supply line (EVSSO), and a control electrode connected to the fourth control signal line. The fourth switch (EVSS_SW) may be turned on when a fourth control signal (Evss_sw) of high voltage (H) is applied to the fourth control signal line, and may be turned off when a fourth control signal (Evss_sw) of low voltage (L) is applied. When the fourth switch (EVSS_SW) is turned on, the low potential voltage common line (EVSSC) can transmit the low potential voltage applied through the low potential voltage supply line (EVSSO) to the first low potential voltage line (EVSS1) and the second low potential voltage line (EVSS2). In contrast, when the fourth switch (EVSS_SW) is turned off, the low voltage common line (EVSSC) is connected to the inverting terminal (-) of the amplifier (CI) to sense low voltage lines placed on the display panel, such as the first low voltage line (EVSS1) or the second low voltage line (EVSS2). In other words, when the fourth switch (EVSS_SW) is turned on, a low voltage can be applied to low voltage lines placed on the display panel, such as the first low voltage line (EVSS1) or the second low voltage line (EVSS2). However, when the fourth switch (EVSS_SW) is turned off, the low voltage applied to low voltage lines placed on the display panel, such as the first low voltage line (EVSS1) or the second low voltage line (EVSS2), can be blocked.

[0069] As illustrated in FIGS. 14 and 15, during the first period (P1), the first switch (SIO) and the second switch (RST) may be in a turned-on state, and the third switch (SAM) and the fourth switch (EVSS_SW) may be in a turned-off state. The first period (P1) may be defined as the reset period of the sensing circuit (160). During the first period (P1), the low potential voltage common line (EVSSC) may be initialized by a reference voltage (VREF_CI) applied to the non-inverting terminal (+) of the amplifier (CI).

[0070] During the second period (P2), the first switch (SIO) may be in a turned-on state, and the second switch (RST), the third switch (SAM), and the fourth switch (EVSS_SW) may be in a turned-off state. The second period (P2) may be defined as the sensing period of the sensing circuit unit (160). During the second period (P2), the current sensed from the first low-potential voltage line (EVSS1), etc., may be transmitted to the low-potential voltage common line (EVSSC), and the integrating circuit may integrate the current. At this time, the output (Ci_out) of the integrating circuit may gradually decrease in correspondence with the integrated current.

[0071] During the third period (P3), the first switch (SIO) and the third switch (SAM) may be in a turned-on state, and the second switch (RST) and the fourth switch (EVSS_SW) may be in a turned-off state. The third period (P3) may be defined as the sampling period of the sensing circuit (160). During the third period (P3), the output circuit (OUTC) may sample the output (Ci_out) of the integration circuit.

[0072] Meanwhile, it should be noted that Rr, Gr, and Br in FIG. 15 are intended to exemplify that a change in low voltage for a red subpixel, a change in low voltage for a green subpixel, and a change in low voltage for a blue subpixel can be sensed based on the operation of the sensing circuit unit (160).

[0073] As shown in FIG. 16, a first sensing data voltage corresponding to 10V can be applied through the first data line (DL1), and a second sensing data voltage (or black data voltage) corresponding to 0V can be applied through the second data line (DL2). Additionally, a dummy scan signal corresponding to a high voltage can be applied through the dummy gate line (GLd), and a scan signal corresponding to a low voltage can be applied to the first gate line (GL1), etc.

[0074] When the second type subpixel (SPB1, SPB2) and the first type subpixel (SPA1, SPA2) are operated under the above conditions, the driving transistor of the second type subpixel (SPB1) connected to the first data line (DL1) is turned on, but the driving transistor of the second type subpixel (SPB2) connected to the second data line (DL2) may be turned off.

[0075] Accordingly, conditions can be formed in which the current (A) applied through the high voltage line (EVDD) can flow through the first low voltage line (EVSS1). When such conditions are formed, the sensing circuit (160) can sense the current (A) flowing through the first low voltage line (EVSS1) based on the operation described in FIGS. 14 and FIGS. 15. As previously described, the current (A) sensed by the sensing circuit (160) can change in correspondence with the positional wiring resistances (Rp1-1, Rp1-2, Rp1-3 ...) formed in the first low voltage line (EVSS1).

[0076] In contrast, since conditions are not formed in which the voltage and current (A) applied through the high voltage line (EVDD) can flow in the second low voltage line (EVSS2), it can be charged by the reference voltage (VREF_CI) applied to the non-inverting terminal (+) of the amplifier (CI).

[0077] In the manner described above, once sensing for the first low voltage line (EVSS1) is completed, sensing for the second low voltage line (EVSS2) through the Nth low voltage line can be performed sequentially thereafter.

[0078] As illustrated in FIG. 17, according to the second embodiment of the present invention, the positional rise in the low potential voltage line can be sensed and stored (EVSS Rising Voltage store) during the first frame (1st Frame). And during the second frame (2nd Frame), the data signal can be compensated (DATA compensation based on EVSS Rising Voltage) based on a compensation voltage formula for the positional rise in the low potential voltage line.

[0079] In addition, according to the second embodiment of the present invention, the rise in low voltage at each position for the low voltage line may be sensed and stored during the period when a non-valid image (e.g., screen saver image) is displayed on the display panel, such as a frame (BLACK) displaying a black image, or during a blank period.

[0080] The current and voltage flowing through the low potential voltage line (EVSS) can be affected by wiring resistance, and if this is represented from the first line (1st) to the Nth line (Nth), it can be expressed in the form of an equivalent circuit as shown on the right side of FIG. 17.

[0081] According to the second embodiment of the present invention, a voltage rise for a low potential voltage line from the first line (1st) to the Nth line (Nth) during the first frame (1st Frame) can be sensed, and a compensation voltage equation for compensating the voltage rise can be provided, which can be expressed as shown in the following table.

[0082] Sensing voltage formula of low voltage lines from the 1st line (1st) to the Nth line (Nth) Compensation voltage formula for low voltage lines from the 1st line (1st) to the Nth line (Nth)

[0083] In the above equation, V represents the voltage of each subpixel in the current frame, and V' may represent the voltage of each subpixel in the previous frame. IS represents the current fluctuation value of each subpixel in the current frame, IS' represents the current fluctuation value of each subpixel in the previous frame, and R may represent the wiring resistance of each subpixel.

[0084] In addition, the compensation voltage equation for compensating for the voltage (Vk) rise for the Kth line (Kth) in the above equation can be rearranged as follows.

[0085]

[0086] In the above equation, Vk represents the voltage of the subpixel of the Kth line (Kth) in the current frame, IS'k represents the current fluctuation value of the subpixel of the Kth line (Kth) in the previous frame, ISk-1 represents the current fluctuation value of the subpixel located one line before the Kth line (Kth) in the current frame, and ISk-1' represents the current fluctuation value of the subpixel located one line before the Kth line (Kth) in the previous frame.

[0087] Meanwhile, the above equation is intended only to help understand how to compensate for a data signal based on a compensation voltage equation after sensing the rise in low potential voltage at each location for a low potential voltage line, and the present invention is not limited thereto.

[0088] FIGS. 18 to 20 are exemplary drawings showing the cross-sectional structure of a first type subpixel and a second type subpixel according to a third embodiment of the present invention.

[0089] As shown in FIG. 18, the first type subpixel (SPA) and the second type subpixel (SPB) may have an aperture region (OPN) defined between the low potential voltage line (EVSS) and the first data line (DL1). The capacitor (CST) and the driving transistor (DT) included therein may be positioned overlapping the low potential voltage line (EVSS) to form a wide aperture region (OPN) (increase the light-emitting area).

[0090] As shown in FIGS. 19 and 20, the first type subpixel (SPA) and the second type subpixel (SPB) may have the same structure, differing only in the presence or absence of an organic light-emitting layer (OL), and their cross-sectional structure is described as follows.

[0091] The substrate (SUB) may include a region where a driving transistor is formed (DTA), a region where a low potential voltage line is formed (EVSSA), a region where an aperture region is formed (OPNA), and a region where a pad portion is formed (PADA).

[0092] A low potential voltage line (EVSS) may be located on the substrate (SUB). The low potential voltage line (EVSS) may be located in the region (EVSSA) where the low potential voltage line is formed. The low potential voltage line (EVSS) may be selected from a material capable of blocking light.

[0093] A buffer layer (BUF) may be located on the substrate (SUB). The buffer layer (BUF) may be located in the region where the driving transistor is formed (DTA), the region where the low potential voltage line is formed (EVSSA), the region where the aperture region is formed (OPNA), and the region where the pad portion is formed (PADA). The buffer layer (BUF) may expose a portion of the low potential voltage line (EVSS).

[0094] A semiconductor layer (ACT) may be formed on the buffer layer (BUF). The semiconductor layer (ACT) may be located in the region where the driving transistor is formed (DTA) and the region where the low potential voltage line is formed (EVSSA). The semiconductor layer (ACT) may be selected from oxide semiconductors, silicon semiconductors, etc.

[0095] A gate insulating layer (GI) may be formed on the buffer layer (BUF) and the semiconductor layer (ACT). The gate insulating layer (GI) may be located in the region where the pad portion is formed (PADA), the region where the driving transistor is formed (DTA), and the region where the low potential voltage line is formed (EVSSA). The gate insulating layer (GI) may be formed in the form of an island. The gate insulating layer (GI) formed in the region where the driving transistor is formed (DTA) and the region where the low potential voltage line is formed (EVSSA) may expose the source and drain regions of the semiconductor layer (ACT).

[0096] A gate metal layer (GAT, GATP) may be formed on the gate insulating layer (GI). The gate metal layer (GAT, GATP) may be located in the region where the pad portion is formed (PADA), the region where the driving transistor is formed (DTA), and the region where the low potential voltage line is formed (EVSSA). The gate metal layer (GAT, GATP) may be formed in an island shape. The gate metal layer (GAT, GATP) may be formed in multiple layers. The gate metal layer (GATP) located in the region where the pad portion is formed (PADA) may be defined as a lower pad electrode layer, and the gate metal layer (GAT) located in the region where the driving transistor is formed (DTA) and the region where the low potential voltage line is formed (EVSSA) may be defined as a gate electrode layer.

[0097] An interlayer insulating layer (ILD) may be formed on the buffer layer (BUF). The interlayer insulating layer (ILD) may be located in the region where the driving transistor is formed (DTA), the region where the low potential voltage line is formed (EVSSA), the region where the aperture region is formed (OPNA), and the region where the pad portion is formed (PADA). The interlayer insulating layer (ILD) may expose a portion of the low potential voltage line (EVSS), a portion of the source and drain regions of the semiconductor layer (ACT), and a portion of the lower pad electrode layer (GATP).

[0098] Source-drain metal layers (SD1, SD2, SDP) may be formed on a portion of the low potential voltage line (EVSS), a portion of the source and drain regions of the semiconductor layer (ACT), and a portion of the lower pad electrode layer (GATP). The first source-drain metal layer (SD1) may be in contact with a portion of the semiconductor layer (ACT). The first source-drain metal layer (SD1) may be defined as the first electrode of the driving transistor. The second source-drain metal layer (SD2) may be in contact with a portion of the low potential voltage line (EVSS) and another portion of the semiconductor layer (ACT). The second source-drain metal layer (SD2) may be defined as the second electrode of the driving transistor. The third source-drain metal layer (SDP) may be in contact with the lower pad electrode layer (GATP). The third source-drain metal layer (SDP) may be defined as the upper pad electrode layer.

[0099] A protective layer (PAS) may be formed on the interlayer insulation layer (ILD). The protective layer (PAS) may be located in the region where the driving transistor is formed (DTA), the region where the low potential voltage line is formed (EVSSA), the region where the aperture region is formed (OPNA), and the region where the pad portion is formed (PADA). The protective layer (PAS) may expose a portion of the first source-drain metal layer (SD1) and a portion of the third source-drain metal layer (SDP).

[0100] A color filter layer (CF) may be formed on the protective layer (PAS). The color filter layer (CF) may be located in the region (OPNA) where the aperture region is formed. The color filter layer (CF) may be selected as red, green, or blue.

[0101] An overcoat layer (OC) may be formed on the protection layer (PAS). The overcoat layer (OC) may be located in the region where the driving transistor is formed (DTA), the region where the low potential voltage line is formed (EVSSA), and the region where the aperture region is formed (OPNA). The overcoat layer (OC) may expose a portion of the first source-drain metal layer (SD1).

[0102] A cathode electrode layer (CAT) may be formed on the overcoat layer (OC). The cathode electrode layer (CAT) may be located in the region where the aperture region is formed (OPNA) and the region where the driving transistor is formed (DTA). The cathode electrode layer (CAT) may be selected from a transparent material with excellent light transmittance.

[0103] A bank layer (BNK) may be formed on the overcoat layer (OC). The bank layer (BNK) may be located in the region where the driving transistor is formed (DTA), the region where the low potential voltage line is formed (EVSSA), and the region where the aperture region is formed (OPNA). The bank layer (BNK) may expose a portion of the cathode electrode layer (CAT) in the region where the aperture region is formed (OPNA).

[0104] An anode electrode layer (ANO) may be formed on the bank layer (BNK). The anode electrode layer (ANO) may be located in the region where the driving transistor is formed (DTA), the region where the low potential voltage line is formed (EVSSA), and the region where the aperture region is formed (OPNA). The anode electrode layer (ANO) may be selected as a low-resistance opaque material with excellent light-blocking properties.

[0105] As illustrated in FIG. 19, the second type subpixel (SPB) does not have an organic light-emitting layer (OL) located between the anode electrode layer (ANO) and the cathode electrode layer (CAT). Therefore, the second type subpixel (SPB) can be formed as a subpixel that cannot emit light because the anode electrode layer (ANO) and the cathode electrode layer (CAT) are in contact (short-circuited) since the organic light-emitting layer (OL) is not located in the second type subpixel (SPB). According to FIG. 19, the second type subpixel (SPB) is formed in a state where only the anode electrode layer (ANO) and the cathode electrode layer (CAT) included in the organic light-emitting diode are formed, that is, a state where only the electrodes are located.

[0106] As illustrated in FIG. 20, the first type subpixel (SPA) has an organic light-emitting layer (OL) located between the anode electrode layer (ANO) and the cathode electrode layer (CAT). Therefore, the first type subpixel (SPA) can be formed as a subpixel capable of emitting light because the organic light-emitting layer (OL) is located therein. Meanwhile, the organic light-emitting layer (OL) can be formed based on an inkjet printing method, a deposition method, or a thermal transfer method, but is not limited thereto.

[0107] In summary, the present invention has the effect of detecting the amount of change in low potential voltage due to the influence of IR (current resistance) at each location by applying a high potential voltage to a low potential voltage line through a subpixel that cannot emit light and then sensing, and compensating the data signal based on this to equalize the display quality of the entire display panel. Furthermore, the present invention has the effect of minimizing the problem of display quality degradation that may be caused by resistance deviations due to process deviations, etc., by sensing the current or voltage flowing through the low potential voltage line and based on this. Explanation of the symbols

[0108] 140: Data driving unit 150: Display panel 120: Timing control unit 160: Sensing circuit unit 170: Compensation circuit 180: Power supply EVDD: High voltage line EVSS: Low voltage line SPA: Type 1 subpixel SPB: Type 2 subpixel

Claims

Claim 1 A display device comprising: a first type subpixel that emits light and a second type subpixel that does not emit light; a high potential voltage line connected to the first type subpixel and the second type subpixel and transmitting a high potential voltage; a low potential voltage line connected to the first type subpixel and the second type subpixel and transmitting a low potential voltage; and a circuit unit connected to the low potential voltage line, wherein the circuit unit senses the low potential voltage line when the second type subpixel operates and compensates for a data signal to be supplied to the first type subpixel based on a sense value obtained through sensing, wherein the first type subpixel is placed in a display area to perform light emission, and the second type subpixel is placed in a non-display area and has a structure in which it does not include a light-emitting element or the anode electrode and cathode electrode of the light-emitting element are short-circuited and is driven for sensing. Claim 2 delete Claim 3 In claim 1, the second type subpixel is a display device in which a driving transistor is turned on in response to a sensing data voltage and a dummy scan signal. Claim 4 A display device according to paragraph 3, wherein when the driving transistor included in the second type subpixel is turned on, the high potential voltage applied through the high potential voltage line is transmitted to the low potential voltage line. Claim 5 In claim 1, the second type subpixel is a display device arranged in a line shape along the direction of the gate line. Claim 6 A display device according to claim 1, wherein the circuit portion compensates the data signal in response to the amount of change in the low potential voltage according to the IR (current resistance) influence at each position of the display panel based on the sensing value obtained through the low potential voltage line. Claim 7 A display device according to claim 6, wherein, during the sensing operation of the circuit portion, the low potential voltage applied through the low potential voltage line is blocked, and instead, the high potential voltage applied through the second type subpixel is transmitted through the low potential voltage line. Claim 8 A method for driving a display device comprising a display panel including a first type subpixel that emits light and a second type subpixel that does not emit light, and a circuit portion that senses a low potential voltage line connected to the first type subpixel and the second type subpixel, wherein the method comprises: a step of applying a sensing data voltage and a dummy scan signal to the second type subpixel; a step of sensing the low potential voltage line connected to the first type subpixel and the second type subpixel; and a step of compensating a data signal to be supplied to the first type subpixel based on a sensing value obtained through the low potential voltage line, wherein the first type subpixel is placed in a display area to perform light emission, and the second type subpixel is placed in a non-display area and has a structure that does not include a light-emitting element or in which the anode electrode and the cathode electrode of the light-emitting element are short-circuited, and is driven for sensing. Claim 9 A driving method for a display device according to claim 8, wherein, during the sensing operation of the circuit portion, the low potential voltage applied through the low potential voltage line is blocked, and instead, the high potential voltage applied through the second type subpixel is transmitted through the low potential voltage line. Claim 10 In claim 9, the step of compensating the data signal is a driving method of a display device that compensates the data signal in response to the change in the low potential voltage according to the IR (current resistance) influence of the display panel at each position based on the sensing value.

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