Display Apparatus and Method for Driving the same

Abstract

The embodiments of the present specification relate to a display device and a driving method thereof that prevent the operation of an NIR proximity sensor from affecting changes in brightness. The display device comprises a display panel having a plurality of pixels and a gate driving unit including first to fourth scan driving units and a light emission control signal driving unit. Each pixel has a driving transistor that controls the driving current of a light-emitting element and a compensation transistor that compensates for the threshold voltage of the driving transistor. Each pixel is sequentially driven through a first bias section, an initialization section, a sampling section, a second bias section, and a light emission section during one frame. Prior to the sampling section, a scan signal can be output so that the compensation transistor is turned on.

Description

Technology Field

[0001] This specification relates to a display device and a method of driving the same. Background Technology

[0002] Electronic devices such as smartphones, tablet PCs, digital cameras, laptop computers, navigation systems, and smart televisions that provide video to users include a display device for displaying video.

[0003] In addition, electronic devices such as smartphones and tablet PCs include proximity sensors configured to detect the proximity of objects in order to perform various applications. Near Infrared Radiation (NIR) proximity sensors are used as such.

[0004] The display device includes a panel that displays an image through pixels arranged in a matrix form where multiple gate lines and multiple data lines intersect each other, and a driving circuit that drives the panel. Each pixel is driven independently by a thin film transistor (TFT).

[0005] However, when the NIR proximity sensor is in operation, an NIR light source is irradiated onto the transistors of each pixel, causing leakage current in the transistors. This can result in a difference in brightness of the display device between when the NIR proximity sensor is in operation and when it is not. The problem to be solved

[0006] The present embodiment provides a display device and a driving method thereof that prevent the operation of an NIR proximity sensor from affecting changes in brightness, in order to solve the aforementioned problems. means of solving the problem

[0007] A display device according to the present embodiment includes a display panel having a plurality of pixels, and a gate driver including a first to fourth scan driver and a light emission control signal driver, wherein each pixel has a driving transistor for controlling the driving current of a light-emitting element and a compensation transistor for compensating the threshold voltage of the driving transistor, and each pixel is sequentially driven through a first bias section, an initialization section, a sampling section, a second bias section, and a light emission section during one frame, and prior to the sampling section, the first scan driver can output a first scan signal to turn on the compensation transistor.

[0008] A display device according to another embodiment comprises a display panel having a plurality of pixels and an NIR proximity sensor for detecting the proximity of an object, and each pixel comprises a driving transistor for controlling the driving current of a light-emitting element and a bias transistor for applying a bias voltage to the driving transistor to mitigate hysteresis of the driving transistor, and the bias voltage supplied to the bias transistor may be supplied at different voltages during the period when the NIR proximity sensor is operating and during the period when the NIR proximity sensor is not operating. Effects of the invention

[0009] The display device and the driving method according to the present embodiment have the following effects.

[0010] Since a scan signal is output to turn on the compensation transistor before the sampling interval, the operation of the NIR proximity sensor can be prevented from affecting changes in brightness.

[0011] In another embodiment, the bias voltage supplied to the bias transistor is supplied at a lower voltage during the period when the NIR proximity sensor is operating than during the period when the NIR proximity sensor is not operating, so that the operation of the NIR proximity sensor does not affect the change in brightness.

[0012] The effects according to the present embodiment are not limited to those exemplified above, and various other effects are included in this specification. Brief explanation of the drawing

[0013] FIG. 1 is a block diagram showing a display device according to an embodiment of the present specification. FIG. 2 is a drawing showing a pixel circuit in a display device according to an embodiment of the present specification. FIGS. 3a and FIGS. 3b are drawings showing driving waveforms corresponding to the refresh period and hold period for the operation of the pixel circuit of FIG. 4. FIG. 4 is a block diagram showing the configuration of a gate driving unit in a display device according to an embodiment of the present specification. FIG. 5 is a diagram showing the driving waveform of the pixel circuit of FIG. 2 for ensuring that the operation of the NIR proximity sensor according to one embodiment of the present specification does not affect changes in brightness. FIGS. 6a to 6e are diagrams for explaining the operation of transistors of subpixels in the first bias period (Tobs1), initialization period (Ti), sampling period (Ts), second bias period (Tobs2), and light emission period (Te) of FIG. 5. FIGS. 7a to 7c are graphs showing the relationship between the bias voltage (Vobs_A) and the bias voltage (Vobs_B) for NIR Mura at operating frequencies of 120 Hz and 10 Hz. FIG. 8 is an example diagram showing the application of NIR Mura optimized bias voltage (Vobs_A) and bias voltage (Vobs_B) on a frame-by-frame basis according to the present embodiment. Specific details for implementing the invention

[0014] The advantages and features of the embodiments of this specification, and the methods for achieving them, will become clear by referring to the various embodiments described below in detail together with the accompanying drawings. However, this specification is not limited to the various embodiments disclosed below but may be implemented in various different forms; the various embodiments of this specification are provided merely to ensure that the disclosure of this specification is complete and to fully inform those skilled in the art of the scope of the invention. Accordingly, this specification is defined by the scope of the claims.

[0015] Shapes, sizes, ratios, angles, numbers, etc. disclosed in the drawings for describing various embodiments of this specification are exemplary, and this specification is not limited to the matters shown in the drawings. Throughout this specification, the same reference numerals refer to the same components. Furthermore, in describing this specification, if it is determined that a detailed description of related prior art could unnecessarily obscure the essence of this specification, such detailed description is omitted. Where terms such as "includes," "has," or "is made up" are used in this specification, other parts may be added unless "only" is used. Where a component is expressed in the singular, it includes cases where it is included in the plural unless specifically stated otherwise.

[0016] In interpreting the components included in the various embodiments of this specification, they are interpreted to include an error range even if there is no separate explicit description.

[0017] In describing various embodiments of this specification, when describing positional relationships, for example, when the positional relationship between two parts is described using expressions such as 'on', 'on the upper part', 'on the lower part', 'next to', etc., unless 'immediately' or 'directly' is used, one or more other parts may be located between the two parts.

[0018] In describing various embodiments of this specification, when describing temporal relationships, for example, when describing temporal sequences using 'after,' 'following,' 'next,' 'before,' etc., cases that are not continuous may be included unless 'immediately' or 'directly' is used.

[0019] In describing the various embodiments of this specification, terms such as 'first~', 'second~', etc. may be used to describe various components, but these terms are used merely to distinguish between identical or similar components. Accordingly, unless otherwise stated, a component modified by 'first~' in this specification may be identical to a component modified by 'second~' within the technical scope of this specification.

[0020] Each of the features of the various embodiments of this specification may be combined or combined with one another, either partially or wholly, and may technically enable various interlocking and operation. Each of the various embodiments may be implemented independently of one another or may be implemented together in an associated relationship.

[0021] Hereinafter, a touch sensing device according to an embodiment of the present specification will be described in more detail with reference to the attached drawings.

[0022] FIG. 1 is a block diagram schematically illustrating a display device according to one embodiment of the present specification.

[0023] Referring to FIG. 1, the display device (10) includes a display panel (100) including a plurality of pixels (P), a controller (200), a gate driver (300) that supplies a gate signal to each of the plurality of pixels (P), a data driver (400) that supplies a data signal (or data voltage) to each of the plurality of pixels (P), and a power supply unit (500) that supplies power required for driving to each of the plurality of pixels (P).

[0024] The display panel (100) includes a display area (AA) where a pixel (P) is located and a non-display area (NA) arranged to surround the display area (AA) and where a gate driver (300) and a data driver (400) are arranged.

[0025] In the display panel (100), a plurality of gate lines (GL) and a plurality of data lines (DL) intersect each other, and each of a plurality of pixels (P) is connected to the gate line (GL) and the data line (DL). Specifically, one pixel (P) receives a gate signal from the gate driver (300) through the gate line (GL), receives a data signal from the data driver (400) through the data line (DL), and receives a high-potential driving voltage (EVDD) and a low-potential driving voltage (EVSS) from the power supply unit (500).

[0026] A gate line (GL) supplies a scan signal (SC) and a light emission control signal (EM) to a plurality of pixels (P), and a data line (DL) supplies a data voltage (Vdata) to a plurality of pixels (P). According to various embodiments, the gate line (GL) may include a plurality of scan lines (SCL) for supplying the scan signal (SC) and a plurality of light emission control signal lines (EML) for supplying the light emission control signal (EM). A plurality of pixels (P) may receive a bias voltage (Vobs) and an initialization voltage (Var, Vini) from a power line (VL).

[0027] Each pixel (P) includes a light-emitting element (EL) and a pixel circuit that controls the driving of the light-emitting element (EL). The light-emitting element (EL) may include an anode electrode, a cathode electrode, and a light-emitting layer between the anode electrode and the cathode electrode.

[0028] The pixel circuit may include a plurality of switching elements, driving elements, and capacitors. The switching elements and driving elements may be composed of thin-film transistors. The driving element controls the amount of current supplied to the light-emitting element (EL) according to the data voltage (Vdata) to regulate the amount of light emitted by the light-emitting element (EL). The plurality of switching elements are switched according to a scan signal (SC) supplied through a plurality of scan lines (SCL) and a light emission control signal (EM) supplied through a light emission control line (EML).

[0029] The display panel (100) can be implemented as a non-transparent display panel or a transparent display panel. A transparent display panel can be applied to a transparent display device in which an image is displayed on the screen and the actual background is visible. The display panel (100) can also be implemented as a flexible display panel. A flexible display panel can be implemented as an OLED panel using a plastic substrate.

[0030] Each pixel (P) can be divided into a red pixel, a green pixel, and a blue pixel for color implementation. Each of the pixels (P) may further include a white pixel. Each of the pixels (P) includes a pixel circuit.

[0031] Touch sensors may be placed on the display panel (100). Touch input may be sensed using separate touch sensors or through pixels (P). The touch sensors may be implemented as on-cell type or add-on type touch sensors placed on the screen of the display panel, or as in-cell type touch sensors embedded in the display panel (100).

[0032] The controller (200) processes image data (RGB) input from the outside to suit the size and resolution of the display panel (100) and supplies it to the data driver (400). The controller (200) generates a gate control signal (GCS) and a data control signal (DCS) using synchronization signals input from the outside, such as a dot clock signal (CLK), a data enable signal (DE), a horizontal synchronization signal (Hsync), and a vertical synchronization signal (Vsync). The controller (200) supplies the gate control signal (GCS) to the gate driver (300) to suggest the operation timing of the gate driver (300). The controller (200) supplies the data control signal (DCS) to the data driver (400) to control the operation timing of the data driver (400). The controller (200) synchronizes the operation timing of the gate driver (300) and the data driver (400) using the gate control signal (GCS) and the data control signal (DCS).

[0033] The controller (200) may be configured to be combined with various processors, such as a microprocessor, mobile processor, application processor, etc., depending on the device being implemented.

[0034] The host system may be any one of a TV (Television) system, set-top box, navigation system, personal computer (PC), home theater system, mobile device, wearable device, or vehicle system.

[0035] The controller (200) can control the operation timing of the display panel driver by multiplying the input frame frequency by i to a frame frequency of input frame frequency × i (i is a positive integer greater than 0) Hz. The input frame frequency is 60 Hz in the NTSC (National Television Standards Committee) system and 50 Hz in the PAL (Phase-Alternating Line) system, and may include 120 Hz and 144 Hz operation frequencies in mobile devices.

[0036] The controller (200) can drive the pixel (P) at various refresh rates. The controller (200) can drive the pixel (P) in a Variable Refresh Rate (VRR) mode, that is, switchably between a first refresh rate and a second refresh rate. For example, the controller (200) can drive the pixel (P) at various refresh rates by simply changing the speed of the clock signal, generating a synchronization signal to create a horizontal blank or a vertical blank, or driving the gate driver (300) in a mask manner.

[0037] The voltage level of the gate control signal (GCS) output from the controller (200) can be converted into a gate-on voltage (VGL, VEL) and a gate-off voltage (VGH, VEH) through a level shifter (not shown) and supplied to the gate driver (300). The level shifter converts the low-level voltage of the gate control signal (GCS) into a gate-low voltage (VGL) and converts the high-level voltage of the gate control signal (GCS) into a gate-high voltage (VGH). The gate control signal (GCS) includes a start pulse and a shift clock.

[0038] The gate driver (300) supplies a gate signal to the gate line (GL) according to the gate control signal (GCS) supplied from the controller (200). The gate driver (300) may be positioned on one or both sides of the display panel (100) in a GIP (Gate In Panel) manner.

[0039] The gate driver (300) sequentially outputs gate signals to a plurality of gate lines (GL) under the control of the controller (200). The gate driver (300) can sequentially supply the signals to the gate lines (GL) by shifting the gate signals using a shift register.

[0040] The gate signal may include a scan signal (SC) and a light emission control signal (EM) in an organic light-emitting display. The scan signal (SC) includes a scan pulse that swings between the gate-on voltage (VGL) and the gate-off voltage (VGH). The light emission control signal (EM) may include a light emission control signal pulse that swings between the gate-on voltage (VEL) and the gate-off voltage (VEH). The scan pulse selects pixels (P) on the line to which the data voltage (Vdata) is to be written. The light emission control signal (EM) defines the light emission time of the pixels (P).

[0041] The gate driving unit (300) may include a light emission control signal driving unit (310) and at least one scan driving unit (320).

[0042] The light emission control signal driving unit (310) outputs a light emission control signal pulse in response to a start pulse and a shift clock from the controller (200), and sequentially shifts the light emission control signal pulse according to the shift clock.

[0043] At least one scan drive unit (320) outputs a scan pulse in response to a start pulse and a shift clock from the controller (200), and shifts the scan pulse in accordance with the shift clock timing.

[0044] The data driving unit (400) converts image data (RGB) into a data voltage (Vdata) according to a data control signal (DCS) supplied from the controller (200), and supplies this data voltage (Vdata) to a pixel (P) through a data line (DL).

[0045] In FIG. 1, the data driving unit (400) is shown as being arranged in a single form on one side of the display panel (100), but the number and arrangement position of the data driving unit (400) are not limited thereto. That is, the data driving unit (400) may be composed of multiple integrated circuits (IC) and arranged in multiple separate units on one side of the display panel (100).

[0046] The power supply unit (500) generates DC power required to drive the pixel array of the display panel (100) and the display panel driver using a DC-DC converter. The DC-DC converter may include a charge pump, a regulator, a buck converter, a boost converter, etc. The power supply unit (500) receives a DC input voltage applied from a host system not shown and can generate DC voltages such as a gate-on voltage (VGL, VEL), a gate-off voltage (VGH, VEH), a high-potential driving voltage (EVDD), and a low-potential driving voltage (EVSS). The gate-on voltage (VGL, VEL) and the gate-off voltage (VGH, VEH) are supplied to a level shifter not shown and a gate driver (300). The high-potential driving voltage (EVDD) and the low-potential driving voltage (EVSS) are supplied to the pixels (P) in common.

[0047] FIG. 2 is an equivalent circuit diagram of one subpixel in a display device according to an embodiment of the present specification.

[0048] FIG. 2 merely illustrates a subpixel circuit as an example. For convenience, a display device having the pixel circuit structure of FIG. 2 will be described below. FIG. 2 illustrates a subpixel of an MTO pixel structure that applies an oxide semiconductor thin film transistor and a polycrystalline silicon thin film transistor in order to improve power consumption and enable low-speed operation.

[0049] Referring to FIG. 2, each of the plurality of subpixels (P) may include a pixel circuit having a driving transistor (DT) and a light-emitting element (EL) driven by the pixel circuit.

[0050] The pixel circuit can drive the light-emitting element (EL) by controlling the driving current flowing through the light-emitting element (EL). The pixel circuit may include a driving transistor (DT), first to seventh switching transistors (T1 to T7), and a capacitor (Cst). Each of the transistors (DT, T1 to T7) may include a first electrode, a second electrode, and a gate electrode. One of the first electrode and the second electrode may be a source electrode, and the other of the first electrode and the second electrode may be a drain electrode.

[0051] Each of the transistors (DT, T1 to T7) may be a P-type thin-film transistor or an N-type thin-film transistor. In the embodiment of FIG. 4, the first switching transistor (T1) and the seventh switching transistor (T7) are N-type thin-film transistors, and the remaining transistors (DT, T2 to T6) are P-type thin-film transistors. However, this is not limited thereto, and depending on the embodiment, all or part of the transistors (DT, T1 to T7) may be P-type thin-film transistors or N-type thin-film transistors. Additionally, the N-type thin-film transistor may be an oxide thin-film transistor, and the P-type thin-film transistor may be a polycrystalline silicon thin-film transistor.

[0052] In the following description, the first switching transistor (T1) and the seventh switching transistor (T7) are N-type thin-film transistors, and the remaining transistors (DT, T2 to T6) are P-type thin-film transistors. Accordingly, the first switching transistor (T1) and the seventh switching transistor (T7) are turned on in response to a high voltage, and the remaining transistors (DT, T2 to T6) are turned on in response to a low voltage.

[0053] According to one example, the first switching transistor (T1) constituting the pixel circuit can function as a compensation transistor, the second switching transistor (T2) as a data supply transistor, the third and fourth switching transistors (T3, T4) as light emission control transistors, the fifth switching transistor (T5) as a bias transistor, and the sixth and seventh switching transistors (T6, T7) as initialization transistors.

[0054] The light-emitting element (EL) may include an anode (or anode electrode) and a cathode (or cathode electrode). The anode electrode of the light-emitting element (EL) may be connected to a fifth node (N5), and the cathode electrode may be connected to a low potential driving voltage (EVSS).

[0055] The driving transistor (DT) may include a first electrode connected to a second node (N2), a second electrode connected to a third node (N3), and a gate electrode connected to a first node (N1). The driving transistor (DT) may provide a driving current to the light-emitting element (EL) corresponding to the voltage of the first node (N1) (or the data voltage (Vdata) stored in the capacitor (Cst) described later).

[0056] The first switching transistor (T1) may include a first electrode connected to a first node (N1), a second electrode connected to a third node (N3), and a gate electrode that receives a first scan signal (SC1(n)). The first transistor (T1) is turned on in response to the first scan signal (SC1(n)) and can sample the threshold voltage (Vth) of the driving transistor (DT) by operating the driving transistor (DT) like a diode by connecting the first node (N1) and the third node (N3). This first switching transistor (T1) may be a compensation transistor.

[0057] A capacitor (Cst) can be connected between the first node (N1) and the fourth node (N4). The capacitor (Cst) can store or maintain a high potential driving voltage (EVDD).

[0058] The second switching transistor (T2) may include a first electrode connected to a data line (DL) (or receiving a data voltage (Vdata)), a second electrode connected to a second node (N2), and a gate electrode receiving a second scan signal (SC2(n)). The second switching transistor (T2) may be turned on in response to the second scan signal (SC2(n)) and may transmit the data voltage (Vdata) to the second node (N2). This second switching transistor (T2) may be a data supply transistor.

[0059] The third switching transistor (T3) and the fourth switching transistor (T4) (or the first and second light-emitting control transistors) are connected between the high potential driving voltage (EVDD) and the light-emitting element (EL), and can form a current path through which the driving current generated by the driving transistor (DT) travels.

[0060] The third switching transistor (T3) may include a first electrode connected to the fourth node (N4) to receive a high potential driving voltage (EVDD), a second electrode connected to the second node (N2), and a gate electrode receiving a light emission control signal (EM(n)).

[0061] The fourth switching transistor (T4) may include a first electrode connected to the third node (N3), a second electrode connected to the fifth node (N5) (or the anode electrode of the light-emitting element (EL)), and a gate electrode that receives a light-emitting control signal (EM(n)).

[0062] The third and fourth switching transistors (T3, T4) are turned on in response to a light emission control signal (EM(n)), in which case a driving current is provided to the light-emitting element (EL), and the light-emitting element (EL) can emit light with a brightness corresponding to the driving current.

[0063] The fifth switching transistor (T5) may include a first electrode receiving a bias voltage (Vobs), a second electrode connected to a second node (N2), and a gate electrode receiving a third scan signal (SC3(n)). This fifth switching transistor (T5) may be a bias transistor.

[0064] The sixth switching transistor (T6) may include a first electrode that receives a first initialization voltage (Var), a second electrode connected to a fifth node (N5), and a gate electrode that receives a third scan signal (SC3(n)).

[0065] The sixth switching transistor (T6) is turned on in response to the third scan signal (SC3(n)) before the light-emitting element (EL) emits light (or after the light-emitting element (EL) emits light), and can initialize the anode electrode (or pixel electrode) of the light-emitting element (EL) using the first initialization voltage (Var). The light-emitting element (EL) may have a parasitic capacitor formed between the anode electrode and the cathode electrode. And while the light-emitting element (EL) emits light, the parasitic capacitor is charged so that the anode electrode of the light-emitting element (EL) can have a specific voltage. Accordingly, by applying the first initialization voltage (Var) to the anode electrode of the light-emitting element (EL) through the sixth switching transistor (T6), the amount of charge accumulated in the light-emitting element (EL) can be initialized.

[0066] In this specification, the gate electrodes of the fifth and sixth switching transistors (T5, T6) are configured to receive the third scan signal (SC3(n)) in common. However, this is not necessarily limited thereto, and the gate electrodes of the fifth and sixth switching transistors (T5, T6) may be configured to be controlled independently according to separate scan signals.

[0067] The seventh switching transistor (T7) may include a first electrode that receives a second initialization voltage (Vini), a second electrode connected to a first node (N1), and a gate electrode that receives a fourth scan signal (SC4(n)).

[0068] The seventh switching transistor (T7) is turned on in response to the fourth scan signal (SC4(n)) and can initialize the gate electrode of the driving transistor (DT) using the second initialization voltage (Vini). Unnecessary charge may remain on the gate electrode of the driving transistor (DT) due to the high potential driving voltage (EVDD) stored in the capacitor (Cst). Therefore, the residual charge can be initialized by applying the second initialization voltage (Vini) to the gate electrode of the driving transistor (DT) through the seventh switching transistor (T7).

[0069] FIGS. 3a and 3b are diagrams for explaining the process of operation of the pixel circuit shown in FIG. 2 according to the scan signal and light emission control signal during the refresh period and the hold period.

[0070] In the embodiments of this specification, another display device may be a display device having a variable refresh rate (VRR) mode. The VRR mode operates at a reference frame frequency, and when high-speed operation is required, increases the refresh rate at which the data voltage (Vdata) is updated above the reference frame frequency to operate the pixels, or when power consumption is reduced or low-speed operation is required, lowers the refresh rate below the reference frame frequency to operate the pixels.

[0071] Each of the plurality of pixels (P) can be driven through a combination of refresh frames and hold frames within 1 second. In this specification, one frame may be defined as a cycle in which a combination of a refresh period in which the data voltage (Vdata) is updated and a hold period in which the data voltage (Vdata) is not updated is repeated for 1 second.

[0072] When the refresh rate is set to 120Hz, it can be driven solely by the refresh period. That is, the refresh period can be driven 120 times within 1 second. One refresh period is 1 / 120 = 8.33ms, and one frame period is also 8.33ms.

[0073] When the refresh rate is driven at 60Hz, the refresh period and the hold period can be driven alternately. That is, the refresh period and the hold period can be driven alternately 60 times each within 1 second. The duration of one refresh period and one hold period is 0.5 / 60 = 8.33ms, and the duration of one frame is 16.66ms.

[0074] When driving at a refresh rate of 1Hz, one frame can be driven with one refresh period and 119 hold periods following one refresh period. The duration of each refresh period and one hold period is 1 / 120 = 8.33ms, and the duration of one frame is 1s.

[0075] The refresh period is when a new data voltage (Vdata) is charged and applied to the driving transistor (DT), whereas the hold period maintains and uses the data voltage (Vdata) of the previous frame. Meanwhile, the hold period may also be referred to as a skip period in the sense that the process of applying a new data voltage (Vdata) to the driving transistor (DT) is omitted.

[0076] Each of the multiple pixels (P) can initialize the voltage charged or remaining within the pixel circuit during the refresh period. Specifically, each of the multiple pixels (P) can remove the influence of the data voltage (Vdata) and high potential driving voltage (EVDD) stored in the previous frame during the refresh period. Accordingly, each of the multiple pixels (P) can display an image corresponding to the new data voltage (Vdata) during the hold period.

[0077] Each of the multiple pixels (P) can provide a driving current corresponding to the data voltage (Vdata) to the light-emitting element (EL) during the hold period to display an image and maintain the turn-on state of the light-emitting element (EL).

[0078] First, the operation of the pixel circuit and the light-emitting element during the refresh period of FIG. 3a will be described. The refresh period may operate by including at least one bias period (Tobs1, Tobs2), an initialization period (Ti), a sampling period (Ts), and a light-emitting period (Te), but this is only one embodiment and is not necessarily bound to this order.

[0079] Referring to FIG. 3a, the pixel circuit may operate by including at least one bias interval (Tobs1, Tobs2) during the refresh period.

[0080] At least one bias section (Tobs1, Tobs2) is a section in which an on-bias stress operation (OBS) is performed with a bias voltage (Vobs) applied, the light emission control signal (EM(n)) is a high voltage, and the third and fourth switching transistors (T3, T4) are turned off. The first scan signal (SC1(n)) and the fourth scan signal (SC4(n)) are low voltages, and the first switching transistor (T1) and the seventh switching transistor (T7) are turned off. The second scan signal (SC2) is a high voltage, and the second switching transistor (T2) is turned off.

[0081] The third scan signal (SC3(n)) is input as a low voltage, and the fifth and sixth switching transistors (T5, T6) are turned on. As the fifth switching transistor (T5) is turned on, a bias voltage (Vobs) is applied to the first electrode of the driving transistor (DT) connected to the second node (N2).

[0082] Here, the bias voltage (Vobs) is supplied to the third node (N3), which is the drain electrode of the driving transistor (DT), thereby reducing the charging time or charging delay of the voltage at the fifth node (N5), which is the anode electrode of the light-emitting element (EL), during the light emission period. The driving transistor (DT) maintains a stronger saturation state.

[0083] For example, as the bias voltage (Vobs) increases, the voltage of the third node (N3), which is the drain electrode of the driving transistor (DT), may increase, and the gate-source voltage or drain-source voltage of the driving transistor (DT) may decrease. Therefore, it is desirable that the bias voltage (Vobs) be at least greater than the data voltage (Vdata).

[0084] At this time, the magnitude of the drain-source current passing through the driving transistor (DT) can be reduced, and the stress on the driving transistor (DT) under positive bias stress conditions can be reduced, thereby eliminating the charging delay of the third node (N3) voltage. In other words, performing an on-bias stress operation (OBS) before sampling the threshold voltage (Vth) of the driving transistor (DT) can alleviate the hysteresis of the driving transistor (DT).

[0085] Accordingly, the on-bias stress operation (OBS) in at least one bias interval (Tobs1, Tobs2) can be defined as an operation of applying a suitable bias voltage to the direct driving transistor (DT) during non-luminous periods.

[0086] In addition, as the sixth switching transistor (T6) is turned on in at least one bias interval (Tobs1, Tobs2), the anode electrode (or pixel electrode) of the light-emitting element (EL) connected to the fifth node (N5) is initialized to the first initialization voltage (Var).

[0087] However, the gate electrodes of the fifth and sixth switching transistors (T5, T6) may be configured to receive separate scan signals and be controlled independently. That is, it is not required that the bias voltage be applied simultaneously to the first electrode of the driving transistor (DT) and the anode electrode of the light-emitting element (EL) during the bias period.

[0088] Referring to FIG. 3a, the pixel circuit may operate including an initialization period (Ti) during the refresh period. The initialization period (Ti) is a period for initializing the voltage of the gate electrode of the driving transistor (DT).

[0089] The first scan signal (SC1(n)) to the fourth scan signal (SC4(n)) and the light emission control signal (EM(n)) are high voltages, and the first switching transistor (T1) and the seventh switching transistor (T7) are turned on. Then, the second to sixth switching transistors (T2, T3, T4, T5, T6) are turned off. As the first and seventh switching transistors (T1, T7) are turned on, the gate electrode and the second electrode of the driving transistor (DT) connected to the first node (N1) are initialized to the second initialization voltage (Vini).

[0090] Referring to FIG. 3a, the pixel circuit may operate including a sampling interval (Ts) during the refresh period. The sampling interval is a period for sampling the threshold voltage (Vth) of the driving transistor (DT).

[0091] The first scan signal (SC1(n)), the third scan signal (SC3(n)), and the light emission control signal (EM(n)) are high voltages, and the second scan signal (SC2(n)) and the fourth scan signal (SC4(n)) are input at low voltages. Accordingly, the third to seventh switching transistors (T3, T4, T5, T6, T7) are turned off, the first switching transistor (T1) remains on, and the second switching transistor (T2) is turned on. That is, the second switching transistor (T2) is turned on so that a data voltage (Vdata) is applied to the driving transistor (DT), and the first switching transistor (T1) is diode-connected between the first node (N1) and the third node (N3) so that the threshold voltage (Vth) of the driving transistor (DT) can be sampled.

[0092] Referring to FIG. 3a, the pixel circuit may operate including a light-emitting section (Te) during the refresh period. The light-emitting section (Te) is a section in which the light-emitting element (EL) emits light with a driving current corresponding to the sampled data voltage and offsets the sampled threshold voltage (Vth).

[0093] The light emission control signal (EM(n)) is a low voltage, and the third and fourth switching transistors (T3, T4) are turned on.

[0094] As the third switching transistor (T3) is turned on, the high potential driving voltage (EVDD) connected to the fourth node (N4) is applied to the first electrode of the driving transistor (DT) connected to the second node (N2) through the third switching transistor (T3). The driving current supplied from the driving transistor (DT) to the light-emitting element (EL) via the fourth switching transistor (T4) is independent of the value of the threshold voltage of the driving transistor (DT), so that the threshold voltage of the driving transistor (DT) can be compensated.

[0095] Next, referring to FIG. 3b, the operation of the pixel circuit and the light-emitting element during the hold period will be explained.

[0096] The hold period may include at least one bias period (Tobs3, Tobs4) and an emission period (Te'). The operation of the pixel circuit identical to the operation of the refresh period will be omitted from the description.

[0097] As described above, the refresh period differs in that a new data voltage (Vdata) is applied to the gate electrode of the driving transistor (DT) by charging a new data voltage (Vdata), whereas the hold period maintains the data voltage (Vdata) of the refresh period. Therefore, unlike the operation of the refresh period, the operation of the hold period does not require an initialization period (Ti) and a sampling period (Ts).

[0098] In the operation during the hold period, the on-bias stress operation (OBS) may be sufficient with just one operation. However, in this embodiment, for the convenience of the driving circuit, the third scan signal (SC3(n)) of the hold period is driven in the same way as the third scan signal (SC3(n)) of the refresh period, and as a result, the on-bias stress operation (OBS) can be operated twice, as in the refresh period.

[0099] The difference between the driving signal during the refresh period described in FIG. 3a and the driving signal during the hold period in FIG. 3b lies in the second and fourth scan signals (SC2(n), SC4(n)). Since the initialization period (Ti) and the sampling period (Ts) are unnecessary during the hold period, unlike in the case of the refresh period, the second scan signal (SC2(n)) is always at a high voltage and the fourth scan signal (SC4(n)) is always at a low voltage. That is, the second and seventh switching transistors (T2, T7) are always off.

[0100] FIG. 4 is a diagram of the configuration of a gate driving unit in a display device of the present specification according to the configuration of a subpixel of FIG. 2.

[0101] Referring to FIG. 4, the gate driver (300) includes a light emission control signal driver (310) and a scan driver (320). The scan driver (320) may be composed of a first scan driver to a fourth scan driver (321, 322, 333, 334). Additionally, the second scan driver (322) may be composed of an odd-numbered second scan driver (322_O) and an even-numbered second scan driver (322_E), respectively.

[0102] The gate driver (300) may include shift registers configured symmetrically on both sides of the display area (AA). Additionally, the gate driver (300) may be configured such that the shift register on one side of the display area (AA) includes a second scan driver (322_O, 322_E), a fourth scan driver (324), and a light emission control signal driver (310), respectively, and the shift register on the other side of the display area (AA) includes a first scan driver (321), a second scan driver (322_O, 322_E), and a third scan driver (323), respectively. However, this is not limited thereto, and the light emission control signal driver (310) and the first to fourth scan drivers (321, 322, 323, 324) may be arranged differently depending on the embodiment.

[0103] Each of the stages (STG1 ~ STGn) of the shift register may include first scan signal generating units (SC1(1) ~ SC1(n)), second scan signal generating units (SC2_O(1) ~ SC2_O(n), SC2_E(1) ~ SC2_E(n)), third scan signal generating units (SC3(1) ~ SC3(n)), fourth scan signal generating units (SC4(1) ~ SC4(n)), and light emission control signal generating units (EM(1) ~ EM(n)).

[0104] The first scan signal generating units (SC1(1) ~ SC1(n)) output first scan signals (SC1(1) ~ SC1(n)) through the first scan lines (SCL1) of the display panel (100). The second scan signal generating units (SC2(1) ~ SC2(n)) output second scan signals (SC2(1) ~ SC2(n)) through the second scan lines (SCL2) of the display panel (100). The third scan signal generating units (SC3(1) ~ SC3(n)) output third scan signals (SC3(1) ~ SC3(n)) through the third scan lines (SCL3) of the display panel (100). The fourth scan signal generating units (SC4(1) ~ SC4(n)) output the fourth scan signals (SC4(1) ~ SC4(n)) through the fourth scan lines (SCL4) of the display panel (100). The light emission control signal generating units (EM(1) ~ EM(n)) output the light emission control signals (EM(1) ~ EM(n)) through the light emission control lines (EML) of the display panel (100).

[0105] The first scan signals (SC1(1) ~ SC1(n)) can be used as signals to drive a first switching transistor (e.g., a compensation transistor) included in the pixel circuit. The second scan signals (SC2(1) ~ SC2(n)) can be used as signals to drive a second switching transistor (e.g., a data supply transistor) included in the pixel circuit. The third scan signals (SC3(1) ~ SC3(n)) can be used as signals to drive a third switching transistor (e.g., a bias transistor) included in the pixel circuit. The fourth scan signals (SC4(1) ~ SC4(n)) can be used as signals to drive a third switching transistor (e.g., an initialization transistor) included in the pixel circuit. The light emission control signals (EM(1) ~ EM(n)) can be used as signals to drive an fourth switching transistor (e.g., a light emission control transistor) included in the pixel circuit. For example, by controlling the light-emitting control transistors of the pixels using light-emitting control signals (EM(1) ~ EM(n)), the light-emitting time of the light-emitting element can be varied.

[0106] Referring to FIG. 4, a bias voltage bus line (VobsL), a first initialization voltage bus line (VarL), and a second initialization voltage bus line (ViniL) may be arranged between the gate driver (300) and the display area (AA).

[0107] The bias voltage bus line (VobsL), the first initialization voltage bus line (VarL), and the second initialization voltage bus line (ViniL) can each receive the bias voltage (Vobs), the first initialization voltage (Var), and the second initialization voltage (Vini) from the power supply unit (500) and supply them to the pixel circuit.

[0108] In FIG. 4, the bias voltage bus line (VobsL), the first initialization voltage bus line (VarL), and the second initialization voltage bus line (ViniL) are each shown as being located only on one side, either the left or the right, of the display area (AA), but are not limited thereto and may be located on both sides, and even if located on one side, the location on the left or the right is not limited.

[0109] Referring to FIG. 4, one or more optical regions (OA1, OA2) may be placed in the display area (AA).

[0110] One or more optical regions (OA1, OA2) may be positioned to overlap with one or more optical electronic devices, such as a camera (image sensor) or a shooting device, a NIR (Near Infrared Radiation) proximity sensor, and an illuminance sensor.

[0111] For the operation of an optical electronic device, one or more optical regions (OA1, OA2) may have a light-transmitting structure formed therein and may have a transmittance of a certain level or higher. In other words, the number of pixels (P) per unit area in one or more optical regions (OA1, OA2) may be smaller than the number of pixels (P) per unit area in the general area excluding the optical regions (OA1, OA2) in the display area (AA). That is, the resolution of one or more optical regions (OA1, OA2) may be lower than the resolution of the general area in the display area (AA).

[0112] In one or more optical regions (OA1, OA2), a light transmission structure can be formed by patterning a cathode electrode in a portion where a pixel (P) is not placed. At this time, the patterned cathode electrode can be removed using a laser, or the cathode electrode can be selectively formed and patterned by using a material such as a cathode deposition prevention layer.

[0113] Additionally, a light transmission structure in one or more optical regions (OA1, OA2) may be formed by separating the light-emitting element (EL) and the pixel circuit in the pixel (P). In other words, the light-emitting element (EL) of the pixel (P) is located on the optical regions (OA1, OA2), and a plurality of transistors (TFTs) constituting the pixel circuit are arranged around the optical regions (OA1, OA2), so that the light-emitting element (EL) and the pixel circuit can be electrically connected through a transparent metal layer.

[0114] When an NIR proximity sensor placed in one or more optical regions (OA1, OA2) described in FIG. 4 is operated and an NIR light source is irradiated onto the transistors of a subpixel configured as in FIG. 2, the OFF current of the transistor increases and the threshold voltage (Vth) of the transistor can be positively shifted.

[0115] In particular, in a subpixel configured as shown in FIG. 2, when an NIR light source is irradiated onto the fifth switching transistor (T5), the off-current of the transistor increases, and the threshold voltage (Vth) of the transistor is positively shifted, which can increase the leakage current of the fifth switching transistor (T5).

[0116] In this way, when the leakage current in the fifth switching transistor (T5) increases, the bias voltage (Vobs) is supplied to the first electrode (second node (N2)) of the driving transistor (DT), causing the gate-source voltage (Vgs) of the driving transistor (DT) to rise.

[0117] In this way, when the NIR proximity sensor operates and the gate-source voltage (Vgs) of the driving transistor (DT) rises, the brightness increases.

[0118] Ultimately, a luminance deviation occurs when the NIR proximity sensor is operating and when the NIR proximity sensor is not operating.

[0119] Therefore, technology is required to ensure that the operation of the NIR proximity sensor does not affect changes in brightness.

[0120] FIG. 5 is a diagram showing the driving waveform of the pixel circuit of FIG. 2 for ensuring that the operation of the NIR proximity sensor according to one embodiment of the present specification does not affect changes in brightness.

[0121] FIGS. 6a to 6e are drawings for explaining the operation of transistors of subpixels in the first bias period (Tobs1), initialization period (Ti), sampling period (Ts), second bias period (Tobs2), and light emission period (Te) of FIG. 5.

[0122] In order to minimize changes in brightness according to the operation of the NIR proximity sensor, a driving method for a display device according to one embodiment of the present specification drives a first scan signal (SC1(n)) to a high level in the first bias interval (Tobs1) described in FIG. 3a.

[0123] To explain this in detail, it is as follows:

[0124] Referring to FIGS. 5 and FIGS. 6a, the pixel circuit can operate including a first bias period (Tobs1).

[0125] The first bias period (Tobs1) is a period in which an on-bias stress operation (OBS) is performed with a bias voltage (Vobs) applied.

[0126] In the first bias period (Tobs1), the light emission control signal (EM(n)) is input as a high level voltage, so the third and fourth switching transistors (T3, T4) are turned off. Since the first scan signal (SC1(n)) is input as a high level voltage and the second scan signal (SC4(n)) is input as a low level voltage, the first switching transistor (T1) is turned on and the second switching transistor (T2) is turned off.

[0127] Since the third scan signal (SC3(n)) is input as a low-level voltage, the fifth and sixth switching transistors (T5, T6) are turned on. As the fifth switching transistor (T5) is turned on, a bias voltage (Vobs) is applied to the first electrode of the driving transistor (DT) connected to the second node (N2).

[0128] Here, the bias voltage (Vobs) is supplied to the third node (N3), which is the drain electrode of the driving transistor (DT), thereby reducing the charging time or charging delay of the voltage at the fifth node (N5), which is the anode electrode of the light-emitting element (EL), during the light emission period. The driving transistor (DT) maintains a stronger saturation state.

[0129] For example, as the bias voltage (Vobs) increases, the voltage of the third node (N3), which is the drain electrode of the driving transistor (DT), may increase, and the gate-source voltage or drain-source voltage of the driving transistor (DT) may decrease. Therefore, it is desirable that the bias voltage (Vobs) be at least greater than the data voltage (Vdata).

[0130] At this time, the magnitude of the drain-source current passing through the driving transistor (DT) can be reduced, and the stress on the driving transistor (DT) under positive bias stress conditions can be reduced, thereby eliminating the charging delay of the third node (N3) voltage. In other words, performing an on-bias stress operation (OBS) before sampling the threshold voltage (Vth) of the driving transistor (DT) can alleviate the hysteresis of the driving transistor (DT).

[0131] As the sixth switching transistor (T6) is turned on by the third scan signal (SC3(n)) in the first bias period (Tobs1), the anode electrode (or pixel electrode) of the light-emitting element (EL) connected to the fifth node (N5) is initialized to the first initialization voltage (Var).

[0132] However, the gate electrodes of the fifth and sixth switching transistors (T5, T6) may be configured to receive separate scan signals and be controlled independently. That is, it is not required that the bias voltage be applied simultaneously to the first electrode of the driving transistor (DT) and the anode electrode of the light-emitting element (EL) during the bias period.

[0133] In addition, since the first scan signal (SC1(n)) is input as a high-level voltage, the first switching transistor (T1) turns on. When the first switching transistor (T1) turns on, the voltage difference between the gate electrode (first node (N1)) and the second electrode (third node (N3)) of the driving transistor disappears (they become equal potential).

[0134] Therefore, due to the leakage current of the fifth switching transistor (T5), the rise in the gate-source voltage (Vgs) of the driving transistor (DT) is mitigated.

[0135] Referring to FIGS. 5 and FIGS. 6b, the pixel circuit may operate including an initialization period (Ti). The initialization period (Ti) is a period for initializing the voltage of the gate electrode of the driving transistor (DT).

[0136] The first scan signal (SC1(n)) to the fourth scan signal (SC4(n)) and the light emission control signal (EM(n)) are input at a high voltage. Accordingly, the first switching transistor (T1) and the seventh switching transistor (T7) are turned on, and the second to sixth switching transistors (T2, T3, T4, T5, T6) are turned off. As the first and seventh switching transistors (T1, T7) are turned on, the gate electrode and the second electrode of the driving transistor (DT) connected to the first node (N1) are initialized to the second initialization voltage (Vini).

[0137] And, since the driving transistor (DT) is turned on by the second initialization voltage (Vini), the first electrode (N2) of the driving transistor (DT) is also initialized with the second initialization voltage (Vini). That is, in the initialization period (Ti), the first node (N1) to the third node (N3) are initialized with the second initialization voltage (Vini).

[0138] Referring to FIGS. 5 and 6c, the pixel circuit can operate including a programming and sampling period (Ts). The programming and sampling period (Ts) is a period for programming data and sampling the threshold voltage (Vth) of the driving transistor (DT).

[0139] The first scan signal (SC1(n)), the third scan signal (SC3(n)), and the light emission control signal (EM(n)) are input at a high voltage, and the second scan signal (SC2(n)) and the fourth scan signal (SC4(n)) are input at a low voltage. Accordingly, the third to seventh switching transistors (T3, T4, T5, T6, T7) are turned off, the first switching transistor (T1) remains on, and the second switching transistor (T2) is turned on. That is, the second switching transistor (T2) is turned on so that a data voltage (Vatat) is applied to the driving transistor (DT), and the first switching transistor (T1) is diode-connected between the first node (N1) and the third node (N3), thereby allowing the threshold voltage (Vth) of the driving transistor (DT) to be sampled.

[0140] Referring to FIGS. 5 and FIGS. 6d, the pixel circuit can operate including a second bias period (Tobs2).

[0141] The second bias period (Tobs2) is a period in which an on-bias stress operation (OBS) is performed with a bias voltage (Vobs) applied.

[0142] In the second bias period (Tobs2), the second scan signal (SC4(n)) and the light emission control signal (EM(n)) are input as high-level voltages, so the second to fourth switching transistors (T3, T4) are turned off.

[0143] Since the first scan signal (SC1(n)), the third scan signal (SC3(n)), and the fourth scan signal (SC4(n)) are input as low-level voltages, the first and seventh switching transistors (T1, T7) are turned off, and the fifth and sixth switching transistors (T5, T6) are turned on. As the fifth switching transistor (T5) is turned on, a bias voltage (Vobs) is applied to the first electrode of the driving transistor (DT) connected to the second node (N2).

[0144] Here, the bias voltage (Vobs) is supplied to the third node (N3), which is the drain electrode of the driving transistor (DT), thereby reducing the charging time or charging delay of the voltage at the fifth node (N5), which is the anode electrode of the light-emitting element (EL), during the light emission period. The driving transistor (DT) maintains a stronger saturation state.

[0145] For example, as the bias voltage (Vobs) increases, the voltage of the third node (N3), which is the drain electrode of the driving transistor (DT), may increase, and the gate-source voltage or drain-source voltage of the driving transistor (DT) may decrease. Therefore, it is desirable that the bias voltage (Vobs) be at least greater than the data voltage (Vdata).

[0146] At this time, the magnitude of the drain-source current passing through the driving transistor (DT) can be reduced, and the stress on the driving transistor (DT) under positive bias stress conditions can be reduced, thereby eliminating the charging delay of the third node (N3) voltage. In other words, performing an on-bias stress operation (OBS) before sampling the threshold voltage (Vth) of the driving transistor (DT) can alleviate the hysteresis of the driving transistor (DT).

[0147] As the sixth switching transistor (T6) is turned on by the third scan signal (SC3(n)) in the second bias period (Tobs3), the anode electrode (or pixel electrode) of the light-emitting element (EL) connected to the fifth node (N5) is initialized to the first initialization voltage (Var).

[0148] Referring to FIGS. 5 and 6e, the pixel circuit may operate including a light-emitting section (Te). The light-emitting section (Te) is a section that offsets the sampled threshold voltage (Vth) and causes the light-emitting element (EL) to emit light with a driving current corresponding to the sampled data voltage.

[0149] Since the first scan signal (SC1(n)), the fourth scan signal (SC4(n)) and the light emission control signal (EM(n)) are input as low voltage, the first and seventh switching transistors (T1, T7) are turned off, and the third and fourth switching transistors (T3, T4) are turned on.

[0150] Since the second scan signal (SC2(n)) and the third scan signal (SC3(n)) are input as high-level voltages, the second, fifth, and sixth switching transistors (T2, T5, T7) are turned off.

[0151] As the third switching transistor (T3) is turned on, the high potential driving voltage (EVDD) connected to the fourth node (N4) is applied to the first electrode of the driving transistor (DT) connected to the second node (N2) through the third switching transistor (T3). The driving current supplied from the driving transistor (DT) to the light-emitting element (EL) via the fourth switching transistor (T4) is independent of the value of the threshold voltage of the driving transistor (DT), so that the threshold voltage of the driving transistor (DT) can be compensated.

[0152] In FIGS. 5 and 6, it is explained that a first scan signal (SC1(n)) is input at a high level voltage in the first bias interval (Tobs1) so that the operation of the NIR proximity sensor does not affect the change in brightness.

[0153] However, not limited to this, even if the first scan signal (SC1(n)) is input at a high level voltage in the interval prior to the programming and sampling interval (Ts), the operation of the NIR proximity sensor can be made so as not to affect the change in brightness.

[0154] Meanwhile, in order to prevent the operation of the NIR proximity sensor from affecting changes in brightness, the bias voltage (Vobs) can be varied to different voltages when the NIR proximity sensor is operating and when the NIR proximity sensor is not operating.

[0155] Electronic devices such as smartphones and tablet PCs equipped with display devices can use synchronization signals input from the outside, for example, a dot clock signal (CLK), a data enable signal (DE), a horizontal synchronization signal (Hsync), and a vertical synchronization signal (Vsync).

[0156] Such electronic devices operate NIR proximity sensors using a synchronization signal (Bsync) similar to the vertical synchronization signal (Vsync) among the synchronization signals.

[0157] That is, the NIR proximity sensor is operated at regular time intervals according to the period of the synchronization signal (Bsync) to detect the proximity of an object. At this time, when the synchronization signal (Bsync) is input, the NIR proximity sensor is operated after a delay time of about 4.5 to 6.25 ms.

[0158] Therefore, the operating time of the NIR proximity sensor can be determined.

[0159] In addition, as described in FIGS. 3a and 3b, the pixel can be operated by increasing the refresh rate at which the data voltage (Vdata) is updated above the reference frame frequency when high-speed operation is required, or by lowering the refresh rate below the reference frame frequency when low-speed operation is required or when power consumption is reduced.

[0160] In order to operate at a variable frequency as described above, it can be driven through a combination of refresh frames and hold frames. In this specification, one frame may be defined as a cycle in which a combination of a refresh period in which the data voltage (Vdata) is updated for 1 second and a hold period in which the data voltage (Vdata) is not updated is repeated.

[0161] Therefore, the bias voltage (Vobs) can be defined corresponding to the refresh period and the hold period. The bias voltage (Vobs) corresponding to the refresh period can be defined as the bias voltage (Vobs_A), and the bias voltage (Vobs) corresponding to the hold period can be defined as the bias voltage (Vobs_B).

[0162] Regarding the bias voltage (Vobs), in an evaluation of the effect of the operation of the NIR proximity sensor on the change in brightness (hereinafter referred to as “NIR Mura”), it was confirmed that for NIR Mura, the bias voltage (Vobs_A) affects both 120Hz and 10Hz, and the bias voltage (Vobs_B) affects 10Hz.

[0163] FIGS. 7a and 7c are graphs showing the relationship between the bias voltage (Vobs_A) and the bias voltage (Vobs_B) according to the present embodiment and the NIR Mura at operating frequencies of 120 Hz and 10 Hz.

[0164] As shown in FIG. 7a, at 120 Hz, NIR Mura is proportional to the bias voltage (Vobs_A), and as shown in FIG. 7b and 7c, at 10 Hz, NIR Mura is proportional to the bias voltage (Vobs_A) and inversely proportional to the bias voltage (Vobs_B).

[0165] According to the results of Figures 7a to 7c, it can be seen that NIR Mura is optimized when the bias voltage (Vobs_A) is 3.0V or less at 120Hz and 3.5V at 10Hz, and NIR Mura is optimized when the bias voltage (Vobs_B) is 5.5V.

[0166] However, since the visibility of the NIR Mura is higher when driven at a low frequency than when driven at a high frequency, in this embodiment, the NIR Mura optimized bias voltage (Vobs_A) and bias voltage (Vobs_B) when driven at 10 Hz can be applied.

[0167] The NIR Mura optimized bias voltage (Vobs_A) and bias voltage (Vobs_B) above are 3.5V and 5.5V, respectively, as described in FIGS. 8a to 8c. This is lower than the typical bias voltage (Vobs_A) and bias voltage (Vobs_B). That is, the typical bias voltage (Vobs_A) and bias voltage (Vobs_B) is about 6-7V.

[0168] FIG. 8 is an example diagram showing the application of NIR Mura optimized bias voltage (Vobs_A) and bias voltage (Vobs_B) on a frame-by-frame basis according to the present embodiment.

[0169] As shown in Fig. 8, the operating time of the NIR proximity sensor is synchronized with the synchronization signal (Vsync) of the display device, and the NIR Mura optimized bias voltage (Vobs_A) and bias voltage (Vobs_B) can be applied on a frame basis according to whether there is a Refresh frame and a Hold frame only during the period when the NIR proximity sensor is operating, by the synchronization signal (Bsync).

[0170] As shown in FIG. 8, during the period in which the NIR proximity sensor operates, the NIR Mura can be minimized by applying a bias voltage (Vobs_A) (e.g., 3.5V) optimized for the NIR Mura to the refresh frame and applying a bias voltage (Vobs_B) (e.g., 5.5V) optimized for the NIR Mura to the hold frame.

[0171] In another embodiment, a method to minimize NIR Mura can be provided by integrating NIR Mura optimized bias voltages (Vobs_A) and (Vobs_B).

[0172] As described in FIGS. 8b to 8c, the deviation between the NIR Mura optimized bias voltage (Vobs_A) and the bias voltage (Vobs_B) is approximately 2.5V (5.5V-3.0V). This can weaken the function of mitigating hysteresis of the driving transistor (DT) by performing an on-bias stress operation (OBS) before sampling the threshold voltage (Vth) of the driving transistor (DT), or cause a brightness deviation during the NIR proximity sensor operation period between the refresh frame and the hold frame, thereby causing flicker.

[0173] To prevent this, additionally, one may consider outputting the optimized bias voltage (Vobs_A) and bias voltage (Vobs_B) of the NIR Mura as a single bias voltage (Vobs).

[0174] That is, by calculating the average value ((3.5V+5.5V) / 2= 4.5V) of the optimized bias voltage (Vobs_A) and bias voltage (Vobs_B) of the NIR Mura, and supplying 4.5V as the bias voltage (Vobs) without distinguishing between refresh frames and hold frames during the time the NIR proximity sensor is operating, the operation of the NIR proximity sensor can be prevented from affecting changes in brightness.

[0175] In the conventional method, a bias voltage (Vobs) of 6-7V is supplied regardless of whether the NIR proximity sensor is operating. Therefore, since the bias voltage (Vobs) supplied during the time the NIR proximity sensor is operating is lower than the bias voltage (Vobs) supplied during the time the NIR proximity sensor is not operating, it is possible to ensure that the operation of the NIR proximity sensor does not affect changes in brightness.

[0176] From the above description, those skilled in the art will understand that various changes and modifications are possible within the scope of the technical concept of this specification. Accordingly, the technical scope of this specification should not be limited to the contents described in the detailed description of the specification, but should be determined by the claims. Explanation of the symbols

[0177] 100: Display panel 300: Gate driver 310: Light emission control signal driver 321, 322, 333, 334: 1st to 4th scan driving units

Claims

Claim 1 A display panel having a plurality of pixels; a gate driver including first to fourth scan driver units and a light emission control signal driver unit; wherein each pixel comprises a driving transistor having a gate electrode, a first electrode receiving a high potential driving voltage, and a second electrode outputting the driving current, a compensation transistor connected between the gate electrode of the driving transistor and the second electrode to compensate for the threshold voltage of the driving transistor, and a bias transistor applying a bias voltage to the driving transistor, wherein each pixel is sequentially driven through a first bias section, an initialization section, a sampling section, a second bias section, and a light emission section during one frame, and prior to the sampling section, the first scan driver outputs a first scan signal to turn on the compensation transistor, and the bias voltage supplied to the bias transistor has different voltage levels depending on whether the NIR proximity sensor is operating. Claim 2 In claim 1, the first scan driving unit outputs a first scan signal to turn on the compensation transistor during a first bias period, a display device. Claim 3 A display panel having a plurality of pixels; a gate driving unit including first to fourth scan driving units and a light emission control signal driving unit; and a display device having an NIR proximity sensor for detecting proximity of an object, wherein each pixel has a driving transistor that controls the driving current of a light-emitting element and a bias transistor, one end of which is connected to the drain terminal of the driving transistor and the other end of which is connected to a bias voltage (Vobs) to apply a bias voltage to the driving transistor to mitigate hysteresis of the driving transistor, and the bias voltage supplied to the bias transistor is supplied at different voltages during the period when the NIR proximity sensor is operating and during the period when the NIR proximity sensor is not operating. Claim 4 In claim 3, the bias voltage supplied to the bias transistor is supplied at a lower voltage during the period when the NIR proximity sensor is operating than during the period when the NIR proximity sensor is not operating. Claim 5 A display device according to claim 3, wherein the bias voltage supplied to the bias transistor is a first bias voltage supplied during a refresh frame, and the first bias voltage is supplied at a lower voltage during the period when the NIR proximity sensor is operating than during the period when the NIR proximity sensor is not operating. Claim 6 In claim 5, the bias voltage supplied to the bias transistor is a second bias voltage supplied during a hold frame, and the second bias voltage is supplied at a lower voltage during the period when the NIR proximity sensor is operating than during the period when the NIR proximity sensor is not operating. Claim 7 In claim 6, the bias voltage supplied to the bias transistor is supplied as the average voltage of the first bias voltage supplied in the refresh frame and the second bias voltage supplied in the hold frame during the period in which the NIR proximity sensor operates. Claim 8 A driving method for a display device comprising: a NIR proximity sensor for detecting the proximity of an object; a driving transistor comprising a gate electrode, a first electrode for receiving a high potential driving voltage, and a second electrode for outputting the driving current, wherein each pixel controls the driving current of a light-emitting element; and a bias transistor comprising one end connected to the first electrode of the driving transistor and the other end connected to a bias voltage (Vobs) for applying a bias voltage to the driving transistor to mitigate hysteresis of the driving transistor, wherein the bias voltage supplied to the bias transistor is supplied at a lower voltage during the period when the NIR proximity sensor is operating than during the period when the NIR proximity sensor is not operating. Claim 9 A driving method for a display device according to claim 8, wherein the bias voltage supplied to the bias transistor is a first bias voltage supplied during a refresh frame, and the first bias voltage is supplied at a lower voltage during the period when the NIR proximity sensor is operating than during the period when the NIR proximity sensor is not operating. Claim 10 A driving method for a display device according to claim 9, wherein the bias voltage supplied to the bias transistor is a second bias voltage supplied during a hold frame, and the second bias voltage is supplied at a lower voltage during the period when the NIR proximity sensor is operating than during the period when the NIR proximity sensor is not operating. Claim 11 A driving method for a display device according to claim 9, wherein the bias voltage supplied to the bias transistor comprises the first bias voltage supplied during the period when the NIR proximity sensor is operating and the second bias voltage supplied during the period when the NIR proximity sensor is not operating, and the second bias voltage has a lower voltage level than the first bias voltage.

Images