Scan Driver and Display apparatus comprising thereof

Abstract

Each of the plurality of stages of a scan driving unit according to one embodiment of the present invention comprises: a first control unit that controls the voltage levels of a first control node and a second control node by means of a first start signal and a second start signal and outputs a first carry signal; a second control unit that controls the voltage levels of a third control node and a fourth control node by means of the first start signal and the second start signal and outputs a second carry signal; and an output unit that includes a pull-up transistor with a gate connected to the first control node and a pull-down transistor with a first gate connected to the third control node, and outputs a scan signal based on an on voltage output through the pull-up transistor and an off voltage output through the pull-down transistor.

Description

Technology Field

[0001] The present invention relates to a scan driving unit and a display device including the same. Background Technology

[0002] The display device includes a pixel unit comprising a plurality of pixels, a scan driving unit, a data driving unit, a control unit, etc. The scan driving unit has stages connected to scan lines, and the stages supply scan signals to the scan lines connected to them in response to signals from the control unit. The problem to be solved

[0003] The present invention aims to provide a scan driving unit capable of stably outputting a scan signal and a display device including the same. The technical problems to be solved by the present invention are not limited to those mentioned above, and other unmentioned technical problems will be clearly understood by those skilled in the art from the description of the present invention. means of solving the problem

[0004] A scan driving unit according to one embodiment of the present invention comprises a plurality of stages, each of the plurality of stages including: a first control unit that controls the voltage levels of a first control node and a second control node by a first start signal and a second start signal and outputs a first carry signal; a second control unit that controls the voltage levels of a third control node and a fourth control node by the first start signal and the second start signal and outputs a second carry signal; and an output unit that includes a pull-up transistor with a gate connected to the first control node and a pull-down transistor with a first gate connected to the third control node, and outputs a scan signal based on an on voltage output through the pull-up transistor and an off voltage output through the pull-down transistor.

[0005] The transistors constituting each of the above plurality of stages may be N-channel oxide thin-film transistors.

[0006] The circuit of the first control unit and the circuit of the second control unit may be symmetrical with respect to a node connected to a terminal that applies an off voltage to the first control unit and the second control unit.

[0007] The pull-up transistor may be connected between a first voltage input terminal to which a first voltage of the on voltage is applied and a first output node to which a first output terminal that outputs the scan signal is connected, and the pull-down transistor may be connected between a third voltage input terminal to which a third voltage of the off voltage is applied and the first output node.

[0008] The first start signal applied to the first stage is a first scan start signal, and the second start signal is an inverted signal of the first start signal, and the first start signal and the second start signal applied to each of the stages after the first stage may be the first carry signal and the second carry signal output by the previous stage.

[0009] The first control unit comprises: a first transistor connected between a first voltage input terminal to which a first on voltage is applied and the first control node, with its gate connected to a first input terminal to which a first start signal is applied; a second transistor connected between the first voltage input terminal and the second control node, with its gate connected to a second input terminal to which a second start signal is applied; a third transistor connected between the first control node and a node to which a second voltage input terminal to which a second off voltage is applied is connected, with its gate connected to the second control node; a fourth transistor connected between the second control node and the node, with its gate connected to the first control node; and a fifth transistor connected between a clock terminal to which a clock signal is applied and a second output node to which a second output terminal that outputs the first carry signal is connected, with its gate connected to the first control node. It may include a sixth transistor connected between the second voltage input terminal and the second output node, with its gate connected to the second control node; a first capacitor connected between the first control node and the second output node; and a second capacitor connected between the second control node and the second voltage input terminal.

[0010] In the first period of the frame, the second start signal is applied as an ON voltage during at least part of the first period, so that the second control node is set to the ON voltage of the first voltage through the second transistor, and the first control node is set to the OFF voltage of the second voltage through the third transistor, and in the second period following the first period, the first start signal is applied as an ON voltage during at least part of the second period, so that the first control node is set to the ON voltage of the first voltage through the first transistor, and the second control node is set to the OFF voltage of the second voltage through the fourth transistor.

[0011] The first control unit can output the first carry signal based on the second voltage output through the sixth transistor during the first period and the clock signal output through the fifth transistor during the second period.

[0012] The clock signal output during the second period may include a plurality of pulses.

[0013] The third transistor includes a pair of subtransistors connected in series between the first control node and the node, and the first control unit may further include a seventh transistor connected between the first voltage input terminal and the intermediate node of the pair of subtransistors.

[0014] The second control unit comprises: an eighth transistor connected between a first voltage input terminal to which a first voltage of the ON voltage is applied and the third control node, with its gate connected to a second input terminal to which the second start signal is applied; a ninth transistor connected between the first voltage input terminal and the fourth control node, with its gate connected to a first input terminal to which the first start signal is applied; a tenth transistor connected between the third control node and a node to which a second voltage input terminal to which a second voltage of the OFF voltage is applied is connected, with its gate connected to the fourth control node; an eleventh transistor connected between the fourth control node and the node, with its gate connected to the third control node; and a twelfth transistor connected between a clock terminal to which a clock signal is applied and a third output node to which a third output terminal outputting the second carry signal is connected, with its gate connected to the third control node. It may include a 13th transistor connected between the second voltage input terminal and the third output node, with its gate connected to the fourth control node; a third capacitor connected between the third control node and the third output node; and a fourth capacitor connected between the fourth control node and the second voltage input terminal.

[0015] In the first period of the frame, the second start signal is applied as an ON voltage during at least part of the first period, so that the third control node is set to the ON voltage of the first voltage through the eighth transistor and the fourth control node is set to the OFF voltage of the second voltage through the eleventh transistor, and in the second period following the first period, the first start signal is applied as an ON voltage during at least part of the second period, so that the fourth control node is set to the ON voltage of the first voltage through the ninth transistor and the third control node is set to the OFF voltage of the second voltage through the tenth transistor.

[0016] The second control unit can output the second carry signal based on the clock signal output through the 12th transistor during the first period and the second voltage output through the 13th transistor during the second period.

[0017] The clock signal output during the first period may include a plurality of pulses.

[0018] The above 10th transistor includes a pair of subtransistors connected in series between the third control node and the node, and the second control unit may further include a 14th transistor connected between the first voltage input terminal and the intermediate node of the pair of subtransistors.

[0019] A display device according to an embodiment of the present invention comprises: a pixel unit including a plurality of pixels, wherein each of the plurality of pixels is connected to a scan line and a data line; and a scan driving unit that outputs a scan signal to the scan line of each of the plurality of pixels; wherein the scan driving unit includes a plurality of stages, and each of the plurality of stages includes: a first control unit that controls the voltage levels of a first control node and a second control node by a first start signal and a second start signal and outputs a first carry signal; a second control unit that controls the voltage levels of a third control node and a fourth control node by the first start signal and the second start signal and outputs a second carry signal; and an output unit that includes a pull-up transistor with a gate connected to the first control node and a pull-down transistor with a first gate connected to the third control node, and outputs a scan signal based on an on voltage output through the pull-up transistor and an off voltage output through the pull-down transistor.

[0020] The transistors constituting the pixel circuits of each of the above pixels and the transistors constituting each of the above stages may be N-channel oxide thin-film transistors.

[0021] The circuit of the first control unit and the circuit of the second control unit may be symmetrical with respect to a node connected to a terminal that applies an off voltage to the first control unit and the second control unit.

[0022] The pull-up transistor may be connected between a first voltage input terminal to which a first voltage of the on voltage is applied and a first output node to which a first output terminal that outputs the scan signal is connected, and the pull-down transistor may be connected between a third voltage input terminal to which a third voltage of the off voltage is applied and the first output node.

[0023] The first start signal applied to the first stage is a first scan start signal, and the second start signal is an inverted signal of the first start signal, and the first start signal and the second start signal applied to each of the stages after the first stage may be the first carry signal and the second carry signal output by the previous stage. Effects of the invention

[0024] According to an embodiment of the present invention, a scan driving unit capable of stably outputting a scan signal and a display device including the same can be provided. The effects of the present invention are not limited to the effects described above and may be extended in various ways within the scope of the spirit of the present invention. Brief explanation of the drawing

[0025] FIG. 1 is a schematic diagram showing a display device according to one embodiment. FIG. 2 is a schematic diagram showing a scan driving unit according to one embodiment. FIG. 3 is a diagram showing the waveforms of some input / output signals applied to the scan drive unit of FIG. 2. FIG. 4 is a circuit diagram showing a stage included in the scan driving unit of FIG. 2 according to one embodiment. Figure 5 is a waveform diagram showing an example of the operation of the stage of Figure 4. FIGS. 6a and FIGS. 6b are equivalent circuit diagrams showing a pixel according to one embodiment. Specific details for implementing the invention

[0026] The present invention is capable of various modifications and may have various embodiments; specific embodiments are illustrated in the drawings and described in detail in the detailed description. The effects and features of the present invention, and the methods for achieving them, will become clear by referring to the embodiments described below in detail together with the drawings. However, the present invention is not limited to the embodiments disclosed below but can be implemented in various forms.

[0027] In the following embodiments, terms such as first, second, etc. are used not in a limiting sense, but for the purpose of distinguishing one component from another component.

[0028] In the following examples, singular expressions include plural expressions unless the context clearly indicates otherwise.

[0029] In the following embodiments, terms such as "include" or "have" mean that the features or components described in the specification are present, and do not preclude the possibility that one or more other features or components may be added.

[0030] In the following embodiments, when a part such as a film, region, or component is described as being on or above another part, it includes not only cases where it is directly on top of another part, but also cases where another film, region, or component is interposed in between.

[0031] In the drawings, the size of components may be exaggerated or reduced for convenience of explanation. For example, the size and thickness of each component shown in the drawings are depicted arbitrarily for convenience of explanation, and therefore the present invention is not necessarily limited to what is illustrated.

[0032] In this specification, "A and / or B" indicates the case where it is A, B, or both A and B. Additionally, in this specification, "at least one of A and B" indicates the case where it is A, B, or both A and B.

[0033] In the following embodiments, when X and Y are described as being connected, the cases may include X and Y being electrically connected, X and Y being functionally connected, or X and Y being directly connected. Here, X and Y may be objects (e.g., devices, components, circuits, wiring, electrodes, terminals, conductive films, layers, etc.). Accordingly, the connection relationships are not limited to a predetermined connection relationship, for example, one indicated in the drawings or detailed description, and may include connection relationships other than those indicated in the drawings or detailed description.

[0034] Cases where X and Y are electrically connected may include, for example, cases where one or more elements that enable electrical connection between X and Y (e.g., switches, transistors, capacitive elements, inductors, resistors, diodes, etc.) are connected between X and Y.

[0035] In the following embodiments, "on" used in association with the device state may refer to the activated state of the device, and "off" may refer to the deactivated state of the device. "On" used in association with the signal received by the device may refer to a signal that activates the device, and "off" may refer to a signal that deactivates the device. The device may be activated by a high-level voltage or a low-level voltage. For example, a P-type transistor is activated (turned on) by a low-level voltage, and an N-type transistor is activated (turned on) by a high-level voltage. Therefore, it should be understood that the "on" voltage for the P-type transistor and the N-type transistor is an opposite (low vs. high) voltage level. Hereinafter, the voltage that turns on the transistor is referred to as the "on voltage," and the voltage that turns off the transistor is referred to as the "off voltage."

[0036] FIG. 1 is a schematic diagram showing a display device according to one embodiment.

[0037] A display device (10) according to one embodiment of the present invention may be a display device such as an organic light-emitting display, an inorganic light-emitting display (inorganic light-emitting display or inorganic EL display), or a quantum dot light-emitting display.

[0038] Referring to FIG. 1, a display device (10) according to one embodiment may include a pixel unit (110), a scan driving unit (130), a data driving unit (150), and a control unit (170).

[0039] In the pixel section (110), a plurality of pixels (PX) and signal lines capable of applying electrical signals to the plurality of pixels (PX) may be arranged. The pixel section (110) may be a display area for displaying an image.

[0040] Multiple pixels (PX) can be repeatedly arranged in a first direction (x-direction, row direction) and a second direction (y-direction, column direction). Multiple pixels (PX) can be arranged in various forms, such as a stripe array, a pentile array, or a mosaic array, to realize an image. Each of the multiple pixels (PX) includes an organic light-emitting diode as a display element, and the organic light-emitting diode can be connected to a pixel circuit. The pixel circuit may include multiple transistors and at least one capacitor. In one embodiment, the multiple transistors included in the pixel circuit may be N-type thin-film transistors. The N-type thin-film transistor may be an oxide thin-film transistor in which the active pattern (semiconductor layer) includes an amorphous or crystalline oxide. The oxide thin-film transistor has excellent off-current characteristics.

[0041] Signal lines capable of applying electrical signals to multiple pixels (PX) may include multiple scan lines (SL) extended in a first direction and multiple data lines (DL) extended in a second direction. Multiple scan lines (SL) are spaced apart along the second direction and can transmit scan signals to the pixels (PX). Multiple data lines (DL) are spaced apart along the first direction and can transmit data signals to the pixels (PX). Each of the multiple pixels (PX) may be connected to at least one corresponding scan line among the multiple scan lines (SL) and a corresponding data line among the multiple data lines (DL). In FIG. 1, for convenience of illustration, one scan line is shown connected to a pixel (PX), but each pixel (PX) may be connected to multiple scan lines depending on the number of transistors constituting the pixel circuit.

[0042] The scan driving unit (130) is connected to a plurality of scan lines (SL) and can generate a scan signal in response to a control signal (SCS) from the control unit (170) and supply it sequentially to the scan lines (SL). The scan lines (SL) are connected to the gate of a transistor included in the pixel circuit, and the scan signal can transmit the scan signal to the gate of the transistor. The scan signal may be a square wave signal in which an on voltage that can turn on the transistor and an off voltage that can turn off the transistor are repeated. In one embodiment, the on voltage may be a high-level voltage (hereinafter referred to as 'high voltage').

[0043] The data driving unit (150) is connected to a plurality of data lines (DL) and can supply a data signal to the data lines (DL) in response to a control signal (DCS) from the control unit (170). The data signal supplied to the data lines (DL) can be supplied to pixels (PX) to which a scan signal is supplied. To this end, the data driving unit (150) can supply a data signal to the data lines (DL) so as to be synchronized with the scan signal.

[0044] The control unit (170) can generate a scan control signal (SCS) and a data control signal (DCS) based on signals input from the outside. The control unit (170) can supply the scan control signal (SCS) to the scan drive unit (130) and supply the data control signal (DCS) to the data drive unit (150).

[0045] FIG. 2 is a schematic diagram showing a scan driving unit according to one embodiment. FIG. 3 is a diagram showing the waveforms of some input / output signals applied to the scan driving unit of FIG. 2.

[0046] Referring to FIG. 2, the scan driving unit (130) may include a plurality of first to nth stages (ST1 to STn). Each of the first to nth stages (ST1 to STn) may correspond to a pixel row (pixel line) provided in the pixel unit (110). The number of stages of the scan driving unit (130) may vary depending on the number of pixel rows.

[0047] Each of the plurality of first to nth stages (ST1 to STn) may include a first input terminal (IN1), a second input terminal (IN2), a clock terminal (CK), a first voltage input terminal (V1), a second voltage input terminal (V2), a third voltage input terminal (V3), a first output terminal (OUT1), a second output terminal (OUT2), and a third output terminal (OUT3).

[0048] The first input terminal (IN1) can receive a first scan start signal (STV1) or a previous first carry signal as a first start signal. In one embodiment, the first scan start signal (STV1) is applied to the first input terminal (IN1) of the first stage (ST1), and the first carry signal output by the previous stage can be applied to the first input terminal (IN1) of each of the second to nth stages (ST2 to STn) following the first stage (ST1). The second input terminal (IN2) can receive a second scan start signal (STV2) or a previous second carry signal as a second start signal. In one embodiment, a second scan start signal (STV2) is applied to the second input terminal (IN2) of the first stage (ST1), and a second carry signal output by the previous stage may be applied to the second input terminal (IN2) of each of the second to nth stages (ST2 to STn) following the first stage (ST1). For example, the first stage (ST1) may start driving by the first scan start signal (STV1) and the second scan start signal (STV2) and generate and output a first output signal (Out[1]). The first carry signal (CRA[n-1]) and the second carry signal (CRB[n-1]) output from the n-1 stage are input to the first input terminal (IN1) and the second input terminal (IN2) of the n-th stage (STn), and the n-th stage (STn) can generate and output the n-th output signal (Out[n]).

[0049] As illustrated in FIG. 3, the first scan start signal (STV1) and the second scan start signal (STV2) may be signals in which a low-level voltage (hereinafter referred to as 'low voltage') and a high voltage alternate. The first scan start signal (STV1) and the second scan start signal (STV2) may have one low voltage period and one high voltage period during one frame. The second scan start signal (STV2) may be an inverted signal of the first scan start signal (STV1). Here, a frame (frame interval) may be a period for displaying a single frame image.

[0050] A clock terminal (CK) can receive a first clock signal (CLK1) or a second clock signal (CLK2). The first clock signal (CLK1) and the second clock signal (CLK2) can be applied alternately to the first to nth stages (ST1 to STn). For example, the first clock signal (CLK1) may be applied to the clock terminal (CK) of an odd-numbered stage, and the second clock signal (CLK2) may be applied to the clock terminal (CK) of an even-numbered stage. As illustrated in FIG. 3, the first clock signal (CLK1) and the second clock signal (CLK2) may be square wave signals that repeat high voltage and low voltage. The first clock signal (CLK1) and the second clock signal (CLK2) may be signals that have the same waveform but are phase-shifted. For example, the second clock signal (CLK2) may be an inverted signal having the same waveform as the first clock signal (CLK1) and a 180-degree phase difference (1 / 2 cycle phase difference). That is, the pulses (high voltage periods) of the first clock signal (CLK1) and the second clock signal (CLK2) may not overlap.

[0051] The first voltage input terminal (V1) can receive a first voltage (VGH) which is a high voltage, the second voltage input terminal (V2) can receive a second voltage (VGL1) which is a low voltage, and the third voltage input terminal (V3) can receive a third voltage (VGL2) which is a low voltage. The third voltage (VGL2) may be a lower voltage than the second voltage (VGL1). The first voltage (VGH), the second voltage (VGL1), and the third voltage (VGL2) may be supplied as global signals from a control unit (170) shown in FIG. 1 and / or a power supply unit not shown, etc.

[0052] The first output terminal (OUT1) can output an output signal. The output signal can be supplied to a pixel through a corresponding scan line. The second output terminal (OUT2) can output a first carry signal. The third output terminal (OUT3) can output a second carry signal.

[0053] A plurality of first to nth stages (ST1 to STn) can output first to nth output signals (Out[1], Out[2], Out[3], Out[4], ..., Out[n]) in response to a first start signal and a second start signal. Here, the output signal output by each of the first to nth stages (ST1 to STn) may be a scan signal. The first to nth output signals (Out[1], Out[2], Out[3], Out[4], ..., Out[n]) may be output sequentially, shifted by the phase difference between the first clock signal (CLK1) and the second clock signal (CLK2).

[0054] Each of the first carry signals (CRA[1], CRA[2], CRA[3], CRA[4], ...) output from the second output terminals (OUT2) of the first to nth stages (ST1 to STn) can be applied to the first input terminal (IN1) of the subsequent stage. Each of the second carry signals (CRB[1], CRB[2], CRB[3], CRB[4], ...) output from the third output terminals (OUT3) of the first to nth stages (ST1 to STn) can be applied to the second input terminal (IN2) of the subsequent stage. In one embodiment, the first carry signal and the second carry signal output from the second output terminal (OUT2) and the third output terminal (OUT3) of the last nth stage (STn) can be applied to a subsequent dummy stage not shown.

[0055] FIG. 4 is a circuit diagram showing a stage included in the scan driving unit of FIG. 2 according to one embodiment. FIG. 5 is a waveform diagram showing an example of the operation of the stage of FIG. 4.

[0056] Each of the first to nth stages (ST1 to STn) has a plurality of nodes, and hereinafter, some of the nodes among the plurality of nodes are referred to as the first to third output nodes (N1 to N3) and the first to fourth control nodes (A, B, C, D).

[0057] Hereinafter, the k-th stage (STk) that outputs the k-th output signal (Out[k]) to the k-th row of the pixel section (110) is described as an example. In one embodiment, a plurality of transistors included in the circuits of each of the first to n-th stages (ST1 to STn) may be N-type thin-film transistors. The N-type thin-film transistors may be oxide thin-film transistors.

[0058] The k-th stage (STk, k is a natural number) illustrated in FIG. 4 may include a first control unit (210), a second control unit (230), and an output unit (250).

[0059] The first control unit (210) and the second control unit (230) may be circuits that are vertically symmetrical with respect to the node (E). The input signals of the first control unit (210) and the second control unit (230), respectively, may include a first start signal, a second start signal, a clock signal (CLK), a first voltage (VGH), a second voltage (VGL1), and a third voltage (VGL2). In the case of the first stage (ST1), the first start signal and the second start signal may be a first scan start signal (STV1) and a second scan start signal (STV2). In the case of the second to nth stages (ST2 to STn), the first start signal and the second start signal may be a first carry signal (CRA[i]) and a second carry signal (CRB[i]) output by the previous stage.

[0060] The first control unit (210) can control the voltage of the first control node (A) and the second control node (B) based on input signals. Depending on the voltage of the first control node (A) and the second control node (B), the first control unit (210) can generate a first carry signal (CRA[k]) based on a clock signal (CLK) or a second voltage (VGL1) and output it to the second output terminal (OUT2) connected to the second output node (N2).

[0061] The first control unit (210) may include a first transistor (TR1), a second transistor (TR2), a third transistor (TR3), a fourth transistor (TR4), a fifth transistor (TR5), a sixth transistor (TR6), a first capacitor (C1), and a second capacitor (C2). The first control unit (210) may further include a seventh transistor (TR7).

[0062] The first transistor (TR1) can be connected between the first voltage input terminal (V1) and the first control node (A). The gate of the first transistor (TR1) can be connected to the first input terminal (IN1).

[0063] The second transistor (TR2) can be connected between the first voltage input terminal (V1) and the second control node (B). The gate of the second transistor (TR2) can be connected to the second input terminal (IN2).

[0064] The third transistor (TR3) may be connected between the first control node (A) and the node (E). The third transistor (TR3) may include a pair of subtransistors connected in series between the first control node (A) and the node (E). In one embodiment, the third transistor (TR3) may include a third-1 transistor (TR3-1) and a third-2 transistor (TR3-2). The gates of the third-1 transistor (TR3-1) and the third-2 transistor (TR3-2) may be connected to the second control node (B).

[0065] The fourth transistor (TR4) can be connected between the second control node (B) and the node (E). The gate of the fourth transistor (TR4) can be connected to the first control node (A).

[0066] The fifth transistor (TR5) can be connected between the clock terminal (CK) and the second output node (N2). The gate of the fifth transistor (TR5) can be connected to the first control node (A). The fifth transistor (TR5) can be turned on or turned off depending on the voltage of the first control node (A). When the first control node (A) is set to a high voltage, the fifth transistor (TR5) is turned on so that the clock signal (CLK) can be output to the second output terminal (OUT2) as the first carry signal (CRA[k]) through the fifth transistor (TR5).

[0067] The sixth transistor (TR6) can be connected between the node (E) and the second output node (N2). The gate of the sixth transistor (TR6) can be connected to the second control node (B). The sixth transistor (TR6) can be turned on or turned off depending on the voltage of the second control node (B). When the second control node (B) is set to a high voltage, the sixth transistor (TR6) is turned on so that the second voltage (VGL1) can be output to the second output terminal (OUT2) as the first carry signal (CRA[k]) through the sixth transistor (TR6).

[0068] The seventh transistor (TR7) can be connected between the intermediate node (common electrode) of the third-1 transistor (TR3-1) and the third-2 transistor (TR3-2) and the first voltage input terminal (V1). The gate of the seventh transistor (TR7) can be connected to the first control node (A). When the seventh transistor (TR7) is turned on, a first voltage (VGH) is applied to the intermediate node of the third-1 transistor (TR3-1) and the third-2 transistor (TR3-2), thereby minimizing current leakage from the first control node (A) through the third transistor (TR3).

[0069] The first capacitor (C1) can be connected between the first control node (A) and the second output node (N2). When the fifth transistor (TR5) is turned on, the voltage of the first control node (A) can be bootstrapped by the first capacitor (C1). The second capacitor (C2) can be connected between the second control node (B) and the node (E).

[0070] The second control unit (230) can control the voltages of the third control node (C) and the fourth control node (D) based on input signals. Depending on the voltages of the third control node (C) and the fourth control node (D), the second control unit (230) can generate a second carry signal (CRB[k]) based on a clock signal (CLK) or a second voltage (VGL1) and output it to the third output terminal (OUT3) connected to the third output node (N3).

[0071] The second control unit (230) may include an eighth transistor (TR8), a ninth transistor (TR9), a tenth transistor (TR10), an eleventh transistor (TR11), a twelfth transistor (TR12), a thirteenth transistor (TR13), a third capacitor (C3), and a fourth capacitor (C4). The second control unit (230) may further include a fourteenth transistor (TR14).

[0072] The eighth transistor (TR8) can be connected between the first voltage input terminal (V1) and the third control node (C). The gate of the eighth transistor (TR8) can be connected to the second input terminal (IN2).

[0073] The ninth transistor (TR9) can be connected between the first voltage input terminal (V1) and the fourth control node (D). The gate of the ninth transistor (TR9) can be connected to the first input terminal (IN1).

[0074] The tenth transistor (TR10) may be connected between the third control node (C) and the node (E). The tenth transistor (TR10) may include a pair of subtransistors connected in series between the third control node (C) and the node (E). In one embodiment, the tenth transistor (TR10) may include a ten-1 transistor (TR10-1) and a ten-2 transistor (TR10-2). The gates of the ten-1 transistor (TR10-1) and the ten-2 transistor (TR10-2) may be connected to the fourth control node (D).

[0075] The eleventh transistor (TR11) can be connected between the fourth control node (D) and node (E). The gate of the eleventh transistor (TR11) can be connected to the third control node (C).

[0076] The 12th transistor (TR12) can be connected between the clock terminal (CK) and the third output node (N3). The gate of the 12th transistor (TR12) can be connected to the third control node (C). The 12th transistor (TR12) can be turned on or turned off depending on the voltage of the third control node (C). When the third control node (C) is set to a high voltage, the 12th transistor (TR12) is turned on so that the clock signal (CLK) can be output to the third output terminal (OUT3) as the second carry signal (CRB[k]) through the 12th transistor (TR12).

[0077] The 13th transistor (TR13) can be connected between the node (E) and the third output node (N3). The gate of the 13th transistor (TR13) can be connected to the fourth control node (D). The 13th transistor (TR13) can be turned on or turned off depending on the voltage of the fourth control node (D). When the fourth control node (D) is set to a high voltage, the 13th transistor (TR13) is turned on so that the second voltage (VGL1) can be output to the third output terminal (OUT3) as the second carry signal (CRB[k]) through the 13th transistor (TR13).

[0078] The 14th transistor (TR14) can be connected between the intermediate node (common electrode) of the 10-1 transistor (TR10-1) and the 10-2 transistor (TR10-2) and the first voltage input terminal (V1). The gate of the 14th transistor (TR14) can be connected to the third control node (C). When the 14th transistor (TR14) is turned on, a first voltage (VGH) is applied to the intermediate node of the 10-1 transistor (TR10-1) and the 10-2 transistor (TR10-2), thereby minimizing current leakage from the third control node (C) through the 10th transistor (TR10).

[0079] The third capacitor (C3) can be connected between the third control node (C) and the third output node (N3). When the 12th transistor (TR12) is turned on, the voltage of the third control node (C) can be bootstrapped by the third capacitor (C3). The fourth capacitor (C4) can be connected between the fourth control node (D) and the node (E).

[0080] The output unit (250) can output a first voltage (VGH) or a third voltage (VGL2) to a first output terminal (OUT1) connected to a first output node (N1) depending on the voltages of the first control node (A) and the third control node (C). The first control node (A) and the third control node (C) can be alternately set to ON voltage on a frame-by-frame basis.

[0081] The output section (250) may include a 15th transistor (TR15) as a pull-up transistor for outputting a high voltage and a 16th transistor (TR16) as a pull-down transistor for outputting a low voltage. The 15th transistor (TR15) may be turned on or turned off by the first control section (210). The 16th transistor (TR16) may be turned on or turned off by the second control section (230). The 15th transistor (TR15) and the 16th transistor (TR16) may be turned on alternately on a frame basis.

[0082] The 15th transistor (TR15) can be connected between the first voltage input terminal (V1) and the first output node (N1). The gate of the 15th transistor (TR15) can be connected to the first control node (A). The 15th transistor (TR15) can be turned on or turned off depending on the voltage of the first control node (A). When the first control node (A) is set to a high voltage, the 15th transistor (TR15) is turned on, and the first voltage (VGH) of the high voltage can be output to the first output terminal (OUT1) as the k-th output signal (Out[k]) through the 15th transistor (TR15).

[0083] The 16th transistor (TR16) can be connected between the third voltage input terminal (V3) and the first output node (N1). The gate of the 16th transistor (TR16) can be connected to the third control node (C). The 16th transistor (TR16) can be turned on or turned off depending on the voltage of the third control node (C). When the third control node (C) is set to a high voltage, the 16th transistor (TR16) is turned on, and a third voltage (VGL2) of low voltage can be output to the first output terminal (OUT1) as the k-th output signal (Out[k]) through the 16th transistor (TR16).

[0084] FIG. 5 illustrates the previous first carry signal (CRA[i]) and previous second carry signal (CRB[i]), clock signal (CLK), node voltages of the first to fourth control nodes (A, B, C, D), the first carry signal (CRA[k]), the second carry signal (CRB[k]), and the output signal (Out[k]) as start signals.

[0085] The previous first carry signal (CRA[i]) and the previous second carry signal (CRB[i]) are the first carry signal and the second carry signal output by the preceding stage, and the preceding stage may be at least one preceding stage. For example, as shown in FIGS. 4 and 5, the previous first carry signal (CRA[i]) and the previous second carry signal (CRB[i]) may be signals output by one preceding stage.

[0086] The clock signal (CLK) may be a first clock signal (CLK1) or a second clock signal (CLK2).

[0087] The high voltage may be the on voltage, and the low voltage may be the off voltage. The operation of the stage in one frame will be explained below with reference to FIG. 5. One frame may include a first period (P1) in which a scan signal of the off voltage is output and a second period (P2) in which a scan signal of the on voltage is output.

[0088] During the first period (P1), the first control node (A) and the fourth control node (D) can be set to an off voltage, and the second control node (B) and the third control node (C) can be set to an on voltage.

[0089] During the first period (P1), a first carry signal (CRA[i]) of low voltage is applied to the first input terminal (IN1), and a second carry signal (CRB[i]) having the waveform of a clock signal (CLK) can be applied to the second input terminal (IN2). The second carry signal (CRB[i]) applied as the waveform of a clock signal (CLK) during the first period (P1) includes a plurality of pulses and can be applied as a high voltage in at least a part of the first period (P1).

[0090] The second transistor (TR2) of the first control unit (210) and the eighth transistor (TR8) of the second control unit (230) can be repeatedly turned on and off by the second carry signal (CRB[i]) which repeats high voltage and low voltage. When the second transistor (TR2) and the eighth transistor (TR8) are turned on by the high voltage of the second carry signal (CRB[i]), the first voltage (VGH) is transmitted to the second control node (B) and the third control node (C), so that the second control node (B) and the third control node (C) can be set to a high voltage. When the second transistor (TR2) and the eighth transistor (TR8) are turned off by the low voltage of the second carry signal (CRB[i]), the second control node (B) and the third control node (C) can maintain a high voltage.

[0091] The 14th transistor (TR14), whose gate is connected to the 3rd control node (C), is turned on so that a high voltage can be transmitted to the intermediate node of the 10th transistor (TR10).

[0092] By the first carry signal (CRA[i]) of the low voltage, the first transistor (TR1) of the first control unit (210) and the ninth transistor (TR9) of the second control unit (230) are turned off, and the third transistor (TR3) and the eleventh transistor (TR11), whose gates are connected to the second control node (B) and the third control node (C) set to a high voltage, can be turned on. Accordingly, the second voltage (VGL1) is transmitted to the first control node (A) through the third transistor (TR3), and the second voltage (VGL1) is transmitted to the fourth anode (D) through the eleventh transistor (TR11), so that the first control node (A) and the fourth control node (D) can be set to a low voltage. The fourth transistor (TR4) and the tenth transistor (T10), whose gates are connected to the first control node (A) and the fourth control node (D), may be turned off.

[0093] The 16th transistor (TR16) of the output unit (250), the 6th transistor (TR6) of the first control unit (210), and the 12th transistor (TR12) of the second control unit (230), which have gates connected to the second control node (B) and the third control node (C) which are high voltages, can each be turned on. The third voltage (VGL2) can be transmitted to the first output node (N1) through the 16th transistor (TR16), the second voltage (VGL1) can be transmitted to the second output node (N2) through the 6th transistor (TR6), and the clock signal (CLK) can be transmitted to the third output node (N3) through the 12th transistor (TR12). Accordingly, the output unit (250) outputs a k-th output signal (Out[k]) of low voltage through the first output terminal (OUT1), the first control unit (210) outputs a first carry signal (CRA[k]) of low voltage through the second output terminal (OUT2), and the second control unit (230) outputs a second carry signal (CRB[k]) following the waveform of a clock signal (CLK) through the third output terminal (OUT3).

[0094] During the first period (P1), the transistor of the pixel circuit that receives the k-th output signal (Out[k]) of low voltage as its gate can be turned off.

[0095] During the second period (P2), the first control node (A) and the fourth control node (D) can be set to an ON voltage, and the second control node (B) and the third control node (C) can be set to an OFF voltage.

[0096] During the second period (P2), a first carry signal (CRA[i]) having the waveform of a clock signal (CLK) may be applied to the first input terminal (IN1), and a second carry signal (CRB[i]) of low voltage may be applied to the second input terminal (IN2). The first carry signal (CRA[i]) applied as the waveform of a clock signal (CLK) during the second period (P2) may include a plurality of pulses and may be applied as a high voltage in at least a portion of the second period (P2).

[0097] The first transistor (TR1) of the first control unit (210) and the ninth transistor (TR9) of the second control unit (230) can be repeatedly turned on and off by the first carry signal (CRA[i]) which repeats high voltage and low voltage. When the first transistor (TR1) and the ninth transistor (TR9) are turned on by the high voltage of the first carry signal (CRA[i]), the first voltage (VGH) is transmitted to the first control node (A) and the fourth control node (D), so that the first control node (A) and the fourth control node (D) can be set to a high voltage. When the first transistor (TR1) and the ninth transistor (TR9) are turned off by the low voltage of the first carry signal (CRA[i]), the first control node (A) and the fourth control node (D) can maintain a high voltage. The seventh transistor (TR7), whose gate is connected to the first control node (A), is turned on so that a high voltage can be transmitted to the intermediate node of the third transistor (TR3).

[0098] By the second carry signal (CRB[i]) of the low voltage, the second transistor (TR2) of the first control unit (210) and the eighth transistor (TR8) of the second control unit (230) are turned off, and the fourth transistor (TR4) and the tenth transistor (TR10), whose gates are connected to the first control node (A) and the fourth control node (D) set to a high voltage, can be turned on. Accordingly, the second voltage (VGL1) is transmitted to the second control node (B) through the fourth transistor (TR4), and the second voltage (VGL1) is transmitted to the third control node (C) through the tenth transistor (TR10), so that the second control node (B) and the third control node (C) can be set to a low voltage. The third transistor (TR3) and the eleventh transistor (T11), whose gates are connected to the second control node (B) and the third control node (C), may be turned off.

[0099] The 15th transistor (TR15) of the output unit (250), whose gate is connected to the 1st control node (A) which is a high voltage, the 5th transistor (TR5) of the 1st control unit (210), and the 13th transistor (TR13) of the 2nd control unit (230), whose gate is connected to the 4th control node (D) which is a high voltage, can each be turned on. The 1st voltage (VGH) can be transmitted to the 1st output node (N1) through the 15th transistor (TR15), the clock signal (CLK) can be transmitted to the 2nd output node (N2) through the 5th transistor (TR5), and the 2nd voltage (VGL1) can be transmitted to the 3rd output node (N3) through the 13th transistor (TR13). Accordingly, the output unit (250) outputs a k-th output signal (Out[k]) of high voltage through the first output terminal (OUT1), the first control unit (210) outputs a first carry signal (CRA[k]) following the waveform of a clock signal (CLK) through the second output terminal (OUT2), and the second control unit (230) outputs a second carry signal (CRB[k]) of low voltage through the third output terminal (OUT3).

[0100] When the first control node (A) and the third control node (C) are at high voltage, the voltage level is boosted by the first capacitor (C1) and the third capacitor (C3), respectively, and can be higher than the voltage level when the second control node (B) and the fourth control node (D) are at high voltage.

[0101] In the second period (P2), the transistor of the pixel circuit that receives the k-th output signal (Out[k]) of high voltage as its gate can be turned on.

[0102] In FIG. 5, the length of the second period (P2) is shown as being longer than the first period (P1), but this is exemplary, and the lengths of the first period (P1) and the second period (P2) can be adjusted according to the function performed by the transistor of the pixel circuit receiving the output signal in the pixel circuit.

[0103] FIGS. 6a and FIGS. 6b are equivalent circuit diagrams showing a pixel according to one embodiment.

[0104] Referring to FIG. 6a, the pixel (PX) may include a pixel circuit (PC) and an organic light-emitting diode (OLED) as a display element connected to the pixel circuit (PC). The pixel circuit (PC) includes a first transistor (T1), a second transistor (T2), a third transistor (T3), a fourth transistor (T4), and a capacitor (Cst). The first transistor (T1) is a driving transistor in which the magnitude of the source-drain current is determined according to the gate-source voltage, and the second to fourth transistors (T2 to T4) may be switching transistors that are turned on / off according to the gate voltage.

[0105] The first transistor (T1) includes a gate connected to the first node (Na), a first terminal connected to the second node (Nb), and a second terminal connected to the third node (Nc). The first terminal of the first transistor (T1) is connected to a driving voltage line that supplies a first power supply voltage (ELVDD) via the fourth transistor (T4), and the second terminal can be connected to the first electrode (pixel electrode, anode) of the organic light-emitting diode (OLED). The first transistor (T1) acts as a driving transistor and can control the amount of driving current flowing to the organic light-emitting diode (OLED) by receiving a data signal (DATA) according to the switching operation of the second transistor (T2).

[0106] The second transistor (T2) (data writing transistor) includes a gate connected to the first scan line (SL1), a first terminal connected to the data line (DL), and a second terminal connected to the first node (Na) (or the gate of the first transistor (T1). The second transistor (T2) is turned on according to a scan signal (SC) input through the first scan line (SL1) to electrically connect the data line (DL) and the first node (Na), and can transmit a data signal (DATA) input through the data line (DL) to the first node (Na).

[0107] The third transistor (T3) (initialization transistor) includes a gate connected to the second scan line (SL2), a first terminal connected to the third node (Nc) (or the second terminal of the first transistor (T1)), and a second terminal connected to an initialization voltage line that supplies an initialization voltage (INT). The third transistor (T3) is turned on by a scan signal (SS) supplied to the second scan line (SL2) and can transmit the initialization voltage (INT) transmitted to the initialization voltage line to the third node (Nc).

[0108] The fourth transistor (T4) (light-emitting control transistor) includes a gate connected to the third scan line (SL3), a first terminal connected to the driving voltage line, and a second terminal connected to the second node (Nb) (or the first terminal of the first transistor (T1)). The fourth transistor (T4) is turned on according to the scan signal (EM) transmitted through the third scan line (SL3), so that current flows through the organic light-emitting diode (OLED).

[0109] A capacitor (Cst) can be connected between the first node (Na) and the second terminal of the first transistor (T1). The capacitor (Cst) can store a voltage corresponding to the difference between the voltage received from the second transistor (T2) and the potential of the second terminal of the first transistor (T1).

[0110] An organic light-emitting diode (OLED) may include a first electrode (pixel electrode, anode) connected to the second terminal of a first transistor (T1) and a second electrode (counter electrode, cathode) to which a second power supply voltage (ELVSS), which is a common voltage, is applied. The organic light-emitting diode (OLED) may emit light having a predetermined brightness by a driving current supplied from the first transistor (T1).

[0111] In another embodiment, the fourth transistor (T4) may be connected between the first transistor (T1) and the organic light-emitting diode (OLED). For example, as in the pixel circuit (PC) shown in FIG. 6b, the fourth transistor (T4) may include a gate connected to the third scan line (SL3), a first terminal connected to the third node (Nc), and a second terminal connected to the first electrode of the organic light-emitting diode (OLED).

[0112] In FIG. 6a and 6b, the first to fourth transistors (T1 to T4) of the pixel circuit (PC) may be N-type transistors. For example, the first to fourth transistors (T1 to T4) may be oxide thin-film transistors.

[0113] In one embodiment, each stage of the scan driver (130) shown in FIG. 2 may be connected to one of the first to third scan lines (SL1 to SL3) connected to the gates of the second to fourth transistors (T2 to T4) of the pixel circuit (PC) shown in FIG. 6a and 6b. The output signal output from the first output terminal (OUT1) of each stage of the scan driver (130) shown in FIG. 2 may be one of the scan signals (SC, SS, EM) applied to the first to third scan lines (SL1 to SL3). For example, each stage of the scan driver (130) shown in FIG. 2 may be connected to the third scan line (SL3) of the pixel circuit (PC) shown in FIG. 6a and 6b provided in the corresponding row, and may output an output signal as a scan signal (EM) to the third scan line (SL3). Accordingly, a scan signal (EM) can be supplied to the gate of the fourth transistor (T4) of the pixel circuit (PC).

[0114] When a high-voltage scan signal (EM) is supplied, that is, when the stage outputs a high-voltage output signal, the fourth transistor (T4) is turned on so that the organic light-emitting diode (OLED) can emit light. In other words, the second period (P2) of FIG. 5 may be the light-emitting period. When a low-voltage scan signal (EM) is supplied, that is, when the stage outputs a low-voltage output signal, the fourth transistor (T4) is turned off so that the organic light-emitting diode (OLED) does not emit light. In other words, the first period (P1) of FIG. 5 may be the non-light-emitting period. In this case, the second period (P2) may be longer than the first period (P1).

[0115] The pixel circuit (PC) illustrated in FIGS. 6a and 6b is exemplary, and various pixel circuits (PC) including at least one transistor to which at least one scan signal is applied may be applied to embodiments of the present invention. For example, the pixel circuit (PC) of a pixel (PX) includes a first transistor (T1) which is a driving transistor, a second transistor (T2) which transmits a data signal, and a fourth transistor (T4) which controls the light emission of an organic light-emitting diode (OLED), and the third transistor (T3) may be omitted, or at least one additional transistor for other functions may be included.

[0116] As such, the present invention has been described with reference to an embodiment illustrated in the drawings, but this is merely illustrative, and those skilled in the art will understand that various modifications and variations of the embodiments are possible therefrom. Accordingly, the true technical scope of protection of the present invention should be determined by the technical spirit of the appended claims. Explanation of the symbols

[0117] 10: Display device 110: Pixel section 130: Injection drive unit 150: Data driver 170: Control unit ST: Stage

Claims

Claim 1 In a scan drive unit comprising a plurality of stages, each of the plurality of stages comprises: a first control unit that controls the voltage levels of a first control node and a second control node by means of a first start signal and a second start signal and outputs a first carry signal to a subsequent stage; and a second control unit that controls the voltage levels of a third control node and a fourth control node by means of the first start signal and the second start signal and outputs a second carry signal to the subsequent stage. A scan driving unit comprising: a pull-up transistor with a gate connected to the first control node and a pull-down transistor with a first gate connected to the third control node, and an output unit that outputs a scan signal based on an on voltage output through the pull-up transistor and an off voltage output through the pull-down transistor; wherein the first carry signal and the second carry signal are output to the first control unit and the second control unit of the rear stage, respectively, as a first start signal and a second start signal, respectively. Claim 2 A scan driving unit according to claim 1, wherein the transistors constituting each of the plurality of stages are N-channel oxide thin-film transistors. Claim 3 A scan driving unit according to claim 1, wherein the circuit of the first control unit and the circuit of the second control unit are symmetrical with respect to a node connected to a terminal that applies an off voltage to the first control unit and the second control unit. Claim 4 A scan driving unit according to claim 1, wherein the pull-up transistor is connected between a first voltage input terminal to which a first voltage of an on voltage is applied and a first output node to which a first output terminal outputting the scan signal is connected, and the pull-down transistor is connected between a third voltage input terminal to which a third voltage of an off voltage is applied and the first output node. Claim 5 A scan driving unit according to claim 1, wherein the first start signal applied to the first stage is a first scan start signal and the second start signal is an inverted signal of the first start signal, and the first start signal and the second start signal applied to each of the stages after the first stage are the first carry signal and the second carry signal output by the previous stage. Claim 6 In claim 5, the first control unit comprises: a first transistor connected between a first voltage input terminal to which a first voltage of an on voltage is applied and the first control node, with its gate connected to a first input terminal to which a first start signal is applied; a second transistor connected between the first voltage input terminal and the second control node, with its gate connected to a second input terminal to which a second start signal is applied; a third transistor connected between the first control node and a node to which a second voltage input terminal to which a second voltage of an off voltage is applied, with its gate connected to the second control node; a fourth transistor connected between the second control node and the node, with its gate connected to the first control node; and a fifth transistor connected between a clock terminal to which a clock signal is applied and a second output node to which a second output terminal that outputs the first carry signal is connected, with its gate connected to the first control node. A scan driving unit comprising: a sixth transistor connected between the second voltage input terminal and the second output node, with its gate connected to the second control node; a first capacitor connected between the first control node and the second output node; and a second capacitor connected between the second control node and the second voltage input terminal. Claim 7 In claim 6, the scan driving unit, wherein in a first period of the frame, the second start signal is applied as an ON voltage during at least a part of the first period, so that the second control node is set to the ON voltage of the first voltage through the second transistor and the first control node is set to the OFF voltage of the second voltage through the third transistor, and in a second period following the first period, the first start signal is applied as an ON voltage during at least a part of the second period, so that the first control node is set to the ON voltage of the first voltage through the first transistor and the second control node is set to the OFF voltage of the second voltage through the fourth transistor. Claim 8 In claim 7, the first control unit outputs the first carry signal based on the second voltage output through the sixth transistor during the first period and the clock signal output through the fifth transistor during the second period. Claim 9 In claim 8, the clock signal output during the second period comprises a plurality of pulses, a scan driving unit. Claim 10 In claim 6, the scan driving unit further comprises: the third transistor including a pair of sub-transistors connected in series between the first control node and the node, and the first control unit including a seventh transistor connected between the first voltage input terminal and the intermediate node of the pair of sub-transistors. Claim 11 In claim 5, the second control unit comprises: an eighth transistor connected between a first voltage input terminal to which a first voltage of the on voltage is applied and the third control node, with its gate connected to a second input terminal to which the second start signal is applied; a ninth transistor connected between the first voltage input terminal and the fourth control node, with its gate connected to a first input terminal to which the first start signal is applied; a tenth transistor connected between the third control node and a node to which a second voltage input terminal to which a second voltage of the off voltage is applied is connected, with its gate connected to the fourth control node; an eleventh transistor connected between the fourth control node and the node, with its gate connected to the third control node; and a twelfth transistor connected between a clock terminal to which a clock signal is applied and a third output node to which a third output terminal outputting the second carry signal is connected, with its gate connected to the third control node. A scan driving unit comprising: a 13th transistor connected between the second voltage input terminal and the third output node, with its gate connected to the fourth control node; a third capacitor connected between the third control node and the third output node; and a fourth capacitor connected between the fourth control node and the second voltage input terminal. Claim 12 A scan driving unit according to claim 11, wherein in a first period of a frame, the second start signal is applied as an ON voltage during at least part of the first period, so that the third control node is set to the ON voltage of the first voltage through the eighth transistor and the fourth control node is set to the OFF voltage of the second voltage through the eleventh transistor, and in a second period following the first period, the first start signal is applied as an ON voltage during at least part of the second period, so that the fourth control node is set to the ON voltage of the first voltage through the ninth transistor and the third control node is set to the OFF voltage of the second voltage through the tenth transistor. Claim 13 In claim 12, the second control unit outputs the second carry signal based on the clock signal output through the 12th transistor during the first period and the second voltage output through the 13th transistor during the second period. Claim 14 In paragraph 13, the clock signal output during the first period comprises a plurality of pulses, a scan driving unit. Claim 15 In claim 11, the scan driving unit further comprises: the 10th transistor including a pair of subtransistors connected in series between the 3rd control node and the node, and the 2nd control unit including a 14th transistor connected between the 1st voltage input terminal and the intermediate node of the pair of subtransistors. Claim 16 A pixel unit comprising a plurality of pixels, wherein each of the plurality of pixels is connected to a scan line and a data line; and a scan driving unit that outputs a scan signal to the scan line of each of the plurality of pixels; wherein the scan driving unit comprises a plurality of stages, and each of the plurality of stages comprises: a first control unit that controls the voltage levels of a first control node and a second control node by a first start signal and a second start signal and outputs a first carry signal to a subsequent stage; and a second control unit that controls the voltage levels of a third control node and a fourth control node by the first start signal and the second start signal and outputs a second carry signal to the subsequent stage. A display device comprising: a pull-up transistor with a gate connected to the first control node and a pull-down transistor with a first gate connected to the third control node, and an output unit that outputs a scan signal based on an on voltage output through the pull-up transistor and an off voltage output through the pull-down transistor; wherein the first carry signal and the second carry signal are output to the first control unit and the second control unit of the subsequent stage, respectively, as a first start signal and a second start signal, respectively. Claim 17 A display device according to claim 16, wherein the transistors constituting the pixel circuit of each of the pixels and the transistors constituting each of the stages are N-channel oxide thin-film transistors. Claim 18 A display device according to claim 16, wherein the circuit of the first control unit and the circuit of the second control unit are symmetrical with respect to a node connected to a terminal that applies an off voltage to the first control unit and the second control unit. Claim 19 A display device according to claim 16, wherein the pull-up transistor is connected between a first voltage input terminal to which a first voltage of an on voltage is applied and a first output node to which a first output terminal outputting the scan signal is connected, and the pull-down transistor is connected between a third voltage input terminal to which a third voltage of an off voltage is applied and the first output node. Claim 20 A display device according to claim 16, wherein the first start signal applied to the first stage is a first scan start signal and the second start signal is an inverted signal of the first start signal, and the first start signal and the second start signal applied to each of the stages after the first stage are the first carry signal and the second carry signal output by the previous stage.

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