Display apparatus and electronic product including the same

Abstract

An embodiment of the present invention discloses a display device comprising: a substrate; a first silicon-based transistor comprising a first semiconductor layer disposed on the substrate and comprising a silicon-based semiconductor and a first gate electrode overlapping with the first semiconductor layer; at least one insulating layer on the first gate electrode; a first oxide-based transistor comprising a semiconductor layer on the at least one insulating layer, wherein the semiconductor layer comprises an oxide-based semiconductor; a first connecting electrode electrically connecting the first semiconductor layer of the first silicon-based transistor and the semiconductor layer of the first oxide-based transistor; and a lower metal layer interposed between the substrate and the first silicon-based transistor and overlapping with a portion of the first semiconductor layer of the first silicon-based transistor, wherein a portion of the lower metal layer overlaps with a first connection point between a portion of the first semiconductor layer and the first connecting electrode.

Description

Technology Field

[0001] Embodiments of the present invention relate to a display device. Background Technology

[0002] Generally, in a display device including a light-emitting diode, thin-film transistors are placed in the display area to control the brightness of the light-emitting diode. The thin-film transistors use a transmitted data signal, a driving voltage, and a common voltage to control the corresponding light-emitting diode to emit light having a predetermined color. The problem to be solved

[0003] The present invention can provide a display device that is robust against external shocks yet flexible. However, this problem is exemplary and does not limit the scope of the present invention. means of solving the problem

[0004] According to one aspect of the present invention, a display device is disclosed comprising: a substrate; a first silicon-based transistor disposed on the substrate and comprising a first semiconductor layer including a silicon-based semiconductor and a first gate electrode overlapping with the first semiconductor layer; at least one insulating layer on the first gate electrode; a first oxide-based transistor comprising a semiconductor layer on the at least one insulating layer, wherein the semiconductor layer comprises an oxide-based semiconductor; a first connecting electrode electrically connecting the first semiconductor layer of the first silicon-based transistor and the semiconductor layer of the first oxide-based transistor; and a lower metal layer interposed between the substrate and the first silicon-based transistor and overlapping with a portion of the first semiconductor layer of the first silicon-based transistor; wherein a portion of the lower metal layer overlaps with a first connection point between a portion of the first semiconductor layer and the first connecting electrode.

[0005] The first semiconductor layer comprises a folded channel region and a drain region disposed on one side of the channel region and connected to the first connecting electrode, and a portion of the lower metal layer may overlap the folded channel region and the drain region of the first semiconductor layer.

[0006] A portion of the above lower metal layer may overlap with a second connection point between the first connecting electrode and the semiconductor layer of the first oxide-based transistor.

[0007] The above lower metal layer can have a voltage level of constant voltage.

[0008] The apparatus further comprises a plurality of inorganic insulating layers between the substrate and the first connecting electrode, wherein the plurality of inorganic insulating layers comprises at least one insulating layer, and the plurality of inorganic insulating layers may comprise a valley having a first depth along the thickness direction of the plurality of inorganic insulating layers.

[0009] At least a portion of the above-mentioned valley may be filled with an organic insulating material.

[0010] A second silicon-based transistor comprising a second semiconductor layer including a silicon-based semiconductor and a second gate electrode overlapping with the second semiconductor layer; and further comprising a first lower scan line electrically connected to the second gate electrode of the second silicon-based transistor, wherein the first lower scan line has an isolated shape on a plane and may be electrically connected to a first upper scan line located on the first lower scan line and crossing the valley on the plane.

[0011] The storage capacitor further comprises a first capacitor electrode and a second capacitor electrode superimposed on the first silicon-based transistor, wherein the at least one insulating layer comprises a first interlayer insulating layer between the first capacitor electrode and the second capacitor electrode; and a second interlayer insulating layer on the first interlayer insulating layer, wherein the second capacitor electrode is disposed below the second interlayer insulating layer, and the semiconductor layer of the first oxide-based transistor may be disposed above the second interlayer insulating layer.

[0012] On a plane, the second capacitor electrode and the first connecting electrode may be arranged adjacently but may not overlap each other.

[0013] The distance between one side of the second capacitor electrode and one side of the first connecting electrode adjacent to each other on a plane may be about 0.5 μm or greater.

[0014] One embodiment of the present invention comprises: a substrate; a lower metal layer disposed on the substrate; a first silicon-based semiconductor pattern disposed on the lower metal layer and including a first semiconductor layer; an oxide-based semiconductor pattern spaced apart from the first silicon-based semiconductor pattern; and a first connecting electrode for electrically connecting a portion of the first silicon-based semiconductor pattern and a portion of the oxide-based semiconductor pattern, wherein a portion of the lower metal layer may overlap at a connection point between the portion of the first silicon-based semiconductor pattern and the first connecting electrode.

[0015] The first semiconductor layer of the first silicon-based semiconductor pattern comprises a folded channel region and an impurity region disposed on one side of the channel region and connected to the first connecting electrode, and a portion of the lower metal layer may overlap the folded channel region and the impurity region of the first semiconductor layer.

[0016] A portion of the above lower metal layer may overlap at a second connection point between the first connecting electrode and the oxide-based semiconductor pattern.

[0017] The above lower metal layer can have a voltage level of constant voltage.

[0018] The apparatus further comprises a plurality of inorganic insulating layers between the substrate and the first connecting electrode, wherein the plurality of inorganic insulating layers may include a valley having a first depth along the thickness direction of the plurality of inorganic insulating layers.

[0019] At least a portion of the above-mentioned valley may be filled with an organic insulating material.

[0020] The first silicon-based semiconductor pattern further includes a first lower scan line, the first silicon-based semiconductor pattern further includes a second semiconductor layer connected to the first semiconductor layer, and the first lower scan line may overlap with a part of the second semiconductor layer.

[0021] The first lower scan line is located on the first lower scan line and can be electrically connected to the first upper scan line that crosses the valley in a plane.

[0022] The first capacitor may further include a first capacitor that overlaps with the first semiconductor layer of the first silicon-based semiconductor pattern, and the first capacitor may include a first capacitor electrode and a second capacitor electrode on the first capacitor electrode.

[0023] On a plane, the second capacitor electrode and the first connecting electrode may be arranged adjacently but may not overlap each other. Effects of the invention

[0024] According to one embodiment of the present invention as described above, the deformation rate of the display caused by external impact is minimized to minimize the occurrence of microcracks, and even if microcracks occur, their propagation to the surroundings can be minimized. Of course, the scope of the present invention is not limited by this effect. Brief explanation of the drawing

[0025] FIG. 1 is a schematic plan view of a display device according to one embodiment of the present invention. FIG. 2 is an equivalent circuit diagram schematically showing a light-emitting diode corresponding to one of the subpixels of a display device according to one embodiment of the present invention and a subpixel circuit connected thereto. FIG. 3 is a schematic plan view showing subpixel circuit regions arranged in a display area of ​​a display device according to one embodiment of the present invention. FIG. 4 is a cross-sectional view of a display device according to one embodiment of the present invention. Figure 5 shows a modified example along the line B-B' of Figure 4. FIGS. 6 to 14 show plan views according to a process for forming components arranged in a display area of ​​a display device according to one embodiment of the present invention. FIG. 15 is an enlarged plan view of a part of FIG. 12. Specific details for implementing the invention

[0026] The present invention is capable of various modifications and may have various embodiments; specific embodiments are illustrated in the drawings and described in detail in the detailed description. The effects and features of the present invention, and the methods for achieving them, will become clear by referring to the embodiments described below in detail together with the drawings. However, the present invention is not limited to the embodiments disclosed below but can be implemented in various forms.

[0027] Hereinafter, embodiments of the present invention will be described in detail with reference to the attached drawings. When describing with reference to the drawings, identical or corresponding components are given the same reference numerals, and redundant descriptions thereof will be omitted.

[0028] In the following embodiments, when various components such as layers, films, regions, and plates are described as being "on" another component, this includes not only cases where they are "directly on" another component, but also cases where other components are interposed between them. Furthermore, for convenience of explanation, the size of components in the drawings may be exaggerated or reduced. For example, the size and thickness of each component shown in the drawings are depicted arbitrarily for convenience of explanation, and therefore the present invention is not necessarily limited to what is illustrated.

[0029] In the following embodiments, the x-axis, y-axis, and z-axis are not limited to three axes in an orthogonal coordinate system and can be interpreted in a broader sense that includes them. For example, the x-axis, y-axis, and z-axis may be orthogonal to each other, but they may also refer to different directions that are not orthogonal to each other.

[0030] FIG. 1 is a schematic plan view of a display device according to one embodiment of the present invention.

[0031] Referring to FIG. 1, various components forming a display device (10) are arranged on a substrate (100). The substrate (100) may include a display area (DA) and a surrounding area (PA) surrounding the display area (DA). The display area (DA) may be covered with a sealing member to be protected from the outside air or moisture.

[0032] Subpixels (P) are arranged in the display area (DA) of the substrate (100). Each subpixel (P) can display an image using light emitted from a display element such as a light-emitting diode. Each light-emitting diode can emit, for example, red, green, and blue light.

[0033] Each light-emitting diode may be electrically connected to a subpixel circuit, and each subpixel circuit may include transistors and a storage capacitor. Each of the subpixel circuits may be electrically connected to peripheral circuits located in a peripheral area (PA). Peripheral circuits located in the peripheral area (PA) may include a first scan driving circuit (SDRV1), a second scan driving circuit (SDRV2), a terminal section (PAD), a driving voltage supply line (11), and a common voltage supply line (13).

[0034] The first scan driving circuit (SDRV1) can apply a scan signal to each of the subpixel circuits corresponding to the subpixels (P) via the scan line (SL). The first scan driving circuit (SDRV1) can apply a light emission control signal to each subpixel circuit via the light emission control line (EL). The second scan driving circuit (SDRV2) may be located on the opposite side of the first scan driving circuit (SDRV1) with respect to the display area (DA) and may be approximately parallel to the first scan driving circuit (SDRV1). Some of the subpixel circuits may be electrically connected to the first scan driving circuit (SDRV1), and the rest may be electrically connected to the second scan driving circuit (SDRV2). In some embodiments, the second scan driving circuit (SDRV2) may be omitted.

[0035] A terminal portion (PAD) may be disposed on one side of the substrate (100). The terminal portion (PAD) is exposed without being covered by an insulating layer and is connected to a display circuit board (30). A display driving portion (32) may be disposed on the display circuit board (30).

[0036] The display driving unit (32) can generate a control signal to be transmitted to the first scan driving circuit (SDRV1) and the second scan driving circuit (SDRV2). The display driving unit (32) generates a data signal, and the generated data signal can be transmitted to the subpixel circuits of the subpixels (P) through the fan-out wiring (FW) and the data line (DL) connected to the fan-out wiring (FW).

[0037] The display driving unit (32) can supply a driving voltage (ELVDD) to the driving voltage supply line (11) and a common voltage (ELVSS) to the common voltage supply line (13). The driving voltage (ELVDD) is applied to the subpixel circuit of the subpixel (P) through the driving voltage line (PL) connected to the driving voltage supply line (11), and the common voltage (ELVSS) can be applied to the opposing electrode of the display element through the common voltage supply line (13).

[0038] The driving voltage supply line (11) may be provided extending along the x-direction from the lower side of the display area (DA). The common voltage supply line (13) may have a loop shape with one side open, partially surrounding the display area (DA).

[0039] The display device (10) of FIG. 1 is a device for displaying video or still images and may be a portable electronic device such as a mobile phone, smartphone, tablet PC, mobile communication terminal, electronic notebook, e-book, PMP (portable multimedia player), navigation, UMPC (Ultra Mobile PC), etc. Alternatively, the display device (10) may be used as a display screen for various products such as a television, laptop, monitor, billboard, Internet of Things (IOT). In addition, the display device (1) according to one embodiment may be used in a wearable device such as a smart watch, watch phone, glasses-type display, and head-mounted display (HMD). Additionally, the display device (10) according to one embodiment can be used as a center information display (CID) placed on the center fascia or dashboard of a vehicle, a room mirror display replacing the side mirror of a vehicle, an entertainment device for the rear seat of a vehicle, or a display placed on the back of the front seat.

[0040] FIG. 2 is an equivalent circuit diagram schematically showing a light-emitting diode corresponding to one of the subpixels of a display device according to one embodiment of the present invention and a subpixel circuit connected thereto.

[0041] Referring to FIG. 2, a light-emitting diode (LED) can be electrically connected to a subpixel circuit (PC) comprising a plurality of transistors and a storage capacitor.

[0042] A light-emitting diode (LED) may be an organic light-emitting diode containing an organic material as a light-emitting material. In another embodiment, the light-emitting diode (LED) may be an inorganic light-emitting diode containing an inorganic material. The inorganic light-emitting diode may include a PN junction diode containing inorganic semiconductor-based materials. When a forward voltage is applied to the PN junction diode, holes and electrons are injected, and the energy generated by the recombination of the holes and electrons is converted into light energy to emit light of a predetermined color. The aforementioned inorganic light-emitting diode may have a width of several to several hundred micrometers or several to several hundred nanometers. In some embodiments, the light-emitting diode (LED) may include a quantum dot light-emitting diode. As described above, the light-emitting layer of the light-emitting diode (LED) may include an organic material, an inorganic material, quantum dots, an organic material and quantum dots, or an inorganic material and quantum dots. For convenience of explanation, the following description assumes that the light-emitting diode (LED) includes an organic light-emitting diode.

[0043] The subpixel circuit (PC) may include a first transistor (T1), a second transistor (T2), a third transistor (T3), a fourth transistor (T4), a fifth transistor (T5), a sixth transistor (T6), and a seventh transistor (T7).

[0044] The subpixel circuit (PC) is connected to signal lines, first and second initialization voltage lines (VIL1, VIL2) and a driving voltage line (PL). The signal lines may include a data line (DL), a first scan line (SL1), a second scan line (SL2), a third scan line (SL3), a fourth scan line (SL4), and a light emission control line (EML). In another embodiment, at least one of the signal lines, the first and second initialization voltage lines (VIL1, VIL2) and / or the driving voltage line (PL) may be shared among adjacent subpixel circuits.

[0045] The driving voltage line (PL) can transmit a first power supply voltage (ELVDD) to the first transistor (T1). The first initialization voltage line (VIL1) can transmit a first initialization voltage (Vint1) that initializes the first transistor (T1) to the subpixel circuit (PC). The second initialization voltage line (VIL2) can transmit a second initialization voltage (Vint2) that initializes the light-emitting diode (LED) to the subpixel circuit (PC).

[0046] The first transistor (T1) is connected to the driving voltage line (PL) via the fifth transistor (T5) and is electrically connected to the light-emitting diode (LED) via the sixth transistor (T6). The first transistor (T1) acts as a driving transistor and receives a data signal (DATA) according to the switching operation of the second transistor (T2) and transmits a driving current (I) to the light-emitting diode (LED). LED supplies ).

[0047] The second transistor (T2) is a switching transistor and is connected to the first scan line (SL1) and the data line (DL), and is connected to the driving voltage line (PL) via the fifth transistor (T5). The second transistor (T2) is turned on according to the first scan signal (GW) received through the first scan line (SL1) and performs a switching operation to transmit the data signal (DATA) transmitted to the data line (DL) to the node (N1).

[0048] The third transistor (T3) is a compensation transistor and is connected to the fourth scan line (SL4) and is connected to a light-emitting diode (LED) via the sixth transistor (T6). The third transistor (T3) is turned on according to the fourth scan signal (GC) received through the fourth scan line (SL4) and diode-connects the first transistor (T1).

[0049] The fourth transistor (T4) is a first initialization transistor and is connected to the previous scan line, the third scan line (SL3), and the first initialization voltage line (VIL1). It is turned on according to the previous scan signal, the third scan signal (GI), received through the third scan line (SL3), and transmits the first initialization voltage (Vint1) from the first initialization voltage line (VIL1) to the gate electrode of the first transistor (T1) to initialize the voltage of the gate electrode of the first transistor (T1).

[0050] The fifth transistor (T5) may be an operation control transistor, and the sixth transistor (T6) may be a light emission control transistor. The fifth transistor (T5) and the sixth transistor (T6) are connected to the light emission control line (EML) and are simultaneously turned on according to the light emission control signal (EM) received through the light emission control line (EML) to form a current path so that a driving current (IOLED) can flow from the driving voltage line (PL) toward the light-emitting diode (LED).

[0051] The seventh transistor (T7) is a second initialization transistor and can be electrically connected to the second scan line (SL2), the second initialization voltage line (VIL2), and the sixth transistor (T6). The seventh transistor (T7) is turned on according to the second scan signal (GB) received through the second scan line (SL2) to transmit the second initialization voltage (Vint2) from the second initialization voltage line (VIL2) to the light-emitting diode (LED) to initialize the light-emitting diode (LED). The seventh transistor (T7) may be omitted. The second scan signal (GB) of the second scan line (SL2) may be the scan signal of the first scan line placed in the previous row of the corresponding subpixel circuit (PC).

[0052] The first capacitor (Cst) includes a first capacitor electrode (CE1) and a second capacitor electrode (CE2). The first capacitor electrode (CE1) is connected to the gate electrode of the first transistor (T1), and the second capacitor electrode (CE2) is connected to the driving voltage line (PL). The first capacitor (Cst) is a storage capacitor and can maintain the voltage applied to the gate electrode of the first transistor (T1) by storing and maintaining a voltage corresponding to the difference between the voltages of the driving voltage line (PL) and the gate electrode of the first transistor (T1).

[0053] The second capacitor (Cbt) includes a third capacitor electrode (CE3) and a fourth capacitor electrode (CE4). The third capacitor electrode (CE3) is connected to the gate electrode of the first scan line (SL1) and the second transistor (T2). The fourth capacitor electrode (CE4) is connected to the gate electrode of the first transistor (T1) and the first capacitor electrode (CE1) of the first capacitor (Cst). The second capacitor (Cbt) is a boosting capacitor, and when the first scan signal (Sn) of the first scan line (SL1) is a voltage that turns off the second transistor (T2), it can increase the voltage of the node (N2) to reduce the voltage that displays black (black voltage).

[0054] A light-emitting diode (LED) may include a first electrode (e.g., an anode) and a second electrode (e.g., a cathode) facing each other, and a light-emitting layer between the first electrode and the second electrode. The second electrode may receive a second power supply voltage (ELVSS). The light-emitting layer of the light-emitting diode (LED) receives a driving current (I) from a first transistor (T1). LED It can emit light by receiving ).

[0055] The specific operation of the subpixel circuit (PC) according to one embodiment is as follows.

[0056] During the first initialization period, when a third scan signal (GI) is supplied through the third scan line (SL3), the fourth transistor (T4) is turned on in response to the third scan signal (GI), and the first transistor (T1) is initialized by the first initialization voltage (Vint1) supplied from the first initialization voltage line (VIL1).

[0057] During the data programming period, when the first scan signal (GW) and the fourth scan signal (GC) are supplied through the first scan line (SL1) and the fourth scan line (SL4), respectively, the second transistor (T2) and the third transistor (T3) are turned on in response to the first scan signal (GW) and the fourth scan signal (GC). At this time, the first transistor (T1) is diode-connected by the turned-on third transistor (T3) and is forward-biased. Then, a voltage compensated for the threshold voltage of the first transistor (T1) from the data signal (DATA) supplied from the data line (DL) is applied to the gate electrode of the first transistor (T1). A first power supply voltage (ELVDD) and a compensation voltage are applied to both ends of the first capacitor (Cst), and a charge corresponding to the voltage difference between the two ends is stored in the first capacitor (Cst).

[0058] During the light emission period, the fifth transistor (T5) and the sixth transistor (T6) are turned on by the light emission control signal (EM) supplied from the light emission control line (EML). The driving current (I) according to the voltage difference between the voltage of the gate electrode of the first transistor (T1) and the first power supply voltage (ELVDD) LED ) is generated, and the driving current (I) is generated through the 6th transistor (T6). LED ) is supplied to the light-emitting diode (LED).

[0059] During the second initialization period, when the second scan signal (GB) is supplied through the second scan line (SL2), the seventh transistor (T7) is turned on in response to the second scan signal (GB), and the light-emitting diode (LED) is initialized by the second initialization voltage (Vint2) supplied from the second initialization voltage line (VIL2).

[0060] At least one of the first to seventh transistors (T1 to T7) of the subpixel circuit (PC) may include a semiconductor layer containing oxide, and the remainder may include a semiconductor layer containing silicon. FIG. 2 illustrates that the third transistor (T3) and the fourth transistor (T4) are oxide-based transistors implemented as NMOS (n-channel MOSFET), and the first transistor (T1), the second transistor (T2), the fifth transistor (T5), the sixth transistor (T6), and the seventh transistor (T7) are silicon-based transistors implemented as PMOS (p-channel MOSFET). In another embodiment, the third transistor (T3) is implemented as an NMOS, and the first transistor (T1), second transistor (T2), fourth transistor (T4), fifth transistor (T5), sixth transistor (T6), and seventh transistor (T7) can be implemented as PMOS.

[0061] Specifically, the first transistor (T1), which directly affects the brightness of the display device, is configured to include a semiconductor layer composed of polycrystalline silicon with high reliability, thereby enabling the implementation of a high-resolution display device.

[0062] Meanwhile, since oxide semiconductors have high carrier mobility and low leakage current, the voltage drop is not significant even when the driving time is long. In other words, since the color change of the image due to the voltage drop is not significant even during low-frequency driving, low-frequency driving is possible. As oxide semiconductors have the advantage of low leakage current, at least one of the third transistor (T3) and the fourth transistor (T4) connected to the gate electrode of the first transistor (T1) is adopted as an oxide semiconductor to prevent leakage current from flowing to the gate electrode of the first transistor (T1) while simultaneously reducing power consumption.

[0063] The subpixel circuit (PC) is not limited to the number and circuit design of the thin-film transistors and storage capacitors described with reference to FIG. 2, and the number and circuit design can be varied.

[0064] FIG. 3 is a schematic plan view showing subpixel circuit regions arranged in a display area of ​​a display device according to an embodiment of the present invention. Subpixel circuits described above with reference to FIG. 2 are arranged in the display area (DA) of the display device described with reference to FIG. 1. In this regard, FIG. 3 shows subpixel circuits arranged in the display area (DA). The subpixel circuits are arranged in subpixel circuit regions (PCA) forming rows and columns, and in this regard, FIG. 3 illustrates subpixel circuit regions (PCA) arranged in row (N) and row (N-1), and column (M-1) and column (M). FIG. 3 shows two adjacent subpixel circuit regions (PCA) arranged in row (N), and parts of two adjacent subpixel circuit regions (PCA) arranged in row (N-1).

[0065] The first scan line (SL1), the second scan line (SL2), the third scan line (SL3), the fourth scan line (SL4), the light emission control line (EML), and the first and second initialization voltage lines (VIL1, VIL2) can each be extended in the first direction (x) and spaced apart from each other. The data line (DL) and the driving voltage line (PL) can each be extended in the second direction (y) and spaced apart from each other. In one embodiment, FIG. 3 illustrates that the driving voltage line (PL) is shared between column (M-1) and column (M). In other words, the driving voltage line (PL) placed in column (M-1) and the driving voltage line (PL) placed in column (M) can be formed integrally (e.g., integrally connected). In another embodiment, the driving voltage line (PL) placed in column (M-1) and the driving voltage line (PL) placed in column (M) can be separated and spaced apart from each other.

[0066] Multiple transistors and multiple capacitor electrodes may be disposed in each subpixel circuit area (PCA). In this regard, FIG. 3 illustrates that seven transistors and two capacitors are disposed in each subpixel circuit area (PCA).

[0067] Referring to a subpixel circuit region (PCA, hereinafter referred to as the first subpixel circuit region (PCA1)) placed in row (N) and column (M-1), the first to sixth transistors (T1, T2, T3, T4, T5, T6), the first capacitor (Cst), and the second capacitor (Cbt) corresponding to the subpixel circuit (PC, FIG. 2) described above with reference to FIG. 2 may be placed in the first subpixel circuit region (PCA1).

[0068] A seventh transistor (T7) electrically connected to the first to sixth transistors (T1, T2, T3, T4, T5, T6), the first capacitor (Cst), and the second capacitor (Cbt) placed in the first subpixel circuit area (PCA1) may be located in row (N-1). In other words, the first to sixth transistors (T1, T2, T3, T4, T5, T6), the first capacitor (Cst), and the second capacitor (Cbt) placed in the first subpixel circuit area (PCA1) may be electrically connected to the seventh transistor (T7) placed in the subpixel circuit area (hereinafter referred to as the third subpixel circuit area (PCA3)) located in row (N-1) and column (M-1). For example, the seventh transistor (T7) placed in the third subpixel circuit area (PCA3) of row (N-1) can be electrically connected to the sixth transistor (T6) placed in the first subpixel circuit area (PCA1) through the seventh connecting electrode (NM7) and the connecting line (ML). The first to sixth transistors (T1, T2, T3, T4, T5, T6), the first capacitor (Cst), and the second capacitor (Cbt) placed in the first subpixel circuit area (PCA1), and the seventh transistor (T7) placed in the third subpixel circuit area (PCA3) can be operated to turn on / off the same light-emitting diode (LED, FIG. 2). The seventh transistor (T7") placed in the first subpixel circuit area (PCA1) of row (N) can be electrically connected to the first to sixth transistors placed in the subpixel circuit area of ​​row (N+1). The seventh transistor (T7) placed in the third subpixel circuit area (PCA3) can receive a second scan signal and a second initialization voltage, respectively, through the second scan line (SL2) and the second initialization voltage line (VIL2) passing through the third subpixel circuit area (PCA3). The second scan line (SL2) may correspond to the first scan line (SL1') that provides a first scan signal to the second transistor (T2') placed in the third subpixel circuit area (PCA3).

[0069] Each of the first transistor (T1), second transistor (T2), fifth transistor (T5), sixth transistor (T6), and seventh transistor (T7) is a transistor comprising a silicon-based semiconductor layer (hereinafter referred to as a silicon-based transistor) and can be formed along a silicon semiconductor pattern. The third transistor (T3) and the fourth transistor (T4) are each transistors comprising an oxide-based semiconductor layer (hereinafter referred to as oxide-based transistors) and can be formed along an oxide semiconductor pattern.

[0070] A subpixel circuit region (PCA, hereinafter referred to as the second subpixel circuit region (PCA2)) placed in row (N) and column (M) may have the same structure as the first subpixel circuit region (PCA1). In one embodiment, FIG. 3 illustrates that the first subpixel circuit region (PCA1) and the second subpixel circuit region (PCA2) located in the same row have a symmetrical structure with respect to a virtual line (VL, a virtual line in the y-direction) between them. In another embodiment, the first subpixel circuit region (PCA1) and the second subpixel circuit region (PCA2) may be asymmetric with respect to the virtual line (VL).

[0071] The first to sixth transistors (T1, T2, T3, T4, T5, T6), the first capacitor (Cst), and the second capacitor (Cbt) placed in the second subpixel circuit area (PCA2) can be electrically connected to the seventh transistor (T7) placed in the subpixel circuit area (hereinafter referred to as the fourth subpixel circuit area (PCA4)) placed in row (N-1) and column (M). In other words, the first to sixth transistors (T1, T2, T3, T4, T5, T6), the first capacitor (Cst), and the second capacitor (Cbt), and the seventh transistor (T7) placed in the fourth subpixel circuit area (PCA4) can form a single subpixel circuit (PC, FIG. 2) for driving the same light-emitting diode (LED, FIG. 2).

[0072] The structure of the third subpixel circuit area (PCA3) and the fourth subpixel circuit area (PCA4), respectively, is identical to the structure of the first subpixel circuit area (PCA1) and the second subpixel circuit area (PCA2), respectively.

[0073] The first to sixth transistors (T1, T2, T3, T4, T5, T6), the first capacitor (Cst), and the second capacitor (Cbt) placed in each subpixel circuit area (PCA) may have an electrical connection structure as described above with reference to FIG. 2, and the specific structure thereof will be described later with reference to FIG. 5 to 14.

[0074] FIG. 4 is a cross-sectional view of a display device according to an embodiment of the present invention. The first transistor and the third transistor shown in FIG. 4 correspond to the cross-section taken along the line IV-IV' of FIG. 3. Hereinafter, the stacking order will be described with reference to FIG. 4.

[0075] Referring to the cross-section along line A-A' of FIG. 4, the substrate (100) may include a glass material, a ceramic material, a metal material, a plastic, or a material having flexible or bendable properties. When the substrate (100) has flexible or bendable properties, the substrate (100) may include a polymer resin such as polyethersulfone (PES), polyacrylate, polyetherimide (PEI), polyethylene naphthalate (PEN), polyethylene terephthalate (PET), polyphenylene sulfide (PPS), polyarylate, polyimide (PI), polycarbonate (PC), and cellulose acetate propionate (CAP).

[0076] The substrate (100) may have a single layer or a multilayer structure of the above material, and in the case of a multilayer structure, may further include an inorganic layer. For example, the substrate (100) may include a first organic base layer (101), a first inorganic barrier layer (102), a second organic base layer (103), and a second inorganic barrier layer (104). The first organic base layer (101) and the second organic base layer (103) may each include a polymer resin. The first inorganic barrier layer (102) and the second inorganic barrier layer (104) may be a single layer or a multilayer, comprising an inorganic insulating material such as silicon nitride and / or silicon oxide, as barrier layers that prevent the penetration of external foreign substances.

[0077] A bottom metal layer (BML) may be disposed on a substrate (100). The bottom metal layer (BML) may comprise one or more materials selected from aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and copper (Cu). In some embodiments, the bottom metal layer (BML) may be a single layer of molybdenum, have a double-layer structure in which a molybdenum layer and a titanium layer are stacked, or have a triple-layer structure in which a titanium layer, an aluminum layer, and a titanium layer are stacked.

[0078] The buffer layer (111) may be disposed on the lower metal layer (BML). The buffer layer (111) may be an inorganic insulating layer comprising an inorganic insulating material such as silicon nitride and / or silicon oxide, and may have a single layer or multilayer structure comprising the aforementioned material.

[0079] A semiconductor layer of silicon-based transistors may be disposed on the buffer layer (111). In this regard, FIG. 4 illustrates a first semiconductor layer (A1) of a first transistor (T1) corresponding to a part of a first silicon semiconductor pattern (PSL1). The first semiconductor layer (A1) may include impurity regions that are disposed on both sides of a first channel region (C1) and impurity-doped regions, and in this regard, FIG. 4 illustrates a second region (D1) which is one of the impurity regions disposed on one side of the first channel region (C1).

[0080] The first gate insulating layer (112) may be disposed on the first silicon semiconductor pattern (PSL1). The first gate insulating layer (112) may be an inorganic insulating layer comprising an inorganic insulating material such as silicon oxide, silicon nitride, and / or silicon oxynitride, and may have a single layer or multilayer structure comprising the aforementioned material.

[0081] The first gate electrode (G1) and the first capacitor electrode (CE1) may be disposed on the first gate insulating layer (112). FIG. 4 illustrates that the first gate electrode (G1) is formed integrally with the first capacitor electrode (CE1). In other words, the first gate electrode (G1) may perform the function of the first capacitor electrode (CE1), or the first capacitor electrode (CE1) may perform the function of the first gate electrode (G1).

[0082] The first gate electrode (G1) and / or the first capacitor electrode (CE1) may include aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and / or copper (Cu), and may be formed as a single layer or a multilayer including the aforementioned materials.

[0083] The first interlayer insulating layer (113) may be disposed on the first gate electrode (G1) and / or the first capacitor electrode (CE1). The first interlayer insulating layer (113) may be an inorganic insulating layer comprising an inorganic insulating material such as silicon oxide, silicon nitride, and / or silicon oxynitride, and may have a single layer or multilayer structure comprising the aforementioned material.

[0084] The second capacitor electrode (CE2) may be disposed on the first interlayer insulating layer (113). The second capacitor electrode (CE2) may include aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and / or copper (Cu), and may be formed as a single layer or a multilayer containing the aforementioned materials. The second capacitor electrode (CE2) may overlap with the first gate electrode (G1) and / or the first capacitor electrode (CE1). The second capacitor electrode (CE2) may include a hole (CE2-H) so that a node connection electrode (171) for electrically connecting the first gate electrode (G1) of the first transistor (T1) and the third transistor (T3) is connected to the first gate electrode (G1). The hole (CE2-H) may overlap with a part of the first gate electrode (G1).

[0085] The second interlayer insulating layer (114) may be disposed on the second capacitor electrode (CE2). The second interlayer insulating layer (114) may be an inorganic insulating layer comprising an inorganic insulating material such as silicon oxide, silicon nitride, and / or silicon oxynitride, and may have a single layer or multilayer structure comprising the aforementioned material.

[0086] Oxide semiconductor layers may be disposed on the second interlayer insulating layer (114). In this regard, FIG. 4 illustrates a third semiconductor layer (A3) of a third transistor (T3) corresponding to a part of an oxide semiconductor pattern (OSL). The third semiconductor layer (A3) may include a third channel region (C3) and conductive regions disposed on both sides of the third channel region (C3), and in this regard, FIG. 4 illustrates a second region (D3), which is one of the conductive regions disposed on one side of the third channel region (C3).

[0087] The third gate electrode (G3) may be positioned below and / or above the third semiconductor layer (A3). In one embodiment, FIG. 4 illustrates that the third gate electrode (G3) includes a third lower gate electrode (G3a) positioned below the third semiconductor layer (A3) and a third upper gate electrode (G3b) positioned above the third semiconductor layer (A3). In another embodiment, either the third lower gate electrode (G3a) or the third upper gate electrode (G3b) may be omitted.

[0088] The third lower gate electrode (G3a) may be made of the same material as the second capacitor electrode (CE2) and may be located on the same layer (e.g., the first interlayer insulating layer (113)). The third upper gate electrode (G3b) may be placed on the third semiconductor layer (A3) with the second gate insulating layer (115) in between. The third upper gate electrode (G3b) may include aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and / or copper (Cu), and may be formed as a single layer or a multilayer containing the aforementioned materials.

[0089] FIG. 4 illustrates that the second gate insulating layer (115) is disposed only between the third upper gate electrode (G3b) and the third semiconductor layer (A3), but the present invention is not limited thereto. The second gate insulating layer (115) may be formed to cover the entire substrate (100) like other insulating layers, such as the first gate insulating layer (112). The second gate insulating layer (115) may be an inorganic insulating layer comprising an inorganic insulating material such as silicon oxide, silicon nitride, and / or silicon oxynitride, and may have a single layer or multilayer structure comprising the aforementioned material.

[0090] The third interlayer insulating layer (116) may be disposed on the third upper gate electrode (G3b). The third interlayer insulating layer (116) may be an inorganic insulating layer comprising an inorganic insulating material such as silicon oxide, silicon nitride, and / or silicon oxynitride, and may have a single layer or multilayer structure comprising the aforementioned material.

[0091] The node connecting electrode (171) and the first connecting electrode (NM1) may be disposed on the third interlayer insulating layer (116). The node connecting electrode (171) and the first connecting electrode (NM1) may include aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and / or copper (Cu), and may be formed as a single layer or a multilayer including the aforementioned materials.

[0092] The first connecting electrode (NM1) can electrically connect the first semiconductor layer (A1) and the third semiconductor layer (A3). The first connecting electrode (NM1) can be connected to a part of the first semiconductor layer (A1) (e.g., D1 in FIG. 4) through the first contact hole (CNT1) and connected to a part of the third semiconductor layer (A3) (e.g., D3 in FIG. 4) through the second contact hole (CNT2). The first contact hole (CNT1) can penetrate inorganic insulating layers interposed between the first semiconductor layer (A1) and the first connecting electrode (NM1), such as the first gate insulating layer (112), the first interlayer insulating layer (113), the second interlayer insulating layer (114), and the third interlayer insulating layer (116). The second contact hole (CNT2) can penetrate the third interlayer insulating layer (116) interposed between the third semiconductor layer (A3) and the first connecting electrode (NM1).

[0093] The depth of the first contact hole (CNT1) is greater than the depth of the second contact hole (CNT2). When touch input, such as a finger or a stylus pen, is applied, or when unintended pressure is applied to the display area (DA), microcracks may occur due to tension in the plane direction (e.g., xy direction) caused by bending deformation and vertical compression concentrated on structurally weak parts among the components of the subpixel circuit placed in the display area (DA). Microcracks may occur in relatively structurally weak parts. For example, a first connecting electrode (NM1) formed along the inner surface of the first contact hole (CNT1) may develop microcracks near the "A" portion, which is the lower part of the first contact hole (CNT1). When microcracks propagate to the surroundings through inorganic insulating layers (e.g., buffer layer (111), first gate insulating layer (112), first interlayer insulating layer (113), second interlayer insulating layer (114), etc.), defects such as weak dark spots may occur around the first transistor (T1). Here, a dark spot may indicate that light with saturation (e.g., red, green, or blue light) is locally emitted even though the display device is driven to display a black image through the display area. However, according to an embodiment of the present invention, the lower metal layer (BML) below the first semiconductor layer (A1) of the first transistor (T1) overlaps with the first connection point (e.g., first contact hole, CNT1) between the first connection electrode (NM1) and the first semiconductor layer (A1), so the aforementioned problem can be prevented or minimized.

[0094] A second connection point (e.g., a second contact hole, CNT2) between the first connection electrode (NM1) and the third semiconductor layer (A3) may be positioned adjacent to the first contact hole (CNT1). In some embodiments, the lower metal layer (BML) may overlap both the first connection point between the first connection electrode (NM1) and the first semiconductor layer (A1) and the second connection point between the first connection electrode (NM1) and the third semiconductor layer (A3).

[0095] The lower metal layer (BML) may have a voltage level of a constant voltage. For example, the lower metal layer (BML) may be electrically connected to the driving voltage supply line (11, FIG. 1) described with reference to FIG. 1 and may have the same voltage level as the driving voltage supply line (11, FIG. 1) (e.g., driving voltage, ELVDD, FIG. 2). The lower metal layer (BML) prevents (-) charges from accumulating at the bottom of the first semiconductor layer (A1) of the first transistor (T1), thereby preventing or minimizing the problem of afterimages caused by (-) charges.

[0096] The first organic insulating layer (121) may be formed on the first connecting electrode (NM1) and the node connecting electrode (171). The first organic insulating layer (121) may include organic materials such as acrylic, BCB (Benzocyclobutene), polyimide, or HMDSO (Hexamethyldisiloxane).

[0097] A second organic insulating layer (123) may be disposed on the first organic insulating layer (121), and a driving voltage line (PL) may be disposed on the second organic insulating layer (123). A third organic insulating layer (125) may be disposed on the driving voltage line (PL). The driving voltage line (PL) may include aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), titanium (Ti), and / or tungsten (W). In some embodiments, the driving voltage line (PL) may include a triple layer structure of a titanium layer, an aluminum layer, and a titanium layer.

[0098] The second organic insulating layer (123) and the third organic insulating layer (125) may each include an organic material such as BCB (Benzocyclobutene), polyimide, or HMDSO (Hexamethyldisiloxane).

[0099] A light-emitting diode (LED) may be formed on a third organic insulating layer (125). The light-emitting diode (LED) may include a first electrode (210), a light-emitting layer (220), and a second electrode (230) on the third organic insulating layer (125). The light-emitting layer (220) may include a low-molecular-weight or high-molecular-weight organic material. Between the first electrode (210) and the second electrode (230), at least one layer selected from a hole injection layer (HIL), a hole transport layer (HTL), an electron transport layer (ETL), and an electron injection layer (EIL) may be further disposed.

[0100] The edge of the first electrode (210) can be covered by the bank layer (130), and the inner portion of the first electrode (210) can be superimposed on the light-emitting layer (220) through the opening (130OP) of the bank layer (130). While the first electrode (210) is formed for each light-emitting diode (LED), the second electrode (230) can be formed corresponding to a plurality of light-emitting diodes (LEDs). In other words, a plurality of light-emitting diodes (LEDs) can share the second electrode (230), and a stacked structure of a portion of the first electrode (210), the light-emitting layer (220), and the second electrode (230) can correspond to a light-emitting diode (LED).

[0101] The encapsulation layer (300) may be disposed on a light-emitting diode (LED). The encapsulation layer (300) may include at least one inorganic encapsulation layer and at least one organic encapsulation layer. FIG. 4 illustrates, in one embodiment, that the encapsulation layer (300) includes a first inorganic encapsulation layer (310), an organic encapsulation layer (320), and a second inorganic encapsulation layer (330). The first inorganic encapsulation layer (310) and the second inorganic encapsulation layer (330) may include silicon oxide, silicon nitride, and / or silicon oxynitride, and the organic encapsulation layer (320) may include an organic insulator.

[0102] Referring to the cross-section along line B-B' in FIGS. 3 and 4, the inorganic insulating layers disposed on the substrate (100) may include a valley (VY) provided between adjacent subpixel circuit regions (PCA). For example, the valley (VY) may penetrate at least a portion of the inorganic insulating layers on the substrate (100), such as a buffer layer (111), a first gate insulating layer (112), a first interlayer insulating layer (113), a second interlayer insulating layer (114), and a third interlayer insulating layer (116), as shown in FIG. 4. The first depth of the valley (VY) may be equal to or less than the sum of the thicknesses of the buffer layer (111), the first gate insulating layer (112), the first interlayer insulating layer (113), the second interlayer insulating layer (114), and the third interlayer insulating layer (116).

[0103] At least a portion of the valley (VY) may be filled with an organic insulating material. For example, as shown in FIG. 4, a portion of the first organic insulating layer (121) placed on the first and third transistors (T1, T3) may exist within the valley (VY). Through the valley (VY) structure, a flexible display device can be provided that is robust against external shocks (e.g., shocks occurring during events where a certain pressure is applied to a localized area, such as with a finger or a stylus pen). Microcracks occurring between the substrate (100) and the light-emitting diode (LED) may occur in structurally weak parts as previously mentioned. Here, structurally weak parts may refer to parts where the density of the layer (or electrode) formed by the deposition process is reduced due to a structural shape such as part "A" in FIG. 4. The valley (VY) can suppress the occurrence of the aforementioned microcracks and prevent the propagation of microcracks in the horizontal direction (a direction parallel to the upper surface of the substrate (100)).

[0104] FIG. 4 illustrates that an organic insulating material filling at least a portion of the valley (VY) is part of the first organic insulating layer (121), but the present invention is not limited thereto.

[0105] Figure 5 shows a modified example along the line B-B' of Figure 4.

[0106] In another embodiment, the organic insulating material filling at least a portion of the valley (VY) may be an organic insulating material that does not overlap with the transistors provided in the subpixel circuit. For example, as shown in FIG. 5, the organic insulating material (127) filling at least a portion of the valley (VY) may exist only within the valley (VY) within the display area (DA).

[0107] FIGS. 6 to 14 show plan views according to a process for forming components disposed in a display area of ​​a display device according to an embodiment of the present invention, and FIG. 15 is an enlarged plan view of a part of FIG. 12. For convenience of explanation, FIGS. 6 to 14 show plan views according to a process for forming components disposed in the first and second subpixel circuit areas (PCA1, PCA2) described above with reference to FIG. 3.

[0108] Referring to FIGS. 3, FIGS. 4, and FIGS. 6, a lower metal layer (BML) is formed on a substrate (100, FIG. 4). The lower metal layer (BML) may include the material described above with reference to FIG. 4. For example, the lower metal layer (BML) may include metals such as molybdenum, titanium, and aluminum. The lower metal layer (BML) may be, for example, a single layer of molybdenum, a double layer of molybdenum and titanium, or a triple layer of titanium, aluminum, and titanium.

[0109] The lower metal layer (BML) may include a portion (hereinafter referred to as the main portion, BML-m) located in each of the first and second subpixel circuit regions (PCA1, PCA2), as shown in FIG. 6. The main portion (BML-m) may be connected to other portions (hereinafter referred to as branch portions, BML-b) that extend along the x-direction and y-direction. The main portion (BML-m) may have a relatively constant width. In this regard, FIG. 3 and FIG. 6 illustrate that the width in the x-direction and the width in the y-direction of the main portion (BML-m) are relatively constant.

[0110] Referring to FIGS. 3 and 6, the lower metal layer (BML) placed in the first and second subpixel circuit regions (PCA1, PCA2) may be symmetrical with respect to the virtual line (VL) between the first and second subpixel circuit regions (PCA1, PCA2). The main part (BML-m) placed in the first subpixel circuit region (PCA1) and the main part (BML-m) placed in the second subpixel circuit region (PCA2) may be directly connected.

[0111] In another embodiment, the main part (BML-m) placed in the first subpixel circuit area (PCA1) and the main part (BML-m) placed in the second subpixel circuit area (PCA2) are not directly connected, and an additional branch part with a width (e.g., width in the y-direction) smaller than the main part (BML-m) may be interposed between them. In other words, the main parts (BML-m) placed in each of the adjacent subpixel circuits (PC) may be connected to each other through the additional branch part.

[0112] Referring to FIGS. 3, 4, and 7, a silicon semiconductor pattern can be formed after a buffer layer (111, FIG. 4) is formed on a lower metal layer (BML). In this regard, FIG. 7 illustrates a first silicon semiconductor pattern (PSL1) and a second silicon semiconductor pattern (PSL2) disposed in each of the first and second subpixel circuit regions (PCA1, PCA2). The first and second subpixel circuit regions (PCA1, PCA2) disposed in the first and second subpixel circuit regions (PCA1, PCA2) may be symmetrical with respect to a virtual line (VL) between the first and second subpixel circuit regions (PCA1, PCA2). The first silicon semiconductor pattern (PSL1) and the second silicon semiconductor pattern (PSL2) may include a silicon-based material, such as polycrystalline silicon.

[0113] The first silicon semiconductor pattern (PSL1) and the second silicon semiconductor pattern (PSL2), which are placed in the same subpixel circuit area, may be spaced apart from each other. The first silicon semiconductor pattern (PSL1) may be curved in various shapes, and the first transistor (T1), the second transistor (T2), the fifth transistor (T5), and the sixth transistor (T6), described with reference to FIG. 3, may be formed along the first silicon semiconductor pattern (PSL1). In this regard, FIG. 7 illustrates the arrangement of the first semiconductor layer (A1) of the first transistor (T1), the second semiconductor layer (A2) of the second transistor (T2), the fifth semiconductor layer (A5) of the fifth transistor (T5), and the sixth semiconductor layer (A6) of the sixth transistor (T6) along the first silicon semiconductor pattern (PSL1). In other words, the first silicon semiconductor pattern (PSL1) may include a first semiconductor layer (A1), a second semiconductor layer (A2), a fifth semiconductor layer (A5), and a sixth semiconductor layer (A6). The first semiconductor layer (A1), the second semiconductor layer (A2), the fifth semiconductor layer (A5), and the sixth semiconductor layer (A6) may be connected to each other to form a single unit.

[0114] The first semiconductor layer (A1) includes a first channel region (C1) and first and second regions (B1, D1) disposed on both sides of the first channel region (C1). The first and second regions (B1, D1) of the first semiconductor layer (A1) are regions doped with impurities and have greater electrical conductivity than the first channel region (C1). One of the first and second regions (B1, D1) may be a source region and the other may be a drain region. The first channel region (C1) may have a curved shape on a plane (e.g., a curved shape of an omega shape), and the length of the first channel region (C1) may be increased within a narrow space according to the aforementioned shape.

[0115] The first semiconductor layer (A1) may overlap with the lower metal layer (BML). For example, the first channel region (C1) of the first semiconductor layer (A1) and at least one of the first and second regions (B1, D1) may overlap with the lower metal layer (BML). For example, as shown in FIGS. 3 and 6, the first channel region (C1) and the second region (D1) of the first semiconductor layer (A1) may overlap with the main portion (BML-m) which is part of the lower metal layer (BML).

[0116] The second semiconductor layer (A2) includes a second channel region (C2) and first and second regions (B2, D2) disposed on both sides of the second channel region (C2). The first and second regions (B2, D2) of the second semiconductor layer (A2) are regions doped with impurities and have greater electrical conductivity than the second channel region (C2). One of the first and second regions (B2, D2) may be a source region and the other may be a drain region.

[0117] The fifth semiconductor layer (A5) includes a fifth channel region (C5) and first and second regions (B5, D5) disposed on both sides of the fifth channel region (C5). The first and second regions (B5, D5) of the fifth semiconductor layer (A5) are regions doped with impurities and have greater electrical conductivity than the fifth channel region (C5), and one of the first and second regions (B5, D5) may be a source region and the other may be a drain region.

[0118] The sixth semiconductor layer (A6) includes a sixth channel region (C6) and first and second regions (B6, D6) disposed on both sides of the sixth channel region (C6). The first and second regions (B6, D6) of the sixth semiconductor layer (A6) are regions doped with impurities and have greater electrical conductivity than the sixth channel region (C6), and one of the first and second regions (B6, D6) may be a source region and the other may be a drain region.

[0119] In one embodiment, the first region (B1) of the first semiconductor layer (A1) may be integrally connected with the second region (D2) of the second semiconductor layer (A2) and the second region (D5) of the fifth semiconductor layer (A5), and the second region (D1) of the first semiconductor layer (A1) may be integrally connected with the first region (B6) of the sixth semiconductor layer (A6).

[0120] A seventh transistor (T7") described with reference to FIG. 3 can be formed along the second silicon semiconductor pattern (PSL2). In this regard, FIG. 7 illustrates that a seventh semiconductor layer (A7") of the seventh transistor (T7") is formed along the second silicon semiconductor pattern (PSL2). The seventh semiconductor layer (A7") of FIG. 7 corresponds to the semiconductor layer of the seventh transistor (T7") ( FIG. 3) which is electrically connected to the first to sixth transistors placed in the (N+1) row subpixel circuit region described above with reference to FIG. 3.

[0121] The seventh semiconductor layer (A7) includes a seventh channel region (C7) and first and second regions (B7", D7) disposed on both sides of the seventh channel region (C7). The first and second regions (B7, D7) of the seventh semiconductor layer (A7) are regions doped with impurities and have greater electrical conductivity than the seventh channel region (C7), and one of the first and second regions (B7", D7) may be a source region and the other may be a drain region.

[0122] Referring to FIGS. 3, 4, and 8, a first gate insulating layer (112) is formed on first and second silicon semiconductor patterns (PSL1, PSL2), and a first gate electrode (G1) of a first transistor (T1), a second gate electrode (G2) of a second transistor (T2), a fifth gate electrode (G5) of a fifth transistor (T5), a sixth gate electrode (G6) of a sixth transistor (T6), and a seventh gate electrode (G7) of a seventh transistor (T7) may be disposed on the first gate insulating layer (112). A first capacitor electrode (CE1), a first lower scan line (SL1a), and a lower light emission control line (EMLa) may be disposed on the first gate insulating layer (112).

[0123] The first gate electrode (G1) has an isolated shape in a planar form, and the first gate electrode (G1) may include a first capacitor electrode (CE1). In other words, the first gate electrode (G1) and the first capacitor electrode (CE1) may be formed integrally, and it may be indicated that the first capacitor electrode (CE1) includes the first gate electrode (G1).

[0124] The first gate electrode (G1) and / or the first capacitor electrode (CE1) may be formed to cover the first channel region (C1) of the first semiconductor layer (A1) entirely. The main portion (BML-m) of the lower metal layer (BML) may have a larger area than the first gate electrode (G1) and / or the first capacitor electrode (CE1). The main portion (BML-m) of the lower metal layer (BML) entirely covers the first channel region (C1) of the first semiconductor layer (A1) and may also entirely cover the second region (D1) of the first semiconductor layer (A1) adjacent to the first channel region (C1).

[0125] The first gate electrode (G1) and / or the first capacitor electrode (CE1) disposed in each of the first and second subpixel circuit regions (PCA1, PCA2) may be symmetric with respect to the virtual line (VL) between the first and second subpixel circuit regions (PCA1, PCA2). The first lower scan line (SL1a) and the lower light emission control line (EMLa) may each extend from the first and second subpixel circuit regions (PCA1, PCA2) to cross the virtual line (VL).

[0126] The first lower scan line (SL1a) and the lower light emission control line (EMLa) may each extend along the x-direction. The first lower scan line (SL1a) and the lower light emission control line (EMLa) may be spaced apart from each other in a plane with the first gate electrode (G1) and / or the first capacitor electrode (CE1) in between.

[0127] The first lower scan line (SL1a) may include a second gate electrode (G2) and a third capacitor electrode (CE3). A portion of the first lower scan line (SL1a) includes a portion that is wider in the y-direction than other portions, and the relatively wider portion may correspond to the third capacitor electrode (CE3). The lower light emission control line (EMLa) may include a fifth gate electrode (G5) and a sixth gate electrode (G6).

[0128] The first lower scan line (SL1a) may include a seventh gate electrode (G7"). The first lower scan line (SL1a) may correspond to a sublayer of the second scan line (i.e., the second lower scan line (SL2a")) of the seventh transistor (T7"), which is connected to the first to sixth transistors arranged in the subpixel circuit region arranged in row (N+1) as described above with reference to FIG. 3.

[0129] The first lower scan line (SL1a) and the lower light emission control line (EMLa) may include the same material as the first gate electrode (G1) and / or the first capacitor electrode (CE1), and the specific material is as described above with reference to FIG. 4.

[0130] Referring to FIGS. 3, 4, and 9, after forming a first interlayer insulating layer (113, FIG. 4) on the structure of FIG. 8, a second capacitor electrode (CE2), a third lower gate line (SL3aa), and a fourth lower gate line (SL4aa) can be formed. The second capacitor electrode (CE2) placed in each of the first and second subpixel circuit regions (PCA1, PCA2) may be symmetrical with respect to the virtual line (VL) between the first and second subpixel circuit regions (PCA1, PCA2). Each of the third lower gate line (SL3aa) and the fourth lower gate line (SL4aa) may extend from the first and second subpixel circuit regions (PCA1, PCA2) to cross the virtual line (VL).

[0131] The second capacitor electrode (CE2) may overlap with the first capacitor electrode (CE1) and include a hole (CE2-H) that exposes a portion of the first capacitor electrode (CE1). The hole (CE2-H) may be a structure that is entirely surrounded by a portion of the material forming the second capacitor electrode (CE2) in a planar plane. The second capacitor electrode (CE2) may be a donut shape in a planar plane. The first capacitor electrode (CE1) and the second capacitor electrode (CE2) may form a first capacitor (Cst).

[0132] The third lower gate line (SL3aa) and the fourth lower gate line (SL4aa) may each extend along the x-direction. The third lower gate line (SL3aa) and the fourth lower gate line (SL4aa) may be spaced apart from each other with the first lower scan line (SL1a) in between. The fourth lower gate line (SL4aa) may include a third lower gate electrode (G3a), and the third lower gate line (SL3aa) may include a fourth lower gate electrode (G4a).

[0133] The second capacitor electrode (CE2), the third lower gate line (SL3aa), and the fourth lower gate line (SL4aa) contain the same material and are disposed on the same layer (e.g., the first interlayer insulating layer, 113 in FIG. 4). The third lower gate line (SL3aa) and the fourth lower gate line (SL4aa) are made of the same material as the second capacitor electrode (CE2) described earlier with reference to FIG. 4.

[0134] Referring to FIGS. 3, 4, and 10, an oxide semiconductor pattern (OSL) can be formed after forming a second interlayer insulating layer (114, FIG. 4) on the structure of FIG. 9. The oxide semiconductor pattern (OSL) placed in each of the first and second subpixel circuit regions (PCA1, PCA2) may be symmetrical with respect to the virtual line (VL) between the first and second subpixel circuit regions (PCA1, PCA2).

[0135] In this regard, FIG. 10 illustrates an oxide semiconductor pattern (OSL) disposed in each of the first and second subpixel circuit regions (PCA1, PCA2). The oxide semiconductor pattern (OSL) may be formed from an oxide-based semiconductor material, such as Zn oxide, In-Zn oxide, Ga-In-Zn oxide, etc. In some embodiments, the oxide semiconductor pattern (OSL) may include an IGZO (In-Ga-Zn-O) semiconductor, an ITZO (In-Sn-Zn-O) semiconductor, or an IGTZO (In-Ga-Sn-Zn-O) semiconductor, in which metals such as indium (In), gallium (Ga), and tin (Sn) are contained in ZnO.

[0136] The oxide semiconductor pattern (OSL) may include a third semiconductor layer (A3) of a third transistor (T3, FIG. 3) and a fourth semiconductor layer (A4) of a fourth transistor (T4, FIG. 3). The third semiconductor layer (A3) and the fourth semiconductor layer (A4) may be connected to each other to form an integral structure.

[0137] The third semiconductor layer (A3) includes a third channel region (C3) and first and second regions (B3, D3) disposed on both sides of the third channel region (C3). The first and second regions (B3, D3) of the third semiconductor layer (A3) are conductive regions and have greater electrical conductivity than the third channel region (C3). One of the first and second regions (B3, D3) may be a source region and the other may be a drain region.

[0138] The fourth semiconductor layer (A4) includes a fourth channel region (C4) and first and second regions (B4, D4) disposed on both sides of the fourth channel region (C4). The first and second regions (B4, D4) of the fourth semiconductor layer (A4) are conductive regions and have greater electrical conductivity than the fourth channel region (C4). One of the first and second regions (B4, D4) may be a source region and the other may be a drain region.

[0139] The oxide semiconductor pattern (OSL) may include a fourth capacitor electrode (CE4). The portion of the oxide semiconductor pattern (OSL) that overlaps with the third capacitor electrode (CE3, FIG. 8) may correspond to the fourth capacitor electrode (CE4). The third capacitor electrode (CE3) and the fourth capacitor electrode (CE4) may form a second capacitor (Cbt, FIG. 3).

[0140] FIG. 10 illustrates that the oxide semiconductor patterns (OSL) of the first and second subpixel circuit regions (PCA1, PCA2) are connected to each other, but the present invention is not limited thereto. In another embodiment, the oxide semiconductor pattern (OSL) of the first subpixel circuit region (PCA1) and the oxide semiconductor pattern (OSL) of the second subpixel circuit region (PCA2) may not be connected to each other.

[0141] Referring to FIGS. 3, 4, and 11, a third upper gate line (SL3ba) and a fourth upper gate line (SL4ba) may be formed on the structure of FIG. 10. Each of the third upper gate line (SL3ba) and the fourth upper gate line (SL4ba) may extend from the first and second subpixel circuit regions (PCA1, PCA2) to cross the virtual line (VL) and may be symmetrical with respect to the virtual line (VL).

[0142] At least a portion of the fourth upper gate line (SL4ba) may overlap with the fourth lower gate line (SL4aa) with an oxide semiconductor pattern (OSL) in between. The fourth upper gate line (SL4ba) includes the third upper gate electrode (G3b).

[0143] At least a portion of the third upper gate line (SL3ba) may overlap with the third lower gate line (SL3aa) with an oxide semiconductor pattern (OSL) in between. The third upper gate line (SL3ba) includes a fourth upper gate electrode (G4b).

[0144] The third upper gate line (SL3ba) and the fourth upper gate line (SL4ba) may contain the same material as the third upper gate electrode (G3b) described earlier with reference to FIG. 4.

[0145] Referring to FIGS. 3, 4, and 12, after forming a third interlayer insulating layer (116, FIG. 4) on the structure of FIG. 11, first to eleventh connecting electrodes (NM1, NM2, NM3, NM4, NM5, NM6, NM7, NM8, NM9, NM10, NM11) and a node connecting electrode (171) can be formed. The first to eleventh connecting electrodes (NM1, NM2, NM3, NM4, NM5, NM6, NM7, NM8, NM9, NM10, NM11) and the node connecting electrode (171) disposed in each of the first and second subpixel circuit regions (PCA1, PCA2) may be symmetrical with respect to the virtual line (VL) between the first and second subpixel circuit regions (PCA1, PCA2).

[0146] Referring to FIGS. 12 and 15, the first connecting electrode (NM1) can electrically connect the first semiconductor layer (A1) of the first silicon semiconductor pattern (PSL1) and the third semiconductor layer (A3) of the oxide semiconductor pattern (OSL). As shown in FIG. 15, the first connecting electrode (NM1) can be connected to a second region (D1), which is a part of the first semiconductor layer (A1), through a first contact hole (CNT1), and connected to a second region (D3), which is a part of the third semiconductor layer (A3), through a second contact hole (CNT2).

[0147] The first connection point (e.g., first contact hole, CNT1) between the first connection electrode (NM1) and the first semiconductor layer (A1) is a structurally weak part and is prone to microcracks. In order to prevent the occurrence of microcracks and / or the propagation of microcracks to the surroundings even if they occur, the lower metal layer (BML) may be extended below the first connection point between the first connection electrode (NM1) and the first semiconductor layer (A1). In this regard, FIG. 15 illustrates that the main part (BML-m) of the lower metal layer (BML) overlaps the first channel region (C1) and the second region (D2) of the first semiconductor layer (A1), and is extended to overlap the first contact hole (CNT1), which is the first connection point between the first connection electrode (NM1) and the first semiconductor layer (A1). The main portion (BML-m) of the lower metal layer (BML) can overlap with the first channel region (C1) and the second region (D2) of the first semiconductor layer (A1) described above, as well as the entire area of ​​the first gate electrode (G1).

[0148] The first connecting electrode (NM1) can overlap the main part (BML-m) of the lower metal layer (BML) as a whole. For example, the main part (BML-m) of the lower metal layer (BML) can overlap the second connection point (e.g., second contact hole, CNT2) between the first connecting electrode (NM1) and the third semiconductor layer (A3).

[0149] The first connecting electrode (NM1) is adjacent to the second capacitor electrode (CE2) but does not overlap. On a plane, one side of the first connecting electrode (NM1) may be spaced apart from one side of the second capacitor electrode (CE2) to have a first distance (d1). The first distance (d1) is the shortest distance between the first connecting electrode (NM1) and the second capacitor electrode (CE2), and may be about 0.5 μm or greater. In order to prevent or minimize the occurrence of microcracks caused by structural interference between the first connecting electrode (NM1) and the second capacitor electrode (CE2) formed below it, it may be better to form the first distance (d1) to be about 1 μm or greater.

[0150] The node connection electrode (171) can electrically connect the first gate electrode (G1) and the first region (B3) of the third semiconductor layer (A3).

[0151] Referring again to FIG. 12, the second connecting electrode (NM2) can electrically connect the fourth lower gate line (SL4aa) and the fourth upper gate line (SL4ba) using contact holes (CNTs). The fourth lower gate line (SL4aa) and the fourth upper gate line (SL4ba) can form the fourth lower scan line (SL4a).

[0152] The third connecting electrode (NM3) can electrically connect the third lower gate line (SL3aa) and the third upper gate line (SL3ba) using contact holes (CNTs). The third lower gate line (SL3aa) and the third upper gate line (SL3ba) can form the third lower scan line (SL3a).

[0153] The fourth connecting electrode (NM4) can be connected to the first lower scan line (SL1a), and the fifth connecting electrode (NM5) can be connected to the lower light emission control line (EMLa). The sixth connecting electrode (NM6) can be connected to a part of the sixth semiconductor layer (A6), and the seventh connecting electrode (NM7) can be connected to a part of the seventh semiconductor layer (A7) (e.g., the first region (B7) of FIG. 7). The eighth connecting electrode (NM8) can be connected to a part of the fourth semiconductor layer (A4). The ninth connecting electrode (NM9) can be connected to another part of the seventh semiconductor layer (A7) (e.g., the second region (D7) of FIG. 7). The 10th connecting electrode (NM10) can be connected to the 2nd semiconductor layer (A2), and the 11th connecting electrode (NM11) can be connected to the 2nd capacitor electrode (CE2).

[0154] The first and second subpixel circuit regions (PCA1, PCA2) may be surrounded by a valley (VY) on a plane. The valley (VY) of FIG. 12 is the same as the valley (VY) described earlier with reference to FIG. 4 and FIG. 5, and the valley (VY) formed by removing a portion of each of the inorganic insulating layers may be at least partially filled by an organic insulating material.

[0155] Referring to FIGS. 3, FIGS. 4, FIGS. 12 and FIGS. 13, after forming a first organic insulating layer (121, FIG. 4) on the structure of FIG. 12, a first upper scan line (SL1b), a third upper scan line (SL3b), a fourth upper scan line (SL4b), an upper light emission control line (ELMb), a first initialization voltage line (VIL1), a second initialization voltage line (VIL2"), a 20th connecting electrode (NM20), and a 21st connecting electrode (NM21) can be formed. The first upper scan line (SL1b), the third upper scan line (SL3b), the fourth upper scan line (SL4b), the upper light emission control line (ELMb), the first initialization voltage line (VIL1), and the second initialization voltage line (VIL2") can be extended along the x-direction to cross a virtual line (VL).

[0156] The first upper scan line (SL1b) can be connected to the fourth connecting electrode (NM4, FIG. 12). The first upper scan line (SL1b) can be electrically connected to the first lower scan line (SL1a, FIG. 12) via the fourth connecting electrode (NM4, FIG. 12). The first lower scan line (SL1a) shown in FIG. 12 extends in the x-direction but has an isolated shape, and therefore both ends of the first lower scan line (SL1a) cannot extend past the valley (VY). On the other hand, the first upper scan line (SL1b) shown in FIG. 13 extends in the x-direction but can cross the valley (VY). The first lower scan line (SL1a) can be electrically connected to another first lower scan line and the first upper scan line (SL1b) placed in the same row with the valley (VY) in between.

[0157] The third upper scan line (SL3b) can be connected to the third connecting electrode (NM3, FIG. 12). The third upper scan line (SL3b) can be electrically connected to the third lower scan line (SL3a, FIG. 12) via the third connecting electrode (NM3, FIG. 12). The third lower scan line (SL3a) shown in FIG. 12 extends in the x-direction but has an isolated shape, and therefore both ends of the third lower scan line (SL3b) cannot extend past the valley (VY). On the other hand, the third upper scan line (SL3b) shown in FIG. 13 extends in the x-direction but can cross the valley (VY). The third lower scan line (SL3a, FIG. 12) can be electrically connected to another third lower scan line and a third upper scan line (SL3b) placed in the same row with the valley (VY) in between.

[0158] The fourth upper scan line (SL4b) can be connected to the second connecting electrode (NM2, FIG. 12). The fourth upper scan line (SL4b) can be electrically connected to the fourth lower scan line (SL4a, FIG. 12) via the second connecting electrode (NM2, FIG. 12). The fourth lower scan line (SL4a) shown in FIG. 12 extends in the x-direction but has an isolated shape, and therefore, both ends of the fourth lower scan line (SL4a) cannot extend past the valley (VY). On the other hand, the fourth upper scan line (SL4b) shown in FIG. 13 extends in the x-direction but can cross the valley (VY). The fourth lower scan line (SL4a, FIG. 12) can be electrically connected to another fourth lower scan line and a fourth upper scan line (SL4b) placed in the same row with the valley (VY) in between.

[0159] The upper light-emitting control line (ELMb) can be connected to the fourth connecting electrode (NM5, ​​FIG. 12). The upper light-emitting control line (ELMb) can be electrically connected to the lower light-emitting control line (EMLa, FIG. 12) via the fourth connecting electrode (NM5, ​​FIG. 12). The lower light-emitting control line (EMLa) shown in FIG. 12 extends in the x-direction but has an isolated shape, and therefore, both ends of the lower light-emitting control line (EMLa) cannot extend past the valley (VY). On the other hand, the upper light-emitting control line (ELMb) shown in FIG. 13 extends in the x-direction but can cross the valley (VY). The lower light-emitting control line (EMLa) can be electrically connected to another lower light-emitting control line (EMLa) placed in the same row with the valley (VY) in between through the upper light-emitting control line (ELMb).

[0160] The first initialization voltage line (VIL1) can be connected to the eighth connection electrode (NM8, FIG. 12), and the second initialization voltage line (VIL2) can be connected to the ninth connection electrode (NM9, FIG. 12). The first initialization voltage line (VIL1) can provide a first initialization signal to the fourth transistor (T4, FIG. 3). The second initialization voltage line (VIL2) can provide a second initialization signal to the seventh transistor (T7", FIG. 3).

[0161] The 20th connection electrode (NM20) can be connected to the 10th connection electrode (NM10, FIG. 12), and the 21st connection electrode (NM21) can be connected to the 11th connection electrode (NM11, FIG. 12). The connection line (ML) can be connected to the 6th connection electrode (NM6, FIG. 12). The connection line (ML) extends along the y-direction for electrical connection between the 6th transistor (T6, FIG. 3) placed in the 1st and 2nd subpixel circuit regions (PCA1, PCA2) and the 7th transistor (T7, FIG. 3) placed in row (N-1) described above with reference to FIG. 3. Another connecting line (ML") extends along the y-direction to electrically connect the 7th transistor (T7", FIG. 3) placed in the 1st and 2nd subpixel circuit regions (PCA1, PCA2) placed in row (N) and the 6th transistor placed in row (N+1).

[0162] The first upper scan line (SL1b), the third upper scan line (SL3b), the fourth upper scan line (SL4b), the upper light emission control line (ELMb), the first initialization voltage line (VIL1), the second initialization voltage line (VIL2"), the connection lines (ML, ML"), the 20th connection electrode (NM20), and the 21st connection electrode (NM21) may include aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and / or copper (Cu), and may be formed as a single layer or a multilayer including the aforementioned materials. In one embodiment, the first upper scan line (SL1b), the third upper scan line (SL3b), the fourth upper scan line (SL4b), the upper light emission control line (ELMb), the first initialization voltage line (VIL1), the second initialization voltage line (VIL2"), the connection line (ML, ML"), the 20th connection electrode (NM20), and the 21st connection electrode (NM21) may include a triple-layer structure in which a titanium layer, an aluminum layer, and a titanium layer are stacked.

[0163] Referring to FIGS. 3, FIGS. 4, FIGS. 13, and FIGS. 14, a second organic insulating layer (123, FIG. 4) is formed on the structure of FIG. 13, and then a data line (DL), a driving voltage line (PL), and a 30th connecting electrode (NM30) are formed. The data line (DL) and the driving voltage line (PL) extend along the y-direction.

[0164] The data line (DL) is connected to the 20th connection electrode (NM20, FIG. 13). The data line (DL) can provide a data signal to the second semiconductor layer (A2, FIG. 12) via the 20th connection electrode (NM20, FIG. 13) and the 10th connection electrode (NM10, FIG. 12) below it.

[0165] The driving voltage line (PL) is connected to the 21st connecting electrode (NM21, FIG. 13). The driving voltage line (PL) can be electrically connected to the 2nd capacitor electrode (CE2, FIG. 12) via the 21st connecting electrode (NM21, FIG. 13) and the 11th connecting electrode (NM11, FIG. 12) below it.

[0166] The 30th connecting electrode (NM30) is connected to the connecting line (ML). The 30th connecting electrode (NM30) can be connected to the first electrode (210, FIG. 4) of the light-emitting diode described with reference to FIG. 4.

[0167] Data lines (DL) and driving voltage lines (PL) may extend along the y-direction across the valley (VY). Data lines (DL) and driving voltage lines (PL) may include aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and / or copper (Cu), and may be formed as a single layer or a multilayer including the aforementioned materials. In one embodiment, the data lines (DL), driving voltage lines (PL), and upper connection lines (MLb, MLb") may include a structure in which a titanium layer, an aluminum layer, and a titanium layer are stacked.

[0168] As such, the present invention has been described with reference to the embodiments illustrated in the drawings, but this is merely illustrative, and those skilled in the art will understand that various modifications and equivalent alternative embodiments are possible therefrom. Accordingly, the true technical scope of protection of the present invention should be determined by the technical spirit of the appended claims. Explanation of the symbols

[0169] 10; Common voltage supply line 11, 12, 13: 1st to 3rd common voltage input sections 20: Driving voltage supply line VSL: Common voltage line HVSL, HVSL1-HVSL3, HVSL1'-HVSL3': Horizontal common voltage line DL: Data line CL: Connection line

Claims

Claim 1 A substrate; a first silicon-based transistor disposed on the substrate and comprising a first semiconductor layer including a silicon-based semiconductor and a first gate electrode overlapping with the first semiconductor layer; at least one insulating layer on the first gate electrode; a first oxide-based transistor comprising a semiconductor layer on the at least one insulating layer, wherein the semiconductor layer includes an oxide-based semiconductor; and a first connecting electrode electrically connecting the first semiconductor layer of the first silicon-based transistor and the semiconductor layer of the first oxide-based transistor. and a lower metal layer interposed between the substrate and the first silicon-based transistor and overlapping a portion of the first semiconductor layer of the first silicon-based transistor; wherein the portion of the lower metal layer overlaps at a first connection point between a portion of the first semiconductor layer and the first connection electrode, and further comprises a plurality of inorganic insulating layers between the substrate and the first connection electrode, wherein the plurality of inorganic insulating layers comprises the at least one insulating layer, and the plurality of inorganic insulating layers comprises a valley having a first depth along the thickness direction of the plurality of inorganic insulating layers, and a second silicon-based transistor comprising a second semiconductor layer including a silicon-based semiconductor and a second gate electrode overlapping with the second semiconductor layer; A display device further comprising a first lower scan line electrically connected to the second gate electrode of the second silicon-based transistor, wherein the first lower scan line has an isolated shape on a plane and is electrically connected to a first upper scan line located on the first lower scan line and crossing the valley on the plane. Claim 2 A display device according to claim 1, wherein the first semiconductor layer comprises a folded channel region and a drain region disposed on one side of the channel region and connected to the first connecting electrode, and the portion of the lower metal layer overlaps the folded channel region and the drain region of the first semiconductor layer. Claim 3 A display device according to claim 1, wherein a portion of the lower metal layer overlaps at a second connection point between the first connecting electrode and the semiconductor layer of the first oxide-based transistor. Claim 4 In claim 1, the lower metal layer has a voltage level of a constant voltage, a display device. Claim 5 delete Claim 6 A display device according to claim 1, wherein at least a portion of the belly is filled with an organic insulating material. Claim 7 delete Claim 8 A display device according to claim 1, further comprising a storage capacitor including a first capacitor electrode and a second capacitor electrode superimposed on the first semiconductor layer of the first silicon-based transistor, wherein the at least one insulating layer comprises: a first interlayer insulating layer between the first capacitor electrode and the second capacitor electrode; and a second interlayer insulating layer on the first interlayer insulating layer, wherein the second capacitor electrode is disposed below the second interlayer insulating layer, and the semiconductor layer of the first oxide-based transistor is disposed above the second interlayer insulating layer. Claim 9 A display device according to claim 8, wherein, on a plane, the second capacitor electrode and the first connecting electrode are arranged adjacently but do not overlap each other. Claim 10 A display device according to claim 9, wherein the distance between one side of the second capacitor electrode and one side of the first connecting electrode adjacent to each other on a plane is 0.5 μm or greater. Claim 11 A substrate; a lower metal layer disposed on the substrate; a first silicon-based semiconductor pattern disposed on the lower metal layer and comprising a first semiconductor layer; and an oxide-based semiconductor pattern spaced apart from the first silicon-based semiconductor pattern. A display device comprising a first connecting electrode that electrically connects a portion of the first silicon-based semiconductor pattern and a portion of the oxide-based semiconductor pattern, wherein a portion of the lower metal layer overlaps at a connection point between the portion of the first silicon-based semiconductor pattern and the first connecting electrode, and further comprising a plurality of inorganic insulating layers between the substrate and the first connecting electrode, wherein the plurality of inorganic insulating layers include a valley having a first depth along the thickness direction of the plurality of inorganic insulating layers, and further comprising a first lower scan line on the first silicon-based semiconductor pattern, wherein the first silicon-based semiconductor pattern further comprises a second semiconductor layer connected to the first semiconductor layer, and the first lower scan line overlaps with a portion of the second semiconductor layer and is electrically connected to a first upper scan line located on the first lower scan line and crossing the valley in a plane. Claim 12 A display device according to claim 11, wherein the first semiconductor layer of the first silicon-based semiconductor pattern comprises a folded channel region and an impurity region disposed on one side of the channel region and connected to the first connecting electrode, and the portion of the lower metal layer overlaps the folded channel region and the impurity region of the first semiconductor layer. Claim 13 A display device according to claim 11, wherein the portion of the lower metal layer overlaps at a second connection point between the first connecting electrode and the oxide-based semiconductor pattern. Claim 14 In claim 11, the above-mentioned lower metal layer has a voltage level of a constant voltage, a display device. Claim 15 delete Claim 16 In paragraph 11, a display device in which at least a portion of the above-mentioned valley is filled with an organic insulating material. Claim 17 delete Claim 18 delete Claim 19 A display device according to claim 11, further comprising a first capacitor overlapping with the first semiconductor layer of the first silicon-based semiconductor pattern, wherein the first capacitor comprises a first capacitor electrode and a second capacitor electrode on the first capacitor electrode. Claim 20 A display device according to claim 19, wherein, on a plane, the second capacitor electrode and the first connecting electrode are arranged adjacently but do not overlap each other. Claim 21 An electronic device comprising a display device according to any one of paragraphs 1 through 4, paragraph 6, paragraphs 8 through 14, paragraph 16, paragraph 19, and paragraph 20.

Images