Display apparatus

Abstract

The present invention, in order to implement a display device with an expanded display area that reduces power consumption and enables an image to be displayed even in an area where electronic components are placed, and to implement a display device that prevents degradation of display quality by protecting pixel circuits placed around an area where electronic components are placed from external light, comprises: a first display area in which a plurality of first light-emitting elements are placed; a second display area in which a plurality of second light-emitting elements are placed and which includes a transmission area; a third display area in which a plurality of third light-emitting elements are placed and which is located between the first display area and the second display area; and a plurality of pixel circuits placed in the third display area and electrically connected to each of the plurality of third light-emitting elements, wherein each of the plurality of pixel circuits comprises: a first thin-film transistor having a first semiconductor layer and a first gate electrode that overlaps at least a portion with the first semiconductor layer; and a second thin-film transistor having a second semiconductor layer having a material different from the first semiconductor layer and a second gate electrode that overlaps at least a portion with the second semiconductor layer. A display device is provided comprising: a lower shielding layer located below the second semiconductor layer and arranged to overlap at least a portion of the second semiconductor layer on a plane.

Description

Technology Field

[0001] The present invention relates to a display device. Background Technology

[0002] Electronic devices based on mobility are widely used. In addition to small electronic devices such as mobile phones, tablet PCs have recently become widely used as mobile electronic devices. Such mobile electronic devices include display devices to provide users with various functions, such as visual information like images or videos.

[0003] Recently, as other components for driving display devices become smaller, the proportion of display devices in electronic devices is gradually increasing, and the demand for high-resolution display devices is growing. Accordingly, research is actively underway to address the issues of high integration and power consumption in display devices. Furthermore, as display devices are utilized in diverse ways, the number of functions that can be integrated or linked to display devices is increasing. The problem to be solved

[0004] Embodiments of the present invention aim to provide a display device with an expanded display area that reduces power consumption and enables image display even in the area where electronic components are placed. Additionally, the invention aims to provide a display device that prevents degradation of display quality by protecting pixel circuits placed around the area where electronic components are placed from external light. However, these objectives are exemplary and do not limit the scope of the present invention. means of solving the problem

[0005] According to one aspect of the present invention, a display device is provided comprising: a first display area in which a plurality of first light-emitting elements are arranged; a second display area in which a plurality of second light-emitting elements are arranged and which includes a transmission area; a third display area in which a plurality of third light-emitting elements are arranged and which is located between the first display area and the second display area; and a plurality of pixel circuits arranged in the third display area and electrically connected to each of the plurality of third light-emitting elements, wherein each of the plurality of pixel circuits comprises: a first thin-film transistor having a first semiconductor layer and a first gate electrode that overlaps at least a portion with the first semiconductor layer; a second thin-film transistor having a second semiconductor layer having a material different from the first semiconductor layer and a second gate electrode that overlaps at least a portion with the second semiconductor layer; and a lower shielding layer located below the second semiconductor layer and arranged to overlap at least a portion with the second semiconductor layer on a plane.

[0006] According to the present embodiment, the first semiconductor layer of the first thin-film transistor comprises a silicon semiconductor material, and the second semiconductor layer of the second thin-film transistor may comprise an oxide semiconductor material.

[0007] According to the present embodiment, the device further comprises a wiring layer containing the same material as the second gate electrode of the second thin-film transistor, and the wiring layer can be electrically connected to the lower shielding layer through a contact hole located in the third display area.

[0008] According to the present embodiment, each of the plurality of pixel circuits further includes a capacitor electrode that overlaps at least a portion with the first gate electrode of the first thin-film transistor, and the lower shielding layer may include the same material as the capacitor electrode.

[0009] According to the present embodiment, the lower shielding layer may include the same material as the first gate electrode of the first thin-film transistor.

[0010] According to the present embodiment, the lower shielding layer may include the same material as the first semiconductor layer of the first thin-film transistor.

[0011] According to the present embodiment, the first thin-film transistor may further include a lower metal layer located below the first semiconductor layer and overlapping with the first semiconductor layer on a plane.

[0012] According to the present embodiment, a light-blocking member located in the third display area and comprising at least two conductive layers may be further included.

[0013] According to the present embodiment, the light blocking member may be positioned on a plane so as to be closer to the second display area than to the plurality of pixel circuits.

[0014] According to the present embodiment, the light blocking member may be arranged to surround at least a portion of the second display area on a flat surface.

[0015] According to the present embodiment, the at least two conductive layers of the light blocking portion may include a first conductive layer comprising the same material as the first gate electrode or the second gate electrode, and a second conductive layer located on the first conductive layer and electrically connected to the first conductive layer.

[0016] According to the present embodiment, the first thin-film transistor further comprises a lower metal layer located below the first semiconductor layer and overlapping with the first semiconductor layer on a plane; and the at least two conductive layers of the light-blocking portion may further comprise a third conductive layer that is electrically connected to the first conductive layer and has the same material as the lower metal layer.

[0017] According to the present embodiment, each of the plurality of third light-emitting elements comprises a pixel electrode, a counter electrode on the pixel electrode, and an intermediate layer between the pixel electrode and the counter electrode, and the pixel electrode can overlap with the second thin-film transistor of each of the plurality of pixel circuits on a plane.

[0018] According to another aspect of the present invention, a substrate having a first region, a second region, and a third region between the first region and the second region; a first semiconductor layer disposed on the substrate and located in the third region and comprising a silicon semiconductor material; a first insulating layer covering the first semiconductor layer; a first gate electrode disposed on the first insulating layer and at least partially overlapping with the first semiconductor layer; a second insulating layer covering the first gate electrode; a second semiconductor layer disposed on the second insulating layer and located in the third region and comprising an oxide semiconductor material; a third insulating layer covering the second semiconductor layer; and a second gate electrode disposed on the third insulating layer and at least partially overlapping with the second semiconductor layer. A display device is provided comprising: a lower shielding layer interposed between the substrate and the second semiconductor layer and overlapping with at least a portion of the second semiconductor layer on a plane; wherein each of the first to third insulating layers includes a hole overlapping with a portion of the second region.

[0019] According to the present embodiment, the method further comprises a wiring layer disposed on the third insulating layer and containing the same material as the second gate electrode, and the lower shielding layer may be electrically connected to the wiring layer through a contact hole located in the third region.

[0020] According to the present embodiment, the lower shielding layer may include the same material as the first gate electrode or the first semiconductor layer.

[0021] According to the present embodiment, a lower metal layer interposed between the substrate and the first semiconductor layer and overlapping with the first semiconductor layer on a plane may be further included.

[0022] According to the present embodiment, the apparatus further comprises a fourth insulating layer covering the second gate electrode; and a light blocking portion located in the third region; wherein the light blocking portion may include a first conductive layer disposed on the same layer as the first gate electrode or the second gate electrode, and a second conductive layer disposed on the fourth insulating layer, the second conductive layer being electrically connected to the first conductive layer through a contact hole formed in the fourth insulating layer.

[0023] According to the present embodiment, the light blocking member may be positioned on a plane so as to be closer to the second region than to the region where the second semiconductor layer is placed among the third regions.

[0024] According to the present embodiment, the light blocking member may be arranged to surround at least a portion of the second region on a flat plane.

[0025] Other aspects, features, and advantages other than those described above will become clear from the following specific details, claims, and drawings for implementing the invention.

[0026] These general and specific aspects may be implemented using a system, method, computer program, or any combination of a system, method, or computer program. Effects of the invention

[0027] According to the embodiments of the present invention as described above, a display device with an expanded display area can be implemented to reduce power consumption and enable image display even in the area where electronic components are placed. Additionally, a display device can be implemented that prevents degradation of display quality by protecting pixel circuits placed around the area where electronic components are placed from external light. Of course, the scope of the present invention is not limited by these effects. Brief explanation of the drawing

[0028] FIG. 1 is a perspective view schematically illustrating an electronic device including a display device according to one embodiment of the present invention. FIG. 2 is a cross-sectional view schematically illustrating a part of an electronic device according to one embodiment of the present invention. FIG. 3 is an equivalent circuit diagram of any one pixel circuit included in a display device according to one embodiment of the present invention. FIG. 4 is a plan view schematically illustrating the arrangement of pixels of a display device according to one embodiment of the present invention. FIG. 5 is a cross-sectional view schematically illustrating a part of a display device according to one embodiment of the present invention. FIG. 6 is a cross-sectional view schematically illustrating a part of a display device according to another embodiment of the present invention. FIG. 7 is a cross-sectional view schematically illustrating a part of a display device according to another embodiment of the present invention. FIG. 8 is a schematic layout diagram illustrating some components of a display device according to one embodiment of the present invention. Specific details for implementing the invention

[0029] The present invention is capable of various modifications and may have various embodiments; specific embodiments are illustrated in the drawings and described in detail in the detailed description. The effects and features of the present invention, and the methods for achieving them, will become clear by referring to the embodiments described below in detail together with the drawings. However, the present invention is not limited to the embodiments disclosed below but can be implemented in various forms.

[0030] Hereinafter, embodiments of the present invention will be described in detail with reference to the attached drawings. When describing with reference to the drawings, identical or corresponding components are given the same reference numerals, and redundant descriptions thereof will be omitted.

[0031] In the following embodiments, terms such as first, second, etc. are used not in a limiting sense, but for the purpose of distinguishing one component from another component.

[0032] In the following examples, singular expressions include plural expressions unless the context clearly indicates otherwise.

[0033] In the following embodiments, terms such as "include" or "have" mean that the features or components described in the specification are present, and do not preclude the possibility that one or more other features or components may be added.

[0034] In the following embodiments, when a part such as a film, region, or component is described as being on or above another part, it includes not only cases where it is directly on top of another part, but also cases where another film, region, or component is interposed in between.

[0035] In the drawings, the size of components may be exaggerated or reduced for convenience of explanation. For example, the size and thickness of each component shown in the drawings are depicted arbitrarily for convenience of explanation, so the present invention is not necessarily limited to what is illustrated.

[0036] Where an embodiment can be implemented differently, a specific process sequence may be performed differently from the order described. For example, two processes described consecutively may be performed substantially simultaneously or proceed in the reverse order of the description.

[0037] In this specification, "A and / or B" indicates the case where it is A, B, or both A and B. And, "at least one of A and B" indicates the case where it is A, B, or both A and B.

[0038] In the following embodiments, when a membrane, region, component, etc. is described as being connected, it includes cases where the membrane, region, or component is directly connected, or / or cases where other membranes, regions, or components are interposed between the membranes, regions, or components to be indirectly connected. For example, when a membrane, region, component, etc. is described as being electrically connected in this specification, it indicates cases where the membrane, region, or component, etc. are directly electrically connected, and / or cases where other membranes, regions, or components are interposed between them to be indirectly electrically connected.

[0039] The x-axis, y-axis, and z-axis are not limited to the three axes of an orthogonal coordinate system but can be interpreted in a broader sense that includes them. For example, the x-axis, y-axis, and z-axis may be orthogonal to each other, but they may also refer to different directions that are not orthogonal to each other.

[0040] FIG. 1 is a perspective view schematically illustrating an electronic device including a display device according to one embodiment of the present invention.

[0041] Referring to FIG. 1, the electronic device (1) may include a display area (DA) and a surrounding area (PA) adjacent to the display area (DA). The electronic device (1) may provide an image through an array of multiple pixels (PX) arranged in the display area (DA).

[0042] A display area (DA) may include a first display area (DA1), a second display area (DA2) having a transparent area (TA), and a third display area (DA3) located between the first display area (DA1) and the second display area (DA2). A plurality of pixels (PX) may include a plurality of first pixels (PX1) located in the first display area (DA1), a plurality of second pixels (PX2) located in the second display area (DA2), and a plurality of third pixels (PX3) located in the third display area (DA3).

[0043] In one embodiment, an array of multiple first pixels (PX1) may be different from an array of multiple second pixels (PX2). For example, a transparent area (TA) may be disposed between multiple second pixels (PX2) and / or adjacent to multiple second pixels (PX2), so that the array of multiple first pixels (PX1) and the array of multiple second pixels (PX2) may be different from each other. In one embodiment, an array of multiple first pixels (PX1) may be identical to an array of multiple third pixels (PX3).

[0044] The electronic device (1) may provide a first image using light emitted from first pixels (PX1) placed in a first display area (DA1), provide a second image using light emitted from second pixels (PX2) placed in a second display area (DA2), and provide a third image using light emitted from third pixels (PX3) placed in a third display area (DA3). In some embodiments, the first to third images may be parts of any one image provided through the display area (DA) of the electronic device (1). Or, in some embodiments, the electronic device (1) may provide first to third images that are independent of each other. Or, in some embodiments, the electronic device (1) may have the first image and the third image as parts of any one image, and the second image as an image independent of said one image.

[0045] As described above, the second display area (DA2) may include a transmission area (TA) located between the second pixels (PX2) and / or adjacent to the second pixels (PX2). The transmission area (TA) is an area through which light can pass, and may not have pixels (PX) placed therein.

[0046] The peripheral area (PA) is a non-display area that does not provide an image and can surround the display area (DA) entirely or partially. Drivers or the like for providing electrical signals or power to the display area (DA) may be placed in the peripheral area (PA). Pads, which are areas where electronic components or printed circuit boards can be electrically connected, may be placed in the peripheral area (PA).

[0047] Meanwhile, the second display area (DA2) may have a circular shape or an elliptical shape on a plane as shown in FIG. 1. Alternatively, the second display area (DA2) may have a polygonal shape such as a square or a bar type. The present invention is not limited to a specific shape on a plane of the second display area (DA2).

[0048] The second display area (DA2) may be positioned inside the first display area (DA1) or on one side of the first display area (DA1). As illustrated in FIG. 1, the second display area (DA2) may be entirely surrounded by the first display area (DA1). In some embodiments, the second display area (DA2) may be partially surrounded by the first display area (DA1). For example, the second display area (DA2) may be partially surrounded by the first display area (DA1) while being located at one corner of the first display area (DA1).

[0049] The ratio of the second display area (DA2) to the display area (DA) may be smaller than the ratio of the first display area (DA1) to the display area (DA). The electronic device (1) may include one second display area (DA2) as shown in FIG. 1, or two or more second display areas (DA2).

[0050] A third display area (DA3) may be positioned between a first display area (DA1) and a second display area (DA2). As illustrated in FIG. 1, the third display area (DA3) may completely surround the second display area (DA2) and may be completely surrounded by the first display area (DA1). In some embodiments, the third display area (DA3) may partially surround the second display area (DA2).

[0051] The electronic device (1) may have a rounded rectangular shape on a flat surface as shown in FIG. 1, but is not limited thereto. The electronic device (1) may have various shapes such as polygons, circles, and ellipses.

[0052] The electronic device (1) may include a mobile phone, tablet PC, laptop, smart watch or smart band worn on the wrist, electronic device for vehicles, etc.

[0053] FIG. 2 is a cross-sectional view schematically illustrating a part of an electronic device according to one embodiment of the present invention.

[0054] Referring to FIG. 2, the electronic device (1) may include a display device (10) and an electronic component (20) positioned overlapping the display device (10).

[0055] The display device (10) may include a substrate (100), a display layer (DPL) disposed on the substrate (100), and a thin film encapsulation layer (300) on the display layer (DPL).

[0056] The electronic component (20) may be positioned to overlap with the second display area (DA2). The electronic component (20) may be an electronic element that uses light or sound. For example, the electronic element may be a sensor that measures distance, such as a proximity sensor; a sensor that recognizes a part of the user's body (e.g., fingerprint, iris, face, etc.); a small lamp that emits light; or an image sensor that captures images (e.g., a camera). An electronic element that uses light may use light of various wavelength bands, such as visible light, infrared light, or ultraviolet light. An electronic element that uses sound may use ultrasound or sound of other frequency bands. In some embodiments, the electronic component (20) may include sub-components such as a light-emitting part and a light-receiving part. The light-emitting part and the light-receiving part may have an integrated structure, or a pair of light-emitting parts and light-receiving parts may form a single electronic component (20) with physically separated structures.

[0057] The substrate (100) of the display device (10) may include glass or a polymer resin. The substrate (100) may have a multilayer structure including a layer containing the aforementioned polymer resin and an inorganic layer (not shown).

[0058] A buffer layer (111) and a display layer (DPL) may be disposed on the front surface of the substrate (100), and a lower protection film (175) may be disposed on the back surface of the substrate (100). The lower protection film (175) may be attached to the back surface of the substrate (100). An adhesive layer may be interposed between the lower protection film (175) and the substrate (100). Alternatively, the lower protection film (175) may be formed directly on the back surface of the substrate (100), in which case no adhesive layer is interposed between the lower protection film (175) and the substrate (100).

[0059] The lower protective film (175) can serve to support and protect the substrate (100). The lower protective film (175) may have an opening (175OP) corresponding to the second display area (DA2). The opening (175OP) of the lower protective film (175) is a concave portion formed by removing a portion of the lower protective film (175) in the thickness direction. In some embodiments, the opening (175OP) of the lower protective film (175) may be formed by removing a portion of the lower protective film (175) entirely along the thickness direction, in which case it may have the shape of a through-hole as shown in FIG. 2. In some embodiments, the opening (175OP) of the lower protective film (175) may have the shape of a blind-hole by removing a portion of the lower protective film (175) partially along the thickness direction.

[0060] By having an opening (175OP) in the lower protective film (175), the transmittance of the second display area (DA2), such as the light transmittance of the transmission area (TA), can be improved. The lower protective film (175) may include an organic insulating material such as polyethylene terephthalate (PET) or polyimide (PI).

[0061] The display layer (DPL) may include a light-emitting diode as a light-emitting element (200). The light-emitting diode may be, for example, an organic light-emitting diode (OLED). Additionally, the display layer (DPL) may include a thin-film transistor (TFT) electrically connected to the light-emitting element (200), and insulating layers (IL) located above, below, and / or between the layers constituting the thin-film transistor (TFT). The light-emitting element (200), for example, an organic light-emitting diode (OLED), may emit light of different colors, such as red, green, or blue, depending on the type of organic material included. The light-emitting element (200) of the display layer (DPL) emits light through a light-emitting region, and the light-emitting region may be defined as a pixel (PX). A pixel (PX) may be defined as a region capable of emitting light of, for example, red, green, or blue. Since an array of pixels (PX) forms a display area (DA), the light-emitting element is located in the display area (DA).

[0062] In one embodiment, a first light-emitting element (200-1), a second light-emitting element (200-2), and a third light-emitting element (200-3) may be disposed in a first display area (DA1), a second display area (DA2), and a third display area (DA3), respectively. As described above, the first to third light-emitting elements (200-1, 200-2, 200-3) may each be electrically connected to a thin-film transistor. The light-emitting areas in which the first to third light-emitting elements (200-1, 200-2, 200-3) each emit light may be defined as first to third pixels (PX1, PX2, PX3). In some embodiments, the thin-film transistor electrically connected to the second light-emitting element (200-2) may be located in the first display area (DA1), the third display area (DA3), and / or the surrounding area (PA).

[0063] The second display area (DA2) may include a transmission area (TA) in which thin-film transistors (TFTs) and organic light-emitting diodes (OLEDs) are not placed. The transmission area (TA) is an area through which light emitted from and / or directed toward the electronic component (20) can be transmitted. In the display device (10), the transmittance of the transmission area (TA) may be about 30% or more, about 40% or more, about 50% or more, about 60% or more, about 75% or more, about 80% or more, about 85% or more, or about 90% or more.

[0064] The display layer (DPL) may be sealed with a sealing member. In some embodiments, the sealing member may include a thin film sealing layer (300) as shown in FIG. 2. The thin film sealing layer (300) may include at least one inorganic layer and at least one organic layer. In one embodiment, the thin film sealing layer (300) may include first and second inorganic layers (310, 330) and an organic layer (320) between them. The first and second inorganic layers (310, 330) may include one or more inorganic insulating materials such as silicon oxide (SiO2), silicon nitride (SiNx), silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), or zinc oxide (ZnO2). The organic layer (320) may include a polymer-based material. Polymer-based materials may include silicone resins, acrylic resins, epoxy resins, polyimide, and polyethylene.

[0065] In the second display area (DA2), one electronic component (20) may be disposed, or multiple electronic components (20) may be disposed. When the electronic device (1) includes multiple electronic components (20), the electronic device (1) may include a number of second display areas (DA2) corresponding to the number of electronic components (20). For example, the electronic device (1) may include multiple second display areas (DA2) that are spaced apart from each other. In some embodiments, multiple electronic components (20) may be disposed in a single second display area (DA2). For example, the electronic device (1) may include a bar-type second display area (DA2), and multiple electronic components (20) may be spaced apart from each other along the length direction of the second display area (DA2).

[0066] According to one embodiment of the present invention, a second pixel (PX2) is disposed in the second display area (DA2), so the second display area (DA2) can display an image. Additionally, the second display area (DA2) is an area where an electronic component (20) is disposed and includes a transmission area (TA) through which light / signal toward the electronic component (20) and light / signal from the electronic component (20) can be transmitted, so it may be an area where a function by the electronic component (20) is performed. Through this, a display device (10) with an expanded display area can be implemented so that image expression is possible even in the area where the electronic component (20) is disposed.

[0067] Meanwhile, FIG. 2 describes a display device (10) that includes an organic light-emitting diode (OLED) as a light-emitting element (200), but the display device (10) of the present invention is not limited thereto. As another embodiment, the display device (10) may be an inorganic light-emitting display device including an inorganic material such as a micro LED, a quantum dot light-emitting display, or an organic-inorganic composite light-emitting display device. However, for convenience of explanation, the following description will focus on the case where the display device (10) includes an organic light-emitting diode (OLED) as a light-emitting element (200).

[0068] FIG. 3 is an equivalent circuit diagram of any one pixel circuit included in a display device according to one embodiment of the present invention.

[0069] Referring to FIG. 3, the pixel circuit (PC) may include first to seventh thin-film transistors (T1, T2, T3, T4, T5, T6, T7), a first capacitor (Cst), and a second capacitor (Cbt). Additionally, the pixel circuit (PC) may be connected to a plurality of signal lines, first and second initialization voltage lines (VIL1, VIL2), and a power supply voltage line (PL). The signal lines may include a data line (DL), a first scan line (SL1), a second scan line (SL2), a third scan line (SL3), a fourth scan line (SL4), and a light emission control line (EL). In another embodiment, at least one of the signal lines, the first and second initialization voltage lines (VIL1, VIL2) and / or the power supply voltage line (PL) may be shared among adjacent pixel circuits.

[0070] The power supply voltage line (PL) can transmit a driving power supply voltage (ELVDD) to the first thin-film transistor (T1). The first initialization voltage line (VIL1) can transmit a first initialization voltage (Vint1) that initializes the first thin-film transistor (T1) to the pixel circuit (PC). The second initialization voltage line (VIL2) can transmit a second initialization voltage (Vint2) that initializes the organic light-emitting diode (OLED) to the pixel circuit (PC).

[0071] For example, in FIG. 3, among the first to seventh thin-film transistors (T1 to T7), the third thin-film transistor (T3) and the fourth thin-film transistor (T4) are implemented as NMOS (n-channel MOSFET), and the rest are implemented as PMOS (p-channel MOSFET).

[0072] The first thin-film transistor (T1) is connected to the power supply voltage line (PL) via the fifth thin-film transistor (T5) and can be electrically connected to the organic light-emitting diode (OLED) via the sixth thin-film transistor (T6). The first thin-film transistor (T1) acts as a driving thin-film transistor and can receive a data signal (Dm) according to the switching operation of the second thin-film transistor (T2) and supply a driving current (Id) to the organic light-emitting diode (OLED).

[0073] The second thin-film transistor (T2) is a switching thin-film transistor and is connected to the first scan line (SL1) and the data line (DL), and can be connected to the power supply voltage line (PL) via the fifth thin-film transistor (T5). The second thin-film transistor (T2) can perform a switching operation in which it is turned on according to the first scan signal (Sn) received through the first scan line (SL1) and transmits the data signal (Dm) transmitted to the data line (DL) to the first node (N1).

[0074] The third thin-film transistor (T3) is a compensation thin-film transistor and is connected to the fourth scan line (SL4), and can be connected to an organic light-emitting diode (OLED) via the sixth thin-film transistor (T6). The third thin-film transistor (T3) is turned on according to the fourth scan signal (Sn') received through the fourth scan line (SL4) and can diode-connect the first thin-film transistor (T1).

[0075] The fourth thin-film transistor (T4) is a first initialization thin-film transistor and is connected to the third scan line (SL3), which is a previous scan line, and the first initialization voltage line (VIL1). It is turned on according to the third scan signal (Sn-1), which is a previous scan signal received through the third scan line (SL3), and transmits the first initialization voltage (Vint1) from the first initialization voltage line (VIL1) to the gate electrode of the first thin-film transistor (T1) to initialize the voltage of the gate electrode of the first thin-film transistor (T1).

[0076] The fifth thin-film transistor (T5) may be an operation control thin-film transistor, and the sixth thin-film transistor (T6) may be a light-emitting control thin-film transistor. The fifth thin-film transistor (T5) and the sixth thin-film transistor (T6) are connected to a light-emitting control line (EL), and are simultaneously turned on according to a light-emitting control signal (En) received through the light-emitting control line (EL) to form a current path so that a driving current (Id) can flow from the power supply voltage line (PL) toward the organic light-emitting diode (OLED).

[0077] The seventh thin-film transistor (T7) is a second initialization thin-film transistor and is connected to the second scan line (SL2), which is the next scan line, and the second initialization voltage line (VIL2). It is turned on according to the second scan signal (Sn+1), which is the next scan signal received through the second scan line (SL2), and transmits the second initialization voltage (Vint2) from the second initialization voltage line (VIL2) to the organic light-emitting diode (OLED) to initialize the organic light-emitting diode (OLED). In some embodiments, the seventh thin-film transistor (T7) may be omitted.

[0078] The first capacitor (Cst) may include a first electrode (CE1) and a second electrode (CE2). The first electrode (CE1) may be connected to the gate electrode of the first thin-film transistor (T1), and the second electrode (CE2) may be connected to the power supply voltage line (PL). The first capacitor (Cst) can maintain the voltage applied to the gate electrode of the first thin-film transistor (T1) by storing and maintaining a voltage corresponding to the difference between the voltages of the power supply voltage line (PL) and the gate electrode of the first thin-film transistor (T1).

[0079] The second capacitor (Cbt) may include a third electrode (CE3) and a fourth electrode (CE4). The third electrode (CE3) may be connected to the gate electrode of the first scan line (SL1) and the second thin-film transistor (T2). The fourth electrode (CE4) may be connected to the gate electrode of the first thin-film transistor (T1) and the first electrode (CE1) of the first capacitor (Cst). The second capacitor (Cbt) is a boosting capacitor, and when the first scan signal (Sn) of the first scan line (SL1) is a voltage that turns off the second thin-film transistor (T2), it can increase the voltage of the second node (N2) to reduce the voltage that displays black (black voltage).

[0080] An organic light-emitting diode (OLED) includes a pixel electrode and a counter electrode, and the counter electrode can receive a common power supply voltage (ELVSS). The organic light-emitting diode (OLED) receives a driving current (Id) from a first thin-film transistor (T1) and emits light to display an image.

[0081] The specific operation of each pixel circuit (PC) according to one embodiment is as follows.

[0082] During the first initialization period, when a third scan signal (Sn-1) is supplied through the third scan line (SL3), the fourth thin-film transistor (T4) is turned on in response to the third scan signal (Sn-1), and the first thin-film transistor (T1) can be initialized by the first initialization voltage (Vint1) supplied from the first initialization voltage line (VIL1).

[0083] During the data programming period, when the first scan signal (Sn) and the fourth scan signal (Sn') are supplied through the first scan line (SL1) and the fourth scan line (SL4), respectively, the second thin-film transistor (T2) and the third thin-film transistor (T3) can be turned on in response to the first scan signal (Sn) and the fourth scan signal (Sn'). At this time, the first thin-film transistor (T1) can be diode-connected to the turned-on third thin-film transistor (T3) and forward-biased. Then, a voltage compensated for the threshold voltage (Vth) of the first thin-film transistor (T1) from the data signal (Dm) supplied from the data line (DL) can be applied to the gate electrode of the first thin-film transistor (T1). A driving power supply voltage (ELVDD) and a compensation voltage are applied to both ends of the first capacitor (Cst), and a charge corresponding to the voltage difference between the two ends can be stored in the first capacitor (Cst).

[0084] During the light emission period, the fifth thin-film transistor (T5) and the sixth thin-film transistor (T6) can be turned on by a light emission control signal (En) supplied from the light emission control line (EL). A driving current (Id) is generated according to the voltage difference between the voltage of the gate electrode of the first thin-film transistor (T1) and the driving power supply voltage (ELVDD), and the driving current (Id) can be supplied to the organic light-emitting diode (OLED) through the sixth thin-film transistor (T6).

[0085] During the second initialization period, when the second scan signal (Sn+1) is supplied through the second scan line (SL2), the seventh thin-film transistor (T7) is turned on in response to the second scan signal (Sn+1), and the organic light-emitting diode (OLED) is initialized by the second initialization voltage (Vint2) supplied from the second initialization voltage line (VIL2).

[0086] Meanwhile, in one embodiment, a plurality of thin-film transistors (T1 to T7) may include silicon-based thin-film transistors comprising a silicon semiconductor. In another embodiment, at least one of the plurality of thin-film transistors (T1 to T7) may include an oxide-based thin-film transistor comprising an oxide semiconductor, and the remainder may include silicon-based thin-film transistors comprising a silicon semiconductor.

[0087] Specifically, the first thin-film transistor (T1), which directly affects the brightness of the display device (10, see FIG. 1), is composed of a silicon-based thin-film transistor including a silicon semiconductor layer composed of polycrystalline silicon with high reliability, thereby enabling the implementation of a high-resolution display device.

[0088] Meanwhile, since oxide semiconductors have high carrier mobility and low leakage current, the voltage drop is not significant even when the driving time is long. In other words, since the color change of the image due to the voltage drop is not significant even during low-frequency driving, low-frequency driving is possible. As oxide semiconductors have the advantage of low leakage current, at least one of the third thin-film transistor (T3) and the fourth thin-film transistor (T4) connected to the gate electrode of the first thin-film transistor (T1) is equipped with an oxide semiconductor to prevent leakage current from flowing to the gate electrode of the first thin-film transistor (T1) while simultaneously reducing power consumption.

[0089] According to one embodiment of the present invention, a pixel circuit (PC) located in a first display area (DA1) having the largest area ratio among the display areas (DA) is provided with a plurality of thin-film transistors (T1 to T7), wherein at least one of the plurality of thin-film transistors (T1 to T7) is an oxide-based thin-film transistor and the remainder are silicon-based thin-film transistors. Specifically, the first thin-film transistor (T1), the second thin-film transistor (T2), and the fifth to seventh thin-film transistors (T5, T6, T7) of the first display area (DA1) are silicon-based thin-film transistors, and the third and fourth thin-film transistors (T3, T4) of the first display area (DA1) are oxide-based thin-film transistors. In addition, a pixel circuit (PC) located in a third display area (DA3) adjacent to the first display area (DA1) may also have the same configuration as the pixel circuit (PC) of the first display area (DA1). Through this, a display device (10) can be provided that achieves high resolution while preventing leakage current and reducing power consumption.

[0090] In an optional embodiment, the plurality of thin-film transistors (T1 to T7) of the pixel circuit (PC) located in the second display area (DA2) may be, as described above, at least one oxide-based thin-film transistor and the remainder silicon-based thin-film transistors. Alternatively, the plurality of thin-film transistors (T1 to T7) of the second display area (DA2) may all be silicon-based thin-film transistors. Hereinafter, for convenience of explanation, the case where the plurality of thin-film transistors (T1 to T7) of the pixel circuit (PC) located in the second display area (DA2) are all silicon-based thin-film transistors will be described.

[0091] FIG. 4 is a plan view schematically illustrating the arrangement of pixels of a display device according to one embodiment of the present invention.

[0092] Referring to FIG. 4, a plurality of first pixels (PX1) may be arranged in a first display area (DA1). The plurality of first pixels (PX1) may include, for example, a red first pixel, a green first pixel, and a blue first pixel, and the red first pixel, the green first pixel, and the blue first pixel may have different sizes (i.e., areas) from each other. FIG. 4 illustrates a plurality of first pixels (PX1) arranged in a pentile type, but the present invention is not limited thereto and may be arranged in various forms such as a stripe type.

[0093] A plurality of second pixels (PX2) may be arranged in the second display area (DA2). The plurality of second pixels (PX2) may include, for example, a red second pixel, a green second pixel, and a blue second pixel, and these may differ in size (i.e., area).

[0094] The second display area (DA2) may include a pixel group (PG) comprising at least one second pixel (PX2) and a transmission area (TA). In one embodiment, as shown in FIG. 4, a transmission area (TA) may be placed between adjacent pixel groups (PG). In another embodiment, the pixel group (PG) and the transmission area (TA) may be arranged alternately along the x and y directions, for example, the pixel group (PG) and the transmission area (TA) may be arranged in a grid shape. In yet another embodiment, the transmission area (TA) may be formed by being arranged to completely surround a plurality of adjacent pixel groups (PG). As such, the present invention is not limited to a specific arrangement of the pixel group (PG) and the transmission area (TA) and can be designed in various ways according to various purposes.

[0095] A pixel group (PG) can be defined as a collection of pixels that groups multiple second pixels (PX2) into a preset unit. For example, as shown in FIG. 4, one pixel group (PG) may include eight second pixels (PX2) arranged in a pentile structure. For example, one pixel group (PG) may include two red second pixels, four green second pixels, and two blue second pixels. Of course, the present invention is not necessarily limited thereto, and the number of second pixels (PX2) included in the pixel group (PG) may be modified according to the resolution of the second display area (DA2).

[0096] The transmission area (TA) is an area for light to pass through, and the second pixel (PX2) may not be placed therein. Additionally, the pixel circuit (PC, see FIG. 3) and various signal lines electrically connected to the pixel circuit (PC) may not be placed in the transmission area (TA).

[0097] Since the second display area (DA2) includes a transmission area (TA), as shown in FIG. 4, the number of first pixels (PX1) in the first display area (DA1) per equal area may be greater than the number of second pixels (PX2) in the second display area (DA2). That is, the resolution in the first display area (DA1) may be higher than the resolution in the second display area (DA2).

[0098] A plurality of third pixels (PX3) may be arranged in the third display area (DA3). The plurality of third pixels (PX3) may include, for example, a red third pixel, a green third pixel, and a blue third pixel, and these may differ in size (i.e., area). The arrangement of the plurality of third pixels (PX3) may be identical to the arrangement of the plurality of first pixels (PX1). For example, as shown in FIG. 4, if the first pixels (PX1) are arranged in a pentile shape, the third pixels (PX3) may also be arranged in a pentile shape.

[0099] As described above, the third display area (DA3) can be located between the first display area (DA1) and the second display area (DA2), and can be located adjacent to each of the first display area (DA1) and the second display area (DA2). Accordingly, a plurality of third pixels (PX3) can be adjacent to the first pixel (PX1), as well as adjacent to the transmission area (TA) of the second display area (DA2).

[0100] According to one embodiment of the present invention, a light blocking member (500) may be located in the third display area (DA3). The light blocking member (500) may be located on a plane between the transmission area (TA) of the second display area (DA2) and the third pixel (PX3) of the third display area (DA3). In other words, the light blocking member (500) may be located closer to the transmission area (TA) than to the third pixel (PX3).

[0101] The light blocking members (500) may be arranged to surround at least a portion of the second display area (DA2) on a plane. Here, the expression "on a plane" may mean "on a virtual plane when looking vertically at one side of the substrate (100, see FIG. 2) of the display device (10)." In one embodiment, as shown in FIG. 4, the light blocking members (500) may be provided in multiple numbers, formed in an island shape or isolated shape on a plane, and arranged spaced apart from each other. The multiple light blocking members (500) may be arranged along the boundary between the second display area (DA2) and the third display area (DA3) (i.e., the edge of the second display area). By doing so, the multiple light blocking members (500) may surround at least a portion of the second display area (DA2). In another embodiment, the light blocking portion (500) may be formed integrally, in which case the light blocking portion (500) may extend along the edge of the second display area (DA2) to surround at least a portion of the second display area (DA2).

[0102] Referring to FIG. 5 below, the structure and function of the light blocking unit (500) will be explained in more detail.

[0103] FIG. 5 is a cross-sectional view schematically illustrating a part of a display device according to one embodiment of the present invention, corresponding to a cross-section of the display device taken along the V-V' line of FIG. 4.

[0104] Referring to FIG. 5, the display device (10) may include a substrate (100) having a first region, a second region, and a third region between the first region and the second region. Here, the first to third regions of the substrate (100) correspond to the first to third display regions (DA1, DA2, DA3) of the display device (10), respectively. The substrate (100) may include glass or a polymer resin. For example, the substrate (100) may include a polymer resin such as polyethersulfone (PES), polyacrylate, polyetherimide (PEI), polyethylene naphthalate (PEN), polyethylene terephthalate (PET), polyphenylene sulfide (PPS), polyarylate, polyimide (PI), polycarbonate (PC), and cellulose acetate propionate (CAP). When the substrate (100) includes a polymer resin, the substrate (100) may have flexible or bendable properties.

[0105] The substrate (100) may have a single layer or a multilayer structure of the above material, and in the case of a multilayer structure, may further include an inorganic layer. For example, the substrate (100) may include a first base layer (101), a first barrier layer (102), a second base layer (103), and a second barrier layer (104) that are sequentially stacked. The first base layer (101) and the second base layer (103) may each include the polymer resin described above. The first barrier layer (102) and the second barrier layer (104) are barrier layers that prevent the penetration of external foreign substances, and are silicon nitride (SiN x ) or silicon oxide (SiO x It may be a single layer or a multilayer containing inorganic materials such as ).

[0106] A buffer layer (111) may be disposed on the substrate (100). The buffer layer (111) may serve to increase the smoothness of the upper surface of the substrate (110), and the buffer layer (111) may be silicon oxide (SiO₂). x Oxide films such as ), and / or silicon nitride (SiN x Nitride films such as ), or silicon oxynitride (SiO₂) x N y It can be provided as ).

[0107] A plurality of pixel circuits (PC) may be disposed on the buffer layer (111). The plurality of pixel circuits (PC) may include a plurality of first pixel circuits (PC1) located in a first display area (DA1), a plurality of second pixel circuits (PC2) located in a second display area (DA2), and a plurality of third pixel circuits (PC3) located in a third display area (DA3). Each of the first to third pixel circuits (PC1, PC2, PC3) may be electrically connected to the first to third light-emitting elements (200-1, 200-2, 200-3) described later. In one embodiment, each of the first to third pixel circuits (PC1, PC2, PC3) includes a plurality of thin-film transistors (T1, T2, T3, T4, T5, T6, T7), but in FIG. 5, only the first thin-film transistor (T1) and the third thin-film transistor (T3, T3') are shown for convenience of illustration.

[0108] For the convenience of explanation, the stacked structure of the display device (10) will first be explained with the first display area (DA1) as the center.

[0109] A silicon semiconductor layer containing a silicon semiconductor material may be disposed on the buffer layer (111). FIG. 5 illustrates a first semiconductor layer (A1) of a first thin-film transistor (T1) as a silicon semiconductor layer. The first semiconductor layer (A1) may include a first channel region (C1), a first source region (S1) and a first drain region (D1) on both sides of the first channel region (C1). For example, the source region and the drain region may be doped with impurities, and the impurities may include N-type impurities or P-type impurities. The channel region is a region that overlaps with the gate electrode to be described later, and may not be doped with impurities or may contain a very small amount of impurities. The source region and the drain region may correspond to the source electrode and the drain electrode of the thin-film transistor, respectively. The source region and the drain region may be interchanged depending on the properties of the thin-film transistor. For convenience, the terms source region and drain region will be used below instead of source electrode and drain electrode.

[0110] A first gate insulating layer (112) may be located on the first semiconductor layer (A1). The first gate insulating layer (112) may include an inorganic material including an oxide or a nitride. For example, the first gate insulating layer (112) may include at least one silicon oxide (SiO2), silicon nitride (SiNx), silicon oxynitride (SiOxNy), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), and zinc oxide (ZnO2).

[0111] A first gate electrode (G1) may be disposed on the first gate insulating layer (112). The first gate electrode (G1) may overlap at least partially with the first semiconductor layer (A1). For example, the first gate electrode (G1) may overlap with the first channel region (C1) of the first semiconductor layer (A1). The first gate electrode (G1) of the first thin-film transistor (T1) may include a low-resistance conductive material such as molybdenum (Mo), aluminum (Al), copper (Cu), and / or titanium (Ti), and may be a single layer or multilayer structure made of the aforementioned materials.

[0112] The first capacitor (Cst) may include a first electrode (CE1) and a second electrode (CE2). In one embodiment, the first capacitor (Cst) may be formed to overlap with the first thin-film transistor (T1). In this case, the first gate electrode (G1) may simultaneously perform the function of the first electrode (CE1) as well as the function of the gate electrode of the first thin-film transistor (T1). That is, the first gate electrode (G1) may be formed integrally with the first electrode (CE1). The first electrode (CE1) may be formed as an island-shaped electrode. In another embodiment, the first capacitor (Cst) may exist in a separate location without overlapping with the first thin-film transistor (T1).

[0113] A second gate insulating layer (113) may be disposed on the first gate electrode (G1). The second gate insulating layer (113) may include an inorganic material including an oxide or a nitride. For example, the second gate insulating layer (113) may be silicon oxide (SiO2) or silicon nitride (SiN2). x ), silicon oxynitride (SiO₂ x N y It may include at least one aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), and zinc oxide (ZnO2).

[0114] The second electrode (CE2) of the first capacitor (Cst) can be arranged to overlap with the first electrode (CE1). At this time, a second gate insulating layer (113) may be interposed between the first electrode (CE1) and the second electrode (CE2), and the second gate insulating layer (113) may serve as the dielectric layer of the first capacitor (Cst). The storage capacitance can be determined by the charge accumulated in the first capacitor (Cst) and the voltage between the two electrodes (CE1, CE2).

[0115] The second electrode (CE2) of the first capacitor (Cst) may include a metal, an alloy, a conductive metal oxide, a transparent conductive material, etc. The second electrode (CE2) may include, for example, at least one of aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and copper (Cu), and may be composed of a single layer or multiple layers.

[0116] A first interlayer insulating layer (114) may be disposed on the second electrode (CE2) of the first capacitor (Cst). The first interlayer insulating layer (114) may include an inorganic material including an oxide or a nitride. For example, the first interlayer insulating layer (114) may be silicon oxide (SiO2) or silicon nitride (SiN2).x ), silicon oxynitride (SiO₂ x N y It may include at least one aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), and zinc oxide (ZnO2).

[0117] An oxide-based semiconductor layer including an oxide semiconductor may be disposed on the first interlayer insulating layer (114). The oxide-based semiconductor layer may be a Zn oxide-based material and may include Zn oxide, In-Zn oxide, Ga-In-Zn oxide, etc. In some embodiments, the oxide-based semiconductor layer may include an IGZO (In-Ga-Zn-O), ITZO (In-Sn-Zn-O), or IGTZO (In-Ga-Sn-Zn-O) semiconductor containing metals such as indium (In), gallium (Ga), and tin (Sn) in ZnO. FIG. 5 illustrates a third semiconductor layer (A3) of a third thin-film transistor (T3) as an oxide semiconductor layer. The third semiconductor layer (A3) may include a third channel region (C3), a third source region (S3) on both sides of the third channel region (C3), and a third drain region (D3).

[0118] A third gate insulating layer (115) may be disposed on the third semiconductor layer (A3) of the third thin-film transistor (T3). The third gate insulating layer (115) may include an inorganic material including an oxide or a nitride. For example, the third gate insulating layer (115) may be silicon oxide (SiO2) or silicon nitride (SiN2). x ), silicon oxynitride (SiO₂ x N y It may include at least one aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), and zinc oxide (ZnO2).

[0119] A third gate electrode (G3) of a third thin-film transistor (T3) may be disposed on the third gate insulating layer (115). The third gate electrode (G3) may overlap with at least a portion of the third semiconductor layer (A3) of the third thin-film transistor (T3), for example, with the third channel region (C3) of the third semiconductor layer (A3). The third gate electrode (G3) may include a low-resistance conductive material such as molybdenum (Mo), aluminum (Al), copper (Cu), and / or titanium (Ti), and may be a single layer or multilayer structure made of the aforementioned materials.

[0120] A second interlayer insulating layer (116) may be disposed on the third gate electrode (G3) of the third thin-film transistor (T3). The second interlayer insulating layer (116) may cover the third thin-film transistor (T3) of the first pixel circuit (PC1) and the third pixel circuit (PC3). The second interlayer insulating layer (116) may include an inorganic material including an oxide or a nitride. For example, the second interlayer insulating layer (116) may be silicon oxide (SiO2) or silicon nitride (SiN2). x ), silicon oxynitride (SiO₂ x N y It may include at least one aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), and zinc oxide (ZnO2).

[0121] A first flattening layer (117) and a second flattening layer (118) may be disposed on the second interlayer insulation layer (116). The first flattening layer (117) and the second flattening layer (118) may include organic materials such as acrylic, BCB (Benzocyclobutene), polyimide, or HMDSO (Hexamethyldisiloxane). Alternatively, the first flattening layer (117) and the second flattening layer (118) may include inorganic materials. The first flattening layer (117) and the second flattening layer (118) serve as a protective film covering the pixel circuit (PC), and the upper surfaces of the first flattening layer (117) and the second flattening layer (118) are provided to be flattened. The first flattening layer (117) and the second flattening layer (118) may be provided as a single layer or multiple layers.

[0122] A plurality of pixel electrodes (210) may be disposed on the upper portion of the second planarization layer (118). The pixel electrode (210) may include a transparent conductive layer formed of a transparent conductive oxide such as ITO, In2O3, or IZO, and a reflective layer formed of a metal such as Al or Ag. For example, the pixel electrode (210) may have a three-layer structure of ITO / Ag / ITO.

[0123] A pixel defining film (120) is disposed on the pixel electrode (210), and the pixel defining film (120) can define a pixel (PX) by having an opening corresponding to each pixel (PX), that is, an opening (120OP) that exposes at least the central part of the pixel electrode (210). In addition, the pixel defining film (120) can prevent the occurrence of arcs, etc. between the edge of the pixel electrode (210) and the opposing electrode (230) by increasing the distance between them. The pixel defining film (120) can be formed from an organic material such as polyimide or HMDSO (hexamethyldisiloxane), for example.

[0124] An intermediate layer (220) may be disposed on the pixel defining film (120). The intermediate layer (220) may be disposed between the pixel electrode (210) and the counter electrode (230).

[0125] The intermediate layer (220) may include a light-emitting layer formed to correspond to the pixel electrode (210). The light-emitting layer may include an organic light-emitting material, such as a polymer or low-molecular-weight organic material, that emits light of a predetermined color. Alternatively, the light-emitting layer may include an inorganic light-emitting material or quantum dots.

[0126] As an optional embodiment, functional layers such as a hole transport layer (HTL), a hole injection layer (HIL), an electron transport layer (ETL), and an electron injection layer (EIL) may be further disposed below and above the light-emitting layer. For example, among the functional layers, the first functional layer may be a single-layer hole transport layer (HTL) and may be formed of polyethylene dihydroxythiophene (PEDOT) or polyaniline (PANI). Alternatively, the first functional layer may include a hole injection layer (HIL) and a hole transport layer (HTL). Among the functional layers, the second functional layer (223) may include an electron transport layer (ETL) and / or an electron injection layer (EIL).

[0127] Although FIG. 5 illustrates, as an example, that an intermediate layer (220) is formed corresponding to one pixel electrode (210), the present invention is not limited thereto. As another example, various variations are possible, such as the intermediate layer (220) including a layer that is integral across a plurality of pixel electrodes (210).

[0128] The counter electrode (230) is placed on the intermediate layer (220) and may be positioned to cover the display area (DA). That is, the counter electrode (230) may be formed integrally to cover a plurality of pixel electrodes (210). The counter electrode (230) may extend from the display area (DA, see FIG. 1) to the surrounding area (PA, see FIG. 1). The counter electrode (230) may be made of a conductive material with a low work function. For example, the counter electrode (230) may include a (semi)transparent layer comprising silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), or an alloy thereof. Alternatively, the counter electrode (230) may further include a layer such as ITO, IZO, ZnO, or In2O3 on a (semi)transparent layer containing the aforementioned material.

[0129] The stacked structure of the pixel electrode (210), the intermediate layer (220), and the counter electrode (230) can form an organic light-emitting diode (OLED) as a light-emitting element (200). The light-emitting region of the light-emitting element (200) can be defined as a pixel (PX). Since the opening (120OP) of the pixel defining film (120) defines the size and / or width of the light-emitting region, the size and / or width of the pixel (PX) may depend on the size and / or width of the corresponding opening (120OP) of the pixel defining film (120).

[0130] A display device (10) may be provided with a plurality of light-emitting elements (200). The plurality of light-emitting elements (200) may include a plurality of first light-emitting elements (200-1) disposed in a first display area (DA1). Each first light-emitting element (200-1) may be electrically connected to a first pixel circuit (PC1) located in the first display area (DA1) through a contact metal (CM) located on the first flattening layer (117). The light-emitting area of ​​the first light-emitting element (200-1) may be defined as a first pixel (PX1).

[0131] Next, the configuration of the display device (10) located in the second display area (DA2) will be described.

[0132] A second pixel circuit (PC2) may be disposed on the buffer layer (111). Since the first thin-film transistor (T1) of the second pixel circuit (PC2) has the same structure as the first thin-film transistor (T1) of the first pixel circuit (PC1) described above, the description thereof will be omitted below for the sake of brevity.

[0133] As described above, the third thin-film transistor (T3') of the second pixel circuit (PC2) may be provided as a silicon-based thin-film transistor. Accordingly, the third thin-film transistor (T3') may include a third semiconductor layer (A3') as a silicon semiconductor layer disposed on the buffer layer (111). The third semiconductor layer (A3') may include a channel region (C3'), source regions (S3') and drain regions (D3') on both sides of the channel region (C3').

[0134] The third thin-film transistor (T3') of the second pixel circuit (PC2) may include a third gate electrode (G3') that overlaps at least partially with the third semiconductor layer (A3'). For example, the third gate electrode (G3) may overlap with the channel region (C3') of the third semiconductor layer (A3'). The third gate electrode (G3') may be insulated from the third semiconductor layer (A3') by the first gate insulating layer (112). The third gate electrode (G3') may include a low-resistance conductive material such as molybdenum (Mo), aluminum (Al), copper (Cu), and / or titanium (Ti), and may be a single layer or multilayer structure made of the aforementioned materials.

[0135] A second gate insulating layer (113), a first interlayer insulating layer (114), a third gate insulating layer (115), a second interlayer insulating layer (116), a first flattening layer (117), and a second flattening layer (118) may be sequentially arranged on the third gate electrode (G3') of the third thin-film transistor (T3') of the second pixel circuit (PC2).

[0136] In the second display area (DA2), a plurality of second light-emitting elements (200-2) among a plurality of light-emitting elements (200) may be located. The second light-emitting elements (200-2) may be electrically connected to the second pixel circuit (PC2) through a contact metal (CM) located on the first flattening layer (117). The light-emitting area of ​​the second light-emitting elements (200-2) may be defined as the second pixel (PX2).

[0137] Meanwhile, as described above, an electronic component (20) may be disposed in the second display area (DA2), and a transmission area (TA) through which light emitted from or directed toward the electronic component (20) is transmitted may be disposed. The insulating layers on the substrate (100) may each include a hole formed in the transmission area (TA). For example, the first gate insulating layer (112), the second gate insulating layer (113), the first interlayer insulating layer (114), the third gate insulating layer (115), the second interlayer insulating layer (116), the first flattening layer (117), the second flattening layer (118), and the pixel defining film (120) may each include first to eighth holes (H1, H2, H3, H4, H5, H6, H7, H8) located in the transmission area (TA) and overlapping each other. Through this, the light transmittance in the transmission region (TA) can be improved.

[0138] A first lower metal layer (BML1) may be located in the second display area (DA2). The first lower metal layer (BML1) may be interposed between the substrate (100) and the second pixel circuit (PC2), for example, between the substrate (100) and the first semiconductor layer (A1) of the first thin-film transistor (T1) of the second pixel circuit (PC2). The first lower metal layer (BML1) may include a light-blocking material, and the light-blocking material may include, for example, a metallic material such as chromium (Cr) or molybdenum (Mo), black ink and / or dye.

[0139] In one embodiment, the first lower metal layer (BML1) may be arranged to overlap entirely with the second pixel circuit (PC2). In another embodiment, the first lower metal layer (BML1) may be arranged to partially overlap with the second pixel circuit (PC2), but at least overlap with the first semiconductor layer (A1) of the first thin-film transistor (T1) of the second pixel circuit (PC2). Although not illustrated, the first lower metal layer (BML1) may be electrically connected to the second pixel circuit (PC2) to receive a constant voltage. This may help the first thin-film transistor (T1) of the second pixel circuit (PC2) to have stable electrical characteristics.

[0140] The first lower metal layer (BML1) can prevent light emitted from or directed toward the electronic component (20) from diffracting through the components of the second pixel circuit (PC2) or the signal lines connected to the second pixel circuit (PC2). This minimizes the performance degradation of the electronic component (20). Additionally, the first lower metal layer (BML1) can prevent light emitted from or reflected from the electronic component (20) from being incident on the second pixel circuit (PC2). This minimizes the performance degradation of the thin-film transistor of the second pixel circuit (PC2) caused by the light.

[0141] However, the first lower metal layer (BML1) may not overlap with the transmission area (TA) of the second display area (DA2) so as not to cause a decrease in light transmittance in the transmission area (TA).

[0142] Next, the configuration of the display device (10) located in the third display area (DA3) will be described.

[0143] In the third display area (DA3), a plurality of third light-emitting elements (200-3) among a plurality of light-emitting elements (200) are arranged, and a plurality of third pixel circuits (PC3) electrically connected to each of the plurality of third light-emitting elements (200-3) may be arranged.

[0144] The third pixel circuit (PC3) can be placed on the buffer layer (111). The third pixel circuit (PC3) includes a plurality of thin-film transistors (T1, T2, T3, T4, T5, T6, T7) as described above, but for convenience of illustration, only the first thin-film transistor (T1) and the third thin-film transistor (T3) are shown.

[0145] The first and third thin-film transistors (T1, T3) of the third pixel circuit (PC3) may have the same structure as the first and third thin-film transistors (T1, T3) of the first pixel circuit (PC1) described above. Accordingly, the same reference numeral has been assigned to the first thin-film transistor (T1) of the first pixel circuit (PC1) and the third pixel circuit (PC3), respectively, and likewise, the same reference numeral has been assigned to the third thin-film transistor (T3) of the first pixel circuit (PC1) and the third pixel circuit (PC3), respectively. Hereinafter, a detailed description of the first and third thin-film transistors (T1, T3) of the third pixel circuit (PC3) is omitted for the sake of brevity, and will be mentioned again only when necessary.

[0146] In one embodiment, the third pixel circuit (PC3) may include a first thin-film transistor (T1) having a first semiconductor layer (A1) and a first gate electrode (G1) that overlaps at least a portion with the first semiconductor layer (A1), a third semiconductor layer (A3) having a material different from the first semiconductor layer (A1), and a third thin-film transistor (T3) having a third gate electrode (G3) that overlaps at least a portion with the third semiconductor layer (A3). For example, the first semiconductor layer (A1) of the first thin-film transistor (T1) of the third pixel circuit (PC3) may include a silicon semiconductor material, and the third semiconductor layer (A3) of the third thin-film transistor (T3) may include an oxide semiconductor material.

[0147] In one embodiment, the third pixel circuit (PC3) may include a first capacitor (Cst) that is arranged to overlap with the first thin-film transistor (T1). For example, the first gate electrode (G1) of the first thin-film transistor (T1) may function as the first electrode (CE1) of the first capacitor (Cst), and the second electrode (CE2) of the first capacitor (Cst) may overlap with at least a portion of the first gate electrode (G1).

[0148] According to one embodiment of the present invention, the third pixel circuit (PC3) may include a lower shielding layer (BSL) located below the third semiconductor layer (A3) of the third thin-film transistor (T3) of the third pixel circuit (PC3) and arranged to overlap at least a portion of the third semiconductor layer (A3) on a plane. For example, the lower shielding layer (BSL) may overlap entirely with the third semiconductor layer (A3) or at least with the third channel region (C3) of the third semiconductor layer (A3). As an example, the lower shielding layer (BSL) may include the same material as the second electrode (CE2) of the first capacitor (Cst).

[0149] Since the third pixel circuit (PC3) of the third display area (DA3) is adjacent to the transmission area (TA) of the second display area (DA2), light incident on the electronic component (20) through the transmission area (TA) can be reflected from the electronic component (20) and incident on the third pixel circuit (PC3). Oxide semiconductors may be susceptible to light, and therefore, such light can adversely affect the third semiconductor layer (A3) of the third thin-film transistor (T3) of the third pixel circuit (PC3) containing oxide semiconductor material, and may cause problems that degrade the device characteristics and reliability of the third thin-film transistor (T3). However, the lower shielding layer (BSL) according to one embodiment of the present invention can prevent such problems by blocking the light incident on the third thin-film transistor (T3). Therefore, the deterioration of display quality can be prevented.

[0150] Although the above description focused on the third thin-film transistor (T3), this is purely exemplary and can be applied in the same way to other thin-film transistors including oxide-based semiconductors, such as the fourth thin-film transistor (T4, see FIG. 3) of the third pixel circuit (PC3). That is, the lower shielding layer (BSL) can be positioned so as to overlap at least partially with the fourth thin-film transistor (T4) at the bottom of the fourth thin-film transistor (T4).

[0151] According to one embodiment of the present invention, a wiring layer (WL) may be provided that is disposed on the same layer and includes the same material as the third gate electrode (G3) of the third thin-film transistor (T3) of the third pixel circuit (PC3). The wiring layer (WL) may be one of the signal lines that transmit an electrical signal to the third pixel circuit (PC3). The wiring layer (WL) may be electrically connected to the lower shielding layer (BSL) through a first contact hole (CNT1) located in the third display area (DA3). The first contact hole (CNT1) may be formed in insulating layers interposed between the wiring layer (WL) and the lower shielding layer (BSL), for example, as shown in FIG. 5, it may be formed in the third gate insulating layer (115) and the first interlayer insulating layer (114). The lower shielding layer (BSL) can receive a predetermined electrical signal from the wiring layer (WL) and may not be electrically floating. This helps the third semiconductor layer (A3) of the third thin-film transistor (T3) to have stable electrical characteristics.

[0152] According to one embodiment of the present invention, a second lower metal layer (BML2) may be disposed below the third pixel circuit (PC3). For example, the second lower metal layer (BML2) may be interposed between the substrate (100) and the third pixel circuit (PC3), or, for example, between the substrate (100) and the first semiconductor layer (A1) of the first thin-film transistor (T1) of the third pixel circuit (PC3). The second lower metal layer (BML2) may include the same material as the first lower metal layer (BML1) of the second display area (DA2).

[0153] For example, the second lower metal layer (BML2) may overlap entirely with the third pixel circuit (PC3), or for another example, partially. In this case, the second lower metal layer (BML2) may overlap at least with the first semiconductor layer (A1) of the first thin-film transistor (T1) of the third pixel circuit (PC3).

[0154] In one embodiment, the second lower metal layer (BML2) is located below the first semiconductor layer (A1) of the first thin-film transistor (T1) of the third pixel circuit (PC3), and may overlap with the first semiconductor layer (A1) on a plane. The second lower metal layer (BML2) can prevent light incident on the electronic component (20) through the transmission region (TA) from being reflected from the electronic component (20) and incident on the first semiconductor layer (A1) of the first thin-film transistor (T1) of the third pixel circuit (PC3). By doing so, the degradation of the device characteristics and performance of the first thin-film transistor (T1) of the third pixel circuit (PC3) can be prevented. Therefore, the degradation of display quality can be prevented.

[0155] Although not shown, the second lower metal layer (BML2) is electrically connected to the third pixel circuit (PC3) and can receive a constant voltage. This helps the first thin-film transistor (T1) of the third pixel circuit (PC3) to have stable electrical characteristics.

[0156] According to one embodiment of the present invention, a light blocking member (500) comprising at least two conductive layers may be located in the third display area (DA3). In one embodiment, the light blocking member (500) may be located closer to the second display area (DA2) than to the third pixel circuit (PC3) on a plane. That is, the light blocking member (500) may be located between the area where the third pixel circuit (PC3) is placed and the transmission area (TA) of the second display area (DA2) on a plane.

[0157] In one embodiment, the light blocking portion (500) may include a first conductive layer (510) and a second conductive layer (520) located on the first conductive layer (510). That is, the first conductive layer (510) and the second conductive layer (520) may be located on different layers. For example, the first conductive layer (510) may include the same material as the first gate electrode (G1) of the first thin-film transistor (T1), the third gate electrode (G3) of the third thin-film transistor (T3), or the second electrode (CE2) of the first capacitor (Cst), and may be placed on the same layer. As an example, FIG. 5 illustrates that the first conductive layer (510) is placed on the same layer as the first gate electrode (G1).

[0158] The second conductive layer (520) may be located on the second interlayer insulating layer (116). For example, the second conductive layer (520) may be located between the second interlayer insulating layer (116) and the first flattening layer (117), and for another example, it may be located between the first flattening layer (117) and the second flattening layer (118). The second conductive layer (520) may include aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), nickel (Ni), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and / or copper (Cu), and may be a single layer or multilayer structure including the aforementioned materials.

[0159] According to one embodiment, the first conductive layer (510) and the second conductive layer (520) of the light blocking unit (500) can be electrically connected to each other through a second contact hole (CNT2) located in the third display area (DA3). For example, as previously described with reference to FIG. 4, when a plurality of light blocking units (500) are provided and arranged along the edge of the second display area (DA2), the second contact hole (CNT2) may be provided for each light blocking unit (500) and arranged along the edge of the second display area (DA2) on a plane. For another example, when the light blocking unit (500) is formed integrally and extends along the edge of the second display area (DA2), the second contact hole (CNT2) may also extend along the edge of the second display area (DA2) on a plane.

[0160] External light incident on the display device (10) may be incident obliquely in a direction having a predetermined angle with respect to a direction perpendicular to one surface of the substrate (100). Such light may be incident laterally from the transmission area (TA) of the second display area (DA2) toward the third pixel circuit (PC3) of the third display area (DA3). Here, 'lateral direction' may mean a direction having a component of the x-direction or y-direction in FIG. 5, and may refer to a direction toward the third pixel circuit (PC3) from the transmission area (TA) on a plane. Additionally, some of the light passing through the transmission area (TA) may be incident from the transmission area (TA) toward the third pixel circuit (PC3) along the lateral direction as a result of being reflected by various components located in the second display area (DA2). The aforementioned lower shielding layer (BSL) and the second lower metal layer (BML2) can block light incident from the bottom of the third pixel circuit (PC3), but it is difficult to block light incident on the third pixel circuit (PC3) along the lateral direction.

[0161] However, according to one embodiment of the present invention, the light blocking portion (500) is provided with a first conductive layer (510) and a second conductive layer (520) disposed on different layers and a contact structure connecting them, thereby functioning as a wall that blocks light incident on the third pixel circuit (PC3) along the lateral direction. Accordingly, the problem of the device characteristics and reliability of the thin-film transistors of the third pixel circuit (PC3), specifically oxide-based thin-film transistors, being degraded by light incident on the lateral direction from the transmission area (TA) toward the third pixel circuit (PC3) can be prevented. Accordingly, the deterioration of display quality can be prevented.

[0162] As an optional embodiment, the light blocking member (500) may further include a third conductive layer (530) disposed on the same layer and containing the same material as the first and second lower metal layers (BML1, BML2). The third conductive layer (530) of the light blocking member (500) may be electrically connected to the first conductive layer (510) through a third contact hole (CNT3). In this case as well, the third contact hole (CNT3) may also be arranged and / or extended along the edge of the second display area (DA2) in a plane. By additionally providing the third conductive layer (530), the range of light blocking member (500) that blocks light traveling in a lateral direction may be increased.

[0163] FIG. 6 is a cross-sectional view schematically illustrating a part of a display device according to another embodiment of the present invention, and FIG. 7 is a cross-sectional view schematically illustrating a part of a display device according to yet another embodiment of the present invention. Descriptions of components identical to or corresponding to the components described above with reference to FIG. 5 are omitted, and the following description focuses on the differences.

[0164] First, referring to FIG. 6, the third thin-film transistor (T3) of the first pixel circuit (PC1) and the third pixel circuit (PC3) may have a double gate structure. Specifically, the third gate electrode (G3) of the third thin-film transistor (T3) may have a lower gate electrode located below the third semiconductor layer (A3) and overlapping with at least a portion of the third semiconductor layer (A3), and an upper gate electrode located above the third semiconductor layer (A3) and overlapping with the lower gate electrode.

[0165] According to another embodiment of the present invention, the lower shielding layer (BSL) may comprise the same material as the first gate electrode (G1) of the first thin-film transistor (T1) and may be disposed on the same layer. The lower shielding layer (BSL) may be electrically connected to the wiring layer (WL) located above it through a first contact hole (CNT1). In this case, the first contact hole (CNT1) may be formed in the third gate insulating layer (115), the first interlayer insulating layer (114), and the second gate insulating layer (113).

[0166] Referring to FIG. 7, the lower shielding layer (BSL) may contain the same material as the first semiconductor layer (A1) of the first thin-film transistor (T1) and may be arranged on the same layer. That is, the lower shielding layer (BSL) may contain a silicon semiconductor material. In this case, the lower shielding layer (BSL) may also be electrically connected to the wiring layer (WL) located above it through the first contact hole (CNT1), and the first contact hole (CNT1) may be formed in the third gate insulating layer (115), the first interlayer insulating layer (114), the second gate insulating layer (113), and the first gate insulating layer (112). As such, the location where the lower shielding layer (BSL) is formed in the stacked structure of the display device (10) can be designed to be varied in many ways according to the structure of the third pixel circuit (PC3).

[0167] FIG. 8 is a schematic layout diagram illustrating excerpts of some configurations of a display device according to an embodiment of the present invention. FIG. 8 illustrates some configurations of a pair of third pixel circuits (PC3) arranged in the same row of adjacent columns. The third pixel circuit (PC3-L) arranged on the left and the third pixel circuit (PC3-R) arranged on the right shown in FIG. 8 have a left-right symmetrical structure.

[0168] Referring to FIG. 8, the first to seventh thin-film transistors (T1, T2, T3, T4, T5, T6, T7), the first scan line (SL1), the second scan line (SL2), the third scan line (SL3), the fourth scan line (SL4), and the light emission control line (EL) are shown in the configuration of the third pixel circuit (PC3).

[0169] The second scan line (SL2) shown in FIG. 8 may be the first scan line (SL1) of the next row. That is, the first scan line (SL1) shown in FIG. 8 may be the second scan line (SL2) of the previous row. FIG. 8 shows together a seventh thin-film transistor (T7) connected to the pixel circuit of the previous row and placed in the circuit area of ​​the current row, and a seventh thin-film transistor (T7) connected to the pixel circuit of the current row and placed in the circuit area of ​​the next row. For convenience of illustration and explanation, the seventh thin-film transistor (T7) placed in the circuit area of ​​the current row will be described as an example below.

[0170] The semiconductor layers (A1, A2, A5, A6, A7) of the first thin-film transistor (T1), the second thin-film transistor (T2), the fifth thin-film transistor (T5), the sixth thin-film transistor (T6), and the seventh thin-film transistor (T7) are arranged in the same layer and can be formed of polycrystalline silicon. The semiconductor layers (A1, A2, A5, A6, A7) are connected to each other and can be bent into various shapes.

[0171] The first thin-film transistor (T1) includes a first semiconductor layer (A1) and a first gate electrode (G1). The first semiconductor layer (A1) includes a first channel region (C1), a first source region (S1) and a first drain region (D1) on both sides of the first channel region (C1). The first semiconductor layer has a curved shape, so that the first channel region (C1) can be formed longer than other channel regions (C2 to C7). For example, by having the first semiconductor layer folded multiple times, such as 'S', 'M', 'W', etc., a long channel length can be formed within a narrow space. Since the first channel region (C1) is formed long, the driving range of the gate voltage applied to the first gate electrode (G1) is widened, allowing for more precise control of the gradation of light emitted from the organic light-emitting diode (OLED) and improving display quality. The first gate electrode (G1) can be provided in an isolated form so as to overlap with the first channel region (C1).

[0172] The second thin-film transistor (T2) may include a second semiconductor layer (A2) and a second gate electrode (G2). The second semiconductor layer (A2) may include a second channel region (C2), a second source region (S2) and a second drain region (D2) on both sides of the second channel region (C2). The second source region (S2) is electrically connected to a data line (DL), and the second drain region (D2) may be connected to a first source region (S1). The second gate electrode (G2) may be provided as part of a first scan line (SL1).

[0173] The fifth thin-film transistor (T5) may include a fifth semiconductor layer (A5) and a fifth gate electrode (G5). The fifth semiconductor layer (A5) may include a fifth channel region (C5), a fifth source region (S5) and a fifth drain region (D5) on both sides of the fifth channel region (C5). The fifth source region (S5) is electrically connected to a power supply voltage line (not shown), and the fifth drain region (D5) may be connected to a first source region (S1). The fifth gate electrode (G5) may be provided as part of a light emission control line (135).

[0174] The sixth thin-film transistor (T6) may include a sixth semiconductor layer (A6) and a sixth gate electrode (G6). The sixth semiconductor layer (A6) may include a sixth channel region (C6), a sixth source region (S6) and a sixth drain region (D6) on both sides of the sixth channel region (C6). The sixth source region (S6) is connected to the first drain region (D1), and the sixth drain region (D6) may be electrically connected to the pixel electrode (210, see FIG. 5) of the organic light-emitting diode (OLED). The sixth gate electrode (G6) may be provided as part of the light-emitting control line (EL).

[0175] The seventh thin-film transistor (T7) may include a seventh semiconductor layer (A7) and a seventh gate electrode (G7). The seventh semiconductor layer (A7) may include a seventh channel region (C7), a seventh source region (S7) and a seventh drain region (D7) on both sides of the seventh channel region (C7). The seventh source region (S7) may be electrically connected to a second initialization voltage line (not shown), and the seventh drain region (D7) may be connected to a sixth drain region (D6). The seventh gate electrode (G7) may be provided as part of a second scan line (SL2).

[0176] The semiconductor layers (A3, A4) of the third thin-film transistor (T3) and the fourth thin-film transistor (T4) are placed on the same layer and can be formed of oxide semiconductors.

[0177] The third thin-film transistor (T3) includes a third semiconductor layer (A3) and a third gate electrode (G3). The third semiconductor layer (A3) may include a third channel region (C3), and a third source region (S3) and a third drain region (D3) on both sides of the third channel region (C3). The third source region (S3) may be bridge-connected to the first gate electrode (G1) through a node connection line (not shown). Additionally, the third source region (S3) may be connected to a fourth drain region (D4) disposed in the same layer. The third drain region (D3) may be electrically connected to the first semiconductor layer (A1) of the first thin-film transistor (T1) and the sixth semiconductor layer (A6) of the sixth thin-film transistor (T6). The third gate electrode (G3) may be provided as part of the fourth scan line (SL4).

[0178] The fourth thin-film transistor (T4) may include a fourth semiconductor layer (A4) and a fourth gate electrode (G4). The fourth semiconductor layer may include a fourth channel region (C4), a fourth source region (S4) and a fourth drain region (D4) on both sides of the fourth channel region (C4). The fourth source region (S4) may be electrically connected to a first initialization voltage line (not shown), and the fourth drain region (D4) may be bridge-connected to the first gate electrode (G1) through a node connection line (not shown). The fourth gate electrode (G4) may be provided as part of the third scan line (SL3).

[0179] As an optional embodiment, some of the wirings may be provided with two conductive layers disposed on different layers. For example, the third scan line (SL3) may include a lower scan line (143) and an upper scan line (163) disposed on different layers. The lower scan line (143) may be provided with the same material on the same layer as the second electrode (CE2) of the first capacitor (Cst). The lower scan line (143) may be disposed to overlap at least partially with the upper scan line (163). Since the lower scan line (143) and the upper scan line (163) correspond to a part of the third gate electrode (G3) of the third thin-film transistor (T3), the third thin-film transistor (T3) may have a dual-gate structure having control electrodes on the upper and lower parts of the third semiconductor layer (A3), respectively.

[0180] Additionally, the fourth scan line (SL4) may include a lower scan line (145) and an upper scan line (165) disposed on different layers. The lower scan line (145) may be provided with the same material on the same layer as the second electrode (CE2) of the first capacitor (Cst). The lower scan line (145) may be disposed to overlap at least partially with the upper scan line (165). Since the lower scan line (145) and the upper scan line (165) correspond to a part of the fourth gate electrode (G4) of the fourth thin-film transistor (T4), the fourth thin-film transistor (T4) may have a dual gate structure having control electrodes on the upper and lower parts of the fourth semiconductor layer (A4), respectively.

[0181] According to one embodiment of the present invention, a plurality of third light-emitting elements (200-3) can each overlap with an oxide-based thin-film transistor of a corresponding third pixel circuit (PC3). For example, a pixel electrode (210-3-L) of a third light-emitting element electrically connected to a third pixel circuit (PC3-L) positioned on the left can overlap with a third thin-film transistor (T3) of the third pixel circuit (PC3-L) in a plane. Additionally, a pixel electrode (210-3-R) of a third light-emitting element electrically connected to a third pixel circuit (PC3-R) positioned on the right can overlap with a fourth thin-film transistor (T4) of the third pixel circuit (PC3-R) in a plane.

[0182] Of course, this is exemplary, and the arrangement of the pixel electrodes (210-3-L, 210-3-R) can be varied in many ways. As another example, the pixel electrode (210-3-L) may overlap in a plane with the fourth thin-film transistor (T4) of the third pixel circuit (PC3-L) placed on the left, and the pixel electrode (210-3-R) may overlap in a plane with the third thin-film transistor (T3) of the third pixel circuit (PC3-R) placed on the right. As another example, the pixel electrode (210-3-L) may overlap with both the third thin-film transistor (T3) and the fourth thin-film transistor (T4) of the third pixel circuit (PC3-L) positioned on the left, and the pixel electrode (210-3-R) may overlap with both the third thin-film transistor (T3) and the fourth thin-film transistor (T4) of the third pixel circuit (PC3-R) positioned on the right.

[0183] As described above, since the oxide semiconductor of the oxide-based thin-film transistor may be vulnerable to external light, the pixel electrode (210) is positioned to overlap with the oxide semiconductor, thereby minimizing the possibility that external light incident from the top of the display device (10) will reach the oxide semiconductor. Through this, the degradation of the device characteristics and reliability of the oxide-based thin-film transistor, such as the third thin-film transistor (T3) and the fourth thin-film transistor (T4), can be prevented, and the degradation of the display quality can be prevented.

[0184] Although the present invention has primarily described display devices so far, it is not limited thereto. For example, a method for manufacturing such a display device is also considered to fall within the scope of the present invention.

[0185] The present invention has been described with reference to the embodiments illustrated in the drawings, but this is merely illustrative, and those skilled in the art will understand that various modifications and equivalent alternative embodiments are possible therefrom. Accordingly, the true technical scope of protection of the present invention should be determined by the technical spirit of the appended claims. Explanation of the symbols

[0186] 1: Electronic devices 10: Display device 20: Electronic Components 500: Light blocking section BSL: Lower Shielding Layer BML1,2: 1st and 2nd lower metal layers T1: First thin-film transistor T3: Third thin-film transistor T4: 4th thin-film transistor WL: Wiring layer

Claims

Claim 1 A first display area in which a plurality of first light-emitting elements are arranged; a second display area in which a plurality of second light-emitting elements are arranged and which includes a transmission area; a third display area in which a plurality of third light-emitting elements are arranged and which is located between the first display area and the second display area; and a plurality of pixel circuits arranged in the third display area and electrically connected to each of the plurality of third light-emitting elements, wherein each of the plurality of pixel circuits comprises: a first thin-film transistor having a first semiconductor layer and a first gate electrode that overlaps at least a portion with the first semiconductor layer; and a third thin-film transistor having a third semiconductor layer having a material different from the first semiconductor layer and a third gate electrode that overlaps at least a portion with the third semiconductor layer. A display device comprising: a lower shielding layer located below the third semiconductor layer and arranged to overlap with at least a portion of the third semiconductor layer on a plane; wherein the first semiconductor layer and the third semiconductor layer are arranged on different layers. Claim 2 A display device according to claim 1, wherein the first semiconductor layer of the first thin-film transistor comprises a silicon semiconductor material, and the third semiconductor layer of the third thin-film transistor comprises an oxide semiconductor material. Claim 3 A display device according to claim 1, further comprising a wiring layer having the same material as the third gate electrode of the third thin-film transistor, wherein the wiring layer is electrically connected to the lower shielding layer through a contact hole located in the third display area. Claim 4 A display device according to claim 1, wherein each of the plurality of pixel circuits further comprises a capacitor electrode that overlaps at least a portion with the first gate electrode of the first thin-film transistor, and the lower shielding layer comprises the same material as the capacitor electrode. Claim 5 A display device according to claim 1, wherein the lower shielding layer comprises the same material as the first gate electrode of the first thin-film transistor. Claim 6 A display device according to claim 1, wherein the lower shielding layer comprises the same material as the first semiconductor layer of the first thin-film transistor. Claim 7 A display device according to claim 1, further comprising a lower metal layer located below the first semiconductor layer of the first thin-film transistor and overlapping with the first semiconductor layer on a plane. Claim 8 A display device according to claim 1, further comprising a light-blocking member including at least two conductive layers positioned in the third display area and disposed on different layers. Claim 9 A display device according to claim 8, wherein the light blocking member is positioned on a plane so as to be closer to the second display area than to the plurality of pixel circuits. Claim 10 In claim 8, the light blocking member is a display device arranged to surround at least a portion of the second display area on a flat plane. Claim 11 A display device according to claim 8, wherein the at least two conductive layers of the light blocking portion comprise a first conductive layer having the same material as the first gate electrode or the third gate electrode, and a second conductive layer located on the first conductive layer and electrically connected to the first conductive layer. Claim 12 A display device according to claim 11, further comprising a lower metal layer located below the first semiconductor layer of the first thin-film transistor and overlapping with the first semiconductor layer in a planar manner; wherein the at least two conductive layers of the light-blocking portion further comprise a third conductive layer electrically connected to the first conductive layer and having the same material as the lower metal layer. Claim 13 A display device according to claim 1, wherein each of the plurality of third light-emitting elements comprises a pixel electrode, a counter electrode on the pixel electrode, and an intermediate layer between the pixel electrode and the counter electrode, wherein the pixel electrode overlaps with the third thin-film transistor of each of the plurality of pixel circuits on a plane. Claim 14 A substrate having a first region, a second region, and a third region between the first region and the second region; a first semiconductor layer disposed on the substrate and located in the third region, comprising a silicon semiconductor material; a first insulating layer covering the first semiconductor layer; a first gate electrode disposed on the first insulating layer and overlapping at least partially with the first semiconductor layer; a second insulating layer covering the first gate electrode; a third semiconductor layer disposed on the second insulating layer and located in the third region, comprising an oxide semiconductor material; a third insulating layer covering the third semiconductor layer; a third gate electrode disposed on the third insulating layer and overlapping at least partially with the third semiconductor layer; A display device comprising: a lower shielding layer interposed between the substrate and the third semiconductor layer and overlapping with at least a portion of the third semiconductor layer on a plane; wherein each of the first to third insulating layers includes a hole overlapping with a portion of the second region. Claim 15 A display device according to claim 14, further comprising a wiring layer disposed on the third insulating layer and containing the same material as the third gate electrode, wherein the lower shielding layer is electrically connected to the wiring layer through a contact hole located in the third region. Claim 16 A display device according to claim 14, wherein the lower shielding layer comprises the same material as the first gate electrode or the first semiconductor layer. Claim 17 A display device according to claim 14, further comprising a lower metal layer interposed between the substrate and the first semiconductor layer and overlapping with the first semiconductor layer on a plane. Claim 18 A display device according to claim 14, further comprising: a fourth insulating layer covering the third gate electrode; and a light blocking portion located in the third region; wherein the light blocking portion comprises a first conductive layer disposed on the same layer as the first gate electrode or the third gate electrode, and a second conductive layer disposed on the fourth insulating layer and partially electrically connected to the first conductive layer through a contact hole formed in the fourth insulating layer. Claim 19 A display device according to claim 18, wherein the light blocking portion is positioned on a plane such that it is closer to the second region than to the region in which the third semiconductor layer is disposed among the third regions. Claim 20 In paragraph 18, the light-blocking member is a display device arranged to surround at least a portion of the second region on a flat plane.

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