How to organize and utilize empty spaces

Abstract

The present invention can form a stable system by adjusting the density of empty spaces formed in the object to be detected to maintain the effective area of ​​the object to be detected equally, thereby minimizing the sensitivity distribution of the system caused by the difference in the area of ​​the object to be detected.

Description

Technology Field

[0001] The present invention relates to an apparatus and method for detecting a capacitance added to a capacitance detection area by driving a plurality of capacitances connected to a single detection signal line, and more specifically, to an apparatus for detecting an added capacitance by utilizing the difference between a first detection signal detected after applying a driving voltage to one side of a plurality of capacitances connected in parallel to a detection signal line, and a second detection signal detected after applying a driving voltage to one side of the plurality of capacitances after an object capacitance formed by an object is added.

[0002] More specifically, the invention relates to a device that reduces the size of the common electrode capacitance among multiple capacitances and maintains the areas of capacitance detection regions of different sizes to be equal to each other so that the size of the common electrode capacitance is formed to be constant. Background Technology

[0004] In the past, mechanical buttons were used to dial phone numbers on mobile phones, but recently, input devices have been shifting from mechanical to electronic, such as allowing phone numbers to be entered simply by lightly touching the display with a finger; capacitive type input devices are primarily used as an example of such electronic input devices.

[0005] A capacitive input device detects a change in the magnitude of capacitance that occurs when a finger or pen is adjacent to or contacts a "capacitance detection area" installed on the upper surface of a display device, and determines that the input at that location is valid, just as if a mechanical button were pressed.

[0006] FIG. 1 is an embodiment of the present invention regarding the modeling of a capacitive input device. Referring to FIG. 1, Cd is the "line-to-line capacitance," Cprs is the "internal parasitic capacitance" formed between the detection signal line and the semiconductor substrate or other signal lines inside the semiconductor IC, and Ccm is the "common electrode capacitance" formed between the capacitance detection area and the display device. One side of these three capacitances is connected in parallel to point P, which is indicated by the equivalent circuit of the detection signal line. In this case, Vprs, the voltage supplied to the other side of the "internal parasitic capacitance," is either a DC power source representing the potential of the semiconductor substrate or an AC potential resulting from noise in other coupled signal lines; Vcm, the voltage supplied to the other side of the "common electrode capacitance," is a pixel voltage representing a DC voltage of a predetermined magnitude; and Vd, the voltage supplied to the inter-line capacitance Cd, is a driving voltage whose magnitude changes from Vd1 to Vd2 or from Vd2 to Vd1.

[0007] If we define Vp as the voltage at which point P is stabilized by the voltage supplied to the three capacitances, define id as the current flowing through Cd by the voltage Vd supplied to the line capacitance (Cd), define iprs as the current flowing through Cprs by the voltage Vprs supplied to the internal parasitic capacitance (Cprs), and assume icm as the current flowing through Ccm by the voltage Vcm supplied to the common electrode capacitance (Ccm), then according to Kirchhoff's current law, id = iprs + icm.

[0008]

[0009] since,

[0010]

[0011] It is. If we rearrange this mathematical equation for Vp...

[0012]

[0013] am.

[0014] If the voltage Vd supplied to the line capacitance (Cd) in the above mathematical formula is replaced with Vd1, the voltage at point P when Vd1 is applied

[0015]

[0016] And, the voltage at point P when Vd2, which is a voltage greater than Vd1, is supplied to the line capacitance (Cd).

[0017]

[0018] Therefore, when voltages Vd1 and Vd2 of different magnitudes are applied to the line capacitance (Cd), the (Vp2-Vp1) detected at connection point P is equal to <Equation 1>.

[0019]

[0022] Figure 2 is hypothetical data for verifying mathematical formula 1. Referring to Figure 2, Vd1=0V and Vd2=5V, and the line capacitance (Cd) was set to increase from 13pF to 34pF. The internal parasitic capacitance (Cprs) was alternately used between 8 and 14pF, and the common electrode capacitance (Ccm) was alternately used between 1 and 2pF.

[0023] By substituting the data from Fig. 2 into <Equation 1> to calculate Vp2-Vp1, as shown in Fig. 2, Max=3.929V and Min=2.5V, so it can be seen that Max-Min=1.429V.

[0024] Since it is appropriate to use a 10-bit ADC with a detection range of 1.6 V to detect a voltage with a range of 1.429 V, assuming that the bias voltages of the ADC, ADC_top and ADC_btm, are 3 V and 1.4 V respectively, the resolution of the 10-bit ADC with a detection range of 1.6 V is 1.6 V / 1024 bit, which is 1.56 mV / bit.

[0025] Referring to the bottom data of Single Driving in Fig. 13 described below, when the magnitude of the object capacitance (Cobj) formed by the object is 0.2 pF, the difference between the first voltage and the second voltage detected at point P is 16 mV, which is about 10 codes with an ADC resolution of 1.56 mV / bit.

[0026] 10 codes is about 1% of the total resolution of the ADC, which is 1024 codes. Considering that it is generally difficult to distinguish a signal within 2 to 3% of the detection signal due to noise, there is a problem in that it is difficult to distinguish a real signal with a signal magnitude of about 1%. The problem to be solved

[0028] The present invention is proposed to solve the problems of the conventional technology described above, and provides a device that improves sensitivity by minimizing the signal detection range of a DAC by forming an empty space in the capacitance detection area to reduce the size of the common electrode capacitance and making the size of the common electrode capacitance between the capacitance detection areas equal.

[0029] In addition, the present invention provides a capacitance detection device and method that are useful for use as an input means for portable terminals or laptops sensitive to current consumption, by blocking noise entering the detection signal line by the shielding area of ​​the present invention to improve the SNR of the detected signal and reducing current consumption by lowering the driving voltage compared to existing embodiments. means of solving the problem

[0031] To achieve the above objectives, one embodiment of the present invention comprises: a capacitance detection area having an independent conductive region installed in a display device; a signal line connecting one input terminal of a differential amplifier located inside a semiconductor IC to the capacitance detection area; and a portion of the capacitance detection area is peeled away into an empty space, but the signal line connected to the peeled capacitance detection area is not peeled away, and a driving voltage is applied to a plurality of capacitors connected to the signal line to detect a capacitor added to the portion of the peeled capacitance detection area.

[0032] In addition, the density of the peeled voids is constant in the same capacitance detection area.

[0033] In addition, the difference in the empty space peeling ratio between the capacitance detection area having the peeled empty space and the capacitance detection area adjacent thereto is within 5%.

[0034] In addition, the peeled shape in the capacitance detection area is formed identically in the same capacitance detection area, and the peeled shape of the capacitance detection area adjacent to the peeled capacitance detection area is also identical.

[0035] In addition, the ratio of empty space peeled off in the capacitance detection area is within a maximum of 90%.

[0036] In addition, a DAC is connected to the other input terminal of the differential amplifier to which the above signal line is connected, and the differential amplifier outputs the difference between the DAC output voltage and the voltage formed on the above signal line, and detects the added capacitance by calculating the magnitude of the voltage output from the differential amplifier.

[0037] In addition, one of the plurality of capacitors connected to the signal line is a shielding capacitance, and the shielding capacitance is a capacitance formed between the signal line and a shielding region installed on the upper and lower layers of the semiconductor IC layer on which the signal line is patterned. Effects of the invention

[0039] According to one embodiment of the present invention, the size of the common electrode capacitance is reduced, thereby improving the resolution of the ADC.

[0040] In addition, according to one embodiment of the present invention, the effective area of ​​the capacitance detection region is configured equally so that the size of the common electrode capacitance is constant, thereby reducing the operating range of the DAC and improving sensitivity.

[0041] In addition, according to one embodiment of the present invention, noise entering the signal detection line can be blocked by the shielding area to improve the SNR.

[0042] In addition, according to one embodiment of the present invention, the current consumption of a semiconductor IC can be reduced to improve the usability of mobile phone terminals or laptops that are sensitive to current consumption.

[0043] The effects of the present invention are not limited to the effects described above, and should be understood to include all effects that can be inferred from the configuration of the invention described in the detailed description of the invention or the claims. Brief explanation of the drawing

[0045] FIG. 1 is an embodiment of the present invention regarding the modeling of a capacitive input device. Figure 2 is hypothetical data for verifying <Mathematical Equation 1>. FIG. 3 is a display device module equipped with a capacitance detection device according to an embodiment of the present invention. FIG. 4 is an embodiment of the present invention regarding the formation of a common electrode capacitance (Ccm). FIG. 5 is an embodiment of the present invention regarding a method for reducing the area of ​​a CDA facing a common electrode. FIG. 6 is an embodiment of the present invention in which a new driving layer is installed between the CDA and the common electrode. FIG. 7a is an embodiment of the present invention regarding the formation of a capacitor formed between one signal line and two adjacent signal lines. FIG. 7b is an embodiment of the present invention relating to the equivalent circuit of FIG. 7a. FIG. 7c is an embodiment of the present invention regarding a method for simultaneously selecting a driving signal line and a detection signal line. FIG. 7d is an embodiment of the present invention for reducing the number of switch control signal lines. FIG. 8 is an embodiment of the present invention regarding the configuration of a semiconductor IC. FIG. 9 is an example of a layer configuration of a semiconductor IC. FIG. 10 is an embodiment of the present invention in which a shielding region is added to a signal line inside a semiconductor IC. Fig. 11a is a cross-sectional view of Fig. 10 B-B'. FIG. 11b is another embodiment of the present invention regarding the implementation of a shielding region. FIG. 12a is an embodiment of the present invention that applies a driving voltage to a shielding capacitance (Cin_sd). FIG. 12b is an embodiment of the present invention for detecting voltage when an object capacitor is added. Fig. 13a is hypothetical data for verifying mathematical formula 3. Figure 13b is a graph of the results of <Equation 1> and <Equation 4> calculated based on the data of Figure 13a. FIG. 14 is an embodiment of the present invention regarding the application of a driving voltage. FIG. 15 is an embodiment of the present invention in which a driving voltage is applied in a driving unit. FIG. 16a is an embodiment of the present invention relating to a process of extracting a duplicated DAC code identical to a first detection signal. FIG. 16b is an embodiment of the present invention regarding the process of detecting the output signal V1 of a differential amplifier using a duplicated DAC. FIG. 16c is an embodiment of the present invention regarding a method of connecting multiple signal lines to a single differential amplifier. FIG. 16d is an embodiment of the present invention regarding a method of connecting Sample & Hold to a detection signal line. FIG. 17 is an embodiment of the present invention relating to a memory for storing a DAC. FIG. 18a is an embodiment of the present invention that reduces the number of detection signal lines output from a plurality of loaders. FIG. 18b is an embodiment of the apparatus of the present invention regarding signal flow. FIG. 19 is an embodiment of the present invention regarding a method for connecting a DAC and signal lines of a differential amplifier. FIG. 20 is an embodiment of the present invention that applies a reset voltage to a detection signal line. FIG. 21 is another embodiment of the present invention regarding a method for applying a reset voltage. FIG. 22 is an embodiment of the present invention relating to a flowchart illustrating a method for detecting capacitance. Specific details for implementing the invention

[0046] The terms used in this invention have been selected based on currently widely used general terms whenever possible, taking into account their functions within the invention; however, these terms may vary depending on the intent of those skilled in the art, case law, or the emergence of new technologies. Additionally, in specific cases, terms arbitrarily selected by the applicant have been used, and in such instances, their meanings will be described in detail in the relevant description of the invention. Therefore, the terms used in this invention should be defined not merely by their names, but based on their meanings and the overall context of the invention.

[0047] In addition, the size and thickness of each component shown in the drawings are depicted arbitrarily for convenience of explanation, and the present invention is not necessarily limited to what is illustrated.

[0048] In drawings, thicknesses or widths are exaggerated using relative enlargements or reductions to clearly represent various layers and regions. When a part such as a layer or region is described as being "above," "on," "upper side," or "upper surface" of another part, this includes not only cases where it is "directly above" another part, but also cases where there is another part in between. "Below," "lower side," or "lower surface" have the same meaning.

[0049] When a part of a specification is described as "including" a certain component, this means that, unless specifically stated otherwise, it does not exclude other components but may include additional components. Furthermore, terms such as "...part" or "module" as used in the specification refer to a unit that processes at least one function or operation, and this may be implemented in hardware or software, or as a combination of hardware and software.

[0051] Definition of Terms

[0052] In this specification, "capacitance" and "capacitor" are used interchangeably.

[0053] In addition, a finger or pen that forms a capacitance opposite to the CDA (100) is designated as an object (20) or Object.

[0054] Additionally, among the multiple CDA signal lines (200), the signal line that detects voltage (or detects a signal) based on the mathematical formula provided in the present invention is labeled as the Detect Signal Line, and the CDA (100) connected to the Detect Signal Line is labeled as the Detect CDA. The signal line adjacent to the Detect Signal Line, which forms a line-to-line capacitance with the Detect Signal Line and to which a driving voltage is applied, is labeled as the Driving Signal Line.

[0055] In addition, other signal lines required for operation inside the semiconductor IC (400), such as a Logic Signal Line, Oscillator Signal Line, Power Line, etc., which are not connected to the CDA (100) signal line (200), are indicated as "Different Signal Lines" to distinguish them from the CDA signal line (200) of the present invention.

[0056] Furthermore, the capacitance symbol is used in two senses: as a drawing symbol for capacitance and as a reference to the magnitude of capacitance. For example, Cprs refers to capacitance as a drawing symbol indicating the capacitance formed by the detection signal line and the semiconductor bulk (substrate) within a semiconductor IC, or it may refer to the magnitude of capacitance having a specific size. In cases where the meaning is confusing, it is distinguished and indicated as either "capacitance" or "magnitude of capacitance."

[0057] Additionally, the CDA (100) and the detection signal line (200) connected thereto are geometrically distinct but electrically identical. Therefore, the meaning of "extracting a detection signal from the detection signal line (200)" is the same as the meaning of "extracting a detection signal from the CDA (100) connected to the detection signal line (200)."

[0058] Additionally, in this specification, the output voltage of the differential amplifier that outputs the difference between the first detection signal and the second detection signal is denoted as "V1".

[0059] Additionally, a DAC is a device that outputs an analog voltage in response to a given input code. In this specification, the analog voltage output for a "DAC code" is referred to as "DAC voltage" or "DAC output." When only a DAC is used, it may be a DAC device that includes both a DAC code and a DAC voltage, or it may refer to only one of the two: a DAC code or a DAC voltage.

[0060] In addition, the distance standard, such as long distance / short distance, is based on the semiconductor IC (400), and long distance means being far from the semiconductor IC and short distance means being close to the semiconductor IC (400).

[0061] In addition, a single column formed by a set of CDAs was called CDA Column, and was indicated as Column where it was clear from the context.

[0062] Additionally, multiple CDA columns combine to form a column group. Where the context makes it clear, it is indicated as a group.

[0064] The following description, with reference to the attached drawings, explains in detail the embodiments of the present invention so that those skilled in the art can easily implement them. However, the present invention may be embodied in various different forms and is not limited to the embodiments described herein. Furthermore, in order to clearly explain the present invention in the drawings, parts unrelated to the explanation have been omitted, and similar parts throughout the specification have been denoted by similar reference numerals.

[0065] FIG. 3 is a display device module with a capacitance detection device installed according to an embodiment of the present invention. The capacitance detection area (100, Capacitor Detect Area, hereinafter CDA) of the capacitance detection device is made of a conductor and is installed inside the display device (10) or on the upper surface of the display device (10) and has an independent area, and is connected to the signal detection unit (410) of the semiconductor IC (400) by a CDA signal line (200) connected to one side.

[0066] The CDA (100) installed on the upper surface of the display device is covered with tempered glass, plastic, or film so as to be protected from objects (20) or external foreign substances. The CDA (100) is a geometric shape such as a circle, square, or triangle having a predetermined area, and is mostly composed of identical or similar geometric shapes. When an object such as a person's finger or a pen appears on the upper surface of the CDA (100) and faces it, object capacitance (Cobj) is formed according to the mutual clearance distance and the facing area.

[0067] Meanwhile, a CDA signal line (200) connected to one side of the CDA (100) electrically connects the CDA (100) to a semiconductor IC (400) located outside the display device (10), and the CDA signal line (200) is connected to the semiconductor IC (400) through a connecting member (300, Material for connection).

[0069] The display device (10) is made of an LCD or an OLED. The LCD is of the VA (Vatical Alignment) series or IPS (In Plane Switching) series, and all a-Si, LTPS, and Oxide type TFTs are used. The LCD is formed by bonding a TFT glass in which pixels of the display device are formed and a Color Filter Glass. In the case of a VA series LCD, a common voltage (Vcom) is supplied to a common electrode layer formed on the upper Color Filter Glass, and in the case of an IPS series LCD, a common voltage is applied to a common electrode layer formed on the lower TFT Glass.

[0070] When the display device (10) is an OLED (Organic Light Emitting Diode), a cathode is located on the upper layer, and the OLED is encapsulated by an encapsulator made of a thin film of glass or polyimide. The display device (10) of this specification is not limited to LCD or OLED. Although most examples using LCD have been given, the upper surface of the LCD is used with the same meaning as the upper surface of the OLED, and the elements of the present invention embedded in the display device are meant to be manufactured on an LCD TFT substrate or an OLED substrate.

[0071] The object capacitance (Cobj) is formed by the distance "d" between the capacitance detection area (CDA, 100) and the object (20) and the opposing area "s", and the size (Capacitance) of the formed object capacitance (Cobj) is ε is the permittivity of the material existing between CDA (100) and the object (20), and a composite permittivity is applied by a protective layer (7) such as glass or film and (if the object is floating in the air) air, etc.

[0072] The position of CDA (100) within the display device is as follows.

[0073] 1) In the case of an LCD 1: It is formed on the upper side of the Color Filter Glass, that is, on the Color Filter Glass where the Color Filter Glass and the polarizing plate are bonded, or on the lower or upper side of the polarizing plate, or installed on the lower side of the protective layer (7).

[0074] 2) In the case of LCD 2: It is formed at the common electrode location of the TFT substrate and performs two roles: common electrode and CDA (100).

[0075] 3) In the case of an LCD, 3: it is formed on the bottom layer of the TFT substrate, and after the formation of the CDA and the application of passivation, the process of the Gate Metal or Source Metal begins. The devices connected to the CDA signal line (200) are formed as switching devices manufactured in the LCD process and are embedded in the TFT substrate or located inside the semiconductor IC (400).

[0076] 4) In the case of an OLED, 1: Passivation is applied to the upper surface of the cathode and then formed on the upper surface of the passivation. The components of the device, such as a switch group connected to the CDA signal line (200), a loader (450), or a decoder (436), are formed during the manufacturing process of the OLED and are embedded in the OLED substrate or located inside the semiconductor IC (400).

[0077] 5) In the case of OLED 3: It is formed on the upper surface of a PI (Polyimide) series thin film, which is the encapsulation substrate of the OLED, or on the upper or lower surface of the encapsulation glass. The components of this device connected to the CDA signal line are located inside the semiconductor IC.

[0079] The set of CDA (100) in Fig. 3 consists of 3 rows and 4 columns, and area A1 in Fig. 3 has the coordinates of Row 2 and Column 1, and the location is indicated as R2C1.

[0080] The CAD (100) set of FIG. 3 is shown with 3 rows and 4 columns for convenience, but in reality, depending on the size of the display device (10), it can be used in various forms such as 15 (row) x 20 (column), 20 x 25, or 25 x 20.

[0081] In this specification, the direction in which the number of signal lines increases is defined as a column. In FIG. 3, since the number of signal lines increases from 1 to 3 in the direction from the top to the bottom, the up and down directions can be defined as columns. Additionally, the direction orthogonal to the column direction is defined as a row. In FIG. 3, one column consists of CDAs (100) corresponding to three rows, and the CDA of the top row (R1C1) is called the 1st CDA, the CDA of the second row (R2C1) is called the 2nd CDA or the CDA of the second row, and the 3rd or 4th CDA, etc. are consecutively followed.

[0083] Since the CDA (100) formed on the LCD or OLED faces the common electrode layer (Vcom Layer) of the LCD or the cathode layer of the OLED at a certain distance and a predetermined area, between the CDA (100) and the display device A common electrode capacitance having the size (Capacitance) is formed.

[0084] FIG. 4 is an embodiment of the present invention regarding the formation of a common electrode capacitance (Ccm), and the display device is an LCD.

[0085] Referring to FIG. 4, a CDA (100) is positioned on the upper surface of a Color Filter Glass (5). An R / G / B Color Layer (4) is positioned on the lower surface of the Color Filter Glass (5), and a common electrode (3) is positioned on the lower surface of the Color Layer (4).

[0086] Since the dielectric constant of the Color Filter Glass (5) and the dielectric constant of the Color Layer are different, a capacitance Ccm1 based on the dielectric constant of the glass and a capacitance Ccm2 based on the dielectric constant of the Color Layer (4) are formed in series between the CDA (100) and the Color Filter Glass (5). Therefore, the common electrode capacitance (Ccm) formed between the CDA (100) and the common electrode (3) is a composite capacitance formed by the series connection of Ccm1 and Ccm2.

[0087] Meanwhile, although not shown in FIG. 4, since the CDA signal line (200) is also part of the CDA (100), a common electrode capacitance is formed between the CDA signal line (200) and the common electrode (3). Therefore, when considering the magnitude of the common electrode capacitance (Ccm) due to the CDA (100), the magnitude of the common electrode capacitance (Ccm) due to the CDA signal line (200) must also be added.

[0088] If we assume that Fig. 4 is an OLED rather than an LCD, then reference numeral 5 becomes an encapsulation substrate, reference numeral 3 becomes a cathode, and reference numeral 4 can be replaced with a passivation on the upper surface of the cathode. Therefore, even when using an OLED as a display device, Ccm1 and Ccm2 are formed in the same way as in the LCD embodiment, and it is possible to calculate the size of Ccm using this.

[0089] A fixed voltage of a certain magnitude is supplied to the common electrode of an LCD (or the cathode of an OLED), and voltage fluctuations are not allowed to display a normal screen. Therefore, since the common electrode voltage (Vcm) connected to the common electrode capacitance (Ccm) cannot apply a driving voltage of a different magnitude, the common electrode capacitance (Ccm) cannot be located in the numerator of <Equation 1>. Therefore, the common electrode capacitance (Ccm) is a capacitance to which a driving voltage cannot be applied in the present invention relating to a device for detecting an added capacitance by driving multiple capacitances. As will be described later, a method is proposed to apply a driving voltage to the Ccm by changing the LCD process to form a "Ccm driving layer" on the upper surface of the common electrode (3) and applying a driving voltage to the Ccm driving layer.

[0091] Since the CDA (100) on the upper surface of the display device (10) has a different area depending on its position in the column, and the CDA signal line (200) also has different lengths depending on the position of the CDA (100), the magnitude of the common electrode capacitance (Ccm) has various distribution values ​​depending on the position of the CDA (100) within the display device (10). When calculating by substituting such various distribution values ​​into <Equation 1>, Vp2-Vp1 shows a value of various distribution as much as the magnitude of the common electrode capacitance (Ccm) varies. If the distribution of the calculated value according to <Equation 1> widens, it results in a worsening of the resolution of the ADC; therefore, it is desirable to maintain the magnitude of the common electrode capacitance (Ccm) constant regardless of the position of the CDA (100) within the display device (100).

[0092] As previously discussed, the magnitude of the common electrode capacitance (Ccm) formed between the CDA (100), the CDA signal line (200), and the common electrode (3) is correlated with the area (s) of the CDA (100) and the CDA signal line (200) and the opposing distance (d) of the common electrode (3) of the display device. Among these, the opposing distance (d) is a value determined during the manufacturing process of the display device and is an unchangeable factor. Therefore, a possible method to maintain the magnitude of the common electrode capacitance (Ccm) constant regardless of the position of the CDA (100) within the display device (100) is to maintain the area (s) of all CDA (100) and CDA signal line (200) as equally as possible.

[0093] The CDA (101, R1C1) located at a distance from the display device (10) has a long CDA signal line (201), and the CDA (103, R3C1) located at a short distance has a short signal line (203). If we assume that the area of ​​the CDA (101) at a distance and the area of ​​the signal line (201) connected thereto are 100%, and the area of ​​the CDA (103) at a short distance and the signal line (203) connected thereto are 80%, it is more advantageous to reduce the area of ​​the CDA (101) at a short distance and the signal line (201) at a short distance so that the sum of the areas becomes 80%, rather than increasing the area of ​​the CDA (103) at a short distance and the signal line, as this reduces the size of the common electrode capacitance (Ccm).

[0094] FIG. 5 is an embodiment of the present invention regarding a method for reducing the area of ​​a CDA (100) facing a common electrode (3).

[0095] Referring to FIG. 5, a portion of the CDA (100) is formed as empty spaces (150), and a portion of the conductor forming the CDA (100) is peeled off. By adjusting the ratio of the effective space to the empty space (150) in the CDA (100), it is possible to adjust the area of ​​the CDA (100) facing the common electrode (3). In the embodiment of FIG. 5, the empty space (150) is formed as a square, but it can be formed in various geometric shapes, such as a circle, triangle, rhombus, or a shape including an uneven surface with a continuously connected W. In addition, to avoid problems that may be visually perceived, the peeled shape in a single CDA (100) and in all CDAs (100) of the device must have the same shape. For example, if the peeled shape is a circle type, the peeled shape in a single unit CDA (100) is all circle, and the peeled shape in all CDAs of the device is also circle.

[0096] In addition, if the density of empty space in a single CDA (100) is different, the presence of the CDA (100) can be visually perceived on the display device (10) due to the difference in density, and since this serves to degrade the quality of the screen displayed on the display device, the density of empty space (150) in a single CDA (100) must be constant. Also, to reduce visual perception problems, it is desirable that the difference in density of empty space (150) with surrounding CDAs (100) be within 5% at most.

[0097] Because, when there are 25 CDAs (100) in one column and the density difference of the empty space between the upper and lower CDAs is 5%, the density difference of the empty space (150) between CDA 1 (100) and CDA 25 (100) is at least 70%, and as a result, the upper CDA and the lower CDA can be visually perceived due to the density difference of the empty space, and it may be impossible to design a density difference when the number of CDAs increases further.

[0098] Although a void space (150) can be installed in the CDA signal line (200), if the width of the signal line is narrowed due to the void space, it becomes a factor that increases the resistance of the CDA signal line (200), so preferably, a void space (150) is not formed in the CDA signal line (200).

[0099] In order to maintain the area of ​​the CDA (100) of Fig. 5 at 80%, 20% of the total area of ​​the CDA (100) is maintained as empty space (150). By calculating the area of ​​the CDA (100) and the CDA signal line (200) in this way and installing empty space (150) in the CDA (100), and ensuring that the sum of the effective areas excluding the empty space (150) for each CDA (100) is equal or similar, each CDA (100) has a common electrode capacitance (Ccm) of the same or similar size.

[0100] In this way, when the sum of the areas of a CDA (100) and a CDA signal line (200) installed at any location of a display device (10) is different from each other, the ratio of the empty space (150) peeled off from the CDA (200) is adjusted so that the sum of the areas of all CDA (100) and CDA signal lines (200) is the same or similar.

[0101] When designing and manufacturing CDA (100) according to these principles, the error range of the area between groups of 10 adjacent CDAs (100) is within ±20%, and the difference between the absolute area of ​​the empty space (150) peeled off from the distant CDA (101) and the absolute area of ​​the empty space (150) peeled off from the near CDA (103) is at least 20%.

[0102] The empty space (150) in the CDA (100) is used not only to maintain equal areas between the CDA (100) and the CDA signal line (200), but also to reduce the size of the common electrode capacitance (Ccm), thereby improving the detection sensitivity of the object capacitance (Cobj).

[0103] A method for achieving this objective is to reduce the effective area of ​​the CDA (100), and the ratio of the peeled empty space (150) in the CDA (100) is applied equally to all CDAs (100), but it is desirable that the area of ​​the peeled empty space (150) be 50% or more. In addition, it is desirable to limit the sum of the peeling ratio applied equally to all CDAs (100) and the peeling ratio applied differently to each CDA (100) to ensure equality of area between CDAs (100) to within 90% of the area of ​​any CDA (100). This is because at least 10% of the total area of ​​the CDA (100) must be maintained to enable detection of the object capacitance (Cobj).

[0105] Due to the influence of multiple CDA signal lines (200) belonging to a single column, the area of ​​the CDA (100) is reduced as it moves closer, and the signal line width of the distant signal line (201) is generally widened to reduce the magnitude of the line resistance. For this reason, since the area of ​​the CDA (100) and the CDA signal line (200) differs for each CDA (100), the magnitude of the common electrode capacitance (Ccm) differs for each CDA (100).

[0106] Due to the different common electrode capacitance (Ccm) for each CDA (100), deviations in the detection voltage based on <Equation 1> occur, which causes a decrease in the resolution of the ADC. A method to compensate for this problem is to supply charge by driving the common electrode capacitance (Ccm).

[0107] In FIG. 4, since the potential of the common electrode capacitance (Ccm) must not be changed, the method of driving the common electrode capacitance (Ccm) is to install a new driving layer between the CDA (100) and the common electrode (3) and apply a driving voltage to the new driving layer.

[0108] FIG. 6 is an embodiment of the present invention in which a new driving layer is installed between the CDA (100) and the common electrode (3).

[0109] Referring to FIG. 6, a new CCM driving layer (6) is formed on the upper surface of the color layer (4) of the LCD, and the CCM driving layer (6) is composed of a conductive transparent material such as ITO (Indium Tin Oxide) or Metal Mesh. If the display device (10) is an LCD, the CCM driving layer (6) may be installed anywhere between the CDA (100) and the common electrode (6). Additionally, if the display device (10) is an OLED, an insulating layer may be installed on the upper surface of the cathode, and the CCM driving layer (6) may be formed on the upper surface of the insulating layer.

[0110] A driving signal line (201) for applying a driving voltage is installed in the Ccm driving layer (6). In the case of an LCD, a driving voltage is applied to the Ccm driving layer (6) using metal paste at a Short Point, which is an electrical signal junction of the TFT substrate and the Color Filter substrate, or a driving voltage application method using a conductive ball is used.

[0111] In the case of an OLED, the Ccm driving layer (6) can apply a driving voltage by connecting to a driving signal line using a contact point with the metal on the lower side.

[0112] When driving voltages Vcm1 and Vcm2 (where Vcm2 > Vcm1) are applied to the Ccm driving layer (6), Equation 1 is modified as Equation 2.

[0113]

[0114] Compared to Equation 1, Equation 2 has the advantage that the Ccm driving layer (6) is driven and Ccm is located in the numerator, so the result of (Vp2-Vp1) caused by the deviation of the common electrode capacitance (Ccm) is reduced compared to Equation 1, and thus the resolution of the ADC is increased. Vcm1 and Vcm2 are applied from the driving unit (420) and follow the driving voltage application method of FIG. 14.

[0116] The following is an example of a method for forming a line capacitance (Cd) and applying a driving voltage to the line capacitance (Cd).

[0117] When detecting object capacitance (Cobj) in the CDA (100) of FIG. 3, the CDA signal line (202) connected to the A1 CDA (102, R2C1) is connected to the signal detection unit (410) of the semiconductor IC (400), and the CDA signal lines (201, 203) adjacent to this signal line are connected to the driving unit (420) of FIG. 8. The CDA signal line connected to the signal detection unit to detect object capacitance (Cobj) is referred to as the detection signal line, and the signal line adjacent to the detection signal line that is connected to the driving unit and to which a driving voltage is applied is referred to as the driving signal line. In this specification, the CDA signal line is represented by the reference numeral 200, the detection signal line is represented by the reference numeral 202, and the driving signal line is represented by the reference numeral 201.

[0118] A capacitor between lines is formed between the detection signal line (202) and the driving signal line (201) of CDA R1C1, and between the detection signal line (202) and the driving signal line (203) of CDA R3C1, as illustrated in FIGS. 7a and 7b.

[0119] FIG. 7a is an embodiment of the present invention regarding the formation of inter-line capacitance between a detection signal line (202) and two adjacent driving signal lines (201, 203), and is a cross-sectional view of A and A' of FIG. 3, and FIG. 7b is an embodiment of the present invention regarding the equivalent circuit of FIG. 7a.

[0120] Referring to FIGS. 7a and 7b, the driving signal lines (201, 203) adjacent to the left and right sides of the detection signal line (202) are spaced apart by a certain distance (d_pad) and have opposing areas, so a capacitance Cd201 is generated between them according to the mathematical formula es / d, and in the same way, a capacitance Cd203 is also formed between the detection signal line (202) and the driving signal line (203) adjacent to the right side.

[0121] Meanwhile, the detection signal line (202) faces the common electrode (3) with a width of d_sig(um) and is spaced apart by a distance equal to the thickness of the Color Filter Glass (5) and the thickness of the Color Layer (4), so a capacitance (Cd211) is formed according to the mathematical formula es / d.

[0122] In addition, a capacitance (Cd212) is formed between the detection signal line (202) and the common electrode (3) in the same way. When a driving voltage is applied to the driving signal line (201), the voltage of the driving signal line (201) rises above that of the detection signal line (202), and the charge supplied to the driving signal line (201) moves to the detection signal line (202) through Cd201, and moves to the detection signal line (202) along the capacitance path of Cd211 and Cd212.

[0123] Cd211 and Cd212 operate as a series-connected capacitance through the charge paths of Cd211 and Cd212, and since this capacitance operates as a capacitance connected in parallel with Cd201, which is another charge path, it is circuit analysis possible to consider that Cd1, which is an equivalent capacitance, is formed between the driving signal line (201) to which the driving voltage is applied and the detection signal line (202), as shown in FIG. 7b.

[0124] In the same way, when a driving voltage is applied to the driving signal line (203) on the right to detect a signal from the detection signal line (202), the capacitances formed between the detection signal line (202) and the driving signal line (203) on the right can be equivalently represented as Cd2 of FIG. 7-2.

[0125] Referring to <Mathematical Formula 6> described below, since the detection sensitivity of the object capacitance (Cobj) improves as the size of the inter-line capacitance (Cd) decreases, it is better for the size (Capacitance) of Cd1 or Cd2 in FIG. 7-2 to be smaller. In order to make the size of Cd1 or Cd2 smaller, it is better for the spacing (d_pad) between the detection signal line (202) and the driving signal line (201 or 203) to be wider, and it is better for the line width (Width, d_sig) of the detection signal line (202) and the driving signal line (201 or 203) to be narrower.

[0126] However, if the spacing between lines (d_pad) becomes too wide, the occupied area due to the CDA signal lines (200) increases, which reduces the width of the CDA (100) that detects the object (20). Additionally, a Dead Zone is formed due to the occupied area of ​​the CDA signal lines (200), causing a problem where detection errors occur as the area for detecting the object decreases. Furthermore, as the signal line width (d_sig) becomes narrower, the resistance of the CDA signal lines (200) increases, which increases the time required to detect the signal.

[0127] To solve this problem, the CDA signal line width is made long for long distances and narrows as it moves closer to the short distance. This manufacturing method reduces the resistance per unit length of the long signal line for long distances and increases the resistance per unit length for short distances, thereby reducing the variation in resistance according to the length of the signal line.

[0128] In order to reduce the time constant RC in an RC circuit formed by resistance (R) and capacitance (C), it is important to reduce the size of capacitance C in addition to reducing the size of resistance R. Since the distance between signal lines increases as the length increases and the size of the inter-line capacitance formed between signal lines increases as the distance decreases as the length of the signal lines decreases as the distance decreases, it is possible to reduce the variation in inter-line capacitance due to the difference in length between far and near signal lines by widening the inter-line spacing (Distance, d_pad) between far signal lines and narrowing the inter-line spacing between near signal lines, as the size of the inter-line capacitance per unit length is different.

[0129] If the same driving voltage is applied to the left driving signal line (201) and the right driving signal line (203), Cd1 and Cd2 can be equivalent to a single capacitance connected in parallel, that is, a single capacitance represented as Cd in FIG. 1 or Cd in FIG. 12. As a result, even if the driving signal line is driven in two directions—left and right—of a single detection signal line (202), it is possible to model it so that charge flows through a single capacitance (Cd), thereby enabling the establishment of <Equation 3> to <Equation 4>, which will be described later. To achieve this effect, two driving signal lines (201 and 203) adjacent to a single detection signal line (202) are interconnected so that the same driving voltage is applied.

[0131] Meanwhile, in order to apply a driving voltage to the aforementioned inter-line capacitance (Cd), a plurality of driving signal lines (201) adjacent to the detection signal line (202) must be selected as a pair and interconnected, and the same driving voltage must be applied to the interconnected driving signal lines. Therefore, a means for selecting the detection signal line (202) and the plurality of driving signal lines (201) adjacent to the detection signal line (202) in the column is required. In the embodiment of FIG. 3, one pair of driving signal lines adjacent to the detection signal line (202) was selected, but in order to reduce the saturation time of the driving signal lines (201, 203) for the applied driving voltage, a large number of driving signal lines, such as two pairs or three pairs, may be selected and the driving voltage applied. A pair is a driving signal line adjacent to a detection signal line on the left and right or up and down, and one driving signal line on each side of the detection signal line is a pair of driving signal lines, and two driving signal lines on each side of the detection signal line are two pairs of driving signal lines.

[0132] FIG. 7c is an embodiment of the present invention regarding a method for simultaneously selecting a driving signal line (201, 203) and a detection signal line (202).

[0133] Referring to FIG. 7c, a detection / drive signal line switch group (437, hereinafter, detection / drive switch group) composed of a plurality of switch groups (SG1 to SG3) is installed in one column. SG1, one of the switch groups constituting the detection / drive switch group (437), is a drive signal line switch group (437-2, hereinafter, drive switch group) that selects a drive signal line (203) adjacent to a detection signal line (202); SG2 is a detection signal line switch group (437-1, hereinafter, detection switch group) that selects a detection signal line (202); and SG3 is a drive switch group (437-2) that selects a drive signal line (201) adjacent to the right of the detection signal line (202).

[0134] Each switch group (SG1 to SG3) is composed of an equal or smaller number of internal switches (438, SW1 to SW3) as the CDA (100) included in one column. The internal switches (438) constituting the detection / drive switch group (437) are composed of transistors, CMOS, TFTs of LCDs, PMOS or NMOS of OLEDs, or combinations of PMOS and NMOS, and the energization status, such as turning on or turning off, is determined by the magnitude of the on / off voltage applied to the Gate or Base, which is the on / off control terminal. This method of configuring switches applies to all switches of this specification.

[0135] The drive switch group (437-2) can be installed in greater numbers than the two shown in FIG. 7-2. As described above, as more drive signal lines (201) are selected, such as two or three pairs rather than one pair, the drive switch group (437-2) is installed in the same number. For example, if three pairs of drive signal lines are selected, seven switch groups are installed, including one detection switch group (437-1) and six drive switch groups (437-2).

[0136] The CPU (460) or Logic unit inside the semiconductor IC (400) outputs an on / off control signal line and an on / off control signal that control the conduction of an internal switch (438) within a switch group. The on / off control signal line is connected to a Base or Gate, which is an on / off control terminal of the internal switch (438), and the on / off control signal applied to the control signal line determines the turn-on or turn-off state of the internal switch (438), and one detection signal line (202) connected to the internal switch (438) is selected by the turn-on of the internal switch (438).

[0138] The following is an example of simultaneously selecting one detection signal line (202) and a plurality of driving signal lines (201) adjacent to the detection signal line (202) in one column.

[0139] FIG. 7c illustrates a column composed of multiple CDAs (100), and the column contains 20 or more CDAs (100). All CDAs (100) included in the column are connected to a detection switch group (437-1) and multiple driving switch groups (437-2).

[0140] To select the detection signal line (202) of FIG. 7c, a turn-on voltage is applied to the (not shown) on / off control terminal of SW2, which is connected to the detection signal line (202) among the three internal switches (438) of the detection switch group (SG2), to turn on SW2, and a turn-off voltage is applied to the (not shown) on / off control terminals of the remaining internal switches (438), SW1 and SW3, to keep SW1 and SW3 switches in the turn-off state. As a result, the detection signal line (202) connected to the energized SW2 is selected in the detection switch group (SG2), and a signal is output through SW2.

[0141] In addition, to select the driving signal line (201) to the right of the detection signal line, SW3 of the driving switch group (SG3) is turned on and SW1 and SW2 are turned off, and to select the driving signal line (203) to the left of the detection signal line (202), SW1 of the driving switch group (SG1) is turned on and SW2 and SW3 are turned off. As a result, the driving signal line 203 is selected in the driving switch group SG1 and the driving signal line 201 is selected in the driving switch group SG3. The selected driving signal lines (201 and 203) are interconnected and connected to the driving unit (420) inside the semiconductor IC (400).

[0143] In one embodiment, the number of CDAs (100) included in one column may be 20 to 25 or more. If 25 are assumed in this specification, at least 25 internal switches (438) are required in one switch group, so 75 on / off control signal lines are required for the internal switches (438) of three switch groups (SG1, SG2, SG3). If the number of on / off control signal lines increases, there is a problem that the layout becomes complex.

[0144] FIG. 7d is an embodiment for solving the above-mentioned problem and is an embodiment of the present invention for reducing the number of switch control signal lines.

[0145] The embodiment of FIG. 7d is a detection / drive switch group (437) included in each column, and consists of one detection switch group (437-1) and two drive switch groups (437-2). It is assumed that 25 CDAs (200) are installed in the column, and all CDAs (100) are connected to all detection / drive switch groups (437).

[0146] An embodiment of the present invention for reducing the number of on / off control signal lines of a switch group is to use a decoder (436). For the input "n" signal lines, the decoder [uses] 2 n" It is a device that outputs two signal lines and outputs only one of the output signal lines in an Enable state, either High or Low.

[0147] Although only one decoder is shown in FIG. 7d, one decoder can be installed for each switch group. Since the 5x32 (5 inputs, 32 outputs) decoder outputs an Enable signal that selects and energizes one of the 25 internal switches (438) using 5 decoder input signal lines, it is possible to achieve the same effect as the existing 25 on / off control signal lines with 5 decoder input signal lines, thereby saving 20 signal lines. Therefore, if one decoder is installed for each switch group (SG1, SG2, SG3) of FIG. 7d, the existing 75 on / off control signal lines are reduced to 15.

[0149] Another embodiment is to apply a single decoder (436) to all switch groups (437).

[0150] Referring to FIG. 7d, the decoders installed individually in the three switch groups (SG1, SG2, SG3) require 15 input signals. If one decoder (436) can perform the role of three decoders, the 15 input signals will be reduced to 5.

[0151] When 25 on / off control signals output from one decoder (436) are connected to the on / off control terminals of the internal switches (438) of the three switch groups (437-1, 437-2), one internal switch (438) in the three switch groups (437-1, 437-2) is turned on by one turn-on voltage output from the decoder (436). If one detection signal is output through the internal switch turned on for each switch group and two driving signal lines can be selected, it is possible to perform the same role as three decoders with one decoder.

[0153] When the decoder (436) is inside the semiconductor IC (400), the signal level indicating High or Low input to the decoder is the same as the signal level used by the CPU (460) or the Logic unit. However, when the decoder (4436) is installed inside the display device (10), the signal level of the switching element used in the decoder is different from that of the semiconductor IC (400). Therefore, the signal output from the semiconductor IC (400) and input to the decoder (436) of the display device (10) needs to have its Logic Level changed by passing through a Level Shifter (439) in the middle.

[0154] In one embodiment, when the magnitude of the turn-off voltage output from the semiconductor IC (400) is 0V and the magnitude of the turn-off voltage of the decoder (436) or internal switch (438) built into the display device is -6V, and when the magnitude of the turn-on voltage output from the semiconductor IC is 3V and the magnitude of the turn-on voltage of the decoder (436) or internal switch (438) installed in the display device (10) is 10V, the 0V voltage output from the semiconductor IC (400) is converted to -6V by the level shifter (439), and the 3V voltage is changed to 10V.

[0155] In the decoder (436), on / off control signal lines corresponding to the number of CDA (100) included in the column are output, and a switch turn-on signal is applied to only one of the output signal lines. In the embodiment of FIG. 7d, 25 signals corresponding to G0 to G24 are output to correspond to 25 internal switches (438), and only one of the 25 signals outputs a voltage capable of turning on the internal switches (438).

[0156] The internal switches (438) of each switch group have their on / off control terminals jointly connected for each switch of the same order. Additionally, the output of the decoder (4360) is sequentially connected to the on / off control terminals of each jointly connected internal switch (438).

[0157] Referring to the embodiment of FIG. 7d, the on / off control terminal of the first internal switch of each switch group is jointly connected to the G0 address of the decoder (436), and the on / off control terminal of the second internal switch of each switch group is also jointly connected to the G1 address of the decoder, and so on, the on / off control terminals of the internal switches (438) having a common sequence number of all switch groups are jointly connected, and the outputs of the decoder are continuously connected from G0 to G25.

[0158] Even if the number of switch groups (437) is increased to 5 or 7 instead of 3 as in the embodiment of FIG. 7d, the on / off control terminals of internal switches with the same sequence number within all switch groups are jointly connected, and the output of one decoder (436) is continuously connected to the on / off terminal of the jointly connected internal switch (438).

[0159] The number of output signal lines of the decoder (436) is 25, but if the number of output signal lines used is less than 25, only the required number of output signal lines is used. In the embodiment of FIG. 7d, 25 signals are output from the decoder (436), but only 24 are used in switch group 1 (SG1), 25 are used in SG2, and only 23 are used in SG3.

[0161] Referring again to FIG. 7c, the present invention is characterized in that only the detection signal line (202) and the adjacent CDA signal line (200) are selected as driving signal lines (201 and 203). Among the plurality of CDAs (100) belonging to one column, the distant CDA (100) is designated as CDA No. 1, and the order of the CDAs is determined in ascending order as they get closer from distant to near distance. For n CDAs, the detection signal line and the driving signal line are combined as follows.

[0162] Combination of detection and driving signal lines

[0163] (CDA1, CDA2), (CDA1, CDA2, CDA3), (CDA2, CDA3, CDA4), (CDA n-2, CDA n-1, CDA n), (CDA n-1, CDA n)

[0164] In the first (CDA1, CDA2), CDA1 is the detection signal line (202) and CDA2 is the driving signal line. Below, the middle of the parentheses is the detection signal line and the left and right are the driving signal lines. When reaching the last CDA number n, in (n-1,n), n-1 is the driving signal line and n is the detection signal line.

[0165] To obtain such a combination, 1) the number of switch groups must be equal to the number of CDA signal lines (200) to be selected, and 2) the number of the CDA signal line (200) selected for the same address on / off control signal line output from the decoder (436) is such that when the n-th detection signal line is selected in the detection switch group, the (n-1)-th driving signal line is selected in one of the driving switch groups and the (n+1)-th is selected in one of the other driving switch groups. Since the output of the decoder (436) is connected equally to all switch groups, one CDA (100) is selected in each switch group for one Enable signal output from the decoder (436), and as a result, the detection signal line and the driving signal line are output simultaneously.

[0166] If the driving signal lines must be selected as multiple pairs (Pair) rather than one pair, for the nth CDA selected in the detection switch group, the driving signal lines "(CDAn±1), (CDAn±2), (CDAn±3).. (CDAn±m), m=1, 2, m. m is the number of pairs" are selected.

[0167] In order for this selection to be made, based on the CDA signal line (200) connected to the detection switch group, one number in one of the driving switch groups must be shifted to the left and one number in the other driving switch group must be shifted to the right. Whenever a driving signal line is added, the number is shifted m to the left and m to the right by the number of m pairs added. For example, if two pairs of driving signal lines are required, in addition to the existing pair, the second pair added is shifted by two numbers to the left and two numbers to the right based on the CDA signal line (200) connected to the detection switch group.

[0168] Referring to FIG. 7d, when the output G2 of the decoder (436) is connected to the on / off control terminal of the internal switch (438) of the detection switch group (SG2) and CDA3 is connected to the input terminal of the internal switch (438), in the driving switch group SG1, the CDA number is shifted one number to the right relative to the detection switch SG2, and CDA2 is connected to the input terminal of the internal switch (438) that uses the same decoder output G2. In the other detection switch group SG3, the number is shifted one number to the left relative to the detection switch group SG2, and CDA4 is connected to the input terminal of the internal switch (438) that uses the same decoder output G2. Since the CDA signal line (200) is not connected to the first or last internal switch (438) by the amount shifted to the left or right in the drive switch group (437-2), the number of internal switches (438) in the drive switch group is reduced by the number of shifts.

[0169] When a decoder is not used, 75 control signal lines are required for three switch groups, but if one decoder (436) is used per switch group, it is reduced to 15 control signal lines, and if one decoder of the present invention is used, the same effect can be achieved with 5 control signal lines. When the detection / drive switch group (437) and the decoder (436) are installed in the display device (10), due to the reduction of signal lines as described above, the number of signal lines transmitted from the semiconductor IC (400) to the display device (10) via the connecting member (300) is drastically reduced, thereby reducing the area of ​​the semiconductor IC (400) and reducing the area of ​​the junction (301) connecting the connecting member (300) and the display device (10), making it easier to configure the module of the display device (10), and there are many advantages such as the convenience of the layout due to the reduction in the number of signal lines within the display device (10).

[0171] Referring again to FIG. 3, the connecting member (300) is manufactured as a Flexible Printed Circuit (FPC), Chip On Film (COF), or Tape Carrier Package (TCP), and a semiconductor IC (400) is located on one side of the connecting member (300). A bonding portion (301) on one side of the connecting member (300) is bonded to a display device (10), and is connected to a PCB (not shown) through a connecting portion (302) formed on the other side, and a necessary signal is input from the PCB to the semiconductor IC (400) through this connecting portion (302).

[0172] The semiconductor IC (400) can be directly mounted in the form of a COG (Chip One Glass) on one side of the upper surface of the display device (10) or on the same layer where the DDI (Display Drive IC) of the display device is mounted. In this case, an external signal is input to the semiconductor IC (400) through a connecting member (300) on which the semiconductor IC (400) is not mounted.

[0173] In another embodiment, the semiconductor IC (400) may be mounted on a PCB or FPC other than the display device (10) or the connecting member (300) and connected to the display device (10) through the connecting member.

[0174] In another embodiment, the semiconductor IC (400) may be manufactured as an integral part of the DDI (Display Drive IC) that drives the display device (10) and may be located inside the DDI.

[0176] FIG. 8 is an embodiment of the present invention regarding the configuration of a semiconductor IC (400).

[0177] Referring to FIG. 8, there are four CDA columns composed of three CDAs (200), and the CDA signal line (200) connected to the CDA (100) is connected to the signal line input Pin (401) of the semiconductor IC (400). The signal line (200) connected to the signal line input Pin (401) is simultaneously connected to the detection switch group (437-1) and the driving switch group (437-2).

[0178] Although the drive switch group (437-2) is shown as one, it may be composed of two switch groups (SG1 and SG3) as in the embodiment of FIG. 7d, or composed of four or more switch groups.

[0179] Since one detection signal line (202) is selected through a dedicated detection switch group (437-1) in one column, four column detection signal lines (210 to 240) are selected in four columns, and driving signal lines (210-1 to 240-1) are selected for each column through a dedicated driving switch group (437-2) for each column and input to the driving unit (420). In the embodiment of FIG. 8, the driving unit is shown as being separated into two parts, but this is for the convenience of drawing, and it can be separated into one or more driving units.

[0180] In the embodiment of FIG. 8, a component such as a detection / drive switch group (437), a Loader (450), or an AMP input signal line selection unit (430) connected to the Loader (450) may be installed embedded in a display device, and in this case, a detection signal line (202) output from a component embedded in the display device (10) is connected to a signal line input pin (401).

[0181] The detection signal lines (210 to 240) selected in each column are input to the first group Loader (450-1) and the second group Loader (450-2). The Loader is a device that outputs all signals input to the Loader (450) by the "LD" Enable signal generated by the Logic unit of the signal detection unit (410) or the CPU (460).

[0182] Preferably, one Loader (450) is installed for each column group. The Loader (450) includes switches equal to the number of CDA columns included in the column group. The Loader (450) is manufactured as a combination of PMOS, NMOS, or CMOS in the semiconductor IC (400), and when the Loader of the present invention is installed in the display device (10), it is composed of a-Si, Oxide, LTPS TFT, or OLED PMOS or NMOS and a combination thereof used as pixel switching elements of the display device (10), and is composed of the same switching elements as the switching elements used in the display device. The switch used in the Loader (450) or the detection / driving switch group (437) is a switch that transmits an input signal without loss, and is referred to as a Transfer Switch in this specification.

[0183] One method of outputting all signals input to the Loader (450) by the enabled "LD" signal is that the LD signal is connected to the on / off terminals of all switches constituting the Loader (450), and since all switches of the Loader (450) are turned on simultaneously by the High or Low LD Enable signal, all signals input to the Loader (450) are output simultaneously.

[0184] A set of columns composed of multiple CDA columns forms multiple meaningful combinations. As in the embodiment of FIG. 8, it may be divided into two groups, such as a left side group and a right group, or into two groups, such as an odd group composed only of odd columns and an even group composed only of even columns, and in some embodiments, it may be divided into three or four or more repeating groups.

[0185] The embodiment of FIG. 8, divided into a left group and a right group, includes only two columns on the left and two columns on the right for convenience, but in actual use, each group may include 10 or more columns.

[0186] Multiple detection signal lines output from multiple columns of the same group are gathered and connected to a dedicated Loader (450) for that group. Referring to FIG. 8, two column signal lines (210 and 220) of the left group, which consists of two columns, are connected to a first group Loader (450-1), and two column signal lines (230 and 240) of the right group are connected to a second group Loader (450-2). If it is assumed that the number of columns included in the left group is 10, then 10 detection signal lines are connected to the first group Loader (450-1) dedicated to the left group.

[0187] The semiconductor IC (400) of the present invention uses an ADC and a DAC to detect object capacitance (Cobj) in the form of voltage. Multiple ADCs or DACs may be used, and preferably, one DAC and one ADC are used. When one DAC and one ADC are used, processing is performed for multiple groups in a time-division method. For example, when the left group is being processed, the right group is not processed, and when the processing of the left group is completed and the processing ends, the right group is then started, and when the processing of the right group ends, the processing of the left group is started again, and so on, the start and end of processing for each group are repeated, and the operation of one ADC and one DAC only in the group where processing is started is called time-division method operation.

[0188] Although it is possible to process the detection signal lines of all columns included in the device of the present invention simultaneously, as the number of columns increases, the operating time of the time-division ADC and DAC increases, and there is a problem in that discharge occurs in the detection signal lines of columns processed later, causing distortion of the detected signal.

[0189] Therefore, it is a good way to prevent signal distortion caused by discharge of the detection signal lines by dividing the column groups as much as possible and processing only the limited detection signal lines within a column group before processing the next group. It is better to divide the groups as much as possible, but since preparing to detect the signal takes a lot of time, it is generally better to separate them within the range of 2 or 4.

[0190] As such, the device of the present invention is divided into a plurality of groups consisting of sets of columns including a plurality of CDAs (100), and is characterized by having different processing start times for detecting object capacitance (Cobj) for each group.

[0192] All detection signal lines (250) simultaneously output from the Loader (450) are transmitted to the signal detection unit (410). Inside the signal detection unit (410), there is a differential amplifier or an AMP input signal line selection unit (430-2) or an ADC or DAC, and the input detection signal lines (250) are sequentially selected to extract the magnitude of the object capacitance (Cobj) using a time division method.

[0193] The signal detection unit (410) detects the voltage defined in <Equation 1> or <Equation 4>, and the detected voltage is digitized by the ADC and stored in memory. The data stored in memory is transmitted to the CPU (460), after which the CPU calculates whether an object appears or the location of an object, and the calculated information is transmitted to a Host CPU located outside the semiconductor IC (400). The CPU (460) inside the semiconductor IC (400) and the memory storing the ADC data may be located outside the semiconductor IC (400), and the Host CPU may act as the CPU of the semiconductor IC (400).

[0194] Meanwhile, the semiconductor IC (400) may include a logic unit that controls components used in the device, such as a CPU (460), memory, switch group / decoder / Loader / AMP input signal line detection unit, or a power supply unit, an oscillator, a level shifter (439), and all components mentioned in the specification for implementing the device of the present invention, as well as universal circuit elements used for signal analysis or software for driving the CPU (460).

[0196] A semiconductor IC (400) is formed by stacking multiple insulating layers and multiple conductive layers on a substrate (461) in a specific pattern, and includes multiple components having electrical characteristics and multiple wirings. For example, a source metal layer, a gate metal layer, a power layer, a ground layer, or a signal for any purpose may constitute a signal layer. Since this signal layer is patterned with conductive metal, it is separated by an insulator layer to avoid short circuits between adjacent signal layers.

[0197] FIG. 9 is an example of a layer configuration of a semiconductor IC (400). Referring to FIG. 9, an insulating layer (462) is placed on the upper surface of a semiconductor silicon substrate (461), and a first signal layer (463), a second signal layer (464), and a third signal layer (465) are placed on the upper surface of the insulating layer. Each signal layer is patterned with a metal line, and the patterned line serves to transmit a signal, supply power, or act as a ground. In this embodiment, three signal layers are used as an example, but three or more signal layers may be used.

[0198] Referring again to FIG. 8, the detection signal line (202) of the present invention is classified into several different names depending on its location within the semiconductor IC (400), such as the Pin input signal line (200-1), column detection signal lines (210 to 240), and group detection signal lines (250-1 and 250-2). The Pin input signal line is the detection signal line (200-1) in the path where the CDA signal line (200) connected to the input Pin (401) is input to the detection switch group (437-1), the detection signal line in the path where it is output from the detection switch group (437-1) and input to the Loader (450) is the column detection signal line, and the detection signal line output from the Loader (450) is called the group detection signal line.

[0199] In a general embodiment, these three types of detection signal lines are patterned and arranged in a specific pattern at any location of the first signal layer (463) to the third signal layer (465), and the three types of detection signal lines (200-1, 210~240, 250-1 / 250-2) are arranged according to the facing distance (d1) and facing area (S1) with the lower semiconductor substrate (461) or the facing distance (d2) and facing area (S2) with the "other signal lines" of the upper layer. and An IC internal capacitance (Cprs) is formed as a parallel composite capacitance (Cprs1+Cprs2) of two capacitances having the size of . Since the internal capacitance (Cprs) is formed by IC internal signal lines (200-1, 210~240, 250-1 / 250-2) which are extensions of the detection signal line (202), it is equivalent to one end being connected to point P, which distinguishes the detection signal line (202) in the embodiment of FIG. 12, and the other end being connected to a power source (Vprs) provided by a semiconductor substrate (461) or "another signal line".

[0200] There are two problems with these IC internal capacitances (Cprs), the first of which is detection error due to signal interference.

[0201] The "other signal lines" inside the semiconductor IC (400) are logic signals synchronized with the clock, power signals, oscillators, or analog signals. Among these multiple internal IC (400) signal input / output lines, if the logic signal line, clock signal line, or oscillator signal line is opposed to the CDA detection signal line (200-1, 210~240, 250-1 / 250-2), noise may be introduced through coupling via internal parasitic capacitance (Cprs1 or Cprs2) formed between the mutually opposing areas, and this noise may affect the CDA detection signal line (200-1, 210~240, 250-1 / 250-2), causing signal distortion in the detection signal line (200-1, 210~240, 250-1 / 250-2) and resulting in a signal detection error.

[0202] In order to solve this problem, the layout of "other signal lines" that cause noise is avoided on the upper or lower side of the CDA detection signal lines (200-1, 210~240, 250-1 / 250-2) inside the IC, and this reduces the freedom of patterning design and becomes a factor that exacerbates the difficulty of development.

[0203] The second problem caused by the IC internal capacitance (Cprs) is that the length of the path (200-1, 210~240, 250-1 / 250-2) reaching from the signal line input pin (401) of FIG. 8 to the signal detection unit (410) is different for most detection signal lines, and due to the difference in path length, the magnitude of the internal parasitic capacitance (Cprs) varies for each detection signal line, and as a result, a deviation occurs in the result value of <Equation 1>, which causes the resolution of the ADC to decrease.

[0204] To solve the above-mentioned problem, the present invention installs a conductive shielding area on the upper layer or lower layer of the IC internal signal line (200-1, 210~240, 250-1 / 250-2) and applies a driving voltage to the installed shielding area to reduce the deviation of the output voltage of <Equation 1> caused by the difference in magnitude of the internal parasitic capacitance (Cprs) of the semiconductor IC (400) internal detection signal line (200-1, 210~240, 250-1 / 250-2). Preferably, an IC internal detection signal line (200-1, 210~240, 250-1 / 250-2) is placed on the uppermost surface of the semiconductor IC (400), a conductive shielding area is placed below this signal line, and the size of the shielding capacitance (Cin_sd) is further reduced, and a driving voltage is applied to this shielding area to detect the signal.

[0205] FIG. 10 is an embodiment of the present invention in which a shielding area is added to the detection signal lines (200-1, 210~240, 250-1 / 250-2) inside the semiconductor IC (400), and FIG. 11a is a cross-sectional view of B-B' located in column 1 of FIG. 10.

[0206] Referring to FIGS. 10 and FIGS. 11a, the upper signal layer (465) and lower signal layer (463) of the semiconductor IC (400) signal layer (464) patterned with the Pin input signal line (200-1) of column 1 have a column 1 first shielding area (261) installed.

[0207] In addition, the first shielding area (262) of column 2 is placed on the upper and lower signal layers of the Pin input signal line (200-1) input to column 2, and the first shielding area of ​​column 3 and the first shielding area of ​​column 4 are placed in the same way on the remaining columns 3 and 4.

[0208] Referring to FIG. 11a, which is a cross-sectional view of B-B' of the first shielding area (261) of the column, the Pin input signal lines (200-1 to 200-3) are placed in the second signal layer (464), which is an intermediate layer of the semiconductor IC (400) signal layer. The upper shielding area (261-1) of the first shielding area (261) of the column 1 is placed above the three signal lines (200-1 to 200-3) placed in the second signal layer (464), and the lower shielding area (261-2) of the first shielding area (261) of the column 1 is placed below. That is, the first shielding area (261) of the column 1 is divided into an upper shielding area (261-1) and a lower shielding area (261-2) and is placed above and below the detection signal lines (200-1 to 200-3).

[0209] The upper shielding area (261-1) and the lower shielding area (261-2) are electrically connected to each other at any point via a Contact Point and connected to the Column 1 first shielding area driving signal line (251). The Column 1 first shielding area driving signal line (251) is connected to a driving unit (420) to apply a driving voltage to the Column 1 first shielding area (261).

[0210] When a stable DC voltage is applied to the first shielding area (261) of the Column 1 of the present invention, which is installed on the upper and lower sides of the detection signal lines (200-1 to 200-3), the coupling caused by the capacitance formed between the detection signal line (200-1) and the "other signal line" (which exists on the upper or lower side of the shielding area) of the other signal layer (not shown) is blocked by the first shielding area (261), so that noise interference caused by the coupling between the detection signal line (200-1) and the "other signal line" does not occur, and also when a driving voltage is applied to the first shielding area, the deviation of the voltage detected in the detection signal line (202) is reduced as described later, and the resolution of the ADC is improved.

[0211] In addition, since there are "other signal lines" on the left and right sides of the detection signal line (200-1), it is desirable to place shielding areas (261-3) on the left and right sides of the detection signal line (200-1) to apply DC voltage or driving voltage. At this time, the shielding areas (261-3) located on the left and right sides of the detection signal line (200-1) are connected to the upper shielding area (261-1) or lower shielding area (261-2) of the column 1 first area driving signal line (251) or the column 1 first shielding area using the Short Point technique of the semiconductor manufacturing process at any point.

[0212] All column detection signal lines (210 / 220 / 230 / 240) are also placed in the intermediate layer (464) of the semiconductor metal layer, and second shielding areas (263, 264) are installed on the upper (465) and lower (453) signal layers and on the left and right sides. In addition, third shielding areas (265) for Group 1 and third shielding areas (266) for Group 2 are installed on the upper and lower layers and on the left and right sides of Group 1 detection signal lines (250-1) and Group 2 detection signal lines (250-2). Furthermore, a shielding area driving signal line is installed for each shielding area and connected to a driving unit (420).

[0213] In the embodiment of the present invention, the first shielding area, the second shielding area, and the third shielding area are virtual areas introduced to explain the embodiment of the shielding area. In reality, they may be subdivided further or reduced to one or two. Importantly, a shielding area is installed along every path from the point where a single detection signal line (202) reaches the signal detection unit (410) through the layout inside the semiconductor IC (400), and the shielding area is connected to the shielding area driving signal line and connected to the driving unit (420), and the driving unit (420) applies a driving voltage according to the driving method of FIG. 14, which will be described later.

[0214] As described above, a shielding area is installed on the upper or lower side or left and right side of all paths where a single detection signal line (202) is connected to the input pin (401) of the semiconductor IC (400) and input to the signal detection unit (410). When no signal is detected, a stable DC voltage is supplied to the shielding area to block noise, and when a signal is detected, a driving voltage is applied so that the term of the shielding capacitance is placed in the numerator of <Equation 1>. This eliminates the internal parasitic capacitance (Cprs) that was the cause of the deviation in the detection value in <Equation 1>, and instead, the deviation of the voltage detected from the detection signal line (202) is reduced due to the driving of the shielding capacitance, thereby improving the resolution of the ADC.

[0216] In the embodiments of FIGS. 10 and FIGS. 11a, the first shielding area of ​​the column covers all detection signal lines (200-1 to 200-3) included in the shielding area and drives the shielding area with a single shielding area driving signal line. However, it is possible to install individual shielding areas for each individual detection signal line, such as a dedicated shielding area for detection signal line 200-1, a dedicated shielding area for detection signal line 200-2, and a dedicated shielding area for detection signal line 200-3, and to apply a driving voltage to each individual shielding area. In this case, although there is a disadvantage that the number of driving units driving individual shielding areas increases, there is an advantage that only the necessary shielding capacitance is driven, and since the area of ​​the individual shielding area for driving is reduced, the capacitive loading is reduced, and the current capacity of the driving element of the driving unit is reduced, thereby reducing the current consumption.

[0218] In the embodiments described so far, shielding areas are installed on the upper and lower surfaces and left and right sides of the detection signal line (200-1,210~240,250-1 / 250-2) by modifying the layout inside the semiconductor IC. Capacitance is formed between the shielding areas on the upper and lower surfaces facing the detection signal line (200-1,210~240,250-1 / 250-2) and between the shielding wires on the left and right sides of the detection signal line (200-1,210~240,250-1 / 250-2), and the sum of these capacitances is referred to as shielding capacitance (Cin_sd).

[0219] Since the shielding capacitance (Cin_sd) is formed between the detection signal line (202) and the shielding region, the shielding capacitance (Cin_sd) can be modeled as an equivalent circuit in which one side is connected to the detection signal line (202) and the voltage supplied to the shielding region is connected to the other side. Additionally, since the shielding capacitance (Cin_sd) is connected in parallel with the common electrode capacitance (Ccm) and the inter-line capacitance (Cd) at the detection signal line (202), it is possible to model it as having one side connected to point P and a voltage (Vcin) applied to the other side as shown in FIG. 12b.

[0220] Referring to Equation 1, the calculated value before and after the object capacitance (Cobj) is added to the denominator of Equation 1 decreases as the value of the capacitance in the denominator increases. To improve the detection sensitivity of the object capacitance, the magnitudes of the capacitances in the denominator must be reduced.

[0221] The present invention detects object capacitance (Cobj) when object capacitance (Cobj) is added. To achieve this objective, it is necessary to improve the sensitivity of object capacitance (Cobj). Therefore, a method is proposed to reduce the size of the common electrode capacitance (Ccm) due to the empty space (150), and a design plan is proposed to adjust the inter-line width (d_pad) between detection signal lines to reduce the size of the inter-line capacitance (Cs). Since shielding capacitance (Cin_sd) also affects the detection sensitivity of object capacitance (Cobj), it is better for the size of the shielding capacitance to be as small as possible. The following is a method to reduce the size of the shielding capacitance (Cin_sd).

[0222] As the size of the capacitance formed between the two conductors decreases as the area of ​​opposition between the two conductors decreases, the size of the shielding capacitance (Cin_sd) is reduced by narrowing the width of the detection signal line (200-1,210~240,250-1 / 250-2) forming the shielding capacitance (minimizing the area of ​​opposition S), thickening the width of the insulator (462) between the detection signal line (200-1,210~240,250-1 / 250-2) and the shielding region (minimizing the distance of opposition d), and increasing the distance between the shielding wires on the left and right of the detection signal line (minimizing the distance of opposition d).

[0223] Since the minimum width of the metal and the minimum thickness of the insulator (462) constituting the detection signal line (200-1, 210~240, 250-1 / 250-2) in the semiconductor IC (400) process cannot be changed, there is a limit to reducing the size of the shielding capacitance (Cin_sd) even when the size of the shielding capacitance (Cin_sd) formed according to the minimum width of the metal and the minimum thickness of the insulator (462) is not satisfactory.

[0224] To solve these problems, the present invention positions the detection signal line (200-1, 210~240, 250-1 / 250-2) on the uppermost surface of the semiconductor IC (400), so that there is no signal layer above the detection signal line, and installs a shielding area only on the lower side of the detection signal line (200-1, 210~240, 250-1 / 250-2).

[0225] FIG. 11b is another embodiment of the present invention regarding the implementation of a shielding region.

[0226] Referring to FIG. 11b, three Pin input signal lines (200-1 to 200-3) inside the semiconductor IC (400) are placed on the uppermost surface (465) of the metal layer of the semiconductor IC (400), and there is no metal layer for placing "other signal lines" on the upper surface of the Pin input signal lines (200-1 to 200-3).

[0227] A Column 1 first shielding area (261) is positioned below the Pin input signal lines (200-1 to 200-3), and a shielding area (261-3) electrically connected to the Column 1 first shielding area (217) is installed on the left and right sides of the CDA signal lines. This structure is applied to all detection signal lines, including the column detection signal lines (210 to 240) and the group detection signal line (250).

[0228] Compared to the embodiment of FIG. 11a in which shielding regions are arranged on the upper, lower, left, and right sides of the detection signal lines (200-1, 210~240, 250-1 / 250-2), this structure has the effect of reducing the size of the shielding capacitance (Cin_sd) by about half because shielding regions are arranged only on the lower and left and right sides.

[0229] Since the detection signal lines (200-1, 210~240, 250-1 / 250-2) placed on the uppermost layer may use lower metal layers (463 and 464) to be connected to the signal detection unit (410), it is desirable to maintain the ratio of any detection signal line placed on the uppermost layer at least 50% of the ratio of the total detection signal lines.

[0231] As seen so far, the present invention has 1) a common electrode capacitance (Ccm), 2) a composite capacitance between lines (Cd), and 3) a shielding capacitance (Cin_sd) combined in parallel on a single CDA signal line (200). If the resistance of the CDA signal line (200) is not taken into account, the CDA signal line (200) is equivalent to a single point (P in FIG. 1), which is equivalent to the common electrode capacitance (Ccm), the composite capacitance between lines (Cd), and the shielding capacitance (Cin_sd) being connected in parallel at a single point (P).

[0232] Previously, the shielding capacitance (Cin_sd) was positioned in the denominator of <Equation 1> in the form of uncontrollable internal parasitic capacitance (Cprs), acting as an unnecessary dummy that reduced sensitivity. In some cases, a separate capacitance was introduced to apply the driving voltage and added to the denominator of <Equation 1>, thereby reducing sensitivity. However, in the present invention, the internal parasitic capacitance, which previously acted as an unnecessary dummy, is modified into a shielding capacitance to apply the driving voltage, thereby supplying additional charge and improving sensitivity.

[0234] FIG. 12a is an embodiment of the present invention that applies a driving voltage to a shielding capacitance (Cin_sd).

[0235] Referring to Fig. 12-1, iin_sd = id + icm. (where iin_sd is the current flowing through the shielding capacitance (Cin_sd), icm is the current flowing through the common electrode capacitance (Ccm), and id is the current flowing through the line-to-line capacitor (Cd). Also, Vd is the constant voltage applied to one side of the line-to-line capacitance (Cd), and Vcm is the common electrode constant voltage applied to one side of the common electrode capacitance (Ccm). Additionally, two driving voltages, distinguished as Vcin1 and Vcin2, are applied to one side of the shielding capacitance (Cin_sd).)

[0236] am.

[0237] Since iin_sd=id + icm,

[0238] am.

[0239] If we rearrange this mathematical equation for Vp, It can be seen that.

[0240] Vp1, the voltage at point P when Vcin1 is applied to the shielding capacitance (Cin_sd), is,

[0241] And,

[0242] Vp2, the voltage at point P when Vcin2 is applied to the shielding capacitance (Cin_sd), is,

[0243] am.

[0244] The shielding capacitance (Cin_sd) is driven by two different voltages, Vcin1 and Vcin2, and the difference between Vp1 and Vp2 detected at P is given by Equation 3 below.

[0245]

[0246] FIG. 12b is an example in which a driving voltage is applied to the line capacitance (Cd) and the shielding capacitance (Cin_sd), respectively, and a driving voltage is applied to the capacitance excluding the common electrode capacitance (Ccm).

[0247] In the embodiment of FIG. 1, Equation 1 was derived by applying driving voltages (Vd1, Vd2) only to the line capacitance (Cd), and in the embodiment of FIG. 12a, Equation 3 was derived by applying driving voltages (Vcin1, Vcin2) only to the shielding capacitance (Cin_sd).

[0248] Referring to FIG. 12b, a driving voltage is applied to the line capacitance (Cd) and the shielding capacitance (Cin_sd). The line capacitance (Cd) is driven by Vd1 and Vd2, and the shielding capacitance (Cin_sd) is driven by Vcin1 and Vcin2.

[0249] When a driving voltage is applied to two capacitances, the voltage Vp at point P can be calculated by the superposition theory by referring to Equations 1 and 3.

[0250] When a driving voltage is applied to the line capacitance (Cd) and shielding capacitance (Cin_sd), respectively, the potential Vp at point P is given by Equation 4.

[0251]

[0252] Figure 13a is virtual data for verifying <Equation 4> and is identical to the data in Figure 2-1. Figure 2-1 is data for the case of Single Driving in which only the inter-line capacitance (Cd) is driven, and simulation results for Vp2-Vp1, while Figure 13a is the result for Single Driving and simulation results for Vp2-Vp1 in the case of Dual Driving in which two capacitances, such as the inter-line capacitance (Cd) and shielding capacitance (Cin_sd), are driven simultaneously.

[0253] When applying the data of Fig. 13a to Equation 1, when Single Driving is performed with only the inter-line capacitance (Cd) as Vd1 and Vd2 driving voltages, the difference between the maximum and minimum values ​​of (Vp2-Vp1) is 1.429V. In the case of Dual Driving, where the inter-line capacitance (Cd) excluding the common electrode capacitance (Ccm) is driven with Vd2 and Vd1 and the shielding capacitance (Cin_sd) is driven with Vcin2 and Vcin1, the difference between the maximum and minimum values ​​of (Vp2-Vp1) is 0.271V.

[0254] When using a 10-bit ADC with a detection range of 1.6V to detect 1.429V (Vp2-Vp1) at point P during single driving, the resolution is 1.56mV / bit. When using a 10-bit ADC with a detection range of 300mV to detect 0.271V (Vp2-Vp1) detected at point P during dual driving, the resolution is approximately 0.3mV / bit. Therefore, it can be seen that the resolution improves by more than 5 times with the same capacitance configuration simply by changing the driving method.

[0255] This phenomenon occurs because a capacitance to which no driving voltage is applied operates as a load capacitance that shares charge with the charge supplied by the capacitance to which the driving voltage is applied, whereas the driven capacitance operates as a source supplying charge. Within the defined size of the mutually connected capacitances, the larger the size of the capacitance supplying charge, the smaller the size of the load capacitance becomes, resulting in a smaller voltage difference for the same driving voltage. Additionally, as the driving capacitance increases, the amount of charge sharing in the added object capacitance (Cobj) increases, which has the effect of improving sensitivity.

[0256] Since the voltage difference (Vp2-Vp1) caused by the driving voltage is generated by the deviation of the load capacitance that is not driven out of the total capacitance, the deviation of Vp2-Vp1 becomes smaller as the proportion of the non-driving capacitance in the total capacitance (capacitance located in the denominator of Equation 1) decreases. Based on this principle, the present invention proposes a method to reduce the size (Capacitance) of the capacitances located in the denominator of Equation 1, modifies the internal parasitic capacitance (Cprs) to which the driving voltage cannot be applied so that the driving voltage can be applied, and presents a device that can apply the driving voltage to the common electrode capacitance (Ccm). As a result, the deviation of the voltage detected in the detection signal line (202) before and after the application of the driving voltage is reduced, thereby narrowing the detection range of the ADC to improve the resolution of the ADC and improving the detection sensitivity of the added object capacitance (Cobj).

[0257] Meanwhile, FIG. 13b is a graph of the results of Equations 1 and 4 calculated based on the data in FIG. 13a.

[0258] Figure 13b illustrates Vp2-Vp1 for Single Driving based on Equation 1 and Dual Driving based on Equation 4 under the same conditions. In the case of Single Driving, the common electrode capacitance (Ccm) and internal parasitic capacitance (Cprs) act as load capacitances, resulting in a large deviation in Vp2-Vp1. However, in the case of Dual Driving, only the common electrode capacitance (Ccm) acts as load capacitance, and since the deviation in Vp2-Vp1 is mostly caused by the deviation of the common electrode capacitance (Ccm), it can be seen that the fluctuation range of Vp2-Vp1 is stable for the common electrode capacitance (Ccm), which has a relatively small deviation.

[0259] Referring again to FIGS. 13a and 13b, it can be expected that if the magnitude (capacitance) of the shielding capacitance (Cin_sd) is nearly constant, the fluctuation range of the voltage detected at point P will be further reduced.

[0260] Since the size (Capacitance) of the shielding capacitance (Cin_sd) is determined mainly by the width of the detection signal lines (200-1,210~240,250-1 / 250-2) inside the semiconductor IC (400), it is possible to set the size of the shielding capacitance by the detection signal lines (200-1,210~240,250-1 / 250-2) to be almost similar for each signal line by adjusting the signal line width. In one embodiment, the width of a signal line with a long length is narrowed to the minimum width to reduce the size (Capacitance) of the shielding capacitance (Cin_sd), and the width of a signal line with a short length is widened to increase the size (Capacitance) of the shielding capacitance (Cin_sd). Since the length of the detection signal line in the semiconductor IC (400) can be calculated, it is possible to design and manufacture it so that the area obtained by multiplying the signal line width and length is the same for all detection signal lines, thereby maintaining a constant size of the shielding capacitance (Cin_sd) for each detection signal line.

[0261] Thus, the present invention adjusts the line width of the internal detection signal lines (200-1, 210~240, 250-1 / 250-2) of the semiconductor IC (400), making the width of the longer signal lines larger than that of the shorter signal lines, thereby adjusting the area between the detection signal lines to be similar, so that the size of the shielding capacitance (Cin_sd) formed by the detection signal lines (200-1, 210~240, 250-1 / 250-2) can be generated similarly for each signal line, thereby reducing the deviation of (Vp2-Vp1) according to Equation 4.

[0263] Up until now, the expression “forcing a driving voltage” has been used to describe applying Vd1 and Vd2 to the line capacitance (Cd) of Equation 1 or Equation 4, or applying Vcin1 and Vcin2 to the shielding capacitance (Cin_sd), and applying a driving voltage means applying two voltages of different magnitudes to the capacitance.

[0264] FIG. 14 is an embodiment of the present invention regarding the application of a driving voltage.

[0265] Referring to FIG. 14, the upper drawing is an example of a method for applying a driving voltage (Vd2, Vd1) to a line capacitance (Cd), and the lower drawing is an example of applying a driving voltage (Vcin2, Vcin1) to a shielding capacitance (Cin_sd), wherein the driving voltage has the following characteristics.

[0266] 1. The driving voltage consists of a High Voltage and a Low Voltage, and a combination of the High Voltage and Low Voltage constitutes a Cycle Time. As the driving voltage changes (transition), an increase or decrease in charge occurs in the driven capacitance, and voltage fluctuations occurring in the non-driven capacitance can be detected by utilizing the charge sharing phenomenon that occurs in the non-driven capacitance according to this increase or decrease in charge.

[0267] 2. Different Cycle Times may be applied depending on the position of the CDA (100) installed in the display device (10).

[0268] For example, since the line resistance and line-to-line capacitance (Cd) of the CDA signal line (201) located far from the semiconductor IC (400) are greater than the line resistance and line-to-line capacitance (Cd) of the CDA signal line (203) located near the semiconductor IC (400), more time is required for the signal to reach a stable state (saturation status). Therefore, the cycle timer of the driving voltage supplied to the far CDA signal line must be longer than the cycle time supplied to the near CDA.

[0269] Referring to ZONE A in FIG. 14, it has a cycle time of 50% compared to ZONE B to ZONE D. This cycle time of ZONE A can be applied to CDA (103) located near the semiconductor IC (400), and a cycle having a width that is two or three times greater than the cycle time of ZONE A can be applied to CDA (101) located far from the semiconductor IC (400).

[0270] 3. When changing the voltage from Low Voltage to High Voltage or from High Voltage to Low Voltage to apply a driving voltage, there are methods of driving with a pulse wave as in the example of ZONE A in FIG. 14 and methods of driving smoothly with a rising edge and falling edge as a sine wave as in ZONE B to ZONE D. Since driving with a pulse wave with sharp edges can cause EMC or EMI problems due to voltages having sharp rising or falling edges such as the 1st, 3rd, or 5th harmonics of the pulse wave, it is desirable to drive the rising edge and falling edge of the driving voltage smoothly in the form of a sine wave.

[0271] 4. The driving voltage can be driven from "low voltage to high voltage" as in the embodiments of ZONE A to ZONE D of FIG. 14, and can also be driven from "high voltage to low voltage" as in the embodiment of ZONE S of FIG. 14. However, a low voltage must be applied simultaneously or a high voltage must be applied simultaneously to the capacitance connected to a single detection signal line.

[0272] For example, this means that the line capacitance (Cd) should not be driven from "low voltage to high voltage," while the shielding capacitance (Cin_sd) should not be driven from "high voltage to low voltage." This is to induce a charge sharing phenomenon in the load capacitance; if voltages of different polarities are applied simultaneously, the amount of charge increasing or decreasing may be similar, which could result in the charge sharing phenomenon not being generated. High Voltage and Low Voltage are relative concepts. Since the driving voltage has two states, Low Voltage and High Voltage, it should be understood that one of them is Low Voltage and the other is High Voltage. This concept applies to all voltages having the two states of Low Voltage and High Voltage in this specification, and in the case of multiple voltages, the meaning of Low Voltage and High Voltage is that one of the two voltages being compared is low and the other is high.

[0273] 5. Duty of the 1st Stage Driving Voltage and the 2nd Stage Driving Voltage (2 ndThe duty cycles of the Stage Driving Voltages are different. The first stage driving voltage is the driving voltage supplied initially, and it is a voltage with a voltage level difference from the second stage driving voltage supplied second. For example, if the first stage driving voltage is Low Voltage, the second stage driving voltage is High Voltage, and if the first stage driving voltage is High Voltage, the second stage driving voltage is Low Voltage.

[0274] Since the time constant of the CDA signal line installed at a distance from the display device (10) is greater than the time constant of the CDA signal line at a short distance, the time it takes for the signal of the long-distance signal line to become saturated and stabilized is longer than that of the CDA signal line at a short distance. As a result, the forcing time of the second stage driving voltage, High Voltage (Vd2, Vcin2), is longer than that of the first stage driving voltage, Low Voltage (Vd1, Vcin1), supplied at a distance, as in ZONE D of FIG. 14. Also, in the CDA signal line at a short distance, the length of the first stage driving voltage is long and the length of the second stage driving voltage is short, as in ZONE C. However, in the case of the CDA signal line at a short distance, it is more desirable to shorten the Cycle Time as in the embodiment of ZONE A, as this can reduce the sword-fighting time.

[0275] 6. Within a single column, a phase difference may occur in the second stage driving voltage supplied to individual capacitances connected to the same detection signal line according to the length of the detection signal line (or according to the CDA position).

[0276] Referring to FIGS. 12b and FIGS. 14, Vd2 is supplied as a second-stage driving voltage to the line-to-line capacitance (Cd), and Vcin2 is supplied as a second-stage driving voltage to the shielding capacitance (Cin_sd). The magnitude of the line-to-line capacitance (Cd) of a distant CDA signal line may be larger than the magnitude of the shielding capacitance (Cin_sd) of the same CDA signal line. If the second-stage driving voltage is applied to both capacitances at the same time, the voltage of the shielding capacitance (Cin_sd), which has a smaller time constant, may stabilize first, while the line-to-line capacitance, which has a larger time constant, may continue to rise in voltage. According to the principle of superposition, the shielding capacitance (Cin_sd), which reaches a stable state first, begins to discharge after stabilization, and the discharge continues until the voltage of the line-to-line capacitance stabilizes and a signal is detected. Since errors in the signal detected by the detection signal line (202) may occur due to such discharge, it is desirable to apply the driving voltage applied to the shielding capacitance (Cin_sd) at a later time by varying the application timing. ZONE S is a figure explaining this technical concept. After the second voltage Vd2 of the upper figure is applied, the second stage driving voltage Vcin2 is supplied to the shielding capacitance (Cin_sd) after a time of “Φ”.

[0277] Since the magnitude of the inter-line capacitance (Cd) of the CDA signal line in the short distance may be smaller than the shielding capacitance (Cin_sd), the second stage driving voltage of the shielding capacitance may be applied to the signal line in the short distance first, and then the second stage driving voltage may be applied to the inter-line capacitance (Cd).

[0278] Meanwhile, there are other advantages obtained by varying the driving time for each capacitance. Since the driving voltage is applied to the capacitance, a momentary overcurrent flows through the capacitance due to sharp voltages such as the first and third harmonics of the Transit Voltage, such as the initial rising or falling of the driving voltage. As a result, the potential of the driving voltage may change, or components such as switches that apply the driving voltage in the driving unit (420) may be continuously damaged, and if this situation continues, the components may be damaged. A way to avoid this problem is to use different driving units (420) for each capacitance to vary the driving timing.

[0279] 7. The magnitude of the driving voltage supplied to the line capacitance (Cd) and the magnitude of the driving voltage supplied to the shielding capacitance (Cin_sd) may be different from each other.

[0280] FIG. 15 is an embodiment of the present invention in which a driving voltage is applied in a driving unit (420). Referring to FIG. 15, there are voltage generators (VG) VG1 and VG2, and there is a reference voltage (Vref1) supplied to the resistor string of VG1 and a reference voltage (Vref2) supplied to VG2.

[0281] The reference voltages (Vref1 and Vref2) are voltages of precise magnitude generated by the Band Gap Reference (BGR), and the two reference voltages (Vref1 and Vref2) may be equal to or different from each other.

[0282] The driving voltage is generated by the AMP. The magnitude of the AMP output voltage is determined using the reference voltage cited from the resistor string, and current is supplied from the power supply (VDD) supplied to the AMP. The part that generates the driving voltage, consisting of the reference voltage and the AMP, is called the Driving Voltage Generator.

[0284] In a single Voltage Generator, multiple reference voltages and driving voltages are generated. For example, the driving voltages of the present invention, Vd1 / Vd2, or the reference voltages applied to the ADC, such as ADC_top and ADC_btm, are generated in VG1, and Vcin1 / Vcin2 and the DAC reference voltages, such as DAC_top or DAC_btm, can be generated in VG2.

[0285] Voltage drop or component damage caused by the aforementioned peak current is prevented by the driving voltages (Vd1 / Vd2 and Vcin1 / Vcin2) generated separately by the isolated voltage generator.

[0287] As such, in the present invention, driving voltages generated by different voltage generators can be used as driving voltages for different capacitances. For example, Vd1 / Vd2, which is the driving voltage generated by VG1, can be used for the line-to-line capacitance connected to the same point P, and Vcin1 / Vcin2, generated by VG2, can be used for the shielding capacitance.

[0289] Referring to Equation 4 and FIG. 13a, in the case of Dual Driving, Vp2-Vp1 detected by the detection signal line (200) is 4.615V to 4.886V. Generally, OPAMPs are frequently used in the process of processing analog signals and outputting them as digital signals through an ADC. In the case of a general OPAMP that is not a Rail-to-Rail type OPAMP, if Vdd of a single power supply is supplied as the power supply voltage, a sufficient output is not formed to match the supplied power supply voltage. For example, if the power supply of the OPAMP used as a buffer is a 5V single power supply with 0V as the ground, when the input signal of the OPAMP is 5V, the output voltage should be the same 5V; however, 5V is not output, and only about 4.5V is output. Therefore, in this device as well, in the case of an OPAMP using a 5V single power supply, the voltage of 4.615V to 4.886V in FIG. 13a may not be output normally, and only 4.5V may be output.

[0290] Referring to mathematical formula 4, by varying the magnitude of the driving voltage (Vd2-Vd1) or the driving voltage (Vcin2-Vcin1), the value of Vp2-Vp1 during Dual Driving in FIG. 13a can be adjusted so that it is formed at 4.5V or lower, rather than in the range of 4.615~4.886V.

[0291] For example, it can be adjusted such as Vd2-Vd1=5V and Vcin2-Vcin1=3V. To this end, it is possible to design the line capacitance driving voltage so that Vd2=5V and Vd1=0V, and the shielding capacitance driving voltage so that Vcin2=4V and Vcin1=1V. The line capacitance driving voltages Vd2 and Vd1 can be finely adjusted through the resistor string of VG1 as in the embodiment of FIG. 15, and the shielding capacitance driving voltage generated in VG2 can also be adjusted to have various sizes, so it is possible to set the operating point of the OPAMP to a safe region.

[0292] As such, the magnitude of the High Voltage or Low Voltage of the driving voltage supplied to different capacitances in the present invention may be the same or different, and it is possible to control the position of the formed voltage by using different driving voltages. Furthermore, the device of the present invention provides a plurality of voltage references that generate such different driving voltages.

[0293] The embodiment of FIG. 15, which is a device for generating a driving voltage, is an example using a resistor string, and it is possible to generate the driving voltage in a manner different from the method of FIG. 15. For example, all driving voltages can be supplied independently one by one using a regulator, or multiple independent driving voltages can be generated using a BGR (Band Gap Reference), and only their current capacities can be amplified and used. Therefore, the method of generating the driving voltage is not limited to the method using a resistor string as in the embodiment of FIG. 15, and various methods can be used.

[0294] As in the embodiment of FIG. 3, a plurality of capacitances, namely a common electrode capacitance (Ccm), a line-to-line capacitance (Cd), and a shielding capacitance (Cin_sd), are formed or generated in a single CDA (100) and a detection signal line (202) connected thereto. The present invention derives <Equation 4> which detects (Vp2-Vp1) at the detection signal line (202) or at point P, which is an equivalent circuit thereto, by driving the line-to-line capacitance (Cd) and the shielding capacitance (Cin_sd), excluding the common electrode capacitance (Ccm), among these capacitances.

[0295] If the Ccm driving layer (6) of FIG. 6 is driven with driving voltages of different sizes, Vcm1 and Vcm2, another mathematical formula can be created in which a term (Vcm2-Vcm1)*Ccm is added to the numerator of <Equation 4>, and this will contribute to lowering the variation value of Vp2-Vp1 caused by the common electrode capacitance (Ccm) of various sizes generated by the CDA (100) and the signal line connected thereto.

[0296] As described above, when resistance is not taken into account, a single detection signal line (202) can be equivalent to a single point (P) as in FIG. 1 or FIG. 12. One side of the multiple capacitances generated by the detection signal line (202), namely the common electrode capacitance (Ccm), the inter-line capacitance (Cd), and the shielding capacitance (Cin_sd), is connected in parallel to the common electrode capacitance (Ccm). A driving voltage is applied to the other end of the remaining capacitances, excluding the common electrode capacitance (Ccm), to detect Vp1, Vp2, or Vp2-Vp1 at the point P. Additionally, the process of detecting Vp1, Vp2, or Vp2-Vp1 at the point P is also referred to by another term, "detecting the signal."

[0298] Now, with reference to FIG. 12b, an embodiment of the present invention for detecting an object by applying a driving voltage will be described.

[0299] Mathematical formula 4 is This is the case. When qualitatively analyzing Equation 4, Vd1, which determines Vp1 in FIG. 12b, is applied to the line capacitance and Vcin1 is applied to the shielding capacitance. After waiting for a predetermined time until the voltage at point P stabilizes, the voltage at point P at this time is detected by the signal detector (410), and this becomes Vp1. Subsequently, to detect Vp2, Vd2 and Vcin2 are applied, and after waiting for a predetermined time until the signal at point P reaches a saturation state (or target value), the voltage at point P is detected by the signal detector (410). Equation 4 is the difference between Vp1 and Vp2 detected in this way.

[0300] The present invention aims to determine whether an object (20) appears and the coordinate of the object (20) on the display device (10) by the amount of change in object capacitance (Cobj) when an object (20) is positioned on the upper surface of the display device (10).

[0301] Referring to FIG. 4, when an object (20) is positioned on the upper surface of the CDA (100), an object capacitance (Cobj) is formed between the CDA (100) and the object (20), and the magnitude of the object capacitance is Cobj = ed / S. Here, "d" is the distance between the object (20) and the CDA (100), and "S" is the opposing area between the object (20) and the CDA (100).

[0302] The elements determining the gap "d" are a protective layer (7) composed of protective glass or protective film between the CDA (100) and the object (20), a transparent adhesive (not shown) such as an adhesive bonding the CDA (100) and the protective layer (7), and an air layer when the object (20) does not touch the upper surface of the protective layer (7).

[0303] The size of the object capacitance (Cobj) is determined by the composite capacitance (series connection of Cair, Cgls, and Cadh) formed based on the thickness of the air layer and the permittivity (e) of the air layer (Cair), the thickness of the protective layer and the permittivity (e) of the protective layer element (Cgls), and the thickness of the transparent adhesive and the permittivity (e) of the transparent adhesive element (Cadh), based on the opposing area of ​​the object (20) and the CDA (100).

[0304] In the case of a general embodiment, when an object (20) having an area of ​​4 mm x 4 mm comes into contact with a protective glass with a thickness of 0.5 mm, which is a protective layer (7) on the upper surface of the CDA (100), a capacitance of 0.5 pF to 1 pF is formed between the CAD (100) and the object (20) according to calculation.

[0305] The object capacitance (Cobj) formed on the upper surface of the CDA (100) can be equivalent to having one side connected to point P, which is equivalent to the CDA signal line (200), and the other side connected to Vobj, which is the potential (Voltage Level) of the object. If the object (20) is a human finger, the potential (Vobj) of the object (20) is 0V, which is ground, and in the case of a pen, it is the output voltage of the pen.

[0306] FIG. 12b is an embodiment of the present invention for applying a driving voltage to the inter-line capacitance (Cd) and shielding capacitance (Cin_sd), excluding the common electrode capacitance (Ccm), and for detecting a voltage in the detection signal line (200) when the object capacitance (Cobj) generated by the appearance of an object is added. Referring to FIG. 12b and <Equation 4>, when the object (20) is a human finger, the potential (Vobj) of the object (20) is constant, so Equation 4 is derived as Equation 5 by the principle of superposition.

[0307]

[0308] Since the present invention determines the presence of an object (20) based on the magnitude of the object capacitance (Cobj), it is possible to determine the presence or absence of the object (20) or the contact area by knowing the difference between <Equation 4>, which is the voltage at point P when the object (20) is absent, and <Equation 5>, which is the voltage at point P when the object (20) is present. Equation 6 is defined as Equation 4 - Equation 5 and is as follows.

[0309]

[0310] Referring to Equation 6, the difference between Equation 4 and Equation 5 is the presence or absence of the object capacitance (Cobj) in the denominator term. Therefore, by detecting the change in Equation 4 based on its value, it is possible to detect the magnitude of the object capacitance (Cobj) as voltage.

[0311] If the signal detected by Equation 4 when there is no object is called the "first detection signal" and the signal detected by Equation 5 when there is an object is called the "second detection signal," it is possible to detect the magnitude of the object capacitance (Cobj) based on the difference between the first detection signal and the second detection signal.

[0312] In order to know the amount of change of the "second detection signal" relative to the "first detection signal," the reference "first detection signal" must be stored and retrieved, and the difference from the regularly detected second signal must be identified, so the first detection signal must be recorded and stored in memory.

[0314] FIGS. 16a to 16d illustrate an embodiment of the present invention regarding the use of a differential amplifier, wherein the differential amplifier is included in a signal detection unit (410).

[0315] A differential amplifier is a device that amplifies the difference between the voltage input to the positive input terminal and the voltage input to the negative input terminal, and its amplification rate is determined by the ratio between the feedback resistor and the resistors connected to the positive input terminal. (In this embodiment, the connection of the resistors determining the amplification rate has been omitted.)

[0316] FIG. 16a is an embodiment of the present invention relating to a process for extracting a duplicated DAC code identical to a first detection signal.

[0317] A Digital-to-Analog Converter (DAC) that outputs an analog voltage is connected to the Positive input terminal, and a "first detection signal" is connected to the Negative input terminal. Since the first detection signal is detected by the detection signal line (200), the detection signal line is connected to the Negative input terminal of the differential amplifier.

[0318] A DAC is a device that outputs an analog voltage when a digital code is given. Since the DAC output is connected to the positive input terminal of a differential amplifier, two analog voltages are connected to the differential amplifier, and the differential amplifier amplifies the difference between the two voltages at an amplification rate based on a preset resistance ratio.

[0319] Vo, the output voltage of the differential amplifier, is the voltage according to Equation 7 below.

[0320]

[0321] DAC_ini is the initial output value of the DAC and is an arbitrary value. Alternatively, it may be a duplicated DAC value used previously. As the characteristics of the circuit elements of the semiconductor IC (400) change due to changes in temperature, the first detection signal detected by the detection signal line changes frequently, and the duplicated DAC value that tracks the first detection signal must also change frequently. Therefore, when an old DAC value stored in memory is called to correct the changed DAC and a corrected new DAC value is obtained, the DAC value stored in memory can be used for the purpose of DAC_ini. Since the new DAC value does not differ significantly from the old DAC value, the new DAC can be extracted quickly. However, if power is applied to the device and there is no DAC value stored in memory, an arbitrary DAC value must be set as DAC_ini, and the value of DAC_ini must be changed while monitoring the output of the differential amplifier. Gain is the amplification rate of the differential amplifier.

[0322] In Equation 7, if the magnitude of the voltage of DAC_ini is equal to the voltage of the first detection signal, Vo becomes 0V (Zero Volt). That is, when the object does not appear, a driving voltage is applied to the inter-line capacitance (Cd) and shielding capacitance (Cin_sd) in Fig. 12b based on Equation 4, and the value of DAC_ini is adjusted so that the Vo value detected by the differential amplifier becomes 0V; at this point, the DAC_ini value is the same as the first detection signal, and the extracted DAC Code is denoted as DAC_copy, which is the copied value (Copied Value or Same Value) of the first detection signal. (DAC_copy may also refer to the copied voltage output from the DAC.)

[0323] In the same way, for all CDAs (100), a DAC code with a duplicated magnitude of the first detection signal is extracted and stored in the memory of the semiconductor IC (400) for each CDA.

[0324] FIG. 17 is an embodiment of the present invention relating to a memory for storing a DAC.

[0325] According to the above <Mathematical Formula 7>, the first detection signal detected in all CDAs (100) is stored in memory as a DAC Code, and DAC_rxcy stored in memory is a duplicated DAC code detected in the CDA (100) located in row x and column y of FIG. 3. For example, DAC_r2C1 is the same DAC code as the first detection signal detected in the A1 CDA (100) of FIG. 3.

[0326] The first detection signal stored in the form of a DAC duplicated in memory is called whenever the second detection signal of the corresponding CDA (100) is detected and connected to the Positive or Negative Input terminal of the differential amplifier according to the embodiments of FIG. 16b to 16d, or is used in the embodiment of FIG. 16a to obtain a corrected DAC value.

[0328] FIG. 16b is an embodiment of the present invention regarding a process for detecting the output signal V1 of a differential amplifier using a duplicated DAC.

[0329] A detection signal line (202) is connected to the Negative Input terminal of the differential amplifier, and a second detection signal based on <Equation 5> is formed by the appearance of an object, and is connected to the Positive Input terminal of the duplicated DAC voltage of the first detection signal.

[0330] Due to this connection method, the output of the differential amplifier according to the embodiment of FIG. 16b outputs a voltage V1 that is the same as Equation 6, Equation 4 - Equation 5, or (first detection signal - second detection signal). In the embodiment of FIG. 16b, the transfer function forming the output voltage V1 of the differential amplifier is the following Equation 8.

[0331]

[0332] Referring to Equation 8, V1 is the value output from the differential amplifier based on the difference between the first detection signal, DAC_copy, and the second detection signal. Since the second detection signal varies according to the magnitude of the object capacitance (Cobj), the differential amplifier output V1 is a voltage whose magnitude changes according to the magnitude of the object capacitance (Cobj), where only the magnitude of the object capacitance (Cobj) acts as a variable.

[0333] FIG. 16c is an embodiment of the present invention regarding a method of connecting multiple signal lines to a single differential amplifier.

[0334] An embodiment of the present invention uses a DAC to store a first detection signal as digital data in memory. The DAC is sequentially called from memory, and the output voltage of the called DAC is connected to one input terminal of the differential amplifier, and the detection signal line (202) of the CDA, which is the master of the duplicated DAC, is sequentially connected to the other input terminal of the differential amplifier so that the voltage difference is output in sequence. In an embodiment of the present invention, two or more DAC devices may be used, but since using a large number of DACs increases the area of ​​the semiconductor IC (400), complicates the design and configuration of the logic circuit controlling the DAC, and increases current consumption, it is preferable to use one DAC.

[0335] In addition, the present invention may use two or more ADC devices, but since using a large number of ADCs increases the area of ​​the semiconductor IC (400), complicates the design and configuration of the logic circuit controlling the ADC, and increases current consumption, it is preferable to use only one ADC, and the ADC is connected to the output terminal of the differential amplifier and performs processing to convert the output voltage V1 into a digital code using a time-sharing method.

[0337] There are the following three methods for configuring a differential amplifier to use a DAC and ADC in a time-division method.

[0338] * Example of the first method regarding the configuration of a differential amplifier using a DAC and an ADC

[0339] A method using one differential amplifier for each detection signal line (200), and a differential amplifier is required for each column included in one group.

[0340] Since the DAC outputs only one voltage corresponding to a single input code, the DAC is sequentially connected to differential amplifiers installed according to the number of columns included in a group, such as being reconnected to the next differential amplifier after processing is completed in one differential amplifier.

[0341] The ADC shifts positions in the same way as the DAC and is sequentially connected to multiple differential amplifiers in the same way as the DAC.

[0342] When V1 is output sequentially from multiple differential amplifiers, the voltage V1 is converted into a digital value by processing of the ADC and temporarily stored in memory, and the necessary information is extracted by the CPU (460).

[0343] Once the processing of the first column group is completed, processing proceeds in the second column group; if a third or fourth group exists, processing for all groups proceeds sequentially according to a predefined order.

[0344] In the case of the first embodiment of the method, since a differential amplifier is connected to each detection signal line (202), there is an advantage that the signal formed in the detection signal line is stable, but there are disadvantages that the number of differential amplifiers increases, the DAC and ADC must be connected to the input or output of all differential amplifiers, the layout becomes complex, the current consumption increases due to the increase in the number of differential amplifiers, and the area of ​​the semiconductor IC (400) increases.

[0346] * Example of a second method for configuring a differential amplifier using a DAC and an ADC

[0347] An embodiment of the second method uses one differential amplifier for each column group and connects all detection signal lines of the column group to a single differential amplifier. Since the number of differential amplifiers is only required for the number of groups, there are advantages in terms of current consumption and layout as the number of differential amplifiers is reduced compared to the embodiment of the first method.

[0348] The AMP input signal line selection unit (450-2) of FIG. 16c is a switch that selects one of the detection signal lines input to the differential amplifier. Since it is assumed that there are 10 columns in one group, 10 detection signal lines are input to the differential amplifier, and only one of the switches of the AMP input signal line selection unit (450-2) is selectively turned on by the control of the CPU (460) or the Logic unit of the semiconductor IC (400). With the remaining switches other than the turned-on switch turned off, when the duplicated DAC of the CDA (100) connected to the turned-on switch is called from memory and connected to the differential amplifier, the difference between the two voltages is output, and processing is performed by the ADC that operates in pair with the DAC.

[0350] * Example of the third method regarding the configuration of a DAC, ADC, and differential amplifier

[0351] An embodiment of the third method is a method in which the column-specific detection signal lines output from each group share a single differential amplifier, and is an embodiment in which only a single differential amplifier is used.

[0352] A Loader (450) is installed for each column group, and the signal lines output from each Loader installed in multiple groups are connected to have the same output components so that they operate as a single Loader (450), and by activating only the Loader (450) of the column group that requires processing, it is possible to process all CDAs with a single differential amplifier.

[0353] When a Loader (450) is installed in a display device and an AMP input signal detection unit (430-2) and a differential amplifier (430-1) are installed in a semiconductor IC (400), the output of the Loader is input to the AMP input signal detection unit (430-2) through a connecting member (300) connected to the display device (10). Since the Loader (450) receives and outputs detection signal lines (202) equal to the number of columns constituting a column group, the number of detection signal lines transmitted from the output of the Loader (300) to the AMP input input detection unit through the connecting member (300) is at least equal to the number of columns included in the column group. Generally, there are about 10 columns in the column group and about 10 signal lines for the output and driving voltage of the semiconductor IC (400) input to the decoder (436) for the detection / driving switch group (437). Therefore, the number of pads of the joint portion (301) of the connecting member (300) that connects the semiconductor IC (400) and the display device (10) through the connecting member (300) is about 20. As a result, the width of the connecting member (300) is also narrowed, so the form of the module configured by installing the device on the display device (10) is simplified, and it is possible to simply install the joint portion (301) on the left or right corner portion where there is no output of the Source IC of the display device.

[0355] FIG. 18a is an embodiment of the present invention that reduces the number of detection signal lines output from multiple Loaders (450-1, 450-2) in order to use a single differential amplifier, and FIG. 18b is an embodiment of the apparatus of the present invention regarding signal flow between components used in FIG. 18a. Hereinafter, with reference to FIG. 18a and FIG. 18b, an embodiment using only one differential amplifier (430-1) and signal flow between various components will be described.

[0356] In the embodiment of FIG. 18-1, 20 columns were separated into two groups, a left group and a right group, and the group containing 10 columns from left COL1 to COL10 was called Group 1, and the group containing 10 columns from right COL11 to COL20 was called Group 2.

[0357] In one embodiment of FIG. 18a, 25 CDAs (100), ranging from far-distance CDA 1 to near-distance CDA 25, and 25 CDA signal lines (200) connected to each CDA are installed in one column. In the present invention, among the 25 CDAs included in one column, CDAs are selected sequentially according to a pre-set order, and the object capacitance (Cobj) at the selected CDA (100) is detected. The position (number) of the detection CDA (100) selected in each column may differ from column to column, but preferably, the position of the detection CDA (100) selected in each column is the same, and as a result, all CDAs (100) in the same row in one group operate as detection CDAs.

[0358] The present invention selects a detection signal line (202) connected to a detection CDA and a plurality of driving signal lines (201) adjacent to the detection signal line, and detects an object in the detection CDA and applies a driving voltage to the driving signal lines.

[0359] When the nth detection signal line is selected, one pair or multiple pairs of driving signal lines can be selected. When the nth detection signal line and a pair of driving signal lines are selected, a pair of driving signal lines [(n-1), (n+1)] is selected.

[0360] When the nth CDA in a column is selected as the detection CDA, m pairs of driving signal lines can be selected. That is, in "CDA(n, ±m), 1, 2, m, where m is a positive integer," CDAn is the row number of the detection signal line, the row number of the driving signal line is (CDA(n±m), m=1 to m), and m is the number of pairs of driving signal lines. For example, if the detection signal line and driving signal line in a column are indicated as (10, ±3), the CDA in the 10th row is the detection CDA, three pairs of detection signal lines are selected, and the row numbers of the three pairs of detection signal lines are (9,11) / (8,12) / (7,13).

[0361] In the apparatus of the present invention having multiple groups, when the processing of all CDAs included in the nth row of the first group is completed, all CDAs included in the same nth row of the remaining groups are selected and processing is performed. In another embodiment, CDAs in rows at different locations may be processed by a pre-set method. In one embodiment, in the apparatus of the present invention having four groups, the first group may be processed in the 10th row, the second group may be processed in the first row, the third group may be processed in the 5th row, and the fourth group may be processed in the first row.

[0362] The embodiment of FIG. 18a is divided into two groups, and it is assumed that the processing of the left group is followed by the processing of the right group, and that the processing is performed in the CDA (100) located in the same row of all columns.

[0363] Referring to FIG. 18b, once the processing of the n-th row is completed, the processing of the (n+1)-th row proceeds, followed by the processing of the (n+2)-th row (not shown), and so on, up to the last row or a pre-set row. Although processing can be performed simultaneously in multiple groups, there are issues such as inrush current during operation, discharge in the detection signal line, or increased capacity of the ADC or DAC; therefore, preferably, processing should be performed in only one group, such as when processing is completed in one group and then processing proceeds in the next group. In the embodiment of FIG. 18, it is assumed that processing proceeds in Group 2 after processing proceeds in Group 1.

[0365] There may be various ways to select the detected CDA (102) in a single column. For example, only the CDAs in odd rows may be processed, or only the CDAs in even rows may be processed. Alternatively, the row number of the CDA may be determined using a mathematical formula such as 2C+1 (C=0, 1, 2, ... positive integers), such as skipping two CDAs based on the selected row's CDA and processing the third CDA, or it may be set as 3C+1 (C=0, 1, 2, ... positive integers) in the same way. Scanning only a portion of the CDA instead of scanning the entire CDA is intended to determine only the presence or absence of an object, and since the scanning time is reduced, the power consumption is reduced. If an object is detected, the entire CDA is scanned to obtain the precise location coordinates of the object.

[0367] In SG1 and SG2 of FIG. 18, the numbers represent the group numbers, and SG1,1-1 means switch group 1 of column 1 of group 1. In FIG. 18, three switch groups are installed for each column. This is the case for "(n, ±m), m=1", where three switch groups are required because a pair of detection signal lines is selected centered on the nth detection signal line. If the case is "(n , ±m), m=1, 2", five switch groups would be required for each column.

[0368] One of the multiple switch groups is a detection switch group (437-1) that selects a detection signal line, and the rest are driving switch groups (437-2). In the embodiment of FIG. 18-1, the central switch group is assumed to be the detection switch group (437-1), and the left and right switch groups are assumed to be driving switch groups (437-2).

[0369] All CDAs included in one column are input to all switch groups of that column and one is output for each switch group. In the embodiment of FIG. 18a, 25 CDAs (100) and 25 CDA signal lines (200) included in one column are all input to three switch groups.

[0370] A CDA signal line (200) is connected to each input terminal of the internal switch (438), and one internal switch (438) is turned on for each switch group, so that one CDA signal line is output for each switch group (437).

[0371] When the CDA of the present invention is installed in the display device (10) and the detection / drive switch group (437) is also installed in the display device, it is preferable that the internal switch (438) uses the same element as the switching element that outputs pixel data of the display device (10). The switching element that outputs pixel data of the display device (10) is turned on or turned off by an on / off control signal output from the Gate Drive IC of the display device (10), and is an element that serves to transmit pixel information output from the Source Drive IC of the display device (10) to the pixel, and the internal switch (438) also performs the same function.

[0372] Therefore, in the process of manufacturing a switching element for a pixel of a display device (10), if an internal switch (438) included in the switch group (437) of the present invention is manufactured using the same mask, it is possible to manufacture the internal switch (438) without a separate process.

[0373] In addition, when the internal switch (438) is the same as the switching element for the pixel of the display device (10), the turn-on and turn-off voltages used for the internal switch (438) can be the turn-on and turn-off voltages output from the Gate Drive IC of the display device. Therefore, if the output of the decoder (436) of the present invention is set to be the same as the output voltage of the Gate Drive IC, it is possible to stably perform the turn-on or turn-off operation of the internal switch (438).

[0374] When the switch group (437) and the decoder (436) are installed in the display device, it is preferable that the level of the signal output from the decoder be the same as the High and Low voltages output from the Gate Drive IC of the display device (10). In addition, when the Gate Drive IC is embedded in the display device (10), it is preferable that the switching element used in the decoder (436) be the same switching element used in the Gate Drive IC, and that it be manufactured by the same process as the manufacturing process of the switching element of the Gate Drive IC. Furthermore, in order for the decoder (436) to output a voltage identical to the High and Low voltages output from the Gate Drive IC of the display device (10), the decoder (436) must be supplied with a voltage identical to the High and Low voltages used by the Gate Drive IC of the display device (10). In one embodiment, when the device responsible for the output of the decoder is a CMOS, the High voltage used by the Gate Drive IC is connected to the Source terminal of the CMOS, and the Low voltage used by the Gate Drive IC is applied to the Drain terminal of the CMOS.

[0375] Generally, the above-mentioned Gate Drive IC used in the display device (10) outputs only one of hundreds of outputs as a turn-on voltage, and the remaining outputs are turn-off voltages. Similarly, the decoder (436) of the present invention outputs only one of dozens of outputs as a turn-on voltage that turns on the internal switch (438), and the rest are turn-off voltages of the internal switch (438). In the embodiment of FIG. 18a, since 25 CDAs (100) are installed in one column, at least 25 outputs of the decoder are required, and among the 25 (G0~G24) outputs of the decoder (436), the output line number (Output Line Address) where the turn-on voltage is output is indicated as "Gn" in the Decoder out of FIG. 18b. Since the Decoder out is "Gn," it means that the voltage output from the nth line among the 25 decoder outputs is the turn-on voltage. The turn-on voltage of the switching element (438) composed of NMOS is High Voltage, but the turn-on voltage of the switching element (438) composed of PMOS is Low Voltage. Therefore, one turn-on voltage output from the decoder (436) can be High Voltage or Low Voltage.

[0376] The input control signal that controls the output of the decoder (436) is output from the CPU (460) or the logic section of the semiconductor IC (400) and input to the decoder (436). If the decoder (436) is installed in the display device (10), the decoder (436) may not be controlled by the High and Low Levels output from the semiconductor IC (400). Therefore, the Level output from the semiconductor IC (400) is changed to the High and Low Levels of the switching element used in the display device (10) by the Level Shifter (439) installed inside the display device (10). By the Level Shifter (439), the High voltage output from the semiconductor IC (400) is changed to the High Level of the switching element used in the display device (10), and the Low Level output of the semiconductor IC (400) is changed to the Low Level of the switching element of the display device. For example, the 0V Low voltage output from the semiconductor IC (400) is changed to -6V, which is the Low Level voltage of the switching element used in the display device (10), by the Level Shifter (439), and the 3V High Level voltage output from the semiconductor IC (400) is changed to 10V, which is the High Level voltage of the switching element used in the display device (10).

[0377] The switch group (437) of FIG. 18a requires 25 decoder outputs, so 5 decoder input control signals are required, and the number of signals output from the decoder is 2 n The number of input control signals n is determined so as not to exceed .

[0378] Meanwhile, the input control signal input to the decoder (436) can be replaced with two signals. Generally, a circuit of the shift register method is used in the gate drive IC of the display device (10), and the shift register is a device that outputs only one of the multiple output signals based on two input signals as High. The shift register consists of two signal lines, such as Start Clock and Clock, and when a High signal is given to the Start Clock, the first output signal (G0) of the shift register is output as High at the time when the clock changes from Low to High, which continuously repeats High and Low, and thereafter, even if the "Start Clock" remains in a Low state, the output of the shift register is sequentially output as High whenever the "Clock" becomes High. As a result, among the outputs from G0 to Gn of the shift register, G0 becomes High first, then the G1 output becomes High, and then High is sequentially output from G2 to the last signal.

[0379] In one embodiment of such a Shift Register, the Shift Register is used as a Gate Drive element of a display device (10), and when the number of Gate Lines of the display device (10) is 256, a T-Con outside the display device (10) sets the Start Clock to a High state, and when 256 clocks are applied, only one output among the 256 Shift Register outputs from G0 to G255 sequentially outputs a High signal. If the switch turn-on signal used in the display device is a Low signal, it is possible to change the state by adding an Inverter to all signals output from the Gate IC.

[0380] When the decoder (436) is installed in the display device, the output of the decoder (436) can be applied in the same manner as the embodiment of the shift register of the gate drive IC of the display device (10). Therefore, the decoder (426) is designed with the structure of a shift register and has output signal lines equal to the number of CDAs included in the column and the two input control signals, Start Clock and Clock. Additionally, one of the output signal lines is sequentially output with a high voltage by the logic of the Start Clock and Clock. The gate drive IC is installed on the left or right side of the display device (10) and may be composed of a switching element used in an LCD or OLED. In this case, the decoder circuit may have the same configuration as the shift register circuit applied to the gate drive IC of the display device, and the decoder circuit can be manufactured using the same mask and the same process as when the gate drive IC of the display device is manufactured.

[0382] In the embodiment of FIG. 18, when the output of the detection switch group (437-1) is CDAn, that is, when the nth CDA is selected in the detection switch group (437-1), it is assumed that the driving signal line selected in the driving switch group 3 is the driving signal line corresponding to the CDA(n+1)th, and the driving signal line selected in the driving switch group 1 is the driving signal line corresponding to the CDA(n-1)th, just as in the embodiment of FIG. 7d. Additionally, in the embodiments of FIG. 18a and FIG. 18b, it is assumed that the Row processed in Group 1 is processed in the same way in Group 2.

[0383] The detection signal line (210) of column 1 selected by the detection switch group (437-1) by the on / off control signal of the decoder (436) is input to the first group loader (450-1), and the column detection signal lines selected one by one from columns 2 (COL2) to 10 (COL10) are also all input to the first group loader (450-1). Likewise in Group 2, the detection signal lines selected one by one from columns 11 (COL11) to 20 (COL20) by the detection switch group (437-1) are input to the second group loader (450-2).

[0384] The Loader (450) is a device of the present invention that has the characteristic of outputting the input signal as is, and has the characteristic that all input signals are output simultaneously when the control signal called "LD" is in the Enable state. The Loader (450) is composed of a combination of switches and has the characteristic of outputting the magnitude of the input signal without loss. Since this characteristic is the same as that of the switching device of the LCD's TFT or OLED, when the Loader is installed in a display device, it is desirable to use the same switch used in the Loader (450) as the switch used in the display device. If the same mask is used in the manufacturing process of the switch of the display device, the same characteristics as the display device can be secured, and the effect of reducing manufacturing costs is achieved.

[0385] Additionally, when the Loader (450) is installed in the display device, the "LD" signal, which is a control signal of the Loader (450) given by the semiconductor IC (400), is also changed in the Level Shifter (439) to suit the on / off characteristics of the switching element used in the Loader (450) and connected to the "LD" terminal of the Loader (450). When the switch used in the Loader (450) and the switch used in the decoder are the same switch, the magnitudes of the Hi and Low Levels of the "LD" and Decoder (436) input signals that have passed through the Level Shifter are the same.

[0386] The Loader (450) of FIG. 18a has 10 output elements, ranging from out1 to out10. An embodiment of the present invention is to connect identical output elements output from the Loader to each other. Referring to the embodiment of FIG. 18a, out1 of the first group Loader (450-1) is connected to out1 of the second group Loader (450-2), and out2 of the first group Loader (450-1) is connected to out2 of the second group Loader (450-2), and so on, the output elements of the first group Loader and the output elements of the second group Loader are connected to each other. When the output components of the Loader (450) are connected to each other, the control signal "LD" of the Loader (450) is selectively enabled only one of the multiple Loaders, so the signal is output only from the enabled Loader (450) and the switches of the other Loaders (450) are all turned off, so there is no mutual interference between the detection signal lines.

[0388] Referring to the embodiments of FIGS. 18a and 18b, the CDA (100) of the same row in Group 1 and Group 2 is selected by the output of the same decoder (436) and input to the first group loader (450-1) and the second group loader (450-2). However, initially, only "LD1" of the first group loader (450-1) is in the enabled state, so all input signals of the first group loader (450-1) are output. But since "LD2" of the second group loader (450-2) is in the disabled state, the input signals of the second group loader (450-2) are not output, so the signals of the same output components of the second group loader (450-2) do not affect the first group loader (450-1). When processing of Group 1 is completed and processing proceeds in Group 2, only the signal of the second group loader (450-2) must be output. Therefore, "LD1" is in a disabled state and "LD2" is in an enabled state, and since only the signal of Group 2 is output through the second group loader (450-2), it is possible to proceed with processing of Group 2. The output signals of the first group loader (450-1) and the second group loader (45-2) must not interfere with each other. Even if there are more group loaders (450) than this, only the "LD" which is the control signal of the group loader that is being processed must be in an enabled state, and the "LD" which controls the output of the group loader that is not being processed must not be in an enabled state at the same time.

[0390] Multiple driving signal lines selected, such as detection signal lines in one column, are interconnected to apply the same driving voltage, and for the simplification of the driving unit (420), they are all connected to driving signal lines of other columns within the same group and connected to the driving unit (420). The column 1 driving signal line (210-1) of FIG. 18a is a combination of two driving signal lines output from driving switch group 1 and driving switch group 3, and all of these driving signal lines of group 1 are connected to the driving unit (420) as a single driving signal line named G1_Vd, and all of the driving signal lines of group 2 are connected to the driving unit (420) as a single driving signal line named G2_Vd.

[0391] For the processing of Group 1, it is desirable to apply a driving voltage only to Group 1, and not to apply a driving voltage to Group 2, which is a group where processing does not proceed. Additionally, it is desirable to reduce current consumption by setting the driving voltage of the group that does not proceed to a High Impedance (Hi-z) state, and either only the first stage driving voltage or only the second stage driving voltage may be applied. Accordingly, the driving unit has three states: High voltage (Vd2), Low voltage (Vd1), and Hi-z.

[0392] In order to distinguish between Water or Coin and fingers, a driving voltage may also be applied to the driving signal line of a group where processing is not performed. In such cases, the driving voltage of Group 1 (G1_Vd) and the driving voltage of Group 2 (G2_Vd) in FIG. 18b have the same type of driving voltage, and G1_Vd and G2_Vd may be interconnected within the driving unit (420).

[0393] Referring to FIG. 18b, at the processing time of Group 1, a first stage driving voltage Vd1 is applied through G1_Vd, which applies the driving voltage of Group 1 along with the reset voltage described later, and after a time for applying a predetermined reset voltage has elapsed, the reset voltage is cut off, and subsequently, a second stage driving voltage Vd2 is applied. At the processing time of Group 1, the driving voltage of Group 2 maintains a Hi-z state, but a driving voltage of the same form as the driving voltage of Group 1 may be applied, or Vd1 may be applied, or Vd2 may be applied.

[0394] When the processing of Group 1 is completed, the first stage driving voltage Vd1 and the second stage driving voltage Vd2 are applied through G2_Vd of the driving unit (420) that applies the driving voltage to Group 2, which is the same as Group 1.

[0396] In the embodiment of FIG. 18b, after a predetermined time has elapsed following the application of a High voltage, which is the second stage driving voltage, the AMP input signal line selection unit (430-2) outputs the input signals one by one in a predetermined order. The "select" controlling the AMP input signal line selection unit (430-2) is a signal for selecting and outputting one of the 10 input signals, and selects one of the 10 input signals according to the logic of the 4 signal lines. In the embodiment of FIG. 18b, a HEX Code is input, and the output signal is determined according to the input HEX Code. For example, if the HEX Code of the input Select signal is 0H, the signal of the first input signal line, "in1", is output, and if the HEX Code of the select signal is 9H, in10 is selected and the signal of in10 is output. Referring to FIG. 18b, the “select” controlling the AMP input signal line selection unit (430-2) is given sequentially from 0H to 9H, and the AMP input signal line selection unit responds to this and sequentially outputs 10 signals from in1 to in10.

[0397] The signal output from the AMP input signal line selection unit (430-2) passes through "Block 1". Block 1 may be a low-pass filter (LPF), an analog buffer, an amplifier, a switch, etc., and may also be composed of various circuits by a combination of OPAMP, resistors, capacitances, CMOS, etc. Alternatively, the output of the AMP input signal line selection unit may be directly connected to the input of a differential amplifier without passing through Block 1.

[0398] In the embodiment of FIG. 18b, the given code, such as 0H or 1H of the DAC, is the address of a duplicated DAC stored in memory, and when the DAC code stored at the corresponding address is applied to the DAC connected to the differential amplifier, the DAC converts it into an analog voltage, and the voltage difference with the detection signal line is amplified by the differential amplifier and output.

[0399] The signal output from the differential amplifier passes through Block 2, and Block 2 is a circuit composed of components such as filters, amplifiers, buffers, OPAMPs, or CMOS, just like Block 1, and the signal passing through Block 2 is processed by the ADC and stored in memory.

[0400] When processing for 10 detection signal lines by the ADC is completed, the first group loader (450-1) is disabled by LD1, and an enable signal is given to LD2 of the second group loader (450-1) for processing of group 2.

[0401] Subsequently, the signals from column 11 to column 20 of group 2 are detected through the same process as group 1, but since the location of the CDA is different, the address of the DAC stored in memory is different. In the embodiment of FIG. 18b, for convenience, the address of the DAC corresponding to the nth CDA of the 11th column is set as AH (11th), and the last DAC address is set as 13H, which is the 20th.

[0402] For each column, in order for processing to proceed for the second CDA, CDA(n+1), the output G(n+1) of the Decoder (436) is the output voltage in the turn-on state, and as a result, CDA(n+1) is selected in the detection switch group (437-1) and CDAn and CDA(n+2) are selected in the driving switch group.

[0403] Afterwards, a driving voltage is applied to the driving signal line, and the LD signal of the Loader (450) is controlled for each group to be processed. The output signal is sequentially selected in the AMP input signal line selection unit (430-2), and the duplicated DAC is also sequentially called from memory. The difference between the first signal and the second signal is detected using a differential amplifier, and the result is converted into a digital code through an ADC and stored in memory. This process is repeated continuously.

[0404] Meanwhile, referring again to an embodiment of FIG. 18a, the output of the decoder (436) supplied to each column is laid out in the horizontal direction, and the connection lines for each output component of the first group loader (450-1) and the second group loader (450-2) are also laid out in the horizontal direction. In addition, the signal line output from the loader (450) and connected to the AMP input signal line selection unit (430-2) is laid out in the vertical direction.

[0405] When components of this device, such as a decoder (436), a switch group (437), a loader (450), a level shifter (439), or an AMP input signal line selection unit (430-2), are installed embedded in the display device (10), wiring must be done carefully so that interference with the wiring for pixel data and gate signal lines of the display device (10) does not occur.

[0406] The signal line for transmitting pixel data of the display device (10) is wired mainly in the longitudinal direction using a source metal, and the gate signal line is mostly laid out in the transverse direction and uses a gate metal of a different layer from the source metal to avoid interference with the pixel data signal line using the source metal.

[0407] In the present invention, the signal line laid out in the transverse direction uses the metal used for the Gate signal line, preferably Gate Metal, and the signal line laid out in the longitudinal direction uses the same layout as the longitudinal layout, which is the pixel data transmission signal line, preferably Source Metal. At the point where the longitudinal wiring and the transverse wiring meet, the Source Metal and the Gate Metal are connected using a Short Point.

[0408] In accordance with these principles, the output of the decoder (436) transmitted to all switch groups uses Gate metal to avoid interference with pixel signal lines, and the connection signal lines for each output component of the Loader also use transverse Gate metal to avoid interference with pixel signal lines. In addition, it is preferable that multiple signal lines output from the Loader and input to the AMP input signal line selection unit (430-2) use longitudinal metal or Source Metal to avoid interference with the Gate Metal of the transverse pixel switching element.

[0409] Meanwhile, when the AMP input signal line selection unit (430-2) is located in the display device (10), since there is only one detection signal line input to the differential amplifier (430-1) of the semiconductor IC (400), the signal line input pin (401) is significantly reduced, and the size of the semiconductor IC (400) is further reduced, and at least it does not fall within the Pad Limit where the size of the semiconductor IC is determined by the number of pads. In addition, the problem caused by the deviation of shielding capacitance (Cin_sd) due to the difference in length of the detection signal lines described above is resolved, and wiring becomes simpler, and the performance of the device is further improved.

[0410] In this way, all components of the path from the CDA (100) to the AMP input signal line detection unit (430-2) are installed in the display device (10) to improve the performance of the device, and these components are a switch group (437), a Loader (450), an AMP input signal line selection unit (430-2), a Level Shifter (439), and a Decoder (436) connected to the CDA signal line installed in the display device (10).

[0411] These elements are installed on one side of the display device (10), and can be positioned in the corner of the display device where there is no output line of the Source Drive IC of the display device, or between the Source signal lines so as not to overlap with the Source signal lines. In addition, they can be installed in an area where there are no Gate signal lines to avoid interference with the Gate signal lines output from the Gate IC.

[0412] In addition, it may be installed in the BM (Black Matrix) area where the Source data Line or Gate driving Line is located in the area where the screen of the display device is displayed, or it may be installed in the non-visible area of ​​the screen where the image is not displayed.

[0414] Some display devices (10) fold the screen using an "In Folding" method where the screen is not visible, or an "Out Folding" method where the screen is folded once so that it comes out. Some display devices are commercialized as Z-type displays that combine the In Folding and Out Folding methods, where the screen is folded twice to make it look like three displays are stacked, and when viewing the entire screen, the folded screen is unfolded to be viewed as one.

[0415] When the screen is folded twice in a Z-shape, utilizing both in-folding and out-folding methods, the outer display of the folded screen functions as a sub-display, serving roles such as displaying the time or showing the caller's information when a call comes in.

[0416] When creating an object detection device for a display device that folds multiple times using the device of the present invention, if the display device (10) is in a folded state and a part of the folded display device (10) is used as a sub-display, the Loader (450) is configured to activate only the Loader of the group in which the CDA (100) installed in the display device used as a sub-display is installed, and by applying a driving voltage only to the CDA (100) used in the display device (10) used as a sub-display to detect an object signal, the current consumption is reduced because only the CDA (100) and a part of the component operate. A signal indicating that the screen is folded is received from an external Host CPU, and an object is detected only in the sub-display when the screen is folded.

[0418] Meanwhile, in the embodiment of FIG. 18a, during the process of sequentially connecting the detection signal lines selected by the AMP input signal line selection unit (430-2) to the differential amplifier one by one, the voltage of the detection signal line (202) not selected by the AMP input signal line selection unit (430-2) is gradually discharged, and there is a possibility that an error may occur in the detected voltage V1. To solve this problem, all signal lines connected to the AMP input signal line selection unit (430-2) are connected to an analog voltage memory called Sample & Hold (hereinafter S&H). FIG. 16d is an embodiment of the present invention regarding a method of connecting S&H to a detection signal line, which solves the problem regarding discharge.

[0419] S&H serves to preserve the stored signal. Therefore, for all detection signal lines (202) input to the AMP input signal line selection unit (430-2), if the signal formed on the detection signal line (202) is stored (Sampling) and not discharged (Hold) using S&H as shown in FIG. 16d, then the detection signal line waiting for processing in the AMP input signal line selection unit (430-2) does not discharge, so stable signal detection becomes possible.

[0420] Subsequently, as in the embodiment of FIG. 16c, by sequentially energizing the switch of the detection signal line selection unit (450-1) to detect V1 output from the differential amplifier using the DAC and ADC, the signal is preserved in S&H, thereby preventing distortion caused by the signal leaking from the detection signal line.

[0422] In the case of the third embodiment as described above, the positions of the DAC and ADC are fixed by using only one differential amplifier, so the wiring of the DAC and ADC is simplified, and since only one differential amplifier is used, the current consumption is reduced and the area of ​​the semiconductor IC (400) is reduced.

[0423] The CPU (460) analyzes the digital code transmitted from the ADC to determine 1) whether an object appears, or 2) the position of the object on the display device, i.e., the coordinates of the object, or 3) the distance between the object and the CDA (200), and transmits it to a Host outside the device not shown.

[0425] Referring to FIG. 14, which is an embodiment of the present invention regarding the application of driving voltage, the first stage driving voltages Vd1 and Vcin1 in ZONE A to ZONE D are low voltages compared to the second stage driving voltages Vd2 and Vcin2. As a result, the magnitudes of (Vd2-Vd1) or (Vcin2-Vcin1) in <Equation 4> have positive values.

[0426] Based on <Equation 4>, the magnitude of <Equation 5>, in which the object capacitance (Cobj) term is added to the denominator, is always a smaller value than <Equation 4>. In order for the output of the differential amplifier of FIG. 16 using a single power supply to be normal, the magnitude of the output value must always be positive; therefore, the DAC, which is the duplicate value of Equation 4, must be connected to the Positive Input terminal of the differential amplifier, and the detection signal line (202), which has the information of Equation 5 that is equal to or smaller than the DAC, must be connected to the Negative Input terminal of the differential amplifier.

[0427] ZONE S of FIG. 14 is an example in which the first stage driving voltage is High Voltage (Vd2) and the second stage driving voltage is Low Voltage (Vd1).

[0428] In an embodiment of this case, mathematical formula 6 is modified as follows in mathematical formula 9.

[0429]

[0431] (Vd1-Vd2) in Equation 9 is a negative value, and likewise (Vcin1-Vcin2) is also a negative value. For this reason, the first detection signal and the second detection signal of Equation 9 have negative values. Since a signal having a negative value should not be connected to a differential amplifier using a single power supply with 0V as the ground, a High Voltage reset voltage is applied to the detection signal line (202) in advance to apply the first stage driving voltage so that the potential of the detection signal line becomes the High Voltage reset voltage. Subsequently, when the driving voltage according to Equation 9 is applied and the voltage of the detection signal line drops by a negative value, the magnitude of the reset voltage is selected so that it does not fall below 0V, and a normal signal is output even when using a differential amplifier with a single power supply.

[0432] In one embodiment, when the first detection voltage value of <Equation 9> is -4V, if the detection signal line is reset to a reset voltage Vd2 (e.g., 5V) in advance, the first detection voltage becomes 1V (5V-4V).

[0433] Since the magnitude of the absolute value of the second detection signal in <Equation 9> is equal to or smaller than the absolute value of the first detection signal in <Equation 9>, when the reset voltage is 5V, the magnitude of the second detection signal is 1V or greater than 1V.

[0434] These calculation results indicate that when the first stage driving voltage is High Voltage and the second stage driving voltage is Low Voltage, the magnitude of the second detection signal is equal to or greater than the magnitude of the first detection signal. Therefore, in a differential amplifier using a single power supply, when the first stage driving voltage is High Voltage and the second stage driving voltage is Low Voltage, in order to maintain the output of the differential amplifier at a positive value, the detection signal line (202) must be connected to the Positive Input terminal of the differential amplifier, and the duplicated DAC must be connected to the Negative Input terminal. Considering these results, FIGS. 16a and 16b show the connection method of the DAC and the detection signal line when the first stage driving voltage is Low and the second stage driving voltage is High, and FIGS. 16c and 16d show the connection method of the DAC and the detection signal line when the first stage driving voltage is High and the second stage driving voltage is Low.

[0435] In this way, the method of connecting the detection signal line (202) and the DAC to the differential amplifier varies according to the height of the first stage driving voltage and the second stage driving voltage.

[0436] When the first stage driving voltage is Low Voltage and the second stage driving voltage is High Voltage, the detection signal line (202) is connected to the Negative Input terminal of the differential amplifier and the DAC is connected to the Positive Input terminal; and when the first stage driving voltage is High Voltage and the second stage driving voltage is Low Voltage, the detection signal line (202) is connected to the Positive Input terminal of the differential amplifier and the DAC is connected to the Negative Input terminal.

[0437] Up until now, with reference to the embodiment regarding the application of driving voltage in FIG. 14, we have described cases where the first driving voltage is Low Voltage and the second driving voltage is High Voltage, as in the embodiment of ZONE A to ZONE D in FIG. 14, or where the first driving voltage is High Voltage and the second driving voltage is Low, as in the embodiment of ZONE S. If a method in which the magnitudes of the first driving voltage and the second driving voltage are always constant is defined as "one-way driving," the object detection method by one-way driving requires a lot of time.

[0438] Referring again to ZONE A to ZONE D of FIG. 14, when a first stage driving voltage is applied and a reset voltage (0V in one embodiment) is applied to point P (or detection signal line) of FIG. 12, time is required for the reset voltage to reach a target value due to the line resistance of the detection signal line (202) and the capacitances connected in parallel to the detection signal line (202). In the case of an RC circuit, when an arbitrary signal is applied to resistor R and a time of about three times the time constant (R*C) has elapsed, the voltage detected at the capacitance is 95% of the input voltage, and generally, in an RC circuit, it is preferable to use the voltage of the capacitance after waiting for a time of about three times the time constant.

[0439] If we assume that the line resistance of a detection signal line is 400Kohm and the sum of the capacitances connected in parallel to the detection signal line is 40pF, then the time constant R*C is 16us, and three times the time constant is 48us. According to this, it means that after applying a reset voltage to the detection signal line, one must wait 48us until the target value (reset voltage) is reached. It also means that one must wait for almost the same amount of time, 48us, to apply a second stage driving voltage to the capacitance of a detection signal line having a line resistance of 400Kohm and a capacitance of 40pF and to extract the second detection signal.

[0440] As in the above embodiment, when approximately 96us is consumed to detect a signal after applying a reset voltage and a driving voltage on a single detection signal line, a problem arises in that the processing time becomes long and a large amount of current is consumed when the number of groups is large or the number of CDAs included in a single column is large. Therefore, in order to reduce current consumption, the time required for signal detection must be reduced, and one embodiment of a method to reduce the time required for signal detection is to drive in a bidirectional manner.

[0441] All driving methods of ZONE A to ZONE S in FIG. 14 are unidirectional driving methods, and the bidirectional driving method is a combination of the unidirectional driving methods of ZONE A to ZONE D in FIG. 14 and the unidirectional driving method of ZONE S.

[0442] In bidirectional driving, just like in the case of unidirectional driving of ZONE A to ZONE D, after detecting a signal from the differential amplifier using an ADC after 96us, the state of point P, which maintains a High state with the current second stage driving voltage applied, is considered as if the first stage driving voltage in a High state has already been applied, as in ZONE S, and the reset voltage is also applied as a High voltage.

[0443] Bidirectional driving reuses the state of the second stage driving voltage as a state where the first stage driving voltage has already been applied, and uses it as a condition for applying a reset voltage of the same High or Low state as the first stage driving voltage, so the time required for charging the reset voltage is reduced, and thus the overall processing time is shortened.

[0444] As described in the above embodiment, in bidirectional driving, whenever a driving voltage is applied, the magnitudes of the first driving voltage and the second driving voltage alternate between Low Voltage and High Voltage. Additionally, the reset voltage is applied in accordance with the potential of the first driving voltage. For example, if the first driving voltage is Low Voltage, the reset voltage is also Low Voltage, and if the first driving voltage is High Voltage, the reset voltage is also High Voltage. At this time, Low Voltage and High Voltage refer to the higher and lower values ​​among the two voltages of the first driving voltage and the second driving voltage, and refer to the higher and lower values ​​among the two reset voltages.

[0445] In this way, the present invention, when driving in both directions, the magnitude of the first stage driving voltage applied to the capacitance connected to the detection signal line alternates sequentially between Low Voltage and High Voltage whenever the driving voltage is applied.

[0446] In addition, when the first stage driving voltage is applied, a reset voltage is applied to the detection signal line (202), and at this time, if the first stage driving voltage is Low Voltage, the reset voltage is also Low Voltage, and if the first stage driving voltage is High Voltage, the reset voltage is also High Voltage.

[0447] During bidirectional driving, if the second stage driving voltage is High Voltage, the first and second detection signals are detected in the High Voltage region, and if the second stage driving voltage is Low Voltage, the detection signal is detected in the Low Voltage region. Therefore, in the case of bidirectional driving, the voltage range of the DAC that replicates the first detection signal must also be managed by distinguishing it into High Voltage and Low Voltage regions.

[0448] In this case, a method can be used to output Low Voltage DAC voltage and High Voltage DAC voltage using a single DAC device, or to use two DAC devices to handle the Low Voltage DAC region and the High Voltage DAC region respectively.

[0449] The following embodiment describes a case where a single DAC is used to output both a low voltage range DAC voltage output and a high voltage range DAC voltage output. To output voltages in both ranges using a single DAC, there is a method in which the single DAC covers the entire low voltage and high voltage ranges; however, this embodiment has the problem of significantly reduced DAC resolution. For example, when covering the 0~5V range with a 10-bit DAC, the DAC resolution is 5mV / bit, which shows significantly lower performance compared to the resolution described above.

[0450] Referring to the hypothetical data in Fig. 13, the signal detection range is located in the High Voltage range of approximately 4.615V to 4.886V due to the 0V reset voltage and 5V driving voltage during Dual Driving. When the first stage driving voltage Vd1=5V and the second stage driving voltage Vd2=0V, it can be calculated that if the reset voltage is 5V, the signal detection range will be in the range of 0.114 to 0.385V. According to the result of the above calculation, it can be expected that the detection range will be approximately 0.3V when the detection signal of the differential amplifier is formed in the High Voltage region or when the detection signal is formed in the Low Voltage region. Accordingly, in the detection signal range formed at High Voltage, DAC_top can be set to 4.9V and DAC_btm to extract the duplicated DAC, and in the signal range formed at Low Voltage, DAC_top can be set to 0.4V and DAC_btm to 0.1V to extract the duplicated DAC.

[0451] When detecting objects in the Low Voltage region, duplicated DACs are extracted for each CDA based on DAC_top=0.4V and DAC_btm=0.1V and stored in memory; when detecting objects in the High Voltage region, duplicated DAC values ​​are extracted based on DAC_top=4.9V and DAC_btm=4.6V and stored in memory, provided that the DAC values ​​for the Low Voltage region and the High Voltage region are stored in different memory areas; when detecting a signal in the Low Voltage region, the DAC value from the Low Voltage region is retrieved and used, and when detecting a signal in the High Voltage region, the DAC value from the High Voltage region stored in memory is retrieved and used.

[0452] As such, in the case of bidirectional driving, the present invention stores the DAC value of the Low Voltage region and the DAC value of the High Voltage region in different memory regions.

[0453] In addition, when detecting a signal in the Low Voltage region, the DAC value of the Low Voltage region of the memory is called and used, and when detecting a signal in the High Voltage region, the DAC value of the High Voltage region of the memory is called and used.

[0454] As in the above embodiment, when using a single DAC during bidirectional driving, the bias voltage of the DAC is set to Low Voltage when the detection signal range is Low Voltage, and the bias voltage of the DAC is set to High Voltage when the detection signal range is High Voltage.

[0455] Meanwhile, when using two DACs, one DAC always operates as a dedicated DAC in the High Voltage range, and the other DAC is used exclusively when the detection signal is Low Voltage.

[0456] Since the differential amplifier outputs only the difference between the first detection signal and the second detection signal regardless of whether it is driven unidirectionally or bidirectionally, the output of the differential amplifier is identical regardless of whether it is driven unidirectionally or bidirectionally, and for this reason, only one ADC is needed to detect the output of the differential amplifier.

[0457] As such, the present invention uses only one ADC even when driving in both directions.

[0459] The reason why the connection method of the DAC and detection signal line in the differential amplifier must be different when the first stage driving voltage is Low Voltage and the second stage driving voltage is High Voltage, and when the first stage driving voltage is High Voltage and the second stage driving voltage is Low Voltage, and the connection method are as described above.

[0460] When operating in bidirectional mode, the first stage driving voltage and the second stage driving voltage change sequentially; therefore, the connection method of the DAC and detection signal lines in the differential amplifier must also be changed according to the change in driving voltage.

[0461] FIG. 19 is an embodiment of the present invention regarding a method for connecting a DAC and signal lines of a differential amplifier.

[0462] When the first stage driving voltage is Low Voltage and the second stage driving voltage is High Voltage, the object signal is detected at High Voltage. As described above, the analog voltage of the duplicated DAC must be connected to the Positive Input terminal of the differential amplifier, and the detection signal line must be connected to the Negative Input terminal of the differential amplifier. This is implemented by turning on Switch 1 (SW1) and Switch 3 (SW3) through the Enable signal applied to the on / off terminals of Switch 1 (SW1) and Switch 3 (SW3) in FIG. 19. Additionally, High Voltage is used for the bias voltage of the DAC.

[0463] In addition, when the first stage driving voltage is High Voltage and the second stage driving voltage is Low Voltage—that is, when a signal is detected at Low Voltage—the analog voltage of the duplicated DAC must be connected to the Negative Input terminal of the differential amplifier, and the detection signal line must be connected to the Positive Input terminal of the differential amplifier. This is the connection line indicated by the Blue Line in Fig. 19, and is executed by turning on SW2 and SW4 through the Enable signal applied to the on / off terminals of SW2 and SW4. Additionally, a Low Voltage is applied as the bias voltage of the DAC.

[0464] As such, in the present invention, when driving in both directions, if the second stage driving voltage is High Voltage, the DAC output voltage for detecting the object signal is connected to the Positive Input terminal of the differential amplifier, and if the second stage driving voltage is Low Voltage, the DAC output voltage is connected to the Negative Input terminal of the differential amplifier. A detection signal line (202) is connected to the other terminal to which the DAC output voltage is not connected.

[0465] In addition, the Enable signal connected to the on / off control terminals of SW1 to SW4 is controlled to turn on or turn off by the control operation of the CPU (460) or Logic part of the semiconductor IC.

[0467] The improvements regarding the method of driving a single capacitor and the case of driving a dual capacitor of the present invention are as follows.

[0468] Referring to the hypothetical data and calculation results in Fig. 13, for Single Driving, the Min to Max of (Vp2-Vp1) is 1.429V, so an ADC with a bias voltage of at least 1.5V must be used. At this time, the resolution is approximately 1.5mV / bit. Also, for Dual Driving, (Vp2-Vp1) is 0.271V, so an ADC with a bias voltage of 0.3V can be used, and the resolution at this time is 0.5mV / bit.

[0469] When the object capacitance (Cobj) is 0.2 pF, referring to the worst case at the bottom of the virtual data, the voltage detected by the differential amplifier in the case of Single Driving is 16 mV. This is approximately 10.6 codes considering a resolution of 1.5 mV / bit. This sensitivity corresponds to about 1% of the total resolution, which is an unsuitable level for use as a signal given that the typical noise range is 2% to 3%.

[0470] On the other hand, in the case of Dual Driving, the voltage detected by the differential amplifier is 21mV, which is 42 codes considering the resolution of 0.5mV / bit. This represents a fourfold increase in sensitivity compared to Single Driving and is a sensitivity equivalent to about 4% of the total resolution, making it suitable for use as a signal.

[0471] As described above, the method of driving a plurality of capacitances including the shielding capacitance (Cin_sd) of the present invention is not affected by noise caused by interference with "other signal lines," and by modifying and driving the internal capacitance, which previously acted only as a dummy included in the denominator and had an adverse effect of spreading the dispersion of the detection signal, it has the effect of increasing the sensitivity of the detection signal by at least four times.

[0473] Meanwhile, referring to Equation 4, the driving voltage is not applied only to the common electrode capacitance (Ccm) among the components of the denominator constituting the first voltage prior to the appearance of the object (20). If the driving voltage is also applied to the Ccm driving layer (6), the (Vp2-Vp1) voltage detected by Equation 4, which performs Dual Driving, shows a more stable deviation, and the equation at this time is as shown in Equation 6-1 below.

[0475] <Mathematical Formula 6-1>

[0476]

[0478] To detect an object (20), the magnitude of the first detection signal of the detection signal line must always be constant. If, for any reason, the magnitude of the first detection signal of any CDA (100) changes frequently, it is impossible to construct the device of the present invention.

[0479] In order for the magnitude of the first detection voltage formed by Equation 4 in any CDA (100) not to change, the potential of the detection signal line (202), i.e., point P, must always be constant at the time when the first stage driving voltage of the driving voltage is applied. In order to always maintain the potential of point P constant, the same known voltage is applied to point P to always maintain the potential of point P constant.

[0480] FIG. 20 is an embodiment of the present invention that applies a reset voltage to a detection signal line.

[0481] In the embodiment of FIG. 20, the reset switch 1 (Reset SW1) and the reset switch 2 are switches that apply a reset voltage, and one side of the reset switch is connected to the driving voltage and the other side is connected to point P, i.e., the CDA signal line (200).

[0482] Reset switch 1 is connected to the line capacitance (Cd) driving voltage, and reset switch 2 is connected to the shielding capacitance (Cin_sd). When a reset voltage is applied, only one of reset switch 1 or reset switch 2 operates, and only one of reset switch 1 or reset switch 2 can be installed.

[0483] If it is assumed that only reset switch 1 is installed, at the time when the first stage driving voltage is applied, reset switch 1 is turned on, and the first stage driving voltage Vd1 or Vd2 is applied to the detection signal line (202). If the driving voltage is operating according to the types of ZONE A to ZONE D of FIG. 14, at the time when the first stage driving voltage is applied, a low voltage of Vd1 is applied to the detection signal line (202), and point P is charged with the voltage of Vd1. In the embodiment of FIG. 18b, the reset voltage is an embodiment in which the low voltage Vd1 is applied, and the application of the reset voltage must be stopped before the second stage driving voltage is applied, and for this purpose, reset switch 1 is turned off. Afterward, the second stage driving voltage is applied and a predetermined time elapses, a voltage based on Equation 6 is detected in the differential amplifier.

[0484] Equation 4 is an equation assuming that the initial voltage of point P is 0V, and if point P is charged with a reset voltage of magnitude Vd1 that is not 0V, Equation 4 becomes as follows Equation 10.

[0486]

[0487] Looking at the above mathematical formula 10, since the values ​​of all factors are fixed values ​​that do not change, the voltage detected according to the formula also always has a constant value. In addition, in mathematical formula 5, only the object capacitance (Cobj) is included in the denominator of the formula, and since the magnitude of the object capacitance (Cobj) always changes depending on the opposing area and opposing distance with the CDA (100), it is possible to accurately detect the amount of change in the object capacitance (Cobj).

[0488] Meanwhile, as in the embodiment of ZONE S in FIG. 14, when the first stage driving voltage is High Voltage and the second stage driving voltage is Low Voltage, the reset voltage applied to the detection signal line through switch 1 is High Voltage Vd2, and Equation 4 is modified as Equation 11 below.

[0489]

[0490] Looking at the above mathematical formula 11, since (Vd1-Vd2) and (Vcin1-Vcin2) have negative values, they are falling voltages relative to the reset voltage Vd2. These voltages can form a voltage less than 0V, and since a negative signal should not be input to a differential amplifier using a single power supply, Vd2 must be a higher voltage than the value in the formula, taking this into account. In a typical embodiment, the first stage driving voltage Vd2 satisfies these conditions.

[0491] Accordingly, in the present invention, the first stage driving voltage is used as a reset voltage, and the reset voltage is applied by turning on a reset switch existing between the first stage driving voltage and the detection signal line (202), and the reset switch is turned off before the second stage driving voltage is applied to stop the application of the reset voltage.

[0492] In addition, the present invention supplies a reset voltage of the same magnitude to the detection signal lines of all columns within a group that performs processing to detect an object among a plurality of groups composed of a set of columns composed of a plurality of CDAs (100).

[0493] In addition, if the first stage driving voltage is High Voltage, the reset voltage is High Voltage Vd2, and if the first stage driving voltage is Low Voltage, the reset voltage is Low Voltage Vd1.

[0495] Meanwhile, the second detection signal based on Equation 10, which includes the reset voltage, is given by the following Equation 12.

[0497]

[0498] Since the differential amplifier detects only the difference between the first detection signal and the second detection signal, the voltage output from the differential amplifier according to Equations 10 and 12 when a reset voltage is applied is the same as Equation 6.

[0499] In addition, the second detection signal when a High reset voltage is applied based on Equation 11 is the following Equation 13.

[0500]

[0501] Based on Equations 11 and 13, the output voltage V1 of the differential amplifier based on the object capacitance (Cobj) when the first stage driving voltage is High Voltage and the second stage driving voltage is Low Voltage and a reset voltage (Vd2) of High Voltage is applied is given by the following Equation 14.

[0503]

[0505] As with Equation 6, it can be seen that in Equation 14, the reset voltage is eliminated in the differential amplifier and has no effect on V1.

[0506] Referring to the above mathematical equations 6 and 14, the reset voltage does not affect the V1 voltage output from the differential amplifier. Since the purpose of applying the reset voltage is to keep the voltage of the detection signal line constant when the driving voltage is applied, using the driving voltage as the reset voltage has the advantage of simplifying the circuit because it is not necessary to create a separate reset voltage.

[0508] Meanwhile, referring to the data for Dual Driving in Fig. 13a, when the magnitudes of the reset voltages Vd1 and Vcin1 are 0V, the magnitude of (Vp2-Vp1) is 4.615V to 4.886V, with a variation range of 0.271V.

[0509] If the upper values ​​of 4.615V, 4.688V, and 4.667V among the values ​​of (Vd2-Vd1) detected by Dual Driving in Fig. 13a can all be changed to values ​​of approximately 4.7V, the fluctuation range of (Vp2-Vp1) can be reduced to 0.186V, and a higher resolution of the ADC can be expected.

[0511] FIG. 21 is another embodiment of the present invention regarding a method for applying a reset voltage.

[0512] Referring to FIG. 21, a reference voltage Vref3 is connected to a resistor string composed of multiple resistors. Vref3 is generated by a Band Gap Reference (BGR) or a separate reference voltage component. Vref3 has means to be adjusted to have a predetermined voltage value, and generally, the output value of Vref3 is determined by the resistance ratio.

[0513] Another device for applying a reset voltage according to the present invention can be easily implemented as a resistor string as in the embodiment of FIG. 21, and can output a precise output value and a large number of output values ​​by utilizing the resistance ratio of each resistor.

[0514] A select switch that outputs one of multiple reset voltages through a resistor string is used as a reset switch.

[0515] In the embodiment of FIG. 21, the selection switch is a switch that selects one of five inputs, and the reset voltage selected by the switch is connected to point P, which is the detection signal line (200), and fixes point P as the reset voltage. When all five switches are turned off, the reset voltage output from the resistor String is not connected to point P, and all switches of the selection switch are turned off before the second stage driving voltage is applied.

[0516] The reset voltage created by the resistor String can be supplied with a voltage of a different magnitude for each CDA (100). Alternatively, a reset voltage of the same magnitude can be applied to all detection signal lines to which a driving voltage is applied at the same time. Also, a reset voltage of a different magnitude can be applied for each row.

[0517] For example, in a group formed by combining 10 columns of 25 CDAs, a reset voltage of size RST1 is applied to the 10 CDAs included in the first row of the 10 columns, but when the second row is processed, a reset voltage of RST2, which has a different size from RST1, is applied, and thus it is possible to vary the size of the reset voltage for each row. By this method, among the values ​​of (Vd2-Vd1) detected by Dual Driving in FIG. 13a, if a reset voltage of about 0.1V is used instead of a reset voltage of 0V for the upper CDAs outputting 4.615V, 4.688V, or 4.667V, the operating point of the above values ​​shifts to a value in the 4.7V range. Consequently, the voltage range of (Vp2-Vp1) detected using the virtual data of FIG. 13 based on <Equation 4> is further reduced to about 0.2V, thereby increasing the resolution of the ADC.

[0518] Since the magnitude of the voltage V1 detected based on the object capacitance does not change even if the magnitude of the reset voltage is varied, if the magnitude of the reset voltage is varied for each CDA so that the voltage level of the first detection signal of various sizes determined for each CDA is located in as narrow a range as possible, the resolution of the ADC is further improved.

[0519] In the embodiment of FIG. 21, only five reset voltages are shown, but this is merely one example. There may be cases where the number of reset voltages output from the resistor string is 8, 16, or more, and the number of selector switches is also increased by the same amount.

[0521] The following is an embodiment of the present invention regarding a capacitance detection method. FIG. 22 is an embodiment of the present invention regarding a flowchart illustrating a capacitance detection method.

[0522] Referring to FIG. 22, the initial step (F110) is to select a CDA (100) to detect an object and then connect the selected detection signal line (202) to a differential amplifier. The two groups distinguished in the embodiment of the present invention consist of multiple columns, and only one CDA (100) in one column is used for signal detection. A CDA (100) located in the same row in all columns included in one group is selected, and the selected detection CDA (100) is connected to a differential amplifier either directly or through S&H.

[0523] The second step (F120) is a step of applying a reset voltage and a first stage driving voltage, waiting for a predetermined time, releasing the reset voltage, and applying a second stage driving voltage. When the second stage driving voltage is applied and a predetermined time is waited, the voltage of the detection signal line (202) is formed as a voltage based on <Equation 12> to <Equation 13>.

[0524] The third step (F130) is to call the DAC duplicated from memory and connect the DAC voltage to one side of the differential amplifier.

[0525] At this time, the signal V1 output from the differential amplifier is output based on <Equation 6> or <Equation 14>.

[0526] The fourth step (F140) is a step in which the analog voltage signal output from the differential amplifier of the third step is converted into a digital signal using an ADC. After signal processing is completed and the result is stored in memory, the process returns to the first step to perform the same processing on other detection signal lines.

[0527] The foregoing description of the present invention is for illustrative purposes only, and those skilled in the art will understand that the present invention can be easily modified into other specific forms without changing the technical concept or essential features of the invention.

[0528] Therefore, the embodiments described above should be understood as illustrative in all respects and not restrictive. For example, individual devices described as single units may be combined to form a composite device, and likewise, a composite device may be formed in a combined form of undescribed individual devices. The scope of the invention is defined by the claims set forth below, and all modifications or variations derived from the meaning and scope of the claims and their equivalents should be interpreted as being included within the scope of the invention. Explanation of the symbols

[0530] 3: Common electrode 4: Color Layer 5 : Color Filter Glass 6 : Ccm driving layer 7 : Protective layer 10 : Display device 20 : Object 100: CDA (Capacitor Detect Area) 101 : Ranged CDA 103 : Close-range CDA 150 : empty spaces 200 : CDA signal line 200-1 : Pin input signal line 201: Long-distance CDA signal line 202 : Intermediate distance CDA signal line 203 : Near-field CDA signal line 210 : Column1 detection signal line 210-1 : Column1 driving signal line 220 : Column2 detection signal line 220-1 : Column 2 driving signal line 230 : Column3 detection signal line 230-1 : Column3 Driving Signal Line 240 : Column 4 detection signal line 240-1 : Column4 drive signal line 250-1 : Group 1 detection signal line 250-2 : Group 2 detection signal line 251 : Column1 1st Shielding Area Driving Signal Line 252 : Column 2 1st Shielding Area Driving Signal Line 253 : Column 1 2nd Shielding Area Driving Signal Line 254 : Column 2 Second Shielding Area Driving Signal Line 255 : Group 1 3rd Shielding Area Driving Signal Line 256 : Group 2 3rd Shielding Area Driving Signal Line 259 : Column 4 1st Shielding Area Driving Signal Line 261 : Column1 1st Shielding Area 261-1 :Cloumn1 1st Upper Shielding Area 261-2 :Cloumn1 1st Lower Shielding Area 261-3 :Cloumn1 1st Left and Right Shielding Areas 262 : Column 2 1st Shielding Area 263 : Column1 Second shielding area 264 : Column2 Second Shielding Area 265 : Group 1 Third Shielding Area 266 : Group 2 Third Shielding Area 270-1: Group1 Loading Signal Line (LD Signal Line) 270-2: Group2 Loading Signal Line (LD Signal Line) 300 : Connecting member 301 : Joint 302 : Connection part 400 : Semiconductor IC 401: Signal line input Pin 410 : Signal detection unit 420 : Drive unit 430-1 : Differential amplifier 430-2 : AMP Input Signal Line Selector 436 : Decoder 437 : Detection / Drive Signal Line Switch Group 437-1 : Sensing Signal Line Switch Group (SSL SG) 437-2 : Driving Signal Line Switch Group (DSL SG) 438 : Switch group internal switch 450 : Loader 450-1 : Group 1 Loader 450-2 : Group 2 Loader 460 : CPU 461 : Substrate 462 : Insulater 463 : 1st Metal Layer 464 : 2nd Metal Layer 465 : 3rd Metal Layer 466 : Passivation 490 : Level Shifter

Claims

Claim 1 A capacitance detection device comprising: a capacitance detection area installed in a display device and having an independent conductive region; a semiconductor IC that detects a touch in the capacitance detection area; and a signal line connecting one input terminal of a differential amplifier located inside the semiconductor IC and the capacitance detection area; wherein a portion of the capacitance detection area is peeled off into an empty space, the peeled-off empty space is installed opposite to a light-transmitting or light-nontransmitting portion of a unit pixel (Sub Pixel) constituting the display device, and the signal line connected to the capacitance detection area is not peeled off, and a driving voltage is applied to a plurality of capacitors connected to the signal line to detect a capacitor added to the capacitance detection area where a portion is peeled off. Claim 2 A capacitance detection device according to claim 1, characterized in that the density of the peeled void is constant in the same capacitance detection area. Claim 3 A capacitance detection device according to claim 1, characterized in that the difference in the empty space peeling ratio between the capacitance detection region having the peeled empty space and the capacitance detection region adjacent thereto is within 5%. Claim 4 A capacitance detection device according to claim 1, characterized in that the peeled shape in the capacitance detection area is formed identically in the same capacitance detection area, and the peeled shape of the capacitance detection area adjacent to the peeled capacitance detection area is also identical. Claim 5 A capacitance detection device according to claim 1, characterized in that the ratio of the empty space peeled off in the capacitance detection area is within a maximum of 90%. Claim 6 In claim 1, a DAC is connected to the other input terminal of the differential amplifier to which the signal line is connected, and the differential amplifier outputs the difference between the DAC output voltage and the voltage formed on the signal line, and a capacitance detection device that calculates the magnitude of the voltage output from the differential amplifier to detect the added capacitance. Claim 7 A capacitance detection device according to claim 1, wherein one of the plurality of capacitors connected to the signal line is a shielding capacitance, and the shielding capacitance is a capacitance formed between the signal line and a shielding region installed on the upper and lower layers of a semiconductor IC layer on which the signal line is patterned.

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