Semiconductor device and method for fabricating the same

Abstract

A semiconductor device and a method for manufacturing the same are provided for preventing the formation of an unmerged epitaxial pattern. The semiconductor device comprises a substrate, a first active pattern extending in a first direction on the substrate, a second active pattern stacked on the first active pattern and extending in the first direction, a first gate structure extending in a second direction intersecting the first direction and intersecting the first active pattern and the second active pattern, a second gate structure spaced apart from the first gate structure in the first direction and extending in a second direction and intersecting the first active pattern and the second active pattern, a first epitaxial pattern connected to the first active pattern between the first gate structure and the second gate structure, a second epitaxial pattern connected to the second active pattern between the first gate structure and the second gate structure, an insulating pattern interposed between the first epitaxial pattern and the second epitaxial pattern, and a semiconductor film extending along the upper surface of the insulating pattern between the insulating pattern and the second epitaxial pattern.

Description

Technology Field

[0001] The present invention relates to a semiconductor device and a method for manufacturing the same. More specifically, the present invention relates to a semiconductor device comprising stacked multi-gate transistors and a method for manufacturing the same. Background Technology

[0002] As one of the scaling techniques to increase the density of integrated circuit devices, a multi-gate transistor has been proposed in which a silicon body in the shape of a fin or nanowire is formed on a substrate and a gate is formed on the surface of the silicon body.

[0003] Since these multi-gate transistors utilize a three-dimensional channel, they are easy to scale. In addition, current control capability can be improved without increasing the gate length of the multi-gate transistor. Furthermore, the short channel effect (SCE), in which the potential of the channel region is affected by the drain voltage, can be effectively suppressed. Prior art literature

[65535] U.S. Patent Publication US 2021 / 0366782 A1 (Published Nov. 25, 2021) The problem to be solved

[0004] The technical problem that the present invention aims to solve is to provide a semiconductor device that prevents the formation of unmerged epitaxial patterns.

[0005] Another technical problem that the present invention aims to solve is to provide a method for manufacturing a semiconductor device that prevents the formation of an unmerged epitaxial pattern.

[0006] The technical problems of the present invention are not limited to those mentioned above, and other unmentioned technical problems will be clearly understood by those skilled in the art from the description below. means of solving the problem

[0007] A semiconductor device according to some embodiments for achieving the above technical problem comprises a substrate, a first active pattern extending in a first direction on the substrate, a second active pattern stacked on the first active pattern and extending in the first direction, a first gate structure extending in a second direction intersecting the first direction and intersecting the first active pattern and the second active pattern, a second gate structure spaced apart from the first gate structure in a first direction and extending in a second direction and intersecting the first active pattern and the second active pattern, a first epitaxial pattern connected to the first active pattern between the first gate structure and the second gate structure, a second epitaxial pattern connected to the second active pattern between the first gate structure and the second gate structure, an insulating pattern interposed between the first epitaxial pattern and the second epitaxial pattern, and a semiconductor film extending along the upper surface of the insulating pattern between the insulating pattern and the second epitaxial pattern.

[0008] A semiconductor device according to some embodiments for achieving the above technical problem comprises a substrate, a first active pattern extending in a first direction on the substrate, a second active pattern stacked on the first active pattern and extending in the first direction, a gate structure extending in a second direction intersecting the first direction on the substrate, through which the first active pattern and the second active pattern penetrate, a first epitaxial pattern connected to the first active pattern on a side of the gate structure, a second epitaxial pattern connected to the second active pattern on a side of the gate structure, an insulating pattern interposed between the first epitaxial pattern and the second epitaxial pattern, and a semiconductor film interposed between the insulating pattern and the second epitaxial pattern, wherein the second epitaxial pattern includes an epitaxial layer grown using the second active pattern and the semiconductor film as a seed layer.

[0009] A semiconductor device according to a few embodiments for achieving the above technical problem comprises: a substrate; a plurality of lower sheet patterns stacked sequentially on the substrate and spaced apart from each other and each extending in a first direction; a plurality of upper sheet patterns stacked sequentially on the plurality of lower sheet patterns and spaced apart from each other and each extending in a first direction; a separation pattern interposed between the plurality of lower sheet patterns and the plurality of upper sheet patterns; a gate structure extending in a second direction intersecting the first direction on the substrate, through which the plurality of lower sheet patterns and the plurality of upper sheet patterns are each penetrated; a first epitaxial pattern having a first conductivity type connected to the plurality of lower sheet patterns on the side of the gate structure; a second epitaxial pattern having a second conductivity type different from the first conductivity type connected to the plurality of upper sheet patterns on the side of the gate structure; an insulating pattern interposed between the first epitaxial pattern and the second epitaxial pattern on the side of the separation pattern; and a polysilicon film extending along the upper surface of the insulating pattern between the insulating pattern and the second epitaxial pattern.

[0010] Specific details of other embodiments are included in the detailed description and drawings. Brief explanation of the drawing

[0011] FIG. 1 is a schematic layout diagram for illustrating a semiconductor device according to some embodiments. Figure 2 is a cross-sectional view taken along A1-A1 of Figure 1. Figure 3 is a cross-sectional view taken along BB of Figure 1. FIGS. 4 to 6 are comparative drawings for explaining the effects of a semiconductor device according to some embodiments. FIGS. 7 to 11 are various cross-sectional views for illustrating a semiconductor device according to some embodiments. FIG. 12 is a schematic layout diagram for illustrating a semiconductor device according to some embodiments. FIG. 13 is a cross-sectional view taken along A1-A1 and A2-A2 of FIG. 12. FIGS. 14 to 30 are intermediate step drawings for explaining a method of manufacturing a semiconductor device according to some embodiments. FIG. 31 is an intermediate step diagram for explaining a method of manufacturing a semiconductor device according to some embodiments. FIG. 32 is an intermediate step diagram for explaining a method of manufacturing a semiconductor device according to some embodiments. Specific details for implementing the invention

[0012] Hereinafter, a semiconductor device according to exemplary embodiments is described with reference to FIGS. 1 to 13. Although terms such as "first," "second," etc. are used to describe various elements or components in this specification, it is understood that these elements or components are not limited by these terms. These terms are used merely to distinguish one element or component from another. Accordingly, it is understood that the first element or component mentioned below may be the second element or component within the technical scope of the present invention.

[0013] FIG. 1 is a schematic layout diagram for illustrating a semiconductor device according to some embodiments. FIG. 2 is a cross-sectional view taken along A1-A1 of FIG. 1. FIG. 3 is a cross-sectional view taken along BB of FIG. 1.

[0014] Referring to FIGS. 1 to 3, a semiconductor device according to some embodiments comprises a substrate (100), a first active pattern (110A), a second active pattern (110B), a field insulating film (105), an isolation pattern (120), a first gate structure (G1), a second gate structure (G2), a first epitaxial pattern (160A), a second epitaxial pattern (160B), an insulating pattern (140), a liner film (142), a semiconductor film (150), an interlayer insulating film (190), a first source / drain contact (180A) and a second source / drain contact (180B).

[0015] The substrate (100) may be bulk silicon or SOI (silicon-on-insulator). Alternatively, the substrate (100) may be a silicon substrate, or may include other materials, for example, silicon germanium, SGOI (silicon germanium on insulator), indium antimonide, lead telluride compound, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide. Alternatively, the substrate (100) may be a base substrate on which an epitaxial layer is formed. For convenience of explanation, the substrate (100) is described below as a silicon substrate.

[0016] A first active pattern (110A) and a second active pattern (110B) may be arranged sequentially on a substrate (100). The first active pattern (110A) may be spaced apart from the substrate (100) on the substrate (100). The second active pattern (110B) may be spaced apart from the first active pattern (110A) on the first active pattern (110A). That is, the second active pattern (110B) may be spaced further from the substrate (100) than the first active pattern (110A). The first active pattern (110A) and the second active pattern (110B) may each extend in a first direction (X1) parallel to the upper surface of the substrate (100). Additionally, the first active pattern (110A) and the second active pattern (110B) can be superimposed in a direction intersecting the upper surface of the substrate (100) (e.g., a third direction (Z1)).

[0017] The first active pattern (110A) and the second active pattern (110B) may each include silicon (Si) or germanium (Ge), which are elemental semiconductor materials. Alternatively, the first active pattern (110A) and the second active pattern (110B) may each include a compound semiconductor, for example, a group IV-IV compound semiconductor or a group III-V compound semiconductor. The group IV-IV compound semiconductor may be, for example, a binary compound, a ternary compound containing at least two of carbon (C), silicon (Si), germanium (Ge), and tin (Sn), or a compound doped with a group IV element. The above III-V compound semiconductor may be, for example, one of a binary compound, a ternary compound, or a quaternary compound formed by combining at least one of the Group III elements aluminum (Al), gallium (Ga), and indium (In) with at least one of the Group V elements phosphorus (P), arsenic (As), and antimonium (Sb). For convenience of explanation, the first active pattern (110A) and the second active pattern (110B) are described below as being silicon patterns.

[0018] In some embodiments, the first active pattern (110A) may include a plurality of lower sheet patterns (e.g., first to third sheet patterns (111 to 113)) spaced apart from the substrate (100). The first to third sheet patterns (111 to 113) are arranged sequentially on the substrate (100) and spaced apart from each other, each extending in a first direction (X1). These lower sheet patterns include an MBCFET comprising a multi-bridge channel. ® It can be used as a channel area. The number of lower sheet patterns is merely exemplary and is not limited thereto.

[0019] In some embodiments, the first active pattern (110A) may further include a pin pattern (110F). The pin pattern (110F) may be formed between the substrate (100) and the first sheet pattern (111). The pin pattern (110F) may protrude from the upper surface of the substrate (100) and extend in a first direction (X1). The pin pattern (110F) may be formed by etching a portion of the substrate (100) or may be an epitaxial layer grown from the substrate (100). In some other embodiments, the pin pattern (110F) may be omitted.

[0020] In some embodiments, the second active pattern (110B) may include a plurality of upper sheet patterns (e.g., fourth to sixth sheet patterns (114 to 116)) spaced apart from the first active pattern (110A). The fourth to sixth sheet patterns (114 to 116) are arranged sequentially on the first active pattern (110A) and spaced apart from each other, each extending in a first direction (X1). These upper sheet patterns include an MBCFET comprising a multi-bridge channel. ® It can be used as a channel area. The number of upper sheet patterns is merely exemplary and is not limited thereto.

[0021] A field insulating film (105) may be formed on a substrate (100). The field insulating film (105) may cover at least a portion of the side of the first active pattern (110A). For example, as shown in FIG. 3, the field insulating film (105) may cover a portion of the side of the pin pattern (110F). The field insulating film (105) may include, for example, at least one of silicon oxide, silicon nitride, silicon oxynitride, and combinations thereof, but is not limited thereto.

[0022] A separation pattern (120) may be interposed between a first active pattern (110A) and a second active pattern (110B). For example, the separation pattern (120) may be interposed between the uppermost sheet pattern among the lower sheet patterns (e.g., a third sheet pattern (113)) and the lowermost sheet pattern among the upper sheet patterns (e.g., a fourth sheet pattern (114)). Such a separation pattern (120) may separate the first active pattern (110A) and the second active pattern (110B) from each other. The separation pattern (120) may include at least one insulating material, for example, silicon oxide, silicon nitride, silicon oxynitride, and combinations thereof, but is not limited thereto.

[0023] In some embodiments, the separation pattern (120) may fill the area between the first active pattern (110A) and the second active pattern (110B). For example, the lower surface of the separation pattern (120) may contact the uppermost sheet pattern among the lower sheet patterns (e.g., the third sheet pattern (113)), and the upper surface of the separation pattern (120) may contact the lowermost sheet pattern among the upper sheet patterns (e.g., the fourth sheet pattern (114)).

[0024] A first gate structure (G1) and a second gate structure (G2) may be formed on a substrate (100) and a field insulating film (105). Each of the gate structures (G1, G2) may intersect with a first active pattern (110A) and a second active pattern (110B). For example, each of the gate structures (G1, G2) may extend in a second direction (Y1) that intersects a first direction (X1) and is parallel to the upper surface of the substrate (100). The first gate structure (G1) and the second gate structure (G2) may extend side by side, spaced apart from each other in the first direction (X1).

[0025] The first active pattern (110A) and the second active pattern (110B) can each extend in a first direction (X1) and penetrate the gate structures (G1, G2). For example, each gate structure (G1, G2) can surround the sides of the lower sheet patterns (e.g., first to third sheet patterns (111 to 113)) and the sides of the upper sheet patterns (e.g., fourth to sixth sheet patterns (114 to 116)).

[0026] In some embodiments, each gate structure (G1, G2) may include a gate dielectric film (132), a gate electrode (134A, 134B), a gate spacer (136), and a gate capping pattern (138).

[0027] Gate electrodes (134A, 134B) may be formed on a substrate (100) and a field insulating film (105). Gate electrodes (134A, 134B) may extend in a second direction (Y1) and intersect with a first active pattern (110A) and a second active pattern (110B). Gate electrodes (134A, 134B) may include, for example, at least one of TiN, WN, TaN, Ru, TiC, TaC, Ti, Ag, Al, TiAl, TiAlN, TiAlC, TaCN, TaSiN, Mn, Zr, W, Al, and combinations thereof, but are not limited thereto.

[0028] The gate electrodes (134A, 134B) may be formed through a replacement process, but are not limited thereto. Although the gate electrodes (134A, 134B) are illustrated as being single films, this is merely illustrative, and it is understood that the gate electrodes (134A, 134B) may be formed by stacking multiple conductive layers. For example, the gate electrodes (134A, 134B) may include a work function control film that controls the work function and a filling conductive film that fills the space formed by the work function control film. The work function control film may include, for example, at least one of TiN, TaN, TiC, TaC, TiAlC, and combinations thereof. The filling conductive film may include, for example, W or Al.

[0029] In some embodiments, the gate electrodes (134A, 134B) may include a lower gate electrode (134A) and an upper gate electrode (134B) stacked on the lower gate electrode (134A). The lower gate electrode (134A) may extend in a second direction (Y1) and intersect with the first active pattern (110A). The upper gate electrode (134B) may extend in a second direction (Y1) on the lower gate electrode (134A) and intersect with the second active pattern (110B).

[0030] The lower gate electrode (134A) and the upper gate electrode (134B) may comprise different materials. For example, the lower gate electrode (134A) may comprise a metal of the first conductivity type, and the upper gate electrode (134B) may comprise a metal of the second conductivity type. For example, when the first active pattern (110A) is used as the channel region of a PFET and the second active pattern (110B) is used as the channel region of an NFET, the lower gate electrode (134A) may comprise a p-type work function metal and the upper gate electrode (134B) may comprise an n-type work function metal. The p-type work function metal may comprise, for example, at least one of aluminum (Al), aluminum oxide, titanium nitride (TiN), tungsten nitride (WN), and ruthenium oxide, but is not limited thereto. The above n-type work function metal may include, for example, at least one of lanthanum (La), lanthanum oxide, tantalum (Ta), tantalum nitride, niobium (Nb), and titanium nitride (TiN), but is not limited thereto.

[0031] In FIG. 3, the lower gate electrode (134A) and the upper gate electrode (134B) are shown only in contact with each other, but this is merely illustrative. In other examples, the lower gate electrode (134A) and the upper gate electrode (134B) may be electrically separated by an insulating layer or the like.

[0032] The gate dielectric film (132) may be interposed between the first active pattern (110A) and the gate electrodes (134A, 134B) and between the second active pattern (110B) and the gate electrodes (134A, 134B). Additionally, the gate dielectric film (132) may be interposed between the pin pattern (110F) and the gate electrodes (134A, 134B) and between the field insulating film (102) and the gate electrodes (134A, 134B).

[0033] The gate dielectric film (132) may include, for example, at least one of silicon oxide, silicon oxynitride, silicon nitride, or a high dielectric constant material having a dielectric constant greater than that of silicon oxide. The high dielectric constant material may include, for example, at least one of hafnium oxide, hafnium silicon oxide, hafnium aluminum oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, lead zinc niobate, and combinations thereof, but is not limited thereto.

[0034] A semiconductor device according to some embodiments may include a negative capacitance (NC) FET using a negative capacitor. For example, the gate dielectric film (132) may include a ferroelectric material film having ferroelectric properties and a paraelectric material film having paraelectric properties.

[0035] The ferroelectric material film may have negative capacitance, and the paraelectric material film may have positive capacitance. For example, if two or more capacitors are connected in series and the capacitance of each capacitor has a positive value, the total capacitance decreases compared to the capacitance of each individual capacitor. On the other hand, if at least one of the capacitances of the two or more capacitors connected in series has a negative value, the total capacitance may have a positive value and be greater than the absolute value of each individual capacitance.

[0036] When the ferroelectric material film having negative capacitance and the paraelectric material film having positive capacitance are connected in series, the total capacitance value of the series-connected ferroelectric material film and paraelectric material film can increase. By utilizing the increase in the total capacitance value, a transistor containing the ferroelectric material film can have a subthreshold swing (SS) of less than 60 mV / decade at room temperature.

[0037] The ferroelectric material film may have ferroelectric properties. The ferroelectric material film may include, for example, at least one of hafnium oxide, hafnium zirconium oxide, barium strontium titanium oxide, barium titanium oxide, and lead zirconium titanium oxide. Here, as an example, hafnium zirconium oxide may be a material in which zirconium (Zr) is doped into hafnium oxide. As another example, hafnium zirconium oxide may be a compound of hafnium (Hf), zirconium (Zr), and oxygen (O).

[0038] The ferroelectric material film may further include a doped dopant. For example, the dopant may include at least one of aluminum (Al), titanium (Ti), niobium (Nb), lanthanum (La), yttrium (Y), magnesium (Mg), silicon (Si), calcium (Ca), cerium (Ce), dysprosium (Dy), erbium (Er), gadolinium (Gd), germanium (Ge), scandium (Sc), strontium (Sr), and tin (Sn). Depending on which ferroelectric material the ferroelectric material film contains, the type of dopant included in the ferroelectric material film may vary.

[0039] When the ferroelectric material film comprises hafnium oxide, the dopant included in the ferroelectric material film may include, for example, at least one of gadolinium (Gd), silicon (Si), zirconium (Zr), aluminum (Al), and yttrium (Y).

[0040] When the dopant is aluminum (Al), the ferroelectric material film may contain 3 to 8 at% (atomic %) of aluminum. Here, the ratio of the dopant may be the ratio of aluminum to the sum of hafnium and aluminum.

[0041] When the dopant is silicon (Si), the ferroelectric material film may contain 2 to 10 at% silicon. When the dopant is yttrium (Y), the ferroelectric material film may contain 2 to 10 at% yttrium. When the dopant is gadolinium (Gd), the ferroelectric material film may contain 1 to 7 at% gadolinium. When the dopant is zirconium (Zr), the ferroelectric material film may contain 50 to 80 at% zirconium.

[0042] The above-mentioned paraelectric material film may have paraelectric properties. The above-mentioned paraelectric material film may include, for example, at least one of silicon oxide and a metal oxide having a high dielectric constant. The metal oxide included in the paraelectric material film may include, for example, at least one of hafnium oxide, zirconium oxide, and aluminum oxide, but is not limited thereto.

[0043] The ferroelectric material film and the paraelectric material film may contain the same material. The ferroelectric material film may have ferroelectric properties, while the paraelectric material film may not have ferroelectric properties. For example, if the ferroelectric material film and the paraelectric material film contain hafnium oxide, the crystal structure of the hafnium oxide contained in the ferroelectric material film is different from the crystal structure of the hafnium oxide contained in the paraelectric material film.

[0044] The above-mentioned ferroelectric material film may have a thickness having ferroelectric properties. The thickness of the above-mentioned ferroelectric material film may be, for example, 0.5 to 10 nm, but is not limited thereto. Since the critical thickness exhibiting ferroelectric properties may vary for each ferroelectric material, the thickness of the above-mentioned ferroelectric material film may vary depending on the ferroelectric material.

[0045] For example, the gate dielectric film (132) may include a single ferroelectric material film. As another example, the gate dielectric film (132) may include a plurality of ferroelectric material films spaced apart from each other. The gate dielectric film (132) may have a stacked film structure in which a plurality of ferroelectric material films and a plurality of paraelectric material films are alternately stacked.

[0046] In some embodiments, an interface film (131) may be formed between each sheet pattern (111–116) and the gate dielectric film (132). The interface film (131) may include an oxide of each sheet pattern (111–116). For example, the interface film (131) may include silicon oxide, but is not limited thereto.

[0047] A gate spacer (136) may be formed on a substrate (100) and a field insulating film (105). The gate spacer (136) may extend along the side of the gate electrodes (134A, 134B). In some embodiments, a portion of the gate dielectric film (132) may be interposed between the gate electrodes (134A, 134B) and the gate spacer (136). For example, the gate dielectric film (132) may extend further along the inner side of the gate spacer (136). Such a gate dielectric film (132) may be formed through a replacement process, but is not limited thereto.

[0048] The gate spacer (136) may include, for example, at least one of silicon nitride, silicon oxynitride, silicon oxycarbonate, silicon boron nitride, silicon boron carbonitride, silicon oxycarbonate, and combinations thereof, but is not limited thereto.

[0049] The gate capping pattern (138) may cover at least a portion of the upper surface of the gate electrodes (134A, 134B). For example, the gate capping pattern (138) may extend along the upper surface of the gate electrodes (134A, 134B). Only the upper surface of the gate spacer (136) is shown to be placed in co-plane with the upper surface of the gate capping pattern (138), but this is merely exemplary. As another example, the gate capping pattern (138) may be formed to cover the upper surface of the gate spacer (136).

[0050] The gate capping pattern (138) may include, for example, at least one of silicon nitride, silicon oxynitride, silicon oxycarbonate, silicon boron nitride, silicon boron carbonitride, silicon oxycarbonate, and combinations thereof, but is not limited thereto.

[0051] The first epitaxial pattern (160A) may be formed on the upper surface of the substrate (100) and on the side surface of the gate structures (G1, G2). The first epitaxial pattern (160A) may be connected to the first active pattern (110A). For example, the first to third sheet patterns (111 to 113) may each penetrate the gate structures (G1, G2) and be connected to the first epitaxial pattern (160A). The first epitaxial pattern (160A) may be electrically isolated from the gate electrodes (134A, 134B) by a gate dielectric film (132) and / or a gate spacer (136). This first epitaxial pattern (160A) can be provided as a source / drain region of a field-effect transistor including a first active pattern (110A) and gate structures (G1, G2).

[0052] The first epitaxial pattern (160A) may include an epitaxial layer grown using the substrate (100; or pin pattern (110F)) and the first active pattern (110A) as a seed layer. For example, the first epitaxial pattern (160A) may be an epitaxial layer grown by an epitaxial growth method from the upper surface of the substrate (100) and the side of the first active pattern (110A).

[0053] A second epitaxial pattern (160B) may be formed on the upper surface of the first epitaxial pattern (160A) and on the side surface of the gate structures (G1, G2). The second epitaxial pattern (160B) may be connected to the second active pattern (110B). For example, the fourth to sixth sheet patterns (114–116) may each penetrate the gate structures (G1, G2) and be connected to the second epitaxial pattern (160B). The second epitaxial pattern (160B) may be electrically isolated from the gate electrodes (134A, 134B) by a gate dielectric film (132) and / or a gate spacer (136). This second epitaxial pattern (160B) can be provided as a source / drain region of a field-effect transistor including a second active pattern (110B) and gate structures (G1, G2).

[0054] The second epitaxial pattern (160B) may include an epitaxial layer grown using the second active pattern (110B) and the semiconductor film (150) described later as a seed layer. For example, the second epitaxial pattern (160B) may be an epitaxial layer grown by an epitaxial growth method from the upper surface of the semiconductor film (150) and the side of the second active pattern (110B).

[0055] The first epitaxial pattern (160A) and the second epitaxial pattern (160B) are each depicted as single films, but this is merely illustrative. As another example, the first epitaxial pattern (160A) and the second epitaxial pattern (160B) may each be formed as multiple films containing impurities of different concentrations.

[0056] In some embodiments, the first epitaxial pattern (160A) and the second epitaxial pattern (160B) may have different conductivity types. For example, the first epitaxial pattern (160A) may have a first conductivity type, and the second epitaxial pattern (160B) may have a second conductivity type different from the first conductivity type. For example, the first conductivity type may be p-type and the second conductivity type may be n-type. In this case, the first active pattern (110A) may be used as the channel region of a PFET, and the second active pattern (110B) may be used as the channel region of an NFET. However, this is merely exemplary, and it is obvious that the first conductivity type may be n-type and the second conductivity type may be p-type.

[0057] When the device formed by the first active pattern (110A) or the second active pattern (110B) is p-type (e.g., PFET), the first epitaxial pattern (160A) or the second epitaxial pattern (160B) may include p-type impurities or impurities to prevent the diffusion of p-type impurities. For example, the first epitaxial pattern (160A) or the second epitaxial pattern (160B) may include at least one of B, C, In, Ga, Al, and combinations thereof.

[0058] In some embodiments, when the device formed by the first active pattern (110A) or the second active pattern (110B) is p-type (e.g., PFET), the first epitaxial pattern (160A) or the second epitaxial pattern (160B) may include a compressive stress material. For example, when the first active pattern (110A) or the second active pattern (110B) is a silicon pattern, the first epitaxial pattern (160A) or the second epitaxial pattern (160B) may include a material having a lattice constant larger than that of silicon (Si) (e.g., silicon germanium (SiGe)). The compressive stress material may apply compressive stress to the first active pattern (110A) or the second active pattern (110B) to improve the carrier mobility of the channel region.

[0059] When the device formed by the first active pattern (110A) or the second active pattern (110B) is an n-type (e.g., NFET), the first epitaxial pattern (160A) or the second epitaxial pattern (160B) may include n-type impurities or impurities to prevent the diffusion of n-type impurities. For example, the first epitaxial pattern (160A) or the second epitaxial pattern (160B) may include at least one of P, Sb, As, and combinations thereof.

[0060] In some embodiments, when the device formed by the first active pattern (110A) or the second active pattern (110B) is n-type (e.g., NFET), the first epitaxial pattern (160A) or the second epitaxial pattern (160B) may include a tensile stress material. For example, when the first active pattern (110A) or the second active pattern (110B) is a silicon pattern, the first epitaxial pattern (160A) or the second epitaxial pattern (160B) may include a material having a smaller lattice constant than silicon (Si) (e.g., silicon carbide (SiC)). The tensile stress material may apply tensile stress to the first active pattern (110A) or the second active pattern (110B) to improve the carrier mobility of the channel region.

[0061] An insulating pattern (140) may be interposed between the first epitaxial pattern (160A) and the second epitaxial pattern (160B). Additionally, the insulating pattern (140) may be formed on the side of the separation pattern (120). The insulating pattern (140) may include at least one insulating material, for example, silicon oxide, silicon nitride, silicon oxynitride, and combinations thereof, but is not limited thereto. Such an insulating pattern (140) can electrically separate the first epitaxial pattern (160A) and the second epitaxial pattern (160B).

[0062] In some embodiments, the insulating pattern (140) may be formed lower than the separation pattern (120). For example, with respect to the upper surface of the substrate (100), the height of the upper surface of the insulating pattern (140) may be lower than the height of the upper surface of the separation pattern (120). In this case, the height of the upper surface of the insulating pattern (140) may be lower than the height of the lower surface of the lowest sheet pattern among the upper sheet patterns (e.g., the fourth sheet pattern (114)).

[0063] A liner film (142) may be interposed between the separation pattern (120) and the insulation pattern (140). For example, the liner film (142) may extend conformally along the side of the insulation pattern (140). The liner film (142) may comprise at least one insulating material, for example, silicon oxide, silicon nitride, silicon oxynitride, and combinations thereof, but is not limited thereto.

[0064] In some embodiments, the liner film (142) may comprise an insulating material different from the insulating pattern (140). For example, the insulating pattern (140) may comprise silicon oxide, and the liner film (142) may comprise silicon nitride.

[0065] Although it is illustrated that the upper surface of the liner film (142) is positioned in a co-plane with the upper surface of the insulating pattern (140), this is merely illustrative. The upper surface of the liner film (142) may be higher or lower than the upper surface of the insulating pattern (140). Additionally, although it is illustrated that the lower surface of the liner film (142) is positioned in a co-plane with the lower surface of the insulating pattern (140), this is merely illustrative. The lower surface of the liner film (142) may be higher or lower than the lower surface of the insulating pattern (140).

[0066] The semiconductor film (150) may be interposed between the insulating pattern (140) and the second epitaxial pattern (160B). The semiconductor film (150) may extend along the upper surface of the insulating pattern (140). For example, the semiconductor film (150) may extend conformally along the upper surface of the insulating pattern (140) and the upper surface of the liner film (142).

[0067] The semiconductor film (150) can function as a seed layer for forming a second epitaxial pattern (160B) by an epitaxial growth method. For example, as described above, the second epitaxial pattern (160B) may be an epitaxial layer grown by an epitaxial growth method from the upper surface of the semiconductor film (150) and the side of the second active pattern (110B).

[0068] In some embodiments, the upper surface (160U) of the second epitaxial pattern (160B) may include a flat surface (160U1), a first inclined surface (160U2), and a second inclined surface (160U3). The flat surface (160U1) may be parallel to the upper surface of the substrate (100). The first inclined surface (160U2) may extend from one side of the flat surface (160U1), and the second inclined surface (160U3) may extend from the other side of the flat surface (160U1). For example, the second epitaxial pattern (160B) between the first gate structure (G1) and the second gate structure (G2) may include a first inclined surface (160U2) between the first gate structure (G1) and the flat surface (160U1), and a second inclined surface (160U3) between the second gate structure (G2) and the flat surface (160U1). The first inclined surface (160U2) and the second inclined surface (160U3) may each form an obtuse angle with the flat surface (160U1). For example, the first inclined surface (160U2) may form a first obtuse angle (θ1) with the flat surface (160U1), and the second inclined surface (160U3) may form a second obtuse angle (θ2) with the flat surface (160U1). The shape of the upper surface (160U) of the second epitaxial pattern (160B) may be attributed to the fact that the second epitaxial pattern (160B) is formed from the second active pattern (110B) and the semiconductor film (150) by an epitaxial growth method.

[0069] Additionally, as the second epitaxial pattern (160B) grows from the upper surface of the semiconductor film (150), the lower surface (160L) of the second epitaxial pattern (160B) may come into contact with the upper surface of the semiconductor film (150) in its entirety. For example, as illustrated, when the upper surface of the semiconductor film (150) is parallel to the upper surface of the substrate (100), the lower surface (160L) of the second epitaxial pattern (160B) may also be parallel to the upper surface of the substrate (100).

[0070] In some embodiments, the semiconductor film (150) may comprise a polycrystalline semiconductor material. For example, the semiconductor film (150) may comprise a polysilicon (poly-Si) film. In this case, the second epitaxial pattern (160B) formed from the semiconductor film (150) by an epitaxial growth method may comprise a polycrystalline film. For example, the lower portion of the second epitaxial pattern (160B) adjacent to the semiconductor film (150) may be polycrystalline.

[0071] An interlayer insulating film (190) may be formed on the substrate (100) and the field insulating film (105). The interlayer insulating film (190) may be formed to fill the space on the outer surface of the gate spacer (136). For example, the interlayer insulating film (190) may cover the outer surface of the gate spacer (136) and the upper surface of the second epitaxial pattern (160B). Although the interlayer insulating film (190) is illustrated only as exposing the upper surface of the gate structures (G1, G2), this is merely exemplary, and the interlayer insulating film (190) may also cover the upper surface of the gate structures (G1, G2).

[0072] The interlayer insulating film (190) may include, for example, at least one of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbonate, silicon boron nitride, silicon boron carbonitride, silicon oxycarbonate, and a low dielectric constant material. The above low dielectric constant material may include, for example, at least one of FOX (Flowable Oxide), TOSZ (Torene SilaZene), USG (Undoped Silica Glass), BSG (Borosilica Glass), PSG (PhosphoSilica Glass), BPSG (BoroPhosphoSilica Glass), PETEOS (Plasma Enhanced Tetra Ethyl Ortho Silicate), FSG (Fluoride Silicate Glass), CDO (Carbon Doped Silicon Oxide), Xerogel, Aerogel, Amorphous Fluorinated Carbon, OSG (Organo Silicate Glass), Parylene, BCB (bis-benzocyclobutenes), SiLK, polyimide, porous polymeric material, and combinations thereof, but is not limited thereto.

[0073] The first source / drain contact (180A) may be electrically connected to the first epitaxial pattern (160A). For example, the first source / drain contact (180A) may be interposed between the first epitaxial pattern (160A) and the insulating pattern (140) and may be in contact with the upper surface of the first epitaxial pattern (160A). Although the liner film (142) is illustrated as extending only from the upper surface of the first source / drain contact (180A), this is merely exemplary. As another example, the liner film (142) may extend along a portion of the side of the first source / drain contact (180A).

[0074] In some embodiments, the bottom surface of the first source / drain contact (180A) may be formed lower than the top surface of the first epitaxial pattern (160A). For example, as shown in FIG. 2, the top surface of the first epitaxial pattern (160A) may include a contact recess (160R), and at least a portion of the first source / drain contact (180A) may be formed to fill the contact recess (160R).

[0075] The second source / drain contact (180B) may be electrically connected to the second epitaxial pattern (160B). For example, the second source / drain contact (180B) may extend in a third direction (Z1) to penetrate the interlayer insulating film (190) and may come into contact with the upper surface of the second epitaxial pattern (160B). Only the lower surface of the second source / drain contact (180B) is shown being formed lower than the flat surface (160U1), but this is merely illustrative. As another example, the lower surface of the second source / drain contact (180B) may be positioned in a co-plane with the flat surface (160U1). As yet another example, the second source / drain contact (180B) may penetrate the second epitaxial pattern (160B).

[0076] Although the first source / drain contact (180A) and the second source / drain contact (180B) are each illustrated as having a single film, this is merely illustrative, and it is understood that the first source / drain contact (180A) and the second source / drain contact (180B) may each be formed by stacking multiple conductive layers. For example, the first source / drain contact (180A) and the second source / drain contact (180B) may each include a silicide film and a filling conductive film that are stacked in sequence. The silicide film may include, for example, platinum (Pt), nickel (Ni), or cobalt (Co), but is not limited thereto. The filling conductive film may include, for example, titanium (Ti), titanium nitride (TiN), tungsten (W), aluminum (Al), or copper (Cu), but is not limited thereto.

[0077] FIGS. 4 to 6 are comparative drawings for explaining the effects of a semiconductor device according to some embodiments. For convenience of explanation, parts that overlap with those described above using FIGS. 1 to 3 are briefly explained or omitted.

[0078] As semiconductor devices become increasingly highly integrated, semiconductor devices utilizing stacked multi-gate transistors are being studied to implement more semiconductor devices in the same area. Such a semiconductor device may include a lower multi-gate transistor on a substrate and an upper multi-gate transistor stacked on the lower multi-gate transistor.

[0079] Meanwhile, an epitaxial pattern may be provided as the source / drain region of the multi-gate transistor. However, unlike the epitaxial pattern of the lower multi-gate transistor, the epitaxial pattern of the upper multi-gate transistor may be formed in an unmerged form due to the absence of a substrate. Specifically, referring to FIGS. 4 to 6, the first epitaxial pattern (160A) may be formed in a merged form as it grows from the upper surface of the substrate (100) and the side of the first active pattern (110A) (i.e., three-sided growth). In contrast, the second epitaxial pattern (160B) may be formed in an unmerged form as it grows only from the side of the second active pattern (110B) (i.e., two-sided growth).

[0080] For example, the second epitaxial pattern (160B) between the first gate structure (G1) and the second gate structure (G2) may include a first sub-pattern (161) and a second sub-pattern (162). The first sub-pattern (161) may be grown from the side of the second active pattern (110B) intersecting the first gate structure (G1), and the second sub-pattern (162) may be grown from the side of the second active pattern (110B) intersecting the second gate structure (G2). Additionally, the first sub-pattern (161) and the second sub-pattern (162) may be spaced apart in the first direction (X1) to form an unmerged second epitaxial pattern (160B).

[0081] In some embodiments, the first sub-pattern (161) and the second sub-pattern (162) may each include a lower inclined surface (161L, 162L) and an upper inclined surface (161U, 162U). The lower inclined surface (161L, 162L) may form an acute angle with the upper surface of the substrate (100), and the upper inclined surface (161U, 162U) may form an obtuse angle with the upper surface of the substrate (100). The shape of the second epitaxial pattern (160B) may be due to the second epitaxial pattern (160B) being formed from the second active pattern (110B) by an epitaxial growth method.

[0082] The second epitaxial pattern (160B) formed in an unmerged form can cause various problems during the manufacturing process of the semiconductor device.

[0083] For example, as illustrated in FIG. 4, the second source / drain contact (180B) may not be electrically connected to the unmerged second epitaxial pattern (160B). For example, the second source / drain contact (180B) may be formed between the first sub-pattern (161) and the second sub-pattern (162) and may not be in contact with at least one of the first sub-pattern (161) and the second sub-pattern (162).

[0084] To ensure a connection between the second source / drain contact (180B) and the unmerged second epitaxial pattern (160B), the width of the second source / drain contact (180B) may be increased as shown in FIG. 5. However, this second source / drain contact (180B) has the problem of excessively increasing parasitic capacitance with the gate structures (G1, G2).

[0085] As another example, as illustrated in FIG. 6, the second source / drain contact (180B) may be shorted to the first source / drain contact (180A). For example, in the etching process to form the second source / drain contact (180B), the unmerged second epitaxial pattern (160B) may not provide an end point for the etching process. Accordingly, the interlayer insulating film (190) and the insulating pattern (140) may be penetrated, so that a portion of the first source / drain contact (180A) is exposed, and the second source / drain contact (180B) in contact with the exposed first source / drain contact (180A) may be formed.

[0086] However, according to some embodiments, the semiconductor device may effectively prevent the formation of the aforementioned unmerged second epitaxial pattern (160B) by providing a semiconductor film (150). Specifically, as described above using FIGS. 1 to 3, the second epitaxial pattern (160B) may be grown on three sides, similar to the first epitaxial pattern (160A), as it grows from the upper surface of the semiconductor film (150) and the side of the second active pattern (110B). Accordingly, the second epitaxial pattern (160B) may be provided in a merged form, similar to the first epitaxial pattern (160A).

[0087] FIGS. 7 to 11 are various cross-sectional views for illustrating semiconductor devices according to some embodiments. For convenience of explanation, parts that overlap with those described above using FIGS. 1 to 3 are briefly described or omitted.

[0088] Referring to FIG. 7, in a semiconductor device according to some embodiments, a portion of the semiconductor film (150) extends further along the side of the second active pattern (110B) and / or the side of the gate structures (G1, G2).

[0089] For example, the semiconductor film (150) may extend along the upper surface of the insulating pattern (140), the upper surface of the liner film (142), a portion of the side of the separation pattern (120), a portion of the side of the second active pattern (110B), and a portion of the side of the gate structures (G1, G2).

[0090] In some embodiments, the thickness of the semiconductor film (150) extending along the side of the second active pattern (110B) and / or the side of the gate structures (G1, G2) may be smaller than the thickness of the semiconductor film (150) extending along the upper surface of the insulating pattern (140) and / or the upper surface of the liner film (142). In some embodiments, the thickness of the semiconductor film (150) extending along the side of the second active pattern (110B) and / or the side of the gate structures (G1, G2) may decrease as it moves away from the upper surface of the insulating pattern (140).

[0091] Referring to FIG. 8, in a semiconductor device according to some embodiments, the upper surface of the insulating pattern (140) is concave upward.

[0092] For example, the upper surface of the insulating pattern (140) may include a concave surface (140U). The semiconductor film (150) may extend conformally along the concave surface (140U). The lower surface (160L) of the second epitaxial pattern (160B) may come into contact with the upper surface of the semiconductor film (150) in its entirety. In this case, as illustrated, the lower surface (160L) of the second epitaxial pattern (160B) may be convex downward.

[0093] Referring to FIG. 9, in a semiconductor device according to some embodiments, the upper surface (160U) of the second epitaxial pattern (160B) is parallel to the upper surface of the substrate (100) in its entirety.

[0094] For example, the upper surface (160U) of the second epitaxial pattern (160B) may not include an inclined surface (e.g., the first inclined surface (160U2) or the second inclined surface (160U3) of FIG. 2). In some embodiments, the second epitaxial pattern (160B) may be an elevated source / drain region. That is, the upper surface (160U) of the second epitaxial pattern (160B) may be formed higher than the top surface of the second active pattern (110B).

[0095] Referring to FIG. 10, in a semiconductor device according to some embodiments, the separation pattern (120) is formed as a multilayer film.

[0096] For example, the separation pattern (120) may include a first insulating film (122) and a second insulating film (124) alternately stacked on a first active pattern (110A). The first insulating film (122) and the second insulating film (124) may each include an insulating material, for example, at least one of silicon oxide, silicon nitride, silicon oxynitride, and combinations thereof, but are not limited thereto. The first insulating film (122) and the second insulating film (124) may include different materials. For example, the first insulating film (122) may include silicon nitride, and the second insulating film (124) may include silicon oxide.

[0097] Referring to FIG. 11, in a semiconductor device according to some embodiments, each gate structure (G1, G2) further includes an internal spacer (137).

[0098] An internal spacer (137) may be formed on the side of a gate electrode (134A, 134B) interposed between sheet patterns (e.g., first to sixth sheet patterns (111 to 116)). In FIG. 11, only the internal spacer (137) formed on the side of a gate electrode (134A, 134B) between upper sheet patterns (e.g., fourth to sixth sheet patterns (114 to 116)) is illustrated, but this is merely exemplary. As another example, the internal spacer (137) may be formed on the side of a gate electrode (134A, 134B) between lower sheet patterns (e.g., first to third sheet patterns (111 to 113)).

[0099] In some embodiments, the internal spacer (137) may be formed on the side of the gate electrode (134A, 134B) of the PFET. For example, the first active pattern (110A) may be used as the channel region of the PFET, and the second active pattern (110B) may be used as the channel region of the NFET. In this case, as illustrated, the internal spacer (137) may be formed on the side of the gate electrode (134A, 134B) between the upper sheet patterns (e.g., fourth to sixth sheet patterns (114–116)) and may not be formed on the side of the gate electrode (134A, 134B) between the lower sheet patterns (e.g., first to third sheet patterns (111–113)).

[0100] FIG. 12 is a schematic layout diagram for explaining a semiconductor device according to some embodiments. FIG. 13 is a cross-sectional view taken along A1-A1 and A2-A2 of FIG. 12. For convenience of explanation, parts that overlap with those described above using FIG. 1 to 11 are briefly described or omitted.

[0101] Referring to FIGS. 12 and 13, in a semiconductor device according to some embodiments, the substrate (100) includes a first region (I) and a second region (II).

[0102] The first region (I) and the second region (II) may be regions separated from each other or regions connected to each other. In some embodiments, the first region (I) may be a region implemented with a lower integration density than the second region (II). For example, the first region (I) may be an input / output (I / O) region, and the second region (II) may be a logic region or a static RAM (SRAM) region. As another example, the first region (I) may be an extra gate FET (EGFET) region of a logic device, and the second region (II) may be a single gate FET (SGFET) region of a logic device.

[0103] A first active pattern (110A), a second active pattern (110B), a first gate structure (G1), a second gate structure (G2), a first epitaxial pattern (160A), a second epitaxial pattern (160B), a semiconductor film (150), a first source / drain contact (180A) and a second source / drain contact (180B) may be formed on a first region (I) of a substrate (100).

[0104] On the second region (II) of the substrate (100), a third active pattern (210A), a fourth active pattern (210B), a third gate structure (G3), a fourth gate structure (G4), a third epitaxial pattern (260A), a fourth epitaxial pattern (260B), a third source / drain contact (280A), and a fourth source / drain contact (280B) may be formed.

[0105] The third active pattern (210A) and the fourth active pattern (210B) may be arranged sequentially on the substrate (100). The third active pattern (210A) may be spaced apart from the substrate (100) on the substrate (100). The fourth active pattern (210B) may be spaced apart from the first active pattern (110A) on the first active pattern (110A). The third active pattern (210A) and the fourth active pattern (210B) may each extend in a fourth direction (X2) parallel to the upper surface of the substrate (100). Additionally, the third active pattern (210A) and the fourth active pattern (210B) may overlap in a direction intersecting the upper surface of the substrate (100) (e.g., a sixth direction (Z2)). Since the third active pattern (210A) and the fourth active pattern (210B) may be similar to the first active pattern (110A) and the second active pattern (110B), respectively, a detailed description is omitted below.

[0106] In some embodiments, the width (W11) of the first and second active patterns (110A, 110B) may be the same as the width (W21) of the third and fourth active patterns (210A, 210B). In this specification, "same" means not only completely identical but also includes fine differences that may occur due to process margins, etc. In some other embodiments, the width (W11) of the first and second active patterns (110A, 110B) may be different from the width (W21) of the third and fourth active patterns (210A, 210B).

[0107] The third gate structure (G3) and the fourth gate structure (G4) may each extend in a fifth direction (Y2) that intersects the fourth direction (X2) and is parallel to the upper surface of the substrate (100). Additionally, the third gate structure (G3) and the fourth gate structure (G4) may extend side by side, spaced apart from each other in the fourth direction (X2). Since the third gate structure (G3) and the fourth gate structure (G4) may each be similar to the first gate structure (G1) and the second gate structure (G2), a detailed description is omitted below.

[0108] In some embodiments, the channel length of the first and second active patterns (110A, 110B) may be greater than the channel length of the third and fourth active patterns (210A, 210B). For example, the width (W12) of the first and second gate structures (G1, G2) may be greater than the width (W22) of the third and fourth gate structures (G3, G4).

[0109] In some embodiments, the distance (D1) between the first and second gate structures (G1, G2) may be greater than the distance (D2) between the third and fourth gate structures (G3, G4). For example, the distance (D1) between the first and second gate structures (G1, G2) may be about 15 nm or more, and the distance (D2) between the third and fourth gate structures (G3, G4) may be about 15 nm or less. For example, the distance (D1) between the first and second gate structures (G1, G2) may be about 15 nm to about 30 nm, and the distance (D2) between the third and fourth gate structures (G3, G4) may be about 5 nm to about 15 nm.

[0110] A third epitaxial pattern (260A) may be formed on the upper surface of the substrate (100) and on the side surface of the gate structures (G3, G4). The third epitaxial pattern (260A) may be connected to a third active pattern (210A). This third epitaxial pattern (260A) may be provided as a source / drain region of a field-effect transistor comprising the third active pattern (210A) and the gate structures (G3, G4).

[0111] The third epitaxial pattern (260A) may include an epitaxial layer grown using the substrate (100) and the third active pattern (210A) as a seed layer. For example, the third epitaxial pattern (260A) may be an epitaxial layer grown by an epitaxial growth method from the upper surface of the substrate (100) and the side of the third active pattern (210A). Since the third epitaxial pattern (260A) may be similar to the first epitaxial pattern (160A), a detailed description is omitted below.

[0112] A fourth epitaxial pattern (260B) may be formed on the upper surface of the third epitaxial pattern (260A) and on the side of the gate structures (G3, G4). The fourth epitaxial pattern (260B) may be connected to the fourth active pattern (210B). This fourth epitaxial pattern (260B) may be provided as a source / drain region of a field-effect transistor comprising the fourth active pattern (210B) and the gate structures (G3, G4).

[0113] In some embodiments, the semiconductor film (150) may be formed on the first region (I) and may not be formed on the second region (II). For example, the semiconductor film (150) may be interposed between the insulating pattern (140) and the second epitaxial pattern (160B), and may not be interposed between the insulating pattern (140) and the fourth epitaxial pattern (260B).

[0114] The fourth epitaxial pattern (260B) may include an epitaxial layer grown using the fourth active pattern (210B) as a seed layer. For example, the fourth epitaxial pattern (260B) may be an epitaxial layer grown by an epitaxial growth method from the side of the second active pattern (110B).

[0115] In some embodiments, the fourth epitaxial pattern (260B) may be formed in a merged form, similar to the third epitaxial pattern (260A). For example, as the distance (D2) between the third and fourth gate structures (G3, G4) decreases (e.g., to about 15 nm or less), the fourth epitaxial pattern (260B) may be formed in a merged form.

[0116] The third source / drain contact (280A) may be electrically connected to the third epitaxial pattern (260A). For example, the third source / drain contact (280A) may be interposed between the third epitaxial pattern (260A) and the insulating pattern (140) and may be in contact with the upper surface of the third epitaxial pattern (260A). Since the third source / drain contact (280A) may be similar to the first source / drain contact (180A), a detailed description is omitted below.

[0117] The fourth source / drain contact (280B) can be electrically connected to the fourth epitaxial pattern (260B). For example, the fourth source / drain contact (280B) can extend in the sixth direction (Z2) to penetrate the interlayer insulating film (190) and can come into contact with the upper surface of the fourth epitaxial pattern (260B). Since the fourth source / drain contact (280B) may be similar to the second source / drain contact (180B), a detailed description is omitted below.

[0118] The epitaxial pattern of the upper multi-gate transistor can be formed in an unmerged form as the distance between gate structures increases (e.g., about 15 nm or more). A semiconductor device according to some embodiments can effectively prevent the formation of an unmerged epitaxial pattern by having a semiconductor film (150) that is selectively formed in a region where the distance between gate structures is large (e.g., a first region (I)).

[0119] Hereinafter, a method for manufacturing a semiconductor device according to exemplary embodiments will be described with reference to FIGS. 1 to 32.

[0120] FIGS. 14 to 30 are intermediate step drawings for explaining a method of manufacturing a semiconductor device according to some embodiments. For convenience of explanation, parts that overlap with those described above using FIGS. 1 to 13 are briefly explained or omitted.

[0121] Referring to FIG. 14, a plurality of sheet patterns (111 to 116), a plurality of sacrifice patterns (310), and dummy gate structures (DG1, DG2) are formed on a substrate (100).

[0122] For example, a first material film and a second material film may be formed by alternately stacking on a substrate (100). Subsequently, a mask pattern extending in a first direction (X1) may be formed on the first material film and the second material film. Subsequently, a patterning process may be performed to pattern the first material film and the second material film using the mask pattern as an etching mask. The patterned second material film may form sheet patterns (111 to 116). The patterned first material film may form sacrificial patterns (310).

[0123] In some embodiments, the sheet patterns (111–116) and the sacrificial patterns (310) may have different etching selectivity ratios. For example, the sheet patterns (111–116) may include silicon (Si), and the sacrificial patterns (310) may include silicon germanium (SiGe).

[0124] In some embodiments, during the process of patterning the first material film and the second material film, a portion of the substrate (100) may be etched to form a pin pattern (110F).

[0125] Next, dummy gate structures (DG1, DG2) can be formed. The dummy gate structures (DG1, DG2) can intersect with sheet patterns (111–116) and sacrifice patterns (310). For example, the dummy gate structures (DG1, DG2) can extend in a second direction (Y1). The sheet patterns (111–116) and sacrifice patterns (310) can each extend in a first direction (X1) and penetrate the dummy gate structures (DG1, DG2).

[0126] Dummy gate structures (DG1, DG2) may include, for example, a dummy gate dielectric film (332), a dummy gate electrode (334), and a gate spacer (136) that are stacked in sequence. The dummy gate dielectric film (332) and the dummy gate electrode (334) may be formed by a patterning process using a mask pattern (350) as an etching mask. For example, a dielectric film and an electrode film that are stacked in sequence may be formed on a substrate (100). Subsequently, a mask pattern (350) extending in a second direction (Y1) may be formed on the electrode film. Subsequently, a patterning process may be performed to pattern the dielectric film and the electrode film using the mask pattern (350) as an etching mask. The patterned dielectric film may form a dummy gate dielectric film (332), and the patterned electrode film may form a dummy gate electrode (334). The gate spacer (136) can be extended along the side of the dummy gate electrode (334).

[0127] The dummy gate electrode (334) may comprise a material having a different etching selectivity than the sheet patterns (111–116) and the sacrifice patterns (310). For example, the dummy gate electrode (334) may comprise polysilicon (poly-Si).

[0128] Referring to FIG. 15, a first recess process is performed on the sheet patterns (111–116) and the sacrifice patterns (310).

[0129] As the above first recess process is performed, a portion of the sheet patterns (111–116) and a portion of the sacrifice patterns (310) disposed on the outside of the dummy gate structures (DG1, DG2) may be removed. Accordingly, a first recess (R1) may be formed that exposes the sides of the sheet patterns (111–116) and the sides of the sacrifice patterns (310).

[0130] Referring to FIG. 16, a first peeling sacrificial membrane (320) is formed.

[0131] A first filling sacrificial layer (320) may be formed on the result of FIG. 15. Additionally, the first filling sacrificial layer (320) may fill the first recess (R1) of FIG. 15. The first filling sacrificial layer (320) may comprise a material having an etching selectivity different from that of the sheet patterns (111–116) and the sacrificial patterns (310). For example, the first filling sacrificial layer (320) may comprise a spin-on hardmask (SOH).

[0132] Referring to FIG. 17, a second recess process is performed on the first filling sacrificial film (320) to form a preliminary liner film (142p).

[0133] As the second recess process is performed, the sides of the upper sheet patterns (114–116) may be exposed. For example, the upper portion of the first filling sacrificial membrane (320) may be removed to form a second recess (R2) that exposes the sides of the upper sheet patterns (114–116). After the second recess process is performed, the first filling sacrificial membrane (320) may cover the sides of the lower sheet patterns (111–113). For example, the second recess (R2) may not expose the sides of the lower sheet patterns (111–113).

[0134] The pre-liner film (142p) may be laminated on the first filling sacrificial film (320) on which the second recess process is performed. For example, the pre-liner film (142p) may be conformally extended along the second recess (R2), the side of the separation pattern (120), the side of the second active pattern (110B), and the side of the gate structures (G1, G2).

[0135] Referring to FIG. 18, the upper surface of the first peeling sacrificial membrane (320) is exposed.

[0136] For example, a portion of the pre-liner film (142p) extending along the upper surface of the first filling sacrificial film (320) may be removed. Removing a portion of the pre-liner film (142p) may be performed, for example, by a dry etching process, but is not limited thereto. By doing so, the first filling sacrificial film (320) exposed from the pre-liner film (142p) may be formed. Additionally, the remaining pre-liner film (142p) may extend along the side of the separation pattern (120), the side of the second active pattern (110B), and the side of the gate structures (G1, G2).

[0137] Referring to FIG. 19, a first epitaxial pattern (160A) is formed by replacing the first filling sacrificial membrane (320).

[0138] For example, the first filling sacrificial layer (320) exposed from the preliminary liner layer (142p) may be removed. Removing the first filling sacrificial layer (320) may be performed, for example, by a wet etching process, but is not limited thereto. As the first filling sacrificial layer (320) is removed, the sides of the lower sheet patterns (111–113) and the top surface of the substrate (100; or pin pattern (110F)) may be exposed. Subsequently, a first epitaxial pattern (160A) that fills the area from which the first filling sacrificial layer (320) was removed may be formed. Specifically, an epitaxial growth process may be performed using the substrate (100; or pin pattern (110F)) and the first active pattern (110A) as a seed layer. Since the second active pattern (110B) can be protected by a preliminary liner film (142p), the second active pattern (110B) may not be used as a seed layer in the epitaxial growth process. Through this, a first epitaxial pattern (160A) connected to the first active pattern (110A) can be formed. As described above, the first epitaxial pattern (160A) can be provided in a merged form as it is formed by three-sided growth.

[0139] Referring to FIG. 20, a liner film (142), a sacrificial contact pattern (380), and an insulating pattern (140) are formed on the first epitaxial pattern (160A).

[0140] For example, the preliminary liner film (142p) of FIG. 19 may be removed. Subsequently, the liner film (142), the sacrificial contact pattern (380), and the insulating pattern (140) may be stacked in sequence. For example, the liner film (142) may extend conformally along the top surface of the first epitaxial pattern (160A), the side of the separation pattern (120), the side of the second active pattern (110B), and the side of the gate structures (G1, G2). The sacrificial contact pattern (380) may fill a portion of the area on the liner film (142), and the insulating pattern (140) may fill the space formed by the sacrificial contact pattern (380).

[0141] Subsequently, a third recess process may be performed on the liner film (142) and the insulation pattern (140). As the third recess process is performed, the sides of the upper sheet patterns (114–116) may be exposed. In some embodiments, the upper surface of the insulation pattern (140) and / or the upper surface of the liner film (142) may be formed lower than the upper surface of the separation pattern (120).

[0142] Referring to FIG. 21, a semiconductor film (150) is formed.

[0143] The semiconductor film (150) may be formed on the upper surface of the insulating pattern (140) and / or the upper surface of the liner film (142). For example, the semiconductor film (150) may extend conformally along the upper surface of the insulating pattern (140) and the upper surface of the liner film (142). In some embodiments, the semiconductor film (150) may comprise a polycrystalline semiconductor material. For example, the semiconductor film (150) may comprise a polysilicon (poly-Si) film.

[0144] In some embodiments, the semiconductor film (150) may be formed by a directional deposition process. As the directional deposition process is performed, the semiconductor film (150) may be selectively formed on the upper surface of the result of FIG. 20. For example, the semiconductor film (150) may be selectively formed on the upper surface of the insulating pattern (140), the upper surface of the liner film (142), the upper surface of the mask pattern (350), and the upper surface of the gate spacer (136). Additionally, the semiconductor film (150) may not be formed on the side of the isolation pattern (120), the side of the second active pattern (110B), and the side of the sacrificial patterns (310).

[0145] Referring to FIG. 22, a second peeling sacrificial membrane (390) is formed.

[0146] A second filling sacrificial layer (390) may be formed on the result of FIG. 21. The second filling sacrificial layer (390) may include a material having an etching selectivity different from that of the sheet patterns (111–116), sacrificial patterns (310), and semiconductor film (150). For example, the second filling sacrificial layer (390) may include a spin-on hardmask (SOH).

[0147] Referring to Fig. 23, a flattening process is performed.

[0148] As the above planarization process is performed, the semiconductor film (150) on the upper surface of the mask pattern (350) can be removed. For example, the planarization process can remove the upper surface of the second filling sacrificial film (390) and the upper surface of the semiconductor film (150) by using the upper surface of the mask pattern (350) as an end point. The planarization process may include, for example, a Chemical Mechanical Polishing (CMP) process, but is not limited thereto.

[0149] Referring to FIG. 24, the second peeling sacrificial membrane (390) is selectively removed.

[0150] As the second filling sacrificial film (390) is removed, the sides of the upper sheet patterns (114–116) and the upper surface of the semiconductor film (150) may be exposed.

[0151] Referring to FIG. 25, a second epitaxial pattern (160B) is formed.

[0152] Specifically, an epitaxial growth process can be performed using the semiconductor film (150) and the second active pattern (110B) as a seed layer. Through this, a second epitaxial pattern (160B) connected to the second active pattern (110B) can be formed. As described above, the second epitaxial pattern (160B) can be provided in a merged form as it is formed by three-sided growth, just like the first epitaxial pattern (160A).

[0153] Referring to FIG. 26, the dummy gate dielectric film (332) and the dummy gate electrode (334) are removed.

[0154] For example, an interlayer insulating film (190) may be formed on the substrate (100). The interlayer insulating film (190) may be formed to fill the space on the outer surface of the gate spacer (136). For example, the interlayer insulating film (190) may cover the outer surface of the gate spacer (136) and the upper surface of the second epitaxial pattern (160B).

[0155] Subsequently, the dummy gate dielectric film (332), dummy gate electrode (334), and mask pattern (350) exposed by the interlayer insulating film (190) and the gate spacer (136) can be removed. As the dummy gate dielectric film (332) and the dummy gate electrode (334) are removed, the sheet patterns (111–116) and sacrificial patterns (310) disposed inside the gate spacer (136) can be exposed.

[0156] Referring to FIG. 27, the sacrifice patterns (310) are removed.

[0157] As described above, the sheet patterns (111–116) and the sacrifice patterns (310) may have different etching selectivity ratios. Accordingly, the sacrifice patterns (310) may be selectively removed. As the sacrifice patterns (310) are removed, sheet patterns (111–116) that are sequentially stacked and spaced apart from each other may be formed on the substrate (100).

[0158] Referring to FIG. 28, gate structures (G1, G2) are formed.

[0159] For example, an interface film (131) may be formed along the surface of the exposed sheet patterns (111–116). Subsequently, a gate dielectric film (132) may be formed conformally extending on the interface film (131). Subsequently, gate electrodes (134A, 134B) may be formed on the gate dielectric film (132). In some embodiments, the upper surface of the gate electrodes (134A, 134B) may be recessed. A gate capping pattern (138) may be extended along the upper surface of the recessed gate electrodes (134A, 134B). Accordingly, gate structures (G1, G2) comprising the interface film (131), the gate dielectric film (132), the gate electrodes (134A, 134B), the gate spacer (136), and the gate capping pattern (155) may be formed.

[0160] Referring to FIG. 29, a first epitaxial pattern (160A) is exposed.

[0161] For example, the sacrificial contact pattern (380) may be removed. Additionally, as the sacrificial contact pattern (380) is removed, at least a portion of the exposed liner film (142) may be removed. Through this, a gap (380G) exposing the upper surface of the first epitaxial pattern (160A) may be formed between the first epitaxial pattern (160A) and the insulating pattern (140).

[0162] Referring to FIG. 30, a first source / drain contact (180A) is formed.

[0163] The first source / drain contact (180A) can be formed to fill the gap (380G) of FIG. 29. By doing so, the first source / drain contact (180A) can be formed to be electrically connected to the first epitaxial pattern (160A).

[0164] Next, referring to FIG. 2, a second source / drain contact (180B) is formed.

[0165] The second source / drain contact (180B) can penetrate the interlayer insulating film (190) and be electrically connected to the second epitaxial pattern (160B). Through this, the semiconductor device described above can be manufactured using FIGS. 1 to 3.

[0166] FIG. 31 is an intermediate step diagram for explaining a method for manufacturing a semiconductor device according to some embodiments. For convenience of explanation, parts that overlap with those described above using FIG. 1 to 30 are briefly explained or omitted. For reference, FIG. 31 is an intermediate step diagram for explaining steps after FIG. 20.

[0167] Referring to FIG. 31, a semiconductor film (150) is formed.

[0168] As illustrated, a portion of the semiconductor film (150) may be further extended along the side of the second active pattern (110B) and / or the side of the dummy gate structures (DG1, DG2). For example, the semiconductor film (150) may be extended along the upper surface of the insulating pattern (140), the upper surface of the liner film (142), a portion of the side of the isolation pattern (120), a portion of the side of the second active pattern (110B), and a portion of the side of the dummy gate structures (DG1, DG2).

[0169] In some embodiments, the semiconductor film (150) may be formed by a directional deposition process. Depending on the characteristics of the directional deposition process, a portion of the semiconductor film (150) may be formed not only on the upper surface of the result of FIG. 20 but also on at least a portion of the side surface.

[0170] Next, the steps described above can be performed using FIGS. 22 to 30 and FIG. 2. Through this, the semiconductor device described above can be manufactured using FIG. 7.

[0171] FIG. 32 is an intermediate step diagram for explaining a method for manufacturing a semiconductor device according to some embodiments. For convenience of explanation, parts that overlap with those described above using FIG. 1 to 30 are briefly explained or omitted. For reference, FIG. 32 is an intermediate step diagram for explaining steps after FIG. 19.

[0172] Referring to FIG. 32, a third recess process is performed on the liner film (142) and the insulation pattern (140).

[0173] As illustrated, as the third recess process is performed, the upper surface of the insulation pattern (140) may include a concave surface (140U).

[0174] Next, the steps described above can be performed using FIGS. 21 to 30 and FIG. 2. Through this, the semiconductor device described above can be manufactured using FIG. 8.

[0175] Although embodiments of the present invention have been described above with reference to the attached drawings, the present invention is not limited to the above embodiments and can be manufactured in various different forms, and those skilled in the art will understand that the present invention can be implemented in other specific forms without changing the technical concept or essential features of the present invention. Therefore, the embodiments described above should be understood as illustrative in all respects and not restrictive. Explanation of the symbols

[0176] 100: Substrate 105: Field insulating film 110A: 1st active pattern 110B: 2nd active pattern 110F: Pin pattern 120: Separation pattern 131: Interface film 132: Gate dielectric film 134A, 134B: Gate electrodes 136: Gate spacer 138: Gate capping pattern 140: Insulation pattern 142: Liner film 150: Semiconductor film 160A: 1st Epitaxial Pattern 160B: 2nd Epitaxial Pattern 180A: 1st Source / Drain Contact 180B: 2nd Source / Drain Contact 190: Interlayer insulation film

Claims

Claim 1 A substrate; a first active pattern extending in a first direction on the substrate; a second active pattern laminated on the first active pattern and extending in the first direction; a first gate structure extending in a second direction intersecting the first direction and intersecting the first active pattern and the second active pattern; a second gate structure spaced apart from the first gate structure in the first direction and extending in the second direction and intersecting the first active pattern and the second active pattern; a first epitaxial pattern connected to the first active pattern between the first gate structure and the second gate structure; a second epitaxial pattern connected to the second active pattern between the first gate structure and the second gate structure; an insulating pattern interposed between the first epitaxial pattern and the second epitaxial pattern; A semiconductor device comprising a semiconductor film extending along the upper surface of the insulating pattern between the insulating pattern and the second epitaxial pattern, wherein the semiconductor film is in contact with the upper surface of the insulating pattern. Claim 2 A semiconductor device according to claim 1, wherein the semiconductor film comprises a polysilicon film. Claim 3 A semiconductor device according to claim 1, wherein the distance between the first gate structure and the second gate structure is 15 nm or more. Claim 4 A semiconductor device according to claim 1, wherein the second epitaxial pattern comprises a polycrystalline film. Claim 5 A semiconductor device according to claim 1, wherein the upper surface of the second epitaxial pattern comprises a flat surface parallel to the upper surface of the substrate, a first inclined surface between the first gate structure and the flat surface, and a second inclined surface between the second gate structure and the flat surface, wherein the first inclined surface and the second inclined surface each form an obtuse angle with the flat surface. Claim 6 A semiconductor device according to claim 5, wherein the lower surface of the second epitaxial pattern is parallel to the upper surface of the substrate. Claim 7 A semiconductor device according to claim 1, wherein the second epitaxial pattern comprises an epitaxial layer grown using the second active pattern and the semiconductor film as a seed layer. Claim 8 A semiconductor device comprising: a substrate; a first active pattern extending in a first direction on the substrate; a second active pattern stacked on the first active pattern and extending in the first direction; a gate structure extending in a second direction intersecting the first direction on the substrate, through which the first active pattern and the second active pattern penetrate; a first epitaxial pattern connected to the first active pattern on a side of the gate structure; a second epitaxial pattern connected to the second active pattern on a side of the gate structure; an insulating pattern interposed between the first epitaxial pattern and the second epitaxial pattern; and a semiconductor film interposed between the insulating pattern and the second epitaxial pattern, wherein the second epitaxial pattern comprises an epitaxial layer grown using the second active pattern and the semiconductor film as a seed layer, and the semiconductor film contacts the upper surface of the insulating pattern. Claim 9 A semiconductor device according to claim 8, wherein the semiconductor film is formed by a directional deposition process. Claim 10 A substrate; a plurality of lower sheet patterns sequentially stacked on the substrate and spaced apart from each other, each extending in a first direction; a plurality of upper sheet patterns sequentially stacked on the plurality of lower sheet patterns and spaced apart from each other, each extending in the first direction; a separation pattern interposed between the plurality of lower sheet patterns and the plurality of upper sheet patterns; a gate structure extending in a second direction intersecting the first direction on the substrate, through which the plurality of lower sheet patterns and the plurality of upper sheet patterns are each penetrated; a first epitaxial pattern having a first conductivity type connected to the plurality of lower sheet patterns on a side of the gate structure; a second epitaxial pattern having a second conductivity type different from the first conductivity type connected to the plurality of upper sheet patterns on a side of the gate structure; and an insulating pattern interposed between the first epitaxial pattern and the second epitaxial pattern on a side of the separation pattern. A semiconductor device comprising a polysilicon film extending along the upper surface of the insulating pattern between the insulating pattern and the second epitaxial pattern, wherein the polysilicon film is in contact with the upper surface of the insulating pattern.

Images