Integrated circuit having latch with transistors of different gate widths

Abstract

The integrated circuit includes a first inverter, a first transmission gate, and a second inverter composed of a wide Type 1 transistor and a wide Type 2 transistor. The integrated circuit also includes a first clock inverter and a second clock inverter composed of a narrow Type 1 transistor and a narrow Type 2 transistor. The master latch is composed of the first inverter and the first clock inverter. The slave latch is composed of the second inverter and the second clock inverter. The first transmission gate is connected between the master latch and the slave latch. The wide Type 1 transistor is formed as a wide Type 1 active region structure, and the narrow Type 1 transistor is formed as a narrow Type 1 active region structure. The wide Type 2 transistor is formed as a wide Type 2 active region structure, and the narrow Type 2 transistor is formed as a narrow Type 2 active region structure.

Description

Technology Field

[0001] Claim of priority

[0002] This application claims priority to U.S. Provisional Application No. 63 / 381,887 filed November 01, 2022, the entirety of which is incorporated herein by reference. Background Technology

[0003] Recent trends in the miniaturization of integrated circuits (ICs) have resulted in smaller devices that consume less power while providing more functionality at higher speeds. The miniaturization process has brought about reliability challenges as well as stricter design and manufacturing specifications. Various electronic design automation (EDA) tools generate, optimize, and verify these standard cell layout designs while ensuring that standard cell layout design and manufacturing specifications for integrated circuits are met. Brief explanation of the drawing

[0004] The aspects of the present disclosure are best understood from the following detailed description when read together with the accompanying drawings. Note that, in accordance with standard industry practice, various features are not drawn in a fixed proportion. In fact, the dimensions of various features may be increased or decreased at will for the sake of clarity of discussion. FIG. 1 is a circuit diagram of an integrated circuit having a master-slave flip-flop and an associated support circuit according to some embodiments. FIGS. 2a to 2g are plan views of the integrated circuit of FIG. 1 according to some embodiments. FIGS. 3a to 3d are circuit diagrams of various variations of the integrated circuit of FIG. 1 according to some embodiments. FIG. 4a is a circuit diagram of an integrated circuit having a data latch and clock support circuit according to some embodiments. FIG. 4b is a plan view of the integrated circuit of FIG. 4a according to some embodiments. FIGS. 5a to 5e are plan views of a multi-cell integrated circuit comprising a plurality of single-height circuit cells and multi-height circuit cells having the integrated circuit of FIG. 1 according to some embodiments. FIG. 6 is a circuit diagram of a flip-flop circuit used with a combinational logic circuit according to some embodiments. FIG. 7 is a flowchart of a method for manufacturing an integrated circuit according to some embodiments. FIG. 8 is a block diagram of an electronic design automation (EDA) system according to some embodiments. FIG. 9 is a block diagram of an integrated circuit (IC) manufacturing system and an associated IC manufacturing flow according to some embodiments. Specific details for implementing the invention

[0005] The following disclosure provides many different embodiments or examples for implementing different features of the invention provided. To simplify the disclosure, specific examples of components, values, actions, materials, arrangements, etc. are described below. Of course, these are merely examples and are not intended to be limiting. Other components, values, actions, materials, arrangements, etc. are considered. For example, in the following description, the formation of a first feature on or above a second feature may include an embodiment in which the first feature and the second feature are formed in direct contact, and may also include an embodiment in which an additional feature may be formed between the first feature and the second feature so that the first feature and the second feature are not in direct contact. Additionally, the disclosure may repeat reference numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity and does not itself indicate a relationship between the various embodiments and / or configurations described.

[0006] Additionally, spatial relative terms such as "bottom," "below," "lower," "top," and "upper" may be used herein for ease of explanation to describe the relationship of one element or feature to other element(s) or feature(s), as illustrated in the drawings. Spatially relative terms are intended to include different orientations of the device during use or operation, in addition to the orientations illustrated in the drawings. The device may be oriented differently (rotated 90 degrees or oriented in a different way), and accordingly, the spatial relative terms used herein may be interpreted in the same manner.

[0007] In some embodiments, the master-slave flip-flop includes a transmission gate coupled between a master latch and a slave latch. The master latch includes a first inverter and a first clock inverter. The slave latch includes a second inverter and a second clock inverter. The output of the first inverter and the input of the first clock inverter are connected to the input of the transmission gate, and the input of the first inverter and the output of the first clock inverter are connected together. The input of the second inverter and the output of the second clock inverter are connected to the output of the transmission gate, and the output of the second inverter and the input of the second clock inverter are connected together. The first inverter, the transmission gate, and the second inverter are made of wide transistors within a wide active region structure, thereby reducing the time delay along the forward data path in the master-slave flip-flop. The first clock inverter and the second clock inverter are made of narrow transistors within a narrow active region structure. The average gate width of the wide transistor is greater than the average gate width of the narrow transistor. In some embodiments, the first inverter, transmission gate, and second inverter within the wide active area structure also form an aligned list along the forward data path of the master-slave flip-flop circuit, thereby reducing the master-slave flip-flop.

[0008] FIG. 1 is a circuit diagram of an integrated circuit (100) having a master-slave flip-flop and an associated support circuit according to some embodiments. The master-slave flip-flop is formed by a clock gate input circuit (101), a master latch (102), a transmission gate (104), a slave latch (106), and an output driver (109). The master latch (102) is coupled between the clock gate input circuit (101) and the transmission gate (104). The slave latch (106) is coupled between the transmission gate (104) and the output driver (109). The associated support circuit includes a clock support circuit (105) implemented with two inverters (110A and 110B). The associated support circuit also includes a data input support circuit (107) implemented with an inverter (110C). The clock support circuit (105) receives a clock signal (CP) and generates an inverted clock signal (CPB) and an in-phase clock signal (CPBB). The data input support circuit (107) receives a scan enable signal (SE) and generates an inverted scan enable signal (SEB).

[0009] The clock gate input circuit (101) includes a transmission gate (110F1), a gate inverter (110D), and a gate inverter (110E). The gate inverter (110D) is configured to receive a data signal (D), and the gate inverter (110E) is configured to receive a scan signal (SI). Each of the gate inverter (110D) and the gate inverter (110E) includes a first portion having a PMOS transistor (correspondingly labeled as 110Dp and 110Ep) and a second portion having an NMOS transistor (correspondingly labeled as 110Dn and 110En).

[0010] Each of the gate inverter (110D) and the gate inverter (110E) is configured to receive a scan enable signal (SE) and an invert scan enable signal (SEB). The combination of the gate inverter (110D) and the gate inverter (110E) forms a multiplexer. When the scan enable signal (SE) is logic LOW (and when the invert scan enable signal (SEB) is logic HIGH), the data signal (D) is selected as an input signal coupled to the transmission gate (110F1), and the scan signal (SI) is decoupled from the transmission gate (110F1). Alternatively, when the scan enable signal (SE) is logic HIGH (and when the invert scan enable signal (SEB) is logic LOW), the scan signal (SI) is selected as an input signal coupled to the transmission gate (110F1), and the data signal (D) is decoupled from the transmission gate (110F1).

[0011] The transmission gate (110F1) is configured to receive an inverted clock signal (CPB) and a common-phase clock signal (CPBB). When the inverted clock signal (CPB) is logic LOW (and when the common-phase clock signal (CPBB) is logic HIGH), neither the data signal (D) nor the scan signal (SI) is transmitted to the input node (ml_ax) of the master latch (102). When the inverted clock signal (CPB) is logic HIGH (and when the common-phase clock signal (CPBB) is logic LOW), the inverse of the selected input signal (data signal (D) or scan signal (SI)) is transmitted to the input node (ml_ax) of the master latch (102). Here, when the scan enable signal (SE) is logic LOW, the inversion of the data signal (D) is transmitted to the input node (ml_ax), but when the scan enable signal (SE) is logic HIGH, the inversion of the scan signal (SI) is transmitted to the input node (ml_ax).

[0012] In FIG. 1, the master latch (102) includes an inverter (110G) and a clock inverter (110F2) driven by clock signals (CPB and CPBB). The output of the inverter (110G) is connected to the input of the clock inverter (110F2), and the output of the clock inverter (110F2) is connected to the input of the inverter (110G). When the clock signal (CPB) is logic HIGH (and when the clock signal (CPBB) is logic LOW), the master latch (102) is in an unlocked state, and the signal at the output node (ml_b) of the master latch (102) is the inversion of the signal at the input node (ml_ax) of the master latch (102). Consequently, the signal at the output node (ml_b) becomes the inversion of the selected input signal (data signal (D) or scan signal (SI)) received from the clock gate input circuit (101). Meanwhile, the transmission gate (104) is set to a disconnected state by clock signals (CPB and CPBB), and the input node (sl_a) of the slave latch (106) is decoupled from the output node (ml_b) of the master latch (102). After that, the inverted clock signal (CPB) is changed to logic LOW (and the in-phase clock signal (CPBB) is changed to logic HIGH), the master latch (102) is changed to a latch state, and the signal of the output node (ml_b) of the master latch (102) is maintained for a time interval during which the clock signal (CPB) is logic LOW (and the clock signal (CPB) is logic HIGH). The latch signal value at the output node (ml_b) is the signal value of the input signal selected at the first falling edge of the clock signal (CPB) as the clock signal (CPB) changes to logic LOW (received from the clock gate input circuit (101)).

[0013] When the clock signal (CPB) changes to logic LOW (and when the clock signal (CPBB) changes to logic HIGH), the transmission gate (104) changes to a connected state by the clock signals (CPB and CPBB), and the latch signal at the output node (ml_b) of the master latch (102) is transmitted to the input node (sl_a) of the slave latch (106). In the embodiment illustrated in FIG. 1, the transmission gate (104) is implemented as a transmission gate (110H1) having a PMOS transistor that receives the clock signal (CPB) as a gate voltage and an NMOS transistor that receives the clock signal (CPBB) as a gate voltage.

[0014] In FIG. 1, the slave latch (106) includes an inverter (110I) and a clock inverter (110H2) driven by clock signals (CPB and CPBB). The output of the inverter (110I) is connected to the input of the clock inverter (110H2), and the output of the clock inverter (110H2) is connected to the input of the inverter (110I). When the clock signal (CPB) is logic LOW (and when the signal (CPBB) is logic HIGH), the slave latch (106) is in an unlocked state, and the signal at the output node (sl_bx) of the slave latch (106) is the inversion of the signal at the input node (sl_a) of the slave latch (106). Consequently, the inversion of the latch signal at the output node (ml_b) of the master latch (102) is transmitted to the output node (sl_bx) of the slave latch (106). Then, when the clock signal (CPB) changes to logic HIGH (and when the signal (CPBB) changes to logic LOW), the slave latch (106) changes to a latch state, and the signal of the output node (sl_bx) of the slave latch (106) is maintained, and the latch signal value of the output node (sl_bx) after the current rising edge of the clock signal (CPB) is the inversion of the latch signal at the output node (ml_b) that is latched after the previous falling edge (first falling edge) of the clock signal (CPB).

[0015] During the time interval when the clock signal (CPB) is logic HIGH after the current rising edge of the clock signal (CPB), the signal value (Q) at the output (Q) of the output driver (109) (implemented by the inverter (110J)) n+1 ) is equivalent to the signal value of the selected input signal (received from the clock gate input circuit (101)) at the previous falling edge (first falling edge) of the clock signal (CPB). That is, when the scan enable signal (SE) is logic LOW, Q n+1 = D n and when the scan enable signal (SE) is logic LOW, Q n+1 = SI n am.

[0016] In FIG. 1, the gate inverter (110D), transmission gate (110F1), inverter (110G), transmission gate (110H1), inverter (110I), and inverter (110J) are each implemented as Class-1 devices, and the clock inverter (110F2) and clock inverter (110F2) are each implemented as Class-2 devices. The average gate width of the PMOS transistors in the Class-1 device is greater than the average gate width of the PMOS transistors in the Class-2 device. The average gate width of the NMOS transistors in the Class-1 device is greater than the average gate width of the NMOS transistors in the Class-2 device. The PMOS transistors in the Class-1 device are manufactured with a wide PMOS active region structure, and the PMOS transistors in the Class-2 device are manufactured with a narrow PMOS active region structure. The NMOS transistors in the Class-1 device are manufactured with a wide NMOS active region structure, and the NMOS transistors in the Class-2 device are manufactured with a narrow NMOS active region structure.

[0017] In some embodiments, when the active region structure is formed as a fin structure, the PMOS transistor fabricated within the PMOS active region structure and the narrow PMOS active region structure is a p-channel FinFET, and the NMOS transistor fabricated within the NMOS active region structure and the narrow NMOS active region structure is an n-channel FinFET. In some embodiments, when the active region structure is formed as a nanosheet structure, the PMOS transistor fabricated within the PMOS active region structure and the narrow PMOS active region structure is a p-channel nanosheet transistor, and the NMOS transistor fabricated within the NMOS active region structure and the narrow NMOS active region structure is an n-channel nanosheet transistor. In some embodiments, when the active region structure is formed as a nanowire structure, the PMOS transistor fabricated within the PMOS active region structure and the narrow PMOS active region structure is a p-channel nanowire transistor, and the NMOS transistor fabricated within the NMOS active region structure and the narrow NMOS active region structure is an n-channel nanowire transistor.

[0018] FIGS. 2a to 2g are plan views of the integrated circuit (100) of FIG. 1 according to some embodiments. In FIGS. 2a to 2g, inverter (110A), inverter (110B), inverter (110C), gate inverter (110D) and gate inverter (110E) are implemented corresponding to layout areas "A", "B", "C", "D" and "E". Transmission gate (110F1), clock inverter (110F2), inverter (110G), transmission gate (110H1) and clock inverter (110H2) are implemented corresponding to layout areas "F1", "F2", "G", "H1" and "H2".

[0019] Each of the integrated circuits of FIGS. 2a through 2g includes a wide PMOS active region structure (220P) extending in the X direction, a wide NMOS active region structure (220N) extending in the X direction, a narrow PMOS active region structure (230P) extending in the X direction, and a narrow NMOS active region structure (230N) extending in the X direction. Each of the gate inverter (110D), transmission gate (110F1), inverter (110G), transmission gate (110H1), inverter (110I), and inverter (110J) (correspondingly, layout areas "D", "F1", "G", "H1", "I", and "J") is made of wide transistors within the wide PMOS active region structure (220P) and the wide NMOS active region structure (220N). The clock inverter (110F2) and the clock inverter (110H2) are each made of a narrow transistor within a narrow PMOS active region structure (230P) and a narrow NMOS active region structure (230N) (correspondingly layout areas "F2" and "H2").

[0020] In FIGS. 2a through 2g, each of the inverters (110A, 110B, and 110C) is optionally implemented as a wide transistor within a wide active area structure (i.e., 220P and 220N) or as a narrow transistor within a narrow active area structure (i.e., 230P and 230N). In the plan view (200A) of FIG. 2a, the inverter (110A) is implemented as a wide transistor within a wide active area structure (i.e., 220P and 220N), and the inverters (110B and 110C) are implemented as narrow transistors within a narrow active area structure (i.e., 230P and 230N). In the plan view (200B) of FIG. 2, the inverter (110B) is implemented as a wide transistor within a wide active area structure (i.e., 220P and 220N), whereas the inverters (110A and 110C) are implemented as a narrow transistor within a narrow active area structure (i.e., 230P and 230N). In each of the plan views (200C to 200G) as shown in FIG. 2c to 2g, the inverter (110C) is implemented as a wide transistor within a wide active area structure (i.e., 220P and 220N), and the inverters (110A and 110B) are implemented as a narrow transistor within a narrow active area structure (i.e., 230P and 230N).

[0021] Some exemplary arrangements of two wide active area structures (i.e., 220P and 220N) and two narrow active area structures (i.e., 230P and 230N) are shown in FIGS. 2a to 2g.

[0022] In the plan views (200A to 200C) illustrated in FIGS. 2a to 2c, two wide active region structures (i.e., 220P and 220N) are positioned laterally between two narrow active region structures (i.e., 230P and 230N). In the plan view (200A) of FIG. 2a, the narrow PMOS active region structure (230P) is adjacent to the wide PMOS active region structure (220P), whereas the narrow NMOS active region structure (230N) is adjacent to the wide NMOS active region structure (220N). In both the plan view (200B) of FIG. 2b and the plan view (200C) of FIG. 2c, the narrow PMOS active region structure (230P) is adjacent to the wide NMOS active region structure (220N), whereas the narrow NMOS active region structure (230N) is adjacent to the wide PMOS active region structure (220P).

[0023] In the plan views (200D to 200E) illustrated in FIGS. 2d to 2e, two narrow active region structures (i.e., 230P and 230N) are laterally positioned between two wide active region structures (i.e., 220P and 220N). In the plan view (200D) of FIG. 2d, the wide PMOS active region structure (220P) is adjacent to the narrow PMOS active region structure (230P), while the wide NMOS active region structure (220N) is adjacent to the narrow NMOS active region structure (230N). In the plan view (200E) of FIG. 2e, the wide NMOS active region structure (220N) is adjacent to the narrow PMOS active region structure (230P), while the wide PMOS active region structure (220P) is adjacent to the narrow NMOS active region structure (230N).

[0024] In the plan views (200F to 200G) illustrated in FIGS. 2f to 2g, two wide active region structures (i.e., 220P and 220N) form a first pair of adjacent active region structures, and two narrow active region structures (i.e., 230P and 230N) form a second pair of adjacent active region structures. In the plan view (200F) of FIG. 2f, the wide PMOS active region structure (220P) is adjacent to the narrow PMOS active region structure (230P), whereas the two PMOS active region structures (i.e., 220P and 230P) are positioned between the wide NMOS active region structure (220N) and the narrow NMOS active region structure (230N). In the plan view (200G) of FIG. 2g, the wide NMOS active region structure (220N) is adjacent to the narrow NMOS active region structure (230N), while the two NMOS active region structures (i.e., 220N and 230N) are positioned between the wide PMOS active region structure (220P) and the narrow PMOS active region structure (230P).

[0025] In FIGS. 2a through 2g, the gate inverter (110D), transmission gate (110F1), inverter (110G), transmission gate (110H1), inverter (110I), and inverter (110J) (all of which are Class-1 devices) are made of wide transistors in wide active area structures (i.e., 220P and 220N). Additionally, the gate inverter (110D), transmission gate (110F1), inverter (110G), transmission gate (110H1), inverter (110I), and inverter (110J) form an aligned list arranged along the X direction.

[0026] The order of devices in an aligned list is determined by the direction of data signal propagation. In the examples of FIGS. 2a through 2g, the data signal propagates from the gate inverter (110D) to the transmission gate (110F1), then from the transmission gate (110F1) to the inverter (110G), then from the inverter (110G) to the transmission gate (110H1), then from the transmission gate (110H1) to the inverter (110I), and then from the inverter (110I) to the inverter (110J). When the Class-1 devices in the aligned list are arranged along the X direction, the X coordinates of the Class-1 devices in the aligned list change monotonically after the order of the Class-1 devices in the list. For example, in FIGS. 2a to 2g, the X coordinate of the gate inverter (110D) is smaller than the X coordinate of the transmission gate (110F1), the X coordinate of the transmission gate (110F1) is smaller than the X coordinate of the inverter (110G), the X coordinate of the inverter (110G) is smaller than the X coordinate of the transmission gate (110H1), the X coordinate of the transmission gate (110H1) is smaller than the X coordinate of the inverter (110I), and the X coordinate of the inverter (110I) is smaller than the X coordinate of the inverter (110J).

[0027] In some embodiments, the plan views of FIGS. 2a through 2g are modified to accommodate various variations of the integrated circuit (100) of FIG. 1. The clock gate input circuit (101) of FIG. 1 includes a transmission gate (110F1), a gate inverter (110D), and a gate inverter (110E) forming a clock gate multiplexer. Other implementations of the clock gate input circuit are within the scope of the present disclosure. As a first example, in the integrated circuit (300A) of FIG. 3a, the clock gate input circuit (101) is implemented with a gate inverter (110D) connected in series with the transmission gate (110F1). As a second example, in the integrated circuit (300B) of FIG. 3b, the clock gate input circuit (101) is implemented with an inverter (310D) connected in series with the transmission gate (110F1). The inverter (310D) and the transmission gate (110F1) form a clock inverter used as a clock gate input circuit (101).

[0028] In some embodiments, a plan view of the integrated circuit (300A) of FIG. 3a or the integrated circuit (300B) of FIG. 3a is obtained by modifying one of the plan views of FIG. 2a through 2g. For example, in some embodiments, modification of the plan views of FIG. 2a through 2g includes removing the gate inverter (110E) from layout area "E". In some embodiments, after removing the gate inverter (110E) from layout area "E", one or more dummy devices are implemented in layout area "E". In some alternative embodiments, after removing the gate inverter (110E) from layout area "E", one of the inverters (110A, 110B, and 110C) that were implemented as wide active area structures (i.e., 220P and 220N) is moved to layout area "E" and implemented as a narrow active area structure (e.g., 230P and 230N). Modification of the plan view (200A) of FIG. 2a includes moving the inverter (110A) to layout area "E". Modification of the plan view (200B) of FIG. 2b includes moving the inverter (110B) to layout area "E". For the integrated circuit (300A) of FIG. 3a, modification of one of the plan views (200C to 200G) of FIG. 2c to 2g includes moving the inverter (110C) to layout area "E". However, for the integrated circuit (300B) of FIG. 3b, the modification includes removing the inverter (110C) from layout area "C". Other modifications of the plan views of FIG. 2a to 2g for implementing the integrated circuit (300A or 300B) are also within the scope of consideration of the present disclosure.

[0029] Another variation of the integrated circuit (100) of FIG. 1 is the integrated circuit (300C) shown in FIG. 3c. In the integrated circuit (300C), the inverter (110G) of the master latch (102) of FIG. 1 is implemented as a resettable inverter (310G), and the clock inverter (110H2) of the slave latch (106) of FIG. 1 is implemented as a resettable clock inverter (310H2). A reset logic signal (CD) is coupled to the resettable inverter (310G) and the resettable clock inverter (310H2), respectively. When the reset logic signal (CD) is logic LOW, the resettable inverter (310G) of FIG. 3c functions identically to the inverter (110G) of FIG. 1, and the resettable clock inverter (310H2) of FIG. 3c functions identically to the clock inverter (110H2) of FIG. 1. However, when the reset logic signal (CD) is in logic HIGH, the signal at the output node (ml_b) of the master latch (102) is driven to logic LOW, and the slave latch (106) is driven to the latch-unlocked state. Additionally, during the time interval when the clock signal (CPB) is in logic LOW, the logic LOW at the output node (ml_b) passes through the transmission gate (110H1); then, the logic LOW at the input node (sl_a) of the slave latch (106) passes through both inverters (110I and 110J). Consequently, the signal at the output Q of the output driver (109) is reset to logic LOW by the reset logic signal (CD).

[0030] In some embodiments, a plan view of the integrated circuit (300C) of FIG. 3c is obtained by modifying one of the plan views of FIG. 2a through 2g. For example, in some embodiments, modification of the plan views of FIG. 2a through 2g includes expanding the layout area "G" along the X direction to accommodate a wide transistor newly added to the resettable inverter (310G), and modification also includes expanding the layout area "H2" along the X direction to accommodate a narrow transistor newly added to the resettable clock inverter (310H2). Other modifications of the plan views of FIG. 2a through 2g for implementing the integrated circuit (300C) are also within the scope of consideration of the present disclosure.

[0031] Another variation of the integrated circuit (100) of FIG. 1 is the integrated circuit (300D) illustrated in FIG. 3d. In the integrated circuit (300D), the output driver (109) is implemented as an inverter (310J) having two PMOS transistors and two NMOS transistors, thereby increasing the driving strength of the output driver (109) compared to an output driver implemented as an inverter having only one PMOS and one NMOS transistor. In some embodiments, to further increase the driving strength of the output driver (109), two or more PMOS transistors and two or more NMOS transistors are used in the inverter for the output driver (109). Other variations of the output driver (109) are within the scope of consideration of the present disclosure. For example, in some embodiments, the output driver (109) is implemented as a buffer circuit, and the output signal of the buffer circuit and the input signal of the buffer circuit have the same logic value. In some embodiments, a plan view of the integrated circuit (300D) of FIG. 3d is obtained by modifying one of FIG. 2a through 2g. For example, in some embodiments, modification of the plan view of FIG. 2a through 2g includes expanding the layout area “J” along the X direction to accommodate a wide transistor newly added to the inverter (310J). Other modifications of the plan view of FIG. 2a through 2g for implementing the integrated circuit (300D) are also within the scope of the present disclosure.

[0032] In FIG. 1, a master-slave flip-flop is used as an example. In the master-slave flip-flop, the Class-1 device is made of a wide transistor within a wide active area structure, and the Class-2 device is made of a narrow transistor within a narrow active area structure. In the embodiment illustrated in FIG. 4a, a data latch is used as another example. In the data latch, the Class-1 device is made of a wide transistor within a wide active area structure, and the Class-2 device is made of a narrow transistor within a narrow active area structure.

[0033] FIG. 4a is a circuit diagram of an integrated circuit (400) having a data latch and a clock support circuit according to some embodiments. The data latch includes an inverter (410D), a transmission gate (410F1), an inverter (410G), a clock inverter (410F2), an inverter (410K1), and an inverter (410K2). A clock support circuit (105) implemented with two inverters (110A and 110B) receives a clock signal (CP) and generates an inverted clock signal (CPB) and an in-phase clock signal (CPBB). The inverter (410D) and the transmission gate (410F1) are connected as clock inverters to form a clock gate input circuit (401). The inverter (410K1) and the inverter (410K2) form an output driver (409). Each of the inverter (410G) and the clock inverter (410F2) is coupled between the clock gate input circuit (401) and the output driver (409). The output of the inverter (410G) is connected to the input of the clock inverter (410F2), and the output of the clock inverter (410F2) is connected to the input of the inverter (410G).

[0034] Each of the transmission gate (410F1) and clock inverter (410F2) is driven by clock signals (CPB and CPBB). When the inverted clock signal (CPB) is logic HIGH (and when the in-phase clock signal (CPBB) is logic LOW), the inversion of the data signal (D) is transmitted to the input of the inverter (410G) (i.e., node (ml_ax)), and because the clock inverter (410F2) is disabled by the clock signals (CPB and CPBB), the logic value of the output of the inverter (410G) (i.e., node (ml_b)) is the same as the logic value of the data signal (D). Subsequently, when the inverted clock signal (CPB) changes to logic LOW (and the in-phase clock signal (CPBB) changes to logic HIGH), the logic value of the output of the inverter (410G) (i.e., node (ml_b)) is latched by the clock inverter (410F2) because the clock inverter (410F2) is enabled by the clock signals (CPB and CPBB). Additionally, during the time interval when the clock signal (CPB) is logic LOW (and the in-phase clock signal (CPBB) is logic HIGH), the transmission gate (410F1) also prevents the data signal (D) from being transmitted to the input of the inverter (410G) (i.e., node (ml_ax)). The logic value of the output of the inverter (410G) (i.e., node (ml_b)) is transmitted to the output of the inverter (410K2) as a latch output signal (Q).

[0035] FIG. 4b is a top view of the integrated circuit (400) of FIG. 4a according to some embodiments. In FIG. 4b, a wide PMOS active area structure (220P), a wide NMOS active area structure (220N), a narrow PMOS active area structure (230P), and a narrow NMOS active area structure (230N) each extend in the X direction. An inverter (410D), a transmission gate (410F1), an inverter (410G), an inverter (410K1), and an inverter (410K2) are implemented correspondingly in layout areas "D", "F1", "G", "K1", and "K2", and an inverter (110A), a clock inverter (410F2), and an inverter (110B) are implemented correspondingly in layout areas "A", "F2", and "B". Inverter (410D), transmission gate (410F1), inverter (410G), inverter (410K1), and inverter (410K2) are each implemented as Class-1 devices made of wide transistors within wide active area structures (i.e., 220P and 220N), and clock inverter (410F2) is implemented as a Class-2 device made of narrow transistors within narrow active area structures (i.e., 230P and 230N). In FIG. 4b, inverters (110A and 110B) are each also made of narrow transistors within narrow active area structures (i.e., 230P and 230N). Additionally, as shown in the order of layout areas "D", "F1", "G", "K1", "K2", an aligned list of inverters (410D), transmission gates (410F1), inverters (410G), inverters (410K1) and inverters (410K2) is arranged along the X direction of the plan view.

[0036] The plan view of FIG. 4b is provided as an example, and various variations of the plan views of FIG. 2a through 2g adapted to the integrated circuit (400) of FIG. 4a are within the scope of the present disclosure. Other embodiments of the plan view for the integrated circuit (400) of FIG. 4a are also within the scope of the present disclosure.

[0037] In some embodiments, the integrated circuit (100) of FIG. 1 is designed as a circuit cell based on the plan views of FIG. 2a through 2g. In some embodiments, the integrated circuit (400) of FIG. 4a is designed as a circuit cell based on the plan view of FIG. 4b. The circuit cells of the integrated circuit (100) or the integrated circuit (400) are often placed in a larger multi-cell integrated circuit having other single-height circuit cells. In the larger multi-cell integrated circuit, most logic gates (e.g., NOT gate, NOR gate, and NAND gate) are implemented as single-height circuit cells, whereas the integrated circuit (100) or the integrated circuit (400) is implemented as a double-height circuit cell or a triple-height circuit cell.

[0038] FIGS. 5a through 5e are plan views of a multi-cell integrated circuit comprising a plurality of single-height circuit cells and multi-height circuit cells having the integrated circuit (100) of FIG. 1 according to some embodiments. In FIGS. 5a through 5e, a circuit cell (500) occupying a plurality of cell rows is positioned between two cell rows (510 and 520). Cell row (510) is identified as between horizontal lines (501 and 503), and cell row (520) is identified as between horizontal lines (502 and 504). Along a cell column (510) extending in the X direction, a plurality of single-height circuit cells (not all shown in the drawings) are aligned between horizontal lines (501 and 503), and one of the single-height circuit cells is identified as a single-height circuit (514). The single-height circuit (514) is implemented in the layout area "U" of each plan view. Along the cell column (520) extending in the X direction, a plurality of single-height circuit cells (not all shown in the drawing) are aligned between horizontal lines (502 and 504), and one of the single-height circuit cells is identified as a single-height circuit (524). The single-height circuit (524) is implemented in the layout area "V" of each plan view. The cell height of each cell is measured along the Y direction in units of "CH". The Y direction is orthogonal to the X direction.

[0039] Each of the single-height circuits (514) and (524) has a cell height equivalent to 1.0*CH. The circuit cell (500) (implemented by the integrated circuit (100) of FIG. 1) is bounded between horizontal lines (501 and 502). In FIG. 5a, the circuit cell (500) has a cell height equivalent to 3.0*CH. In FIG. 5b through 5e, the circuit cell (500) has a cell height equivalent to 2.0*CH.

[0040] In FIG. 5a-5e, the circuit cells of cell row (510) are made of PMOS transistors within the PMOS active region structure (542P) and NMOS transistors within the NMOS active region structure (542N). The circuit cells of cell row (520) are made of PMOS transistors within the PMOS active region structure (544P) and NMOS transistors within the NMOS active region structure (544N). The PMOS active region structures (542P and 544P) and NMOS active region structures (542N and 544N) extending in the X direction are all parallel to the wide active region structures (i.e., 220P and 220N) and the narrow active region structures (i.e., 230P and 230N).

[0041] The circuit cells (500) of FIGS. 5a through 5e are implemented as the integrated circuit (100) of FIG. 1. Each plan view of the circuit cells (500) of FIGS. 5a through 5e corresponds to one of the plan views of FIGS. 2b through 2c and FIGS. 2e through 2g. In some embodiments, NMOS active region structures (i.e., 220N, 230N, 542N, and 544N) are fabricated on a p-type substrate, and PMOS active region structures (i.e., 220P, 230P, 542P, and 544P) are fabricated in n-type wells within a p-type substrate.

[0042] In FIG. 5a, the circuit cell (500) has the same plan as the plan view (200B) in FIG. 2b, which has already been described with reference to FIG. 2b. In FIG. 5a, a PMOS active region structure (542P) and a narrow PMOS active region structure (230P) are fabricated in an n-type well (550AS), a wide PMOS active region structure (220P) is fabricated in an n-type well (550AL), and a PMOS active region structure (544P) is fabricated in an n-type well (554A). In some embodiments, the n-type wells (550AS, 550AL, and 554A) are equally spaced along the Y direction.

[0043] In FIG. 5b, the circuit cell (500) has the same plan as the plan view (200C) of FIG. 2c, which has already been described with reference to FIG. 2c. In FIG. 5b, the wide PMOS active region structure (220P) and the narrow PMOS active region structure (230P) are manufactured correspondingly in the n-type wells (550BL and 550BS), and the PMOS active region structures (542P and 544P) are manufactured correspondingly in the n-type wells (552B and 554B). In some embodiments, the n-type wells (552B, 550BS, 550BL, and 554B) are equally spaced along the Y direction.

[0044] In FIG. 5c, the circuit cell (500) has the same plan as the plan view (200E) in FIG. 2e, which has already been described with reference to FIG. 2e. In FIG. 5c, the wide PMOS active region structure (220P) and the narrow PMOS active region structure (230P) are manufactured correspondingly in the n-type wells (550CL and 550CS), and the PMOS active region structures (542P and 544P) are manufactured correspondingly in the n-type wells (552C and 554C). In some embodiments, the n-type wells (552C, 550CS, 550CL, and 554C) are equally spaced along the Y direction.

[0045] In FIG. 5d, the circuit cell (500) has the same plan as the plan view (200F) of FIG. 2f, which has already been described with reference to FIG. 2f. In FIG. 5d, a wide PMOS active region structure (220P) and a narrow PMOS active region structure (230P) are fabricated in an n-type well (550D), and PMOS active region structures (542P and 544P) are fabricated correspondingly in n-type wells (552D and 554D). In some embodiments, the n-type wells (552D, 550D, and 554D) are equally spaced along the Y direction.

[0046] In FIG. 5e, the circuit cell (500) has the same plan as the plan view (200G) in FIG. 2g, which has already been described with reference to FIG. 2g. In FIG. 5e, a wide PMOS active region structure (220P) and a narrow PMOS active region structure (230P) are manufactured correspondingly in n-type wells (550EL and 550ES). In n-type wells (550EL and 550ES), PMOS active region structures (542P and 544P) are also manufactured correspondingly. In some embodiments, n-type wells (550EL and 550ES) and adjacent n-type wells (not shown in the drawing) are equally spaced along the Y direction.

[0047] In FIG. 1, the gate inverter (110D), transmission gate (110F1), inverter (110G), transmission gate (110H1), inverter (110I), and inverter (110J) are all located on the forward data path of the flip-flop circuit. In FIG. 2a through 2g, each device on the forward data path is implemented as a Class-1 device made of transistors of wide active area structures (i.e., 220P and 220N). Additionally, in FIG. 2a through 2g, the gate inverter (110D), transmission gate (110F1), inverter (110G), transmission gate (110H1), inverter (110I), and inverter (110J) are arranged in a plan view along the X direction as an aligned list after the forward data path of the flip-flop circuit. When implementing a flip-flop circuit based on one of the plan views shown in FIGS. 2a to 2g, the setup slack time at the second transmission gate (H1) of the flip-flop circuit is improved compared to some alternative implementations where some devices on the forward data path are not implemented as Class-1 devices. When implementing a flip-flop circuit based on one of the plan views shown in FIGS. 2a to 2g, the setup slack time at the second transmission gate (H1) of the flip-flop circuit is also improved compared to some alternative implementations where the gate inverter (110D), transmission gate (110F1), inverter (110G), transmission gate (110H1), inverter (110I), and inverter (110J) are not arranged in a sorted list along the forward data path.

[0048] When a flip-flop circuit is used with a combinational logic circuit, the setup slack time is related to the time delay of the gate inverter (110D), transmission gate (110F1), inverter (110G), transmission gate (110H1), inverter (110I), and inverter (110J) on the forward data path. FIG. 6 is a circuit diagram of a flip-flop circuit used with a combinational logic circuit according to some embodiments. FIG. 6 includes flip-flop circuits (620 and 640) and a combinational logic circuit (630) coupled between the flip-flop circuits (620 and 640). Each flip-flop circuit (620 and 640) is implemented as an example of the flip-flop circuit of FIG. 1, and each flip-flop circuit (620 and 640) receives a clock signal (CP) from a clock input node (611). In FIG. 6, at the moment of the triggering edge of the clock signal (CP), the data signal received at the input (D) of the flip-flop circuit (620) is transmitted to the output (Q) of the flip-flop circuit (620). Subsequently, the output (Q) of the flip-flop circuit (620) passes through the coupling logic circuit (630) and reaches the input (D) of the flip-flop circuit (640). Then, the data signal at the input (D) of the flip-flop circuit (640) is transmitted to a transmission gate (110H1) (shown in FIG. 1) within the flip-flop circuit, which is to be latched by a slave latch (106) (shown in FIG. 1).

[0049] In FIG. 6, the data arrival time (T) at the input of the transmission gate (110H1) of the flip-flop circuit (640) arr ) is equation T arr = T clock + T CP2Q + T comb + T D2ml_b It is given as, where T clock is the time of the triggering edge of the clock signal (CP), and T CP2Q is the delay time from the trigger input of the flip-flop circuit (620) to the output (Q) of the flip-flop circuit (620), and T comb is the delay time of the combination logic circuit (630), and TD2ml_b is the delay time from the input (D) of the flip-flop circuit (640) to the input of the transmission gate (110H1) of the flip-flop circuit (640). The data request time (T) of the data at the transmission gate (110H1) of the flip-flop circuit (640). req ) is equation T req = T clock + T ck2TXG It is given as, and here T ck2TXG is the delay time from the trigger input of the flip-flop circuit (640) to the input of the transmission gate (110H1) of the flip-flop circuit (640). The setup slack time at the input of the transmission gate (110H1) is the data request time (T) at the input of the transmission gate (110H1). req ) and arrival time (T arr It is the difference of ). When the flip-flop circuits (620 and 640) are implemented in one of the plan views of FIGS. 2a to 2g, the delay time (T CP2Q ) and delay time (T D2ml_b Each of these is reduced, resulting in an improved setup slack time at the input of the transmission gate (110H1). Additionally, if the flip-flop circuit (640) is implemented as one of the plan views of FIGS. 2c through 2g, the delay time (T ck2TXG ) also increases, further improving the setup slack time at the input of the transmission gate (110H1).

[0050] FIG. 7 is a flowchart of a method (700) for manufacturing an integrated circuit according to some embodiments. The order of operations of the method (700) shown in FIG. 7 is for illustrative purposes only; the operations of the method (700) may be performed in a different order than that shown in FIG. 7. It is understood that additional operations may be performed before, during, and / or after the method (700) shown in FIG. 7, and that some other processes may be described only briefly in this specification.

[0051] In operation (710) of method (700), a wide Type 1 active region structure and a narrow Type 1 active region structure extending in the X direction are manufactured. In operation (720) of method (700), a wide Type 2 active region structure and a narrow Type 2 active region structure extending in the X direction are manufactured. In the exemplary embodiments illustrated in FIGS. 2a to 2g and FIGS. 3a to 3e, a wide PMOS active region structure (220P) and a narrow PMOS active region structure (230P) are manufactured in operation (710) (or alternatively operation (720)), and a wide NMOS active region structure (220N) and a narrow NMOS active region structure (230N) are manufactured in operation (720) (or alternatively operation (710)). Additionally, in the exemplary embodiments illustrated in FIGS. 3a through 3e, PMOS active region structures (542P and 544P) are manufactured in operation (710) (or alternatively operation (720)), and NMOS active region structures (542N and 544N) are manufactured in operation (720) (or alternatively operation (710)). After operations (710 and 720), the manufacturing process proceeds to operations (730 and 740).

[0052] In operation (730) of method (700), the first inverter, the first transmission gate, and the second inverter are formed with a wide Type 1 transistor in a wide Type 1 active region structure and a wide Type 2 transistor in a wide Type 2 active region structure. In the exemplary embodiments illustrated in FIGS. 2a to 2g and FIGS. 3a to 3e, the inverter (110G), the transmission gate (110H1), and the inverter (110I) are formed with a wide PMOS transistor in a wide PMOS active region structure (220P) and a wide NMOS transistor in a wide NMOS active region structure (220N). In operation (740) of method (700), the first clock inverter and the second clock inverter are formed with a narrow Type 1 transistor in a narrow Type 1 active region structure and a narrow Type 2 transistor in a narrow Type 2 active region structure. In the exemplary embodiments illustrated in FIGS. 2a to 2g and FIGS. 3a to 3e, the clock inverter (110F2) and the clock inverter (110H2) are formed with a narrow PMOS transistor within a narrow PMOS active region structure (230P) and a narrow NMOS transistor within a narrow NMOS active region structure (230N). After operations (710 and 720), the manufacturing process proceeds to operations (750 and 760).

[0053] In operation (750) of method (700), the first clock inverter is connected to the first inverter to form a first latch circuit. In the exemplary embodiments illustrated in FIGS. 2a to 2g and FIGS. 3a to 3e, the output of the inverter (110G) is connected to the input of the clock inverter (110F2), and the output of the clock inverter (110F2) is connected to the input of the inverter (110G) to form a master latch (102). In operation (760) of method (700), the second clock inverter is connected to the second inverter to form a second latch circuit. In the exemplary embodiments illustrated in FIGS. 2a to 2g and FIGS. 3a to 3e, the output of the inverter (110I) is connected to the input of the clock inverter (110H2), and the output of the clock inverter (110H2) is connected to the input of the inverter (110I) to form a slave latch (106).

[0054] In some embodiments, at least a portion of the wide active region structure and the narrow active region structure manufactured in operation (710) and operation (720) has a uniform width along the Y direction. For example, in the plan view of FIGS. 2f to 2g, the width of the wide PMOS active region structure (220P) and the width of the wide NMOS active region structure (220N) in at least layout areas D, F1, G, H1, I, J for implementing a Class-1 device are each kept uniform and identical, and the width of the narrow PMOS active region structure (230P) and the width of the narrow NMOS active region structure (230N) in at least layout areas F2 and H2 for implementing a Class-2 device are also each kept uniform and identical. In FIGS. 2f to 2g, the uniform width (or average width) of the wide PMOS active region structure (220P) is greater than the uniform width (or average width) of the narrow PMOS active region structure (230P), and the uniform width of the wide NMOS active region structure (220N) is greater than the uniform width (or average width) of the narrow NMOS active region structure (230N).

[0055] In some alternative embodiments, parts of the wide active area structure and the narrow active area structure manufactured in operation (710) and operation (720) do not have a uniform width along the Y direction. In some plan views of FIGS. 2a through 2e, the width of the wide PMOS active area structure (220P) and the width of the wide NMOS active area structure (220N) within some layout areas D, F1, G, H1, I, J for implementing a Class-1 device are individually adjusted to further improve the slack time of the flip-flop of FIG. 1. In some plan views of FIGS. 2a through 2e, the width of the narrow PMOS active area structure (230P) and the width of the narrow NMOS active area structure (230N) within some layout areas F2 and H2 for implementing a Class-2 device are individually adjusted.

[0056] As an example, in the embodiment illustrated in FIG. 2b and FIG. 2d, even though the width of the narrow PMOS active region structure (230P) and the width of the narrow NMOS active region structure (230N) within layout areas F2 and H2 for implementing a Class-2 device are each kept uniform and identical, the width of the wide PMOS active region structure (220P) within layout areas D, F1, G, H1, I, J is not uniform and identical, and the width of the wide NMOS active region structure (220N) within layout areas D, F1, G, H1, I, J is not uniform and identical. In FIG. 2b and FIG. 2d, the average width of the wide PMOS active region structure (220P) is still greater than the uniform width (or average width) of the narrow PMOS active region structure (230P) within layout areas F2 and H2, and the average width of the wide NMOS active region structure (220N) is still greater than the uniform width (or average width) of the narrow NMOS active region structure (230N) within layout areas F2 and H2. Consequently, the average gate width of the wide PMOS transistor of the Class-1 device is greater than the average gate width of the narrow PMOS transistor of the Class-2 device, and the average gate width of the wide NMOS transistor of the Class-1 device is greater than the average gate width of the narrow NMOS transistor of the Class-2 device.

[0057] As an example, in the embodiment illustrated in FIG. 2c and FIG. 2e, even though the widths of the wide PMOS active region structure (220P) and the wide NMOS active region structure (220N) within layout areas D, F1, G, H1, I, J for implementing Class-1 are each kept uniform and identical, the widths of the narrow PMOS active region structure (230P) within layout areas F2 and H2 are not uniform and identical, and the widths of the narrow NMOS active region structure (230N) within layout areas F2 and H2 are not uniform and identical. In FIG. 2c and FIG. 2e, the uniform width (or average width) of the wide PMOS active region structure (220P) is still greater than the average width of the narrow PMOS active region structure (230P) within layout areas F2 and H2, and the uniform width (or average width of the wide NMOS active region structure (220N)) is still greater than the average width of the narrow NMOS active region structure (230N) within layout areas F2 and H2. Consequently, the average gate width of the wide PMOS transistor of the Class-1 device is greater than the average gate width of the narrow PMOS transistor of the Class-2 device, and the average gate width of the wide NMOS transistor of the Class-1 device is greater than the average gate width of the narrow NMOS transistor of the Class-2 device.

[0058] As an example, in the embodiment illustrated in FIG. 2a, the width of the wide PMOS active region structure (220P) in layout areas D, F1, G, H1, I, J is not uniform and equal, the width of the wide NMOS active region structure (220N) in layout areas D, F1, G, H1, I, J is not uniformly equal, the width of the narrow PMOS active region structure (230P) in layout areas F2 and H2 is not uniformly equal, and the width of the narrow PMOS active region structure (230P) in layout areas F2 and H2 is not uniformly equal. In FIG. 2a, the average width of the wide PMOS active region structure (220P) in layout areas D, F1, G, H1, I, J for implementing a Class-1 device is still greater than the average width of the narrow PMOS active region structure (230P) in layout areas F2 and H2 for implementing a Class-2 device, and the average width of the wide NMOS active region structure (220N) in layout areas D, F1, G, H1, I, J for implementing a Class-1 device is greater than the average width of the narrow NMOS active region structure (230N) in layout areas F2 and H2 for implementing a Class-2 device. Consequently, the average gate width of the wide PMOS transistor of the Class-1 device is greater than the average gate width of the narrow PMOS transistor of the Class-2 device, and the average gate width of the wide NMOS transistor of the Class-1 device is greater than the average gate width of the narrow NMOS transistor of the Class-2 device.

[0059] FIG. 8 is a block diagram of an electronic design automation (EDA) system (800) according to some embodiments.

[0060] In some embodiments, the EDA system (800) includes an automated place and route (APR) system. The method described herein for designing a layout diagram represents a wire routing arrangement according to one or more embodiments, which can be implemented, for example, using the EDA system (800) according to some embodiments.

[0061] In some embodiments, the EDA system (800) is a general-purpose computing device comprising a hardware processor (802) and a non-transient computer-readable storage medium (804). Among other things, the storage medium (804) is encoded into computer program code (806), that is, a set of executable instructions, i.e., stores them. Execution of the instructions (806) by the hardware processor (802) represents an EDA tool (at least partially) that implements some or all of the methods described herein according to one or more embodiments (hereinafter referred to as processes and / or methods).

[0062] The processor (802) is electrically coupled to a computer-readable storage medium (804) via a bus (808). The processor (802) is also electrically coupled to an I / O interface (810) by the bus (808). A network interface (812) is also electrically connected to the processor (802) via the bus (808). The network interface (812) is connected to a network (814) so ​​that the processor (802) and the computer-readable storage medium (804) can access an external element via the network (814). The processor (802) is configured to execute computer program code (806) encoded in the computer-readable storage medium (804) to enable the system (800) to perform some or all of the aforementioned process and / or method. In one or more embodiments, the processor (802) is a central processing unit (CPU), a multiprocessor, a distributed processing system, an application specific integrated circuit (ASIC), and / or a suitable processing unit.

[0063] In one or more embodiments, the computer-readable storage medium (804) is an electronic, magnetic, optical, electromagnetic, infrared, and / or semiconductor system (or device or apparatus). For example, the computer-readable storage medium (804) includes semiconductor or solid-state memory, magnetic tape, removable computer diskette, random access memory (RAM), read-only memory (ROM), rigid magnetic disk, and / or optical disk. In one or more embodiments using optical disks, the computer-readable storage medium (804) includes a CD-ROM (compact disk-read only memory), a CD-R / W (compact disk-read / write), and / or a DVD (digital video disc).

[0064] In one or more embodiments, the storage medium (804) stores computer program code (806) configured to enable a system (800) (such execution representing (at least partially) an EDA tool) to perform some or all of the mentioned processors and / or methods. In one or more embodiments, the storage medium (804) also stores information that facilitates performing some or all of the mentioned processors and / or methods. In one or more embodiments, the storage medium (804) stores a library (807) of standard cells including such standard cells disclosed herein. In one or more embodiments, the storage medium (804) stores one or more layout diagrams (809) corresponding to one or more layouts disclosed herein.

[0065] The EDA system (800) includes an I / O interface (810). The I / O interface (810) is coupled to an external circuit. In one or more embodiments, the I / O interface (810) includes a keyboard, keypad, mouse, trackball, trackpad, touchscreen, and / or cursor direction keys for transmitting information and commands to a processor (802).

[0066] The EDA screen (800) also includes a network interface (812) coupled to a processor (802). The network interface (812) enables the system (800) to communicate with a network (814), to which one or more other computer systems are connected. The network interface (812) includes a wireless network interface such as BLUETOOTH, WIFI, WIMAX, GPRS, or WCDMA; or a wired network interface such as ETHERNET, USB, or IEEE-1364. In one or more embodiments, some or all of the aforementioned process and / or method is implemented in two or more systems (800).

[0067] The system (800) is configured to receive information through an I / O interface (810). The information received through the I / O interface (810) includes one or more of instructions, data, design rules, a library of standard cells, and / or other parameters for processing by the processor (802). The information is transmitted to the processor (802) via a bus (808). The EDA (800) is configured to receive information related to a user interface (UI) through the I / O interface (810). The information is stored on a computer-readable medium (804) as the UI (842).

[0068] In some embodiments, some or all of the mentioned processes and / or methods are implemented as standalone software applications for execution by a processor. In some embodiments, some or all of the mentioned processes and / or methods are implemented as software applications that are part of additional software applications. In some embodiments, some or all of the mentioned processes and / or methods are implemented as plug-ins into software applications. In some embodiments, at least one of the mentioned processes and / or methods is implemented as a software application that is part of an EDA tool. In some embodiments, some or all of the mentioned processes and / or methods are implemented as software applications used by an EDA system (800). In some embodiments, a layout diagram including standard cells is generated using a tool such as VIRTUOSO®, available from CADENCE DESIGN SYSTEMS Inc., or other suitable layout generation tool.

[0069] In some embodiments, the process is implemented as a function of a program stored on a non-transient computer-readable recording medium. Examples of a non-transient computer-readable recording medium include, but are not limited to, one or more of external / removable and / or internal / embedded storage or memory units, such as optical discs like DVDs, magnetic discs like hard disks, ROM, RAM, and semiconductor memory such as memory cards.

[0070] FIG. 9 is a block diagram of an integrated circuit (IC) manufacturing system (900) and an associated IC manufacturing flow according to some embodiments. In some embodiments, based on a layout diagram, at least one of (A) one or more semiconductor masks or (B) at least one component within a layer of a semiconductor integrated circuit is manufactured using the manufacturing system (900).

[0071] In FIG. 9, the IC manufacturing system (900) includes entities such as a design house (920), a mask house (930), and an IC manufacturer / fab (950), which interact with each other in the design, development, and manufacturing cycles and / or services related to manufacturing an IC device (960). Entities within the system (900) are connected by a communication network. In some embodiments, the communication network is a single network. In some embodiments, the communication network is various different networks, such as an intranet and the Internet. The communication network includes wired and / or wireless communication channels. Each entity interacts with one or more other entities and provides and / or provides services to one or more of the other entities or receives services from them. In some embodiments, two or more of the design house (920), the mask house (930), and the IC fab (950) are owned by a larger single company. In some embodiments, two or more of the design house (920), mask house (930), and IC fab (950) coexist in a common facility and use common resources.

[0072] A design house (or design team) (920) generates an IC design layout diagram (922). The IC design layout diagram (922) includes various geometric patterns designed for an IC device (960). The geometric patterns correspond to patterns of metal, oxide, or semiconductor layers that constitute various components of the IC device (960) to be manufactured. Various layers combine to form various IC features. For example, some of the IC design layout diagrams (922) include various IC features such as active regions, gate electrodes, source and drain, vias for metal lines or interlayer interconnections, and openings for bonding pads to be formed on a semiconductor substrate (e.g., a silicon wafer) and various material layers placed on the semiconductor substrate. The design house (920) implements an appropriate design procedure to form the IC design layout diagram (922). The design procedure includes one or more of logic design, physical design, or placement and routing. The IC design layout diagram (922) is presented in one or more data files containing information on the geometric patterns. For example, the IC design layout diagram (922) can be represented in the GDSII file format or the DFII file format.

[0073] The mask house (930) includes data preparation (932) and mask manufacturing (944). The mask house (930) uses the IC design layout diagram (922) to manufacture one or more masks (945) to be used to manufacture various layers of an IC device (960) according to the IC design layout diagram (922). The mask house (930) performs mask data preparation (932), where the IC design layout diagram (922) is converted into a representative data file (RDF). The mask data preparation (932) provides the RDF to the mask manufacturing (944). The mask manufacturing (944) includes a mask writer. The mask writer converts the RDF into an image on a substrate, such as a mask (reticle) (945) or a semiconductor wafer (953). The design layout diagram (922) is manipulated by the mask data preparation (932) to comply with specific characteristics of the mask writer and / or requirements of the IC fab (950). In FIG. 9, mask data preparation (932) and mask manufacturing (944) are illustrated as separate elements. In some embodiments, mask data preparation (932) and mask manufacturing (944) may be collectively referred to as mask data preparation.

[0074] In some embodiments, mask data preparation (932) includes optical proximity correction (OPC) using lithography enhancement techniques to compensate for image errors that may arise from diffraction, interference, other process effects, etc. OPC adjusts the IC design layout diagram (922). In some embodiments, mask data preparation (932) includes additional resolution enhancement techniques (RET), such as off-axis illumination, sub-resolution assist features, phase-shifting masks, other suitable techniques, or combinations thereof. In some embodiments, inverse lithography technology (ILT) that addresses OPC as an inverse imaging problem is also used.

[0075] In some embodiments, mask data preparation (932) includes a mask rule checker (MRC) that checks the IC design layout diagram (922) in which the process in OPC has been performed with a set of mask generation rules that include specific geometric and / or connection constraints to ensure sufficient margins and to account for variability in the semiconductor manufacturing process. In some embodiments, the MRC modifies the IC design layout diagram (922) to compensate for photolithography implementation effects during mask manufacturing (944), which can cancel some of the modifications performed by OPC to satisfy the mask generation rules.

[0076] In some embodiments, mask data preparation (932) includes lithography process checking (LPC) that simulates the processing to be implemented by the IC fab (950) to manufacture the IC device (960). The LPC simulates this processing based on the IC design layout diagram (922) to produce a simulated manufactured device such as the IC device (960). Processing parameters in the LPC simulation may include parameters associated with various processes of the IC manufacturing cycle, parameters associated with the tools used to manufacture the IC, and / or other aspects of the manufacturing process. The LPC considers various factors such as aerial image contrast, depth of focus (DOF), mask error enhancement factor (MEEF), other appropriate factors, or combinations thereof. In some embodiments, after a simulated manufactured device is generated by LPC, if the simulated device is not geometrically close enough to satisfy the design rules, OPC and / or MRC are repeated to further refine the IC design layout diagram (922).

[0077] It should be understood that the above description of mask data preparation (932) has been simplified for clarity. In some embodiments, data preparation (932) includes additional features, such as logic operations (LOPs), for modifying the IC design layout diagram (922) according to manufacturing rules. Additionally, the processes applied to the IC design layout diagram (922) during data preparation (932) may be executed in various different orders.

[0078] After mask data preparation (932) and during mask manufacturing (944), a mask (945) or a group of masks (945) is manufactured based on a modified IC design layout diagram (922). In some embodiments, mask manufacturing (944) involves performing one or more lithographic exposures based on the IC design layout diagram (922). In some embodiments, an electron beam (e-beam) or a plurality of e-beam mechanisms are used to form a pattern on the mask (photomask or reticle) (945) based on the modified IC design layout diagram (922). The mask (945) can be formed using various techniques. In some embodiments, the mask (945) is formed using binary techniques. In some embodiments, the mask pattern includes opaque regions and transparent regions. A radiation beam, such as an ultraviolet (UV) beam used to expose an image-sensitive material layer (e.g., photoresist) coated on a wafer, is blocked by the opaque regions and transmitted through the transparent regions. In one example, a binary mask version of the mask (945) comprises a transparent substrate (e.g., fused quartz) and an opaque material (e.g., chrome) coated on the opaque areas of the binary mask. In another example, the mask (945) is formed using phase shift technology. In the phase shift mask (PSM) version of the mask (945), various features in the pattern formed on the phase shift mask are configured to have an appropriate phase difference to improve resolution and imaging quality. In various examples, the phase shift mask may be an attenuated PSM or an alternating PSM. The mask(s) produced by mask manufacturing (944) are used in various processes.For example, these mask(s) are used in an ion implantation process for forming various doping regions within a semiconductor wafer (953), in an etching process for forming various etching regions within a semiconductor wafer (953), and / or in other suitable processors.

[0079] An IC fab (950) is an IC manufacturing business comprising one or more manufacturing facilities for manufacturing different IC products. In some embodiments, the IC fab (950) is a semiconductor foundry. For example, there may be a manufacturing facility for the front-end manufacturing (i.e., front-end-of-line (FEOL) manufacturing) of a plurality of IC products, but a second manufacturing facility may provide back-end manufacturing (i.e., back-end-of-line (BEOL) manufacturing) for interconnecting and packaging of IC products, and a third manufacturing facility may provide other services for the foundry business.

[0080] The IC fab (950) includes a manufacturing tool (952) configured to perform various manufacturing operations on a semiconductor wafer (953) so that an IC device (960) is manufactured according to mask(s), e.g., mask (945). In various embodiments, the manufacturing tool (952) includes a wafer stepper, an ion implanter, a photoresist coater, a process chamber, e.g., a CVD chamber or an LPCVD furnace, a CMP system, a plasma etching system, a wafer cleaning system, or one or more of other manufacturing equipment capable of performing one or more of the suitable manufacturing processes discussed herein.

[0081] The IC fab (950) uses mask(s) (945) manufactured by the mask house (930) to manufacture the IC device (960). Thus, the IC fab (950) manufactures the IC device (960) using at least indirectly the IC design layout diagram (922). In some embodiments, a semiconductor wafer (953) is manufactured by the IC fab (950) using the mask(s) (945) to form the IC device (960). In some embodiments, IC manufacturing involves performing one or more lithography exposures based at least indirectly on the IC design layout diagram (922). The semiconductor wafer (953) comprises a silicon substrate or other suitable substrate on which a material layer is formed. The semiconductor wafer (953) further comprises one or more of various doping regions, dielectric features, multi-level interconnects, etc. (formed in a subsequent manufacturing step).

[0082] An aspect of the present disclosure relates to an integrated circuit. The integrated circuit comprises a wide Type 1 active region structure extending in a first direction and a wide Type 2 active region structure, and a narrow Type 1 active region structure extending in a first direction and a narrow Type 2 active region structure. The integrated circuit also comprises a wide Type 1 transistor within the wide Type 1 active region structure and a narrow Type 1 transistor within the narrow Type 1 active region structure, and a wide Type 2 transistor within the wide Type 2 active region structure and a narrow Type 2 transistor within the narrow Type 2 active region structure. The average gate width of the wide Type 1 transistor is greater than the average gate width of the narrow Type 1 transistor. The average gate width of the wide Type 2 transistor is greater than the average gate width of the narrow Type 2 transistor. The integrated circuit also comprises a first inverter, a first transmission gate, and a second inverter made of a wide Type 1 transistor and a wide Type 2 transistor. The first transmission gate is coupled between the output of the first inverter and the input of the second inverter. The integrated circuit further includes a first clock inverter and a second clock inverter made of a narrow Type 1 transistor and a narrow Type 2 transistor. The first clock inverter is coupled between the output of the first inverter and the input of the first inverter to form a master latch, and the second clock inverter is coupled between the output of the second inverter and the input of the second inverter to form a slave latch.

[0083] Another aspect of the present disclosure relates to an integrated circuit. The integrated circuit comprises a wide Type 1 active region structure extending in a first direction and a wide Type 2 active region structure, and a narrow Type 1 active region structure extending in a first direction and a narrow Type 2 active region structure. The integrated circuit also comprises a wide Type 1 transistor within the wide Type 1 active region structure and a narrow Type 1 transistor within the narrow Type 1 active region structure, and a wide Type 2 transistor within the wide Type 2 active region structure and a narrow Type 2 transistor within the narrow Type 2 active region structure. The average gate width of the wide Type 1 transistor is greater than the average gate width of the narrow Type 1 transistor. The average gate width of the wide Type 2 transistor is greater than the average gate width of the narrow Type 2 transistor. The integrated circuit also comprises a clock gate input circuit made of a wide Type 1 transistor and a wide Type 2 transistor, a first inverter, and an output driver. The first inverter is coupled between the output of the clock gate input circuit and the input of the output driver. The integrated circuit further includes a first clock inverter made of a narrow Type 1 transistor and a narrow Type 2 transistor. The first clock inverter is coupled between the output of the first inverter and the input of the first inverter to form a latch.

[0084] Another aspect of the present disclosure relates to a method. The method comprises the steps of manufacturing a wide Type 1 active region structure and a narrow Type 1 active region structure extending in a first direction, and manufacturing a wide Type 2 active region structure and a narrow Type 2 active region structure extending in the first direction. The average width of the wide Type 1 active region structure is greater than the average width of the narrow Type 1 active region structure. The average width of the wide Type 2 active region structure is greater than the average width of the narrow Type 2 active region structure. The method also comprises the steps of forming a first inverter, a first transmission gate, and a second inverter using a wide Type 1 transistor within the wide Type 1 active region structure and a wide Type 2 transistor within the wide Type 2 active region structure, and forming a first clock inverter and a second clock inverter using a narrow Type 1 transistor within the narrow Type 1 active region structure and a narrow Type 2 transistor within the narrow Type 2 active region structure. The first transmission gate is coupled between the output of the first inverter and the input of the second inverter. The method further includes the steps of connecting the input of a first clock inverter to the output of a first inverter, connecting the output of a first clock inverter to the input of a first inverter, connecting the input of a second clock inverter to the output of a second inverter, and connecting the output of a second clock inverter to the input of a second inverter.

[0085] A person skilled in the art will readily understand that one or more of the disclosed embodiments satisfy one or more of the advantages described above. After reading the foregoing specification, a person skilled in the art will be able to make various modifications, substitutes of equivalents, and various other embodiments as disclosed herein for the task. Accordingly, the protection granted herein is intended to be limited only by the definitions contained in the appended claims and their equivalents.

[0087] Examples

[0088] 1. In integrated circuits,

[0089] A wide Type 1 active area structure extending in the first direction and a wide Type 2 active area structure;

[0090] A narrow Type 1 active region structure and a narrow Type 2 active region structure extending in the first direction;

[0091] A wide Type 1 transistor within the wide Type 1 active region structure and a narrow Type 1 transistor within the narrow Type 1 active region structure - the average gate width of the wide Type 1 transistor is greater than the average gate width of the narrow Type 1 transistor - ;

[0092] A wide Type 2 transistor within the wide Type 2 active region structure and a narrow Type 2 transistor within the narrow Type 2 active region structure - the average gate width of the wide Type 2 transistor is greater than the average gate width of the narrow Type 2 transistor - ;

[0093] A first inverter, a first transmission gate, and a second inverter formed by the wide Type 1 transistor and the wide Type 2 transistor, wherein the first transmission gate is coupled between the output of the first inverter and the input of the second inverter; and

[0094] A first clock inverter and a second clock inverter formed by the above-mentioned narrow Type 1 transistor and the above-mentioned narrow Type 2 transistor - the first clock inverter is coupled between the output of the first inverter and the input of the first inverter to form a master latch, and the second clock inverter is coupled between the output of the second inverter and the input of the second inverter to form a slave latch -

[0095] An integrated circuit including

[0097] 2. In Paragraph 1,

[0098] A clock gate input circuit having a gate inverter formed by the wide Type 1 transistor and the wide Type 2 transistor—the first inverter is coupled between the output of the gate inverter and the input of the first transmission gate—

[0099] An integrated circuit that further includes

[0101] 3. In Paragraph 1,

[0102] A clock gate input circuit having a second transmission gate formed by the wide Type 1 transistor and the wide Type 2 transistor - the first inverter is coupled between the output of the second transmission gate and the input of the first transmission gate -

[0103] An integrated circuit that further includes

[0105] 4. In Paragraph 1,

[0106] A clock gate input circuit formed by the wide Type 1 transistor and the wide Type 2 transistor - the input of the first inverter is connected to the output of the clock gate input circuit and the output of the first inverter is connected to the input of the first transmission gate, and the clock gate input circuit, the first inverter, the first transmission gate, and the second inverter are arranged in order along the first direction -

[0107] An integrated circuit that further includes

[0109] 5. In Paragraph 1,

[0110] An output driver formed by the wide Type 1 transistor and the wide Type 2 transistor - the second inverter is coupled between the output of the first transmission gate and the input of the output driver -

[0111] An integrated circuit that further includes

[0113] 6. In Paragraph 5,

[0114] An integrated circuit arranged along the first direction in the order of the first inverter, the first transmission gate, the second inverter, and the output driver.

[0116] 7. In Paragraph 5,

[0117] An integrated circuit comprising a clock gate input circuit made of the wide Type 1 transistor and the wide Type 2 transistor, wherein the clock gate input circuit, the first inverter, the first transmission gate, the second inverter, and the output driver are arranged along the first direction.

[0119] 8. In Paragraph 1,

[0120] An integrated circuit in which the wide Type 1 active region structure and the wide Type 2 active region structure are laterally positioned between the narrow Type 1 active region structure and the narrow Type 2 active region structure.

[0122] 9. In Paragraph 1,

[0123] An integrated circuit in which the narrow Type 1 active region structure and the narrow Type 2 active region structure are laterally positioned between the wide Type 1 active region structure and the wide Type 2 active region structure.

[0125] 10. In Paragraph 1,

[0126] An integrated circuit wherein the wide Type 1 active region structure and the wide Type 2 active region structure form a first pair of adjacent active region structures, and the narrow Type 1 active region structure and the narrow Type 2 active region structure form a second pair of adjacent active region structures.

[0128] 11. In Paragraph 10,

[0129] An integrated circuit in which the wide Type 1 active region structure and the narrow Type 1 active region structure are laterally positioned between the wide Type 2 active region structure and the narrow Type 2 active region structure.

[0131] 12. In Paragraph 1,

[0132] An integrated circuit in which the first average width of the wide Type 1 active region structure within the area used to make the wide Type 1 transistor is greater than the second average width of the narrow Type 1 active region structure within the area used to make the narrow Type 1 transistor.

[0134] 13. In Paragraph 1,

[0135] An integrated circuit in which the first average width of the wide Type 2 active region structure within the area used to make the wide Type 2 transistor is greater than the second average width of the narrow Type 2 active region structure within the area used to make the narrow Type 2 transistor.

[0137] 14. In Paragraph 1,

[0138] An integrated circuit in which the first inverter is a resettable inverter and the second clock inverter is a resettable clock inverter.

[0140] 15. In integrated circuits,

[0141] A wide Type 1 active area structure extending in the first direction and a wide Type 2 active area structure;

[0142] A narrow Type 1 active region structure and a narrow Type 2 active region structure extending in the first direction;

[0143] A wide Type 1 transistor within the wide Type 1 active region structure and a narrow Type 1 transistor within the narrow Type 1 active region structure - the average gate width of the wide Type 1 transistor is greater than the average gate width of the narrow Type 1 transistor - ;

[0144] A wide Type 2 transistor within the wide Type 2 active region structure and a narrow Type 2 transistor within the narrow Type 2 active region structure - the average gate width of the wide Type 2 transistor is greater than the average gate width of the narrow Type 2 transistor - ;

[0145] A clock gate input circuit, a first inverter, and an output driver formed by the wide Type 1 transistor and the wide Type 2 transistor—the first inverter is coupled between the output of the clock gate input circuit and the input of the output driver—; and

[0146] A first clock inverter formed by the above-mentioned narrow Type 1 transistor and the above-mentioned narrow Type 2 transistor - the first clock inverter is coupled between the output of the first inverter and the input of the first inverter to form a latch -

[0147] An integrated circuit including

[0149] 16. In Paragraph 15,

[0150] The above clock gate input circuit is an integrated circuit that is a clock inverter.

[0152] 17. In Paragraph 15,

[0153] The above output driver is an integrated circuit that is a buffer or an inverter.

[0155] 18. In Paragraph 15,

[0156] An integrated circuit in which the average width of the wide Type 1 active region structure within the area used to make the wide Type 1 transistor is greater than the average width of the narrow Type 1 active region structure within the area used to make the narrow Type 1 transistor, and the average width of the wide Type 2 active region structure within the area used to make the wide Type 2 transistor is greater than the average width of the narrow Type 2 active region structure within the area used to make the narrow Type 2 transistor.

[0158] 19. Regarding the method,

[0159] Step of manufacturing a wide Type 1 active region structure and a narrow Type 1 active region structure extending in a first direction - the average width of the wide Type 1 active region structure is greater than the average width of the narrow Type 1 active region structure - ;

[0160] Step of manufacturing a wide Type 2 active region structure and a narrow Type 2 active region structure extending in the first direction - the average width of the wide Type 2 active region structure is greater than the average width of the narrow Type 2 active region structure - ;

[0161] A step of forming a first inverter, a first transmission gate, and a second inverter using a wide Type 1 transistor within the wide Type 1 active region structure and a wide Type 2 transistor within the wide Type 2 active region structure - the first transmission gate is coupled between the output of the first inverter and the input of the second inverter - ;

[0162] A step of forming a first clock inverter and a second clock inverter using a narrow Type 1 transistor within the narrow Type 1 active region structure and a narrow Type 2 transistor within the narrow Type 2 active region structure; and

[0163] A step of connecting the input of the first clock inverter to the output of the first inverter, connecting the output of the first clock inverter to the input of the first inverter, connecting the input of the second clock inverter to the output of the second inverter, and connecting the output of the second clock inverter to the input of the second inverter.

[0164] A method including

[0166] 20. In Paragraph 19,

[0167] A method of forming a clock gate input circuit and an output driver using the wide Type 1 transistor and the wide Type 2 transistor, wherein the clock gate input circuit, the first inverter, the first transmission gate, the second inverter, and the output driver are arranged along the first direction in that order.

Claims

Claim 1 In an integrated circuit, a wide Type 1 active region structure and a wide Type 2 active region structure extending in a first direction; a narrow Type 1 active region structure and a narrow Type 2 active region structure extending in the first direction; a wide Type 1 transistor within the wide Type 1 active region structure and a narrow Type 1 transistor within the narrow Type 1 active region structure - the average gate width of the wide Type 1 transistor is greater than the average gate width of the narrow Type 1 transistor -; a wide Type 2 transistor within the wide Type 2 active region structure and a narrow Type 2 transistor within the narrow Type 2 active region structure - the average gate width of the wide Type 2 transistor is greater than the average gate width of the narrow Type 2 transistor -; a first inverter, a first transmission gate, and a second inverter - each of the first inverter, the first transmission gate, and the second inverter is made using both the wide Type 1 transistor and the wide Type 2 transistor, and the first transmission gate is coupled between the output of the first inverter and the input of the second inverter -; An integrated circuit comprising: a first clock inverter and a second clock inverter formed by the narrow type 1 transistor and the narrow type 2 transistor, wherein the first clock inverter is coupled between the output of the first inverter and the input of the first inverter to form a master latch, and the second clock inverter is coupled between the output of the second inverter and the input of the second inverter to form a slave latch. Claim 2 An integrated circuit according to claim 1, further comprising a clock gate input circuit having a gate inverter made of the wide type 1 transistor and the wide type 2 transistor, wherein the first inverter is coupled between the output of the gate inverter and the input of the first transmission gate. Claim 3 An integrated circuit according to claim 1, further comprising a clock gate input circuit having a second transmission gate formed by the wide type 1 transistor and the wide type 2 transistor, wherein the first inverter is coupled between the output of the second transmission gate and the input of the first transmission gate. Claim 4 An integrated circuit according to claim 1, further comprising a clock gate input circuit formed by the wide Type 1 transistor and the wide Type 2 transistor— wherein the input of the first inverter is connected to the output of the clock gate input circuit and the output of the first inverter is connected to the input of the first transmission gate, and the clock gate input circuit, the first inverter, the first transmission gate, and the second inverter are arranged in order along the first direction. Claim 5 An integrated circuit according to claim 1, further comprising an output driver made of the wide type 1 transistor and the wide type 2 transistor, wherein the second inverter is coupled between the output of the first transmission gate and the input of the output driver. Claim 6 An integrated circuit according to claim 1, wherein the wide Type 1 active region structure and the wide Type 2 active region structure are laterally positioned between the narrow Type 1 active region structure and the narrow Type 2 active region structure. Claim 7 An integrated circuit according to claim 1, wherein the narrow Type 1 active region structure and the narrow Type 2 active region structure are laterally positioned between the wide Type 1 active region structure and the wide Type 2 active region structure. Claim 8 An integrated circuit according to claim 1, wherein the wide Type 1 active region structure and the wide Type 2 active region structure form a first pair of adjacent active region structures, and the narrow Type 1 active region structure and the narrow Type 2 active region structure form a second pair of adjacent active region structures. Claim 9 In an integrated circuit, a wide Type 1 active region structure and a wide Type 2 active region structure extending in a first direction; a narrow Type 1 active region structure and a narrow Type 2 active region structure extending in the first direction; a wide Type 1 transistor within the wide Type 1 active region structure and a narrow Type 1 transistor within the narrow Type 1 active region structure - the average gate width of the wide Type 1 transistor is greater than the average gate width of the narrow Type 1 transistor -; a wide Type 2 transistor within the wide Type 2 active region structure and a narrow Type 2 transistor within the narrow Type 2 active region structure - the average gate width of the wide Type 2 transistor is greater than the average gate width of the narrow Type 2 transistor -; a clock gate input circuit, a first inverter, a first transmission gate, a second inverter, and an output driver - each of the clock gate input circuit, the first inverter, the first transmission gate, the second inverter, and the output driver is constructed using both the wide Type 1 transistor and the wide Type 2 transistor, and the first inverter is the output of the clock gate input circuit and the An integrated circuit comprising: a first transmission gate coupled between inputs, and a second inverter coupled between output of the first transmission gate and input of the output driver; and a first clock inverter made of the narrow type 1 transistor and the narrow type 2 transistor, wherein the first clock inverter is coupled between output of the first inverter and input of the first inverter to form a latch. Claim 10 A method comprising the steps of: manufacturing a wide Type 1 active region structure and a narrow Type 1 active region structure extending in a first direction, wherein the average width of the wide Type 1 active region structure is greater than the average width of the narrow Type 1 active region structure; manufacturing a wide Type 2 active region structure and a narrow Type 2 active region structure extending in the first direction, wherein the average width of the wide Type 2 active region structure is greater than the average width of the narrow Type 2 active region structure; forming a first inverter, a first transmission gate, and a second inverter, wherein each of the first inverter, the first transmission gate, and the second inverter is made using both the wide Type 1 transistor and the wide Type 2 transistor, and the first transmission gate is coupled between the output of the first inverter and the input of the second inverter; and forming a first clock inverter and a second clock inverter using a narrow Type 1 transistor within the narrow Type 1 active region structure and a narrow Type 2 transistor within the narrow Type 2 active region structure. A method comprising the steps of connecting the input of the first clock inverter to the output of the first inverter, connecting the output of the first clock inverter to the input of the first inverter, connecting the input of the second clock inverter to the output of the second inverter, and connecting the output of the second clock inverter to the input of the second inverter.

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