Semiconductor device with dielectric structure in channel region and manufacturing methods thereof

Abstract

The present disclosure provides a semiconductor device and a method for forming the same. A method according to one embodiment of the present disclosure comprises the steps of forming a plurality of semiconductor nanostructures vertically stacked on a substrate; forming a dielectric structure floating on the uppermost semiconductor nanostructure among the semiconductor nanostructures; forming a plurality of inner spacers interleaved with the semiconductor nanostructures; forming an epitaxial feature in contact with the semiconductor nanostructures; and forming a gate structure surrounding each of the semiconductor nanostructures and the dielectric structure.

Description

Technology Field

[0001] Priority Information

[0002] This application claims priority to U.S. provisional patent application No. 63 / 620,225 filed January 12, 2024, the full disclosure thereof of which is incorporated herein by reference. Background Technology

[0003] The semiconductor integrated circuit (IC) industry has grown rapidly. Technological advancements in IC materials and design have led to generations of ICs featuring smaller and more complex circuits than the previous one. Throughout the evolution of ICs, functional density (i.e., the number of interconnected devices per chip area) has generally increased, while geometric size (i.e., the smallest component (or line) that can be produced using a manufacturing process) has decreased. This scaling down process generally offers benefits by increasing production efficiency and lowering associated costs. However, such reduction has also increased the complexity of IC processing and manufacturing.

[0004] For example, as IC technology advances to smaller nodes, multi-gate metal-oxide-semiconductor field effect transistors (multi-gate MOSFETs, or multi-gate devices) have been introduced to improve gate control by increasing gate-channel coupling, reducing off-state current, and reducing short-channel effects (SCE). Multi-gate devices generally refer to devices having a gate structure or part thereof positioned over more than one side of the channel region. Fin-like field effect transistors (FinFETs) and gate-all-around (GAA) transistors are examples of multi-gate devices that have become popular and promising candidates for high-performance and low-leakage applications. FinFETs have a raised channel where more than one side is wrapped by the gate (for example, the gate wraps the top and sidewalls of the "fins" of the semiconductor material extending from the substrate). The GAA transistor has a gate structure that can extend around the channel region to provide access to the channel region on all four sides.

[0005] To improve the performance of GAA transistors, efforts are being made to develop structures within channel regions that improve the uniformity of metal gate heights and channel member thicknesses. Conventional channel region structures are generally suitable for their intended purposes, but are not satisfactory in all aspects. Brief explanation of the drawing

[0006] The embodiments of the present disclosure are best understood from the content when the specific details for carrying out the invention described below are read together with the accompanying drawings. It should be emphasized that, in accordance with standard practice in the art, the various features are not drawn to scale. In fact, the dimensions of the various features may be increased or decreased at will to clarify the discussion. FIGS. 1a and 1b illustrate a flowchart of an exemplary method for manufacturing a semiconductor device according to some embodiments of the present disclosure. FIGS. 2a, 3a, 4a, 5a, 6a, 7a, 8a, 9a, 10a, 11a, 12a, 13a, 14a, 15a, 16a, 17a, 18a, 19a, 20a, 21a, 22a, 23a, 24a, 25a, 26a, 27a, 28a, 29a, 30a, 31a, 32a, and 33a illustrate perspective views of semiconductor devices configured according to the method of FIGS. 1a and 1b, according to some embodiments. FIGS. 2b, 3b, 4b, 5b, 6b, 7b, 8b, 9b, 10b, 11b, 12b, 13b, 14b, 15b, 16b, 17b, 18b, 19b, 20b, 21b, 22b, 23b, 24b, 25b, 26b, 27b, 28b, 29b, 30b, 31b, 32b, and 33b illustrate, respectively, cross-sectional views in the YZ plane of a portion of a semiconductor device during a manufacturing process according to the method of FIGS. 1a and 1b, according to some embodiments of the present disclosure. FIGS. 2c, 3c, 4c, 5c, 6c, 7c, 8c, 9c, 10c, 11c, 12c, 13c, 14c, 15c, 16c, 17c, 18c, 19c, 20c, 21c, 22c, 23c, 24c, 25c, 26c, 27c, 28c, 29c, 30c, 31c, 32c, and 33c illustrate, respectively, cross-sectional views in the XZ plane of a portion of a semiconductor device during a manufacturing process according to the method of FIG. 1a and 1b, according to some embodiments of the present disclosure. Specific details for implementing the invention

[0007] The following disclosure provides many different embodiments or examples for implementing different features of the present disclosure. To simplify the present disclosure, specific examples of components and arrangements are described below. These are, of course, merely examples and are not intended to be limiting. For example, in the following description, forming a first feature on or above a second feature may include embodiments in which the first feature and the second feature are formed in direct contact, and may also include embodiments in which an additional feature is formed between the first feature and the second feature so that the first feature and the second feature do not come into direct contact. Additionally, the present disclosure may repeat reference numbers and / or letters in various examples. Such repetition is for the purpose of simplification and clarification, and such repetition itself does not affect the relationship between the various embodiments and / or configurations discussed.

[0008] Additionally, the present disclosure may repeat reference numbers and / or letters in various examples. Such repetition is intended for simplification and clarification, and the repetition itself does not affect the relationships between the various embodiments and / or configurations discussed. Furthermore, in the following disclosure, a feature being formed on another feature, formed connected thereto, and / or formed in combination thereto may include an embodiment in which the features are formed in direct contact, and may also include an embodiment in which an additional feature is formed between the features so that the features do not come into direct contact. In addition, spatially relative terms, such as "lower," "upper," "horizontal," "vertical," "above," "over," "below," "beneath," "up," "down," "top," and "bottom," as well as their derivatives (e.g., "horizontally," "downwardly," "upwardly"), are used to facilitate the initiation of a relationship between one feature and another. Spatially relative terms are intended to cover different orientations of the device containing the feature. Additionally, when a number or a range of numbers is described as “about,” “approximately,” etc., this term is intended to encompass numbers within a reasonable range that includes the described number, such as within + / - 10% of the described number or within other values ​​as understood by those skilled in the art. For example, the term “about 5 nm” encompasses a dimensional range of 4.5 nm to 5.5 nm.

[0009] The present disclosure provides a semiconductor device having a dielectric structure floating on semiconductor nanostructures vertically stacked within the channel region of a gate all around (GAA) transistor.

[0010] The channel region of a GAA transistor may be placed within semiconductor nanostructures (also referred to as channel members), such as nanowire channel members, bar-shaped channel members, nanosheet channel members, column-shaped channel members, post-shaped channel members, and / or other suitable channel configurations. Depending on the shape of the channel members, the GAA transistor may also be referred to as a nanowire transistor or a nanosheet transistor. Regardless of its shape, each of the channel members of the GAA transistor extends between and is coupled to two epitaxial features within two opposing source / drain regions. The epitaxial features are also referred to as source / drain features or source / drain epitaxial features. The source / drain region(s) may refer to the source or drain individually or collectively, depending on the context. During the replacement gate process, a dummy gate stack is removed to form a gate trench, exposing the channel layers. Subsequently, the interleaving sacrificial layers are removed to release the channel layers into channel members. A metal gate structure is then deposited on and between the channel members to surround them, and a planarization process, such as chemical mechanical planarization (CMP), is performed to reset the metal gate structure. During the removal of the dummy gate stack, the top channel layer may suffer some etching loss from above due to limited etching contrast. Consequently, the top channel layer may become thinner than the other channel members underneath, leading to channel member thickness inconsistency. Process variations during the planarization of the metal gate structure can also result in metal gate height inconsistency.

[0011] The present disclosure provides embodiments of a semiconductor device in which a dielectric structure is provided on a stack of channel members within a channel region. In some embodiments, the dielectric structure may be formed from a hard mask layer. This additional dielectric structure within the channel region provides etching protection during the removal of the dummy gate stack. The dielectric structure also functions as a planarization stop layer to define a uniform top surface of metal gate structures during a metal gate planarization process. Accordingly, the uniformity of both metal gate heights and channel member thicknesses is improved.

[0012] FIG. 1a illustrates a flowchart of a method (100) for manufacturing a semiconductor device according to various embodiments of the present disclosure. FIG. 1b illustrates an alternative embodiment of the method (100). Additional processing is considered by the present disclosure. Additional operations may be provided before, during, and after the method (100), and some of the operations described may be moved, replaced, or removed for additional embodiments of the method (100). FIG. 1a and FIG. 1b are described below together with FIG. 2a through FIG. 33c, which illustrate various perspective and cross-sectional views of a semiconductor device (or device) (200) at various steps of manufacturing according to the method (100) according to some embodiments. In some embodiments, the device (200) is an IC chip, a system on a chip (SoC), or a part thereof, comprising various passive and active microelectronic devices such as a resistor, a capacitor, an inductor, a diode, a p-type field effect transistor (PFET), an n-type field effect transistor (NFET), a FinFET, a nanosheet FET, a nanowire FET, other types of multi-gate FETs, a metal-oxide-semiconductor field effect transistor (MOSFET), a complementary metal-oxide-semiconductor (CMOS) transistor, a bipolar junction transistor (BJT), a laterally diffused MOS (LDMOS) transistor, a high-voltage transistor, a high-frequency transistor, a memory device, other suitable components, or a combination thereof. FIGS. 2a through 33c have been simplified to make it clearer to better understand the inventive concepts of the present disclosure.Additional features may be added within the device (200), and some of the features described below may be replaced, modified, or removed in other embodiments of the device (200).

[0013] In operation (102), the method (100) (Fig. 1a) provides a device (200) having a substrate (202), a stack (204) disposed on the substrate (202), a first hard mask layer (210) disposed on the stack (204), and a second hard mask layer (212) disposed on the first hard mask layer (210), as illustrated in Figs. 2a illustrates a perspective view of the device (200), and Figs. 2b and 2c each partially illustrate cross-sectional views of the device (200) along the A-A line and the B-B line of Fig. 2a. In particular, the A-A line is a cut along the longitudinal direction (direction "Y" or Y direction) of the gate structures to be formed, and the B-B line is a cut along the longitudinal direction (direction "X" or X direction) of the channel members to be formed. The A-A lines and B-B lines in FIGS. 3a to 31c are also configured similarly.

[0014] In some embodiments, the substrate (202) is a semiconductor substrate, such as a silicon (Si) substrate. The substrate (202) may include various doping configurations according to design requirements known in the art. In embodiments where the semiconductor device is of the p type, an n-type doping profile (i.e., an n-type well or an n-well) may be formed on the substrate (202). In some embodiments, the n-type dopant for forming the n-type well may include phosphorus (P) or arsenic (As). In embodiments where the semiconductor device is of the n type, a p-type doping profile (i.e., a p-type well or a p-well) may be formed on the substrate (202). In some embodiments, the p-type dopant for forming the p-type well may include boron (B) or gallium (GA). Suitable doping may include ion implantation and / or diffusion processes of the dopants. The substrate (202) may also include other semiconductors such as germanium (Ge), silicon carbide (SiC), silicon germanium (SiGe), or diamond. Alternatively, the substrate (202) may include a compound semiconductor and / or an alloy semiconductor. Furthermore, the substrate (202) may optionally include an epitaxial layer (epi layer), be strained for performance enhancement, include a silicon-on-insulator (SOI) or germanium-on-insulator (GeOI) structure, and / or have other suitable enhancement features.

[0015] In some embodiments, the stack (204) comprises sacrificial layers (206) of a first semiconductor composition interleaved by channel layers (208) of a second semiconductor composition. The first semiconductor composition and the second semiconductor composition may be different. In some embodiments, the sacrificial layers (206) comprise silicon germanium (SiGe), and the channel layers (208) comprise silicon (Si). It should be noted that four (4) layers of sacrificial layers (206) and three (3) layers of channel layers (208) are arranged alternately as illustrated in FIG. 2a, which is for exemplary purposes only and is not intended to limit beyond what is explicitly stated in the claims. It may be understood that any number of epitaxial layers may be formed within the stack (204). The number of layers depends on the required number of channel members for the semiconductor device (200). In some embodiments, the number of channel layers (208) is 1 to 20.

[0016] In some embodiments, all sacrificial layers (206) may have a substantially uniform first thickness of about 3 nm to about 10 nm, and all channel layers (208) may have a substantially uniform second thickness of about 3 nm to about 8 nm. The first thickness and the second thickness may be the same or different. As described in more detail below, the channel layers (208) or parts thereof may serve as channel members(s) for a multi-gate device to be subsequently formed, and the thickness of each channel layer (208) is selected based on device performance considerations. The epitaxial layers (206) within the channel region(s) may eventually be removed and serve to define the vertical distance between adjacent channel region(s) for a multi-gate device to be subsequently formed, and the thickness of each sacrificial layer (206) is selected based on device performance considerations.

[0017] In the illustrated embodiment, the stack (204) further comprises a top sacrificial layer (208T) disposed on the top sacrificial layer among the sacrificial layers (206). In some cases, the composition of the channel layers (208) and the top sacrificial layer (208T) is substantially the same, such as silicon (Si). The top sacrificial layer (208T) serves to protect the stack (204) from damage during the manufacturing process. The top sacrificial layer (208T) may be thinner than either of the channel layers (208) and the sacrificial layers (206). In some cases, the thickness of the top sacrificial layer (208T) may be about 1 nm to about 2 nm.

[0018] Semiconductor layers within the stack (204) may be deposited using a molecular beam epitaxy (MBE) process, a vapor deposition (VPE) process, and / or other suitable epitaxial growth processes. Accordingly, the stack (204) is also referred to as an epitaxial stack (204), and the layers (206 and 208) are also referred to as epitaxial layers (206 and 208). As described above, in at least some examples, the sacrificial layers (206) comprise an epitaxially grown silicon germanium (SiGe) layer, the channel layer (208) comprises an epitaxially grown silicon (Si) layer, and the top sacrificial layer (208T) comprises an epitaxially grown silicon (Si) layer. In some embodiments, the sacrificial layers (206), channel layers (208), and top sacrificial layers (208T) are substantially dopant-free, for example, and no intentional doping is performed during the epitaxial growth processes for the stack (204). In some embodiments, the top surface of the substrate (202) is within the (100) crystalline plane, and accordingly, each layer of the stack (204) has the (100) top surface. In some alternative embodiments, the top surface of the substrate is within the (110) crystalline plane, and accordingly, each layer of the stack (204) has the (110) top surface.

[0019] Referring further to FIGS. 2a through 2c, the first hard mask layer (210) may comprise a metal oxide, silicon nitride (SiN), silicon carbonitride (SiCN), silicon oxycarbonate (SiOC), silicon oxycarbonite (SiOCN), or a low k dielectric material. The metal oxide may comprise aluminum oxide, zirconium oxide, tantalum oxide, yttrium oxide, titanium oxide, lanthanum oxide, or other suitable metal oxides. Although not explicitly illustrated, the first hard mask layer (210) may be a single layer or a multilayer, such as a two-layer structure having two different material compositions. In some embodiments, the first hard mask layer (210) may be deposited using chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or other suitable processes, including low pressure CVD (LPCVD) and plasma enhanced CVD (PECVD). As described in more detail below, the first hard mask layer (210) will be patterned with dielectric features floating over channel members within the channel region to protect the top channel member from etching loss and also to function as a planarization stop layer to improve metal gate height uniformity. In some embodiments, the first hard mask layer (210) has a thickness in the range of about 2 nm to about 20 nm. This range is not arbitrary or trivial. If the thickness is less than about 2 nm, the resulting dielectric feature will be too thin to effectively function as a planarization stop layer; If the thickness exceeds about 20 nm, the remaining portion of the dielectric feature in the final structure is too thick and will increase the metal gate height, which consequently leads to an increase in parasitic capacitance and can slow down the circuit speed.

[0020] A second hard mask layer (212) is deposited on a first hard mask layer (210). In some embodiments, the second hard mask layer (212) may be deposited using CVD, LPCVD, PECVD, PVD, ALD, or other suitable methods. The second hard mask layer (212) may be a single layer or a multilayer. When the second hard mask layer (212) is a multilayer, the second hard mask layer (212) may include a pad oxide layer and a pad nitride layer. The pad oxide layer may be made of silicon oxide, and the pad nitride layer may be made of silicon nitride. In various embodiments, the first hard mask layer (210) and the second hard mask layer (212) have different material compositions that allow the second hard mask layer (212) to be removed in an optional etching process without causing etching loss to the first hard mask layer (210) (or with minimal etching loss). In some embodiments, the second hard mask layer (212) has a thickness in the range of about 2 nm to about 20 nm. In some additional embodiments, the thickness of the second hard mask layer (212) is greater than the thickness of the first hard mask layer (210). Alternatively, the thickness of the second hard mask layer (212) may be smaller than the thickness of the first hard mask layer (210).

[0021] In operation (104), method (100) (Fig. 1a) patterns a stack (204) to form semiconductor pins (214) (also referred to as pins (214)), as illustrated in Figs. 3a through 3c. The pins (214) may be patterned from the stack (204) and the substrate (202) using a lithography process and an etching process. The lithography process may include photoresist coating (e.g., spin-on coating), soft baking, mask alignment, exposure, post-exposure baking, photoresist development, rinsing, drying (e.g., spin drying and / or hard baking), other suitable lithography techniques and / or combinations thereof. In some embodiments, the etching process may include dry etching (e.g., reactive-ion etching (RIE)), wet etching, and / or other etching methods. The second hard mask layer (212) is patterned with a mask pattern. Through the openings defined in the patterned second hard mask layer (212), the etching process sequentially forms trenches that extend through the first hard mask layer (210), the stack (204), and the top of the substrate (202). The trenches define the pins (214). In some embodiments, for example, a double patterning process or a multi-patterning process may be used to define pin-shaped structures having pitches smaller than otherwise obtainable using a single direct photolithography process. For example, in one embodiment, a material layer is formed on the substrate and patterned using a photolithography process. Spacers are formed alongside the patterned material layer using a self-alignment process. Then, the material layer is removed, and the remaining spacers or mandrels can be used to pattern pins (214) by etching the top of the stack (204) and the substrate (202). The patterned top of the substrate (202) is also referred to as a pin-shaped base (214B).The pin-shaped base (214B) may also be considered as the top surface of the substrate (202) as required by the situation. In the illustrated embodiment, the pins (214), including the patterned stack (204) and the pin-shaped base (214B), extend vertically along the Z direction and lengthwise along the X direction. In some cases, the pins (214) are measured with a width of about 6 nm to about 80 nm along the Y direction, and the distance between the opposing sidewalls of two adjacent pins (214) is measured with a width of about 6 nm to about 115 nm along the Y direction. In FIGS. 3a through 3c, three (3) pins (214) are spaced apart along the Y direction. However, the number of pins (214) is not limited to three and may be one, two, or more than three.

[0022] In operation (106), method (100) (Fig. 1a) deposits a dielectric material within trenches between adjacent pins (214) to form an isolation feature (218), as illustrated in Figs. 4a through 4c, Figs. 5a through 5c, and Figs. 6a through 6c. The isolation feature (218) may include one or more dielectric layers. A dielectric material suitable for the isolation feature (218) may include silicon oxide, silicon nitride, silicon carbide, FSG (fluorosilicate glass), low k dielectric material, and / or other suitable dielectric materials. The dielectric material may be deposited by any suitable technique including thermal growth, CVD, HDP-CVD, PVD, ALD, and / or spin-on techniques. Then, as illustrated in Figs. 4a through 4c, a planarization operation, such as a CMP process, is performed to expose the top surface of the second hard mask layer (212). Subsequently, as illustrated in FIGS. 5a through 5c, a selective etching process is performed to remove the second hard mask layer (212). The selective etching process is adjusted to be selective to the material(s) within the patterned second hard mask layer (212), and the patterned first hard mask layer (210) and the isolation feature (218) remain substantially intact. After the patterned first hard mask layer (210) is exposed, the isolation feature (218) is reset to form a shallow trench isolation (STI) feature (hereinafter also referred to as the STI feature (218)). Any suitable etching technique including dry etching, wet etching, RIE, and / or other etching methods may be used to reset the isolation features (218), and in exemplary embodiments, as illustrated in FIGS. 6a through 6c, anisotropic dry etching is used to selectively remove the dielectric material of the isolation features (218) without etching the pins (214) (including the first hard mask layer (210)).In the illustrated embodiment, the top surface of the STI feature (218) may be below the bottom surface of the stack (204). Alternatively, according to some other embodiments, the top surface of the STI feature (218) may be coplanar with the bottom surface of the stack (204). At the end of the operation (106), the patterned second hard mask layer (212) is removed and the patterned first hard mask layer (210) remains, so the patterned first hard mask layer (210) may also be simply referred to as a hard mask feature (or just "hard mask") (210), a dielectric feature (210), a dielectric structure (210), or a dielectric nanostructure (210).

[0023] In operation (108), method (100) (Fig. 1a) forms a sacrifice (dummy) gate structure (226) as illustrated in Figs. 7a through 7c. In the exemplary embodiment, one sacrifice gate structure (226) is illustrated, but the number of sacrifice gate structures (226) is not limited to one, and two or more sacrifice gate structures are arranged in the X direction. The sacrifice gate structure (226) is formed on parts of the pins (214) that will become channel regions. The sacrifice gate structure (226) defines the channel regions of the transistors to be formed. The sacrifice gate structure (226) includes a sacrifice gate dielectric layer (228) and a sacrifice gate electrode layer (230). The sacrifice gate structure (226) is first formed by blanket-depositing the sacrifice gate dielectric layer (228) on the pins (214). Then, a sacrificial gate electrode layer (230) is deposited on the sacrificial gate dielectric layer (228) and on the pins (214). The sacrificial gate electrode layer (230) comprises silicon such as polycrystalline silicon or amorphous silicon. In some embodiments, the sacrificial gate electrode layer (230) undergoes a planarization operation. The sacrificial gate dielectric layer (228) and the sacrificial gate electrode layer (230) may be deposited using CVD, PVD, ALD, or other suitable processes including LPCVD and PECVD. Subsequently, a mask layer (232) is formed on the sacrificial gate electrode layer (230). The mask layer (232) may include a pad silicon oxide layer (232A) and a silicon nitride mask layer (232B). Subsequently, a patterning operation is performed on the mask layer (232), and the sacrificial gate dielectric and electrode layers are patterned into a sacrificial gate structure (226). By patterning the sacrifice gate structure (226), the pins (214) are partially exposed on both sides of the sacrifice gate structure (226), thereby defining source / drain (S / D) regions.

[0024] In operation (110), method (100) (Fig. 1a) forms gate spacers (234) on the sidewalls of the sacrificial gate structure (226) as well as on the sidewalls of the pins (214), as illustrated in Figs. 8a through 8c. The gate spacers (234) may comprise dielectric materials such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, SiCN, silicon oxycarbide, SiOCN, and / or combinations thereof. In some embodiments, the gate spacers (234) comprise a plurality of layers, such as main spacer walls, liner layers, etc. For example, gate spacers (234) may be formed by blanket-depositing a dielectric material layer conformally onto a sacrificial gate structure (226) using processes such as a CVD process, a subatmospheric CVD (SACVD) process, a fluid CVD process, an ALD process, a PVD process, or other suitable processes. The gate spacers (234) may be single-layer or multi-layer. In one embodiment, the gate spacers (234) comprise a first layer and a second layer disposed on top of the first layer. The first layer may comprise silicon oxynitride, and the second layer may comprise silicon nitride. In some cases, the gate spacers (234) are measured to have a thickness of about 3 nm to about 8 nm along the X direction.

[0025] In operation (112), method (100) (Fig. 1a) recesses portions of pins (214) to form S / D trenches (or S / D recesses) (236) within S / D regions, as illustrated in Figs. 9a through 9c. Stacked epitaxial layers (206 and 208) and a hard mask (210) are etched down within the S / D regions. In many embodiments, operation (112) forms the S / D trenches (236) by a suitable etching process, such as a dry etching process, a wet etching process, or an RIE process. The etching process in operation (112) may be implemented as a dry etching process using an etchant comprising a bromine-containing gas (e.g., HBr and / or CHBr3), a fluorine-containing gas (e.g., CF4, SF6, CH2F2, CHF3, and / or C2F6), other suitable gases, or a combination thereof. The etchant is selected such that the top of the fin-shaped base (214B) is also reset and the top of the sidewalls of the STI feature (218) is exposed within the S / D trenches (236). In the illustrated embodiment, a portion of the gate spacers (234) previously deposited on the sidewalls of the fins (214) remains within the S / D regions at the end of operation (112), which is also referred to as fin spacers or source / drain spacers.

[0026] In operation (114), method (100) (Fig. 1a) forms inner spacers (240) in contact with end portions of sacrificial layers (206), as illustrated in Figs. 10a to 10c and Figs. 11a to 11c. Operation (114) can first laterally etch the end portions of the epitaxial layers (206), thereby forming cavities (238) to be filled with dielectric material as inner spacers (240), as illustrated in Figs. 10a to 10c. The sacrificial layers (206) may be selectively etched by using a wet etching agent such as, but not limited to, ammonium hydroxide (NH4OH), TMAH (tetramethylammonium hydroxide), EDP (ethylenediamine pyrocatechol), or potassium hydroxide (KOH) solution. Alternatively, operation (114) may first selectively oxidize the lateral ends of the sacrificial layers (206) exposed within the S / D trenches (236) to increase the etching selectivity between the epitaxial layers (206 and 208). In some examples, the oxidation process may be performed by exposing the device (200) to a wet oxidation process, a dry oxidation process, or a combination thereof. The cavities (238) also expose the end portions of the channel layers (208) and the top sacrificial layer (208T). Due to limited etching selectivity, the end portions of the channel layers (208) and the top sacrificial layer (208T) may suffer some etching loss. For example, the end portions of the channel layers (208) may be thinner in the Z direction than the center portions, and the end portions of the top sacrificial layer (208T) may be reset in the X direction so that the bottom surface of the hard mask (210) is exposed within the cavities (238), as illustrated in FIG. 10c. Next, operation (114) forms inner spacers (240) on the reset lateral ends of the upper epitaxial layers (206), as illustrated in FIG. 11a through FIG. 11c.For example, the operation (114) may include blanketing an inner spacer material layer within the S / D trenches (236). In particular, the inner spacer material layer is deposited on the recessed lateral ends of the upper sacrificial layers (206) exposed within the cavities (238). The inner spacer material layer may comprise silicon nitride (SiN), silicon carbonitride (SiCN), silicon oxycarbonate (SiOC), silicon oxycarbonitride (SiOCN), or other suitable dielectric materials. In some embodiments, the inner spacer material layer has the same material composition as in the hard masks (210). In some embodiments, the inner spacer material layer has a different material composition from the hard masks (210). In some embodiments, the inner spacer material layer is deposited as a conformal layer having a substantially uniform thickness on different surfaces. The inner spacer material layer may be formed by ALD or any other suitable method. By conformally forming an inner spacer material layer, the volume of the cavities is reduced or completely filled. After the inner spacer material layer is deposited, an etching operation is performed to partially remove the inner spacer material layer from the S / D trenches (236). In particular, the inner spacer material layer is removed from the sidewalls of the sacrificial layers (216). Due to the small volume of the cavities, the inner spacer material layer remains substantially within the cavities by this etching. Generally, plasma dry etching etches layers in wide and flat regions more quickly than layers in concave (e.g., holes, grooves, and / or slits) regions. Accordingly, the inner spacer material layer may remain inside the cavities (238). The remaining portions of the inner spacer material layer inside the cavities provide isolation between the metal gate structures to be formed and the S / D epitaxial features to be formed, and these are referred to as inner spacers (240).

[0027] In operation (116), method (100) (Fig. 1a) forms epitaxial features within S / D trenches (236), such as a buffer epitaxial layer (242) and a doped epitaxial layer (246) disposed on top of the buffer epitaxial layer (242), as illustrated in Figs. 12a through 12c. The buffer epitaxial layer (242) is deposited at the bottom of the S / D trenches (236). In some embodiments, the buffer epitaxial layer (242) comprises the same material as the substrate (202) and channel layer (208), such as silicon (Si), except for the dopant state (doping element and / or doping concentration). For example, the buffer epitaxial layer (242) is made of undoped silicon, the substrate (202) is made of doped silicon, and the channel layers (208) are made of undoped silicon or doped silicon. In some embodiments, the buffer epitaxial layer (242) comprises the same material as the sacrificial layers (206), such as silicon germanium (SiGe), and the germanium (Ge) content is the same or different. In some embodiments, the buffer epitaxial layer (242) is Si x Ge 1-xIt includes, where x is about 0.1 to 1. The germanium content range is not trivial. When the germanium content exceeds about 90%, the lattice mismatch between silicon and germanium can cause too many defects at the interface between the buffer epitaxial layer (242) and the substrate (202). In other embodiments, the buffer epitaxial layer (242), channel layers (208), and sacrificial layers (206) are made of different semiconductor materials. In various embodiments, the buffer epitaxial layer (242) is free of dopants, and, for example, no intentional doping is performed during the epitaxial growth process. For comparison, in one example, the substrate (202) is weakly doped (e.g., an n-type dopant in p-type regions to form PFETs or a p-type dopant in n-type regions to form NFETs), and thus has a higher doping concentration than the buffer epitaxial layer (242). The dopant-free buffer epitaxial layer (242) provides a high-resistance path from the S / D regions to the substrate (202), thereby suppressing leakage current into the substrate (202).

[0028] A doped epitaxial layer (246) is formed on a buffer epitaxial layer (242). Channel layers (208) connect two doped epitaxial layers (246) within two opposing source / drain regions. The doped epitaxial layers (246) are also referred to as S / D epitaxial features. In some embodiments, a dielectric film (not shown) may be deposited on the top surface of the buffer epitaxial layer (242) to separate the doped epitaxial layer (246) from contact with the buffer epitaxial layer (242). In other words, the bottom surface of the doped epitaxial layer (246) may be placed on the top surface of the dielectric film. The dielectric film also suppresses leakage current from the source / drain regions. Alternatively, the bottom surface of the doped epitaxial layer (246) may be placed directly on the top surface of the buffer epitaxial layer (242), as illustrated in the illustrated embodiment. In some embodiments, the doped epitaxial layer (246) comprises an epitaxially grown semiconductor material, such as epitaxially grown silicon, germanium, or silicon germanium. The doped epitaxial layer (246) may be formed by any epitaxial process comprising chemical vapor deposition (CVD) techniques (e.g., vapor epitaxy and / or ultra-high vacuum CVD), molecular beam epitaxy, other suitable epitaxial growth processes, or combinations thereof. The doped epitaxial layer (246) may be doped with an n-type dopant and / or a p-type dopant. In some embodiments, for n-type transistors, the doped epitaxial layer (246) comprises silicon and may be doped with carbon, phosphorus, arsenic, other n-type dopants, or a combination thereof (e.g., forming Si:CS / D epitaxial features, Si:PS / D epitaxial features, or Si:C:PS / D epitaxial features).In some embodiments, for p-type transistors, the doped epitaxial layer (246) comprises silicon germanium or germanium and may be doped with boron, other p-type dopants, or a combination thereof (e.g., forming Si:Ge:BS / D epitaxial features). The doped epitaxial layer (246) may comprise a plurality of epitaxial semiconductor layers having different levels of dopant density. In some embodiments, an annealing process (e.g., rapid thermal annealing (RTA) and / or laser annealing) is performed to activate the dopants within the doped epitaxial layer (246). In the illustrated embodiment, the top surface of the doped epitaxial layer (246) is below the bottom surface of the top sacrificial layer (208T). The uppermost inner spacer (240) separates the doped epitaxial layer (246) from contact with the uppermost sacrificial layer (208T). The uppermost surface of the doped epitaxial layer (246) intersects the side wall of the uppermost inner spacer (240).

[0029] In operation (118), method (100) (Fig. 1a) forms a contact etch stop layer (CESL) (248) on doped epitaxial features (246) and an interlayer dielectric (ILD) layer (250) on the CESL layer (248), as illustrated in Figs. 13a to 13c and Figs. 14a to 14c. The CESL layer (248) may comprise silicon nitride, silicon oxynitride, silicon nitride having an oxygen (O) element or a carbon (C) element, and / or other materials; and may be formed by CVD, PVD (physical vapor deposition), ALD, or other suitable methods. The ILD layer (250) may comprise TEOS (tetraethylorthosilicate) oxide, undoped silicate glass, or doped silicon oxide such as BPSG (borophosphosilicate glass), FSG (fused silica glass), PSG (phosphosilicate glass), BSG (boron-doped silicon glass), and / or other suitable dielectric materials. The ILD layer (250) may be formed by PECVD or FCVD (flow CVD) or other suitable methods. In some embodiments, forming the ILD layer (250) further comprises performing a CMP process to flatten the top surface of the device (200) so that the mask layer (232) on the tops of the sacrificial gate structures (226) is removed, as illustrated in FIGS. 14a through 14c. In the illustrated embodiment, the CESL (248) and ILD layer (250) are also placed on the side walls of the hard mask (210) and the top inner spacer (240) such that the bottom surfaces of the CESL (248) and ILD layer (250) are below the bottom surface of the top sacrificial layer (208T).

[0030] In operation (124), method (100) (Fig. 1a) removes a sacrificial gate structure (226) to form a gate trench (252) by an etching process, as illustrated in FIGS. 15a through 15c. The removal of the sacrificial gate structure (226) may include one or more etching processes optional to the material of the sacrificial gate structure (226). For example, the removal of the sacrificial gate structure (226) may be performed using optional wet etching, optional dry etching, or a combination thereof, optional to the sacrificial gate structure (226). In one embodiment, the etching process is reactive ion etching (RIE). After the removal of the sacrificial gate structure (226), the channel layers (208) and sacrificial layers (206) within the channel region, as well as the sidewalls of the hard masks (210), are exposed within the gate trench (252). In some embodiments where anisotropic dry etching is applied, the hard masks (210) protect the underlying epitaxial layers (206 and 208) from etching loss. The thickness of the hard masks (210) may be reduced by about 5% to about 20% at the end of the operation (124) due to limited etching contrast.

[0031] In operation (126), method (100) (Fig. 1a) selectively removes sacrificial layers (206) from the gate trench (252) by an etching process as illustrated in FIGS. 16a through 16c. The selective removal of the sacrificial layers (206) releases the channel layers (208) to form channel members (also numbered 208). The channel members (208) may also be referred to as nanostructures (208) or semiconductor nanostructures (208). Due to etching protection from the hard mask (210) (or dielectric structure (210)), the top channel member (208) and the other channel members (208) underneath it have substantially the same thickness. The hard mask (210) and the channel members (208) (at least the top channel member (208)) may have substantially the same width measured in the Y direction. In the illustrated embodiment, the thickness of the hard mask (210) may be greater than the thickness of the channel members (208) at the end of the operation (126). Alternatively, the thickness of the hard mask (210) may be equal to or less than the thickness of the channel members (208) at the end of the operation (126). The selective removal of the sacrificial layers (206) also leaves gaps between the channel members (208). The selective removal of the sacrificial layers (206) may be implemented by selective dry etching, selective wet etching, or other selective etching processes. An exemplary selective dry etching process may involve the use of one or more fluorine-based etchants, such as fluorine gas or hydrofluorocarbon. An exemplary selective wet etching process may involve APM etching (e.g., an ammonium hydroxide-hydrogen peroxide-water mixture). The selective removal of the sacrifice layers (206) also removes the top sacrifice layer (208T).

[0032] In operation (130), method (100) (Fig. 1a) forms a metal gate structure (254) within a gate trench (252) as illustrated in Figs. 17a through 17c. The metal gate structure (254) encloses each of the channel members (208) within the channel region, as well as the hard masks (210). Inner spacers (240) separate the metal gate structure (254) from contact with the doped epitaxial features (246).

[0033] The metal gate structure (254) includes a gate dielectric layer (256) that encloses each of the channel members (208) within the channel region, and a gate electrode layer (258) formed on the gate dielectric layer (256). The gate dielectric layer (256) also encloses the hard masks (210). In some embodiments, the gate dielectric layer (256) includes one or more dielectric material layer(s). In addition to some embodiments, the gate dielectric layer (256) includes an interface layer (256A) and a high-k dielectric layer (256B) formed on the interface layer (256A). The interface layer (256A) may be formed by an oxidation process that oxidizes the exposed semiconductor surface of the channel member (208) and the exposed semiconductor surface of the fin-shaped base (214B). That is, the exposed dielectric surfaces of the STI feature (218) and the hard mask (210) may not be directly covered by the interface layer (256A). Then, a high k dielectric layer (256B) is deposited on the interface layer (256A) using ALD, CVD, and / or other suitable methods. The exposed dielectric surfaces of the STI feature (218) and the hard masks (210) instead come into contact with the high k dielectric layer (256B). Examples of high k dielectric materials include HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, zirconium oxide, aluminum oxide, titanium oxide, hafnium dioxide-alumina (HfO2-Al2O3) alloy, other suitable high k dielectric materials, and / or combinations thereof. In one embodiment, the high k dielectric layer (256B) is formed using a highly conformal deposition process, such as ALD, to ensure the formation of a gate dielectric layer having a uniform thickness around each of the channel members.

[0034] A gate electrode layer (258) is formed on a gate dielectric layer (256) to enclose each of the channel members (208) and the hard mask (210). The gate electrode layer (258) comprises one or more conductive material layers such as polysilicon, aluminum, copper, titanium, tantalum, tungsten, cobalt, molybdenum, tantalum nitride, nickel silicide, cobalt silicide, TiN, WN, TiAl, TiAlN, TaCN, TaC, TaSiN, metal alloys, other suitable materials, and / or combinations thereof. The gate electrode layer (258) may be formed by CVD, ALD, electroplating, or other suitable methods. In specific embodiments of the present disclosure, one or more work function adjusting layers are interposed between the gate dielectric layer and the gate electrode layer. The work function adjustment layer is composed of a conductive material such as a single layer of TiN, TaN, TaAlC, TiC, TaC, Co, Al, TiAl, HfTi, TiSi, TaSi, or TiAlC, or a multilayer of two or more of these materials. For an n-channel FET, one or more of TaN, TaAlC, TiN, TiC, Co, TiAl, HfTi, TiSi, and TaSi are used as the work function adjustment layer, and for a p-channel FET, one or more of TiAlC, Al, TiAl, TaN, TaAlC, TiN, TiC, and Co are used as the work function adjustment layer. The work function adjustment layer can be formed by ALD, PVD, CVD, e-beam evaporation, or other suitable processes. Furthermore, the work function adjustment layer can be formed separately for n-type transistors and p-type transistors, which may use different metal layers.

[0035] In operation (132), method (100) (Fig. 1a) performs a planarization process, such as a CMP process, to remove excess dielectric and conductive materials and expose hard masks (210), as illustrated in Figs. 18a through 18c. Typically, it is difficult to control the amount of height reduction during the planarization process without including a planarization stop layer within the channel region. To leave sufficient process margin, the remaining metal gate height may need to be larger than is actually required, which increases parasitic capacitance and reduces circuit speed. Furthermore, a conventional planarization process applied to a large surface, such as a long metal gate structure extending across multiple pins (214) along the Y direction, can result in a curved recessed top surface. By comparison, by having hard masks (210) that function as a planarization stop layer, the metal gate height can be easily controlled to a more uniform, flat top surface. The planarization process removes the top portion of the hard masks (210) and exposes the dielectric material of the hard masks (210) and the high k dielectric layer (256B) on the reset top surface of the device (200). In the illustrated embodiment, the previously larger thickness of the hard masks (210) may now be smaller than the thickness of the channel members (208) at the end of operation (132). Alternatively, the thickness of the hard mask (210) may remain equal to or greater than the thickness of the channel members (208) at the end of operation (132), depending on some other embodiments. In some embodiments, at the end of operation (132), the hard mask (210) has a thickness in the range of about 1 nm to about 18 nm.

[0036] In operation (134), method (100) (Fig. 1a) forms a dielectric feature (260) that divides a metal gate structure (254) into two isolated segments, as illustrated in Figs. 19a through 19c. Each segment of the metal gate structure (254) functions as a metal gate for each transistor. Since the dielectric feature (260) provides isolation between the two segments of the metal gate structure (254), it is also referred to as an isolation feature (260). To form the isolation feature (260), operation (134) may first form a trench by an etching process. The etching process may use one or more etching agents or mixtures of etching agents to etch various layers within the gate electrode layer (258) and the high k dielectric layer (256B), such as dry etching using an etching agent having chlorine atoms, fluorine atoms, bromine atoms, oxygen atoms, carbon atoms, or a combination thereof. In the illustrated embodiment, to ensure isolation between the divided segments of the metal gate structure (254), the operation (134) performs some over-etching to extend the trench into the STI feature (218). This over-etching is carefully controlled so as not to expose the substrate (202). Subsequently, the operation (134) fills the trench with one or more dielectric materials to form an isolation feature (260) and performs a planarization process, such as a CMP process, to planarize the top surface of the device (200). One or more dielectric materials within the trench form the isolation feature (260). One or more dielectric materials can be deposited using CVD, PVD, ALD, or other suitable methods.

[0037] In some embodiments, the isolation feature (260) comprises a single layer of a uniform dielectric material (e.g., silicon oxide or silicon nitride). In some other embodiments, the isolation feature (260) comprises multiple dielectric layers. For example, due to the high aspect ratio of the trench, the deposition of one or more dielectric materials may include multiple deposition steps. For example, a first dielectric material is deposited into the trench and etched back to form the lower portion of the isolation feature (260). The etching back process is intended to ensure that substantially no voids are trapped within the trench. Subsequently, a second dielectric material is deposited into the trench to form the upper portion of the isolation feature (260). The first dielectric material and the second dielectric material may be the same and may be, for example, an oxide (e.g., silicon oxide) or a nitride (e.g., silicon nitride). Alternatively, the first dielectric material and the second dielectric material may be different; for example, the first dielectric material may be an oxide and the second dielectric material may be a nitride, or vice versa. Regardless of whether the first dielectric material and the second dielectric material are identical or different, the interface between the first dielectric material and the second dielectric material may be distinguishable due to two different deposition stages.

[0038] In some other embodiments, instead of a lower portion and an upper portion, the isolation feature (260) includes an outer portion and an inner portion. The outer portion of the isolation feature (260) is formed first, for example, through a conformal deposition process. Subsequently, the inner portion of the isolation feature (260) is formed and is surrounded by the outer portion. The inner portion and the outer portion of the isolation feature (260) may have different material compositions. For example, the outer portion of the isolation feature (260) may include an oxide (e.g., silicon oxide), and the inner portion of the isolation feature (260) may include a nitride (e.g., silicon nitride). The inner portion of the isolation feature (260) being a nitride makes the isolation feature (260) more resistant to subsequent etching and / or planarization processes. Alternatively, since the metallic material of the metal gate structure (254) is in contact with the outer portion of the isolation feature (260), the outer portion may not contain active chemical components such as oxygen (O). For example, the outer portion of the isolation feature (260) may contain silicon nitride and may not contain oxygen or oxide. In some embodiments, the isolation feature (260) may contain some oxide in its inner portion.

[0039] In process (136), method (100) (Fig. 1a) deposits an etch stop layer (ESL) (270) and a dielectric layer (272) on the ESL (270), as illustrated in FIGS. 20a through 20c. In some embodiments, the ESL (270) may comprise silicon nitride, silicon oxynitride, silicon nitride having an oxygen (O) element or a carbon (C) element, and / or other materials; and may be formed by CVD, PVD, ALD, or other suitable methods. The ESL (270) covers the exposed top surfaces of the hard masks (210) and the gate electrode layer (258). In some embodiments, the dielectric layer (272) is another ILD layer and may comprise TEOS oxide, undoped silicate glass, or doped silicon oxide such as BPSG, FSG, PSG, BSG, and / or other suitable dielectric materials. The gate dielectric layer (272) can be formed by PECVD, FCVD, or other suitable methods.

[0040] In operation (138), method (100) (Fig. 1a) forms gate plugs (or gate vias) (274) on divided gate segments of a metal gate structure (254). Each gate plug (274) extends through the dielectric layer (272) and the ESL (270) to reach the gate electrode layer (258). If the gate plug (274) is located directly above the hard mask (210), the gate plug (274) extends further through the hard mask (210) and the underlying high-k dielectric layer (256B) to contact the gate electrode layer (258). In the illustrated embodiments, the gate plugs (274) include a first type gate plug (274A) extending through the dielectric layer (272) and the ESL (270), and a second type gate plug (274B) extending through the dielectric layer (272), the ESL (270), as well as the hard mask (210) and the high-k dielectric layer (256B) under the hard mask (210). In some embodiments, the longer gate plug (274B) has a bottom surface that is about 2 nm to about 25 nm lower than the bottom surface of the shorter gate plug (274A). The formation of the gate plug (274) involves forming plug holes through each dielectric layer by an etching process and depositing a conductive material within the plug holes as the gate plug (274). In the embodiments, the conductive material comprises a barrier layer (e.g., TaN or TiN) and a metal filling layer (e.g., Al, Cu, or W). A layer of conductive material can be deposited using CVD, PVD, PECVD, ALD, plating, or other suitable methods.

[0041] In operation (140), method (100) (Fig. 1a) performs additional steps to complete the manufacture of the device (200). For example, method (100) can form metal interconnects that electrically connect the source, drain, and gate plugs of various transistors to form a complete IC.

[0042] Now, refer to FIG. 1b, which illustrates an alternative embodiment of method (100). In an alternative embodiment of method (100), instead of proceeding to operation (124) to remove the sacrificial gate structure (226) after the formation of the CESL (248) and ILD layer (250) in operation (118), method (100) proceeds to operation (120) to etch the sacrificial gate structure (226) to form a trench (280), as illustrated in FIG. 22a through 22c. In some embodiments, process (120) uses a lithography process comprising forming a resist layer on the device (200) (e.g., by spin coating), performing a baking process before exposure, performing an exposure process using a mask, performing a baking process after exposure, and performing a development process. After development, the developed resist layer includes a resist pattern defining an opening having a width (W1) across two adjacent pins (214). The width (W1) is greater than the gap (W2) between the two adjacent pins (214). The etching process can be extended into the area between the two adjacent pins (214) without causing (or minimizing) etching loss to the epitaxial stack (204) and STI feature (218) by using one or more etching agents or mixtures of etching agents to etch various layers in the sacrificial gate electrode layer (230) and the sacrificial gate dielectric layer (228) through the opening defined within the developed resist layer. Since the selective etching process is self-aligned as being confined within the area between the two adjacent pins (214), the operation (120) is not sensitive to the precise location of the opening having the relatively larger width (W1). The resulting trench (280) has a relatively larger width (W1) at its uppermost part and a relatively smaller width (W2) at its lower part. The trench (280) exposes the uppermost surface of the STI feature (218) but does not extend into the STI feature (218).Due to limited etching contrast, the hard masks (210) may suffer some etching loss, so the corner portions of the hard masks (210) may be reset, as shown in the illustrated embodiment.

[0043] In operation (122), the method (100) (Fig. 1b) fills the trench (280) with one or more dielectric materials to form an isolation feature (282), as illustrated in FIGS. 23a through 23c. The one or more dielectric materials of the isolation feature (282) and their deposition may be substantially similar to the isolation feature (260) discussed above, for example, through a multi-stage deposition process in forming the lower and upper portions of the isolation feature (282) or the outer and inner portions of the isolation feature (282). In the illustrated embodiment as illustrated in FIG. 23b, the one or more dielectric materials of the isolation feature (282) include a dielectric liner (284) deposited on the sidewalls and bottom surface of the trench (280) and a dielectric inner layer (286) filling the remaining opening of the trench (280). The dielectric liner (284) may comprise some oxide, SiN, SiCN, SiOC, SiOCN, or other suitable dielectric material. The dielectric inner layer (286) may comprise SiN, SiCN, SiOC, SiOCN, or other suitable dielectric material. In one embodiment, the dielectric liner (284) may comprise silicon nitride and is free of oxygen or oxide to avoid oxidation of the metal layers within the metal gate structure to be formed.

[0044] In operation (124), method (100) (Fig. 1b) removes a sacrificial gate structure (226) to form a gate trench (252) by an etching process, as illustrated in FIGS. 24a through 24c. The removal of the sacrificial gate structure (226) may include one or more etching processes optional to the material of the sacrificial gate structure (226). For example, the removal of the sacrificial gate structure (226) may be performed using optional wet etching, optional dry etching, or a combination thereof, optional to the sacrificial gate structure (226). In one embodiment, the etching process is reactive ion etching (RIE). After the removal of the sacrificial gate structure (226), the channel layers (208) and sacrificial layers (206), as well as the channel region sidewalls of the hard masks (210), are exposed within the gate trench (252). The exposed portion of the dielectric liner (284) can also be removed so that the top portion of the dielectric inner layer (286) on the hard mask (210) is exposed. In some embodiments where anisotropic dry etching is applied, the hard masks (210) protect the underlying epitaxial layers (206 and 208) from etching loss. The thickness of the hard masks (210) can be reduced by about 5% to about 20% at the end of the operation (124) due to limited etching contrast.

[0045] In operation (126), method (100) (Fig. 1b) selectively removes sacrificial layers (206) from the gate trench (252) by an etching process as illustrated in FIGS. 25a through 25c. The selective removal of the sacrificial layers (206) releases the channel members (208). The selective removal of the sacrificial layers (206) also leaves gaps between the channel members (208). Additionally, the dielectric liner (284) of the isolation feature (282) is exposed within the gaps. The selective removal of the sacrificial layers (206) may be implemented by selective dry etching, selective wet etching, or other selective etching processes. The selective removal of the sacrificial layers (206) also removes the top sacrificial layer (208T).

[0046] In operation (128), method (100) (Fig. 1b) trims the exposed dielectric liner (284) of the CMG feature (282) to expand the gaps between adjacent channel members (208), as illustrated in FIGS. 26a through 26c. Trimming of the dielectric liner (284) may be implemented by optional dry etching, optional wet etching, or other optional etching processes. An exemplary optional dry etching process may involve the use of one or more fluorine-based etchants, such as fluorine gas or hydrofluorocarbon. An exemplary optional wet etching process may involve APM etching (e.g., an ammonium hydroxide-hydrogen peroxide-water mixture). Trimming of the dielectric liner (284) exposes the sidewalls of the dielectric inner layer (286) within the gaps between adjacent channel members (208). The exposed sidewalls of the dielectric inner layer (286) may have a vertical length of about 0 nm to about 5 nm between adjacent remaining segments of the dielectric liner (284). A first portion of the dielectric liner (284) is laterally stacked between the channel members (208) and the dielectric inner layer (286) because it may be difficult for the etching agent to reach this portion of the dielectric liner (284). Similarly, a second portion of the dielectric liner (284) is vertically stacked between the STI feature (218) and the dielectric inner layer (286), and a third portion of the dielectric liner (284) is laterally stacked between the hard mask (210) and the dielectric inner layer (286).

[0047] In operation (130), method (100) (Fig. 1b) forms a metal gate structure (254) within a gate trench (252) as illustrated in FIGS. 27a through 27c. The metal gate structure (254) encloses each of the channel members (208) within the channel region, as well as the hard masks (210). Inner spacers (240) separate the metal gate structure (254) from contact with the doped epitaxial features (246). An interface layer (256A) and a high k dielectric layer (256B) fill the space between the channel member (208) and the dielectric inner layer (286), which is prepared from the trimming process in operation (128). An isolation feature (282) divides the metal gate structure (254) into two isolated segments. Unlike the isolation feature (260) (Figs. 21a and 21b), the isolation feature (282) as shown in Fig. 27b is not partially embedded within the STI feature (218).

[0048] In operation (132), method (100) (Fig. 1b) performs a planarization process, such as a CMP process, to remove excess dielectric material and conductive material and expose the hard masks (210), as also illustrated in Figs. 27a through 27c. By having hard masks (210) that function as a planarization stop layer, the metal gate height can be easily controlled to a more uniform, flat top surface. The planarization process removes the top of the hard masks (210) and exposes the dielectric material of the hard masks (210), as well as the high k dielectric layer (256B) and the isolation feature (282). In the illustrated embodiment, the top of the isolation feature (282) having a larger width (W1) is completely removed by the planarization process, and the lower part of the isolation feature (282) having a smaller width (W2) remains.

[0049] After operation (132), an alternative embodiment of the method (100) proceeds to operation (136) (Fig. 1a) in which an etching stop layer (ESL) (270) and a dielectric layer (272) are deposited, as illustrated in FIG. 28a through 28c, and subsequently to operation (138) (Fig. 1a) in which gate plugs (274) are formed. Additionally, in operation (140), the method (100) (Fig. 1a) performs additional steps to complete the fabrication of the device (200). For example, the method (100) can form metal interconnects that electrically connect the source, drain, and gate plugs of various transistors to form a complete IC.

[0050] FIGS. 29a through 29c illustrate an alternative embodiment of the device (200) at the end of operation (138) in which the dielectric liner (284) is not trimmed (e.g., operation (128) is skipped). Accordingly, the dielectric liner (284) separates the dielectric inner layer (286) from contacting the high k dielectric layer (256B). Additionally, the interface layer (256A) and the high k dielectric layer (256B) are not positioned laterally between the channel members and the isolation feature (282).

[0051] FIGS. 30a through 30c illustrate other alternative embodiments of the device (200) at the end of the remaining operation (138) by controlling the amount of metal gate height reduction in the planarization process in operation (132) by the upper part of the isolation feature (282). Accordingly, the isolation feature (282) has an upper part having a greater width (W1) and a lower part having a smaller width (W2).

[0052] FIGS. 31a through 31c illustrate other alternative embodiments of the device (200) at the end of operation (138) in which the dielectric liner (284) is not trimmed (e.g., operation (128) is skipped) and the top portion of the isolation feature (282) remains. Accordingly, the dielectric liner (284) separates the dielectric inner layer (286) from contacting the high k dielectric layer (256B). Additionally, the interface layer (256A) and the high k dielectric layer (256B) are not positioned laterally between the channel members and the isolation feature (282). Furthermore, the isolation feature (282) has a top portion having a larger width (W1) and a bottom portion having a smaller width (W2).

[0053] FIGS. 32a through 32c illustrate another alternative embodiment of the device (200) in which the isolation feature (282) does not extend the entire lateral distance between the channel members (208). That is, the isolation feature (282) is separated from the channel members (208), and between them there is a high k dielectric layer (256B) and a gate electrode layer (258). The resulting structure is similar to the embodiment illustrated in FIGS. 21a through 21c. One of the differences is that the high k dielectric layer (256B) is deposited on the sidewalls of the isolation feature (282) due to the formation of the metal gate structure (254) after the formation of the isolation feature (282). In the illustrated embodiment, the isolation feature (282) is also partially embedded within the STI feature (218).

[0054] FIGS. 33a through 33c illustrate other alternative embodiments of a device (200) in which a portion of a high k dielectric layer (256B) is interposed between the top inner spacer (240) and the bottom surface of the hard mask (210) (Fig. 33c). This may be due to the high etching selectivity in process (114), which causes the top sacrificial layer (208T) to not be reset in the X direction (compared to FIG. 10c) and subsequently the metal gate structure (254) to occupy the space reserved by the top sacrificial layer (208T). In these embodiments, the high k dielectric layer (256B) may come into contact with the CESL (248), as illustrated in FIG. 33c. The high k dielectric layer (256B) contacting the CESL (248) and separating the uppermost inner spacer (240) from the bottom surface of the hard mask (210) may also occur in other embodiments as illustrated in FIGS. 21a to 21c and FIGS. 28a to 32c.

[0055] While not intended to be limiting, embodiments of the present disclosure provide one or more of the following advantages. For example, embodiments of the present disclosure form a dielectric structure floating on channel members vertically stacked within the channel region of a multi-gate transistor. This advantageously improves the uniformity of the channel member thickness and the metal gate height. Furthermore, embodiments of the present disclosure can be easily integrated into existing semiconductor manufacturing processes.

[0056] In one exemplary embodiment, the present disclosure relates to a method. The present method comprises the steps of: forming a stack on a substrate — the stack comprises a plurality of channel layers interleaved by a plurality of sacrificial layers —; depositing a dielectric structure on the stack; patterning the dielectric structure and the stack to form a fin-shaped structure — the fin-shaped structure comprises a channel region and a source / drain region —; forming a dummy gate stack on the channel region of the fin-shaped structure; depositing gate spacers on the sidewalls of the dummy gate stack; resetting the fin-shaped structure within the source / drain region to form a source / drain trench that exposes the sidewalls of the channel layers and the sacrificial layers; partially resetting the sacrificial layers to form a plurality of inner spacer cavities; forming a plurality of inner spacers within the inner spacer cavities; forming an epitaxial feature within the source / drain trench — the epitaxial feature is in contact with the channel layers —; and, after the step of forming the epitaxial feature, forming a gate trench The method comprises the steps of removing a dummy gate stack, releasing channel layers within a channel region into a plurality of channel members by removing sacrificial layers—wherein a dielectric structure floats over the channel layers within the channel region—and forming a metal gate structure within a gate trench—wherein the metal gate structure surrounds each of the channel members and the dielectric structure. In some embodiments, the method further comprises the step of resetting the metal gate structure to expose the dielectric structure. In some embodiments, the method further comprises the step of forming a gate plug that extends through the dielectric structure and contacts the metal gate structure. In some embodiments, after the step of releasing the channel layers, the dielectric structure and the uppermost channel member among the channel members have the same width. In some embodiments, the metal gate structure contacts the dielectric structure.In some embodiments, the method further comprises the steps of: depositing a hard mask layer on a dielectric structure; patterning the hard mask layer—the pin-shaped structure comprises the hard mask layer—depositing isolation features on a stack, the dielectric structure, and the sidewalls of the hard mask layer; optionally removing the hard mask layer to expose the dielectric structure; and resetting the isolation features. In some embodiments, the method further comprises the step of forming isolation features. The isolation features separate the metal gate structure into two isolated segments. In some embodiments, the isolation features include a bottom portion and a top portion, with a distinguishable interface between them. In some embodiments, the isolation features include an outer layer of a first dielectric material and an inner layer of a second dielectric material different from the first dielectric material.

[0057] In another exemplary embodiment, the present disclosure relates to a method. The method comprises the steps of forming a plurality of semiconductor nanostructures stacked vertically on a substrate; forming a dielectric structure floating on the top semiconductor nanostructure among the semiconductor nanostructures; forming a plurality of inner spacers interleaved with the semiconductor nanostructures; forming an epitaxial feature in contact with the semiconductor nanostructures; and forming a gate structure that encloses each of the semiconductor nanostructures and the dielectric structure. In some embodiments, the method further comprises the steps of flattening the gate structure to expose the dielectric structure, depositing an interlayer dielectric layer on the dielectric structure, and forming a gate plug extending through the interlayer dielectric layer and the dielectric structure. In some embodiments, the gate structure comprises an interface layer, a high k dielectric layer, and a gate electrode layer. The interface layer contacts the semiconductor nanostructures. The high k dielectric layer contacts the dielectric structure. In some embodiments, the method further comprises the step of depositing a dielectric layer on the top surface of the epitaxial feature. The gate structure contacts the dielectric layer. In some embodiments, the present method further comprises the step of forming an isolation feature that separates a gate structure into two isolated segments. The isolation feature is a two-layer structure comprising a first dielectric layer and a second dielectric layer. The first dielectric layer and the second dielectric layer have different material compositions.

[0058] In another exemplary embodiment, the present disclosure relates to a semiconductor device. The semiconductor device comprises a plurality of semiconductor nanostructures disposed on a substrate, a dielectric structure on the top semiconductor nanostructure among the semiconductor nanostructures, a plurality of inner spacers interleaving with the semiconductor nanostructures, a metal gate structure surrounding each of the semiconductor nanostructures—wherein the bottom surface of the dielectric structure is below the top surface of the metal gate structure—gate spacers disposed on the sidewalls of the metal gate structure, and an epitaxial feature in contact with the semiconductor nanostructures. In some embodiments, the top surface of the metal gate structure and the top surface of the dielectric structure are coplanar. In some embodiments, the semiconductor device further comprises a gate plug extending through the dielectric structure and in contact with the metal gate structure. In some embodiments, the metal gate structure is in contact with the sidewalls and the bottom surface of the dielectric structure. In some embodiments, the semiconductor nanostructures are first semiconductor nanostructures and the metal gate structure is a first metal gate structure, and the semiconductor device further comprises a plurality of second semiconductor nanostructures, a second metal gate structure surrounding each of the second semiconductor nanostructures, and an isolation feature separating the first metal gate structure from the second metal gate structure. In some embodiments, the isolation feature comprises a first dielectric layer and a second dielectric layer. A portion of the first dielectric layer is positioned beneath the second dielectric layer. The first dielectric layer and the second dielectric layer have different material compositions.

[0059] Foregoing, features of various embodiments have been outlined to enable those skilled in the art to better understand the following detailed description. Those skilled in the art should understand that the present disclosure can be readily used as a basis for designing or modifying other processes and structures to perform the same purpose and / or achieve the same advantages as the embodiments introduced herein. Furthermore, those skilled in the art should also recognize that such equivalent configurations do not depart from the spirit and scope of the present disclosure, and that various changes, substitutions, and modifications can be made without departing from the spirit and scope of the present disclosure.

[0060] Examples

[0061] Example 1. As a method,

[0062] A step of forming a stack on a substrate — the stack comprises a plurality of channel layers interleaved by a plurality of sacrificial layers —;

[0063] Step of depositing genomic structures on a stack;

[0064] A step of patterning a dielectric structure and a stack to form a fin-shaped structure — the fin-shaped structure includes a channel region and a source / drain region —;

[0065] A step of forming a dummy gate stack on the channel region of a pin-shaped structure;

[0066] Step of depositing gate spacers on the sidewalls of a dummy gate stack;

[0067] A step of resetting a fin-shaped structure within a source / drain region to form a source / drain trench that exposes the sidewalls of the channel layers and the sacrificial layers;

[0068] A step of partially resetting the sacrificial layers to form a plurality of inner spacer cavities;

[0069] A step of forming a plurality of inner spacers within inner spacer cavities;

[0070] A step of forming epitaxial features within source / drain trenches — the epitaxial features are in contact with channel layers —;

[0071] After the step of forming epitaxial features, the step of removing a dummy gate stack to form a gate trench;

[0072] A step of releasing channel layers within a channel region as multiple channel members by removing sacrificial layers — a dielectric structure is suspended over the channel layers within the channel region —; and

[0073] A method comprising the step of forming a metal gate structure within a gate trench — the metal gate structure surrounds each of the channel members and the dielectric structure —.

[0074] Example 2. In Example 1,

[0075] A method comprising the step of resetting a metal gate structure to expose a dielectric structure.

[0076] Example 3. In Example 2,

[0077] A method comprising the step of forming a gate plug that extends through a dielectric structure and contacts a metal gate structure.

[0078] Example 4. The method of Example 1, wherein, after the step of releasing the channel layers, the uppermost channel member among the dielectric structure and the channel members has the same width.

[0079] Example 5. Method of Example 1, wherein the metal gate structure is in contact with the dielectric structure.

[0080] Example 6. In Example 1,

[0081] Step of depositing a hard mask layer on a genome structure;

[0082] Step of patterning a hard mask layer — the pin-shaped structure includes a hard mask layer —;

[0083] A step of depositing isolation features on the sidewalls of the stack, the genome structure, and the hard mask layer;

[0084] A step of selectively removing a hard mask layer to expose a genomic structure; and

[0085] A method comprising an additional step of resetting isolated features.

[0086] Example 7. In Example 1,

[0087] A method further comprising the step of forming an isolation feature — the isolation feature separates the metal gate structure into two isolated segments —.

[0088] Example 8. The method of Example 7, wherein the isolation feature includes a bottom portion and a top portion, and there is a distinguishable interface between them.

[0089] Example 9. The method of Example 8, wherein the isolation feature comprises an outer layer of a first dielectric material and an inner layer of a second dielectric material different from the first dielectric material.

[0090] Example 10. As a method,

[0091] A step of forming a plurality of semiconductor nanostructures that are vertically stacked on a substrate;

[0092] A step of forming a dielectric structure floating on the top semiconductor nanostructure among the semiconductor nanostructures;

[0093] A step of forming a plurality of inner spacers interleaved with semiconductor nanostructures;

[0094] A step of forming an epitaxial feature in contact with semiconductor nanostructures; and

[0095] A method comprising the step of forming a gate structure that encloses each of the semiconductor nanostructures and the dielectric structure.

[0096] Example 11. In Example 10,

[0097] A step of flattening the gate structure to expose the dielectric structure;

[0098] Step of depositing an interlayer dielectric layer on a dielectric structure; and

[0099] A method further comprising the step of forming a gate plug that extends through an interlayer dielectric layer and a dielectric structure.

[0100] Example 12. The method of Example 10, wherein the gate structure comprises an interface layer, a high k dielectric layer, and a gate electrode layer, wherein the interface layer is in contact with semiconductor nanostructures and the high k dielectric layer is in contact with the dielectric structure.

[0101] Example 13. In Example 10,

[0102] A method further comprising the step of depositing a dielectric layer on the uppermost surface of an epitaxial feature — wherein the dielectric layer and the gate structure are in contact —.

[0103] Example 14. In Example 10,

[0104] A method further comprising the step of forming an isolation feature that separates a gate structure into two isolated segments — the isolation feature is a two-layer structure comprising a first dielectric layer and a second dielectric layer, wherein the first dielectric layer and the second dielectric layer comprise different material compositions —

[0105] Example 15. As a semiconductor device,

[0106] Multiple semiconductor nanostructures disposed on a substrate;

[0107] Dielectric structure on top of the top semiconductor nanostructure among the semiconductor nanostructures;

[0108] Multiple inner spacers interleaving with semiconductor nanostructures;

[0109] A metal gate structure surrounding each of the semiconductor nanostructures — the bottom plane of the dielectric structure is located beneath the top plane of the metal gate structure —;

[0110] Gate spacers disposed on the side walls of a metal gate structure; and

[0111] A semiconductor device comprising epitaxial features in contact with semiconductor nanostructures.

[0112] Example 16. A semiconductor device according to Example 15, wherein the top surface of the metal gate structure and the top surface of the dielectric structure are on the same plane.

[0113] Example 17. In Example 15,

[0114] A semiconductor device comprising a gate plug that extends through a dielectric structure and contacts a metal gate structure.

[0115] Example 18. A semiconductor device according to Example 15, wherein the metal gate structure is in contact with the sidewalls and bottom surface of the dielectric structure.

[0116] Example 19. In Example 15, the semiconductor nanostructures are the first semiconductor nanostructures and the metal gate structure is the first metal gate structure, and the semiconductor device is:

[0117] Multiple second semiconductor nanostructures;

[0118] A second metal gate structure surrounding each of the second semiconductor nanostructures; and

[0119] A semiconductor device further comprising an isolation feature that separates a first metal gate structure from a second metal gate structure.

[0120] Example 20. A semiconductor device according to Example 19, wherein the isolation feature comprises a first dielectric layer and a second dielectric layer, a portion of the first dielectric layer is below the second dielectric layer, and the first dielectric layer and the second dielectric layer comprise different material compositions.

Claims

Claim 1 As a method, the steps include: forming a stack on a substrate — said stack comprises a plurality of channel layers interleaved by a plurality of sacrificial layers —; depositing a dielectric structure on said stack; patterning said dielectric structure and said stack to form a fin-shaped structure — said fin-shaped structure comprises a channel region and a source / drain region —; forming a dummy gate stack on said channel region of said fin-shaped structure; depositing gate spacers on the sidewalls of said dummy gate stack; resetting said fin-shaped structure within said source / drain region to form a source / drain trench exposing the sidewalls of said channel layers and said sacrificial layers; partially resetting said sacrificial layers to form a plurality of inner spacer cavities; forming a plurality of inner spacers within said inner spacer cavities; and forming an epitaxial feature within said source / drain trench — said epitaxial feature in contact with said channel layers. —; after the step of forming the epitaxial feature, the step of removing the dummy gate stack to form a gate trench; the step of releasing the channel layers within the channel region as a plurality of channel members by removing the sacrificial layers — the dielectric structure is suspended over the channel layers within the channel region —; and the step of forming a metal gate structure within the gate trench — the metal gate structure surrounds each of the channel members and the dielectric structure — comprising a method. Claim 2 A method according to claim 1, further comprising the step of resetting the metal gate structure to expose the dielectric structure. Claim 3 A method according to claim 1, wherein, after the step of releasing the channel layers, the dielectric structure and the uppermost channel member among the channel members have the same width. Claim 4 A method comprising: forming a plurality of semiconductor nanostructures vertically stacked on a substrate; forming a dielectric structure floating on the uppermost semiconductor nanostructure among the semiconductor nanostructures; forming a plurality of inner spacers interleaved with the semiconductor nanostructures; forming an epitaxial feature in contact with the semiconductor nanostructures; and forming a gate structure surrounding each of the semiconductor nanostructures and the dielectric structure. Claim 5 A method according to claim 4, further comprising the steps of: flattening the gate structure to expose the dielectric structure; depositing an interlayer dielectric layer on the dielectric structure; and forming a gate plug extending through the interlayer dielectric layer and the dielectric structure. Claim 6 A semiconductor device comprising: a plurality of semiconductor nanostructures disposed on a substrate; a dielectric structure situated on the uppermost semiconductor nanostructure among the semiconductor nanostructures; a plurality of inner spacers interleaved with the semiconductor nanostructures; a metal gate structure surrounding each of the semiconductor nanostructures ― the bottom surface of the dielectric structure is below the uppermost surface of the metal gate structure ―; gate spacers disposed on the sidewalls of the metal gate structure; an epitaxial feature in contact with the semiconductor nanostructures; and a gate plug extending through the dielectric structure and in contact with the metal gate structure. Claim 7 A semiconductor device according to claim 6, wherein the uppermost surface of the metal gate structure and the uppermost surface of the dielectric structure are on the same plane. Claim 8 A semiconductor device according to claim 6, wherein the metal gate structure is in contact with the sidewalls and bottom surface of the dielectric structure. Claim 9 In claim 6, the semiconductor nanostructures are first semiconductor nanostructures and the metal gate structure is a first metal gate structure, and the semiconductor device further comprises: a plurality of second semiconductor nanostructures; a second metal gate structure surrounding each of the second semiconductor nanostructures; and an isolation feature separating the first metal gate structure from the second metal gate structure. Claim 10 A semiconductor device according to claim 9, wherein the isolation feature comprises a first dielectric layer and a second dielectric layer, a portion of the first dielectric layer is below the second dielectric layer, and the first dielectric layer and the second dielectric layer have different material compositions.

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