Semiconductor Memory Apparatus and Operation Method Thereof, Memory System Having the Same

Abstract

A semiconductor memory device according to one embodiment may include a memory cell array, an ECC (Error Check and Correction) circuit that detects and corrects an error from data read from a memory cell in response to a read command and outputs an error correction signal whenever an error is corrected, and a flag generation circuit configured to enable a flag output mode and output an error correction signal as an error flag in the flag output mode when the number of times an error correction signal is generated during a monitoring period reaches a threshold.

Description

Technology Field

[0001] The present invention relates to a semiconductor integrated circuit, and more specifically, to a semiconductor memory device and a method of operating the same, and a memory system including the same. Background Technology

[0002] Data stored in semiconductor memory devices can have their logical levels inverted due to various causes, such as electrical or magnetic interference.

[0003] Error Check and Correction (ECC) functions were developed to detect and correct such data corruption.

[0004] The ECC circuit is configured to detect whether an error has occurred and where it is located when reading data from a memory device, and to return the data at the error location to the correct value to output the corrected read data.

[0005] Damage or loss of data stored in a memory device reduces the reliability of the memory device. Therefore, measures are required to prevent the occurrence of critical errors by efficiently managing error information. The problem to be solved

[0006] Embodiments of the present technology can provide a semiconductor memory device with improved reliability, a method of operation thereof, and a memory system including the same. means of solving the problem

[0007] A semiconductor memory device according to one embodiment of the present technology may include: a memory cell array; an ECC (Error Check and Correction) circuit that detects and corrects an error from data read from the memory cell in response to a read command and outputs an error correction signal whenever an error is corrected; and a flag generation circuit configured to enable a flag output mode and output the error correction signal as an error flag in the flag output mode when the number of times the error correction signal is generated reaches a threshold during a monitoring period.

[0008] A semiconductor memory device according to one embodiment of the present technology may include: a memory cell array; an ECC (Error Check and Correction) circuit that detects and corrects an error from data read from the memory cell in response to a read command and outputs an error correction signal whenever an error is corrected; and a flag generation circuit configured to output the error correction signal as an error flag for at least the duration of the monitoring period after the number of times the error correction signal is generated reaches a threshold during the monitoring period.

[0009] A method of operation of a semiconductor memory device according to an embodiment of the present technology may include: a step of detecting an error from data read from a memory cell in response to a read command; a step of outputting an error correction signal whenever the error is corrected; a step of enabling a flag output mode when the number of occurrences of the error correction signal during a monitoring period reaches a threshold; and a step of outputting the error correction signal as an error flag in the flag output mode.

[0010] A memory system according to an embodiment of the present technology includes a semiconductor memory device; and a memory controller that controls the semiconductor memory device, wherein the semiconductor memory device may include: a memory cell array; an ECC (Error Check and Correction) circuit that detects and corrects an error from data read from the memory cell in response to a read command and outputs an error correction signal whenever an error is corrected; and a flag generation circuit configured to enable a flag output mode when the number of times the error correction signal is generated reaches a threshold during a monitoring period, and to generate the error correction signal as an error flag in the flag output mode and output it to the memory controller. Effects of the invention

[0011] According to the present technology, it is possible to prevent the occurrence of fatal errors by monitoring error occurrence situations within a memory device. Brief explanation of the drawing

[0012] FIG. 1 is a configuration diagram of a memory system according to one embodiment. FIG. 2 is a configuration diagram of a semiconductor memory device according to one embodiment. FIG. 3 is a diagram of an ECC circuit according to one embodiment. FIG. 4 is a configuration diagram of an error flag generation circuit according to one embodiment. FIG. 5 is a configuration diagram of an error flag generation circuit according to one embodiment. FIG. 6 is a timing diagram for explaining the operation concept of an error flag generation circuit according to one embodiment. FIGS. 7 to 9 are configuration diagrams of a stacked semiconductor device according to embodiments. FIG. 10 is a configuration diagram of a processing system according to one embodiment. Specific details for implementing the invention

[0013] Hereinafter, embodiments of the present technology will be described in more detail with reference to the attached drawings.

[0014] FIG. 1 is a configuration diagram of a memory system according to one embodiment.

[0015] Referring to FIG. 1, the memory system (10) may include a memory controller (100) and at least one semiconductor memory device (200).

[0016] The memory controller (100) controls the overall operation of the memory system (10) and may be configured to control data exchange between an unillustrated host device and a semiconductor memory device (200). For example, the memory controller (100) may control the memory device (200) to write data or read data stored in the memory device (200) in response to a request from the host device.

[0017] The semiconductor memory device (200) may include a memory device selected from DRAM (dynamic random access), DDR4 (double data rate 4) SDRAM (synchronous DRAM), LPDDR4 (low power DDR4) SDRAM, LPDDR5 SDRAM, DDR5 SDRAM, GDDR (graphic DDR), or SRAM.

[0018] The memory controller (100) transmits a clock signal (CK), a command (CMD), and an address (ADDR) to the semiconductor memory device (200), and can exchange data (DQ) with the semiconductor memory device (200). The semiconductor memory device (200) can generate an error flag (EF) based on an error detection and correction operation performed during a data read operation and transmit it to the memory controller (100).

[0019] That is, the error flag (EF) may include information related to the detection and / or correction of at least one error bit that occurs in the data read from the memory cell array (300). In one embodiment, the error flag (EF) may include information regarding whether an error bit is detected and whether to correct the error bit if one or more error bits are detected.

[0020] The semiconductor memory device (200) may include a control logic circuit (210), a memory cell array (MCA, 300) in which data (DQ) is stored, an ECC circuit (400), and an EF generation circuit (500).

[0021] The control logic circuit (210) can control the operation of the semiconductor memory device (200). For example, the control logic circuit (210) can generate control signals to cause the semiconductor memory device (200) to perform a write operation or a read operation.

[0022] The ECC circuit (400) can perform ECC decoding by reading data from a target page of a memory cell array (300) under the control of the control logic circuit (210). If the ECC circuit (400) corrects an error included in the decoded data, it can transmit an error correction signal (CE) to an error flag generation circuit (500).

[0023] The error flag generation circuit (500) can generate an error flag (EF) based on a read command (RD) transmitted from the control logic circuit (210) and an error correction signal (CE) provided from the ECC circuit (400).

[0024] In one embodiment, the error flag generation circuit (500) can output an error flag (EF) by activating an error flag (EF) output mode when the number of correctable error bits that occurred during a set monitoring period reaches a threshold. The error flag (EF) output mode may be enabled at least during the monitoring period when the number of correctable error bits reaches a threshold. In another embodiment, the error flag (EF) output mode may be enabled during the monitoring period when the number of correctable error bits reaches a threshold and during the tracking monitoring period. The tracking monitoring period may be a subsequent monitoring period.

[0025] In one embodiment, the monitoring interval may be determined based on the number of read operations. The monitoring interval, threshold, and tracking monitoring interval can be set, changed, or programmed through fuse options, mode register set (MRS), etc.

[0026] FIG. 2 is a configuration diagram of a semiconductor memory device according to one embodiment.

[0027] Referring to FIG. 2, a semiconductor memory device (200) according to one embodiment may include a control logic circuit (210), an address register (220), a bank control logic (230), a refresh counter (245), a row address multiplexer (240), a column address latch (250), a row decoder (260), a column decoder (270), a memory cell array (300), a sense amplifier section (280), an input / output (IO) circuit (290), an ECC circuit (400), a data input / output buffer (295), and an EF generation circuit (500).

[0028] The memory cell array (300) may include a plurality of banks. Each of the row decoder (260), column decoder (270), and sense amplifier section (280) may be configured to correspond to each of the plurality of banks.

[0029] The memory cell array (300) may include a plurality of word lines (WL), a plurality of bit lines (BL), and a plurality of memory cells (MC) that are respectively connected between the word lines (WL) and the bit lines (BL).

[0030] The address register (220) can receive an address (ADDR) including a bank address (BANK_ADDR), a row address (ROW_ADDR), and a column address (COL_ADDR) from the memory controller (100) and provide the bank address (BANK_ADDR) to the bank control logic (230), the row address (ROW_ADDR) to the row address multiplexer (240), and the column address (COL_ADDR) to the column address latch (250), respectively.

[0031] The bank control logic (230) can generate bank control signals in response to the bank address (BANK_ADDR). In response to the bank control signals, the row decoder (260) and column decoder (270) corresponding to the access target bank can be activated.

[0032] The row address multiplexer (240) can receive a row address (ROW_ADDR) from the address register (220) and a refresh row address (REF_ADDR) from the refresh counter (245). The row address multiplexer (240) can optionally output the row address (ROW_ADDR) or the refresh row address (REF_ADDR) as a row address (RA). The row address (RA) output from the row address multiplexer (240) can be applied to the row decoder (260).

[0033] The row decoder (260) can decode the row address (RA) output from the row address multiplexer (240) and activate the word line corresponding to the row address.

[0034] The column address latch (250) can receive and temporarily store a column address (COL_ADDR) from the address register (220). The column address (CA) output from the column address latch (250) can be applied to the column decoder (270).

[0035] The column decoder (270) can activate the sense amplifier section (280) corresponding to the bank address (BANK_ADDR) and the column address (CA).

[0036] The input / output circuit (290) may include read data latches for storing data output from the memory cell array (300) and write drivers for writing data to the memory cell array (300).

[0037] Data read from the memory cell array (300) can be detected by the sense amplifier unit (280) and stored in the read data latch of the input / output circuit (290). The ECC circuit (400) can ECC decode the data stored in the read data latch and transmit an error correction signal (CE) to the error flag generation circuit (500).

[0038] The error flag generation circuit (500) can generate an error flag (EF) in response to a read command (RD) and an error correction signal (CE) and apply it to a data input / output buffer (295).

[0039] When writing, the data input / output buffer (295) can receive data (DQ) in synchronization with the clock signal (CK) provided by the memory controller (100) and provide it to the ECC circuit (400).

[0040] The ECC circuit (400) performs an encoding operation to generate parity bits based on data (DQ) and provides the write data and parity bits to the input / output circuit (290) so that they are written to the memory cell array (300).

[0041] During a read operation, the ECC circuit (400) performs ECC decoding based on data read from the target area of ​​the memory cell array (300) and a parity bit. If the decoded data contains at least one error bit and the ECC circuit (400) corrects it, the ECC circuit (400) can generate an error correction signal (CE) and provide it to the error flag generation circuit (500).

[0042] The data input / output buffer (295) can receive read data (DQ) and an error flag (EF) and transmit them to the memory controller (100).

[0043] The control logic circuit (210) can control the operation of the semiconductor memory device (200). For example, the control logic circuit (210) can generate control signals to cause the semiconductor memory device (200) to perform a write operation or a read operation. The control logic circuit (210) may include a command decoder (211) that decodes a command (CMD) received from the memory controller (100) and a mode register (212) for setting the operation mode of the semiconductor memory device (200).

[0044] For example, the command decoder (211) can decode the write enable signal, row address strobe signal, column address strobe signal, chip select signal, etc., to generate control signals corresponding to the command (CMD).

[0045] The control signals may include a first control signal (CTL1) that controls the input / output circuit (290) and a second control signal (CTL2) that controls the ECC circuit (400).

[0046] FIG. 3 is a diagram of an ECC circuit according to one embodiment.

[0047] Referring to FIG. 3, the ECC circuit (400) may include an ECC encoder (410) and an ECC decoder (430).

[0048] FIG. 3 illustrates a memory cell array (300) including a normal cell array (NCA) and a redundancy cell array (RCA).

[0049] The ECC encoder (410) can generate parity bits (PRT) associated with write data (WDQ) to be stored in the normal cell array (NCA). The parity bits (PRT) can be stored in the redundancy cell array (RCA).

[0050] The ECC decoder (430) can perform ECC decoding on the read data (RDQ) using the read data (RDQ) and parity bits (PRT) read from the memory cell array (300). As a result of performing ECC decoding, if the read data (RDQ) contains at least one error bit and is corrected, the ECC decoder (430) can output an error correction signal (CE). The ECC decoder (430) can also correct the error bit and output corrected data (C_DQ).

[0051] FIG. 4 is a configuration diagram of an error flag generation circuit according to one embodiment.

[0052] Referring to FIG. 4, an error flag generation circuit (500) according to one embodiment may include a first interval setting circuit (510), a counter (520), a second interval setting circuit (530), and a flag generator (540).

[0053] The first section setting circuit (510) may be configured to set and reset a section for monitoring error detection and correction conditions. For example, the first section setting circuit (510) may be configured to count the number of read command inputs and output a reset signal (RST) when a set number of read commands are provided. That is, the period until a set number of read commands is provided may be determined as the monitoring section, but is not limited thereto.

[0054] The counter (520) can count the number of times an error correction signal (CE) is generated by the ECC circuit (400). The counter (520) can activate a pre-signal (PRE) when the number of times an error correction signal (CE) is generated reaches a set threshold. The counter (520) can be initialized by receiving a reset signal (RST) from the interval setting circuit (510). Therefore, the counter (520) can activate a pre-signal (PRE) when the number of times an error correction signal (CE) is generated reaches a threshold during the first monitoring interval, and reset the pre-signal (PRE) as the first monitoring interval ends.

[0055] The second section setting circuit (530) may be configured to generate an output enable signal (EN) by delaying the activation section of the pre-recording signal (PRE) during the tracking monitoring section in response to a reset signal (RST). The tracking monitoring section may include at least a monitoring section that follows the previous monitoring section.

[0056] In one embodiment, the second section setting circuit (530) may include a delay circuit (531) and a combination circuit (533).

[0057] The delay circuit (531) receives a preliminary signal (PRE) and, in response to a reset signal (RST), can generate a delayed preliminary signal (D_PRE) by delaying the activation period of the preliminary signal (PRE) to the tracking monitoring period. Alternatively, the delay circuit (531) may be configured to maintain the logic level of the preliminary signal (PRE) during the tracking monitoring period corresponding to the monitoring period when the preliminary signal (PRE) is activated, and output it as a delayed preliminary signal (D_PRE).

[0058] In another perspective, the delay circuit (531) can receive and output a first pre-signal (PRE) in response to a first reset signal (RST) generated as the first monitoring period ends. The delay circuit (531) can output a first delay pre-signal (D_PRE) by maintaining the output of the first pre-signal (PRE) until the second reset signal (RST) is provided after the end of the second monitoring period following the first monitoring period.

[0059] That is, the second section setting circuit (530) can be configured to output a preliminary signal (PRE) generated at a specific level during the previous monitoring section during the next monitoring section.

[0060] The combination circuit (533) can generate an output enable signal (EN) by combining a pre-signal (PRE) and a delayed pre-signal (D_PRE). When the pre-signal (PRE) is enabled in the first monitoring period, the output enable signal (EN) can remain active during the first monitoring period and the tracking monitoring period. In one embodiment, the tracking monitoring period may include at least one monitoring period.

[0061] The flag generator (540) can be configured to output an error correction signal (CE) as an error flag (EF) in response to an output enable signal (EN).

[0062] In one embodiment, when the number of occurrences of an error correction signal (CE) within a first monitoring period reaches a threshold, a preliminary signal (PRE) output from the counter (520) may be enabled. When the first monitoring period ends, a first reset signal (RST) is output from the first section setting circuit (510) to initialize the counter (520) and the preliminary signal (PRE) may be disabled.

[0063] The delay circuit (531) of the second section setting circuit (530) outputs a delayed preliminary signal (D_PRE) that maintains the logic level of the enabled preliminary signal (PRE) up to the tracking monitoring section corresponding to the first monitoring section. That is, the delay circuit (531) can output the delayed preliminary signal (D_PRE) by extending the activation section of the preliminary signal (PRE) from the point in time when the first reset signal (RST) is generated after the end of the first monitoring section until the point in time when the second reset signal (RST) is generated after the end of the second monitoring section.

[0064] The combination circuit (533) can output an output enable signal (EN) synchronized from the enable time of the pre-signal (PRE) to the disable time of the delay pre-signal (D_PRE) in response to the pre-signal (PRE) and the delay pre-signal (D_PRE).

[0065] During the period when the output enable signal (EN) is enabled, the flag generator (540) can output an error flag (EF) whenever an error correction signal (CE) is input.

[0066] FIG. 5 is a configuration diagram of an error flag generation circuit according to one embodiment.

[0067] Referring to FIG. 5, an error flag generation circuit (500-1) according to one embodiment may include a second counter (550), a second counter (560), an enable signal generation unit (570), and a selection unit (580).

[0068] The first counter (550) can be configured to count the number of inputs of a read command (RD) and output a reset signal (RST) when a set number of read commands (RD) are provided.

[0069] The second counter (560) may be configured to activate a pre-recording signal (PRE) when the number of occurrences of an error correction signal (CE) provided by the ECC circuit (400) reaches a set threshold. The second counter (560) may be initialized in response to a reset signal (RST) provided by the first counter (550).

[0070] The enable signal generation unit (570) may include a flip-flop circuit (571) and an OR circuit unit (573).

[0071] The flip-flop circuit (571) may be configured to include a flip-flop circuit (571) that stores a preliminary signal (PRE) in response to a first reset signal (RST) generated after the end of a first monitoring period, and outputs the preliminary signal (PRE) as a delayed preliminary signal (D_PRE) until a second reset signal (RST) is generated after the end of a second monitoring period that follows the first monitoring period.

[0072] The OR circuit section (573) can generate an output enable signal (EN) by performing a logical OR operation on the pre-prep signal (PRE) and the delayed pre-prep signal (PRE).

[0073] The selection unit (580) receives a ground voltage signal (VSS) and an error correction signal (CE), and when the output enable signal (EN) is activated, it can be configured to select the error correction signal (CE) and output it as an error flag (EF).

[0074] In one embodiment, the count count of the first counter (550) and the second counter (560) can be set, changed, or programmed through a fuse option, a mode register set (MRS), etc.

[0075] FIG. 6 is a timing diagram for explaining the operation concept of an error flag generation circuit according to one embodiment.

[0076] When reading data from a memory cell array in response to a read command (RD), if a correctable error occurs, an error correction signal (CE) is output from the ECC circuit (400).

[0077] Referring to Fig. 6, since no error correction signal (CE) was generated during the first monitoring period (Monitoring Period 1), the pre-recording signal (PRE) remains in a disabled state.

[0078] After the first monitoring period (Monitoring Period 1) ends, the second monitoring period (MP2) begins. Before the second monitoring period (MP2) ends, a preliminary signal (PRE) is activated in response to the detection that the number of correctable errors (E1, E2) has reached a threshold. The preliminary signal (PRE) remains active during the second monitoring period (MP2) and can be reset according to the second reset signal (RST2).

[0079] Meanwhile, the output section of the preliminary signal (PRE) can be extended to a tracking monitoring section, for example, to the next monitoring section, to generate a delayed preliminary signal (D_PRE). That is, the preliminary signal (PRE) generated in the second monitoring section (MP2) can be received according to the second reset signal (RST2) and maintained until the third reset signal (RST3) is generated after the end of the third monitoring section (MP3), thereby outputting the delayed preliminary signal (D_PRE).

[0080] During the period in which the output enable signal (EN), which is a combination of the pre-prep signal (PRE) and the delayed pre-prep signal (D_PRE), is enabled, an error flag (EF) can be output whenever an error correction signal (CE) is input.

[0081] Referring to FIG. 6, when the pre-recording signal (PRE) is enabled in the second monitoring interval (MP2), an error flag (EF1) is output. In the third monitoring interval (MP3), since the number of occurrences of the error correction signal (CE) is less than the threshold, the output enable signal (EN) is activated up to the third monitoring interval (MP3). Then, the error correction signal (CE) generated in the third monitoring interval (MP3) is output as an error flag (EF2).

[0082] FIGS. 7 to 9 are configuration diagrams of a stacked semiconductor device according to embodiments.

[0083] FIG. 7 is a configuration diagram of a stacked semiconductor device according to one embodiment.

[0084] A stacked semiconductor device (40) according to one embodiment may include a stacked structure (410) in which a plurality of dies are stacked. The stacked structure (410) may be configured in the form of a High Bandwidth Memory (HBM) or a Hybrid Memory Cube (HMC) in which a plurality of memory dies are stacked and electrically connected through through silicon vias (TSVs) to increase the number of input / output units and thereby increase the bandwidth.

[0085] The stacked structure (410) may include a base die (414) and a plurality of core dies (412).

[0086] A plurality of core dies (412) can be stacked on a base die (414) and connected to each other through through-hole electrodes (TSV). Memory cells for storing data and circuits for core operation of the memory cells can be disposed on each of the core dies (412).

[0087] The core die (412) is electrically connected to the base die (414) through the through-hole electrode (TSV) and can receive signals and power from the base die (414) through the through-hole electrode (TSV).

[0088] The base die (414) can perform various functions within the stacked semiconductor device (40), for example, power management functions through partial activation of memory cells or timing control functions between the core die (412) and the base die (414).

[0089] The physical region (PHY) provided in the base die (414) may be an input / output region for addresses, instructions, data, control signals, etc. The physical region (PHY) may be equipped with as many input / output circuit sections as can satisfy the data processing speed required for the stacked semiconductor device (40). In addition, the physical region (PHY) portion on the back of the base die (414) may be equipped with a plurality of input / output terminals and power supply terminals to receive signals and power required during input / output operations.

[0090] The core die (412) may include a semiconductor memory device such as that shown in FIGS. 2 to 5, for example.

[0091] FIG. 8 is a configuration diagram of a stacked semiconductor device according to one embodiment.

[0092] Referring to FIG. 8, a stacked semiconductor device (400) may include a stacked structure (410) of a plurality of core dies (412) and base dies (414), a memory host (420), and an interface substrate (430). The memory host (420) may be a CPU, a GPU, an ASIC (Application Specific Integrated Circuit), or an FPGA (Field Programmable Gate Array), etc.

[0093] The base die (414) may have a circuit for an interface between the core die (412) and the memory host (420). The stacked structure (410) may have a structure similar to that described with reference to FIG. 7.

[0094] The stacked structure (410) and the memory host (420) can have their respective physical regions (PHYs) connected through an interface substrate (430). The interface substrate (430) may be referred to as an interposer.

[0095] FIG. 9 is a configuration diagram of a stacked semiconductor device according to one embodiment.

[0096] The stacked semiconductor device (4000) illustrated in FIG. 9 can be understood as the stacked semiconductor device (400) illustrated in FIG. 8 placed on a package substrate (440).

[0097] The package substrate (440) and the interface substrate (430) can be electrically connected through a connection terminal.

[0098] A System In Package (SiP) type semiconductor device can be implemented by stacking a stacked structure (410) and a memory host (420) as shown in FIG. 7 on an interface substrate (430), mounting them on a package substrate (440), and then packaging them.

[0099] FIG. 10 is a configuration diagram of a processing system according to one embodiment.

[0100] Referring to FIG. 10, the processing system (5000) of the present embodiment may be a structure in which four stacked memory structures (510-1, 510-2, 510-3, 510-4) are connected to at least one main processor (520) placed on an interposer (530).

[0101] Each of the four stacked memory structures (510-1, 510-2, 510-3, 510-4) may be a structure in which a base die and a plurality of memory dies are stacked, as exemplified by the embodiments described above.

[0102] As such, those skilled in the art to which the present invention pertains will understand that the present invention may be implemented in other specific forms without altering its technical concept or essential features. Therefore, the embodiments described above should be understood as illustrative in all respects and not restrictive. The scope of the present invention is defined by the claims set forth below rather than by the detailed description above, and all modifications or variations derived from the meaning and scope of the claims and their equivalents should be interpreted as being included within the scope of the present invention. Explanation of the symbols

[0103] 10: Memory System 100: Memory controller 200: Semiconductor memory device

Claims

Claim 1 A semiconductor memory device comprising: a memory cell array; an ECC (Error Check and Correction) circuit that detects and corrects an error from data read from the memory cell in response to a read command and outputs an error correction signal whenever an error is corrected; and a flag generation circuit configured such that when the number of times the error correction signal is output reaches a threshold during a monitoring period, a flag output mode is enabled and the error correction signal is output as an error flag in the flag output mode, and the flag output mode is maintained for at least a first monitoring period. Claim 2 delete Claim 3 In claim 1, the flag output mode enabled in the first monitoring period is a semiconductor memory device maintained during the first monitoring period and the tracking monitoring period. Claim 4 A semiconductor memory device according to claim 3, wherein the tracking monitoring section is determined to be a second monitoring section following the first monitoring section. Claim 5 A semiconductor memory device according to claim 1, wherein the monitoring section is determined as a section in which a set number of read commands are input. Claim 6 delete Claim 7 A method of operating a semiconductor memory device comprising: a step of detecting an error from data read from a memory cell in response to a read command; a step of outputting an error correction signal whenever the error is corrected; a step of enabling a flag output mode when the number of times the error correction signal is output reaches a threshold during a monitoring period; and a step of maintaining the flag output mode for at least a first monitoring period and outputting the error correction signal as an error flag in the flag output mode. Claim 8 delete Claim 9 In claim 7, the flag output mode enabled in the first monitoring period is a method of operation of a semiconductor memory device maintained during the first monitoring period and the tracking monitoring period. Claim 10 A method of operation of a semiconductor memory device according to claim 9, wherein the tracking monitoring section is determined to be a second monitoring section following the first monitoring section. Claim 11 A method of operation of a semiconductor memory device according to claim 7, wherein the monitoring section is determined as a section in which a set number of read commands are input. Claim 12 A memory system comprising: a semiconductor memory device; and a memory controller for controlling the semiconductor memory device, wherein the semiconductor memory device comprises: a memory cell array; an ECC (Error Check and Correction) circuit that detects and corrects an error from data read from the memory cell in response to a read command and outputs an error correction signal whenever an error is corrected; and a flag generation circuit configured such that when the number of times the error correction signal is output reaches a threshold during a monitoring period, a flag output mode is enabled, the error correction signal is generated as an error flag in the flag output mode and output to the memory controller, and the flag output mode is maintained for at least a first monitoring period. Claim 13 delete Claim 14 In claim 12, the flag output mode enabled in the first monitoring period is a memory system maintained during the first monitoring period and the second monitoring period following the first monitoring period. Claim 15 In claim 12, the above-mentioned monitoring section is determined as a section in which a set number of read commands are input.

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