Organic interposer and method for manufacturing organic interposer

Abstract

An organic interposer capable of improving insulation reliability and a method for manufacturing the same are provided. The organic interposer (10) comprises an organic insulating laminate (12) comprising a plurality of organic insulating layers and a plurality of wirings (13) arranged within the organic insulating laminate (12), wherein the wirings (13) and the organic insulating layers are separated by a barrier metal film (14). The organic insulating laminate (12) may include a first organic insulating layer (21) having a plurality of grooves (21a) in which the wirings (13) are arranged, and a second organic insulating layer (22) laminated on the first organic insulating layer (21) to embed the wirings (13).

Description

Technology Field

[0001] The present disclosure relates to an organic interposer and a method for manufacturing an organic interposer. Background Technology

[0002] To achieve high density and high performance in semiconductor packages, a mounting configuration in which chips of different performance capabilities are mixed in a single package has been proposed. In this case, high-density interconnect technology between chips that is cost-effective becomes important (e.g., see Patent Document 1).

[0003] Non-patent literature 1 and non-patent literature 2 describe an embodiment of a Package on Package (PoP) in which different packages are connected by stacking them on a package by flip-chip mounting. This PoP is an embodiment that is widely adopted in smartphones, tablet terminals, etc.

[0004] In addition, as other forms for mounting multiple chips at high density, package technology using an organic substrate having high-density wiring (organic interposer), fan-out type package technology having through-mold vias (TMV) (FO-WLP: Fun Out-Wafer Level Package), package technology using a silicon or glass interposer, package technology using through-silicon vias (TSV), and package technology using chips embedded in a substrate for inter-chip transmission have been proposed.

[0005] In particular, when semiconductor chips are mounted together in an organic interposer and FO-WLP, a fine wiring layer is required to conduct high-density connections between the semiconductor chips (e.g., see Patent Document 2). Prior art literature

[0006] Patent Document 1: Japanese Patent Publication No. 2012-529770 Patent Document 2: Specification of U.S. Patent Application Publication No. 2011 / 0221071

[0007] Non-patent document 1: Jinseong Kim et al., 「Application of Through Mold Via (TMV) as PoP Base Package」, Electronic Components and Technology Conference (ECTC), p.1089-1092 (2008) Non-patent document 2: SW Yoon et al., 「Advanced Low Profile PoP Solution with Embedded Wafer Level PoP(eWLB-PoP) Technology」, ECTC, p.1250-1254(2012) The problem to be solved

[0008] In build-up substrates, wafer level packages (WLP), and bottom packages of fan-out type PoPs, an organic interposer having a laminate (organic insulating laminate) formed by stacking multiple organic insulating layers may be used. For example, when multiple fine wires having a line width and a space width of 10 μm or less are arranged within this organic insulating laminate, the wires are formed using the trench method. The trench method is a method of forming a metal layer to serve as wiring in a trench (groove) formed on the surface of an organic insulating layer by means of a plating method or the like. Therefore, the shape of the wiring formed on the organic insulating layer follows the shape of the groove.

[0009] When forming fine wiring within an organic insulating laminate using the trench method, highly conductive metal materials, such as copper, are sometimes used to reduce costs and suppress the rise in wiring resistance. When wiring is formed using such metal materials, the metal material may diffuse into the organic insulating laminate. In this case, there is a risk of short circuits between the wirings through the diffused metal material, which poses a challenge to the insulation reliability of the organic interposer.

[0010] The present invention aims to provide an organic interposer capable of improving insulation reliability and a method for manufacturing the same. means of solving the problem

[0011] An organic interposer related to the first aspect of the present invention comprises an organic insulating laminate comprising a plurality of organic insulating layers and a plurality of wirings arranged within the organic insulating laminate, wherein the wirings and the organic insulating layers are separated by a barrier metal film.

[0012] In this organic interposer, the wiring and the organic insulating layer are separated by a barrier metal film. Consequently, the diffusion of metal materials within the wiring into the organic insulating laminate is suppressed by the barrier metal film. Therefore, since short circuits between multiple wirings caused by diffused metal materials can be suppressed, the insulation reliability of the organic interposer can be improved.

[0013] The organic insulating laminate may include a first organic insulating layer having a plurality of grooves in which wiring is arranged, and a second organic insulating layer laminated to the first organic insulating layer to embed the wiring. In this case, each of the plurality of wirings has a shape that follows the grooves of the first organic insulating layer. Because of this, by forming a plurality of grooves having fine widths and spacing, fine wiring can be easily formed.

[0014] The barrier metal film may include a first barrier metal film formed between the wiring and the inner surface of the groove, and a second barrier metal film formed between the wiring and the second organic insulating layer. In this case, the diffusion of the metal material within the wiring into the first organic insulating layer is well suppressed by the first barrier metal film. Additionally, the diffusion of the metal material into the second organic insulating layer is well suppressed by the second barrier metal film.

[0015] The first barrier metal film may include at least one of titanium, nickel, palladium, chromium, tantalum, tungsten, and gold. Since titanium, nickel, palladium, chromium, tantalum, tungsten, and gold are all difficult to diffuse into the first and second organic insulating layers, the insulation reliability of the organic interposer can be further improved.

[0016] The second barrier metal film may be a plated film. In this case, the manufacturing process of the organic interposer can be simplified because the second barrier metal film can be selectively formed on the wiring within the groove.

[0017] The second barrier metal film may be a nickel-plated film. In this case, a second barrier metal film having good flatness can be easily formed. Additionally, since nickel is difficult to diffuse into the first and second organic insulating layers, the insulation reliability of the organic interposer can be suitably improved.

[0018] The second barrier metal film may be a palladium-plated film. In this case, the second barrier metal film can be easily made thin. Additionally, since palladium is difficult to diffuse into the first and second organic insulating layers, the insulation reliability of the organic interposer can be suitably improved.

[0019] The thickness of the second barrier metal film may be 0.001 μm or more and 1 μm or less. In this case, the diffusion of the metal material within the wiring into the second organic insulating layer is effectively suppressed by the second barrier metal film.

[0020] The surface roughness of the second barrier metal film may be 0.01 μm or more and 1 μm or less. In this case, the second barrier metal film can adhere well to the second organic insulating layer. In addition, the breakage of the organic interposer caused by the surface roughness of the second barrier metal film can be suppressed.

[0021] The thickness of the first organic insulating layer may be 1 μm or more and 10 μm or less. In this case, a plurality of grooves having a width and spacing of 10 μm or less can be formed using the first organic insulating layer.

[0022] The first organic insulating layer may be a cured film formed by curing a photosensitive organic insulating resin comprising a photogenerative agent, a compound having phenolic hydroxyl groups, and a thermosetting resin. In this case, grooves having a fine width and spacing can be easily formed in the first organic insulating layer. Additionally, since the moisture contained in the first organic insulating layer can be reduced, it becomes difficult for metal materials to diffuse into the first organic insulating layer. Accordingly, the insulation reliability of the organic interposer can be improved.

[0023] A method for manufacturing an organic interposer related to a second aspect of the present invention comprises: a first step of forming a plurality of grooves in a first organic insulating layer; a second step of forming a first barrier metal film on the first organic insulating layer to cover the inner surface of the grooves; a third step of forming a wiring layer on the first barrier metal film to fill the grooves; a fourth step of thinning the wiring layer so that the first organic insulating layer is exposed; a fifth step of forming a second barrier metal film to cover the wiring layer within the grooves; and a sixth step of forming a second organic insulating layer on the first organic insulating layer and on the second barrier metal film.

[0024] In the method for manufacturing this organic interposer, a first barrier metal film can be formed between the inner surface of each groove and the wiring layer by undergoing the first to third processes. Additionally, a second barrier metal film can be formed between the wiring layer and the second organic insulating layer in the stacking direction of the organic insulating layer by undergoing the fourth to sixth processes. Accordingly, the diffusion of metal materials within the wiring layer into the first and second organic insulating layers is suppressed by the first and second barrier metal films. Therefore, since short circuits between multiple wirings through the diffused metal materials can be suppressed, the insulation reliability of the organic interposer can be improved.

[0025] In the third process, the wiring layer may be formed by a plating method in which the first barrier metal film is used as a seed layer. In this case, the wiring layer can be formed such that the first barrier metal film is clamped between the first organic insulating layer and the wiring layer. Accordingly, the diffusion of the metal material within the wiring layer into the first organic insulating layer is effectively suppressed.

[0026] In the fifth step, a second barrier metal film may be formed by a plating method in which the wiring layer is used as a seed layer. In this case, since a second barrier metal film can be selectively formed on the wiring layer, the manufacturing process of the organic interposer can be simplified.

[0027] In the fourth process, a portion of the wiring layer within the groove may be removed, and in the fifth process, a second barrier metal film may be formed to fill the groove. In this case, since the second barrier metal film is formed by being embedded within the groove, the formation of a step caused by the second barrier metal film in the organic interposer can be suppressed. Accordingly, semiconductor devices, etc., can be mounted well on the organic interposer. Effects of the invention

[0028] According to the present invention, an organic interposer having good insulation reliability and a method for manufacturing the same can be provided. Brief explanation of the drawing

[0029] FIG. 1 is a schematic cross-sectional view of a semiconductor package having an organic interposer related to the present embodiment. FIG. 2 is a schematic cross-sectional view of an organic interposer related to the present embodiment. Figures 3(a) to 3(c) are drawings illustrating a method for manufacturing an organic interposer. FIGS. 4(a) and FIGS. 4(b) are drawings illustrating a method for manufacturing an organic interposer. FIGS. 5(a) and FIGS. 5(b) are drawings illustrating a method for manufacturing an organic interposer. FIGS. 6(a) and FIGS. 6(b) are drawings illustrating a method for manufacturing an organic interposer. FIGS. 7(a) and FIGS. 7(b) are drawings illustrating a method for manufacturing an organic interposer. FIGS. 8(a) and FIGS. 8(b) are drawings illustrating a method for manufacturing an organic interposer. FIGS. 9(a) and FIGS. 9(b) are drawings illustrating a method for manufacturing an organic interposer. FIGS. 10(a) and FIGS. 10(b) are drawings illustrating a method for manufacturing an organic interposer. FIG. 11(a) is a plan view showing a sample for measurement evaluation of an example, and FIG. 11(b) is a cross-sectional view along the line XIb-XIb of FIG. 11(a). FIG. 12(a) is a plan view showing a sample for measurement evaluation of a comparative example, and FIG. 12(b) is a cross-sectional view along the line XIIb-XIIb of FIG. 12(a). FIG. 13(a) is a graph showing the results of the high-acceleration life test of Example 2 and Comparative Example 2, and FIG. 13(b) is a graph showing the results of the high-acceleration life test of Example 3 and Comparative Example 3. FIG. 14(a) is the EDX analysis result of Cu in the cross-sectional sample of the measurement evaluation sample of Example 3, FIG. 14(b) is the EDX analysis result of Ti in the cross-sectional sample, and FIG. 14(c) is the EDX analysis result of Ni in the cross-sectional sample. Specific details for implementing the invention

[0030] The present embodiment will be described in detail below with reference to the drawings. In the following description, identical or substantial parts are given the same reference numerals, and redundant descriptions are omitted. Furthermore, positional relationships such as up, down, left, and right are based on the positional relationships shown in the drawings unless otherwise specifically stated. Additionally, the dimensional ratios in the drawings are not limited to the ratios shown.

[0031] In the description of the embodiments and claims, where terms such as "left," "right," "front," "back," "top," "bottom," "upward," "downward," "first," and "second" are used, they are intended for illustrative purposes and do not necessarily imply that these are permanent relative positions. Furthermore, "layer" and "film" include structures formed on a part of the surface in addition to structures formed on the entire surface when observed in a plan view. Additionally, the term "process" includes not only independent processes but also processes that cannot be clearly distinguished from other processes, provided that the intended purpose of the process is achieved. Furthermore, regarding numerical ranges described stepwise in this specification, the upper or lower limit of a numerical range in any step may be substituted with the upper or lower limit of a numerical range in another step.

[0032] FIG. 1 is a schematic cross-sectional view of a semiconductor package having an organic interposer related to the present embodiment. The organic interposer of the present disclosure is suitable for use in package types requiring an interposer that mixes heterogeneous chips.

[0033] As illustrated in FIG. 1, the semiconductor package (100) is a device formed by mounting semiconductor chips (2A, 2B) on an organic interposer (10) formed on a substrate (1). The semiconductor chips (2A, 2B) are each fixed on the organic interposer (10) by corresponding underfills (3A, 3B) and are electrically connected to each other through surface wiring (16) (details to be described later) formed within the organic interposer (10). The substrate (1) is an encapsulated body formed by encapsulating semiconductor chips (2C, 2D) and electrodes (5A, 5B) with an insulating material (4). The semiconductor chips (2C, 2D) within the substrate (1) are made capable of being connected to an external device through electrodes exposed from the insulating material (4). The electrodes (5A, 5B) function as conductive paths for electrically connecting, for example, the organic interposer (10) and the external device.

[0034] Each of the semiconductor chips (2A to 2D) is, for example, a Graphic Processing Unit (GPU), volatile memory such as DRAM (Dynamic Random Access Memory) or SRAM (Static Random Access Memory), non-volatile memory such as flash memory, an RF chip, a silicon photonics chip, a MEMS (Micro Electro Mechanical Systems), a sensor chip, etc. The semiconductor chips (2A to 2D) may have TSVs. Each of the semiconductor chips (2A to 2D) may, for example, be a stacked semiconductor device. In this case, a semiconductor device stacked using TSVs may be used. The thickness of the semiconductor chips (2A, 2B) is, for example, 200 μm or less. From the perspective of thinning the semiconductor package (100), it is preferable that the thickness of the semiconductor chips (2A, 2B) be 100 μm or less. Furthermore, from the perspective of handling, it is more preferable that the thickness of the semiconductor chips (2A, 2B) be 30 μm or more.

[0035] The underfill (3A, 3B) is, for example, a capillary underfill (CUF), a mold underfill (MUF), a paste underfill (NCP), a film underfill (NCF), or a photosensitive underfill. Each underfill (3A, 3B) is composed of a liquid curable resin (e.g., epoxy resin) as the main component. In addition, the insulating material (4) is, for example, a curable resin having insulating properties.

[0036] Next, the organic interposer (10) related to the present embodiment will be described in detail with reference to FIG. 2. The organic interposer (10) in the present embodiment is an organic substrate that supports semiconductor devices, etc., and is, for example, a build-up substrate formed by laminating a material (prepreg) in which a glass cloth or carbon fiber is impregnated with resin, a substrate for wafer-level packaging, a coreless substrate, a substrate produced by heat-curing an encapsulation material, or a substrate in which a chip is encapsulated or embedded. The shape of the organic interposer (10) follows the shape of the substrate (11) described later, and may be wafer-shaped (approximately circular shape when viewed from a plane) or panel-shaped (approximately rectangular shape when viewed from a plane). In addition, the coefficient of thermal expansion of the organic interposer (10) is preferably 40 ppm / °C or less from the perspective of suppressing warping. From the perspective of insulation reliability of the organic interposer (10), the coefficient of thermal expansion is preferably 20 ppm / °C or less.

[0037] The organic interposer (10) formed on the substrate (11) illustrated in FIG. 2 comprises an organic insulating laminate (12) comprising a plurality of organic insulating layers, a plurality of wirings (13) arranged within the organic insulating laminate (12), a barrier metal film (14) covering the wirings (13), through wirings (15) penetrating the organic insulating laminate (12), and surface wirings (16) formed on the surface of the organic insulating laminate (12) and in the vicinity thereof.

[0038] The substrate (11) is a support that supports the organic interposer (10). The shape of the substrate (11) as seen from a plane is, for example, a circular shape or a rectangular shape. In the case of a circular shape, the substrate (11) has, for example, a diameter of 200 mm to 450 mm. In the case of a rectangular shape, one side of the substrate (11) is, for example, 300 mm to 700 mm.

[0039] The substrate (11) is, for example, a silicon substrate, a glass substrate, or a fillable copper foil. The substrate (11) may be, for example, a build-up substrate, a substrate for wafer-level packaging, a coreless substrate, a substrate produced by heat-curing an encapsulating material, or a substrate in which a chip is encapsulated or embedded. When a silicon substrate or a glass substrate, etc., is used as the substrate (11), an unillustrated temporary fixing layer may be formed to temporarily fix the organic interposer (10) and the substrate (11). In this case, the substrate (11) can be easily peeled from the organic interposer (10) by removing the temporary fixing layer. Also, the fillable copper foil is a laminate in which a support, a release layer, and a copper foil are superimposed in order. In the fillable copper foil, the support corresponds to the substrate (11), and the copper foil corresponds to the material of a portion of the copper wiring included in the through wiring (15).

[0040] The organic insulating laminate (12) comprises a first organic insulating layer (21) having a plurality of grooves (21a) into which corresponding wiring (13) is arranged, and a second organic insulating layer (22) laminated on the first organic insulating layer (21) to embed the wiring (13). Additionally, the organic insulating laminate (12) has a plurality of openings (12a) formed therein for forming through wiring (15).

[0041] A plurality of grooves (21a) are formed on the surface opposite to the substrate (11) in the first organic insulating layer (21). In a cross-section along a direction orthogonal to the extension direction of the grooves (21a), each of the grooves (21a) has an approximately rectangular shape. Accordingly, the inner surface of the grooves (21a) has a side surface and a bottom surface. Additionally, the plurality of grooves (21a) have a predetermined line width (L) and a space width (S). Each of the line width (L) and the space width (S) is, for example, 0.5 μm to 10 μm, preferably 0.5 μm to 5 μm, and more preferably 2 μm to 5 μm. From the perspective of realizing high-density transmission of the organic interposer (10), it is preferable that the line width (L) be 1 μm to 5 μm. The line width (L) and the space width (S) may be set to be the same or different. The line width (L) corresponds to the width of the groove (21a) in a direction perpendicular to the extension direction of the groove (21a) when viewed from a plane. The space width (S) corresponds to the distance between adjacent grooves (21a). The depth of the groove (21a) corresponds, for example, to the thickness of the fourth organic insulating layer (24) described later.

[0042] Preferably, the surface roughness of the inner surface of the groove (21a) is 0.01 μm to 0.1 μm. When the surface roughness is 0.01 μm or more, the adhesion of the object adhering to the first organic insulating layer (21) within the groove (21a) and the temperature cycle resistance are improved. When the surface roughness is 0.1 μm or less, there is a tendency to suppress short circuits in the wiring (13) and improve the high-frequency characteristics of the wiring (13). The surface roughness of the inner surface of the groove (21a) is calculated, for example, by observing the cross-section of the groove (21a) with an electron microscope. Also, the surface roughness is the arithmetic mean roughness (Ra) specified in JIS B 0601 2001, and all "surface roughness" below shall be "surface roughness (Ra)". Temperature cycle resistance is resistance to volume change, performance deterioration, damage, etc., due to temperature changes.

[0043] The first organic insulating layer (21) is formed between the substrate (11) and the second organic insulating layer (22). The storage modulus of the first organic insulating layer (21) at room temperature is, for example, 500 MPa to 1000 GPa. By having the storage modulus of 500 MPa or more, the elongation of the first organic insulating layer (21) during grinding can be suppressed. Accordingly, for example, the elongated resin material can be prevented from covering the wiring (13) within the groove (21a). In addition, by having the storage modulus of 10 GPa or less, for example, the breakage of the grinding blade can be prevented, and consequently, the expansion of the surface roughness of the first organic insulating layer (21), etc. can be suppressed. Also, "room temperature" refers to approximately 25°C.

[0044] The first organic insulating layer (21) includes a third organic insulating layer (23) located on the substrate (11) side and a fourth organic insulating layer (24) located on the second organic insulating layer (22) side. A plurality of openings corresponding to the groove (21a) are formed in a part of the fourth organic insulating layer (24). The surface of the third organic insulating layer (23) exposed by these openings forms the bottom surface on the inner surface of the groove (21a). Additionally, each side surface on the inner surface of the groove (21a) is formed by the fourth organic insulating layer (24).

[0045] The thickness of the third organic insulating layer (23) and the fourth organic insulating layer (24) is, for example, 0.5 μm to 10 μm each. Accordingly, the thickness of the first organic insulating layer (21) is, for example, 1 μm to 20 μm. By having a thickness of 1 μm or more of the first organic insulating layer (21), the first organic insulating layer (21) contributes to stress relief of the organic insulating laminate (12) and can improve the temperature cycle resistance of the organic insulating laminate (12). By having a thickness of 20 μm or less of the first organic insulating layer (21), bending of the organic insulating laminate (12) is suppressed, and, for example, wiring can be easily exposed when the organic insulating laminate (12) is ground. In terms of forming wiring (13) with a width of 3 μm or less by performing exposure and development, the thickness of the first organic insulating layer (21) is preferably 15 μm or less, and more preferably 10 μm or less.

[0046] Each of the first organic insulating layer (21) and the second organic insulating layer (22) in the organic insulating laminate (12) comprises a curable insulating material, for example, in a liquid or film form. A film-type material (organic insulating material) is preferred from the perspective of the flatness of the organic insulating layer and manufacturing cost. In this case, for example, even if the surface roughness of the substrate (11) is 300 μm or more, the surface roughness of the organic insulating laminate (12) can be reduced. In addition, it is preferable that the film-type organic insulating material be laminateable at 40°C to 120°C. By setting the laminateable temperature to 40°C or higher, the tack (adhesiveness) of the organic insulating material at room temperature is suppressed, and good handling properties can be maintained. By setting the laminateable temperature to 120°C or lower, the occurrence of warping in the organic insulating laminate (12) can be suppressed.

[0047] The coefficient of thermal expansion of the organic insulating material after curing is, for example, 80 ppm / °C or less, in terms of suppressing warping of the organic insulating layer (and organic insulating laminate (12)). In terms of insulation reliability of the organic interposer (10), the coefficient of thermal expansion is preferably 70 ppm / °C or less. In addition, in terms of stress relaxation and processing precision of the organic insulating material, the coefficient of thermal expansion is more preferably 20 ppm / °C or more.

[0048] The organic insulating material is preferably a photosensitive organic insulating material (photosensitive insulating resin) in terms of ease of processing and processing precision. This photosensitive insulating resin is more preferably a negative-type photosensitive insulating resin in terms of heat resistance and ease of handling. The photocurable insulating resin may include a photoradical initiator or a photogenerator, but it is preferable to include a photogenerator in terms of ease of micro-processing. In the above regards, the organic insulating layer is most preferably a negative-type photosensitive insulating resin film containing a photogenerator.

[0049] As for the photogenerator, any compound that generates acid upon light irradiation is not particularly limited. From the perspective of efficient acid generation, the photogenerator is preferably, for example, an onium salt compound or a sulfonimide compound. Examples of onium salt compounds include iodonium salts or sulfonium salts. Specific examples include diaryl iodonium salts such as diphenyl iodium trifluoromethanesulfonate, diphenyl iodium p-toluenesulfonate, diphenyl iodium hexafluoroantimonate, diphenyl iodium hexafluorophosphate, and diphenyl iodium tetrafluoroborate; triaryl sulfonium salts such as triphenyl sulfonium trifluoromethanesulfonate, triphenyl sulfonium p-toluenesulfonate, and triphenyl sulfonium hexafluoroantimonate; 4-tert-butylphenyl-diphenyl sulfonium p-toluenesulfonate; and 4,7-di-n-butoxynaphthyl tetrahydrothiophenium trifluoromethanesulfonate. Specific examples of sulfonimide compounds include N-(trifluoromethylsulfonyloxy)succinimide, N-(trifluoromethylsulfonyloxy)phthalimide, N-(trifluoromethylsulfonyloxy)diphenylmaleimide, N-(trifluoromethylsulfonyloxy)bicyclo[2.2.1]hept-5-en-2,3-dicarboxyimide, N-(trifluoromethylsulfonyloxy)naphthalimide, N-(p-toluenesulfonyloxy)-1,8-naphthalimide, N-(10-campersulfonyloxy)-1,8-naphthalimide, etc.

[0050] In terms of reactivity, as a photocatalyst, a compound having a trifluoromethanesulfonate group, a hexafluoroantimonate group, a hexafluorophosphate group, or a tetrafluoroborate group may be used.

[0051] It is preferable that the photosensitive insulating resin is soluble in a 2.38 mass% aqueous solution of tetramethylammonium. From the perspective of the resolution, storage stability, and insulation reliability of the photosensitive insulating resin, it is preferable that the photosensitive insulating resin contains a compound having a phenolic hydroxyl group. Examples of compounds having a phenolic hydroxyl group include phenol / formaldehyde condensation novolak resin, cresol / formaldehyde condensation novolak resin, phenol-naphthol / formaldehyde condensation novolak resin, polyhydroxystyrene and its polymer, phenol-xylylene glycol condensation resin, cresol-xylylene glycol condensation resin, phenol-dicyclopentadiene condensation resin, etc.

[0052] It is preferable that the photosensitive insulating resin comprises a thermosetting resin. Examples of thermosetting resins include acrylate resin, epoxy resin, cyanate ester resin, maleimide resin, allyl nadiimide resin, phenol resin, urea resin, melamine resin, alkyd resin, unsaturated polyester resin, diallyl phthalate resin, silicone resin, resorcinol formaldehyde resin, trialyl cyanurate resin, polyisocyanate resin, resin containing tris(2-hydroxyethyl)isocyanurate, resin containing trialyl trimellitate, and thermosetting resin synthesized from cyclopentadiene. In terms of the resolution, insulation reliability, and adhesion to metal of the photosensitive insulating resin, it is more preferable that the thermosetting resin is a compound having any one of a methylol group, an alkoxyalkyl group, or a glycidyl group.

[0053] From the above perspective, it is most preferable that each of the first organic insulating layer (21) and the second organic insulating layer (22) is a cured film formed by curing a photosensitive organic insulating resin comprising a photogenerative agent, a compound having phenolic hydroxyl groups, and a thermosetting resin. Additionally, each of the first organic insulating layer (21) and the second organic insulating layer (22) may include a filler. From the perspective of ease of processing and processing precision, the average particle size of the filler is, for example, 500 nm or less. It is preferable that the filler content in the first organic insulating layer (21) (or the second organic insulating layer (22)) is less than 1 mass%. Furthermore, it is more preferable that the first organic insulating layer (21) and the second organic insulating layer (22) do not contain a filler.

[0054] A plurality of wires (13) are formed within the corresponding groove (21a) as described above and function as conductive paths within the organic interposer (10). For this reason, the width of the wires (13) is approximately equal to the line width (L) of the groove (21a), and the spacing between adjacent wires (13) is approximately equal to the space width (S) of the groove (21a). In order to perform the function as a conductive path well, it is preferable that the wires (13) contain a metal material having high conductivity. A metal material having high conductivity is, for example, copper, aluminum, or silver. These metal materials tend to diffuse into the organic insulating laminate (12) upon heating. In terms of conductivity and cost, it is preferable that the metal material included in the wires (13) be copper.

[0055] The barrier metal film (14) is a metal film formed to partition the wiring (13), the first organic insulating layer (21), and the second organic insulating layer (22). The barrier metal film (14) includes a first barrier metal film (31) formed between the wiring (13) and the inner surface of the groove (21a), and a second barrier metal film (32) formed between the wiring (13) and the second organic insulating layer (22). Accordingly, the first barrier metal film (31) is formed to partition the wiring (13) and the inner surface of the groove (21a) (i.e., the first organic insulating layer (21)). Additionally, the second barrier metal film (32) is formed to partition the wiring (13) and the second organic insulating layer (22).

[0056] The first barrier metal film (31) is a conductive film for preventing the diffusion of a metal material within the wiring (13) into the first organic insulating layer (21), and is formed along the inner surface of the groove portion (21a). The first barrier metal film (31) is a metal material that is difficult to diffuse into the organic insulating layer, and includes, for example, at least one of titanium, nickel, palladium, chromium, tantalum, tungsten, and gold. In terms of adhesion to the inner surface of the groove portion (21a), the first barrier metal film (31) is preferably a titanium film or an alloy film containing titanium. In addition, in terms of forming the first barrier metal film (31) by sputtering, the first barrier metal film (31) is preferably a titanium film, a tantalum film, a tungsten film, a chromium film, or an alloy film containing at least one of titanium, tantalum, tungsten, and chromium.

[0057] The thickness of the first barrier metal film (31) is less than half the width of the groove portion (21a) and less than the depth of the groove portion (21a), for example, 0.001 μm to 0.5 μm. From the perspective of preventing the diffusion of metal material within the wiring (13), it is preferable that the thickness of the first barrier metal film (31) be 0.01 μm to 0.5 μm. In addition, from the perspective of increasing the flatness of the first barrier metal film (31) and the amount of current flowing through the wiring (13), it is preferable that the thickness of the first barrier metal film (31) be 0.001 μm to 0.3 μm. From the above, it is most preferable that the thickness of the first barrier metal film (31) be 0.01 μm to 0.3 μm.

[0058] The second barrier metal film (32) is a conductive film for preventing the diffusion of a metal material within the wiring (13) into the second organic insulating layer (22), and is formed to cover the wiring (13). The second barrier metal film (32) is a metal material that is difficult to diffuse into the organic insulating layer, and includes, for example, at least one of titanium, nickel, palladium, chromium, tantalum, tungsten, cobalt, and gold. In addition, the second barrier metal film (32) may be a laminate of different metal films.

[0059] The second barrier metal film (32) is preferably a plating film (e.g., an electroless plating film) with the wiring (13) as a seed layer. For this reason, the second barrier metal film (32) is preferably a nickel plating film, a palladium plating film, a cobalt plating film, a gold plating film, or an alloy plating film comprising at least one of nickel, palladium, cobalt, and gold. It is preferably a nickel plating film or a palladium plating film in terms of adhesion to the wiring (13) and resistance to temperature cycles.

[0060] Examples of nickel plating films include an electroless nickel-phosphorus alloy plating film containing phosphorus, an electroless nickel-boron alloy plating film containing boron, or an electroless nickel-nitrogen alloy plating film containing nitrogen. It is preferable that the nickel content of the nickel plating film be 80 mass% or more. By having a nickel content of 80 mass% or more, the effect of improving the insulation reliability of the organic interposer (10) by the second barrier metal film (32) is well exhibited. From the perspective of insulation reliability, an electroless nickel-phosphorus alloy plating film is preferred for the nickel plating film.

[0061] The second barrier metal film (32) is preferably an electroless palladium plating film in order to obtain good insulation reliability at a thickness of 0.1 μm or less. Examples of electroless palladium plating films include, for instance, a substituted palladium plating film, an electroless palladium plating film using a formic acid compound as a reducing agent, a palladium-phosphorus alloy plating film using hypophosphorous acid or phosphoric acid as a reducing agent, or a palladium-boron alloy plating film using a boron compound.

[0062] The thickness of the second barrier metal film (32) is, for example, 0.001 μm to 1 μm. From the perspective of the yield of the second barrier metal film (32), it is preferable that the thickness of the second barrier metal film (32) be 0.01 μm to 1 μm. Furthermore, from the perspective of improving the production takt, thinning, and temperature cycle resistance of the second barrier metal film (32), it is more preferable that the thickness be 0.001 μm to 0.5 μm. From the perspective of thinning the second barrier metal film (32) and the resolution of the photosensitive insulating resin, it is even more preferable that the thickness be 0.001 μm to 0.3 μm. From the above perspectives, it is most preferable that the thickness of the second barrier metal film (32) be 0.01 μm to 0.3 μm.

[0063] The surface roughness (Ra) of the second barrier metal film (32) is influenced by the surface roughness of the wiring (13), and is, for example, 0.01 μm to 1 μm. When the surface roughness (Ra) of the second barrier metal film (32) is 0.01 μm or more, reliability such as adhesion between the second barrier metal film (32) and the second organic insulating layer (22) and temperature cycle resistance can be secured. When the surface roughness (Ra) of the second barrier metal film (32) is 1 μm or less, it is possible to suppress disconnection within the organic interposer (10) caused by irregularities that occur during the formation of the second organic insulating layer (22), and at the same time, suppress the deterioration of the resolution of the organic insulating laminate (12). From the perspective of adhesion with the second organic insulating layer (22), it is preferable that the surface roughness (Ra) of the second barrier metal film (32) be 0.03 μm or more. In terms of temperature cycle resistance, it is preferable that the surface roughness (Ra) of the second barrier metal film (32) be 0.5 μm or less. In terms of high-frequency characteristics, it is more preferable that the surface roughness (Ra) of the second barrier metal film (32) be 0.1 μm or less. In the above regard, it is most preferable that the surface roughness (Ra) of the second barrier metal film (32) be 0.03 μm to 0.1 μm.

[0064] In the organic interposer (10), the surface roughness (Ra) of the surface formed by combining the first organic insulating layer (21) (i.e., the fourth organic insulating layer (24)) and the second barrier metal film (32) is, for example, 0.01 μm to 1 μm. By having a surface roughness (Ra) of 0.01 μm or more of the surface, the adhesion between the first organic insulating layer (21) (and the second barrier metal film (32)) and the second organic insulating layer (22) is improved. Additionally, by having a surface roughness of 1 μm or less of the surface, the bending of the organic insulating laminate (12) is suppressed, and, for example, when the organic insulating laminate (12) is ground, wiring, etc. can be easily exposed. The surface roughness (Ra) of the above surface is calculated by scanning a range of 100×100 μm including both the first organic insulating layer (21) and the second barrier metal film (32) using, for example, a laser microscope (manufactured by Olympus Corporation, “LEXT OLS3000”).

[0065] The surface roughness (Ra) of the surface formed by combining the first organic insulating layer (21) and the second barrier metal film (32) can be controlled by flattening the wiring (13) and the first organic insulating layer (21). Examples of flattening treatments for the surface include chemical mechanical polishing (CMP) or fly cutting. It is preferable to use fly cutting to suppress dishing of the wiring (13). In addition, fly cutting is a method of physically grinding an object using a grinding device such as a surface planer.

[0066] The through wiring (15) is wiring embedded in the opening (12a) of the organic insulating laminate (12) and functions as a connection terminal for an external device. The through wiring (15) is composed of a plurality of wiring layers (15a to 15c) stacked together. The wiring layer (15b) includes a wiring layer formed simultaneously with the wiring (13) and a metal film formed simultaneously with the barrier metal film (14).

[0067] The surface wiring (16) is wiring for electrically connecting semiconductor chips mounted on the organic interposer (10). For this reason, both ends of the surface wiring (16) are exposed from the organic interposer (10), and the surface wiring (16) other than the two ends is embedded in the organic interposer (10) (more specifically, the second organic insulating layer (22)). For this reason, the second organic insulating layer (22) includes at least two organic insulating layers.

[0068] Next, with reference to FIGS. 3 to 10, a method for manufacturing an organic interposer (10) related to the present embodiment will be described. The organic interposer (10) formed by the following manufacturing method is particularly suitable for shapes that require, for example, miniaturization and multi-pinning. Also, FIG. 4(b) is an enlarged view of a part of FIG. 4(a). Likewise, FIG. 5(b), FIG. 6(b), FIG. 7(b), FIG. 8(b), and FIG. 9(b) are each enlarged views of a part of the corresponding figure.

[0069] First, as a first step, a wiring layer (15a) is formed on a substrate (11) as shown in FIG. 3(a). The wiring layer (15a) is formed by patterning a metal film formed on the substrate (11). In the first step, the metal film is formed by, for example, a physical vapor deposition (PVD) method such as coating, vacuum deposition, or sputtering, a printing method or spray method using a metal paste, or various plating methods. In this embodiment, copper foil is used as the metal film.

[0070] In addition, when a temporary fixing layer (not shown) is formed between the substrate (11) and the wiring layer (15a), the temporary fixing layer comprises, for example, a resin containing a non-polar component such as polyimide, polybenzoxazole, silicone, or fluorine; a resin containing a component that expands in volume or foams upon heating or UV (ultraviolet rays); a resin containing a component that undergoes a cross-linking reaction upon heating or UV; or a resin that generates heat upon light irradiation. Methods for forming the temporary fixing layer include, for example, spin coating, spray coating, or lamination processing. From the perspective of achieving high compatibility between handling and carrier peelability, it is desirable that the temporary fixing layer be easily peeled off by external stimuli such as light or heat. From the perspective of being peelable so that the temporary fixing layer does not remain on the organic interposer (10) manufactured later, it is most desirable that the temporary fixing layer contains a resin that expands in volume upon heat treatment.

[0071] When a temporary fixing layer is formed between the substrate (11) and the wiring layer (15a), the wiring layer (15a) may be formed from the copper foil of the fillable copper foil. In this case, the substrate (11) corresponds to a support of the fillable copper foil, and the temporary fixing layer corresponds to a release layer of the fillable copper foil.

[0072] Next, as a second step, a third organic insulating layer (23) is formed on the substrate (11) to cover the wiring layer (15a), as shown in FIG. 3(b). In the second step, the wiring layer (15a) is covered by attaching the third organic insulating layer (23), which is a film containing a negative-type photosensitive insulating resin, to the substrate (11). Then, if necessary, exposure treatment, development treatment, or curing treatment is performed on the third organic insulating layer (23).

[0073] Next, as a third step, as illustrated in FIG. 3(c), a first organic insulating layer (21) is formed by forming a fourth organic insulating layer (24) on the third organic insulating layer (23). In the third step, a fourth organic insulating layer (24) on a film containing a negative-type photosensitive insulating resin is attached to the third organic insulating layer (23), just as in the second step. Then, if necessary, exposure treatment, development treatment, or curing treatment is performed on the fourth organic insulating layer (24).

[0074] Next, as a fourth step, as illustrated in FIG. 4(a) and FIG. 4(b), a plurality of grooves (21a) and openings (21b) are formed in the first organic insulating layer (21) (also referred to as the first process). In the fourth step, a plurality of grooves (21a) and openings (21b) are formed, for example, by laser ablation, photolithography, or imprinting. It is preferable to apply photolithography in terms of miniaturization of the grooves (21a) and the cost of forming them. For this reason, a plurality of grooves (21a) are formed by performing exposure and development treatments on the first organic insulating layer (21). Additionally, the openings (21b) are formed to expose the wiring layer (15a). Furthermore, if a photosensitive insulating resin is used in the first organic insulating layer (21), the pattern of the grooves (21a) can be formed smoothly in a short time. For this reason, the wiring described below can be made to have excellent high-frequency characteristics.

[0075] In the above photolithography, known projection exposure, contact exposure, or direct exposure methods may be used as methods for exposing the photosensitive insulating resin. Additionally, to develop the photosensitive insulating resin, an alkaline aqueous solution such as sodium carbonate or TMAH may be used.

[0076] In the above fourth step, after forming a plurality of grooves (21a) and openings (21b), the first organic insulating layer (21) may be further heat-cured. In this case, for example, the heating temperature is set to 100 to 200°C and the heating time is set to 30 minutes to 3 hours to heat-cure the first organic insulating layer (21).

[0077] Next, as a fifth step, as illustrated in FIG. 5(a) and FIG. 5(b), a first barrier metal film (31) is formed on the first organic insulating layer (21) to cover the inner surface of the groove (21a) (also referred to as the second process). In the fifth step, the first barrier metal film (31) is formed by, for example, a coating method, a PVD method, a printing method using a metal paste or a spray method, or various plating methods. In the case of a coating method, the first barrier metal film (31) is formed by heating after applying a complex of palladium or nickel onto the first organic insulating layer (21). In the case of using a metal paste, the first barrier metal film (31) is formed by sintering after applying a paste containing metal particles such as nickel or palladium onto the first organic insulating layer (21). In this embodiment, the first barrier metal film (31) is formed by sputtering, which is one of the PVD methods. In addition, the first barrier metal film (31) is formed to also cover the inner surface of the opening (21b).

[0078] Next, as a sixth step, as illustrated in FIG. 6(a) and FIG. 6(b), a wiring layer (13A) is formed on the first barrier metal film (31) to fill the groove (21a) (also referred to as the third process). In the sixth step, the wiring layer (13A) is formed by, for example, a method using metal paste, or by a plating method using the first barrier metal film (31) as a seed layer. The thickness of the wiring layer (13A) is preferably 0.5 to 3 times the thickness of the first organic insulating layer (21). If the thickness of the wiring layer (13A) is 0.5 times or more, there is a tendency to suppress the expansion of the surface roughness (Ra) of the wiring (13) formed in the subsequent process. Additionally, if the thickness of the wiring layer (13A) is 3 times or less, there is a tendency to suppress the bending of the wiring layer (13A) and to adhere well to the first organic insulating layer (21). Also, the wiring layer (13A) is formed to also embed the opening (21b).

[0079] Next, as a seventh step, as illustrated in FIG. 7(a) and FIG. 7(b), the wiring layer (13A) is thinned so that the first organic insulating layer (21) is exposed (also referred to as the fourth step). In the seventh step, the wiring layer (13A) is thinned by removing the portion of the wiring layer (13A) other than the groove (21a) and the opening (21b), and the portion of the first barrier metal film (31) that does not cover the groove (21a) or the opening (21b), thereby exposing the first organic insulating layer (21). Accordingly, wiring (13) embedded within the groove (21a) is formed. This thinning treatment may be a flattening treatment of the combined surface of the first organic insulating layer (21) and the wiring (13). In this case, the target portion of the wiring layer (13A) and the first barrier metal film (31) is removed by CMP or fly cutting, and the surface of the first organic insulating layer (21) is polished or ground to flatten it.

[0080] When using CMP in the seventh step, the slurry used is, for example, a slurry mixed with alumina, which is generally used for polishing resins; a slurry mixed with hydrogen peroxide and silica, which is used for polishing the first barrier metal film (31); and a slurry mixed with hydrogen peroxide and ammonium persulfate, which is used for polishing the wiring layer (13A). In order to reduce costs and control the surface roughness (Ra) to 0.01 μm to 1 μm, it is preferable to grind the first organic insulating layer (21), the first barrier metal film (31), and the wiring layer (13A) (wiring (13)) using a slurry mixed with alumina. When using CMP, there is a tendency for high costs. In addition, when the first organic insulating layer (21), the first barrier metal film (31), and the wiring layer (13A) (wiring (13)) are flattened simultaneously, dishing occurs in the wiring (13) due to the difference in grinding speed, and as a result, the flatness of the combined surface of the first organic insulating layer (21) and the wiring (13) tends to be significantly damaged. For this reason, it is more preferable to grind the first organic insulating layer (21), the first barrier metal film (31), and the wiring layer (13A) (wiring (13)) by a fly-cut method using a surface planer, with the view that the surface roughness (Ra) of the surface is 0.03 μm to 0.1 μm.

[0081] Next, as the eighth step, as illustrated in FIG. 8(a) and FIG. 8(b), a second barrier metal film (32) is formed to cover the wiring (13), which is the wiring layer (13A) within the groove (21a) (also referred to as the fifth step). In the eighth step, the second barrier metal film (32) is formed, for example, by a PVD method, a method using metal paste, or a plating method using the wiring (13) as a seed layer. In terms of forming the second barrier metal film (32) with good selectivity on the wiring (13), it is preferable to form the second barrier metal film (32) by a plating method using the wiring (13) as a seed layer. Also, before the plating process, cleaning of the exposed first organic insulating layer (21) with acid or protective treatment with benzotriazole, etc. may be performed. Also, by going through the eighth step, the wiring layer (15b) formed on the wiring layer (15a) is completed.

[0082] In the eighth step, it is preferable that the second barrier metal film (32) be formed on the portion of the first barrier metal film (31) that contacts the side of the groove (21a), in addition to the wiring (13). In this case, the wiring (13) can be covered without gaps by the first barrier metal film (31) and the second barrier metal film (32).

[0083] Next, as a ninth step, a second organic insulating layer (22) is formed on the first organic insulating layer (21) and the second barrier metal film (32) as illustrated in FIG. 9(a) and FIG. 9(b) (also referred to as the sixth step). In the ninth step, a second organic insulating layer (22) on a film comprising a negative-type photosensitive insulating resin is attached to the first organic insulating layer (21) and the second barrier metal film (32). The second organic insulating layer (22) may be the same film as the first organic insulating layer (21) or may be formed using a different photosensitive insulating resin. For the purpose of preventing the diffusion of the metal constituting the wiring (13), it is preferable not to perform a developing treatment on the second organic insulating layer (22).

[0084] Next, as a 10th step, an opening (22a) is formed in the second organic insulating layer (22) as shown in FIG. 10(a). In the 10th step, the opening (22a) is formed to expose the wiring layer (15b). The opening (22a) is formed, for example, by photolithography.

[0085] Next, as an eleventh step as illustrated in FIG. 10(b), a through wiring (15) is formed by filling a metal material into an opening (22a) to form a wiring layer (15c). In the eleventh step, the wiring layer (15c) is formed, for example, by a PVD method or various plating methods. Examples of metal materials include copper, nickel, tin, etc. After the eleventh step, the organic interposer (10) illustrated in FIG. 2 is manufactured by forming a surface wiring (16), etc. Additionally, if a temporary fixing layer is formed, the organic interposer (10) may be peeled off from the substrate (11).

[0086] According to the organic interposer (10) having the configuration described above, the wiring (13), the first organic insulating layer (21), and the second organic insulating layer (22) are separated by a barrier metal film (14). Because of this, the diffusion of metal material within the wiring (13) into the organic insulating laminate is suppressed by the barrier metal film (14). Therefore, since short circuits between multiple wirings (13) through the diffused metal material can be suppressed, the insulation reliability of the organic interposer (10) can be improved.

[0087] The organic insulating laminate (12) comprises a first organic insulating layer (21) having a plurality of grooves (21a) in which wiring (13) is arranged, and a second organic insulating layer (22) laminated to the first organic insulating layer (21) to embed the wiring (13). Accordingly, each of the plurality of wirings (13) has a shape that follows the grooves (21a) of the first organic insulating layer (21). Because of this, by forming a plurality of grooves (21a) having fine widths and spacing, fine wiring (13) can be easily formed.

[0088] The barrier metal film (14) comprises a first barrier metal film (31) formed between the wiring (13) and the inner surface of the groove (21a), and a second barrier metal film (32) formed between the wiring (13) and the second organic insulating layer (22). Because of this, the diffusion of the metal material within the wiring (13) into the first organic insulating layer (21) is well suppressed by the first barrier metal film (31). Additionally, the diffusion of the metal material into the second organic insulating layer (22) is well suppressed by the second barrier metal film (32).

[0089] The first barrier metal film (31) comprises at least one of titanium, nickel, palladium, chromium, tantalum, tungsten, and gold. Since titanium, nickel, palladium, chromium, tantalum, tungsten, and gold are all difficult to diffuse into the first organic insulating layer (21) and the second organic insulating layer (22), the insulation reliability of the organic interposer (10) can be further improved.

[0090] The second barrier metal film (32) may be a plated film. In this case, the second barrier metal film (32) can be optionally formed on the wiring (13) within the groove (21a), thereby simplifying the manufacturing process of the organic interposer (10). For example, the resist coating process, sputtering process, and resist removal process for forming the second barrier metal film (32) can be omitted.

[0091] The second barrier metal film (32) may be a nickel-plated film. In this case, a second barrier metal film (32) having good flatness can be easily formed. Additionally, since nickel is difficult to diffuse into the first organic insulating layer (21) and the second organic insulating layer (22), the insulation reliability of the organic interposer (10) can be suitably improved.

[0092] The second barrier metal film (32) may be a palladium-plated film. In this case, the second barrier metal film (32) can be formed thinly. Additionally, since palladium is difficult to diffuse into the first organic insulating layer (21) and the second organic insulating layer (22), the insulation reliability of the organic interposer (10) can be suitably improved.

[0093] The thickness of the second barrier metal film (32) may be 0.001 μm or more and 1 μm or less. In this case, the diffusion of the metal material within the wiring (13) into the second organic insulating layer (22) is well suppressed by the second barrier metal film (32).

[0094] The surface roughness (Ra) of the second barrier metal film (32) may be 0.01 μm or more and 1 μm or less. In this case, the second barrier metal film (32) can adhere well to the second organic insulating layer (22). In addition, the breakage of the organic interposer (10) caused by the surface roughness of the second barrier metal film (32) can be suppressed.

[0095] The thickness of the first organic insulating layer (21) may be 1 μm or more and 10 μm or less. In this case, a plurality of grooves (21a) having a width and spacing of 10 μm or less can be formed using the first organic insulating layer (21).

[0096] The first organic insulating layer (21) may be a cured film formed by curing a photosensitive organic insulating resin comprising a photogenerative agent, a compound having phenolic hydroxyl groups, and a thermosetting resin. In this case, a groove (21a) having a fine width and spacing can be easily formed in the first organic insulating layer (21). Additionally, since the moisture contained in the first organic insulating layer (21) can be reduced, it becomes difficult for a metal material to diffuse into the first organic insulating layer (21). Therefore, the insulation reliability of the organic interposer (10) can be improved.

[0097] According to the manufacturing method of the organic interposer (10) related to the present embodiment, a first barrier metal film (31) can be formed between the inner surface of each groove portion (21a) and the wiring layer (13A) by going through steps 4 to 6. Additionally, a second barrier metal film (32) can be formed between the wiring (13) and the second organic insulating layer (22) in the stacking direction of the organic insulating layer by going through steps 7 to 9. Because of this, the diffusion of metal material within the wiring (13) into the first organic insulating layer (21) and the second organic insulating layer (22) is suppressed by the first barrier metal film (31) and the second barrier metal film (32). Therefore, since short circuits between multiple wirings (13) through the diffused metal material can be suppressed, the insulation reliability of the organic interposer (10) can be improved.

[0098] In the sixth step, the wiring layer (13A) may be formed by a plating method in which the first barrier metal film (31) is used as a seed layer. In this case, the wiring layer (13A) can be formed such that the first barrier metal film (31) is clamped between the first organic insulating layer (21) and the wiring layer (13A). Accordingly, the diffusion of the metal material within the wiring layer (13A) into the first organic insulating layer (21) is effectively suppressed.

[0099] In the eighth step, a second barrier metal film (32) may be formed by a plating method in which the wiring (13) is used as a seed layer. In this case, the second barrier metal film (32) can be formed selectively on the wiring (13) without using, for example, a resist. Accordingly, since processes such as a resist formation process and a resist removal process can be omitted when forming the second barrier metal film (32), the manufacturing process of the organic interposer (10) can be simplified.

[0100] In addition, wiring (13) within the organic interposer (10) may be formed, for example, by the semi-additive method. The semi-additive method is a method of forming a seed layer, forming a resist having a desired pattern on the seed layer, thickening the exposed portion of the seed layer by electroplating or the like, removing the resist, and then etching the thin seed layer to obtain the desired wiring. However, when the semi-additive method is applied, the damage to the wiring is significant when etching the thin seed layer. Furthermore, it is difficult to ensure the adhesion strength of the wiring to the organic insulating layer. For this reason, when forming fine wiring with a line width and space width of, for example, 5 μm or less using the semi-additive method, the yield of the organic interposer tends to decrease significantly. Accordingly, in this embodiment, in order to suppress this yield reduction, a trench method is employed in which a groove (21a) is formed in the first organic insulating layer (21) in the fourth process and wiring (13) is formed within the groove (21a).

[0101] Although an organic interposer and a method for manufacturing the same related to one embodiment of the present disclosure have been described above, the present disclosure is not limited to the aforementioned embodiments and may be appropriately modified within the scope of the intent thereof. For example, the cross-sectional shape of the groove (21a) formed in the first organic insulating layer (21) is not limited to a roughly rectangular shape and may be other shapes such as a roughly trapezoidal shape or a roughly semicircular shape.

[0102] In the above embodiment, the wiring (13), wiring layers (15a to 15c), first barrier metal film (31), second barrier metal film (32), and surface wiring (16), etc., may each have a single-layer structure or a multi-layer structure consisting of a plurality of conductive layers.

[0103] In the above embodiment, the first organic insulating layer (21) includes both the third organic insulating layer (23) and the fourth organic insulating layer (24), but is not limited thereto. For example, the first organic insulating layer (21) may have a single-layer structure. In this case, the second and third steps in the above manufacturing method can be combined into one step, thereby simplifying the manufacturing process of the organic interposer (10).

[0104] In the seventh step of the manufacturing method in the above embodiment, a portion of the wiring layer (13A) (wiring (13)) within the groove portion (21a) may be removed, and in the subsequent eighth step, a second barrier metal film (32) may be formed to fill the groove portion (21a). In this case, since the second barrier metal film (32) is formed by being filled within the groove portion (21a), the formation of a step caused by the second barrier metal film (32) in the organic interposer (10) can be suppressed. That is, the surface roughness (Ra) of the combined surface of the second organic insulating layer (22) and the second barrier metal film (32) can be reduced. Accordingly, semiconductor devices, etc., can be mounted well on the organic interposer (10). Also, the removal of a portion of the wiring (13) within the groove portion (21a) is performed using, for example, dishing that occurs when performing CMP. Additionally, a portion of the wiring (13) within the groove (21a) is, for example, at least a portion of the wiring (13) located in the upper half of the groove (21a).

[0105] In the above embodiment, the organic insulating layer included in the organic insulating laminate (12) may include an adhesion aid. Examples of adhesion aids include silane coupling agents, triazole, or tetrazole-based compounds.

[0106] As a silane coupling agent, a compound having a nitrogen atom is preferably used to improve adhesion to the metal. Specifically, examples include N-2-(aminoethyl)-3-aminopropylmethyldimethoxysilane, N-2-(aminoethyl)-3-aminopropyltrimethoxysilane, 3-aminopropyltrimethoxysilane, 3-aminopropyltriethoxysilane, 3-triethoxysilyl-N-(1,3-dimethyl-butylidene)propylamine, N-phenyl-3-aminopropyltrimethoxysilane, tris-(trimethoxysilylpropyl)isocyanurate, 3-ureidopropyltrialkoxysilane, and 3-isocyanatopropyltriethoxysilane. The amount of the silane coupling agent used is preferably 0.1 to 20 parts by mass per 100 parts by mass of a compound having a phenolic hydroxyl group, considering the effects of addition, heat resistance, and manufacturing costs.

[0107] Triazole compounds include 2-(2'-hydroxy-5'-methylphenyl)benzotriazole, 2-(2'-hydroxy-3'-tert-butyl-5'-methylphenyl)-5-chlorobenzotriazole, 2-(2'-hydroxy-3',5'-di-tert-amylphenyl)benzotriazole, 2-(2'-hydroxy-5'-tert-octylphenyl)benzotriazole, 2,2'-methylenebis[6-(2H-benzotriazole-2-yl)-4-tert-octylphenol], 6-(2-benzotriazolyl)-4-tert-octyl-6'-tert-butyl-4'-methyl-2,2'-methylenebisphenol, 1,2,3-benzotriazole, Examples include 1-[N,N-bis(2-ethylhexyl)aminomethyl]benzotriazole, carboxybenzotriazole, 1-[N,N-bis(2-ethylhexyl)aminomethyl]methylbenzotriazole, 2,2'-[[(methyl-1H-benzotriazole-1-yl)methyl]imino]bisethanol.

[0108] Examples of tetrazole compounds include 1H-tetrazole, 5-amino-1H-tetrazole, 5-methyl-1H-tetrazole, 5-phenyl-1H-tetrazole, 1-methyl-5-ethyl-1H-tetrazole, 1-methyl-5-mercapto-1H-tetrazole, 1-phenyl-5-mercapto-1H-tetrazole, 1-(2-dimethylaminoethyl)-5-mercapto-1H-tetrazole, 2-methoxy-5-(5-trifluoromethyl-1H-tetrazole-1-yl)-benzaldehyde, 4,5-di(5-tetrazolyl)-[1,2,3]triazole, 1-methyl-5-benzoyl-1H-tetrazole, etc. The amount of the above triazole or tetrazole compound used is preferably 0.1 to 20 parts by mass per 100 parts by mass of a compound having a phenolic hydroxyl group, in terms of the effect of addition, heat resistance, and manufacturing cost.

[0109] The above silane coupling agent, triazole-based compound and tetrazole-based compound may each be used alone or in combination.

[0110] In addition, an ion capture agent may be added to the organic insulating layer. By adsorbing ionic impurities in the organic insulating layer with the ion capture agent, the insulation reliability during moisture absorption can be improved. Examples of such ion capture agents include compounds known as copper-resistant agents to prevent copper from ionizing and leaching, such as triazinethiol compounds and phenolic reducing agents, and powdered inorganic compounds such as bismuth-based, antimony-based, magnesium-based, aluminum-based, zirconium-based, calcium-based, titanium-based, and tin-based compounds, as well as mixtures thereof.

[0111] Examples of the above-mentioned ion capture agents include inorganic ion capture agents manufactured by Doa Synthetic Co., Ltd. (product names: IXE-300 (antimony-based), IXE-500 (bismuth-based), IXE-600 (antimony, bismuth mixed-based), IXE-700 (magnesium, aluminum mixed-based), IXE-800 (zirconium-based), and IXE-1100 (calcium-based)). These may be used individually or in a mixture of two or more types. The amount of the above-mentioned ion capture agent used is preferably 0.01 to 10 parts by mass per 100 parts by mass of a compound having a phenolic hydroxyl group, considering the effect of addition, heat resistance, and manufacturing cost.

[0112] Examples

[0113] The present invention will be explained in more detail by the following examples, but the present invention is not limited to these examples.

[0114] (Example 1)

[0115] The measurement evaluation samples shown in FIGS. 11(a) and 11(b) were prepared as follows. First, a photosensitive insulating resin film (52) with a thickness of 5 μm was attached to a silicon wafer (51) with a thickness of 150 mm. This photosensitive insulating resin film (52) was formed as follows. First, a photosensitive insulating composition was obtained by mixing a cresol novolak resin (manufactured by Asahi Yukizai Industry Co., Ltd., trade name: TR-4020G, 100 parts by mass), 1,3,4,6-tetrakis(methoxymethyl)glycoluryl (30 parts by mass), trimethylolpropane triglycidyl ether (40 parts by mass), triarylsulfonium salt (manufactured by San Apro Co., Ltd., trade name: CPI-310B, 8 parts by mass), and methyl ethyl ketone (100 parts by mass). Next, the obtained photosensitive insulating composition was applied to a polyethylene terephthalate film (manufactured by Teijin DuPont Film Co., Ltd., trade name: A-53) and dried in an oven at 90°C for 10 minutes to obtain a photosensitive insulating resin film (52) with a thickness of 5 μm.

[0116] Next, a photosensitive insulating resin film (52) attached to a silicon wafer (51) was subjected to exposure treatment, heat treatment, development treatment, and heat curing treatment in sequence. Next, a photosensitive insulating resin film (53) with a thickness of 5 μm, formed in the same manner as the film (52), was attached to the photosensitive insulating resin film (52). Next, the attached photosensitive insulating resin film (53) was subjected to exposure treatment through a photomask, followed by heat treatment, development treatment, and heat curing treatment in sequence. Accordingly, the photosensitive insulating resin film (53) was patterned, and a first groove (53a) and a second groove (53b) were formed in a comb shape to interlock with each other, a first connecting part (53c) connecting the first groove (53a) and a second connecting part (53d) connecting the second groove (53b) were formed. The width of the first groove (53a) and the width of the second groove (53b) were each set to 10 μm. These widths correspond to the line width (L) of the wiring described later. In addition, the distance (space width (S)) between adjacent first groove (53a) and second groove (53b) was set to 10 μm, and the length of each groove was set to 1 mm.

[0117] Next, a barrier metal film (54) containing titanium with a thickness of 0.05 μm was formed on a photosensitive insulating resin film (53) by sputtering. Next, a copper layer was formed to fill the first groove (53a), the second groove (53b), the first connection (53c), and the second connection (53d) by an electroplating method using the barrier metal film (54) as a seed layer. Next, a portion of the copper layer and the portion of the barrier metal film (54) that does not cover the inner surface of the first groove (53a), the second groove (53b), the first connection (53c), and the second connection (53d) were ground by a fly-cutting method using a surface planer. Accordingly, a first wiring (55a) embedded in the first groove (53a), a second wiring (55b) embedded in the second groove (53b), a first connecting wiring (55c) embedded in the first connecting part (53c), and a second connecting wiring (55d) embedded in the second connecting part (53d) were formed. As a surface planer, an automatic surface planer (manufactured by DISCO Co., Ltd., product name "DAS8930") was used. In addition, for grinding by the fly cut method, the feed speed was set to 1 mm / s, and the spindle rotation speed was set to 2000 min -1 Set it to.

[0118] Next, a barrier metal film (56) containing a nickel-phosphorus alloy with a thickness of 0.2 μm was formed by an electroless plating method in which each of the first wiring (55a), the second wiring (55b), the first connecting wiring (55c), and the second connecting wiring (55d) was used as a seed layer. Next, a photosensitive insulating resin film (57) with a thickness of 5 μm, formed in the same manner as the photosensitive insulating resin film (52), was attached so as to expose at least a portion of the first connecting wiring (55c) and a portion of the second connecting wiring (55d). Next, exposure treatment, heat treatment, development treatment, and heat curing treatment were performed in sequence on the attached photosensitive insulating resin film (57). Accordingly, a sample (50) for measurement evaluation shown in FIG. 11(a) and FIG. 11(b) was formed. In this measurement evaluation sample (50), the first wiring (55a) and the first connecting wiring (55c) are connected to each other and covered by a barrier metal film (54, 56). Likewise, the second wiring (55b) and the second connecting wiring (55d) are connected to each other and covered by a barrier metal film (54, 56). Additionally, the first wiring (55a) and the first connecting wiring (55c), and the second wiring (55b) and the second connecting wiring (55d) are insulated from each other by a photosensitive insulating resin film (52, 53, 57).

[0119] To verify the insulation reliability of the aforementioned measurement evaluation sample (50), a Highly Accelerated Stress Test (HAST) described below was performed. In this test, a voltage of 3.3 V was applied to the first connecting wire (55c) and the second connecting wire (55d) under conditions of 85% humidity and 130°C, and the wires were left standing for a predetermined period of time. Accordingly, the change in insulation properties of the first wire (55a) and the second wire (55b) over time was measured. In this test, the resistance value between the first wire (55a) and the second wire (55b) was 1×10⁻⁶ after 200 hours from the start of the test. 6If Ω or greater, evaluate as A, and 1×10⁻⁶ before 200 hours have elapsed from the start of the test 6 If it is less than Ω, it was evaluated as B. The results of the high-acceleration life test of Example 1 are shown in Table 1 below.

[0120] (Example 2)

[0121] A sample (50) for measurement and evaluation was formed in the same manner as in Example 1, except that the line width (L) and space width (S) were set to 5 μm, and the aforementioned high-acceleration life test was performed. The results of the high-acceleration life test of Example 2 are shown in Table 1 below.

[0122] (Example 3)

[0123] A sample (50) for measurement and evaluation was formed in the same manner as in Example 1, except that the line width (L) and space width (S) were set to 2 μm, and the aforementioned high-acceleration life test was performed. The results of the high-acceleration life test of Example 3 are shown in Table 1 below.

[0124] (Example 4)

[0125] A measurement evaluation sample (50) was formed in the same manner as in Example 2, except that the photosensitive insulating resin film (57) was made of a solder resist film (manufactured by Hitachi Kasei Co., Ltd., product name: FZ-2700GA, thickness 30 μm). The aforementioned high-acceleration life test was performed on this measurement evaluation sample (50). The results of the high-acceleration life test of Example 4 are shown in Table 1 below.

[0126] (Example 5)

[0127] A measurement evaluation sample (50) was formed in the same manner as in Example 3, except that the photosensitive insulating resin film (57) was made of a solder resist film (manufactured by Hitachi Kasei Co., Ltd., product name: FZ-2700GA, thickness 30 μm). The aforementioned high-acceleration life test was performed on this measurement evaluation sample (50). The results of the high-acceleration life test of Example 5 are shown in Table 1 below.

[0128] (Comparative Example 1)

[0129] As illustrated in FIG. 12(a) and FIG. 12(b), a measurement evaluation sample (50A) was formed in the same manner as in Example 1, except that a barrier metal film (56) was not formed on the first wiring (55a), the second wiring (55b), the first connecting wiring (55c), and the second connecting wiring (55d). That is, the measurement evaluation sample (50A) was formed such that the first wiring (55a), the second wiring (55b), the first connecting wiring (55c), and the second connecting wiring (55d) were in contact with a photosensitive insulating resin film (57). The aforementioned high-acceleration life test was performed on this measurement evaluation sample (50A). The results of the high-acceleration life test of Comparative Example 1 are shown in Table 1 below.

[0130] (Comparative Example 2)

[0131] A measurement evaluation sample (50A) was formed in the same manner as in Example 2, except that a barrier metal film (56) was not formed on the first wiring (55a), the second wiring (55b), the first connecting wiring (55c), and the second connecting wiring (55d). The aforementioned high-acceleration life test was performed on this measurement evaluation sample (50A). The results of the high-acceleration life test of Comparative Example 2 are shown in Table 1 below.

[0132] (Comparative Example 3)

[0133] A measurement evaluation sample (50A) was formed in the same manner as in Example 3, except that a barrier metal film (56) was not formed on the first wiring (55a), the second wiring (55b), the first connecting wiring (55c), and the second connecting wiring (55d). The aforementioned high-acceleration life test was performed on this measurement evaluation sample (50A). The results of the high-acceleration life test of Comparative Example 3 are shown in Table 1 below.

[0134] (Comparative Example 4)

[0135] A measurement evaluation sample (50A) was formed in the same manner as in Example 4, except that a barrier metal film (56) was not formed on the first wiring (55a), the second wiring (55b), the first connecting wiring (55c), and the second connecting wiring (55d). The aforementioned high-acceleration life test was performed on this measurement evaluation sample (50A). The results of the high-acceleration life test of Comparative Example 4 are shown in Table 1 below.

[0136] (Comparative Example 5)

[0137] A measurement evaluation sample (50A) was formed in the same manner as in Example 5, except that a barrier metal film (56) was not formed on the first wiring (55a), the second wiring (55b), the first connecting wiring (55c), and the second connecting wiring (55d). The aforementioned high-acceleration life test was performed on this measurement evaluation sample (50A). The results of the high-acceleration life test of Comparative Example 5 are shown in Table 1 below.

[0138]

[0139] In Table 1 above, if a barrier metal film (56) is formed, it is indicated as "Y", and if a barrier metal film (56) is not formed, it is indicated as "N". Also, in Table 1 above, if the photosensitive insulating resin film (57) is formed in the same way as the photosensitive insulating resin film (52), it is indicated as "α", and if the photosensitive insulating resin film (57) is formed using a solder resist film, it is indicated as "β". From Table 1, the results of the high-acceleration life tests of Examples 1 to 5 were all rated A, while the results of the high-acceleration life tests of Comparative Examples 1 to 5 were all rated B. From these results, it was found that the insulation reliability of the measurement evaluation sample differed significantly depending on the presence or absence of the barrier metal film (56).

[0140] FIG. 13(a) is a graph showing the results of the high-acceleration life test of Example 2 and Comparative Example 2, and FIG. 13(b) is a graph showing the results of the high-acceleration life test of Example 3 and Comparative Example 3. In FIG. 13(a) and FIG. 13(b), the horizontal axis represents time, and the vertical axis represents the resistance value between the first wiring (55a) and the second wiring (55b). In FIG. 13(a), data 61 is the test result of Example 2, and data 62 is the test result of Comparative Example 2. In FIG. 13(b), data 63 is the test result of Example 3, and data 64 is the test result of Comparative Example 3.

[0141] As shown in FIG. 13(a), in Example 2, even after 300 hours have elapsed from the start of the test, the resistance value between the first wiring (55a) and the second wiring (55b) is 1×10 6 It showed a value greater than Ω. Meanwhile, in Comparative Example 2, the resistance value decreased rapidly at a point of about 20 hours from the start of the test, and 1×10 6It became less than Ω. Likewise, as shown in FIG. 13(b), in Example 3, even after 200 hours have elapsed from the start of the test, the resistance value between the first wiring (55a) and the second wiring (55b) is 1×10 6 While it exhibited an Ω or higher, in Comparative Example 2, the resistance value decreased rapidly at a point several hours from the start of the test, and 1×10 6 It became less than Ω.

[0142] FIGS. 14(a) to 14(c) show the results of analyzing the components of copper, titanium, and nickel in a cross-sectional sample of a measurement evaluation sample (50) after 250 hours of the curing rate life test of Example 3 using TEM (Transmission Electron Microscope) and EDX (Energy Dispersive X-ray Analyzer). FIG. 14(a) shows the analysis result of Cu (copper) in the cross-sectional sample of the measurement evaluation sample (50), FIG. 14(b) shows the analysis result of Ti (titanium) in the cross-sectional sample, and FIG. 14(c) shows the analysis result of Ni (nickel) in the cross-sectional sample. The analysis was performed using a JEM-2100F manufactured by Nihon Denshi Co., Ltd. as the TEM and a JED-2300 manufactured by Nihon Denshi Co., Ltd. as the EDX, with the acceleration voltage set to 200 kV. In Example 3, after the EDX analysis test, no leaching of wiring and barrier metal into the photosensitive insulating resin film was observed. Specifically, the diffusion of copper into the photosensitive insulating resin film constituting the copper layer surrounded by the barrier metal film (54, 56), the diffusion of titanium into the photosensitive insulating resin film constituting the barrier metal film (54), and the diffusion of nickel into the photosensitive insulating resin film constituting the barrier metal film (56) were all not confirmed.

[0143] When the measurement evaluation samples (50A) of Comparative Examples 2 and 3 were visually inspected after the high-acceleration life test, it was confirmed that in Comparative Examples 2 and 3, at least the photosensitive insulating resin film (57) was contaminated by some factor. Meanwhile, when the measurement evaluation samples (50) of Examples 2 and 3 were visually inspected after the high-acceleration life test, no contamination of the photosensitive insulating resin films (52, 53, 57) was confirmed.

[0144] From the above, it is inferred that the rapid decrease in resistance values ​​in Comparative Examples 2 and 3 is due to the metal material within the first wiring (55a) and the second wiring (55b) diffusing into the photosensitive insulating resin film (57), and the first wiring (55a) and the second wiring (55b) being short-circuited through the diffused metal material. On the other hand, in Examples 2 and 3, it is inferred that the diffusion of the metal material within the first wiring (55a) or the second wiring (55b) into the photosensitive insulating resin film (52, 53, 57) is prevented by the barrier metal film (54, 56), and the first wiring (55a) and the second wiring (55b) are not short-circuited. Explanation of the symbols

[0145] 1: Substrate, 2A∼2D: Semiconductor chip, 3A, 3B: Underfill, 4: Insulating material, 10: Organic interposer, 11: Substrate, 12: Organic insulating laminate, 13: Wiring, 13A: Wiring layer, 14: Barrier metal film, 15: Through wiring, 21: First organic insulating layer, 21a: Groove, 21b: Opening, 22: Second organic insulating layer, 31: First barrier metal film, 32: Second barrier metal film, 100: Semiconductor package, L: Line width, S: Space width.

Claims

Claim 1 A substrate for a semiconductor package having an insulating laminate having a first insulating layer, a first wiring disposed within the first insulating layer, a second wiring located on the first wiring, a first barrier conductive film partitioning the first wiring and the first insulating layer, and a second barrier conductive film located between the first wiring and the second wiring, wherein the first wiring is surrounded by the first barrier conductive film and the second barrier conductive film, and the second wiring is in contact with both sides of the first barrier conductive film and the second barrier conductive film. Claim 2 A substrate for a semiconductor package according to claim 1, wherein the first insulating layer has an opening for receiving the first wiring, and the first barrier conductive film is installed between the inner surface of the opening and the first wiring. Claim 3 A substrate for a semiconductor package according to claim 1 or 2, further comprising a through wiring including the first wiring, the second wiring, the first barrier conductive film and the second barrier conductive film, while penetrating the insulating laminate. Claim 4 In claim 1 or 2, the first barrier conductive film comprises at least one of titanium, nickel, palladium, chromium, tantalum, tungsten, and gold, for a substrate for a semiconductor package. Claim 5 In claim 1 or 2, the second barrier conductive film is a plated film, and the substrate for a semiconductor package. Claim 6 In claim 5, the second barrier conductive film is a nickel-plated film or a palladium-plated film, and the substrate for a semiconductor package. Claim 7 A substrate for a semiconductor package according to claim 1 or 2, wherein at least a portion of the second barrier conductive film is located above the first insulating layer. Claim 8 A substrate for a semiconductor package according to claim 1 or 2, wherein the thickness of the second barrier conductive film is 0.001 μm or more and 1 μm or less. Claim 9 A substrate for a semiconductor package comprising an organic interposer, in accordance with claim 1 or 2. Claim 10 In claim 1 or 2, a semiconductor package substrate which is a build-up substrate, a wafer-level package substrate, a coreless substrate, or a substrate on which a semiconductor chip is encapsulated or embedded. Claim 11 A method for manufacturing a substrate for a semiconductor package comprising: a first step of preparing an insulating layer having a plurality of grooves; a second step of forming a first barrier conductive film covering the surface of the insulating layer and the inner surface of the grooves; a third step of forming a wiring layer on the first barrier conductive film to fill the grooves; a fourth step of thinning the wiring layer so as to expose the insulating layer and flattening the surface where the insulating layer and the wiring are combined; and a fifth step of forming a second barrier conductive film covering the exposed portion of the wiring layer remaining within the grooves, wherein the wiring layer remaining within the grooves is surrounded by the first barrier conductive film and the second barrier conductive film. Claim 12 A method for manufacturing a substrate for a semiconductor package according to claim 11, wherein in the third process, the wiring layer is formed by a plating method in which the first barrier conductive film is used as a seed layer. Claim 13 A method for manufacturing a substrate for a semiconductor package, wherein in claim 11 or 12, the second barrier conductive film is formed by a plating method in which the wiring layer is used as a seed layer in the fifth process. Claim 14 delete Claim 15 A method for manufacturing a substrate for a semiconductor package, wherein in claim 11 or 12, the surface of the insulating layer is polished or ground in the fourth process. Claim 16 A method for manufacturing a substrate for a semiconductor package according to claim 11 or 12, wherein at least a portion of the second barrier conductive film is located outside the groove portion.

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