Wiring abnormality detection method and plasma processing apparatus

Abstract

[Assignment] Properly detect wiring abnormalities in the DC power system of a plasma processing device. [Solution] A method for detecting a wiring abnormality in a plasma processing apparatus, wherein the plasma processing apparatus comprises a chamber for performing plasma processing of a substrate inside, a stage having an electrostatic chuck provided inside the chamber and adsorbing and holding the substrate, a DC power supply for controlling plasma generated inside the chamber, and an ammeter for measuring the current flowing through the DC power supply, wherein the DC power supply comprises a DC power supply that applies a DC voltage to the DC power supply, a high-frequency filter for removing high-frequency components from the DC power supply, and a DC voltage application member that is the target of the application of the DC voltage, and the detection method comprises a process of applying a DC voltage by the DC power supply, a process of measuring the current flowing through the circuit constituting the DC power supply, and a process of comparing the measured value of the current with a predetermined threshold value, wherein if the measured value is greater than or equal to the threshold value, it is determined that a wiring abnormality has occurred in the circuit constituting the DC power supply.

Description

Technology Field

[0001] The present disclosure relates to a method for detecting wiring abnormalities and a plasma processing apparatus. Background Technology

[0002] Patent document 1 discloses a method for detecting a disconnection in an electrostatic chuck circuit by applying a higher voltage from a DC power source to the electrostatic chuck when the electrostatic chuck is not holding a substrate than when the substrate is adsorbed. According to the method described in Patent document 1, the current flowing between the DC power source and the electrostatic chuck is measured by applying the voltage, and the disconnection of the electrostatic chuck circuit is detected based on the magnitude thereof. Prior art literature

[0003] [Patent Document 1] Japanese Patent Publication No. 10-308439 The problem to be solved

[0004] The technology according to the present disclosure appropriately detects wiring abnormalities in the DC power system of a plasma processing device. means of solving the problem

[0005] One aspect of the present disclosure is a method for detecting a wiring abnormality in a plasma processing apparatus, wherein the plasma processing apparatus comprises a chamber for performing plasma processing of a substrate inside, a stage having an electrostatic chuck provided inside the chamber and adsorbing and holding the substrate, a DC power supply for controlling plasma generated inside the chamber, and an ammeter for measuring a current flowing through the DC power supply, wherein the DC power supply comprises a DC power supply for applying a DC voltage to the DC power supply, a high-frequency filter for removing high-frequency components from the DC power supply, and a DC voltage application member to which the DC voltage is applied, and the detection method comprises a process of applying a DC voltage by the DC power supply, a process of measuring a current flowing through a circuit constituting the DC power supply, a process of comparing a measured value of the current with a predetermined threshold value, and a process of determining that a wiring abnormality has occurred in the circuit constituting the DC power supply when the measured value is greater than or equal to the threshold value. Effects of the invention

[0006] According to the present disclosure, wiring abnormalities in the DC power system of a plasma processing device can be appropriately detected. Brief explanation of the drawing

[0007] FIG. 1 is a cross-sectional view showing a schematic configuration of a plasma processing device according to the present embodiment. FIG. 2 is an explanatory diagram showing an example of the configuration of a DC power system of a plasma processing device according to the present embodiment. FIG. 3 is an explanatory diagram showing another configuration example of a DC power system of a plasma processing device according to the present embodiment. Figure 4 is an explanatory diagram schematically showing the occurrence of wiring abnormalities in a DC power system. FIG. 5 is a flowchart showing the main process of the wiring abnormality detection method according to the present embodiment. Figure 6 is a graph showing an example of VI characteristics. FIG. 7 is a flowchart showing the main process of a wiring abnormality detection method according to a second embodiment. Figure 8 is a graph showing an example of VI characteristics. Specific details for implementing the invention

[0008] In the manufacturing process of a semiconductor device, a processing gas is supplied to a semiconductor wafer (hereinafter referred to simply as "wafer"), and various plasma treatments such as etching, film deposition, and diffusion are performed on the wafer. In recent years, safety inspections for these plasma treatments have become stricter due to the influence of increased power and voltage, and in particular, an interlock mechanism is required to prohibit access to the active part while the device is active, or to stop the power output when access is detected.

[0009] Conventionally, as the interlock mechanism described above, it has been proposed to provide, for example, an interlock key on the connector of the transmission path of a plasma processing device, or to place an interlock cover on the connector so that the connector cannot be attached or detached unless the cover is removed. In addition, for example, it has been proposed to provide the interlock cover at a position where a switch linked to the power output operation of the plasma processing device is pressed, so that the power output is automatically cut off if the cover is removed while the device is powered on.

[0010] However, in these conventional interlock mechanisms, it was possible to keep the interlock mechanism active even when, for example, wiring was disconnected or broken (hereinafter, these disconnections and broken wires are collectively referred to as "wiring abnormalities"). In other words, since there were cases where the interlock mechanism could not detect the abnormality and could still output power even if a wiring abnormality occurred, there was a risk of abnormal discharge or electric shock to the operator. Particularly in plasma processing devices, since the plasma potential is directly observed in each wire in the DC (Direct Current) power system (e.g., upper electrode circuit or edge ring circuit) used for plasma control, there is a high risk of abnormal discharge during plasma generation if a wiring abnormality occurs.

[0011] Considering these circumstances, it is required that the plasma processing apparatus properly detect wiring abnormalities in the DC power system. The aforementioned Patent Document 1 discloses a method for detecting open circuits in an electrostatic chuck circuit. However, while Patent Document 1 describes open circuit detection in an electrostatic chuck circuit for holding a wafer, it does not describe open circuit detection in a DC power system for performing plasma control as described above.

[0012] The technology according to the present disclosure appropriately detects wiring abnormalities in the DC power system of a plasma processing apparatus, particularly in the upper electrode circuit or edge ring circuit. Hereinafter, a plasma processing apparatus as a substrate processing system and a wafer processing method as a substrate processing method according to the present embodiment will be described with reference to the drawings. In addition, in the present specification and drawings, redundant descriptions are omitted for elements having substantially the same functional configuration by assigning the same reference numerals.

[0013] Plasma Treatment Device

[0014] First, a plasma processing apparatus according to the present embodiment will be described. FIG. 1 is a cross-sectional view showing a schematic configuration of a plasma processing apparatus (1). FIG. 2 is an explanatory diagram showing an example of a power system of a plasma processing apparatus (1). In the plasma processing apparatus (1), plasma processing such as etching, film deposition, and diffusion is performed on a wafer W as a substrate.

[0015] As shown in FIG. 1, the plasma processing device (1) has a chamber (10) that is approximately cylindrical in shape. The chamber (10) defines a processing space S in which plasma is generated. The chamber (10) is made of, for example, aluminum. The chamber (10) is connected to a ground potential.

[0016] Inside the chamber (10), a stage (11) for mounting a wafer W is accommodated. The stage (11) has a lower electrode (12), an electrostatic chuck (13), and an edge ring (14). Additionally, on the lower side of the lower electrode (12), an electrode plate (not shown), for example made of aluminum, may be provided.

[0017] The lower electrode (12) is composed of a conductive metal, such as aluminum, and has a roughly disc shape.

[0018] A refrigerant flow path (15a) is formed inside the lower electrode (12). Refrigerant is supplied to the refrigerant flow path (15a) through a refrigerant inlet pipe (15b) from a chiller unit (not shown) provided outside the chamber (10). The refrigerant supplied to the refrigerant flow path (15a) is returned to the chiller unit through a refrigerant outlet flow path (15c). By circulating a refrigerant, such as cooling water, through the refrigerant flow path (15a), the electrostatic chuck (13), the edge ring (14), and the wafer W can be cooled to a desired temperature.

[0019] The electrostatic chuck (13) is provided on the lower electrode (12). The electrostatic chuck (13) is a member configured to hold both the wafer W and the edge ring (14) by electrostatic force. The electrostatic chuck (13) has a central upper surface that is higher than the periphery upper surface. The central upper surface of the electrostatic chuck (13) becomes a wafer mounting surface on which the wafer W is mounted, and the periphery upper surface of the electrostatic chuck (13) becomes an edge ring mounting surface on which the edge ring (14) is mounted.

[0020] In the central part of the interior of the electrostatic chuck (13), a first electrode (16a) is provided for adsorbing and holding a wafer W. In the peripheral part of the interior of the electrostatic chuck (13), a second electrode (16b) is provided for adsorbing and holding an edge ring (14). The electrostatic chuck (13) has a configuration in which electrodes (16a) and (16b) are sandwiched between insulating materials made of insulating material.

[0021] A DC voltage from a DC power source (not shown) is applied to the first electrode (16a). Due to the electrostatic force generated by this, a wafer W is adsorbed and held on the upper surface of the central part of the electrostatic chuck (13). Likewise, a DC voltage from a DC power source (not shown) is applied to the second electrode (16b). Due to the electrostatic force generated by this, an edge ring (14) is adsorbed and held on the upper surface of the peripheral part of the electrostatic chuck (13).

[0022] In addition, in this embodiment, the central part of the electrostatic chuck (13) where the first electrode (16a) is provided and the peripheral part where the second electrode (16b) is provided are integrally formed, but these central part and peripheral part may be separate.

[0023] The edge ring (14) as a DC voltage application member is a ring-shaped member arranged to surround a wafer W mounted on the upper surface of the central part of the electrostatic chuck (13), and a DC voltage from the DC power source (60) described later is applied. The edge ring (14) is provided to improve the uniformity of the plasma treatment. For this reason, the edge ring (14) is composed of a material appropriately selected according to the plasma treatment, and may be composed of, for example, Si or SiC.

[0024] The stage (11) configured as described above is fastened to a roughly cylindrical support member (17) provided at the bottom of the chamber (10). The support member (17) is made of an insulator, for example, ceramic or quartz.

[0025] Additionally, although omitted, the stage (11) may include a temperature control module configured to control at least one of the electrostatic chuck (13), edge ring (14), and wafer W to a desired temperature. The temperature control module may include a heater, a flow path, or a combination thereof. A temperature control fluid, such as a refrigerant or a heating gas, flows through the flow path.

[0026] Above the stage (11), a shower head (20) is provided so as to face the stage (11). The shower head (20) has an electrode plate (21) provided facing the processing space S, and an electrode support (22) provided above the electrode plate (21). The electrode plate (21) functions as a pair of upper electrodes with the lower electrode (12). When the first high-frequency power source (50) is electrically connected to the lower electrode (12) as described later, the shower head (20) is connected to the ground potential. Additionally, the shower head (20) is supported on the upper surface (ceiling surface) of the chamber (10) through an insulating shielding member (23).

[0027] A plurality of gas outlets (21a) are formed in the electrode plate (21) to supply processing gas sent from the gas diffusion chamber (22a) described later to the processing space S. The electrode plate (21) is composed of, for example, a conductor or semiconductor having a low electrical resistivity that generates less Joule heat. In addition, a DC voltage from the second DC power source (70) described later is applied to the electrode plate (21).

[0028] The electrode support (22) supports the electrode plate (21) in a detachable manner. The electrode support (22) has a configuration in which a plasma-resistant film is formed on the surface of a conductive material, such as aluminum. This film may be a ceramic film formed by an anodic oxidation treatment, or a film formed of yttrium oxide. A gas diffusion chamber (22a) is formed inside the electrode support (22). A plurality of gas flow holes (22b) communicating with a gas outlet (21a) are formed from the gas diffusion chamber (22a). Additionally, a gas introduction hole (22c) connected to a gas supply pipe (33) described later is formed in the gas diffusion chamber (22a).

[0029] Additionally, a gas supply source group (30) that supplies processing gas to a gas diffusion chamber (22a) is connected to the electrode support (22) through a flow control device group (31), a valve group (32), a gas supply pipe (33), and a gas introduction hole (22c).

[0030] The gas supply source group (30) has multiple types of gas supply sources required for plasma treatment. The flow control device group (31) includes multiple flow controllers, and the valve group (32) includes multiple valves. Each of the multiple flow controllers of the flow control device group (31) is a mass flow controller or a pressure-controlled flow controller. In the plasma treatment device (1), treatment gas from one or more gas supply sources selected from the gas supply source group (30) is supplied to the gas diffusion chamber (22a) through the flow control device group (31), the valve group (32), the gas supply pipe (33), and the gas introduction hole (22c). Then, the treatment gas supplied to the gas diffusion chamber (22a) is supplied in a shower shape within the treatment space S through the gas flow hole (22b) and the gas outlet (21a).

[0031] As a bottom portion of the chamber (10), a baffle plate (40) is provided between the inner wall of the chamber (10) and the support member (17). The baffle plate (40) is constructed, for example, by coating an aluminum material with a ceramic such as yttrium oxide. A plurality of through holes are formed in the baffle plate (40). The processing space S is connected to an exhaust port (41) through the baffle plate (40). An exhaust device (42), for example, a vacuum pump, is connected to the exhaust port (41), and the processing space S is configured to be pressure-reduced by the exhaust device (42).

[0032] Additionally, an inlet / outlet port (43) for wafer W is formed on the side wall of the chamber (10), and the inlet / outlet port (43) can be opened and closed by a gate valve (44).

[0033] As shown in FIGS. 1 and 2, the plasma processing device (1) further has a first high-frequency power supply (50), a second high-frequency power supply (51), and a matching device (52). The first high-frequency power supply (50) and the second high-frequency power supply (51) are connected to a lower electrode (12) through the matching device (52).

[0034] The first high-frequency power source (50) is a power source that generates high-frequency power for plasma generation. From the first high-frequency power source (50), high-frequency power HF, which is 40 MHz in frequency, is supplied to the lower electrode (12). The first high-frequency power source (50) is connected to the lower electrode (12) through the first matching circuit (53) of the matching device (52). The first matching circuit (53) is a circuit for matching the output impedance of the first high-frequency power source (50) with the input impedance of the load side (lower electrode (12) side). Additionally, the first high-frequency power source (50) does not have to be electrically connected to the lower electrode (12), and may be connected to the upper electrode, the shower head (20), through the first matching circuit (53).

[0035] The second high-frequency power supply (51) generates high-frequency power (high-frequency bias power) LF for introducing ions into the wafer W and supplies the said high-frequency power LF to the lower electrode (12). The frequency of the high-frequency power LF may be within the range of 400 kHz to 13.56 MHz, and in one example, it is 400 kHz. The second high-frequency power supply (51) is connected to the lower electrode (12) through the second matching circuit (54) of the matching device (52). The second matching circuit (54) is a circuit for matching the output impedance of the second high-frequency power supply (51) with the input impedance of the load side (lower electrode (12) side). In addition, a DC (Direct Current) pulse generator may be used instead of the second high-frequency power supply (51).

[0036] The plasma processing device (1) further has a DC power supply (60), a switching unit (61), and an RF filter (62). The DC power supply (60) is electrically connected to the edge ring (14) through the switching unit (61) and the RF filter (62). In addition, in the following description, the DC power supply (60), the switching unit (61), the RF filter (62), and the edge ring (14) are collectively referred to as the "edge ring circuit" as the DC power supply system for detecting wiring abnormalities according to the present embodiment. Furthermore, the upstream side of the current flow direction in the edge ring circuit, i.e., the DC power supply (60) side, may be referred to simply as the "upstream side," and the downstream side of the current flow direction, i.e., the edge ring (14) side, may be referred to simply as the "downstream side."

[0037] The DC power supply (60) is a power supply that applies a negative DC voltage for plasma control to the edge ring (14). The DC power supply (60) is a variable DC power supply and can adjust the high and low of the DC voltage. In addition, the DC power supply (60) is configured to switch the voltage waveform applied to the edge ring (14) between a pulse wave and a continuous wave (CW).

[0038] The switching unit (61) is configured to stop the application of DC voltage from the DC power source (60) to the edge ring (14). Additionally, the circuit configuration of the switching unit (61) can be arbitrarily designed by a person skilled in the art.

[0039] The RF filter (62) is provided to protect the DC power supply (60) and has an HF filter (63) and an LF filter (64) for reducing or blocking high frequencies. The HF filter (63) reduces or blocks high frequencies of 40 MHz from, for example, the first high frequency power supply (50). The LF filter (64) reduces or blocks high frequencies of 400 kHz from, for example, the second high frequency power supply (51).

[0040] In one example, the LF filter (64) is configured to have a variable impedance. That is, the impedance is made variable by making some of the components of the LF filter (64) variable components. The variable components may be, for example, either a coil or a capacitor. Furthermore, the same function can be achieved with any variable impedance component, such as a diode, not limited to a coil or a capacitor. Also, the component itself does not need to be variable; the impedance may be varied by switching a combination of fixed-value components using a switching circuit. Additionally, the circuit configurations of this LF filter (64) and the HF filter (63) can each be arbitrarily designed by a person skilled in the art.

[0041] The plasma processing device (1) further has a measuring device (not shown) for measuring the self-bias voltage of the edge ring (14) (or the self-bias voltage of the lower electrode (12) or the wafer W). Additionally, the configuration of the measuring device can be arbitrarily designed by a person skilled in the art.

[0042] In addition, an ammeter A is provided in the edge ring circuit configured in this manner to measure the current flowing through the edge ring circuit. The installation location of the ammeter A is not particularly limited, and, for example, as shown in FIGS. 1 and 2, it may be provided inside the DC power source (60), or it may be provided outside immediately after the downstream side of the DC power source (60).

[0043] Additionally, the plasma processing device (1) further has a second DC power supply (70), a second switching unit (71), and a second RF filter (72). The second DC power supply (70) is electrically connected to the electrode plate (21) through the second switching unit (71) and the second RF filter (72). Furthermore, in the following description, the second DC power supply (70), the second switching unit (71), the second RF filter (72), and the electrode plate (21) may be collectively referred to as the "upper electrode circuit" as a DC power system for detecting wiring abnormalities according to the present embodiment.

[0044] The second DC power source (70) is a power source that applies a negative DC voltage for plasma control to the electrode plate (21). The second DC power source (70) is a variable DC power source and can adjust the high and low of the DC voltage. In addition, the second DC power source (70) is configured to switch the voltage waveform applied to the electrode plate (21) between a pulse wave and a continuous wave.

[0045] The second switching unit (71) is configured to stop the application of a DC voltage from the second DC power source (70) to the electrode plate (21). Additionally, the circuit configuration of the second switching unit (71) can be arbitrarily designed by a person skilled in the art.

[0046] The second RF filter (72) is provided to protect the second DC power supply (70) and has an HF filter (73) and an LF filter (74) for reducing or blocking high frequencies. The HF filter (63) reduces or blocks high frequencies of 40 MHz from, for example, the first high frequency power supply (50). The LF filter (74) reduces or blocks high frequencies of 400 kHz from, for example, the second high frequency power supply (51). Additionally, the circuit configurations of the HF filter (73) and the LF filter (74) can each be arbitrarily designed by a person skilled in the art.

[0047] In addition, an ammeter A is provided in the upper electrode circuit configured in this manner to measure the current flowing through the upper electrode circuit. The installation location of the ammeter A is not particularly limited, and, for example, as shown in FIGS. 1 and 2, it may be provided inside the second DC power source (70), or it may be provided outside immediately after the downstream side of the second DC power source (70).

[0048] The above plasma processing device (1) is provided with a control unit (100). The control unit (100) is a computer equipped with, for example, a CPU or memory, and has a program storage unit (not shown). A program for controlling plasma processing in the plasma processing device (1) is stored in the program storage unit. In addition, the program may be recorded on a computer-readable storage medium and installed in the control unit (100) from said storage medium.

[0049] Although various exemplary embodiments have been described above, various additions, omissions, substitutions, and changes may be made without being limited to the exemplary embodiments described above. In addition, it is possible to form other embodiments by combining elements from other embodiments.

[0050] For example, in the above embodiment, the edge ring circuit is directly connected to the edge ring (14), but as shown in FIG. 3, the edge ring circuit may be connected to the edge ring (14) through the lower electrode (12). In this case, the DC power supply for plasma control is applied to the edge ring (14) through the lower electrode (12).

[0051] <Method for Detecting Wiring Anomalies>

[0052] Next, a method for detecting wiring abnormalities in the upper electrode circuit and edge ring circuit in the plasma processing device (1) configured as described above will be explained. Furthermore, since the method for detecting wiring abnormalities in the upper electrode circuit and the edge ring circuit is the same for each, the method for detecting wiring abnormalities in the edge ring circuit will be explained below as an example.

[0053] FIG. 4 is an explanatory diagram schematically illustrating a wiring abnormality pattern of an edge ring circuit, showing (a) a normal connection state and (b) to (d) states in which a wiring abnormality occurs. In the wiring abnormality detection according to the present embodiment, the wiring abnormality of the edge ring circuit is detected based on a change in circuit constants according to the connection state of each element constituting the edge ring circuit, as described below, more specifically, a change in capacitance according to the connection state. In addition, in the edge ring circuit shown in FIG. 4, the influence on the circuit constants during a wiring abnormality is small enough to be negligible, so the illustration of the switching unit (61) is omitted.

[0054] As shown in FIG. 4(a), the edge ring circuit typically has a configuration in which a DC power source (60), an LF filter (64), an HF filter (63), and an edge ring (14) (chamber (10)) are electrically connected to each other through wiring (e.g., coaxial cable). In the edge ring circuit configured in this way, depending on the change in circuit constants in the event of a wiring abnormality, (b) a wiring abnormality in the wiring connecting the LF filter (64) and the HF filter (63), (c) a wiring abnormality on the upstream side of the LF filter (64), and (d) a wiring abnormality immediately after the downstream side of the DC power source (60) are each detected and distinguished from the normal connection state shown in FIG. 4(a).

[0055] In addition, in the case where a wiring abnormality occurs in the wiring connecting the HF filter (63) and the edge ring (14) (chamber (10)), since the amount of change in the circuit constant from the normal connection state shown in FIG. 4(a) is almost the same as the wiring abnormality shown in FIG. 4(b), detection is performed under the same conditions as the wiring abnormality shown in FIG. 4(b).

[0056] FIG. 5 is a flowchart showing the main process of detecting wiring abnormalities in an edge ring circuit according to the present embodiment. In addition, (a) to (d) shown in the flowchart of FIG. 5 correspond to (a) normal connection state and (b) to (d) states where wiring abnormalities are occurring, respectively, as shown in FIG. 4.

[0057] As shown in FIG. 5, for detecting wiring abnormalities in the edge ring circuit, first, when the wafer W is not introduced into the plasma processing device (1), a DC voltage for short-circuit detection (hereinafter referred to as "short-circuit detection voltage V1") is applied to the edge ring (14) from a DC power source (60) (step S1 of FIG. 5). As for the short-circuit detection voltage V1, a voltage lower than the voltage applied to the edge ring (14) when performing plasma processing on the wafer W (e.g., 120 V) can be applied under pulse conditions with a frequency of 20 kHz and a duty ratio of 60%. In addition, the waveform of the short-circuit detection voltage V1 is not limited to a pulse wave and may be applied as a continuous wave.

[0058] Next, the current flowing through the edge ring circuit is measured by ammeter A by applying the short-circuit detection voltage V1 in step S1, and whether the edge ring circuit is short-circuited is detected by comparing the measured current value (hereinafter referred to as "current value I1") with a predetermined threshold value B1. In addition, the threshold value B1 used for such short-circuit detection can be determined in advance, for example, by measuring the current value flowing when the short-circuit detection voltage V1 is applied to the edge ring circuit prior to wiring abnormality detection.

[0059] Specifically, for example, if the current value I1 is not measured, that is, if the measured current value I1 is 0A, it is determined that the wiring is not connected to the DC power source (60) as shown in FIG. 4(d), or that a disconnection has occurred immediately after the downstream side of the DC power source (60) (step S2-1 of FIG. 5). In this case, for example, after an alarm is given to the edge ring circuit indicating that there is a wiring abnormality (d), the application of the short-circuit detection voltage V1 from the DC power source (60) is stopped.

[0060] For example, if the measured current value I1 is greater than or equal to the threshold value B1, it is determined that the edge ring circuit is short-circuited and an excess current is flowing (step S2-2 of FIG. 5). In this case, for example, after an alarm is given indicating that the edge ring circuit is short-circuited, the application of the short-circuit detection voltage V1 from the DC power source (60) is stopped.

[0061] If the measured current value I1 is less than the threshold value B1, it is determined that the edge ring circuit is not short-circuited and that the wiring is connected to at least the DC power source (60), and a short-circuit detection pass is notified (step S2-3 of FIG. 5).

[0062] Next, after stopping the application of the short-circuit detection voltage V1 from the DC power source (60), a DC pulse voltage for open circuit detection (hereinafter referred to as "open circuit detection voltage V2") is applied from the DC power source (60) to the edge ring (14) (step S3 of FIG. 5). As for the open circuit detection voltage V2, any voltage described later is applied, for example, under pulse conditions of frequency 20 kHz and duty ratio 60%.

[0063] Next, the current flowing through the edge ring circuit is measured by ammeter A by applying the voltage V2 for open circuit detection in step S3, and whether an open circuit has occurred in the edge ring circuit is detected by comparing the measured current value (hereinafter referred to as "current value I2") with a predetermined threshold value B2. At this time, the presence or absence of a booting failure in the edge ring circuit is detected by performing the comparison between the current value I2 and the threshold value B2 within a predetermined time t (e.g., 3 seconds in the example of FIG. 5).

[0064] Specifically, for example, when the current value I2 reaches the threshold value B2, that is, when current flows to the edge ring (14) (chamber (10)), but it takes more than 3 seconds to reach the threshold value B2, it is determined that a starting failure has occurred in the edge ring circuit (step S4-1 of FIG. 5). That is, it is determined that although the wiring is connected to the edge ring (14), the current is not flowing properly due to, for example, a connection failure. In this case, for example, after an alarm is given indicating that a starting failure has occurred in the edge ring circuit, the application of the open circuit detection voltage V2 from the DC power source (60) is stopped.

[0065] For example, if the measured current value I2 is less than the threshold value B2, it is determined that a wiring abnormality (a disconnection or a disconnection of each element) has occurred in the edge ring circuit (step S4-2 of FIG. 5). In this case, for example, an alarm is given indicating that a wiring abnormality has occurred in the edge ring circuit, or more preferably, where in the edge ring circuit the wiring abnormality is occurring, and then the application of the disconnection detection voltage V2 from the DC power source (60) is stopped.

[0066] The detection of wiring abnormalities in the edge ring circuit in step S4-2 is explained in more detail. FIG. 6 is a graph showing an example of VI characteristics representing the relationship between voltage V2 and current value I2 for open circuit detection. In addition, (a) to (d) shown in the legend of FIG. 6 correspond to (a) normal connection state and (b) to (d) states where wiring abnormalities have occurred, respectively, as shown in FIG. 4.

[0067] As shown in FIG. 6(a), when no wiring abnormalities occur in the edge ring circuit, current flows appropriately through the entire edge ring circuit, that is, from the DC power source (60) to the edge ring (14) (chamber (10)), by applying the open circuit detection voltage V2. At this time, the current value I2 measured by ammeter A is determined according to the open circuit detection voltage V2, as shown in the VI characteristic of FIG. 6(a).

[0068] Meanwhile, as shown in FIGS. 6(b) to (d), when a wiring fault occurs in the edge ring circuit, if a voltage V2 for detecting a wire break is applied, current flows from the DC power source (60) to the location of the wiring fault. In other words, since no current flows downstream from the location of the wiring fault in the edge ring circuit, the circuit constant changes (the capacitance of the element located downstream from the location of the wiring fault decreases), and the measured current value I2 decreases compared to (a) the normal connection state. Thus, as shown in FIG. 6, based on the VI characteristics acquired in advance, a threshold value B2 is set in advance between the current value I(a) as the first VI characteristic measured in normal conditions and the current value I(b) as the second VI characteristic measured in the case of a wiring fault. By doing this, by comparing the current value I2 actually measured by ammeter A with the threshold value B2, it is possible to detect whether there is a wiring abnormality in the edge ring circuit.

[0069] Also, as described above, if a wiring fault occurs in the edge ring circuit, current does not flow downstream of the wiring fault location, so the measured current value I2 decreases according to the capacitance of the element located downstream of the wiring fault location. From this, based on the current value I2 measured by ammeter A, it is possible to detect which of the wiring fault location has occurred in (b) the wiring connecting the LF filter (64) and the HF filter (63), (c) the wiring on the upstream side of the LF filter (64), or (d) the wiring immediately downstream of the DC power source (60).

[0070] In addition, as shown in FIG. 6, the voltage value of the open-circuit detection voltage V2 applied to the edge ring circuit can be determined arbitrarily. At this time, by increasing the applied open-circuit detection voltage V2, the difference between the settable range of the threshold value B2, that is, the current value I(a) and the current value I(b), can be increased, and the wiring abnormality can be detected more appropriately by distinguishing between (a) normal connection state and (b) to (d) wiring abnormalities. On the other hand, by decreasing the applied open-circuit detection voltage V2, the effect on the electrostatic chuck (13) caused by the application of the open-circuit detection voltage V2 and the generation of residual charge as described in Patent Document 1 can be reduced. Taking these circumstances into account, the voltage value of the voltage V2 for detecting a broken wire in this embodiment is preferably lower than the voltage applied to the edge ring (14) during a normal plasma processing process, and also a voltage value (e.g., 300V to 500V) that allows the threshold value B2 to be appropriately set.

[0071] Returning to the explanation of FIG. 5. If the measured current value I2 is greater than or equal to the threshold value B2, and the time taken to reach the threshold value B2 is within 3 seconds, it is determined that there is no wiring abnormality in the edge ring circuit, and a wire break detection pass is notified (step S4-3 of FIG. 5). Then, when it is determined that there is no wiring abnormality in the edge ring circuit, the application of the wire break detection voltage V2 from the DC power source (60) is stopped, and a series of wiring abnormality detections are completed.

[0072] According to the wiring fault detection method of the present embodiment, by applying a voltage V2 for open circuit detection to the edge ring circuit, the current flowing is measured by an ammeter A, and by comparing the measured current value I2 with a predetermined threshold value B2, wiring faults in the edge ring circuit, such as unconnected wiring or open circuits, can be detected.

[0073] Also, at this time, by observing the reduction amount of the measured current value I2 from the current value I(a) measured during normal wiring connection, the capacitance of the part where current flows can be predicted by applying the open circuit detection voltage V2, that is, the location of the wiring abnormality can be identified.

[0074] In addition, according to the present embodiment, various wiring abnormalities in the edge ring circuit can be detected simply by applying a short-circuit detection voltage V1 and a single-circuit detection voltage V2 from a DC power source (60) connected to the edge ring circuit. That is, since various wiring abnormalities can be detected using the existing interlock mechanism without providing a new interlock mechanism for the plasma processing device (1), it is easy to apply to the existing plasma processing device (1).

[0075] In addition, according to the present embodiment, the voltage V2 for open circuit detection is lower than the voltage applied to the edge ring (14) during a normal plasma processing process, and a voltage value (e.g., 300V to 500V) that allows the threshold value B2 to be appropriately set is applied under pulse conditions, for example, with a frequency of 20kHz and a duty ratio of 60%. In addition, the pulse conditions of the voltage V2 for open circuit detection are not limited to this, and for example, the frequency is preferably determined between 0.1kHz and 100kHz, preferably between 1kHz and 50kHz, and the duty ratio between 10% and 90%.

[0076] Here, when wiring abnormality detection is performed by applying a voltage V2 for open circuit detection to the edge ring circuit as a continuous wave rather than a pulse wave, current does not flow in the circuit at a low voltage (e.g., 300V to 500V) as shown in the example above, and the current value I2 cannot be measured. That is, as shown in Patent Document 1, in order to measure the current value I2 in the edge ring circuit using a continuous wave, it is necessary to apply a higher voltage than during normal operation, and in such a case, there is a concern about abnormal discharge in the current application path or the occurrence of abnormal discharge between the electrostatic chuck (13) and the edge ring (14).

[0077] In this embodiment, a voltage V2 for detecting open circuits is applied to the edge ring circuit by means of a pulse wave containing a high-frequency component, unlike a continuous wave. By doing so, a sufficient amount of current capable of detection can be flowed through the circuit even at a low voltage (e.g., 300V to 500V) as shown in the example above, that is, it becomes possible to detect wiring abnormalities. As a result, compared to the case where a continuous wave is used, a threshold value for detecting the current value I2 can be appropriately set to properly detect wiring abnormalities, and the occurrence of abnormal discharge can be suppressed.

[0078] In addition, according to the present embodiment, short-circuit detection of the edge ring circuit is performed by applying a short-circuit detection voltage V1, which is lower than the open-circuit detection voltage V2 described above, prior to the application of the open-circuit detection voltage V2. If the open-circuit detection voltage V2 is applied while the edge ring circuit is short-circuited, there is a risk that an abnormal discharge may occur in the edge ring circuit due to the application of the open-circuit detection voltage V2. In this regard, in the present embodiment, since short-circuit detection at a low voltage is performed in advance in this manner, the risk of an abnormal discharge occurring due to the application of the open-circuit detection voltage V2 is reduced.

[0079] In addition, in the wiring abnormality detection according to the present embodiment, short-circuit detection is performed by applying a short-circuit detection voltage V1 prior to applying a voltage V2 for open-circuit detection; however, for example, when the voltage V2 for open-circuit detection is applied at a voltage with a low risk of abnormal discharge, or when the short-circuit detection of the edge ring circuit has already been completed, the short-circuit detection process (steps S1 and S2 of FIG. 5) may be appropriately omitted.

[0080] In addition, as described above, in the detection of wiring abnormalities according to the present embodiment, wiring abnormalities of the edge ring circuit are detected based on changes in circuit constants according to the connection state of each element constituting the edge ring circuit, more specifically, changes in capacitance according to the connection state. Therefore, if the difference between the current value I(a) measured in the normal connection state (a) shown in FIG. 6 and the current value I(b) measured when a wiring abnormality occurs (b) becomes small due to, for example, changes in device characteristics, etc., there is a risk that the threshold value B2 cannot be set appropriately and wiring abnormalities cannot be detected appropriately. More specifically, if the difference in capacitance between the chamber (10) and the edge ring circuit becomes small, such as when the capacitance of the chamber (10) is small or when the capacitance of the RF filter (62) is large, there is a risk that the threshold value B2 cannot be set appropriately and the (a) normal connection state and (b) the occurrence of wiring abnormalities cannot be distinguished.

[0081] <Detection of wiring abnormalities according to the second embodiment>

[0082] Next, we will explain the detection of wiring abnormalities according to the second embodiment in the case where the difference in capacitance between the chamber (10) and the edge ring circuit is small. FIG. 7 is a flowchart showing the main process of detecting wiring abnormalities in the edge ring circuit according to the second embodiment. (a) to (d) shown in the flowchart of FIG. 7 correspond to (a) the normal connection state and (b) to (d) the state in which wiring abnormalities occur, respectively, as shown in FIG. 4. In addition, in the following description, redundant explanations may be omitted for processes such as the detection of wiring abnormalities according to the first embodiment shown in FIG. 5.

[0083] As shown in FIG. 7, in the detection of wiring abnormalities of an edge ring circuit according to the second embodiment, first, a short-circuit detection voltage V1 is applied to the edge ring (14) from a DC power source (60) while the wafer W is not introduced into the plasma processing device (1) (step P1 of FIG. 7). The conditions for applying the short-circuit detection voltage V1 to the edge ring circuit are the same as those for the detection of wiring abnormalities according to the first embodiment.

[0084] Next, the current flowing through the edge ring circuit is measured by ammeter A by applying the short-circuit detection voltage V1 in step P1, and whether the edge ring circuit is short-circuited is detected by comparing the measured current value I1 with a predetermined threshold value B1 (step P2 of FIG. 7).

[0085] The short-circuit detection method of the edge ring circuit according to the present embodiment is the same as the short-circuit detection method of the edge ring circuit according to the first embodiment. That is, for example, if the current value I1 is not measured, it is determined that the wiring is not connected to the DC power source (60) or that an open circuit has occurred immediately after the downstream side of the DC power source (60) (Step P2-1 of FIG. 7). Also, for example, if the measured current value I1 is greater than or equal to the threshold value B1, it is determined that the edge ring circuit is short-circuited and an excess current is flowing (Step P2-2 of FIG. 7).

[0086] If the measured current value I1 is less than the threshold value B1, it is determined that the edge ring circuit is not short-circuited and that the wiring is connected to at least the DC power source (60), and a short-circuit detection pass is notified (step P2-3 of FIG. 7).

[0087] Next, after stopping the application of the short-circuit detection voltage V1 from the DC power source (60), plasma is generated inside the chamber (10) (step P3 of FIG. 7). Specifically, first, a processing gas is supplied from the gas supply source group (30) to the processing space S through the shower head (20). Then, high-frequency power HF for plasma generation is supplied to the lower electrode (12) by the first high-frequency power source (50), and the processing gas is excited to generate plasma.

[0088] In addition, the generation of plasma in step P3 is performed under conditions where the risk of abnormal discharge or the like is low due to the generation of plasma, even if there is a wiring abnormality in the edge ring circuit. As for such conditions, for example, it is preferable to have an O2 gas flow rate of 800 sccm, an internal pressure of the chamber (10) of 100 mTorr or more and 1000 mTorr or less, an applied power of high-frequency power HF of 500 W or less as a continuous wave, and Vdc of less than 100 V. Also, it is preferable that the time for generating plasma is, for example, within 5 seconds.

[0089] In addition, when generating plasma, the lower limit of the internal pressure of the chamber (10) can be lowered further under conditions where a wafer W is introduced into the chamber (10). That is, under conditions where a wafer W is not introduced, it is preferable that the internal pressure of the chamber (10) be 100 mTorr or higher as described above, but for example, when a wiring abnormality detection is performed while a wafer W is introduced into the chamber (10), the internal pressure of the chamber (10) can be controlled to 5 mTorr or higher.

[0090] When plasma is generated inside the chamber (10), next, a voltage V3 for open circuit detection is applied to the edge ring (14) from a DC power source (60) (step P4 of FIG. 7). As for the open circuit detection voltage V3, any voltage described later is applied in any application method (applied waveform: pulse wave or continuous wave). Also, when the open circuit detection voltage V3 is applied as a pulse wave, the pulse conditions can be, for example, a frequency of 20 kHz and a duty ratio of 60%.

[0091] Next, the current flowing through the edge ring circuit is measured by ammeter A by applying the voltage V3 for open circuit detection in step P4, and whether an open circuit has occurred in the edge ring circuit is detected by comparing the measured current value (hereinafter referred to as "current value I3") with a predetermined threshold value B3. At this time, the presence or absence of a starting failure in the edge ring circuit is detected by performing the comparison between the current value I3 and the threshold value B3 within a predetermined time t (e.g., 3 seconds in the example of FIG. 7).

[0092] The short-circuit detection method for an edge ring circuit according to the present embodiment is the same as the short-circuit detection method for an edge ring circuit according to the first embodiment. That is, for example, if a current value I3 reaches a threshold value B3 but requires a time of 3 seconds or more to reach the threshold value B3, it is determined that a starting failure has occurred in the edge ring circuit (Step S5-1 of FIG. 7). Also, for example, if the measured current value I3 is less than the threshold value B3, it is determined that a wiring abnormality has occurred in the edge ring circuit (Step P5-2 of FIG. 7).

[0093] The detection of wiring abnormalities in the edge ring circuit in step P5-2 will be explained in more detail. FIG. 8 is a graph showing an example of VI characteristics representing the relationship between the voltage V3 and the current value I3 for open circuit detection. In addition, (a) and (b) shown in the legend of FIG. 8 correspond to (a) a normal connection state and (b) a state where wiring abnormalities have occurred, respectively, as shown in FIG. 4.

[0094] As shown in FIG. 8(a), when there is no wiring abnormality in the edge ring circuit, current flows appropriately through the entire edge ring circuit, that is, from the DC power source (60) to the edge ring (14), by applying a voltage V3 for open circuit detection. Here, the edge ring (14) is positioned adjacent to a processing space S partitioned inside the chamber (10). Therefore, in the plasma processing device (1) according to the present embodiment, the DC power source (60) and the plasma generated inside the chamber (10) are connected on an equivalent circuit through the edge ring (14), and thus the current flowing through the edge ring circuit also flows through the plasma. In other words, when the edge ring circuit is properly connected and current flows to the edge ring (14), the plasma generated inside the chamber (10) can be treated as a low-resistance load, and the current value I3 measured by ammeter A can be increased.

[0095] Meanwhile, as shown in FIG. 8(b), when a wiring abnormality occurs in the edge ring circuit, even if a voltage V3 for detecting open circuit is applied, current does not flow up to the edge ring (14), that is, up to the plasma formed inside the chamber (10), so the current value I3 measured by ammeter A decreases. Therefore, as shown in FIG. 8, based on the VI characteristics acquired in advance, a threshold value B3 is set in advance between the current value I(a) measured in normal conditions and the current value I(b) measured in the event of a wiring abnormality. By doing so, it is possible to detect whether a wiring abnormality has occurred in the edge ring circuit by comparing the current value I3 actually measured by ammeter A with the threshold value B3.

[0096] Returning to the description of FIG. 7. If the measured current value I3 is greater than or equal to the threshold value B3, and the time taken to reach the threshold value B3 is within 3 seconds, it is determined that there is no wiring abnormality in the edge ring circuit, and a wire break detection pass is notified (Step P5-3 of FIG. 7). Then, when it is determined that there is no wiring abnormality in the edge ring circuit, the supply of processing gas to the processing space S and the supply of high-frequency power HF to the lower electrode (12) are stopped, and the generation of plasma inside the chamber (10) is stopped (Step P6 of FIG. 7). After that, the application of the wire break detection voltage V3 from the DC power source (60) is stopped, and a series of wiring abnormality detections are completed.

[0097] According to the second embodiment of the wiring fault detection, the DC power source (60) and the plasma generated inside the chamber (10) are connected in an equivalent circuit, and if current flows through the plasma capacitively or directly, then by generating plasma inside the chamber (10), current can be flowed by considering the plasma as a low-resistance load. That is, as described above, even if the difference in capacitance between the chamber (10) and the edge ring circuit is small, the difference between (a) the current value I(a) measured in a normal connection state and (b) the current value I(b) measured when a wiring fault occurs can be made large, so a wiring fault in the edge ring circuit can be appropriately detected.

[0098] In addition, by appropriately controlling the plasma generation conditions for the interior of the chamber (10), the risk of abnormal discharge caused by plasma generation can be reduced even if there is a wiring abnormality in the edge ring circuit. Furthermore, it is desirable to determine the plasma generation conditions in advance through experiments, etc., according to the plasma processing device (1) used, such that plasma generation conditions do not cause abnormal discharge.

[0099] In addition, according to the present embodiment, since the plasma generated inside the chamber (10) can be considered as a low-resistance load and current can be flowed, the voltage value of the open circuit detection voltage V3 applied from the DC power source (60) to the edge ring circuit can be reduced. Because of this, the load on the electrostatic chuck (13) and the generation of residual charge can be appropriately reduced.

[0100] In addition, regarding the ability to reduce the voltage value of the open circuit detection voltage V3 in this way, unlike the wiring abnormality detection method according to the first embodiment, the voltage waveform of the open circuit detection voltage V3 is not limited to a pulse wave, and a continuous wave can be used.

[0101] In addition, as described above, in an upper electrode circuit to which a second DC power source (70) is connected, wiring abnormalities can be detected by the same method. That is, a DC voltage is applied to an electrode plate (21) constituting the upper electrode in place of the edge ring (14) (chamber (10)), and a wiring abnormality in the upper electrode circuit can be detected by comparing the measured value of the current flowing due to the application of the DC voltage with a threshold value. In this case, the electrode plate (21) constituting the upper electrode corresponds to a DC voltage application member according to the technology of the present disclosure.

[0102] In addition, although the above embodiments have been described as examples of detecting wiring abnormalities in edge ring circuits or upper electrode circuits, the circuits to which the wiring abnormality detection method according to the present disclosure is applied are not limited to the above embodiments. That is, any circuit to which a DC power source is connected can detect wiring abnormalities. In particular, if the power circuit to be detected for wiring abnormalities is connected in an equivalent circuit with any object that can be considered as a low-resistance load (in the present embodiment, plasma generated inside the chamber (10)), wiring abnormalities can be detected appropriately even if there is no difference between the normal connection state of the power circuit and the measured value of the current when a wiring abnormality occurs.

[0103] Furthermore, the threshold value used in the above embodiments is merely an example. That is, for example, other elements may be used as the threshold value instead of the measured current value. In addition, the value used as the threshold value can be appropriately changed based on the detection method for wiring abnormalities, etc.

[0104] In addition, the timing at which wiring abnormality detection according to the present disclosure is performed can be determined arbitrarily. That is, for example, it may be performed periodically during the process of plasma processing on wafer W performed in the plasma processing device (1), or for example, it may be performed during setup, such as starting up the plasma processing device (1). However, wiring abnormalities such as unconnected wiring or disconnected wiring described above often occur during the setup of the device. Therefore, it is preferable that wiring abnormality detection according to the present disclosure be performed at least during setup, such as starting up the plasma processing device (1).

[0105] In addition, in the above embodiment, the case of detecting wiring abnormalities was described as an example when the wafer W is not introduced into the chamber (10), but the wiring abnormality detection may be performed when the wafer W is introduced into the chamber (10). That is, for example, when a problem is identified during the wafer processing process, the wiring abnormality detection may be performed appropriately. In such a case, when plasma is generated inside the chamber (10), as described above, the lower limit of the internal pressure of the chamber (10) can be lowered among the various conditions for plasma generation.

[0106] The embodiments disclosed herein should be considered illustrative in all respects and not restrictive. The above embodiments may be omitted, substituted, or modified in various ways without departing from the scope and common sense of the attached claims. Explanation of the symbols

[0107] 1 Plasma treatment device 10 chambers Stage 11 13 Power outage chuck 14 edge rings 21 electrode plate 60 DC power supply 62 RF filters 70 Second DC Power Supply 72 2nd RF Filter A ammeter B2 threshold B3 threshold I2 current value I3 current value W wafer

Claims

Claim 1 As a method for detecting a wiring abnormality in a plasma processing apparatus, the plasma processing apparatus comprises: a chamber for performing plasma processing of a substrate internally; a stage having an electrostatic chuck provided inside the chamber and adsorbing and holding the substrate; a high-frequency power source for generating plasma inside the chamber; a DC power meter for controlling the plasma generated inside the chamber; and an ammeter for measuring the current flowing through the DC power meter. The DC power meter comprises a DC power source for applying a DC voltage to the DC power meter; a high-frequency filter for removing high-frequency components from the DC power source; and a DC voltage application member to which the DC voltage is applied, which are electrically connected in this order to form a circuit. The detection method comprises a process of applying a DC voltage by the DC power source; a process of measuring the current flowing through the circuit constituting the DC power meter; a process of comparing the measured value of the current with a predetermined threshold value; and when the measured value is greater than or equal to the threshold value, a wiring abnormality is detected in the circuit constituting the DC power meter. A method for detecting wiring abnormalities including a determination process. Claim 2 In claim 1, the DC power source is a method for detecting wiring abnormalities by applying the DC voltage by a pulse wave. Claim 3 A method for detecting wiring abnormalities according to claim 1 or 2, further comprising specifying the location where the wiring abnormality occurs in the circuit based on the measured value of the current. Claim 4 A method for detecting wiring abnormalities according to claim 1, further comprising a process of generating plasma inside the chamber prior to applying a DC voltage from the DC power source. Claim 5 A method for detecting wiring abnormalities according to claim 4, wherein the generation of the plasma is performed under conditions where the internal pressure of the chamber is 1000 mTorr or less and the power applied from the high-frequency power source is 500 W or less. Claim 6 In claim 4 or 5, the DC power source is a method for detecting wiring abnormalities in which the DC voltage is applied by a pulse wave or a continuous wave. Claim 7 A method for detecting wiring abnormalities according to claim 1 or 2, wherein the threshold value is predetermined by comparing a first VI characteristic obtained by applying the DC voltage in a state where no wiring abnormality occurs in the DC power system and a second VI characteristic obtained by applying the DC voltage in a state where a wiring abnormality occurs in the DC power system. Claim 8 A method for detecting wiring defects according to claim 1 or 2, further comprising performing short-circuit detection of the circuit prior to applying a DC voltage from the DC power source. Claim 9 A method for detecting wiring defects according to claim 1 or 2, wherein the DC voltage application member is an edge ring disposed around a substrate mounted on the stage, or an upper electrode disposed above the stage. Claim 10 A plasma processing apparatus for performing plasma processing on a substrate comprises: a chamber for performing plasma processing on the substrate internally; a stage having an electrostatic chuck provided inside the chamber and adsorbing and holding the substrate; a high-frequency power source for generating plasma inside the chamber; a DC power system for controlling the plasma generated inside the chamber; an ammeter for measuring the current flowing through the DC power system; and a control unit for controlling the operation of the DC power system. The DC power system comprises a DC power source for applying a DC voltage to the DC power system; a high-frequency filter for removing high-frequency components from the DC power source; and a DC voltage application member to which the DC voltage is applied, which are electrically connected in this order to form a circuit. The control unit comprises a process of applying a DC voltage by the DC power source; a process of measuring the current flowing through the circuit constituting the DC power system; a process of comparing the measured value of the current with a predetermined threshold value; and, when the measured value is greater than or equal to the threshold value, wiring to the circuit constituting the DC power system. A plasma processing device that controls the above-mentioned DC power system to perform a process of determining that an abnormality is occurring. Claim 11 In claim 10, the control unit controls the operation of the high-frequency power source to perform a process of generating plasma inside the chamber prior to the application of a DC voltage from the DC power source. Claim 12 In claim 10 or 11, the DC power source is a plasma processing device configured to switch the applied waveform of the DC voltage into a pulse wave and a continuous wave. Claim 13 A plasma processing apparatus according to claim 10 or 11, wherein the DC voltage applying member is an edge ring disposed around a substrate mounted on the stage, or an upper electrode disposed above the stage. Claim 14 In claim 10 or 11, the DC power source is a plasma processing device that applies the DC voltage by a pulse wave. Claim 15 A plasma processing device according to claim 10 or 11, wherein the control unit controls the DC power system to specify the location of a wiring abnormality in the circuit based on the measured value of the current. Claim 16 In claim 11, the plasma is a plasma processing device generated under conditions where the internal pressure of the chamber is 1000 mTorr or less and the power applied from the high-frequency power source is 500 W or less. Claim 17 A plasma processing apparatus according to claim 10 or 11, wherein the threshold value is predetermined by comparing a first VI characteristic obtained by applying the DC voltage in a state where no wiring abnormality occurs in the DC power system and a second VI characteristic obtained by applying the DC voltage in a state where a wiring abnormality occurs in the DC power system. Claim 18 A plasma processing device according to claim 10 or 11, wherein the control unit controls the DC power system to perform short-circuit detection of the circuit prior to the application of a DC voltage from the DC power source.

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