Power semiconductor device and method of manufacturing same

Abstract

The present invention relates to a power semiconductor device (1) and a method for manufacturing, and more specifically, to a power semiconductor device (1) and a method for manufacturing such that the upper surface of a barrier layer (130) between a gate electrode (150) and a drain electrode (163) is formed with a stepwise recess (131), thereby enabling effective control of the electric field strength at the side interface adjacent to the drain electrode (163) and effectively suppressing carrier traps between the gate electrode (150) and the drain electrode (163).

Description

Technology Field

[0001] The present invention relates to a power semiconductor device (1) and a method for manufacturing, and more specifically, to a power semiconductor device (1) and a method for manufacturing such that the upper surface of a barrier layer (130) between a gate electrode (150) and a drain electrode (163) is formed with a stepwise recess (131), thereby enabling effective control of the electric field strength at the side interface adjacent to the drain electrode (163) and effectively suppressing carrier traps between the gate electrode (150) and the drain electrode (163). Background Technology

[0003] Nitride semiconductors are being applied to high-voltage and high-power semiconductor devices due to their high saturation electron velocity and wide band gap characteristics. In particular, gallium nitride (GaN) has a wide band gap and high breakdown electric field characteristics compared to silicon and gallium arsenide (GaAs), so it exhibits excellent breakdown voltage characteristics when applied to transistors.

[0004] Furthermore, gallium nitride (GaN)-based devices possess higher electron mobility and saturation electron velocity compared to currently commonly used silicon-based devices, enabling them to exhibit high frequency characteristics. When applied to GaN devices, this high electron mobility results in improved on-resistance characteristics, thereby making the realization of low-loss switching devices possible.

[0005] As such, GaN-based Field Effect Transistors (FETs) are the subject of continuous research because they offer significant advantages as devices requiring high-frequency, high-power characteristics. Although these GaN-based FETs have seen considerable research and development over the past few years, there are still several issues regarding device reliability that need to be resolved. One critical issue concerns the Current Collapse Effect caused by traps present in the semiconductor.

[0007] Figure 1 is a partial cross-sectional view of a conventional power semiconductor device.

[0009] Below, the general structure and problems of a conventional power semiconductor device (9) will be explained with reference to the attached drawings.

[0011] Referring to FIG. 1, in a conventional power semiconductor device (9), a higher voltage may be applied to the drain electrode (950) compared to the source electrode (910) and the gate electrode (930), and carriers may be trapped between the gate electrode (930) and the drain electrode (950). Due to the carrier trapping, a current collapse phenomenon occurs, and this current collapse phenomenon can cause a 'memory' effect in which the conduction current of the device may differ depending on the duration of the previously applied voltage. For example, during transistor operation, electrons are trapped in the epitaxial layer or dielectric layer, and the trapped electrons may push out electrons moving through the channel, thereby hindering current conduction through the 2DEG layer (970). This can cause a problem of increasing the resistance of the channel.

[0013] To solve such problems, the inventors of the present invention present a novel power semiconductor device having an improved structure and a method for manufacturing it, and details will be described below. Prior art literature

[0015] Korean Patent Publication No. 10-2020-0068745 'High Electron Mobility Transistor' The problem to be solved

[0016] It was devised to solve the problems of the prior art described above,

[0018] The present invention aims to provide a power semiconductor device and a method for manufacturing such that the upper surface of the barrier layer between the gate electrode and the drain electrode is formed with a stepwise recess, thereby enabling effective control of the electric field strength at the side interface adjacent to the drain electrode and effectively suppressing carrier traps between the gate electrode and the drain electrode.

[0019] In addition, the present invention aims to provide a power semiconductor device and a manufacturing method that more effectively suppresses carrier traps between the gate electrode and the drain electrode by forming the recess portion in a stepped structure with a narrow recess portion and a wide recess portion.

[0020] In addition, the present invention aims to provide a power semiconductor device and a manufacturing method that more effectively suppresses carrier traps by forming multiple recesses spaced apart along an orthogonal direction, while simultaneously preventing the device current amount from becoming less than necessary.

[0021] In addition, the present invention aims to provide a power semiconductor device and a manufacturing method that prevents a decrease in process efficiency by ensuring that a narrow recess and a wide recess are formed substantially simultaneously by a single etching process. means of solving the problem

[0023] The present invention may be implemented by an embodiment having the following configuration to achieve the aforementioned objectives.

[0025] According to one embodiment of the present invention, a power semiconductor device according to the present invention comprises: a substrate; a channel layer on the substrate; a barrier layer on the channel layer; a capping layer on the barrier layer; a gate electrode on the capping layer; a source electrode and a drain electrode spaced apart from the gate electrode and forming an ohmic contact region on the barrier layer; and an insulating film on the barrier layer; wherein one side of the upper surface of the barrier layer is stepped between the gate electrode and the drain electrode.

[0026] According to another embodiment of the present invention, the barrier layer in the power semiconductor device according to the present invention is characterized by having a stepped structure in which one side of its upper surface is indented downward from the gate electrode toward the drain electrode.

[0027] According to another embodiment of the present invention, the barrier layer in the power semiconductor device according to the present invention is characterized by including a first recess portion that is spaced apart from the edge of the drain electrode on its upper surface and is recessed downward.

[0028] According to another embodiment of the present invention, the first recess portions in the power semiconductor device according to the present invention are characterized by being formed in multiple numbers spaced apart from each other along an orthogonal direction.

[0029] According to another embodiment of the present invention, the barrier layer in the power semiconductor device according to the present invention is characterized by additionally including a second recess portion that is recessed downward from the first recess portion and the drain electrode on the upper surface thereof.

[0030] According to another embodiment of the present invention, the second recess portion in the power semiconductor device according to the present invention is characterized by having a wider horizontal width compared to the first recess portion.

[0031] According to another embodiment of the present invention, the second recess portion in the power semiconductor device according to the present invention is characterized by having a wider orthogonal width size compared to the first recess portion.

[0032] According to another embodiment of the present invention, the second recess portion in the power semiconductor device according to the present invention is characterized by being recessed to a greater depth than the first recess portion.

[0033] According to another embodiment of the present invention, the second recess portion in the power semiconductor device according to the present invention is characterized by being formed substantially simultaneously with the first recess portion.

[0034] According to another embodiment of the present invention, the second recess portion in the power semiconductor device according to the present invention is characterized by having a structure that is physically connected to the first recess portion.

[0035] According to another embodiment of the present invention, a power semiconductor device according to the present invention comprises: a substrate; a buffer layer on the substrate; a channel layer which is a nitride-based semiconductor layer on the buffer layer; a barrier layer which is a nitride-based semiconductor layer different from the channel layer on the channel layer; a capping layer on the barrier layer; a gate electrode on the capping layer; and a source electrode and a drain electrode which are ohmic contact regions on the barrier layer and spaced apart from the gate electrode; wherein the barrier layer comprises a recess portion including a narrow recess portion between the drain electrode and the gate electrode; and a wide recess portion connected to the narrow recess portion between the narrow recess portion and the drain electrode.

[0036] According to another embodiment of the present invention, the recess portions in the power semiconductor device according to the present invention are characterized by being formed in multiple numbers spaced apart from each other along an orthogonal direction on the upper surface of the barrier layer.

[0037] According to another embodiment of the present invention, the narrow recess portion in the power semiconductor device according to the present invention is characterized by having a horizontal central axis substantially identical to that of the connected wide recess portion.

[0038] According to another embodiment of the present invention, the wide recess portion in the power semiconductor device according to the present invention has a deeper indentation depth than the narrow recess portion, so that one side of the upper surface of the barrier layer has a stepped structure in which it is indented downward from the gate electrode to the drain electrode.

[0039] According to another embodiment of the present invention, the recess portion in the power semiconductor device according to the present invention is characterized by having an additional narrow recess portion of an island structure between a pair of narrow recess portions connected to each wide recess portion and an orthogonal space between them.

[0040] According to another embodiment of the present invention, the recess portion in the power semiconductor device according to the present invention is characterized by being formed by a plasma etching process.

[0041] According to one embodiment of the present invention, a method for manufacturing a power semiconductor device according to the present invention comprises: a step of forming a channel layer, which is a nitride-based semiconductor layer such as GaN, on a substrate; a step of forming a barrier layer, which is a nitride-based semiconductor layer such as AlGaN, on the channel layer; a step of forming a capping layer of a first conductivity type on the barrier layer; a step of forming a recess portion that is recessed downward on one side of the upper surface of the barrier layer; a step of forming a gate electrode on the capping layer; a step of forming an insulating film on the barrier layer; and a step of forming a source electrode and a drain electrode on the barrier layer.

[0042] According to another embodiment of the present invention, the recess portion in the method for manufacturing a power semiconductor device according to the present invention is characterized by comprising: a narrow recess portion between the drain electrode and the gate electrode on the upper surface thereof; and a wide recess portion connected to the narrow recess portion between the narrow recess portion and the drain electrode on the upper surface thereof.

[0043] According to another embodiment of the present invention, the step of forming a recess portion in a method for manufacturing a power semiconductor device according to the present invention comprises the step of forming a mask pattern on the upper surface of a barrier layer, the upper surface of which is substantially flat; wherein the mask pattern is characterized in that the width of the side opening space where the narrow recess portion is to be formed is narrower than the width of the side opening space where the wide recess portion is to be formed.

[0044] According to another embodiment of the present invention, the barrier layer formation step in the method for manufacturing a power semiconductor device according to the present invention is characterized by additionally including the step of plasma etching one side of the upper surface of the barrier layer using the mask pattern. Effects of the invention

[0046] The present invention has the following effects based on the configuration described above.

[0048] The present invention has the effect of effectively controlling the electric field strength at the side interface adjacent to the drain electrode and effectively suppressing carrier traps between the gate electrode and the drain electrode by having a recess portion formed with a step on the upper surface of the barrier layer between the gate electrode and the drain electrode.

[0049] In addition, the present invention has the effect of more effectively suppressing carrier traps between the gate electrode and the drain electrode by forming the recess portion in a stepped structure with a narrow recess portion and a wide recess portion.

[0050] In addition, the present invention provides the effect of more effectively suppressing carrier traps by forming multiple recesses spaced apart along the orthogonal direction, while simultaneously preventing the device current amount from becoming less than necessary.

[0051] In addition, the present invention has the effect of preventing a decrease in process efficiency by ensuring that a narrow recess and a wide recess are formed substantially simultaneously by a single etching process.

[0053] Meanwhile, it should be added that even if an effect is not explicitly mentioned here, the effects described in the following specification and the provisional effects expected by the technical features of the present invention are treated as described in the specification of the present invention. Brief explanation of the drawing

[0055] FIG. 1 is a partial cross-sectional view of a conventional power semiconductor device; FIG. 2 is a plan view of a power semiconductor device according to one embodiment of the present invention; FIG. 3 is a cross-sectional view AA' of a power semiconductor device according to FIG. 2; FIG. 4 is a cross-sectional view of BB' of a power semiconductor device according to FIG. 2; FIGS. 5 to 16 are cross-sectional views for explaining a method for manufacturing a power semiconductor device according to an embodiment of the present invention. Specific details for implementing the invention

[0056] Hereinafter, embodiments of the present invention will be described in more detail with reference to the accompanying drawings. Embodiments of the present invention may be modified in various forms, and the scope of the present invention should not be interpreted as being limited to the embodiments below, but should be interpreted based on the matters described in the claims. Furthermore, these embodiments are provided merely for reference to more completely explain the present invention to those with average knowledge in the art.

[0057] In the following description, it should be noted that when one component (or layer) is described as being placed on another component (or layer), the component may be placed directly on the other component, or other component(s) or layer(s) may be located between the components. Furthermore, when one component is described as being placed directly on or above another component, no other component(s) are located between the components. Additionally, being located on the 'top', 'upper', 'lower', 'upper side', 'lower side', or 'one side' or 'side' of a component refers to a relative positional relationship.

[0058] And terms such as first, second, etc. may be used to describe various items such as various elements, areas and / or parts, but the items are not limited by these terms.

[0059] In addition, it should be noted that where specific embodiments can be implemented differently, a specific process sequence may be performed differently from the order described below. For example, two processes described sequentially may be performed substantially simultaneously or in the reverse order.

[0060] Additionally, the conductivity type or doping region of the components may be defined as 'P-type' or 'N-type' depending on the main carrier characteristics; however, this is merely for convenience of explanation and the technical concept of the present invention is not limited to what has been exemplified. For example, 'P-type' or 'N-type' will be used hereinafter as the more general terms 'first conductivity type' or 'second conductivity type,' where the first conductivity type refers to the P-type and the second conductivity type refers to the N-type.

[0061] In addition, 'high concentration' and 'low concentration,' which express the doping concentration of the impurity region, should be understood as referring to the relative doping concentration of one component and another component.

[0062] Hereinafter, the x-axis direction on the illustrated plan view (Fig. 2) will be described as the 'horizontal direction' and the y-axis direction as the 'orthogonal direction'.

[0064] FIG. 2 is a plan view of a power semiconductor device according to one embodiment of the present invention; FIG. 3 is a cross-sectional view AA' of the power semiconductor device according to FIG. 2; and FIG. 4 is a cross-sectional view BB' of the power semiconductor device according to FIG. 2. It should be noted that for convenience of explanation, the illustration of the insulating film and the gate electrode has been omitted in FIG. 2.

[0066] Hereinafter, a power semiconductor device (1) according to one embodiment of the present invention will be described in detail with reference to the attached drawings.

[0068] Referring to FIGS. 2 to 4, the present invention relates to a power semiconductor device (1), and more specifically, to a power semiconductor device (1) for effectively controlling the electric field strength at the side interface adjacent to the drain electrode (163) and effectively suppressing carrier traps between the gate electrode (150) and the drain electrode (163) by having a recess (131) formed in a stepped manner on the upper surface of a barrier layer (130) between the gate electrode (150) and the drain electrode (163).

[0069] To this end, the power semiconductor device (1) may include a substrate (101), a buffer layer (110), a channel layer (120), a barrier layer (130), a capping layer (140), a gate electrode (150), a source electrode (161), a drain electrode (163), and an insulating film (170).

[0070] The substrate (101) is a growth substrate and, for example, may be a silicon substrate, but is not limited thereto and may be a sapphire substrate, a GaN substrate, or a SiC substrate. In the present invention, the substrate (101) is described as being a silicon substrate as an example.

[0071] The buffer layer (110) is a layer formed on the substrate (101), for example, by growing AlN to a predetermined thickness on the substrate (101). Alternatively, the buffer layer (110) may be in the form of a composite layer grown of one or more of GaN and AlGaN, but is not limited thereto. This buffer layer (110) may be a structure for preventing stress caused by the difference in lattice constant and thermal expansion coefficient between the substrate (101) and the channel layer (120) to be described later. The buffer layer (110) may be doped with impurities such as C and / or Fe.

[0072] The channel layer (120) is formed on the substrate (101), more preferably on the buffer layer (110), to have a predetermined thickness and may be composed of a nitride-based semiconductor layer such as GaN, for example. Additionally, the barrier layer (130) is formed on the channel layer (120) to have a predetermined thickness and may be a nitride-based semiconductor layer such as AlGaN, for example. It is preferable that the channel layer (120) and the barrier layer (130) be formed as different nitride-based semiconductor layers. With such a structure, a 2DEG (2-Dimensional Electro Gas) layer (2DEG) can be formed near the interface between the channel layer (120) and the barrier layer (130). At this time, the density and mobility of the 2DEG layer (2DEG) can be controlled by controlling the content of Al and Ga in the barrier layer (130). The 2DEG layer (2DEG) can be formed within the channel layer (120).

[0073] Additionally, the barrier layer (130) may be formed to have a recess (131) between the gate electrode (150) and the drain electrode (163). That is, at least one side of the upper surface of the barrier layer (130) may have a stepped structure formed so as to be stepped downward as it extends from the gate electrode (150) to the drain electrode (163). Additionally, the recess (131) may be formed in multiple numbers so as to extend along the horizontal direction but be spaced apart from each other along the orthogonal direction. By continuously arranging the recess (131) along the orthogonal direction in this way, carrier trapping can be effectively suppressed, and at the same time, by having multiple recess (131) spaced apart from each other, the amount of current of the device (1) can be prevented to the maximum extent from becoming less than necessary.

[0074] Referring to FIG. 2, the recess portion (131) may include a narrow recess portion (131a) and a wide recess portion (131b). The narrow recess portion (131a) is characterized by having a narrower orthogonal width size compared to the wide recess portion (131b) (A1 < A2). Additionally, it is preferable that the narrow recess portion (131a) be formed to have a narrower horizontal width size compared to the wide recess portion (131b) (B1 < B2). This narrow recess portion (131a) is spaced apart from the drain electrode (163), and, for example, it is preferable that it is spaced apart from the drain electrode (163) by a predetermined distance along the horizontal direction.

[0075] And the narrow recess (131a) may be physically connected to an adjacent wide recess (131b) along the horizontal direction (see FIG. 3) or may be formed as an island type spaced apart from the drain electrode (163) (see FIG. 4), and the scope of the invention is not limited by specific examples. It is preferable that such narrow recess (131a) be formed at substantially the same horizontal position along the vertical direction, and may be formed spaced apart along the vertical direction, for example, to form substantially the same row. For example, multiple narrow recess (131a) may be formed to have the same central axis within an error range along the vertical direction.

[0076] And the narrow recess (131a) can be formed to be recessed to a shallow depth relative to the wide recess (131b) on the upper surface of the barrier layer (130) (D1 < D2). Therefore, when the narrow recess (131a) and the wide recess (131b) are connected to each other along the horizontal direction, a stepped structure can be formed on one side of the upper surface of the barrier layer (130) that is stepped downward as it extends from the gate electrode (140) to the drain electrode (163) (see FIG. 3). Additionally, one end of the wide recess (131b) may extend to the edge of the drain electrode (163) or to a side adjacent to the edge of the drain electrode (163), and there are no separate limitations thereon. Furthermore, for example, when the narrow recess (131a) is connected to the wide recess (131b), it is preferable that the horizontal center axes of the components be formed to substantially coincide within an error range. Referring to FIG. 2, the narrow recess (131a) and the wide recess (131b) have a square planar shape, but they may substantially be formed as curved shapes with cut-off edge portions, and there are no separate limitations thereon.

[0077] In the cross-sectional view shown in FIG. 3, the recess (131) is configured to have a two-stage structure in which a narrow recess (131a) and a wide recess (131b) are formed along the horizontal direction, but the recess (131) may be formed in a structure of three or more stages as needed, and in this case, it is preferable that the recess closest to the drain electrode (163) has the deepest depth and the width in the horizontal and vertical directions. That is, when the recess (131) is formed in a multi-stage structure of two or more stages, a stepped structure can be formed that is stepped along the downward direction as it extends from the gate electrode (140) to the drain electrode (163).

[0078] And on the upper surface of the narrow recess (131a) and the wide recess (131b), preferably on the upper surface of the etching stop film, an insulating film (170) to be described later may be formed.

[0080] Hereinafter, with reference to the attached drawings, the general structure and problems of the conventional power semiconductor device (9) and the advantages of the present invention will be explained.

[0082] Referring to FIG. 1, in a conventional power semiconductor device (9), a higher voltage may be applied to the drain electrode (950) compared to the source electrode (910) and the gate electrode (930), and carriers may be trapped between the gate electrode (930) and the drain electrode (950). Due to the carrier trapping, a current collapse phenomenon occurs, and this current collapse phenomenon can cause a 'memory' effect in which the conduction current of the device may differ depending on the duration of the previously applied voltage. For example, during transistor operation, electrons are trapped in the epitaxial layer or dielectric layer, and the trapped electrons may push out electrons moving through the channel, thereby hindering current conduction through the 2DEG layer (970). This can cause a problem of increasing the resistance of the channel.

[0083] Referring to FIGS. 2 to 4, as described above, a power semiconductor device (1) according to one embodiment of the present invention includes a recess (131) having a stepped structure formed such that at least one side of the upper surface of the barrier layer (130) extends downward from the gate electrode (150) to the drain electrode (163). Through this recess (131), the electric field strength at the interface adjacent to the drain electrode (163) can be effectively controlled, thereby obtaining a desired breakdown voltage characteristic, and an advantage arises that carrier traps can be effectively suppressed through continuous arrangement.

[0084] An etch stop layer (not shown) may be formed on the upper surface of the barrier layer (130), and the etch stop layer may be formed by growing an AlN epitaxial layer.

[0085] The capping layer (140) is formed on the barrier layer (130) and is configured to be formed on the lower side of the gate electrode (150), and preferably has positive polarity, for example, as a first conductivity type doping region. If the capping layer (140) is formed with a thickness greater than a predetermined thickness, the distance from the gate electrode (150) to the 2DEG layer (2DEG) becomes longer, which reduces the response speed; conversely, if it is formed with a thickness less than a predetermined thickness, it is difficult to obtain a Normally Off operation, so it is formed with an appropriate thickness, and for example, it is preferably formed within the range of 10 nm to 1000 nm, but is not limited thereto. In addition, the capping layer (140) can be formed by growing p-GaN, and for example, by doping GaN with Mg.

[0086] The capping layer (140) is formed substantially only at the bottom of the gate electrode (150), and the 2DEG layer (2DEG) does not exist on the lower side of the capping layer (140) when not in operation. Therefore, when the gate voltage is off, the 2DEG layer (2DEG) does not exist in the channel layer (120), so it operates normally off, and when the gate voltage is on, the 2DEG layer (2DEG) is formed so that it can be driven.

[0087] The gate electrode (150) is configured to be formed on the barrier layer (130), for example, on the capping layer (140), and can be formed as a single layer or composite layer of any metal such as Ti or Pd. Additionally, the gate electrode (150) is normally off, so that the depletion layer of the gate electrode (150) passes through the barrier layer (130) to reach the channel layer (120) and block the 2DEG layer (2DEG).

[0088] It should be noted that the source electrode (161) and the drain electrode (163) are spaced apart from the gate electrode (150) and form an ohmic contact region on the barrier layer (130), which may be formed, for example, in a stepped cross-sectional shape or a square cross-sectional shape, but may also be formed in various other structures. For example, the source electrode (161), the gate region (150), and the drain electrode (163) may be formed sequentially spaced apart from each other along the horizontal direction. Additionally, the source electrode (161) and the drain electrode (163) may include, for example, any single or composite layer of various metals capable of ohmic contact, such as Ti, Au, or Al, and there are no separate limitations thereon.

[0089] The insulating film (170) may be formed, for example, from a material having electrical insulating properties. This insulating film (170) may be formed on the barrier layer (130). Additionally, the insulating film (170) may be formed at a position that does not cover the source electrode (161) and the drain electrode (163), or up to a position that covers them. The insulating film (170) may be completed, for example, by depositing Al2O3 on the barrier layer (130) to cover both the source electrode (161) and the drain electrode (163), and then forming an opening (H) on the upper side of the source electrode (161) and the drain electrode (163).

[0091] FIGS. 5 to 16 are cross-sectional views for explaining a method for manufacturing a power semiconductor device according to an embodiment of the present invention.

[0093] Hereinafter, a method for manufacturing a power semiconductor device according to an embodiment of the present invention will be described in detail with reference to the attached drawings.

[0095] First, referring to FIG. 5, a buffer layer (110), a channel layer (120), and a barrier layer (130) having a substantially flat upper surface are sequentially formed on a substrate (101). As previously mentioned, the substrate (101) is a growth substrate and may be any one of a silicon substrate, a sapphire substrate, a GaN substrate, or a SiC substrate, but in the present invention, it is described based on the premise that it is a silicon substrate as an example. The buffer layer (110) can be formed on the substrate (101) and below the channel layer (120), for example, by growing an AlN layer to a predetermined thickness.

[0096] Additionally, the channel layer (120) formed on the buffer layer (110) is a nitride-based semiconductor layer such as GaN, and the barrier layer (130) is a nitride-based semiconductor layer such as AlGaN, and a 2DEG layer (2DEG; not shown) can be formed by electrons accumulated at the interface between the channel layer (120) and the barrier layer (130). To explain in detail, piezopolarization can occur at the interface between the channel layer (120) and the barrier layer (130) due to the difference in lattice constants between GaN and AlGaN. At this time, the piezopolarization effect and the spontaneous polarization effect of the channel layer (120) and the barrier layer (130) act together, so that a two-dimensional electron gas with a high electron concentration can be generated at the interface between the two components.

[0097] Then, a capping layer (140) can be formed on the barrier layer (130). The capping layer (140) can be formed by growing a p-GaN layer to a predetermined thickness. For example, when growing a GaN layer to a first conductivity type, such as the barrier layer (130), Mg can be added to the GaN source gas to dope the GaN with Mg. At this time, an etch stop layer may be additionally formed between the barrier layer (130) and the capping layer (140).

[0098] The process of forming the capping layer (140) is described as an example. Referring to FIG. 6, a doping layer (D) is first formed by growing a GaN layer with a first conductivity type on the barrier layer (130). Then, referring to FIG. 7, the capping layer (140) can be formed by etching the open side of the doping layer (D) using a mask pattern (not shown).

[0099] Then, a recess (131) can be formed on one side of the barrier layer (130). It is preferable that this recess (131) be formed by an etching process on the upper surface of the barrier layer (130), which is substantially flat, and it is even more preferable that it be formed by a plasma etching process. Referring to FIG. 8, a mask pattern (PR) is first formed on the upper surface of the barrier layer (130), and this pattern (PR) can be formed with a structure in which the side where the narrow recess (131a) and the wide recess (131b) are to be formed is open.

[0100] At this time, it is preferable that the horizontal and / or orthogonal width of the open space on the side where the narrow recess (131a) is to be formed be narrower than the horizontal and / or orthogonal width of the open space on the side where the wide recess (131b) is to be formed. Then, referring to FIG. 9, the narrow recess (131a) and the wide recess (131b) can be formed together by a single etching process. At this time, a difference in etch rate occurs due to the difference in line width of the pattern (PR) open space.

[0101] In other words, even if etching is performed with plasma of the same density, if the etching area or pattern size differs, a narrow recess (131a) and a wide recess (131b) can be formed by utilizing the loading effect, in which the density supplied to the etching material during the etching process varies according to the reaction area. As a result, there is no need to perform multiple etching processes to form each recess (131a, 131b). Conversely, if two etching processes are performed to form each recess (131a, 131b), the barrier layer (130) at the boundary between the narrow recess (131a) and the wide recess (131b) may be etched more than necessary, or each recess (131a, 131b) may be formed spaced apart along the horizontal direction during the process. Therefore, it is preferable to perform a single etching process.

[0102] In a subsequent process, referring to FIG. 10, an insulating film layer (I1) is formed to cover the barrier layer (130) and the capping layer (140). Then, referring to FIG. 11, an opening (H) is formed at the location where the source electrode (161) and the drain electrode (163) are to be formed. The opening (H) can be formed by performing an etching process on the open side after forming a mask pattern (not shown) on the insulating film layer (I1).

[0103] Then, referring to FIG. 12, a metal layer (M1) is deposited on an insulating film layer (I1) to fill the opening (H), and then a mask pattern (not shown) is formed on the metal layer (M1). Also, referring to FIG. 13, the metal layer (M1) is partially removed by performing an etching process using the mask pattern. By doing so, a source electrode (161) and a drain electrode (163) can be formed.

[0104] In a subsequent process, a gate electrode (150) is formed. First, referring to FIG. 14, after the source electrode (161) and drain electrode (163) are formed, an additional insulating layer (I2) is formed on the insulating layer (I1), and then an opening (H) is formed. This opening (H) can be formed at a position where the upper surface of the capping layer (140) is exposed to the outside. Then, referring to FIG. 15, a metal layer (M2) is formed on the source electrode (161) and drain electrode (163) to fill the opening (H). Then, referring to FIG. 16, the metal layer (M2) can be removed to form the gate electrode (150).

[0106] The above detailed description is illustrative of the present invention. Furthermore, the foregoing describes preferred embodiments of the present invention, and the present invention may be used in various other combinations, modifications, and environments. That is, modifications or alterations are possible within the scope of the concept of the invention disclosed herein, the scope equivalent to the written disclosure, and / or the scope of the art or knowledge. The foregoing embodiments describe the best state for implementing the technical concept of the present invention, and various modifications required for specific fields of application and uses of the present invention are also possible. Accordingly, the above detailed description of the invention is not intended to limit the present invention to the disclosed embodiments. Explanation of the symbols

[0108] 1 : Power semiconductor device 101 : Substrate 110: Buffer layer 120: Channel layer 130 : Barrier layer 131 : Recess section 131a: Narrow recess 131b: Wide recess 140 : Capping layer 141 : Doping layer 150: Gate electrode 161: Source electrode 163: Drain electrode 170 : Insulating film 9: Conventional power semiconductor device 910: Source electrode 930: Gate electrode 950: Drain electrode 970: 2DEG layer 2DEG : 2DEG layer H : Opening I1, I2: Insulating film layer M1, M2: Metal layer D: Doping layer PR: Mask pattern A1: Orthogonal width of the narrow recess A2: Orthogonal width of the wide recess B1: Horizontal width of the narrow recess B2: Horizontal width of the wide recess D1: Depth of the narrow recess D2: Depth of the wide recess

Claims

Claim 1 A power semiconductor device comprising: a substrate; a channel layer on the substrate; a barrier layer on the channel layer; a capping layer on the barrier layer; a gate electrode on the capping layer; a source electrode and a drain electrode spaced apart from the gate electrode and forming an ohmic contact region on the barrier layer; and an insulating film on the barrier layer; wherein the barrier layer comprises: a narrow recess portion spaced apart from the edge of the drain electrode and recessed downward on its upper surface; and a wide recess portion recessed downward between the narrow recess portion and the drain electrode on its upper surface; wherein the wide recess portion has a deeper recessed depth than the narrow recess portion, so that one side of the upper surface of the barrier layer has a stepped structure in which it recesses downward from the gate electrode toward the drain electrode. Claim 2 delete Claim 3 delete Claim 4 A power semiconductor device according to claim 1, characterized in that the narrow recesses are formed in multiple numbers spaced apart from each other along an orthogonal direction. Claim 5 delete Claim 6 A power semiconductor device according to claim 1, wherein the wide recess portion has a wider horizontal width compared to the narrow recess portion. Claim 7 A power semiconductor device according to claim 1, wherein the wide recess portion has a wider orthogonal width size compared to the narrow recess portion. Claim 8 delete Claim 9 A power semiconductor device according to claim 1, characterized in that the wide recess portion is formed simultaneously with the narrow recess portion. Claim 10 A power semiconductor device according to claim 1, characterized in that the wide recess portion is physically connected to the narrow recess portion. Claim 11 A power supply comprising: a substrate; a buffer layer on the substrate; a channel layer which is a nitride-based semiconductor layer on the buffer layer; a barrier layer which is a nitride-based semiconductor layer different from the channel layer on the channel layer; a capping layer on the barrier layer; a gate electrode on the capping layer; and a source electrode and a drain electrode which are ohmic contact regions on the barrier layer and are spaced apart from the gate electrode; wherein the barrier layer comprises: a narrow recess portion between the drain electrode and the gate electrode; a wide recess portion connected to the narrow recess portion between the narrow recess portion and the drain electrode; and an additional narrow recess portion having an island structure between a pair of narrow recess portions connected to each wide recess portion and an orthogonal spaced-apart space between them. Semiconductor device. Claim 12 A power semiconductor device according to claim 11, characterized in that the wide recesses are formed in multiple numbers spaced apart from each other along an orthogonal direction on the upper surface of the barrier layer. Claim 13 A power semiconductor device according to claim 11, characterized in that the narrow recess portion has the same horizontal central axis as the connected wide recess portion. Claim 14 A power semiconductor device according to claim 11, wherein the wide recess portion has a deeper indentation depth than the narrow recess portion, and one side of the upper surface of the barrier layer has a stepped structure in which it is indented downward from the gate electrode to the drain electrode. Claim 15 delete Claim 16 A power semiconductor device according to claim 11, characterized in that the wide recess and the narrow recess are formed by a plasma etching process. Claim 17 A method for manufacturing a power semiconductor device according to claim 1, comprising: a step of forming a channel layer, which is a nitride-based semiconductor layer such as GaN, on a substrate; a step of forming a barrier layer, which is a nitride-based semiconductor layer such as AlGaN, on the channel layer; a step of forming a capping layer of a first conductivity type on the barrier layer; a step of forming a recess portion that is recessed downward on one side of the upper surface of the barrier layer; a step of forming a gate electrode on the capping layer; a step of forming an insulating film on the barrier layer; and a step of forming a source electrode and a drain electrode on the barrier layer. Claim 18 delete Claim 19 A method for manufacturing a power semiconductor device according to claim 17, wherein the step of forming the recess portion comprises the step of forming a mask pattern on the upper surface of a barrier layer having a flat upper surface, and wherein the mask pattern is characterized in that the width size of the side open space where the narrow recess portion is to be formed is narrower than the width size of the side open space where the wide recess portion is to be formed. Claim 20 A method for manufacturing a power semiconductor device according to claim 19, wherein the barrier layer forming step further comprises a step of plasma etching one side of the upper surface of the barrier layer.

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