Radio-frequency circuit for phased array antenna

Abstract

A wireless communication system comprises a plurality of antennas and a plurality of RF chips arranged in a row and coupled to the antennas to provide a plurality of RF (radio-frequency) output signals to the antennas according to an RF signal. The wireless communication system also comprises a transmission line arranged to form a straight line parallel to the row and connected to the RF chips, and a resistive load coupled to a first end of the transmission line. A second end of the transmission line is arranged to receive an RF signal.

Description

Technology Field

[0001] The present invention relates to a radio frequency circuit for a phase array antenna. Background Technology

[0002] In modern wireless communication technology, phased array antenna technology is receiving significant attention due to its advantages over conventional antenna technology, such as high gain, high reliability, and beam steering capabilities. Since phased array antenna technology employs an antenna array arranged with well-managed spacing, the substrate area where the array antenna is placed is much larger than that of conventional non-array antennas. Substrate flatness is one of the critical challenges in developing large-scale antenna arrays at an acceptable cost. Meanwhile, radio frequency (RF) circuits with higher circuit density and lower power consumption are required to achieve better signal processing performance for antenna arrays. Therefore, there is a need to develop new architectures for phased array antennas to address the substrate issue, enabling the formation of RF circuits and antennas at low cost and high performance. The problem to be solved

[0003] The present invention is intended to provide a radio frequency circuit for a phase array antenna. means of solving the problem

[0004] Embodiments of the present invention propose a wireless communication system comprising a plurality of antennas, a plurality of RF chips arranged in a row and coupled to the antennas, and for providing a plurality of radio frequency (RF) output signals to the antennas according to an RF signal. The wireless communication system also comprises a transmission line arranged in a straight line parallel to the row and arranged to be connected to the RF chip; and a resistive load coupled to a first end of the transmission line. A second end of the transmission line is arranged to receive the RF signal.

[0005] A wireless communication system according to an embodiment of the present invention comprises: a plurality of antennas; a plurality of RF chips arranged in a row and coupled to the antennas, for receiving a plurality of radio frequency (RF) signals from the antennas to output a plurality of RF output signals; a transmission line arranged in a straight line parallel to the row and arranged to be connected to the RF chips to receive the RF output signals; and a resistive load coupled to a first end of the transmission line. A second end of the transmission line is arranged to output an accumulated RF output signal of the RF output signals. Effects of the invention

[0006] The proposed configuration of a phased array antenna and RF chip enables transmitters and receivers to be manufactured at a lower cost and operate with less power. Device reliability can also be improved. Brief explanation of the drawing

[0007] Aspects of the present invention are best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industry practice, various features are not drawn to scale. In fact, for clarity of discussion, the size of various features may be arbitrarily increased or decreased. FIG. 1 is a schematic diagram showing a wireless communication system of a next-generation communication scenario according to some embodiments of the present invention. 2a is a schematic perspective view of a transmitter or receiver of a user device according to some embodiments. 2b is a partial enlarged view of the transmitter or receiver shown in FIG. 2a according to some embodiments. 2c is a schematic cross-sectional view of a transmitter or receiver shown in FIG. 2b according to some embodiments. FIG. 3a is a schematic block diagram of a transmitter according to some embodiments. FIG. 3b is a schematic block diagram of the transmitter array of FIG. 3a according to some embodiments. FIG. 3c is a schematic block diagram of a transmitter block of a transmitter array shown in FIG. 3b according to some embodiments. FIG. 3d illustrates a schematic block diagram of the RF chip shown in FIG. 3c and an equivalent circuit of the input of the RF chip according to some embodiments. FIG. 4a is a schematic block diagram of a receiver according to some embodiments. FIG. 4b is a schematic block diagram of a receiver array of FIG. 4a according to some embodiments. FIG. 4c is a schematic block diagram of a receiver block of a receiver array shown in FIG. 4b according to some embodiments. FIG. 4d illustrates a schematic block diagram of the RF chip shown in FIG. 4c and an equivalent circuit of the input of the RF chip according to some embodiments. Specific details for implementing the invention

[0008] The following disclosure provides many different embodiments or examples to embody different features of the subject matter provided. Specific examples of components and arrangements are described below to simplify the disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first feature on or above a second feature may include embodiments in which the first feature and the second feature are formed in direct contact, and may also include embodiments in which an additional feature may be formed between the first and second features, so that the first and second features may not be in direct contact. Furthermore, the present invention may repeat reference numbers and / or letters in various examples. Such repetition is for simplicity and clarity and does not imply a relationship between the various embodiments and / or configurations discussed by themselves.

[0009] Additionally, spatially relative terms such as "beneath," "below," "lower," "above," and "upper" may be used herein for convenience of description to explain the relationship of one element or feature to other elements or features depicted in the drawings. Spatially relative terms are intended to include different directions of the device in use or operation in addition to the directions depicted in the drawings. The device may be oriented in a different direction (rotated 90 degrees or in a different direction), and the spatially relative descriptors used herein may likewise be interpreted accordingly.

[0010] Although the numerical ranges and parameters presenting the broad scope of the invention are approximations, the numerical values ​​described in specific embodiments are reported as accurately as possible. However, all figures inherently contain certain errors that inevitably arise due to deviations typically found in each test measurement. Additionally, the terms “about,” “substantial,” or “substantially” as used herein generally mean within 10%, 5%, 1%, or 0.5% of a given value or range. Alternatively, the terms “about,” “substantial,” or “substantially” mean within the acceptable standard error of the average as considered by those skilled in the art. Except for examples of operation / operation or unless otherwise specified, all numerical ranges, quantities, values, and percentages disclosed herein, such as quantities of material, periods of time, temperatures, operating conditions, ratios of quantities, etc., should be understood to be modified in all cases by the terms “about,” “substantial,” or “substantially.” Accordingly, unless otherwise indicated, the numerical parameters described in this specification and the appended claims are approximations that may vary as desired. At a minimum, each numeric parameter must be interpreted with respect to the reported significant digits and by applying standard rounding techniques. Ranges may be expressed herein from one endpoint to another or between two endpoints. All ranges disclosed herein include endpoints unless otherwise specified.

[0011] As used herein, the term "connected" may be interpreted as "electrically connected," and the term "combined" may be interpreted as "electrically combined." "Connected" and "combined" may also be used to indicate that two or more elements cooperate or interact with each other.

[0012] FIG. 1 is a schematic diagram illustrating a wireless communication system (10) in a next-generation communication scenario according to some embodiments of the present invention. The wireless communication system (10) includes one or more user devices (12, 14, 16 and 18), a ground base station (22), and a non-ground base station (24). In some embodiments, the user devices (12, 14) are carried and moved by a human and are referred to as handheld devices. In some embodiments, the user device (16) is a mobile device mounted on a vehicle moving on land, such as a car or a train. In some embodiments, the user device (118) is a user device mounted on a vessel moving in the sea, a river, etc.

[0013] In some embodiments, the ground base station (22) is an example of a base station deployed in a communication network such as a cellular communication network. The ground base station (22) is configured to provide a communication network to user devices (12, 14, 16), and the user devices (12, 14, 16) can transmit and receive information to and from each other through a network established by a plurality of ground base stations (22). The ground base station (22) may also be referred to as a low-altitude platform. In some embodiments, the non-ground base station (24) is an example of a communication satellite deployed in a communication satellite network. The non-ground base station (24) is configured to provide a communication network to user devices (12, 14, 16, 18), and the user devices (12, 14, 16, 18) can transmit and receive information to and from each other through the satellite network. A plurality of ground base stations (22) and a plurality of non-ground base stations (24) can be connected to each other to form an integrated communication network, and a global communication network can be implemented to cover the entire world regardless of whether the user device is located at a low altitude location, a high altitude location, or any location not covered by the ground base station (22).

[0014] To achieve the goal of a global communication network exemplified by a wireless communication system (10), user devices (12, 14, 16, or 18) may need to be redesigned to include a transmitter or receiver with greater communication capability to communicate with a non-ground base station (24) located high in the sky. Among various transmitter or receiver designs, phased array antenna technology is a promising solution for implementing beamforming technology that can significantly increase transmitter or receiver gain with higher reliability and is suitable for satellite communication.

[0015] FIG. 2a is a schematic perspective view of a transmitter (100) of a user device (12, 14, 16 or 18) illustrated in FIG. 1 according to some embodiments. In some embodiments, the transmitter (100) is an RF transmitter. In some embodiments, the transmitter (100) includes a control circuit board (110), an RF circuit board (120), and a connection circuit board (130) that electrically connects the RF circuit board (120) to the control circuit board (110). Additionally, the RF circuit board (120) includes an antenna array formed by an array of antenna elements (140), such as antenna patches formed on a substrate of the RF circuit board (120). In some embodiments, the transmitter (100) is applicable to a ground base station (22) or a non-ground base station (24).

[0016] In some embodiments, the control circuit board (110) is a printed circuit board (PCB) and includes a substrate on which a plurality of circuit chips and routings are formed. In some embodiments, the control circuit board (110) includes one or more semiconductor dies, for example, a semiconductor die (150) mounted on the surface of the control circuit board (110). The substrate of the control circuit board (110) may be formed of an epoxy resin including a metal (e.g., copper) foil. The control circuit board (110) generates control signals and data signals and provides them to the RF circuit board (120) through the connection circuit board (130). The data signal may be a baseband signal or an intermediate-frequency (IF) signal modulated by a modulation carrier of a predetermined frequency, for example, 455 kHz. In some embodiments, the control circuit board (110) is configured to convert a first voltage potential to a second voltage potential and transmit an appropriate supply voltage to the RF circuit board (120). In some embodiments, the connection circuit board (130) includes a flexible or inflexible substrate and includes a plurality of transmission lines configured to transmit a supply voltage, a control signal, and an IF data signal to an RF circuit board (120).

[0017] In some embodiments, user devices (12, 14, 16 and 18) also have a receiver (not separately shown) that functions in conjunction with a transmitter (100) to achieve bidirectional communication. The configuration of the transmitter (100) shown in FIG. 2a may also be applied to a receiver (101) (see FIG. 4a) having a control circuit board (111), an RF circuit board (121), and a connection circuit board (130) interconnected in a manner similar to that of the transmitter (100). User devices (12, 14, 16 and 18) may form a wireless communication system by including both the transmitter (100) and the receiver (101). Differences between the transmitter (100) and the receiver (101) will be described later.

[0018] FIG. 2b is an enlarged view of portion A1 of the RF circuit board (120) shown in FIG. 2a according to some embodiments. The vertical direction (positive Z-axis) of the RF circuit board (120) shown in FIG. 2b is opposite to that of FIG. 2a. In some embodiments, the RF circuit board (120) includes a substrate (202) and an interconnection structure (204) arranged on the substrate (202). The interconnection structure (204) has an upper surface, and the substrate (202) has a lower surface. In some embodiments, an array of antenna elements (206) is formed on the lower surface of the substrate (202), while a plurality of RF chips (208) are arranged on the upper surface of the interconnection structure (204). The RF chips (208) may be interconnected through a plurality of conductive lines. In some embodiments, the conductive lines (210) may be encapsulated by an electrical insulating material or exposed through the surface of the interconnection structure (204). In some embodiments, the antenna array of the transmitter (100) includes a patch antenna structure, and the antenna element (206) is an antenna patch of each antenna structure.

[0019] FIG. 2c is a schematic cross-sectional view of the RF circuit board (120) shown in FIG. 2b according to some embodiments. The schematic cross-sectional view shown in FIG. 2c is taken from the cutting line AA of FIG. 2b. Referring to FIG. 2c, the substrate (202) is formed of a transparent material such as glass, fused silica, silicon oxide, quartz, etc. In some embodiments, the substrate (202) separates the antenna element (206) from the electronic circuit of the interconnect structure (204) or the RF chip (208). In some embodiments, an RF signal is transmitted from the RF chip (208) formed on the upper surface of the substrate (202) through the RF circuit formed in the interconnect structure (204), radiates across the transparent substrate (202), and is coupled to the antenna element (206) formed on the lower surface of the substrate (202). In some embodiments, the thickness of the substrate (202) is determined based on the operating frequency of the antenna element (206). Since the material of the substrate (202) is transparent to RF signals, the substrate (202) may not have any conductive member for connecting the interconnection structure (204) to the antenna element (206).

[0020] In some embodiments, the interconnection structure (204) is formed in a stack of a plurality of metallization layers. The metallization layers include patterned conductive lines or conductive vias, and these patterned conductive lines and vias are patterned or electrically interconnected to form an interconnection path and other parts of the antenna. For example, a first metallization layer formed on a substrate (202) includes a first conductive line or pad (222A). The first conductive line or pad (222A) can be used as a ground plate, and the remaining space can be formed as an opening for connecting an RF signal to an antenna element (206). A second metallization layer is formed on the first metallization layer and includes a first conductive via comprising an exemplary first conductive via (224A). Likewise, a third metallization layer is formed on the second metallization layer and includes a second conductive line or pad (222B), and a fourth metallization layer is formed on the third metallization layer and includes a plurality of second conductive vias comprising an exemplary second conductive via (224B). The second conductive line may be patterned to form a power line or a signal transmission line. A fifth metallization layer is formed on the fourth metallization layer and includes a third conductive line (222C). The third conductive line (222C) may be patterned to form a transmission line for communicating an RF signal or a control signal between RF chips (208). In some embodiments, the conductive lines (222A, 222B, 222C) are interconnected through conductive vias (224A and 224B). In some embodiments, a plurality of conductive lines (210) are arranged on the sixth metallization layer and electrically connect the conductive lines (222C) to the RF chips (208).

[0021] In some embodiments, the conductive lines (222A, 222B, 222C, and 210) and the conductive vias (224A and 224B) are formed of a conductive material such as copper, tungsten, aluminum, titanium, tantalum, alloys thereof, etc. The conductive lines (222A, 222B, 222C) and the conductive vias (224A, 224B) are further electrically insulated by an insulating material (226A, 226B, or 226C), such as a polymer-based material such as polyimide or epoxy resin.

[0022] FIG. 3a is a schematic block diagram of the transmitter (100) illustrated in FIG. 2a according to some embodiments. Referring to FIG. 2a and FIG. 3a, in some embodiments, the control circuit board (110) includes a power conversion module (312), a memory module (314), a controller (316), a local oscillator module (318), and a data processing module (322). The control circuit board (110) is configured to provide a supply voltage (VD), an IF data signal (IF_in), a reference frequency signal (LO), and control signals (including correction data (Din), a data clock signal (CLK), and a synchronization clock signal (SYNC)) to the RF circuit board (120) through input / output ports on both sides of the connection circuit board (130) of the RF circuit board (120) and signal lines of the connection circuit board (130).

[0023] In some embodiments, the power conversion module (312) is configured to receive input power from a supply voltage source (302) outside the control circuit board (110). The power conversion module (312) may include a voltage converter configured to convert the initial supply voltage of the supply voltage source (302), e.g., 110 volts, to a supply voltage (VD) for the components of the RF circuit board (120), e.g., 5 volts or 1.2 volts. The power conversion module (312) may additionally supply power to other components of the control circuit board (110), such as a memory module (314), a controller (316), a local oscillator module (318), and a data processing module (322). In some embodiments, the power conversion module (312) further includes an electromagnetic interference filter for filtering interference.

[0024] In some embodiments, the memory module (314) is configured to store data and commands, such as transmission data, that are accessible by the controller (316) and the data processing module (322). The memory module (314) may include other types of memory, such as random access memory (RAM), read-only memory (ROM), flash memory, cache memory, etc.

[0025] In some embodiments, the controller (316) is configured to generate an IF data signal (IF_in) by modulating the transmission data with an IF modulation carrier. The transmission data may be provided by a data processing module (322). The IF data signal (IF_in) will be upconverted into an RF signal (RF_in) by an RF circuit board (120).

[0026] In some embodiments, the controller (316) is further configured to generate control signals for correcting RF signals, such as correction data (Din), a data clock signal (CLK), and a synchronization clock signal (SYNC). In some embodiments, the correction data (Din) is used to correct the amplitude or phase of the RF signal (RF_in) according to the transmitted data or command. The correction data may include amplitude correction data or phase correction data, or both. In some embodiments, the data clock signal (CLK) is used to provide a general clock to the registers of the components of the RF circuit board (120). The frequency of the data clock signal (CLK) may represent the operating frequency of digital data processing in the RF circuit board (120). In some embodiments, the synchronization clock signal (SYNC) is used to provide a clock to some registers of different stages to output the correction data at the same clock time. The synchronization clock signal (SYNC) may represent the update rate of the correction data. In some embodiments, the control signals are also referred to as digital control signals because they include a digital form.

[0027] The local oscillator module (318) is configured to generate a reference frequency signal (FR) for up-conversion or down-conversion between an IF signal (IF_in) and an RF signal (RF_in). In some embodiments, the local oscillator module (318) includes a crystal oscillator configured to generate a reference frequency signal (FR) of a predetermined frequency.

[0028] In some embodiments, the data processing module (322) is configured to receive input data or commands from a control unit (304) outside the control circuit board (110). The data processing module (322) may also be configured to transmit output data provided by the controller (316). In some embodiments, the data processing module (322) includes a network interface circuit configured to receive or transmit data or commands under a transmission protocol. The data processing module (322) may be configured to extract transmission data or control signals from the input data.

[0029] In some embodiments, the RF circuit board (120) includes a pair of RF signal generation paths, a pair of power divider networks (342), and two rows of transmitter arrays (300). Each RF signal generation path includes an IF signal receiver (332), a phase-locked loop module (334), amplifiers (335, 338), and a mixer (336).

[0030] In some embodiments, each power divider network (342) is connected to the output of a corresponding mixer (336) and configured to transmit an RF signal (RF_in) to each RF chip (208) (see FIG. 3c). In some embodiments, the power divider network (342) is a multi-stage power divider network formed by a plurality of power dividers (344) connected in a tree structure or a binary structure. In some embodiments, the power divider network (342) includes two stages (K1 and K2), and Each power divider (344) of stage K1 or K2 is configured to distribute the power of the RF signal (RF_in) substantially equally to the two outputs of the power divider (344). Each output of the power divider (344) in stage K2 is connected to a corresponding transmitter array (300). In some embodiments, the left power divider network (342) and the right power divider network (342) are arranged symmetrically with respect to the center line between the left and right power divider networks (342). In some embodiments, the left column of the transmitter array (300) and the right column of the transmitter array (300) are arranged symmetrically with respect to the center line between the left column and the right column of the power divider network (342). In some embodiments, the power divider (344) may also be used as a power combiner in a receiver architecture, wherein the input and output terminals of the power divider (344) are inverted to the output and input terminals of the power combiner.

[0031] In some embodiments, control signals including correction data (Din), a data clock signal (CLK), and a synchronization clock signal (SYNC) are provided to each of the transmitter arrays (300) via a bus or a plurality of signal lines. In some embodiments, the illustrated embodiment shows only a two-stage power divider network (342). However, power divider networks (342) greater or smaller than two stages may also be applied to the transmitter (100) in other embodiments. In some embodiments, the illustrated embodiment shows only four transmitter arrays (300) in one column of the transmitter array (300). However, a number of transmitter arrays (300) greater or smaller than four may also be applied to the transmitter (100) in other embodiments, where the number of transmitter arrays (300) is scaled to the number of stages of the power divider network (342).

[0032] In some embodiments, an IF signal receiver (332) is configured to receive an IF data signal (IF_in) from a connection circuit board (130). A phase-locked loop module (334) may be configured to generate a local oscillator signal (LO) based on a reference frequency (FR) through a phase-locking loop. In some embodiments, the local oscillator signal (LO) is amplified through an amplifier (335). In some embodiments, the amplifier (335) is an operational amplifier. A mixer (336) is configured to up-convert the IF signal (IF_in) to an RF signal (RF_in) at a predetermined operating frequency, e.g., 18 GHz, 28 GHz, or other suitable frequency. In some embodiments, the RF signal (RF_in) is amplified through an amplifier (338). In some embodiments, the amplifier (338) is an operational amplifier. In some embodiments, more control signals, such as phase-locked loop control signals, are provided from the control circuit board (110) to the phase-locked loop module (334).

[0033] FIG. 3b is a schematic block diagram of a transmitter array (300) of the transmitter (100) shown in FIG. 3a according to some embodiments. In some embodiments, the transmitter array (300) includes another power divider network (346) and a plurality of transmitter blocks (310). In some embodiments, the power divider network (346) forms a power divider network combined with a power divider network (342), wherein the final stage (K) of the power divider network (346) N in ) The power divider (344) is connected to the corresponding transmitter block (310). In some embodiments, the power divider network (346) includes N-2 stages, and each power divider (344) of each stage is configured to distribute power of the RF signal (RF_in) at the input terminal substantially equally to the two output terminals of the power divider (344). In some embodiments, the supply voltage (VD) and control signals (Din, CLK, and SYNC) are also provided to each of the transmitter blocks (310) via a bus or a plurality of signal lines.

[0034] FIG. 3c is a schematic block diagram of a transmitter block (310) of a transmitter array (300) illustrated in FIG. 3b according to some embodiments. In some embodiments, the transmitter block (310) is formed by rows of RF chips (208) and rows of antenna feed lines (212) corresponding to the rows of RF chips (208). In some embodiments, as described above with reference to FIG. 2b, each RF chip (208) includes an individual RF circuit and is also referred to as an RF circuit (208). In some embodiments, the RF chip (208) is configured as a transmitter (TX) RF chip. In some embodiments, a supply voltage (VD) is provided and transmitted to each RF chip (208). Additionally, control signals including correction data (Din), a data clock signal (CLK), and a synchronization clock signal (SYNC) are supplied to each RF chip (208) through one or more signal lines. In some embodiments, the RF signal (RF_in) is also supplied to each RF chip (208) through a transmission line (220). Referring to FIGS. 2b and FIGS. 3c, in some embodiments, the RF signal (RF_in) is transmitted to an antenna patch (206) through a transmission line (220), an RF chip (208) (output as RF signal (RF_out)), a supply line (212), and a substrate (202), and is radiated outward by the antenna patch (206).

[0035] The RF chip (208) is configured to generate a corrected RF signal as an RF output signal (RF_out) after the correction of the RF signal (RF_in) according to the correction data (Din) is performed. In some embodiments, the update rate of the correction is controlled by a data clock signal (CLK) and a synchronization clock signal (SYNC). In some embodiments, the RF chip (208) includes input ports for each RF signal (RF_in), supply voltage (VD), correction data (Din), data clock signal (CLK), and synchronization clock signal (SYNC). In some embodiments, the RF chip (208) includes output ports for each correction data (Dout) and two branches of the RF output signal (RF_out), namely RF component signals (RF_out_I and RF_out_Q).

[0036] In some embodiments, the RF output signal (RF_out) consists of an in-phase component (RF_out_I) and an orthogonal component (RF_out_Q) corresponding to the horizontal (H) polarization component and the vertical (V) polarization component, respectively. The separate components (RF_out_I and RF_out_Q) represent the in-phase component (RF_out_I) and the orthogonal component (RF_out_Q) and are orthogonal to each other. The individual orthogonal components of the RF output signal may aid in the correction of the RF signal (RF_in) or the RF output signal (RF_out).

[0037] In some embodiments, the data clock signal (CLK) and the synchronization clock signal (SYNC) are supplied to the respective input ports for the data clock signal (CLK) and the synchronization clock signal (SYNC) of the RF chip (208). In some embodiments, the correction data (Din) is transmitted from the input port of the correction data (Din) to the first (leftmost) RF chip (208) via a signal line, and the first RF chip (208) relays the correction data (Din) from the output port (Dout) of the first RF chip (208) to the second RF chip (208) adjacent to the first RF chip (208) via another signal line. Subsequently, the correction data (Din) is transmitted to the input port (Din) of the correction data (Din) of the third RF chip (208). As a result, the correction data (Din) is transmitted through the input and output ports of the serially connected (cascaded) RF chips (208) to the last (rightmost) RF chip (208). Data reading timing can be controlled by a data clock signal (CLK) and a synchronization signal (SYNC).

[0038] In some embodiments, the transmitter block (310) includes a transmission line (220) between a first end, i.e., an input port of the transmitter block (310), and a second end of the transmission line (220). In some embodiments, the second end of the transmission line (220) is connected to ground through a resistive load (372). In some embodiments, the transmission line (220) is a line comprising a number of line segments extending in a straight line or in different directions. In some embodiments, the transmission line (220) is parallel to a row of RF chips (208). The resistive load (372) may include a resistor. In some embodiments, the resistance of the resistive load (372) is determined to match the impedance of the transmission line (220) to eliminate signal reflection. In some embodiments, the resistive load (372) includes a resistance of about 50 ohms.

[0039] In some embodiments, the RF signal (RF_in) is propagated from the first end to the second end of the transmission line (220). In some embodiments, in a phased array antenna configuration, adjacent antenna supply lines (212) are spaced apart by a predetermined antenna spacing. The antenna spacing may be related to the wavelength of the RF signal (RF_in). Additionally, the RF output signals (RF_out_I, RF_out_Q) transmitted by the individual antenna supply lines (212) must be modulated with an appropriate phase delay according to the phase adjustment data of the correction data (Din) to collectively form a directional RF signal beam. Accordingly, each RF output component signal (RF_out_I and RF_out_Q) is phase-modulated according to one or more design criteria, such as its position in the antenna array.

[0040] In some embodiments, the RF chips (208) may not be arbitrarily arranged on the interconnect structure (204). In some embodiments, a row of RF chips (208) within the same transmitter block (310) is connected to a connection terminal of the transmission line (220) at different locations on the transmission line (220), where index ( i) represents the i-th RF chip (208) of the transmitter block (310), and 1 <i<=L이고, 여기서 L은 1보다 큰 임의의 정수일 수 있다. 일부 실시예에서, 숫자 L은 2와 8 사이의 범위에 있다. 위치(Di)는 소정의 거리만큼 이격되어 있다. 일부 실시예에서, RF 칩(208)은 전송 라인(220)의 제1 단부와 제2 단부 사이에 균등하게 분포된다. 신호 전송 라인(220)을 사용하는 송신기 블록(310) 내의 RF 칩(208)의 신호 공급 방식은 "직렬 공급(series-feed)" 신호 공급 방법이라고 지칭된다. RF 신호(RF_in)는 전송 라인(220)의 상이한 위치(D1, D2 ,... D7,...DL) 간에 위상차를 가질 수 있다. 상이한 위치(D1 내지 DL)에 의해 야기되는 바람직하지 않은 위상 지연은 보정 데이터(Din)의 위상 조정 데이터에 의해 동시에 어드레싱되고 보상될 수 있다. 결과적으로 위상 배열 안테나의 위상 부정확성 문제가 추가 비용 없이 해결될 수 있다.

[0041] The common-mode RF signal (RF_out_I) and the quadrature RF signal (RF_out_Q) are coupled to the antenna patch (206) and combined to be radiated outward through the antenna patch (206). The combined RF signal (RF_out) based on the common-mode RF signal (RF_out_I) and the quadrature RF signal (RF_out_Q) results in a circularly polarized RF signal (RF_out). In some embodiments, the combined RF signal (RF_out) is a right-circularly polarized RF signal or a left-circularly polarized RF signal that depends on the phase order of the common-mode RF signal (RF_out_I) relative to the quadrature RF signal (RF_out_Q). In some embodiments, the validity of the correction data (Din) plays an important role because the ideal circular polarization of the RF signal output (RF_out) is achieved with the same amplitude and an exact phase difference of 90 degrees between the common-mode RF signal (RF_out_I) and the quadrature RF signal (RF_out_Q). In some embodiments, the common-mode RF signal (RF_out_I) and the quadrature RF signal (RF_out_Q) are split and independently receive amplitude correction and phase correction before being transmitted to the antenna patch (206). Additionally, in some embodiments, the common-mode RF signal (RF_out_I) and the quadrature RF signal (RF_out_Q) are received from the antenna patch (206) and independently receive amplitude correction and phase correction at the RF chip (208) before being combined and transmitted to the RF chip (208). Thus, the correction operation can be easily performed without complex correction circuits.

[0042] In some embodiments, the RF chip (208) is designed to include an input terminal or input port having a high impedance. For example, the input impedance (Rin) of the RF chip (208), viewed from the transmission line (220) to the RF chip (208) through the input terminal (208A) or input port of the RF chip (208), is relatively high, for example, greater than about 100K ohms, greater than 500K ohms, or greater than 1000K ohms.

[0043] FIG. 3d illustrates a schematic block diagram of the RF chip (208) shown in FIG. 3c according to some embodiments in the lower left drawing. In some embodiments, the input port (208A) of the RF chip (208) is connected to a field-effect transistor (FET) (M1), for example, a metal-oxide-semiconductor FET (MOSFET), where the gate terminal (M1G) or gate electrode is connected to a transmission line (220) via a branch transmission line (221). In some embodiments, the MOSFET (M1) is connected to the input port (208A) of the RF chip (208) via a capacitor (Cp1). In some embodiments, the capacitor (Cp1) is connected to diodes (D11 and D12) of the RF chip (208) at the gate terminal (M1G). Referring to the right lower figure of FIG. 3d, the circuit of the RF chip (208) connected to the input port (208A) shown in the left lower figure can be represented as an equivalent circuit formed by a capacitor (Cp) connected in parallel with the input resistance (Rp). In some embodiments, the input resistance Rp (or Rin) or input impedance of the RF chip (208) viewed from the gate terminal (M1G) of the RF chip (208) is substantially at least 10 times the impedance viewed from the input terminal (208A) connected to the transmission line (220) toward the transmission line (220), for example, at least about 500 ohms. In some embodiments, the input resistance (Rp), which is equal to the input resistance (Rin) shown in FIG. 3c, is at least 500 ohms, 1000 ohms, or 5000 ohms. In some embodiments, to maintain the high impedance characteristics of the input port (208A) of the RF chip (208), the MOSFET arranged at the input port (208A) of the RF chip (208) is not connected in parallel to other circuits of the RF chip (208). In some embodiments, there is no intermediate circuit, matching network, or buffering circuit between the branch line (221) and the gate terminal (M1G) of the RF chip (208).In some embodiments, the above-described serial signal feeding method of the RF signal (RF_in) is implemented through a voltage-driven signal feeding type. The RF output signal (RF_out) is generated based on a voltage signal transmitted from the gate terminal (M1G) of the input MOSFET (M1), rather than a current-driven signal.

[0044] Based on the above description, the proposed serial signal supply method offers advantages. The current level flowing to the input port (208A) of the RF chip (208) is very low due to the high impedance characteristics of the MOSFET when leakage current can be well managed. Therefore, the power consumption of the RF chip (208) will be relatively low without compromising device performance. Furthermore, an additional phase correction module for the transmitter block (310) is not required to assist in the correction of the RF signal (RF_in) because the correction data of the control signal already includes the phase correction data of the phase array antenna architecture, where the adjustment of the delayed phase also covers phase adjustment or correction.

[0045] Conventional RF chips adopt a current-driven signal supply method for transmitting RF signals, provided with a tree-type power divider network. Each power divider at the final stage of the tree-type power divider network is connected to a corresponding RF chip. Input ports are designed to comply with impedance matching rules, such as having an impedance of approximately 50 ohms. The driving current flows from the RF signal source to each RF chip through the tree-type power divider network. This RF signal supply architecture consumes power when the RF signal is distributed from the end point of the power divider network to the RF chip. Although RF chips in a current-driven signal supply method may have less phase error than voltage-driven signal supply methods because the transmission length of all RF chips with respect to the RF signal source is substantially the same, process-induced device variations still often lead to phase differences that cannot be ignored. Therefore, a phase correction module is typically required to guarantee the performance of a phase array antenna. Conversely, the proposed voltage-driven signaling scheme requires fewer power dividers while consuming less power and not compromising device performance. Therefore, the power, cost, and reliability of the transmitter can be improved through the proposed antenna array structure.

[0046] In some embodiments, the series-feed signaling method of the present invention further aids in routing efficiency. As illustrated in FIGS. 3a, 3b and 3c, the transmitter array (300) (including RF chips (208)) is arranged in a column direction in the central part of the RF circuit board (120), while peripheral circuits, e.g., power divider networks (342 and 346), amplifiers (335, 338) and mixer (336), are arranged on both sides of the RF circuit board (120). The one-dimensional array of the transmitter block (310) extends in a row direction, and the antenna spacing and the number of RF chips determine the length-to-width ratio of the transmitter block (310). For example, if stage number N=5 and RF chip number L=8 are taken in the transmitter block (310), the resulting transmitter array of the transmitter (100) formed as the transmitter array (300) is a square shape with a size of 32 x 32 RF chips (208). In addition, when routing power and signal transmission lines, such as supply voltage (VD), control signals (Din, CLK, SYNC) and RF signals (RF_in) of the transmitter block (310), the percentage of wiring crossing is relatively low due to its row shape. Consequently, a square phased antenna array can be implemented with high routing efficiency. Furthermore, the phased antenna of the present invention can be scaled up or down in a simple manner by simply adjusting the numbers N and L without the need to rework the placement and routing.

[0047] FIG. 4a is a schematic block diagram of a receiver (101) according to some embodiments. In some embodiments, the receiver (101) is an RF receiver. In some embodiments, the receiver (101) is shown as a reciprocal device of the transmitter (100), wherein the receiver (101) also includes a control circuit board (111), an RF circuit board (121), and a connection circuit board (130) connecting the control circuit board (111) to the RF circuit board (121). To facilitate duplex transmission, the operating frequency of the receiver (101) may differ from that of the transmitter (100), for example, one of the transmitter (100) and the receiver (101) is configured to operate at a frequency of 18 GHz, while the other is configured to operate at a frequency of 28 GHz. Device design parameters for the transmitter (100) and the receiver (101) may differ due to the different operating frequencies. In some embodiments, the receiver (101) can be applied to a user device (12, 14, 16, 18), a ground base station (22), or a non-ground base station (24).

[0048] In some embodiments, the control circuit board (111) includes a power conversion module (312), a memory module (314), a controller (317), a local oscillator module (318), and a data processing module (323). In some embodiments, additional modules may be added to the control circuit board (111), or some of the modules described above may be omitted or replaced with other modules. The functions and configurations of the connection circuit board (130), the power conversion module (312), the memory module (314), and the local oscillator module (318) are as described with reference to FIG. 3a, and thus details are not repeated here for the sake of simplification.

[0049] In some embodiments, the controller (317) is configured to control the demodulation of the receiver signal. In some embodiments, the receiver signal generated by the control circuit board (111) takes the form of an IF input signal as IF_out, which will be down-converted into a baseband signal by the controller (317) or the data processing module (323). In some embodiments, the controller (317) is powered by an external power source or a power conversion module (312) and receives an IF signal (IF_out) according to receiver data (IF_out) provided by the RF circuit board (121). In some embodiments, the controller (317) is configured to generate control signals for the phase array antenna, such as correction data (Din), a data clock signal (CLK), and a synchronization clock signal (SYNC).

[0050] In some embodiments, the data processing module (323) illustrated in FIG. 4a is configured to receive commands from a control unit (304) outside the control circuit board (110). The data processing module (323) or controller (317) may be configured to receive transmission data extracted from a received IF signal (IF_out) provided by the RF circuit board (121) and to transmit the transmission data to the control unit (304).

[0051] The RF circuit board (121) includes a pair of RF signal receiving paths, a pair of power combiner networks (352), and two rows of receiver arrays (301). Each RF signal receiving path shown in FIG. 4a proceeds in a manner reciprocal with the RF signal generating path shown in FIG. 3a. In some embodiments, the left row of receiver arrays (301) and the right row of receiver arrays (301) are arranged symmetrically with respect to the centerline between the left row and the right row of receiver arrays (301). In some embodiments, the left power combiner network (352) and the right power combiner network (352) are arranged symmetrically with respect to the centerline between the left power combiner network (352) and the right power combiner network (352). In some embodiments, each RF signal receiving path includes an IF signal receiver (362), a phase-locked loop module (334), amplifiers (335, 338), and a mixer (336). In some embodiments, an IF signal receiver (332) is configured to receive an IF signal (IF_out) from the output of a mixer (336). A phase-locked loop module (334) may be configured to generate a local oscillator signal (LO) based on a reference frequency (FR) through a phase-locked procedure. In some embodiments, the local oscillator signal LO is amplified through an amplifier (335). In some embodiments, the amplifier (335) is an operational amplifier. The mixer (336) is configured to down-convert an RF signal (RF_out) to an IF signal (IF_out) in a predetermined frequency band, e.g., 445 kHz. In some embodiments, the RF signal (RF_out) is amplified through an amplifier, e.g., an operational amplifier.

[0052] In some embodiments, a power combiner network (352) is connected to the input of a mixer (336) and configured to collect RF signals (RF_out) from each RF chip (208) (see FIG. 4c) into a combined RF data signal (RF_out). The power combiner network (352) shown in FIG. 4a is a multi-stage power combiner network similar to the power divider (342) shown in FIG. 3a, except that the input and output terminals are reversed. In some embodiments, control signals including correction data (Din), a data clock signal (CLK), and a synchronization clock signal (SYNC) are provided to each of the receiver arrays (301) via a bus or a plurality of signal lines.

[0053] FIG. 4b is a schematic block diagram of a receiver array (301) of the receiver (101) shown in FIG. 4a according to some embodiments. In some embodiments, the receiver array (301) includes another power combiner network (356) and a plurality of receiver blocks (311). In some embodiments, the power combiner network (356) shown in FIG. 4b is similar to the power divider network (346) shown in FIG. 3b, except that the input and output terminals are reversed. In some embodiments, control signals including supply voltage (VD) and correction data (Din), data clock signal (CLK) and synchronization clock signal (SYNC) are also provided to each receiver block (311) via a bus or a plurality of signal lines.

[0054] FIG. 4c is a schematic block diagram of a receiver block (311) of a receiver array (301) illustrated in FIG. 4b according to some embodiments. In some embodiments, the receiver block (311) is formed by a row of RF chips (209) and a row of antenna supply lines (213) corresponding to the row of RF chips (209). In some embodiments, as described above with reference to FIG. 2b, each RF chip (209) includes an individual RF circuit and is also referred to as an RF circuit (209). In some embodiments, the RF chip (209) is configured as a receiver (RX) RF chip. In some embodiments, a supply voltage (VD) is provided to and transmitted to each RF chip (209). Additionally, a control signal including correction data (Din), a data clock signal (CLK), and a synchronization clock signal (SYNC) is supplied to each RF chip (209). Referring to FIG. 2b and FIG. 4c, in some embodiments, an RF signal (RF_in) is received by an antenna patch (206) and transmitted to a signal port (RF_in) through a substrate (202), a supply line (213), an RF chip (209) (output as an RF signal (RF_out)) and a transmission line (220).

[0055] The RF chip (209) is configured to provide a corrected RF signal (RF_out) from an RF input signal (RF_in) on an antenna supply line (213) according to the correction data (Din). In some embodiments, the update rate of the correction is controlled by a data clock signal (CLK) and a synchronization clock signal (SYNC). In some embodiments, the RF chip (209) includes input ports for the respective in-phase RF signal component (RF_in_I) and orthogonal RF signal component (RF_in_Q), supply voltage (VD), correction data (Din), data clock signal (CLK), and synchronization clock signal (SYNC). In some embodiments, the RF chip (209) includes output ports (Dout) for the respective correction data and RF signal (RF_out). The function and configuration of the correction data (Din), data clock signal (CLK), and synchronization clock signal (SYNC) are similar to those described with reference to FIGS. 3a through 3c, and details are not repeated herein.

[0056] In some embodiments, the receiver block (311) includes a transmission line (220) between the first end, i.e., the output port of the receiver block (311), and the second end of the transmission line (220). In some embodiments, the second end of the transmission line (220) is connected to ground through a resistive load (372). In some embodiments, the transmission line (220) is a line that includes a number of line segments extending in a straight line or in different directions. In some embodiments, the transmission line (220) is parallel to a row of RF chips (209). The resistive load (372) may include a resistor. In some embodiments, the resistance of the resistive load (372) is determined to match the impedance of the transmission line (220) to eliminate signal reflection. In some embodiments, the resistive load (372) includes a resistance of about 50 ohms.

[0057] In some embodiments, the provided RF signal (RF_out) propagates between the first and second ends of the transmission line (220). The RF signal provided by the individual antenna supply line (213) must be demodulated with an appropriate phase delay according to the phase adjustment data of the correction data (Din) to collectively form an accumulated constructive RF signal (RF_out). Thus, before the RF signal components (RF_in_I and RF_in_Q) are combined or before the individual RF signals (RF_out) are supplied to the transmission line (220), they are phase-demodulated according to one or more design criteria, such as their positions in the antenna array. In some embodiments, each RF signal (RF_out) is a current signal (I) supplied from the corresponding RF chip (209) to the corresponding connection terminal at a different position (Di) on the transmission line (220). out )am.

[0058] In some embodiments, the RF chip (209) has a current (I) of the RF signal (RF_out). out To maximize ), it is designed to include an output terminal having an impedance that matches the transmission line (220). For example, the output impedance of the RF chip (209) is about 50 ohms.

[0059] Referring to FIGS. 4a and 4b, the collected and combined RF signal (RF_out) is transmitted through power combiner networks (356 and 352) to reach a mixer (336) to perform down-conversion to an IF signal (IF_out). A phase-locked loop module (334) may be configured to generate a local oscillator signal (LO) based on a reference frequency (FR) through a phase-locking procedure. In some embodiments, an IF signal receiver (362) is configured to receive an IF data signal (IF_in) from the output of the mixer (336). In some embodiments, the local oscillator signal (LO) is amplified through an amplifier (335). In some embodiments, the amplifier (335) is an operational amplifier. The IF signal (IF_out) is transmitted to a control circuit board (110) through the IF signal receiver (362) and a connection circuit board (130). In some embodiments, the IF signal (IF_out) is down-converted to a baseband signal by the controller (317) or the data processing module (323), and the modulated transmission data in the RF signal (RF_out) is demodulated and detected from the baseband signal.

[0060] FIG. 4d illustrates, according to some embodiments, a schematic block diagram of the RF chip (209) shown in FIG. 4c and an equivalent circuit of the output of the RF chip (209). FIG. 4d illustrates, according to some embodiments, a schematic block diagram of the RF chip (209) shown in FIG. 4c as a lower left diagram. In some embodiments, the output terminal (209A) of the RF chip (209) or the output port of the RF chip (209) is formed by a FET (M2), wherein the drain terminal (D2) is connected to the transmission line (220) through a branch transmission line (221). In some embodiments, the output port (209A) of the RF chip (209) is designed to have a relatively high input impedance so that most of the output current (Iout) of the received RF signal (RF_out) provided from one RF chip (209) to the transmission line (220) does not flow back to another RF chip (209) of the same receiver block (311).

[0061] In some embodiments, the MOSFET (M2) is connected to the output port (209A) of the RF chip (209) through a capacitor (Cp1). In some embodiments, the capacitor (Cp1) is connected to the diodes (D21 and D22) of the RF chip (209) at the drain terminal (M2D). Referring to the right lower drawing of FIG. 4d, the circuit of the RF chip (209) connected to the input port (209A) shown in the left lower drawing can be represented as an equivalent circuit consisting of a capacitor (Cp) connected in parallel with the input resistance (Rp). In some embodiments, the input impedance or resistance (Rp) of the RF chip (209) viewed from the drain terminal (M2D) of the RF chip (209) is substantially 10 times greater than the input impedance viewed from the output terminal (209A) connected to the transmission line (220) toward the transmission line (220). In some embodiments, the input resistance (Rp) of the RF chip (209) is at least greater than or equal to 500 ohms, 1000 ohms, or 5000 ohms.

[0062] Based on the above, the proposed series-type signal accumulating method offers advantages. The current level flowing from one RF chip (209) to another RF chip (209) in the same receiver block (311) is very low due to the high impedance characteristics of the MOSFETs when leakage current can be well managed. Therefore, the power collection efficiency of the RF chip (209) will be relatively high without compromising device performance. Additionally, an additional phase correction module for the receiver block (311) is not required because the correction data of the control signal already includes the phase correction data of the phase array antenna architecture to help correct the RF signal (RF_in) (including the in-phase RF signal component (RF_in_I) and the quadrature RF signal component (RF_in_Q). Here, the adjustment of the delayed phase also covers phase adjustment or correction.

[0063] The foregoing outlines the features of various embodiments to enable those skilled in the art to better understand aspects of the invention. Those skilled in the art should recognize that the invention can be readily used as a basis for designing or modifying other processes and structures to perform the same purpose and / or achieve the same benefits of the embodiments described herein. Furthermore, those skilled in the art should recognize that such equivalent configurations do not depart from the spirit and scope of the invention, and that various changes, substitutions, and substitutions may be made in this specification without departing from the spirit and scope of this disclosure.

Claims

Claim 1 A wireless communication system comprising: a plurality of antennas; a plurality of RF chips arranged in a row and coupled to the antennas, for providing a plurality of radio frequency (RF) output signals to the antennas according to a single RF signal; a transmission line arranged in a straight line parallel to the row and wired to the RF chips to transmit the single RF signal to the plurality of RF chips; and a resistive load coupled to a first end of the transmission line; wherein a second end of the transmission line is arranged to receive the RF signal, and each RF chip comprises a metal oxide semiconductor field effect transistor (MOSFET), a capacitor, a first diode, and a second diode, wherein the MOSFET comprises a gate terminal that serves as an input terminal connected to the transmission line through the capacitor, and the first diode and the second diode are connected to the capacitor of the gate terminal. Claim 2 A wireless communication system according to claim 1, characterized in that the RF chips are arranged to be evenly distributed between a first end and a second end to be connected to the transmission line. Claim 3 A wireless communication system according to claim 1, characterized in that each RF chip is arranged to receive an RF signal by combining a voltage signal on a corresponding connection terminal of a transmission line. Claim 4 A wireless communication system according to claim 1, characterized in that the first impedance facing the gate terminal of the corresponding RF chip is 10 times greater than the second impedance facing the transmission line from the corresponding input terminal connected to the transmission line. Claim 5 A wireless communication system according to claim 1, further comprising a plurality of branch transmission lines, wherein each branch transmission line is coupled between the gate terminal of a corresponding RF chip and the transmission line. Claim 6 A wireless communication system according to claim 1, characterized in that the first diode and the second diode are arranged in a reverse bias configuration. Claim 7 A wireless communication system according to claim 1, further comprising a substrate having a first surface and a second surface facing the first surface, wherein the antenna is disposed on the first surface and a plurality of RF chips and transmission lines are disposed on the second surface. Claim 8 A wireless communication system according to claim 7, wherein the substrate is transparent. Claim 9 A wireless communication system according to claim 7, wherein the substrate is formed of glass, fused silica, or quartz. Claim 10 A wireless communication system according to claim 7, wherein the RF chip is configured to couple an RF signal to an antenna through a substrate, and the substrate has no conductive element between the RF chip and the antenna. Claim 11 A wireless communication system according to claim 1, further comprising a plurality of signal lines, wherein the signal lines are connected to an RF chip and configured to provide correction data for an RF signal. Claim 12 A wireless communication system according to claim 11, characterized in that the correction data includes at least one of amplitude correction data and phase correction data. Claim 13 A wireless communication system characterized in that, in claim 12, the above-mentioned phase correction data provides the phase delay of each RF chip for the phase array antenna method of the antenna. Claim 14 A wireless communication system comprising: a plurality of antennas; a plurality of RF chips arranged in a row and coupled to the antennas, for receiving a plurality of radio frequency (RF) signals from the antennas and outputting a plurality of RF output signals; a transmission line arranged in a straight line parallel to the row and connected to the RF chips by a wire to receive the RF output signals as a single accumulated RF output signal; and a resistive load coupled to a first end of the transmission line; wherein the second end of the transmission line is arranged to output a single accumulated RF output signal, and each RF chip comprises a metal oxide semiconductor field effect transistor (MOSFET), a capacitor, a first diode, and a second diode, wherein the MOSFET includes a drain terminal that serves as an output terminal connected to the transmission line through the capacitor, and the first diode and the second diode are connected to the capacitor of the gate terminal. Claim 15 A wireless communication system according to claim 14, characterized in that the RF chips are arranged to be evenly distributed between a first end and a second end to be connected to the transmission line. Claim 16 A wireless communication system according to claim 14, characterized in that each RF output signal is a current signal supplied from a corresponding RF chip to a corresponding connection terminal of a transmission line. Claim 17 A wireless communication system according to claim 14, characterized in that the first impedance facing the drain terminal of the corresponding RF chip is 10 times greater than the second impedance facing the transmission line from the corresponding output terminal connected to the transmission line. Claim 18 A wireless communication system according to claim 14, further comprising a plurality of branch transmission lines, wherein each branch transmission line is coupled between the drain terminal of a corresponding RF chip and the transmission line. Claim 19 A wireless communication system according to claim 14, characterized in that the first diode and the second diode are arranged in a reverse bias configuration. Claim 20 A wireless communication system according to claim 14, further comprising a substrate having a first surface and a second surface facing the first surface, wherein the antenna is disposed on the first surface and a plurality of RF chips and transmission lines are disposed on the second surface.

Images