Transparent display device

Abstract

The present invention can improve light transmittance in a transparent region and maximize a light-emitting region within a non-transparent region. A transparent display device according to one embodiment of the present invention comprises a substrate having a display region including a transparent region and a non-transparent region in which a plurality of subpixels are arranged, and a non-display region surrounding the display region; at least one insulating film provided on the substrate; anode electrodes provided on each of the plurality of subpixels on the at least one insulating film; a bank provided between the anode electrodes; a light-emitting layer provided on the anode electrodes; and a cathode electrode provided on the light-emitting layer. At least one insulating film and the bank are provided only in the non-transparent region.

Description

Technology Field

[0001] The present invention relates to a transparent display device. Background Technology

[0002] As the information society develops, the demand for display devices for displaying images is increasing in various forms. Accordingly, various display devices such as Liquid Crystal Displays (LCDs), Plasma Display Panels (PDPs), Quantum Dot Light Emitting Displays (QLEDs), and Organic Light Emitting Displays (OLEDs) are being utilized recently.

[0003] Meanwhile, research on transparent display devices that allow users to see objects or images located on the opposite side by passing through the display is currently being actively conducted.

[0004] A transparent display device includes a display area where an image is displayed and a non-display area; the display area may include a transparent area capable of transmitting external light and a non-transparent area. It is important for the transparent display device to have high light transmittance in the transparent area and to maximize the light-emitting area within the non-transparent area. The problem to be solved

[0005] The present invention has the technical objective of providing a transparent display device capable of improving light transmittance in a transmission region.

[0006] In addition, another technical objective of the present invention is to provide a transparent display device capable of maximizing the light-emitting area within a non-transmitting area.

[0007] In addition, the present invention has another technical objective of providing a transparent display device capable of preventing diffraction phenomena from occurring when external light passes through a transmission area. means of solving the problem

[0008] A transparent display device according to one embodiment of the present invention comprises a substrate having a display area including a transparent area and a non-transparent area in which a plurality of subpixels are arranged, and a non-display area surrounding the display area; at least one insulating film provided on the substrate; anode electrodes provided on each of the plurality of subpixels on the at least one insulating film; a bank provided between the anode electrodes; a light-emitting layer provided on the anode electrodes; and a cathode electrode provided on the light-emitting layer. At least one insulating film and the bank are provided only in the non-transparent area.

[0009] A transparent display device according to another embodiment of the present invention comprises a substrate having a display area including a transparent area and a non-transparent area in which a plurality of subpixels are arranged, and a non-display area surrounding the display area, a common power line provided on the substrate and extending in a first direction from the display area, and a pixel power line provided on the substrate and extending in the first direction from the display area. The transparent area is provided between the pixel power line and the common power line and includes a plurality of second curved portions. Effects of the invention

[0010] The present invention can improve the light transmittance of a transmission region by removing an insulating film with a high refractive index in the transmission region.

[0011] In addition, the present invention can prevent the occurrence of a yellowish phenomenon in the transmission area by removing the bank in the transmission area.

[0012] In addition, the present invention may alternately arrange common power lines and pixel power lines in a display area and provide a transparent area between the common power line and the pixel power line. Furthermore, the present invention may provide a first sub-pixel in an area where a gate line and a common power line intersect, a third sub-pixel in an area where a gate line and a pixel power line intersect, and a second sub-pixel between the first sub-pixel and the third sub-pixel. Accordingly, the present invention can improve transmittance by maximizing the transparent area.

[0013] In addition, the present invention may comprise an anode electrode provided in each of the first and third subpixels, comprising a first portion, a second portion protruding from one side of the first portion, and a third portion protruding from the other side of the first portion. In this case, the second portion and the third portion can prevent diffraction phenomena caused by the plurality of metal lines by covering the plurality of metal lines provided below.

[0014] In addition, the present invention can maximize the area of ​​the light-emitting region within the non-transmitting region by forming a second part and a third part on the anode electrode provided in each of the first and third subpixels.

[0015] In addition, the present invention can mitigate the concentration of light in a specific direction due to diffraction by providing a curved portion in the transmission area.

[0016] The effects obtainable from the present invention are not limited to those mentioned above, and other unmentioned effects will be clearly understood by those skilled in the art from the description below. Brief explanation of the drawing

[0017] FIG. 1 is a perspective view showing a display device according to one embodiment of the present invention. Figure 2 is a plan view schematically showing a transparent display panel. Figure 3 is an enlarged view of area A of Figure 2. FIG. 4a is a plan view showing the anode electrode, the first interlayer insulating film, the second interlayer insulating film, and the bank. Figure 4b is a plan view showing a color filter layer. Figure 5 is a cross-sectional view showing an example of II of Figure 3. Figure 6 is a cross-sectional view showing an example of II-II of Figures 4a and 4b. Figure 7 is a cross-sectional view showing an example of III-III of Figures 4a and 4b. FIGS. 8A and FIGS. 8B are drawings for explaining the shapes of the first, second, and third anode electrodes. FIGS. 9a to 9e are drawings for explaining the shapes of the transparent region and the non-transparent region. Figure 10 is an enlarged view of area B of Figure 2. Figure 11 is a cross-sectional view showing an example of IV-IV of Figure 10. Figure 12 is a cross-sectional view showing an example of VV of Figure 10. Figure 13 is a cross-sectional view showing an example of VI-VI of Figure 10. Specific details for implementing the invention

[0018] The advantages and features of this specification and the methods for achieving them will become clear by referring to the embodiments described below in detail together with the accompanying drawings. However, this specification is not limited to the embodiments disclosed below but may be implemented in various different forms; these embodiments are provided merely to ensure that the disclosure of this specification is complete and to fully inform those skilled in the art of the scope of the invention, and this specification is defined only by the scope of the claims.

[0019] Shapes, sizes, ratios, angles, numbers, etc. disclosed in the drawings for explaining embodiments of this specification are exemplary and are not limited to the depicted matters. Throughout the specification, the same reference numerals refer to the same components. Furthermore, in describing this specification, if it is determined that a detailed description of related prior art could unnecessarily obscure the essence of this specification, such detailed description is omitted. Where terms such as "includes," "has," or "is made up" are used in this specification, other parts may be added unless "only" is used. Where a component is expressed in the singular, it includes cases where it is included in the plural unless specifically stated otherwise.

[0020] In interpreting the components, they are interpreted to include a margin of error even in the absence of a separate explicit statement.

[0021] In the case of describing a positional relationship, for example, when the positional relationship between two parts is described using expressions such as 'on,' 'upper,' 'lower,' or 'next to,' one or more other parts may be located between the two parts unless 'immediately' or 'directly' is used.

[0022] In the case of an explanation of a temporal relationship, for example, when a temporal sequence is explained using 'after', 'following', 'next', 'before', etc., it may include cases where the sequence is not continuous unless 'immediately' or 'directly' is used.

[0023] The terms first, second, etc. are used to describe various components, but these components are not limited by these terms. These terms are used merely to distinguish one component from another. Accordingly, the first component mentioned below may be the second component within the technical scope of the present invention.

[0024] The term “at least one” should be understood to include all combinations that can be presented from one or more related items. For example, the meaning of “at least one of the first item, the second item, and the third item” may mean not only the first item, the second item, or the third item individually, but also all combinations of items that can be presented from two or more of the first item, the second item, and the third item.

[0025] The features of each of the various embodiments of this specification may be combined or combined with one another, either partially or wholly, and may technically enable various interlocking and operation. Each embodiment may be implemented independently of one another or may be implemented together in an interlocking relationship.

[0026] Hereinafter, a preferred example of a transparent display device according to the present invention will be described in detail with reference to the attached drawings. In assigning reference numerals to the components of each drawing, the same components may have the same reference numeral as much as possible, even if they are shown in different drawings. Furthermore, in describing the present invention, if it is determined that a detailed description of related known components or functions may obscure the essence of the present invention, such detailed description may be omitted.

[0027] Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the attached drawings.

[0028] FIG. 1 is a perspective view showing a display device according to one embodiment of the present invention.

[0029] In the following, the X-axis represents a direction parallel to the gate line, the Y-axis represents a direction parallel to the data line, and the Z-axis represents the height direction of the transparent display device (100).

[0030] Although the transparent display device (100) according to one embodiment of the present invention has been described primarily as being implemented as an organic light-emitting display, it may also be implemented as a liquid crystal display, a plasma display panel (PDP), a quantum dot light-emitting display (QLED), or an electrophoretic display.

[0031] Referring to FIG. 1, a transparent display device (100) according to one embodiment of the present invention includes a transparent display panel (110), a source drive integrated circuit (hereinafter referred to as "IC") (210), a flexible film (220), a circuit board (230), and a timing control unit (240).

[0032] A transparent display panel (110) includes a first substrate (111) and a second substrate (112) facing each other. The second substrate (112) may be an encapsulation substrate. The first substrate (111) may be a plastic film, a glass substrate, or a silicon wafer substrate formed using a semiconductor process. The second substrate (112) may be a plastic film, a glass substrate, or an encapsulation film. These first substrate (111) and second substrate (112) may be made of a transparent material.

[0033] The gate driver supplies gate signals to the gate lines according to the gate control signal input from the timing control unit (240). The gate driver may be formed in a non-display area outside one or both sides of the display area of ​​the transparent display panel (110) using a GIP (gate driver in panel) method. Alternatively, the gate driver may be manufactured as a driving chip, mounted on a flexible film, and attached to a non-display area outside one or both sides of the display area of ​​the transparent display panel (110) using a TAB (tape automated bonding) method.

[0034] The source drive IC (210) receives digital video data and a source control signal from the timing control unit (240). The source drive IC (210) converts the digital video data into analog data voltages according to the source control signal and supplies them to the data lines. When the source drive IC (210) is manufactured as a driving chip, it can be mounted on a flexible film (220) using a COF (chip on film) or COP (chip on panel) method.

[0035] Pads such as power pads and data pads may be formed in the non-display area of ​​the transparent display panel (110). Wiring connecting the pads to the source drive IC (210) and wiring connecting the pads to the wiring of the circuit board (230) may be formed in the flexible film (220). The flexible film (220) is attached to the pads using an anisotropic conducting film, thereby allowing the pads and the wiring of the flexible film (220) to be connected.

[0036] FIG. 2 is a plan view schematically showing a transparent display panel, FIG. 3 is an enlarged view of area A of FIG. 2, FIG. 4a is a plan view showing an anode electrode, a first interlayer insulating film, a second interlayer insulating film, and a bank, FIG. 4b is a plan view showing a color filter layer. FIG. 5 is a cross-sectional view showing an example of II of FIG. 3, FIG. 6 is a cross-sectional view showing an example of II-II of FIG. 4a and FIG. 4b, and FIG. 7 is a cross-sectional view showing an example of III-III of FIG. 4a and FIG. 4b. FIG. 8a and FIG. 8b are drawings for explaining the shapes of the first, second, and third anode electrodes, and FIG. 9a to 9e are drawings for explaining the shapes of the transparent region and the non-transparent region.

[0037] The first substrate (111) can be divided into a display area (DA) where pixels (P) are formed to display an image and a non-display area (NDA) where an image is not displayed.

[0038] The display area (DA) includes a transparent area (TA) and a non-transparent area (NTA) as illustrated in FIG. 3. The transparent area (TA) is an area that transmits most of the light incident from the outside, and the non-transparent area (NTA) is an area that does not transmit most of the light incident from the outside. For example, the transparent area (TA) may be an area with a light transmittance greater than α%, e.g. 90%, and the non-transparent area (NTA) may be an area with a light transmittance less than β%, e.g. 50%. In this case, α is a value greater than β. The transparent display panel (110) can see objects or backgrounds located on the back of the transparent display panel (110) due to the transparent areas (TA).

[0039] The non-transparent region (NTA) may be equipped with pixel power lines (VDDL), common power lines (VSSL), reference lines, data lines, gate lines (GL), and pixels (P).

[0040] The gate lines (GL) can be extended in a first direction (X-axis direction) and can intersect with pixel power lines (VDDL), common power lines (VSSL), and data lines in the display area (DA).

[0041] Pixel power lines (VDDL), common power lines (VSSL), reference lines, and data lines may be extended in a second direction (Y-axis direction) in the display area (DA). In this case, the pixel power lines (VDDL) and the common power lines (VSSL) may be arranged alternately within the display area (DA). Additionally, a transparent area (TA) may be arranged between the pixel power lines (VDDL) and the common power lines (VSSL).

[0042] Pixels (P) emit a predetermined amount of light to display an image. The light-emitting region (EA) may correspond to the region in which the pixel (P) emits light.

[0043] Each of the pixels (P) may include a first subpixel (P1), a second subpixel (P2), and a third subpixel (P3). The first subpixel (P1) may be configured to include a first light-emitting region (EA1) that emits green light, the second subpixel (P2) may be configured to include a second light-emitting region (EA2) that emits red light, and the third subpixel (P3) may be configured to include a third light-emitting region (EA3) that emits blue light, but is not necessarily limited thereto. Each of the pixels (P) may further be configured to include a subpixel that emits white (W) light. The arrangement order of each subpixel (P1, P2, P3) may be varied.

[0044] For convenience of explanation, the first subpixel (P1) is described as a green subpixel emitting green light, the second subpixel (P2) is described as a red subpixel emitting red light, and the third subpixel (P3) is described as a blue subpixel emitting blue light.

[0045] Each of the first subpixel (P1) and the third subpixel (P3) can be positioned to overlap with either the first intersection area (IA1) where the common power line (VSSL) and the gate line (GL) intersect, or the second intersection area (IA2) where the pixel power line (VDDL) and the gate line (GL) intersect.

[0046] For example, the first subpixel (P1) may be positioned to overlap with the first intersection area (IA1) where the common power line (VSSL) and the gate line (GL) intersect, as shown in FIG. 3. The second subpixel (P2) may be positioned to overlap with the second intersection area (IA2) where the pixel power line (VDDL) and the gate line (GL) intersect, but is not necessarily limited thereto. The first subpixel (P1) may be positioned to overlap with the second intersection area (IA2), and the second subpixel (P2) may be positioned to overlap with the first intersection area (IA1). Additionally, the first subpixel (P1) and the second subpixel (P2) may be positioned alternately along the common power line (VSSL) or alternately along the pixel power line (VDDL).

[0047] The second subpixel (P2) may be positioned between the first intersection area (IA1) and the second intersection area (IA2). For example, the second subpixel (P2) may be positioned between the first subpixel (P1) and the third subpixel (P3). In this case, the second subpixel (P2) may overlap with the gate line (GL).

[0048] Each of the first subpixel (P1), the second subpixel (P2), and the third subpixel (P3) may be equipped with a circuit element including a capacitor, a thin-film transistor, etc., and a light-emitting element as shown in FIG. 5. The thin-film transistor may include a switching transistor, a sensing transistor, and a driving transistor (T).

[0049] The switching transistor is switched according to the gate signal supplied to the gate line (GL) and serves to supply the data voltage supplied from the data line to the driving transistor (T).

[0050] The sensing transistor plays the role of sensing the threshold voltage deviation of the driving transistor (T) that causes image degradation.

[0051] The driving transistor (T) is switched according to the data voltage supplied from the switching thin-film transistor and generates a data current from the power supplied from the pixel power line (VDDL) and supplies it to the anode electrode (120) of the pixel.

[0052] The driving transistor (T) includes an active layer (ACT), a gate electrode (GE), a source electrode (SE), and a drain electrode (DE).

[0053] Specifically, an active layer (ACT) may be provided on the first substrate (111). The active layer (ACT) may be formed of a silicon-based semiconductor material or an oxide-based semiconductor material. A buffer film (not shown) may be provided between the active layer (ACT) and the first substrate (111).

[0054] A gate insulating film (GI) may be provided on the active layer (ACT). The gate insulating film (GI) may be formed from an inorganic film, for example, a silicon oxide film (SiOx), a silicon nitride film (SiNx), or a combination thereof.

[0055] A gate electrode (GE) may be provided on the gate insulating film (GI). The gate electrode (GE) may be formed as a single layer or a multilayer made of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof.

[0056] A first interlayer insulating film (ILD1) and a second interlayer insulating film (ILD2) may be provided on the gate electrode (GE). The first interlayer insulating film (ILD1) and the second interlayer insulating film (ILD2) may be formed of an inorganic film, for example, a silicon oxide film (SiOx), a silicon nitride film (SiNx), or a multilayer film thereof.

[0057] In one embodiment of the present invention, a transparent display panel (110) may have insulating films, particularly inorganic films, provided between a first substrate (110) and an anode electrode (120), provided only in a non-transparent region (NTA) and not in a transparent region (TA).

[0058] Specifically, the insulating films provided between the first substrate (110) and the anode electrode (120) may include a gate insulating film (GI), a first interlayer insulating film (ILD1), and a second interlayer insulating film (ILD2).

[0059] Each of the gate insulating film (GI), the first interlayer insulating film (ILD1), and the second interlayer insulating film (ILD2) may be made of an inorganic film such as a silicon oxide film (SiOx) having a refractive index of 1.4 to 1.5 or a silicon nitride film (SiNx) having a refractive index of 1.8 to 1.9. If a high-refractive index film such as a silicon nitride film (SiNx) is formed in the transmission region (TA), light loss may occur as light incident from the outside is reflected from the high-refractive index film. Consequently, the transmittance of the transparent display panel (110) may be reduced in the transmission region (TA).

[0060] A transparent display panel (110) according to one embodiment of the present invention can remove high-refractive index films in a transmission area (TA) to improve transmittance in a transmission area (TA).

[0061] At least one of the gate insulating film (GI), the first interlayer insulating film (ILD1), and the second interlayer insulating film (ILD2) may be formed of silicon nitride (SiNx). For example, the gate insulating film (GI) may be formed of silicon oxide (SiOx), and the first interlayer insulating film (ILD1) and the second interlayer insulating film (ILD2) may be formed of silicon nitride (SiNx). In this case, the first interlayer insulating film (ILD1) and the second interlayer insulating film (ILD2) may be provided only in the non-transparent region (NTA) and not in the transparent region (TA).

[0062] As another example, the gate insulating film (GI), the first interlayer insulating film (ILD1), and the second interlayer insulating film (ILD2) may all be formed of silicon nitride (SiNx). In this case, the gate insulating film (GI), the first interlayer insulating film (ILD1), and the second interlayer insulating film (ILD2) may be provided only in the non-transparent region (NTA) and not in the transparent region (TA).

[0063] As another example, only the second interlayer insulating film (ILD2) may be formed of silicon nitride (SiNx). In this case, the second interlayer insulating film (ILD2) may be provided only in the non-transparent region (NTA) and not in the transparent region (TA).

[0064] A transparent display panel (110) according to one embodiment of the present invention can prevent external light from being lost in a transmission area (TA), and accordingly, can improve the transmittance in the transmission area (TA).

[0065] A source electrode (SE) and a drain electrode (DE) may be provided on the second interlayer insulating film (ILD2). One of the source electrode (SE) and the drain electrode (DE) may be connected to the active layer (ACT) through a second contact hole (CH2) that penetrates the gate insulating film (GI) and the first and second interlayer insulating films (ILD1, ILD2). For example, the drain electrode (DE) may be connected to the active layer (ACT) through a second contact hole (CH2) that penetrates the gate insulating film (GI) and the first and second interlayer insulating films (ILD1, ILD2).

[0066] The source electrode (SE) and drain electrode (DE) may be formed as a single layer or multiple layers made of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof.

[0067] A first flattening film (PLN1) may be provided on the source electrode (SE) and drain electrode (DE) to flatten the step caused by the driving transistor (T). The first flattening film (PLN1) may be formed from an organic film such as an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, or a polyimide resin.

[0068] An anode auxiliary electrode (115) may be provided on the first planarization film (PLN1). The anode auxiliary electrode (115) may be connected to one of the source electrode (SE) and the drain electrode (DE) through a third contact hole (CH3) penetrating the first planarization film (PLN1). For example, the anode auxiliary electrode (115) may be connected to the drain electrode (DE) through the third contact hole (CH3) penetrating the first planarization film (PLN1).

[0069] The anode auxiliary electrode (115) can be formed as a single layer or multiple layers made of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd) and copper (Cu) or an alloy thereof.

[0070] A second planarization film (PLN2) may be formed on the anode auxiliary electrode (115). The second planarization film (PLN2) may be formed from an organic film such as an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, or a polyimide resin.

[0071] On the second planarization film (PLN2), a bank (125) and light-emitting elements consisting of an anode electrode (120), a light-emitting layer (130), and a cathode electrode (140) are provided.

[0072] The anode electrode (120) can be provided on the second planarization film (PLN2) and connected to the driving transistor (T). Specifically, the anode electrode (120) can be connected to the anode auxiliary electrode (115) through a first contact hole (CH1) penetrating the second planarization film (PLN2). Since the anode auxiliary electrode (115) is connected to the source electrode (SE) or drain electrode (DE) of the driving transistor (T) through a third contact hole (CH3), the anode electrode (120) can be electrically connected to the driving transistor (T).

[0073] These anode electrodes (120) may be provided for each subpixel (P1, P2, P3). Specifically, one anode electrode (120) may be formed in the first subpixel (P1), another anode electrode (120) may be formed in the second subpixel (P2), and yet another anode electrode (120) may be formed in the third subpixel (P3). Additionally, the anode electrodes (120) are not provided in the transmission area (TA).

[0074] An anode electrode (120) according to one embodiment of the present invention may include a first anode electrode (121), a second anode electrode (122), and a third anode electrode (123).

[0075] The first anode electrode (121) may be placed on the common power line (VSSL). Specifically, the first anode electrode (121) may be placed to overlap with the first intersection area (IA1) where the common power line (VSSL) and the gate line (GL) intersect.

[0076] A plurality of first anode electrodes (121) may be provided along the common power line (VSSL). A subpixel equipped with a plurality of first anode electrodes (121) may be at least one of a first subpixel (P1) and a third subpixel (P3). For example, a subpixel equipped with a plurality of first anode electrodes (121) may be a first subpixel (P1). For another example, a subpixel equipped with a plurality of first anode electrodes (121) may be a third subpixel (P3). For yet another example, a subpixel equipped with a plurality of first anode electrodes (121) may be a first subpixel (P1) and a third subpixel (P3). At this time, the first subpixels (P1) and the third subpixels (P3) may be arranged alternately on the common power line (VSSL).

[0077] The third anode electrode (123) may be placed on the pixel power line (VDDL). Specifically, the third anode electrode (123) may be placed to overlap with the second intersection area (IA2) where the pixel power line (VDDL) and the gate line (GL) intersect.

[0078] A plurality of third anode electrodes (123) may be provided along the pixel power line (VDDL). A subpixel equipped with a plurality of third anode electrodes (123) may be at least one of a first subpixel (P1) and a third subpixel (P3). For example, a subpixel equipped with a plurality of third anode electrodes (123) may be a first subpixel (P1). For another example, a subpixel equipped with a plurality of third anode electrodes (123) may be a third subpixel (P3). For yet another example, a subpixel equipped with a plurality of third anode electrodes (123) may be a first subpixel (P1) and a third subpixel (P3). At this time, the first subpixels (P1) and the third subpixels (P3) may be arranged alternately on a common power line (VSSL).

[0079] The second anode electrode (122) may be positioned between the first anode electrode (121) and the third anode electrode (123). Specifically, the second anode electrode (122) may be positioned on a gate line (GL) provided between the first intersection region (IA1) and the second intersection region (IA2).

[0080] These first anode electrode (121) and third anode electrode (123) may have a different shape from the second anode electrode (122).

[0081] Specifically, the first anode electrode (121) may include a first portion (121a) and a second portion (121b) as shown in FIG. 8a. In one embodiment, the first anode electrode (121) may further include a third portion (121c).

[0082] The first portion (121a) of the first anode electrode (121) may be positioned to overlap with the first intersection area (IA1) where the common power line (VSSL) and the gate line (GL) intersect. For example, the first portion (121a) of the first anode electrode (121) may have a square shape as shown in FIG. 8a, but is not necessarily limited thereto. The first portion (121a) of the first anode electrode (121) may be formed in various shapes such as a circle, a semicircle, or a polygon.

[0083] The first portion (121a) of the first anode electrode (121) may be provided with thin-film transistors, such as a switching transistor, a sensing transistor, and a driving transistor (T), and a capacitor below it. The first portion (121a) of the first anode electrode (121) may have a width (WA1) that can cover the thin-film transistor and capacitor provided below it.

[0084] The second portion (121b) of the first anode electrode (121) may protrude from one side (S1-1) of the first portion (121a). At this time, the second portion (121b) of the first anode electrode (121) may be positioned on the common power line (VSSL). That is, one side (S1-1) of the first portion (121a) may correspond to the side intersecting the common power line (VSSL). Furthermore, the second portion (121b) of the first anode electrode (121) may protrude in the direction in which the common power line (VSSL) extends, i.e., in the second direction (Y-axis direction).

[0085] The second part (121b) of the first anode electrode (121) may include a first side (S2-1) facing the first part (121a), a second side (S2-2) connecting the first side (S2-1) and the first part (121a), and a third side (S2-3).

[0086] The second part (121b) of the first anode electrode (121) may have a width (WA2) at the first side (S2-1) that is smaller than the width (WA1) of the first part (121a) of the first anode electrode (121). As shown in FIG. 7, the second part (121b) of the first anode electrode (121) may be provided with a plurality of metal lines below, such as a common power line (VSSL), data lines (DL1, DL2), and reference lines (REFL1, REFL2). At this time, the common power line (VSSL), data lines (DL1, DL2), and reference lines (REFL1, REFL2) may all be arranged in the same direction, that is, in the second direction (Y-axis direction), as shown in FIG. 3. Accordingly, the second portion (121b) of the first anode electrode (121) can cover a plurality of metal lines with a width (WA2) smaller than the width (WA1) of the first portion (121a) of the first anode electrode (121).

[0087] Meanwhile, the second part (121b) of the first anode electrode (121) may be provided with a first curved section (CV1) between the first side (S2-1) and the first part (121a), as shown in FIG. 8a. Specifically, the second part (121b) of the first anode electrode (121) may include a second side (S2-2) and a third side (S2-3) connecting the first side (S2-1) and the first part (121a). The second side (S2-2) of the second part (121b) of the first anode electrode (121) may include a first curved section (CV1) that is curved from one point to the first part (121a). Additionally, the third side (S2-3) of the second part (121b) of the first anode electrode (121) may include another first curved section (CV1) that is curved from one point to the first part (121a). In this case, the first curved section (CV1) may be concave inward.

[0088] The third portion (121c) of the first anode electrode (121) may protrude from the other side (S1-2) of the first portion (121a). At this time, the third portion (121c) of the first anode electrode (121) may be positioned on the common power line (VSSL). That is, the other side (S1-2) of the first portion (121a) may correspond to the side that intersects the common power line (VSSL) and faces the one side (S1-1). Furthermore, the third portion (121c) of the first anode electrode (121) may protrude in the direction in which the common power line (VSSL) extends, i.e., in the second direction (Y-axis direction).

[0089] The third part (121c) of the first anode electrode (121) may include a first side (S3-1) facing the first part (121a), a second side (S3-2) connecting the first side (S3-1) and the first part (121a), and a third side (S3-3).

[0090] The third part (121c) of the first anode electrode (121) may have a width (WA3) at the first side (S3-1) that is smaller than the width (WA1) of the first part (121a) of the first anode electrode (121). As shown in FIG. 7, the third part (121c) of the first anode electrode (121) may be provided with a plurality of metal lines below, such as a common power line (VSSL), data lines (DL1, DL2), and reference lines (REFL1, REFL2). At this time, the common power line (VSSL), data lines (DL1, DL2), and reference lines (REFL1, REFL2) may all be arranged in parallel in the same direction, that is, in the second direction (Y-axis direction). Accordingly, the third portion (121c) of the first anode electrode (121) can cover a plurality of metal lines with a width (WA2) smaller than the width (WA1) of the first portion (121a) of the first anode electrode (121).

[0091] The third part (121c) of the first anode electrode (121) may have a width (WA3) at the first side (S3-1) that is equal to the width (WA2) of the second part (121b) of the first anode electrode (121). The third part (121c) of the first anode electrode (121) and the second part (121b) of the first anode electrode (121) may have a shape that is symmetrical with respect to the first part (121a) of the first anode electrode (121).

[0092] Meanwhile, the third part (121c) of the first anode electrode (121) may be provided with a first curved section (CV1) between the first side (S3-1) and the first part (121a), as shown in FIG. 8a. Specifically, the third part (121c) of the first anode electrode (121) may include a second side (S3-2) and a third side (S3-3) connecting the first side (S3-1) and the first part (121a). The second side (S3-2) of the third part (121c) of the first anode electrode (121) may include a first curved section (CV1) that is curved from one point to the first part (121a). Additionally, the third side (S3-3) of the third part (121c) of the first anode electrode (121) may include another first curved section (CV1) that is curved from one point to the first part (121a). In this case, the curved section (CV) may be concave inward.

[0093] The third anode electrode (123) may include a first part (123a) and a second part (123b) as shown in FIG. 8a. In one embodiment, the third anode electrode (123) may further include a third part (123c).

[0094] The first portion (123a) of the third anode electrode (123) may be positioned to overlap with the second intersection area (IA2) where the pixel power line (VDDL) and the gate line (GL) intersect. For example, the first portion (123a) of the third anode electrode (123) may have a square shape as shown in FIG. 8a, but is not necessarily limited thereto. The first portion (123a) of the third anode electrode (123) may be formed in various shapes such as a circle, a semicircle, or a polygon.

[0095] The first portion (123a) of the third anode electrode (123) may be provided with thin-film transistors, such as a switching transistor, a sensing transistor, and a driving transistor (T), and a capacitor below it. The first portion (123a) of the third anode electrode (123) may have a width (WA1) that can cover the thin-film transistor and capacitor provided below it.

[0096] The second portion (123b) of the third anode electrode (123) may protrude from one side (S1-1) of the first portion (123a). At this time, the second portion (123b) of the third anode electrode (123) may be positioned on the pixel power line (VDDL). That is, one side (S1-1) of the first portion (123a) may correspond to the side intersecting the pixel power line (VDDL). Furthermore, the second portion (123b) of the third anode electrode (123) may protrude in the direction in which the pixel power line (VDDL) extends, i.e., in the second direction (Y-axis direction).

[0097] The second part (123b) of the third anode electrode (123) may include a first side (S2-1) facing the first part (123a), a second side (S2-2) connecting the first side (S2-1) and the first part (123a), and a third side (S2-3).

[0098] The second part (123b) of the third anode electrode (123) may have a width (WA2) at the first side (S2-1) that is smaller than the width (WA1) of the first part (123a) of the third anode electrode (123). The second part (123b) of the third anode electrode (123) may be provided with a plurality of metal lines below it, such as a pixel power line (VDDL), data lines (DL1, DL2), and reference lines (REFL1, REFL2). At this time, the pixel power line (VDDL), data lines (DL1, DL2), and reference lines (REFL1, REFL2) may all be arranged in the same direction, that is, in the second direction (Y-axis direction), as shown in FIG. 3. Accordingly, the second portion (123b) of the third anode electrode (123) can cover a plurality of metal lines with a width (WA2) smaller than the width (WA1) of the first portion (123a) of the third anode electrode (123).

[0099] Meanwhile, the second part (123b) of the third anode electrode (123) may be provided with a first curved section (CV1) between the first side (S2-1) and the first part (123a), as shown in FIG. 8a. Specifically, the second part (123b) of the third anode electrode (123) may include a second side (S2-2) and a third side (S2-3) connecting the first side (S2-1) and the first part (123a). The second side (S2-2) of the second part (123b) of the third anode electrode (123) may include a first curved section (CV1) that is curved from one point to the first part (123a). Additionally, the third side (S2-3) of the second part (123b) of the third anode electrode (123) may include another first curved section (CV1) that is curved from one point to the first part (123a). In this case, the curved section (CV) may be concave inward.

[0100] The third portion (123c) of the third anode electrode (123) may protrude from the other side (S1-2) of the first portion (123a). At this time, the third portion (123c) of the third anode electrode (123) may be positioned on the pixel power line (VDDL). That is, the other side (S1-2) of the first portion (123a) may correspond to the side that intersects the pixel power line (VDDL) and faces one side (S1-1). Furthermore, the third portion (123c) of the third anode electrode (123) may protrude in the direction in which the pixel power line (VDDL) extends, i.e., in the second direction (Y-axis direction).

[0101] The third part (123c) of the third anode electrode (123) may include a first side (S3-1) facing the first part (123a), a second side (S3-2) connecting the first side (S3-1) and the first part (123a), and a third side (S3-3).

[0102] The third part (123c) of the third anode electrode (123) may have a width (WA3) at the first side (S3-1) that is smaller than the width (WA1) of the first part (123a) of the third anode electrode (123). The third part (123c) of the third anode electrode (123) may be provided with a plurality of metal lines below it, such as a pixel power line (VDDL), data lines (DL1, DL2), and reference lines (REFL1, REFL2). At this time, the pixel power line (VDDL), data lines (DL1, DL2), and reference lines (REFL1, REFL2) may all be arranged in parallel in the same direction, that is, in the second direction (Y-axis direction). Accordingly, the third portion (123c) of the third anode electrode (123) can cover a plurality of metal lines with a width (WA2) smaller than the width (WA1) of the first portion (123a) of the third anode electrode (123).

[0103] The third part (123c) of the third anode electrode (123) may have a width (WA3) at the first side (S3-1) that is equal to the width (WA2) of the second part (123b) of the third anode electrode (123). The third part (123c) of the third anode electrode (123) and the second part (123b) of the third anode electrode (123) may have a symmetrical shape with the first part (123a) of the third anode electrode (123) in between.

[0104] Meanwhile, the third part (123c) of the third anode electrode (123) may be provided with a first curved section (CV1) between the first side (S3-1) and the first part (123a), as shown in FIG. 8a. Specifically, the third part (123c) of the third anode electrode (123) may include a second side (S3-2) and a third side (S3-3) connecting the first side (S3-1) and the first part (123a). The second side (S3-2) of the third part (123c) of the third anode electrode (123) may include a first curved section (CV1) that is curved from one point to the first part (123a). Additionally, the third side (S3-3) of the third part (123c) of the third anode electrode (123) may include another first curved section (CV1) that is curved from one point to the first part (123a). In this case, the first curved section (CV1) may be concave inward.

[0105] Meanwhile, the second anode electrode (122) may consist only of the first part (122a) as shown in FIG. 8b. The first part (122a) of the second anode electrode (122) may have a square shape as shown in FIG. 8b, but is not necessarily limited thereto. The first part (122a) of the second anode electrode (122) may be formed in various shapes such as a circle, a semicircle, or a polygon.

[0106] The first portion (122a) of the second anode electrode (122) may be provided with thin-film transistors, such as a switching transistor, a sensing transistor, and a driving transistor (T), and a capacitor underneath. The first portion (122a) of the second anode electrode (122) may have a width (WA4) that can cover the thin-film transistor and capacitor provided underneath. The width (WA4) of the first portion (122a) of the second anode electrode (122) may be smaller than the width (WA1) of the first portions (121a, 123a) of the first and third anode electrodes (121, 123), but is not necessarily limited thereto. The width (WA4) of the first portion (122a) of the second anode electrode (122) may be the same as the width (WA1) of the first portion (121a, 123a) of the first and third anode electrodes (121, 123).

[0107] Meanwhile, unlike the first anode electrode (121) and the third anode electrode (123), the second anode electrode (122) does not have a portion protruding from the first portion (122a). The second anode electrode (122) overlaps with the gate line (GL) extended in the first direction (X-axis direction) and does not overlap with the common power line (VSSL) or pixel power line (VDDL) extended in the second direction (Y-axis direction). Accordingly, if the second anode electrode (122) forms a portion protruding from the first portion (122a) in the second direction (Y-axis direction), the non-transparent area (NTA) may be unnecessarily increased and the area of ​​the transparent area (TA) may be reduced. Therefore, it may be preferable for the second anode electrode (122) to consist only of the first portion (122a).

[0108] Consequently, the second anode electrode (122) may have a smaller area than the first anode electrode (121) and the third anode electrode (123). Accordingly, the second subpixel (P2) equipped with the second anode electrode (122) may have a smaller light-emitting area than the first subpixel (P1) and the third subpixel (P3) equipped with the first anode electrode (121) or the third anode electrode (123). The second subpixel (P2) may be a red subpixel that emits red light. Generally, since the red subpixel has a superior lifespan compared to the green subpixel and the blue subpixel, the lifespan of the transparent display panel (110) may not be reduced even if the area of ​​the red subpixel is formed to be small.

[0109] A transparent display panel (110) according to one embodiment of the present invention may include a first anode electrode (121) and a third anode electrode (123), a first part (121a, 123a), a second part (121b, 123b) protruding in a second direction (Y-axis direction) from the first part (121a, 123a), and a third part (121c, 123c).

[0110] At this time, the second part (121b, 123b) and the third part (121c, 123c) are provided below and can cover a plurality of metal lines extended in the second direction (Y-axis direction). At this time, the plurality of metal lines may include power lines (PL), such as a common power line (VSSL) or a pixel power line (VDDL), data lines (DL1, DL2), and reference lines (REFL1, REFL2). The data lines (DL1, DL2) and reference lines (REFL1, REFL2) may be spaced apart from each other on the same layer as shown in FIG. 7. For example, the data lines (DL1, DL2) and reference lines (REFL1, REFL2) may be spaced apart from the source electrode (SE) and drain electrode (DE) of the driving transistor (T) on the same layer. The common power line (VSSL) or pixel power line (VDDL) can be placed on the same layer as the anode auxiliary electrode (115).

[0111] When multiple such metal lines are spaced apart in parallel, slits, specifically long linear or rectangular ones, can be formed between the multiple metal lines. When external light passes through the slits, diffraction may occur.

[0112] The diffraction phenomenon is that as light, which is a plane wave, passes through the slit, it changes into spherical waves, and interference may occur in the spherical waves. Therefore, as constructive and destructive interference occur in the spherical waves, the external light passing through the slit may have irregular light intensity. Accordingly, the clarity of an object or image located on the opposite side of the transparent display panel (110) may be reduced.

[0113] A transparent display panel (110) according to one embodiment of the present invention can cover a plurality of metal lines provided below the first anode electrode (121) and the third anode electrode (123) as much as possible by forming a second part (121b, 123b) and a third part (121c, 123c) protruding from a first part (121a, 123a) in a second direction (Y-axis direction) on the first anode electrode (121) and the third anode electrode (123). Accordingly, the transparent display panel (110) according to one embodiment of the present invention can prevent diffraction phenomena caused by the plurality of metal lines.

[0114] Furthermore, a transparent display panel (110) according to one embodiment of the present invention can increase the area of ​​the light-emitting region (EA) by forming a second portion (121b, 123b) and a third portion (121c, 123c) on the first anode electrode (121) and the third anode electrode (123).

[0115] In addition, a transparent display panel (110) according to one embodiment of the present invention may have a minimum width (WA2, WA3) such that the second portion (121b, 123b) and the third portion (121c, 123c) of each of the first anode electrode (121) and the third anode electrode (123) can cover a plurality of metal lines.

[0116] In one embodiment, the second portion (121b, 123b) and the third portion (121c, 123c) of each of the first anode electrode (121) and the third anode electrode (123) may have the same position in plane as the end of the outermost line among the plurality of signal lines with ends provided below, as shown in FIG. 7. At this time, the plurality of signal lines may include power lines (PL), such as a common power line (VSSL) and a pixel power line (VDDL), data lines (DL1, DL2), and reference lines (REFL1, REFL2).

[0117] For example, the second portions (121b, 123b) and third portions (121c, 123c) of the first anode electrode (121) and the third anode electrode (123), respectively, may have the same position in plane as the end of the first data line (D1) which is positioned at the outermost edge, as shown in FIG. 7. Also, the second portions (121b, 123b) and third portions (121c, 123c) of the first anode electrode (121) and the third anode electrode (123), respectively, may have the same position in plane as the end of the second data line (D2) which is positioned at the outermost edge, as shown in FIG. 7.

[0118] Additionally, the first portions (121a, 122a, 123a) of each of the first anode electrode (121), the second anode electrode (122), and the third anode electrode (123) may have a minimum size such that the width between the transmission regions (TA) can cover a plurality of metal lines.

[0119] Specifically, the first portions (121a, 122a, 123a) of each of the first anode electrode (121), the second anode electrode (122), and the third anode electrode (123) may be provided with a plurality of circuit elements below. Each of the plurality of circuit elements may include a plurality of signal lines (SL) extended in the same layer as any one of the gate electrode (GE), source electrode (SE), drain electrode (DE), and anode auxiliary electrode (115) of the driving transistor (T). The first portions (121a, 122a, 123a) of each of the first anode electrode (121), the second anode electrode (122), and the third anode electrode (123) may have the same position in plane as the end of the outermost line among the plurality of signal lines (SL) with ends provided below as shown in FIG. 6. Accordingly, the transparent display panel (110) according to one embodiment of the present invention can maximize the area of ​​the transmission region (TA) and improve the transmittance.

[0121] Each of these first anode electrode (121), second anode electrode (122), and third anode electrode (123) can be formed from a highly reflective metallic material such as a stacked structure of aluminum and titanium (Ti / Al / Ti), a stacked structure of aluminum and ITO (ITO / Al / ITO), an Ag alloy, and a stacked structure of Ag alloy and ITO (ITO / Ag alloy / ITO). The Ag alloy may be an alloy of silver (Ag), palladium (Pd), and copper (Cu).

[0122] A bank (125) may be provided on a second planarization film (PLN2). Additionally, a bank (125) may be provided between anode electrodes (120). Specifically, a bank (125) may be provided between a first anode electrode (121), a second anode electrode (122), and a third anode electrode (123) that are arranged adjacently in a first direction (X-axis direction). Additionally, a bank (125) may be provided between a plurality of first anode electrodes (121) arranged along a second direction (Y-axis direction) on a common power line (VSSL). Additionally, a bank (125) may be provided between a plurality of third anode electrodes (123) arranged along a second direction (Y-axis direction) on a pixel power line (VDDL).

[0123] And the bank (125) can be formed to cover the edges of each of the first anode electrode (121), the second anode electrode (122), and the third anode electrode (123), and to expose a portion of each of the first anode electrode (121), the second anode electrode (122), and the third anode electrode (123). Accordingly, the bank (125) can prevent the problem of reduced luminous efficiency caused by current concentration at each end of the first anode electrode (121), the second anode electrode (122), and the third anode electrode (123). The bank (125) may be provided only in the non-transparent region (NTA) and not in the transparent region (TA).

[0124] Bank (125) can define light-emitting regions (EA1, EA2, EA3) for each of the subpixels (P1, P2, P3). Each light-emitting region (EA1, EA2, EA3) of the subpixels (P1, P2, P3) represents a region in which an anode electrode (120), a light-emitting layer (130), and a cathode electrode (140) are sequentially stacked, and holes from the anode electrode (120) and electrons from the cathode electrode (140) combine with each other in the light-emitting layer (130) to emit light. In this case, the region where the anode electrode (120) is exposed and the bank (125) is not formed becomes the light-emitting region (EA), and the remaining region becomes the non-light-emitting region (NEA).

[0125] The bank (125) may be provided only in the non-transparent area (NTA) and may not be provided in the transparent area (TA). The bank (125) may have a yellowish color due to the properties of the material. A transparent display panel (110) according to one embodiment of the present invention can prevent the occurrence of a yellowish phenomenon in the transparent area (TA) by not forming the bank (125) in the transparent area (TA).

[0126] Meanwhile, the bank (125) may have a different end from at least one insulating film provided between the anode electrode (120) and the first substrate (111). Specifically, a transparent display panel (125) according to one embodiment of the present invention may form the bank (125) only in the non-transparent region (NTA) and not in the transparent region (TA). In addition, a transparent display panel (125) according to one embodiment of the present invention may form at least one insulating film among the insulating films provided between the anode electrode (120) and the first substrate (111) only in the non-transparent region (NTA) and not in the transparent region (TA). The at least one insulating film may include at least one of a gate insulating film (GI), a first interlayer insulating film (ILD1), and a second interlayer insulating film (ILD2).

[0127] The distance (d2) between the end of the bank (125) and the transmission area (TA) may be greater than the distance (d1) between the end of the transmission area (TA) and at least one insulating film, such as the first interlayer insulating film (ILD1) and the second interlayer insulating film (ILD2). That is, the end of at least one insulating film may be formed closer to the transmission area (TA) than the end of the bank (125).

[0128] Bank (125) may partially overlap with the transmission area (TA) due to process error. Since Bank (125) has a yellowish color, the transparent display panel (110) may show a yellowish color in the transmission area (TA) equipped with Bank (125), and the user may perceive this.

[0129] A transparent display panel (110) according to one embodiment of the present invention can sufficiently form a distance (d2) between the transparent area (TA) and the end of the bank (125) so that the bank (125) does not overlap with the transparent area (TA) even if a process error occurs.

[0130] Meanwhile, at least one insulating film provided between the anode electrode (120) and the first substrate (111) may have a sufficient area to protect circuit elements, such as a driving transistor (T), provided in a non-transmitting region (NTA). The at least one insulating film may be formed to cover the region where the circuit elements are formed. Furthermore, to improve the reliability of the circuit elements, the end of the at least one insulating film may be formed at a location spaced sufficiently far from the region where the driving transistor (T) is formed. Accordingly, the distance (d1) between the transmission region (TA) and the end of the at least one insulating film may be smaller than the distance (d2) between the transmission region (TA) and the end of the bank (125).

[0131] Meanwhile, in FIG. 7, the distance (d1) between the transmission region (TA) and the end of at least one insulating film is shown to be greater than 0, but it is not necessarily limited to this. The distance (d1) between the transmission region (TA) and the end of at least one insulating film may be 0.

[0132] Meanwhile, in the case where there are multiple insulating films provided between the anode electrode (120) and the first substrate (111), the ends of the multiple insulating films may all be the same as shown in FIG. 7, but are not necessarily limited thereto.

[0133] Multiple insulating films may all have different ends. For example, the first interlayer insulating film (ILD1) and the second interlayer insulating film (ILD2) may not be provided in the transmission region (TA). In this case, the distance between the transmission region (TA) and the end of the first interlayer insulating film (ILD1) may be smaller than the distance between the transmission region (TA) and the end of the second interlayer insulating film (ILD2). That is, the first interlayer insulating film (ILD1) and the second interlayer insulating film (ILD2) may have a stepped stacking structure. This stepped stacking structure can mitigate the step difference, and accordingly, prevent interfacial lifting from occurring in the first planarization film (PLN1) formed on top.

[0134] These banks (125) can be formed from organic films such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, and polyimide resin.

[0135] An organic light-emitting layer (130) may be provided on an anode electrode (120). The organic light-emitting layer (130) may include a hole transporting layer, a light-emitting layer, and an electron transporting layer. In this case, when a voltage is applied to the anode electrode (120) and the cathode electrode (140), holes and electrons move to the light-emitting layer through the hole transporting layer and the electron transporting layer, respectively, and combine with each other in the light-emitting layer to emit light.

[0136] The organic light-emitting layer (130) can be formed for each subpixel (P1, P2, P3) as shown in FIG. 5. For example, a green light-emitting layer (131) emitting green light may be formed in the first subpixel (P1), a red light-emitting layer (132) emitting red light may be formed in the second subpixel (P2), and a blue light-emitting layer (133) emitting blue light may be formed in the third subpixel (P3). In this case, the light-emitting layer of the organic light-emitting layer (130) is not formed in the transmission region (TA).

[0137] A cathode electrode (140) may be provided on an organic light-emitting layer (130) and a bank (125). The cathode electrode (140) may be provided in a non-transparent region (NTA) including a light-emitting region (EA) as well as in a transparent region (TA), but is not necessarily limited thereto. The cathode electrode (140) may be provided only in a non-transparent region (NTA) including a light-emitting region (EA) and may not be provided in a transparent region (TA) to improve transmittance.

[0138] These cathode electrodes (140) may be a common layer formed in common across subpixels (P1, P2, P3) to apply the same voltage. The cathode electrodes (140) may be formed from a transparent conductive material (TCO) such as ITO or IZO that can transmit light, or a semi-transmissive conductive material such as magnesium (Mg), silver (Ag), or an alloy of magnesium (Mg) and silver (Ag). When the cathode electrodes (140) are formed from a semi-transmissive conductive material, the light emission efficiency may be increased by microcavities.

[0139] A sealing film (150) may be provided on the light-emitting elements. The sealing film (150) may be formed to cover the cathode electrode (140). The sealing film (150) serves to prevent oxygen or moisture from penetrating into the organic light-emitting layer (130) and the cathode electrode (140). To this end, the sealing film (150) may include at least one inorganic film and at least one organic film.

[0140] Meanwhile, although not shown in FIG. 5, a capping layer may be additionally formed between the cathode electrode (140) and the sealing film (150).

[0141] A color filter layer (170) may be provided on the sealing film (150). The color filter layer (170) may be provided on one side of a second substrate (112) facing the first substrate (111). In this case, the first substrate (111) provided with the sealing film (150) and the second substrate (112) provided with the color filter layer (170) may be bonded together by a separate adhesive layer (160). At this time, the adhesive layer (160) may be an optically clear resin layer (OCR) or an optically clear adhesive film (OCA).

[0142] The color filter layer (170) can be patterned for each subpixel (P1, P2, P3). Specifically, the color filter layer (170) may include a first color filter (CF1), a second color filter (CF2), and a third color filter (CF3). The first color filter (CF1) may be positioned to correspond to the light-emitting region (EA1) of the first subpixel (P1) and may be a green color filter that transmits green light. The second color filter (CF2) may be positioned to correspond to the light-emitting region (EA2) of the second subpixel (P2) and may be a red color filter that transmits red light. The third color filter (CF3) may be positioned to correspond to the light-emitting region (EA3) of the third subpixel (P3) and may be a blue color filter that transmits blue light.

[0143] A transparent display panel (110) according to one embodiment of the present invention is characterized by forming a color filter layer (170) on a second substrate (112) without using a polarizing plate. If a polarizing plate is attached to the transparent display panel (110), the transmittance of the transparent display panel (110) is reduced by the polarizing plate. On the other hand, if a polarizing plate is not attached to the transparent display panel (110), a problem occurs in which light incident from the outside is reflected by the electrodes.

[0144] A transparent display panel (110) according to one embodiment of the present invention can prevent a decrease in transmittance by not attaching a polarizing plate. In addition, a transparent display panel (110) according to one embodiment of the present invention can prevent a portion of the light incident from the outside from being absorbed by the color filter layer (170) and reflected to the electrodes by forming a color filter layer (170) on a second substrate (112). That is, a transparent display panel (110) according to one embodiment of the present invention can reduce external light reflectance without reducing transmittance.

[0145] Meanwhile, a black matrix (BM) may be provided between the color filters (CF1, CF2, CF3). The black matrix (BM) is provided between the subpixels (P1, P2, P3) to prevent color mixing between adjacent subpixels (P1, P2, P3). Additionally, the black matrix (BM) can prevent light incident from the outside from being reflected by a plurality of wires provided between the subpixels (P1, P2, P3), such as gate lines, data lines, pixel power lines, common power lines, reference lines, etc.

[0146] This black matrix (BM) may include a light-absorbing material, for example, a black dye that absorbs all light in the visible light wavelength range.

[0147] The color filter layer (170) can define a non-transmitting area (NTA) within the display area (DA). Specifically, the area equipped with color filters (CF1, CF2, CF3) and a black matrix (BM) can be the non-transmitting area (NTA), and the remaining area can be the transmitting area (TA).

[0148] A transparent display panel (110) according to one embodiment of the present invention may have a transparent area (TA) with rounded corners, as shown in FIGS. 9a to 9e. Specifically, the transparent area (TA) may be provided with a plurality of second curved portions (CV2).

[0149] Each of the plurality of second curved sections (CV2) provided in the transmission region (TA) may have a shape corresponding to the plurality of first curved sections (CV1) provided in the first and third anode electrodes (121, 123), but is not necessarily limited thereto. Since the shape of the plurality of second curved sections (CV2) can be determined by the color filter layer (170), it is not necessarily the same as the plurality of first curved sections (CV1) provided in the first and third anode electrodes (121, 123). The plurality of second curved sections (CV2) provided in the transmission region (TA) and the plurality of first curved sections (CV1) provided in the first and third anode electrodes (121, 123) may have the same curvature or different curvatures.

[0150] Meanwhile, the non-transparent region (NTA) may have a linear or rectangular shape extended in a first direction (X-axis direction), or a linear or rectangular shape extended in a second direction (Y-axis direction). Additionally, a plurality of non-transparent regions (NTAs) having a linear (or rectangular) shape may be arranged in parallel with a predetermined spacing.

[0151] A transmission region (TA) can be positioned between multiple non-transmission regions (NTA) spaced at regular intervals. In this case, the transmission region (TA) can be a periodic slit between linear (or rectangular) non-transmission regions (NTA). When light incident from the outside passes through the periodic slits, it can cause periodic diffraction.

[0152] Specifically, the transparent region (TA) may be provided between linear (or rectangular) non-transparent regions (NTA) that are extended in a first direction (X-axis direction) and between linear (or rectangular) non-transparent regions (NTA) that are extended in a second direction (Y-axis direction). That is, the transparent region (TA) may have a rectangular shape.

[0153] In this case, light incident from the outside can cause periodic diffraction in the first direction (X-axis direction) and the second direction (Y-axis direction), respectively. Accordingly, diffraction patterns orthogonal to the first direction (X-axis direction) and the second direction (Y-axis direction) can be formed. These diffraction patterns may have irregular light intensity and light concentrated only in the first direction (X-axis direction) and the second direction (Y-axis direction). As a result, the clarity of objects or images located on the opposite side of the transparent display panel (110) may be reduced.

[0154] A transparent display panel (110) according to one embodiment of the present invention can mitigate light concentration in a specific direction by forming a second curved portion (CV2) in a transmission area (TA).

[0155] The transmission region (TA) has a square shape as illustrated in FIG. 9a, and may be provided with second curved sections (CV2) at four corners. The transmission region (TA) may include four straight sections (ST) connecting the second curved sections (CV2), with the four corners formed by curves. The four straight sections (ST) may be arranged parallel to the opposing straight sections (ST). When external light passes through the straight sections (ST), orthogonal diffraction patterns may be formed as the light is concentrated only in specific directions, e.g., the first direction (X-axis direction) and the second direction (Y-axis direction). On the other hand, the four second curved sections (CV2) are not parallel to the opposing second curved sections (CV2). When external light passes through the second curved section (CV2), the light is not concentrated in a specific direction, and a diffraction pattern can be formed along the second curved section (CV2). As a result, the transparent display panel (110) can mitigate the concentration of light in a specific direction by utilizing the second curved section (CV2).

[0156] Meanwhile, the transmission region (TA) can increase the proportion of the second curved sections (CV2) at the edge by reducing the length of each of the four straight sections (ST) and increasing the length of each of the four second curved sections (CV2) as shown in FIG. 9b. Alternatively, the transmission region (TA) can increase the proportion of the second curved sections (CV2) at the edge by having more than four second curved sections (CV2) as shown in FIG. 9c.

[0157] The transmission region (TA) shown in FIG. 9b and FIG. 9c can mitigate diffraction more than the transmission region (TA) shown in FIG. 9a, but has the disadvantage that the area of ​​the transmission region (TA) is reduced. The lengths of the second curved section (CV2) and the straight section (ST) can be determined by considering the transmittance of the transmission region (TA).

[0158] Meanwhile, the transmission regions (TA) may be arranged diagonally as shown in FIG. 9d. When the transmission regions (TA) are arranged parallel to each other along the first direction or the second direction, long diffraction patterns in the first direction and the second direction may be formed. Additionally, as the light from each of the transmission regions (TA) overlaps, the intensity of the light may become stronger. By arranging the transmission regions (TA) diagonally, the formation of long and sharp diffraction patterns can be prevented.

[0159] Additionally, the second curved section (CV2) of the transmission region (TA) may be formed as a curve as shown in FIGS. 9a to 9d, but is not necessarily limited thereto. The second curved section (CV2) of the transmission region (TA) may also be formed of multiple diagonal lines as shown in FIG. 9e.

[0160] Referring again to FIG. 2, the non-display area (NDA) may be provided with a pad area (PA) in which pads (PADs) are arranged and at least one gate driver (205).

[0161] Specifically, the non-display area (NDA) may include a first non-display area (NDA1) on which pads (PAD) are placed, a second non-display area (NDA2) placed parallel to the first non-display area (NDA1) with a display area (DA) in between, a third non-display area (NDA3) connecting the first non-display area (NDA1) and the second non-display area (NDA2), and a fourth non-display area (NDA4).

[0162] A gate driver (205) is connected to gate lines (GL) to supply gate signals. This gate driver (205) may be placed in at least one of a third non-display area (NDA3) and a fourth non-display area (NDA4) in a gate driver in panel (GIP) manner. For example, as shown in FIG. 2, a gate driver (205) may be formed in the third non-display area (NDA3) and another gate driver (205) may be formed in the fourth non-display area (NDA4), but is not necessarily limited thereto. A gate driver (205) may be formed in only one of the third non-display area (NDA3) and the fourth non-display area (NDA4).

[0163] The pads (PADs) may include a first pad (VDDP), a second pad (VSSP), a third pad (VREFP), and a fourth pad (DP), and may be provided within a first non-display area (NDA1). That is, the first non-display area (NDA1) may include a pad area (PA).

[0164] A transparent display panel (110) according to one embodiment of the present invention may have a plurality of circuits and a plurality of metal lines disposed in a non-display area (NDA), particularly, a first non-display area (NDA1) and a second non-display area (NDA2). The plurality of circuits may include electrostatic discharge circuits and multiplex circuits disposed in the first non-display area (NDA1).

[0165] For example, the anti-static circuits may be circuits for preventing static electricity from entering or being generated in the transparent display panel (110). These anti-static circuits may be placed in the first non-display area (NDA1). Specifically, the anti-static circuits may be placed in the area (ESDA) between the reference line (VREF1) and the common power line (VSS1) provided in the first non-display area (NDA1), as shown in FIG. 5.

[0166] For example, each of the multiplex circuits may be a circuit for time-division driving multiple data lines. These multiplex circuits may be placed in a first non-display area (NDA1). Specifically, as shown in FIG. 5, the multiplex circuits may be placed in an area (MUXA) between a common power line (VSS1) and a display area (DA) provided in the first non-display area (NDA1).

[0167] A transparent display panel (110) according to one embodiment of the present invention may include a plurality of signal lines connected to subpixels (P1, P2, P3) provided in a display area (DA). For example, a transparent display panel (110) according to one embodiment of the present invention may include a pixel power line (VDD), a common power line (VSS), and a reference line (VREF).

[0168] The pixel power line (VDD) can supply a first power to each driving transistor (T) of the subpixels (P1, P2, P3) provided in the display area (DA).

[0169] To this end, the pixel power line (VDD) may include a first pixel power line (VDD1) provided in a first non-display area (NDA1), a second pixel power line (VDD2) provided in a second non-display area (NDA2), and a plurality of third pixel power lines (VDDL) connecting the first pixel power line (VDD1) and the second pixel power line (VDD2).

[0170] The common power line (VSS) can supply a second power to the cathode electrode (140) of the subpixels (P1, P2, P3) provided in the display area (DA). At this time, the second power may be a common power supplied to the subpixels (P1, P2, P3) in common.

[0171] To this end, the common power line (VSS) may include a first common power line (VSS1) provided in a first non-display area (NDA1), a second common power line (VSS2) provided in a second non-display area (NDA2), and a plurality of third common power lines (VSSL) connecting the first common power line (VSS1) and the second common power line (VSS2).

[0172] The reference line (VREF) can supply an initialization voltage (or sensing voltage) to the driving transistor (T) of each of the subpixels (P1, P2, P3) provided in the display area (DA).

[0173] To this end, the reference line (VREF) may include a first reference line (VREF1) provided in a first non-display area (NDA1) and a plurality of second reference lines (VREFL) placed in a display area (DA).

[0174] Hereinafter, with reference to FIGS. 10 to 13, the first pixel power line (VDD1), the first common power line (VSS1), and the first reference line (VREF1) provided in the first non-display area (NDA1) will be described in more detail.

[0175] FIG. 10 is an enlarged view of area B of FIG. 2, FIG. 11 is a cross-sectional view showing an example of III-III of FIG. 10, FIG. 12 is a cross-sectional view showing an example of IV-IV of FIG. 10, and FIG. 13 is a cross-sectional view showing an example of VV of FIG. 10.

[0176] The first non-display area (NDA1) may be provided with pads (PAD) including a first pad (VDDP), a second pad (VSSP), a third pad (VREFP), and a fourth pad (DP) as shown in FIG. 10, a first pixel power line (VDD1), a first common power line (VSS1), a first reference line (VREF1), third pixel power lines (VDDL), and third common power lines (VSSL).

[0177] Referring to FIGS. 2, FIGS. 10, and FIGS. 11, a first pixel power line (VDD1) may be provided to extend in a first direction (X-axis direction) between a first non-display area (NDA1), specifically, between a pad area (PA) and a display area (DA). The first pixel power line (VDD1) may be connected to a first pad (VDDP) in the first non-display area (NDA1) and may receive a first power supply from the first pad (VDDP). The first pad (VDDP) may be extended in a second direction (Y-axis direction) and connected to the first pixel power line (VDD1). For example, the first pixel power line (VDD1) and the first pad (VDDP) may be provided on the same layer as shown in FIG. 11 and may be connected to each other without being separated.

[0178] In addition, the first pixel power line (VDD1) is connected to a plurality of third pixel power lines (VDDL) placed in the display area (DA), and can supply a first power to each driving transistor (T) of the subpixels (P1, P2, P3) through the plurality of third pixel power lines (VDDL).

[0179] This first pixel power line (VDD1) may be composed of a plurality of metal layers. For example, the first pixel power line (VDD1) may include a first metal layer (VDD1-1) and a second metal layer (VDD1-2) provided on the first metal layer (VDD1-1), as shown in FIG. 11. The first metal layer (VDD1-1) and the second metal layer (VDD1-2) overlap each other and may be connected to each other through a fourth contact hole (CH4).

[0180] At this time, the first metal layer (VDD1-1) of the first pixel power line (VDD1) may be provided in the same layer as the source electrode (SE) and drain electrode (DE) of the driving transistor (T) provided in the display area (DA). The first metal layer (VDD1-1) may be provided with the same material as the source electrode (SE) and drain electrode (DE) of the driving transistor (T).

[0181] The second metal layer (VDD1-2) of the first pixel power line (VDD1) may be provided in the same layer as the anode auxiliary electrode (115) provided in the display area (DA). The second metal layer (VDD1-2) may be provided with the same material as the anode auxiliary electrode (115). In this case, the second metal layer (VDD1-2) of the first pixel power line (VDD1) may be connected to the first metal layer (VDD1-1) through a plurality of fifth contact holes (CH5) penetrating the first planarization film (PLN1).

[0182] A transparent display panel (110) according to one embodiment of the present invention can increase the total area of ​​the first pixel power line (VDD1) by providing a first pixel power line (VDD1) in a double layer in a first non-display area (NDA1), and accordingly, reduce the resistance of the first pixel power line (VDD1).

[0183] In addition, a transparent display panel (110) according to one embodiment of the present invention connects the second metal layer (VDD1-2) of the first pixel power line (VDD1) to the first metal layer (VDD1-1) of the first pixel power line (VDD1) through a plurality of fifth contact holes (CH5), thereby enabling the first metal layer (VDD1-1) and the second metal layer (VDD1-2) to be stably connected.

[0184] Meanwhile, a transparent display panel (110) according to one embodiment of the present invention does not make full contact between the first metal layer (VDD1-1) and the second metal layer (VDD1-2) of the first pixel power line (VDD1). When the first metal layer (VDD1-1) and the second metal layer (VDD1-2) are made full contact, even if a second planarization film (PLN2) is deposited on the second metal layer (VDD1-2), the upper surface in the area where the first metal layer (VDD1-1) and the second metal layer (VDD1-2) are in contact may not be planarized and may be formed concavely toward the first substrate (111). Accordingly, a problem may arise in which films formed on the upper portion of the first metal layer (VDD1-1) and the second metal layer (VDD1-2) of the first pixel power line (VDD1), such as the second common power connection electrode (185), cathode electrode (140), and encapsulation film (150), cannot be stably deposited.

[0185] A transparent display panel (110) according to one embodiment of the present invention can make contact through a plurality of fifth contact holes (CH5) without making full contact between the first metal layer (VDD1-1) and the second metal layer (VDD1-2) of the first pixel power line (VDD1). A transparent display panel (110) according to one embodiment of the present invention can provide a flat upper surface even in the area where the first metal layer (VDD1-1) and the second metal layer (VDD1-2) are in contact by forming a second flattening film (PLN2) on the second metal layer (VDD1-2). Accordingly, in a transparent display panel (110) according to one embodiment of the present invention, films formed on the upper portion of the first metal layer (VDD1-1) and the second metal layer (VDD1-2) of the first pixel power line (VDD1), such as a second common power connection electrode (185), a cathode electrode (140), and a sealing film (150), can be stably deposited.

[0186] The second pixel power line (VDD2) can be extended in the first direction (X-axis direction) from the second non-display area (NDA2). The second pixel power line (VDD2) can be electrically connected to the first pixel power line (VDD2) through the third pixel power line (VDDL).

[0187] The second pixel power line (VDD2) may be composed of multiple layers, similar to the first pixel power line (VDD1). For example, the second pixel power line (VDD2) may be composed of a first metal layer and a second metal layer provided on the first metal layer, similar to the first pixel power line (VDD1).

[0188] A third pixel power line (VDDL) is provided between the transparent regions (TA) in the display area (DA) and can be connected to the driving transistor (T) of each of the subpixels (P1, P2, P3). This third pixel power line (VDDL) extends in a second direction (Y-axis direction) in the display area (DA) and one end can be connected to the first pixel power line (VDD1).

[0189] At this time, the third pixel power line (VDDL) may be connected to the first pixel power line (VDD1) in one layer, but as shown in FIG. 11, it may also be connected to the first pixel power line (VDD1) in multiple layers.

[0190] For example, the third pixel power line (VDDL) may include a second metal layer (VDDL-2) and a third metal layer (VDDL-3) provided below the second metal layer (VDDL-2). The second metal layer (VDDL-2) of the third pixel power line (VDDL) may extend in a second direction (Y-axis direction) from the display area (DA) to the first non-display area (NDA1). The second metal layer (VDDL-2) may be provided in the same layer as the anode auxiliary electrode (115) provided in the display area (DA). The second metal layer (VDDL-2) may be provided with the same material as the anode auxiliary electrode (115).

[0191] A third metal layer (VDDL-3) of a third pixel power line (VDDL) may have one end connected to the second metal layer (VDDL-2) of the third pixel power line (VDDL) in the first non-display area (NDA1), and the other end connected to the first pixel power line (VDDL). The third metal layer (VDDL-3) may be provided in the same layer as the gate electrode (GE) of the driving transistor (T) provided in the display area (DA). The third metal layer (VDDL-3) may be provided with the same material as the gate electrode (GE) of the driving transistor (T).

[0192] The third metal layer (VDDL-3) of the third pixel power line (VDDL) can be connected to the second metal layer (VDDL-2) of the third pixel power line (VDDL) at one end, with the first metal layer (VDDL-1) in between. In this case, the third metal layer (VDDL-3) of the third pixel power line (VDDL) can be connected to the first metal layer (VDDL-1) through a sixth contact hole (CH6) that penetrates the insulating films (ILD1, ILD2) between the first and second layers. The first metal layer (VDDL-1) can be connected to the second metal layer (VDDL-2) of the third pixel power line (VDDL) through a seventh contact hole (CH7) that penetrates the first planarization film (PLN1). Accordingly, the third metal layer (VDDL-3) of the third pixel power line (VDDL) can be electrically connected to the second metal layer (VDDL-2) of the third pixel power line (VDDL).

[0193] Additionally, the third metal layer (VDDL-3) of the third pixel power line (VDDL) can be connected to the first metal layer (VDD1-1) of the first pixel power line (VDD1) through an eighth contact hole (CH8) that penetrates the insulating film between the first and second layers (ILD1, ILD2) at the other end.

[0194] Meanwhile, the third metal layer (VDDL-3) of the third pixel power line (VDDL) may be formed as a single line pattern between the second metal layer (VDDL-2) and the first pixel power line (VDD), but is not necessarily limited thereto. The third metal layer (VDDL-3) of the third pixel power line (VDDL) may include a plurality of line patterns provided between the second metal layer (VDDL-2) and the first pixel power line (VDD). In this case, the third metal layer (VDDL-3) of the third pixel power line (VDDL) may have a plurality of line patterns electrically connected through a metal layer provided in another layer, such as the first metal layer (VDDL-1).

[0195] Referring to FIGS. 2, FIG. 10, and FIG. 12, a first common power line (VSS1) may be provided to extend in a first direction (X-axis direction) between a first non-display area (NDA1), specifically, between a first pixel power line (VDD1) and a display area (DA). The first common power line (VSS1) may be connected to a second pad (VSSP) in the first non-display area (NDA1) and may receive a second power from the second pad (VSSP). Additionally, the first common power line (VSS1) may be connected to a plurality of third common power lines (VSSL) disposed in the display area (DA) and may supply a second power to the cathode electrodes (140) of subpixels (P1, P2, P3) through the plurality of third common power lines (VSSL).

[0196] This first common power line (VSS1) may be composed of a plurality of metal layers. For example, the first common power line (VSS1) may include a first metal layer (VSS1-1) and a second metal layer (VSS1-2) provided on the first metal layer (VSS1-1), as shown in FIG. 12. The first metal layer (VSS1-1) and the second metal layer (VSS1-2) overlap each other and may be connected to each other through a fifth contact portion (CT5).

[0197] At this time, the first metal layer (VSS1-1) of the first common power line (VSS1) may be provided in the same layer as the source electrode (SE) and drain electrode (DE) of the driving transistor (T) provided in the display area (DA). The first metal layer (VSS1-1) may be provided with the same material as the source electrode (SE) and drain electrode (DE) of the driving transistor (T).

[0198] The second metal layer (VSS1-2) of the first common power line (VSS1) may be provided in the same layer as the anode auxiliary electrode (115) provided in the display area (DA). The second metal layer (VSS1-2) may be provided with the same material as the anode auxiliary electrode (115).

[0199] In this case, the second metal layer (VSS1-2) of the first common power line (VSS1) can be connected to the first metal layer (VSS1-1) through a fifth contact portion (CT5) that penetrates the first flattening film (PLN1). The fifth contact portion (CT5) can remove a portion of the first flattening film (PLN1) and expose a portion of the upper surface of the first metal layer (VSS1-1) of the first common power line (VSS1). At this time, the fifth contact portion (CT5) can expose the upper surface of the first metal layer (VSS1-1) of the first common power line (VSS1) along the first direction (X-axis direction). The second metal layer (VSS1-2) of the first common power line (VSS1) can come into direct contact with the exposed upper surface of the first metal layer (VSS1-1) of the first common power line (VSS1). Through this, the second metal layer (VSS1-2) of the first common power line (VSS1) can be stably connected to the first metal layer (VSS1-1) of the first common power line (VSS1) by having a large contact area.

[0200] A transparent display panel (110) according to one embodiment of the present invention can increase the total area of ​​the first common power line (VSS1) by providing a first common power line (VSS1) in a double layer in a first non-display area (NDA1), and accordingly, reduce the resistance of the first common power line (VSS1).

[0201] Meanwhile, the first common power line (VSS1) can be electrically connected to the second pad (VSSP) provided in the pad area (PA). At this time, the first pixel power line (VDD1) and the first reference line (VREF1) may be provided between the first common power line (VSS1) and the second pad (VSSP). If the first common power line (VSS1) is formed on the same layer as the first pixel power line (VDD1) and the first reference line (VREF1), the first common power line (VSS1) and the second pad (VSSP) cannot be formed integrally on the same layer.

[0202] A transparent display panel (110) according to one embodiment of the present invention can electrically connect a first common power line (VSS1) and a second pad (VSSP) using a plurality of connecting electrodes arranged on different layers.

[0203] Specifically, a transparent display panel (110) according to one embodiment of the present invention can electrically connect a first common power line (VSS1) and a second pad (VSSP) using a first common power connection electrode (180) and a second common power connection electrode (185) disposed on different layers.

[0204] The first common power connection electrode (180) is provided in the first non-display area (NDA1). The first common power connection electrode (180) is provided between the first common power line (VSS1) and the first substrate (111) to electrically connect the first common power line (VSS1) and the second pad (VSSP).

[0205] For example, the first common power connection electrode (180) may be provided on the same layer as the gate electrode (GE) of the driving transistor (T) provided in the display area (DA). Additionally, the first common power connection electrode (180) may be provided with the same material as the gate electrode (GE) of the driving transistor (T).

[0206] One end of the first common power connection electrode (180) may be connected to the first common power line (VSS1), and the other end may be connected to the second pad (VSSP). Specifically, the first common power connection electrode (180) may be connected at one end to the first metal layer (VSS1-1) of the first common power line (VSS1) through a ninth contact hole (CH9) that penetrates the first and second interlayer insulating films (ILD1, ILD2). Additionally, the first common power connection electrode (180) may be connected at the other end to the second pad (VSSP) through a tenth contact hole (CH10) that penetrates the first and second interlayer insulating films (ILD1, ILD2).

[0207] Meanwhile, the first common power connection electrode (180) may be formed as a single electrode between the second pad (VSSP) and the first common power line (VSS1), but is not necessarily limited thereto. The first common power connection electrode (180) may include a plurality of electrodes.

[0208] For example, the first common power connection electrode (180) may include one first common power connection electrode (181), another first common power connection electrode (182), and yet another first common power connection electrode (183) as shown in FIG. 12.

[0209] One first common power connection electrode (181) can be connected to the first common power line (VSS1) through the ninth contact hole (CH9), and the other first common power connection electrode (182) can be connected to the second pad (VSSP) through the tenth contact hole (CH10). One first common power connection electrode (181) and the other first common power connection electrode (182) can be provided on the same layer as the gate electrode (GE) of the driving transistor (T).

[0210] Another first common power connection electrode (183) provided on a different layer from one first common power connection electrode (181) and another first common power connection electrode (182) may have one end connected to one first common power connection electrode (181) through a first contact hole (CH11) and the other end connected to another first common power connection electrode (182) through a second contact hole (CH12). At this time, the other first common power connection electrode (183) may be provided on the same layer as the source electrode (SE) and drain electrode (DE) of the driving transistor (T).

[0211] The second common power connection electrode (185) is provided in the first non-display area (NDA1) and may overlap with the first common power connection electrode (180). The second common power connection electrode (185) is provided on the first common power line (VSS1) to electrically connect the first common power line (VSS1) and the second pad (VSSP).

[0212] For example, the second common power connection electrode (185) may be provided in the same layer as the anode electrode (120) of the light-emitting element provided in the display area (DA). Additionally, the second common power connection electrode (185) may be provided with the same material as the anode electrode (120) of the light-emitting element.

[0213] One end of this second common power connection electrode (185) may be connected to the first common power line (VSS1), and the other end may be connected to the second pad (VSSP). Specifically, the second common power connection electrode (185) may be connected at one end to the second metal layer (VSS1-2) of the first common power line (VSS1) through the first contact portion (CT1). The first contact portion (CT1) may remove a portion of the second planarization film (PLN2) and expose a portion of the upper surface of the second metal layer (VSS1-2) of the first common power line (VSS1). At this time, the first contact portion (CT1) may expose the upper surface of the second metal layer (VSS1-2) of the first common power line (VSS1) along the first direction (X-axis direction). The second common power connection electrode (185) may come into direct contact with the exposed upper surface of the first common power line (VSS1). Through this, the second common power connection electrode (185) can be stably connected to the first common power line (VSS1) by having a large contact area. Meanwhile, the first contact portion (CT1) can be formed to overlap with the fifth contact portion (CT5).

[0214] The second common power connection electrode (185) can be connected to the second pad (VSSP) through the second contact portion (CT2) at the other end. The second contact portion (CT2) can remove a portion of the second planarization film (PLN2) and expose a portion of the upper surface of the second pad (VSSP). The second pad (VSSP) may be provided with a plurality of pad portions as shown in FIG. 2. At this time, two adjacent pad portions can be connected to each other through a pad connection electrode (PC). The second contact portion (CT2) can expose the upper surface of the second pad (VSSP) connected by the pad connection electrode (PC) along the first direction (X-axis direction). The second common power connection electrode (185) can come into direct contact with the exposed upper surface of the second pad (VSSP). Through this, the second common power connection electrode (185) can be stably connected to the second pad (VSSP) by having a large contact area.

[0215] Additionally, the second common power connection electrode (185) can be electrically connected to the cathode electrode (140) through the cathode contact portion (CCT) in the first non-display area (NDA1). The cathode contact portion (CCT) can remove a portion of the bank (125) and expose a portion of the upper surface of the second common power connection electrode (185). The cathode contact portion (CCT) can expose the upper surface of the second common power connection electrode (185) along the first direction (X-axis direction). Through this, the second common power connection electrode (185) can be stably connected to the cathode electrode (140) by having a large contact area.

[0216] Consequently, the first common power line (VSS1) can be electrically connected to the cathode electrode (140) through the second common power connection electrode (185). Accordingly, the first common power line (VSS1) can supply the second power delivered from the second pad (VSSP) to the cathode electrode (140).

[0217] A transparent display panel (110) according to one embodiment of the present invention may be connected to each other using a first common power connection electrode (180) and a second common power connection electrode (185) disposed on different layers, wherein a first common power connection electrode (180) and a second common power connection electrode (185) disposed in a first non-display area (NDA1) may be provided below the first common power line (VSS1) and the second pad (VSSP), and the second common power connection electrode (185) may be provided on the first common power line (VSS1) and the second pad (VSSP).

[0218] Accordingly, the transparent display panel (110) according to one embodiment of the present invention can increase the total area of ​​the common power line (VSS), and thereby reduce the resistance of the common power line (VSS).

[0219] In addition, in a transparent display panel (110) according to one embodiment of the present invention, even if a defect occurs in either the first common power connection electrode (180) or the second common power connection electrode (185), the first common power line (VSS1) and the second pad (VSSP) can be connected by the other one. Accordingly, the transparent display panel (110) according to one embodiment of the present invention can stably supply the first power to the subpixels (P1, P2, P3), thereby improving the panel yield.

[0220] The second common power line (VSS2) may extend in the first direction (X-axis direction) from the second non-display area (NDA2). The second common power line (VSS2) may be electrically connected to the first common power line (VSS2) through the third common power line (VSSL).

[0221] The second common power line (VSS2) may be composed of multiple layers, similar to the first common power line (VSS1). For example, the second common power line (VSS2) may be composed of a first metal layer and a second metal layer provided on the first metal layer, similar to the first common power line (VSS1).

[0222] A third common power line (VSSL) is provided between the transparent areas (TA) in the display area (DA). At this time, a transparent display panel (110) according to one embodiment of the present invention can minimize the non-transparent area (NTA) within the display area (DA) by alternately arranging the third common power line (VSSL) and the third pixel power line (VDDL) between the transparent areas (TA) of the display area (DA). Accordingly, the transparent display panel (110) according to one embodiment of the present invention can increase the transmittance by increasing the transparent area (TA).

[0223] Meanwhile, the third common power line (VSSL) extends in the second direction (Y-axis direction) from the display area (DA), and one end may be connected to the first common power line (VSS1). For example, the third common power line (VSSL) and the first common power line (VSS1) may be provided on the same layer as shown in FIG. 12 and may be connected to each other without being separated.

[0224] Referring to FIGS. 2, FIGS. 10, and FIGS. 13, a first reference line (VREF1) may be provided to extend in a first direction (X-axis direction) between a first non-display area (NDA1), specifically between a first pixel power line (VDD1) and a first common power line (VSS1). The first reference line (VREF1) is connected to a third pad (VREFP) in the first non-display area (NDA1) and may receive an initialization voltage (or sensing voltage) from the third pad (VREFP). Additionally, the first reference line (VREF1) may be connected to a plurality of second reference lines (VREFL) disposed in a display area (DA) and may supply an initialization voltage (or sensing voltage) to a driving transistor (T) of each of the subpixels (P1, P2, P3) through the plurality of second reference lines (VREFL).

[0225] This first reference line (VREF1) may be composed of a plurality of metal layers. For example, the first reference line (VREF1) may include a first metal layer (VREF1-1) and a second metal layer (VREF1-2) provided on the first metal layer (VREF1-1), as shown in FIG. 13. The first metal layer (VREF1-1) and the second metal layer (VREF1-2) overlap each other and may be connected to each other through a 13th contact hole (CH13).

[0226] At this time, the first metal layer (VREF1-1) of the first reference line (VREF1) may be provided in the same layer as the source electrode (SE) and drain electrode (DE) of the driving transistor (T) provided in the display area (DA). The first metal layer (VREF1-1) may be provided with the same material as the source electrode (SE) and drain electrode (DE) of the driving transistor (T).

[0227] The second metal layer (VREF1-2) of the first reference line (VREF1) may be provided in the same layer as the anode auxiliary electrode (115) provided in the display area (DA). The second metal layer (VREF1-2) may be provided with the same material as the anode auxiliary electrode (115). In this case, the second metal layer (VREF1-2) of the first reference line (VREF1) may be connected to the first metal layer (VREF1-1) through a 13th contact hole (CH13) penetrating the first planarization film (PLN1).

[0228] A transparent display panel (110) according to one embodiment of the present invention can increase the total area of ​​the first reference line (VREF1) by providing a first reference line (VREF1) in a non-display area (NDA) in a double layer, and accordingly, reduce the resistance of the first reference line (VREF1).

[0229] Meanwhile, the first reference line (VREF1) can be electrically connected to the third pad (VREFP) provided in the pad area (PA). At this time, a first pixel power line (VDD1) may be provided between the first reference line (VREF1) and the third pad (VREFP). If the first reference line (VREF1) is formed on the same layer as the first pixel power line (VDD1), the first reference line (VREF1) and the third pad (VREFP) cannot be formed integrally on the same layer.

[0230] A transparent display panel (110) according to one embodiment of the present invention can electrically connect a first reference line (VREF1) and a third pad (VREFP) using a plurality of connecting electrodes arranged on different layers.

[0231] Specifically, a transparent display panel (110) according to one embodiment of the present invention can electrically connect a first reference line (VREF1) and a third pad (VREFP) using a first reference connection electrode (190) and a second reference connection electrode (195) disposed on different layers.

[0232] The first reference connection electrode (190) is provided in the first non-display area (NDA1). The first reference connection electrode (190) is provided between the first reference line (VREF1) and the first substrate (111) to electrically connect the first reference line (VREF1) and the third pad (VREFP).

[0233] For example, the first reference connection electrode (190) may be provided on the same layer as the gate electrode (GE) of the driving transistor (T) provided in the display area (DA). Additionally, the first reference connection electrode (190) may be provided with the same material as the gate electrode (GE) of the driving transistor (T).

[0234] One end of the first reference connection electrode (190) may be connected to the first reference line (VREF1), and the other end may be connected to the third pad (VREFP). Specifically, the first reference connection electrode (190) may be connected at one end to the first metal layer (VREF1-1) of the first reference line (VREF1) through a 14th contact hole (CH14) that penetrates the first and second interlayer insulating films (ILD1, ILD2). Additionally, the first reference connection electrode (190) may be connected at the other end to the third pad (VREFP) through a 15th contact hole (CH15) that penetrates the first and second interlayer insulating films (ILD1, ILD2).

[0235] Meanwhile, the first reference connection electrode (190) may be formed as a single electrode between the first reference line (VREF1) and the third pad (VREFP), but is not necessarily limited thereto. The first reference connection electrode (190) may include a plurality of electrodes.

[0236] The second reference connection electrode (195) is provided in the first non-display area (NDA1) and may overlap with the first reference connection electrode (190). The second reference connection electrode (195) is provided on the first reference line (VREF1) to electrically connect the first reference line (VREF1) and the third pad (VREFP).

[0237] For example, the second reference connection electrode (195) may be provided in the same layer as the anode electrode (120) of the light-emitting element provided in the display area (DA). Additionally, the second reference connection electrode (195) may be provided with the same material as the anode electrode (120) of the light-emitting element.

[0238] One end of this second reference connection electrode (195) may be connected to the first reference line (VREF1), and the other end may be connected to the third pad (VREFP). Specifically, the second reference connection electrode (195) may be connected at one end to the second metal layer (VREF1-2) of the first reference line (VREF1) through the third contact portion (CT3). The third contact portion (CT3) may remove a portion of the second planarization film (PLN2) and expose a portion of the upper surface of the second metal layer (VREF1-2) of the first reference line (VREF1). At this time, the third contact portion (CT3) may expose the upper surface of the second metal layer (VREF1-2) of the first reference line (VREF1) along the first direction (X-axis direction). Through this, the second reference connection electrode (195) can be stably connected to the first reference line (VREF1) by having a large contact area.

[0239] The second reference connection electrode (195) can be connected to the third pad (VREFP) through the fourth contact portion (CT4) at the other end. The fourth contact portion (CT4) can remove a portion of the second planarization film (PLN2) and expose a portion of the upper surface of the third pad (VREFP). At this time, the fourth contact portion (CT4) can expose the upper surface of the third pad (VREFP) along the first direction (X-axis direction). The second reference connection electrode (195) can come into direct contact with the exposed upper surface of the third pad (VREFP). Through this, the second reference connection electrode (195) can be stably connected to the third pad (VREFP) by having a large contact area.

[0240] These second reference connection electrodes (195) are formed on the same layer as the second common power connection electrode (185) but are spaced apart and are not electrically connected to each other.

[0241] A transparent display panel (110) according to one embodiment of the present invention may be connected to each other using a first reference connecting electrode (190) and a second reference connecting electrode (195) disposed on different layers, wherein a first reference line (VREF1) and a third pad (VREFP) disposed in a first non-display area (NDA1). At this time, the first reference connecting electrode (190) may be provided below the first reference line (VREF1) and the third pad (VREFP), and the second reference connecting electrode (195) may be provided on the first reference line (VREF1) and the third pad (VREFP).

[0242] Accordingly, a transparent display panel (110) according to one embodiment of the present invention can increase the total area of ​​the first reference line (VREF1), and thereby reduce the resistance of the first reference line (VREF1).

[0243] In addition, in a transparent display panel (110) according to one embodiment of the present invention, even if a defect occurs in either the first reference connection electrode (190) or the second reference connection electrode (195), the first reference line (VREF1) and the third pad (VREFP) can be connected by the other one. Accordingly, the transparent display panel (110) according to one embodiment of the present invention can stably supply an initialization voltage (or sensing voltage) to the subpixels (P1, P2, P3), thereby improving the panel yield.

[0244] In addition, a transparent display panel (110) according to one embodiment of the present invention can inspect for defects in a driving transistor (T) before depositing an anode electrode (120).

[0245] The transparent display panel (110) can connect the first common power line (VSS1) and the second pad (VSSP) using only the second common power connection electrode (185) provided on the same layer as the anode electrode (120). Additionally, the transparent display panel (110) can connect the first reference line (VREF1) and the third pad (VREFP) using only the second reference connection electrode (195) provided on the same layer as the anode electrode (120).

[0246] In this case, the process of inspecting for defects in the driving transistor (T) must be performed after the anode electrode (120) is deposited. If a defect occurs in the driving transistor (T), a repair process can be performed to fix the defective part. At this time, in order to perform the repair process, the layers deposited on the defective layer must be removed. For example, if a defect occurs in the layer equipped with the anode auxiliary electrode (115), the second planarization film (PLN2) and the anode electrode (120) must be removed for the repair process. At this time, light emission may not occur in the corresponding area.

[0247] In this way, when a repair process is performed after forming the anode electrode (120), the repair yield decreases and the tact time increases due to the organic film (PLN2) provided on the anode auxiliary electrode (115) and the anode electrode (120).

[0248] A transparent display panel (110) according to one embodiment of the present invention can connect a first common power line (VSS1) and a second pad (VSSP) using a first common power connection electrode (180) and a second common power connection electrode (185). In a transparent display panel (110) according to one embodiment of the present invention, even if the second common power connection electrode (185) is not formed, the first common power line (VSS1) and the second pad (VSSP) can be connected through the first common power connection electrode (180).

[0249] In addition, a transparent display panel (110) according to one embodiment of the present invention can connect a first reference line (VREF1) and a third pad (VREFP) using a first reference connecting electrode (190) and a second reference connecting electrode (195). In a transparent display panel (110) according to one embodiment of the present invention, even if the second reference connecting electrode (195) is not formed, the first reference line (VREF1) and the third pad (VREFP) can be connected through the first reference connecting electrode (190).

[0250] Accordingly, a transparent display panel (110) according to one embodiment of the present invention can inspect for defects in a driving transistor (T) before depositing an anode electrode (120). That is, since the transparent display panel (110) according to one embodiment of the present invention performs a repair process before depositing a second planarization film (PLN2) and an anode electrode (120), it is possible to prevent a decrease in the repair yield due to the second planarization film (PLN2) and an anode electrode (120). In addition, the transparent display panel (110) according to one embodiment of the present invention can reduce the takt time.

[0251] Meanwhile, in a transparent display panel (110) according to one embodiment of the present invention, a pixel power line (VDD), a common power line (VSS), and a reference line (VREF) may be provided only in a first non-display area (NDA1) and a second non-display area (NDA2) within a non-display area (NDA). In a transparent display panel (110) according to one embodiment of the present invention, each of the pixel power line (VDD), the common power line (VSS), and the reference line (VREF) may be formed as a multilayer structure, and each of the common power line (VSS) and the reference line (VREF) provided in the first non-display area (NDA1) may be connected to a plurality of connecting electrodes. Accordingly, even if the pixel power line (VDD), the common power line (VSS), and the reference line (VREF) are provided only in the first non-display area (NDA1) and the second non-display area (NDA2) in a transparent display panel (110) according to one embodiment of the present invention, the respective areas can be sufficiently secured and resistance can be minimized.

[0252] A transparent display panel (110) according to one embodiment of the present invention can improve transmittance in the third non-display area (NDA3) and the fourth non-display area (NDA4) by not providing a pixel power line (VDD), a common power line (VSS), and a reference line (VREF) in the third non-display area (NDA3) and the fourth non-display area (NDA4). That is, the transparent display panel (110) according to one embodiment of the present invention can have a transmittance similar to that in the display area (DA) even in the third non-display area (NDA3) and the fourth non-display area (NDA4).

[0253] Although embodiments of the present invention have been described in more detail with reference to the attached drawings, the present invention is not necessarily limited to these embodiments and may be modified in various ways within the scope of the technical spirit of the present invention. Accordingly, the embodiments disclosed in the present invention are intended to explain, not limit, the technical spirit of the present invention, and the scope of the technical spirit of the present invention is not limited by these embodiments. Therefore, the embodiments described above should be understood as illustrative in all respects and not restrictive. The scope of protection of the present invention shall be interpreted by the claims, and all technical spirits within an equivalent scope shall be interpreted as being included within the scope of rights of the present invention. Explanation of the symbols

[0254] 100: Transparent display device 110: Transparent display panel 111: First substrate 112: Second substrate 120: Anode electrode 125: Bank 130: Organic light-emitting layer 140: Cathode electrode 150: Encapsulation film 160: Adhesive layer 170: Color filter layer 205: Gate driver VDD: Pixel power line VSS: Common power line 180: First common power connection electrode 185: Second common power connection electrode VREF: Reference line 190: First reference connecting electrode 195: Second reference connecting electrode

Claims

Claim 1 A transparent display device comprising: a substrate having a display area including a transparent area and a non-transparent area in which a plurality of subpixels are arranged, and a non-display area surrounding the display area; at least one insulating film provided on the substrate; a plurality of anode electrodes provided on each of the plurality of subpixels on the at least one insulating film; a bank provided between the plurality of anode electrodes; a light-emitting layer provided on the plurality of anode electrodes; a cathode electrode provided on the light-emitting layer; and a color filter layer formed on the cathode electrode, wherein the insulating film and the bank are provided only in the non-transparent area, the color filter layer protrudes further than the bank in the direction of the transparent area, and the distance between the end of the color filter layer and the end of the insulating film is smaller than the distance between the end of the color filter layer and the end of the bank. Claim 2 delete Claim 3 A transparent display device according to claim 1, wherein the insulating film is a high-refractive index film with a refractive index greater than 1.

8. Claim 4 A transparent display device according to claim 1, wherein the insulating film comprises a first interlayer insulating film and a second interlayer insulating film provided on the first interlayer insulating film. Claim 5 A transparent display device according to claim 4, wherein the distance between the transparent area and the end of the first interlayer insulating film is the same as the distance between the transparent area and the end of the second interlayer insulating film. Claim 6 A transparent display device according to claim 4, wherein the distance between the transparent area and the end of the first interlayer insulating film is smaller than the distance between the transparent area and the end of the second interlayer insulating film. Claim 7 In claim 1, the plurality of anode electrodes includes a first anode electrode and a second anode electrode, and the second anode electrode is a transparent display device having a shape different from the first anode electrode. Claim 8 A transparent display device according to claim 7, further comprising: a first common power line provided on the substrate and extending in a first direction in the display area; and a gate line extending in a second direction intersecting the first common power line, wherein the first anode electrode is positioned to overlap with a first intersection area where the first common power line and the gate line intersect. Claim 9 In claim 8, the transparent display device comprises a first anode electrode having a first portion positioned to overlap with the intersection area and a second portion protruding from the first side of the first portion. Claim 10 In claim 9, the transparent display device further comprises a first anode electrode having a third portion protruding from a second side facing the first side of the first portion. Claim 11 In claim 9, the second portion of the first anode electrode is a transparent display device provided on the first common power line. Claim 12 A transparent display device according to claim 9, wherein the second portion of the first anode electrode comprises a first side facing the first portion, a second side connecting the first portion and the first side, and a third side, wherein each of the second side and the third side comprises a first curved portion. Claim 13 A transparent display device according to claim 8, further comprising a first pixel power line provided on the substrate and extending in the first direction in the display area, and further comprising a third anode electrode arranged such that the plurality of anode electrodes overlap with a second intersection area where the first pixel power line and the gate line intersect. Claim 14 In claim 13, the second anode electrode is provided between the first anode electrode and the third anode electrode, and the third anode electrode has the same shape as the first anode electrode and a different shape from the second anode electrode, forming a transparent display device. Claim 15 In paragraph 13, the above-mentioned transparent area is a transparent display device provided between the first pixel power line and the first common power line. Claim 16 In claim 1, the transparent display device wherein the transmission area comprises a plurality of second curved sections. Claim 17 A substrate having a display area including a transparent area and a non-transparent area in which a plurality of subpixels are arranged, and a non-display area surrounding the display area; a first common power line provided on the substrate and extending in a first direction from the display area; and a first pixel power line provided on the substrate and extending in the first direction from the display area, wherein the transparent area is provided between the first pixel power line and the first common power line and includes a plurality of second curved portions, and a bank provided between the plurality of subpixels; and a color filter layer formed on the bank, wherein the color filter layer protrudes further than the bank in the direction of the transparent area, and a plurality of anode electrodes provided on the substrate and provided on each of the plurality of subpixels; A transparent display device further comprising an insulating film provided between the substrate and the plurality of anode electrodes, wherein the bank is provided between the plurality of anode electrodes and is provided only in the non-transparent region, and the distance between the end of the color filter layer and the end of the insulating film is smaller than the distance between the end of the color filter layer and the end of the bank. Claim 18 delete Claim 19 delete Claim 20 A transparent display device according to claim 17, further comprising a gate line extended in a second direction intersecting the common power line and the pixel power line, wherein the plurality of anode electrodes include a first anode electrode arranged to overlap with a first intersection area where the first common power line and the gate line intersect, a third anode electrode arranged to overlap with a second intersection area where the first pixel power line and the gate line intersect, and a second anode electrode arranged between the first anode electrode and the third anode electrode. Claim 21 In claim 20, the transparent display device wherein each of the first anode electrode and the third anode electrode comprises a plurality of first curved sections. Claim 22 A transparent display device according to claim 1, further comprising a first common power line formed on the substrate and extending in a first direction in the display area, wherein the cathode electrode overlaps with the first common power line. Claim 23 A transparent display device according to claim 1, further comprising a first pixel power line formed on the substrate and extending in a first direction in the display area, wherein the cathode electrode overlaps with the first pixel power line. Claim 24 A transparent display device according to claim 1, further comprising a reference line formed on the substrate, wherein the cathode electrode overlaps the reference line and the non-display area. Claim 25 A transparent display device according to claim 1, further comprising a second common power line formed on the substrate and extending in a second direction in the non-display area, wherein the cathode electrode overlaps with the second common power line in the non-display area. Claim 26 A transparent display device according to claim 1, further comprising: a second common power line formed on the substrate and extending in a second direction in the non-display area; and a common power connection electrode electrically connected through the cathode electrode and the cathode contact portion, wherein the common power connection electrode overlaps with the second common power line in the non-display area. Claim 27 A transparent display device according to claim 1, further comprising: a reference line formed on the substrate; and a common power connection electrode electrically connected through the cathode electrode and the cathode contact portion, wherein the common power connection electrode overlaps the reference line and the non-display area. Claim 28 A transparent display device according to claim 1, further comprising: a second pixel power line formed on the substrate and extending in a second direction in the non-display area; and a common power connection electrode electrically connected through the cathode electrode and the cathode contact portion, wherein the common power connection electrode overlaps with the second pixel power line in the non-display area. Claim 29 A transparent display device according to claim 22, further comprising a sealing film formed on the cathode electrode, wherein the sealing film covers an area where the cathode electrode and the first common power line overlap. Claim 30 A transparent display device according to claim 23, further comprising a sealing film formed on the cathode electrode, wherein the sealing film covers an area where the cathode electrode and the first pixel power line overlap. Claim 31 A transparent display device according to claim 24, further comprising a sealing film formed on the cathode electrode, wherein the sealing film covers an area where the cathode electrode and the reference line overlap. Claim 32 A transparent display device according to claim 25, further comprising a sealing film formed on the cathode electrode, wherein the sealing film covers an area where the cathode electrode and the second common power line overlap. Claim 33 In claim 26, a transparent display device further comprising a sealing film formed on the cathode electrode, wherein the sealing film covers an area where the common power connection electrode and the second common power line overlap. Claim 34 A transparent display device according to claim 27, further comprising a sealing film formed on the cathode electrode, wherein the sealing film covers an area where the common power connection electrode and the reference line overlap. Claim 35 A transparent display device according to claim 28, further comprising a sealing film formed on the cathode electrode, wherein the sealing film covers an area where the common power connection electrode and the second pixel power line overlap. Claim 36 A transparent display device according to claim 1, wherein the plurality of subpixels include a first subpixel, a second subpixel, and a third subpixel, and the area of ​​the first subpixel and the third subpixel is larger than the area of ​​the second subpixel. Claim 37 A transparent display device according to claim 36, wherein the first subpixel includes a first light-emitting region, the second subpixel includes a second light-emitting region, and the third subpixel includes a third light-emitting region, and the area of ​​the first light-emitting region and the area of ​​the third light-emitting region are larger than the area of ​​the second light-emitting region. Claim 38 In claim 1, the bank is a transparent display device covering the edges of the anode electrodes. Claim 39 In claim 1, the insulating film is a transparent display device that protrudes further than the bank in the direction of the transparent area.

Images