Display module

Abstract

A display panel comprises a base member, a circuit layer disposed on the base member, a light-emitting element layer disposed on the circuit layer, and an encapsulation layer disposed on the light-emitting element layer. The base member includes an island portion and a plurality of hinge portions, allowing it to stretch well in a predetermined direction. The circuit layer includes a plurality of transistors and wirings. The elongation of the material comprising the control electrode of each of the plurality of transistors is smaller than the elongation of the material comprising the wirings. The wirings are disposed on the hinge portions, and some of the wirings overlap each other.

Description

Technology Field

[0001] The present invention relates to a display module, and specifically to a stretchable display module that can be stretched by an externally applied force. Background Technology

[0002] Display devices provide information to users by displaying various images on a screen. Generally, display devices display information within an allocated screen.

[0003] Recently, flexible display devices including flexible display modules that possess flexibility are being developed. Unlike flat panel displays, flexible display devices can be folded, rolled, bent, or stretched like paper. Flexible display devices, which can change their shape in various ways, can be carried without being constrained by existing screen sizes and can be easily placed on curved objects, thereby improving user convenience.

[0004] In particular, in a display device capable of stretching in a specific direction, light-emitting elements and wiring are arranged on a base member capable of stretching, but there was a problem in that the wiring was damaged when the base substrate stretched. The problem to be solved

[0005] The present invention aims to provide a display module in which wiring for transmitting signals to pixels is not damaged even when stretched by externally applied force. means of solving the problem

[0006] A display module according to one embodiment of the present invention may include a base member, an activation pattern, a gate insulating member, a gate metal pattern, an interlayer insulating member, a first circuit insulating member, a first metal pattern, a plurality of first wirings, a second circuit insulating member, a second metal pattern, a plurality of second wirings, a third circuit insulating member, a third metal pattern, and a plurality of third wirings.

[0007] The base member comprises a plurality of unit parts, and each of the plurality of unit parts may include an island part and a plurality of hinge parts extending from the island part.

[0008] The above activation pattern is disposed on the base member and overlaps the island portion, and may include a semiconductor material.

[0009] The gate insulating member is disposed on the base member and can cover the activation pattern.

[0010] The gate metal pattern is disposed on the gate insulating member and can overlap the island portion.

[0011] The above interlayer insulating member is disposed on the base member and can cover the gate metal pattern.

[0012] The first circuit insulating member is disposed on the base member and covers at least a portion of the gate insulating member, overlaps the island portion and the plurality of hinge portions, and a first contact hole may be defined.

[0013] The first metal pattern is disposed on the interlayer insulating member and can overlap the island portion.

[0014] The plurality of first wires are disposed on the first circuit insulating member, each of which overlaps at least one of the plurality of hinge portions, and at least one of which can be electrically connected to the gate metal pattern through the first contact hole.

[0015] The second circuit insulating member may be disposed on the first metal pattern and the plurality of first wirings.

[0016] The second metal pattern is disposed on the second circuit insulating member and can overlap the island portion.

[0017] The plurality of second wires are disposed on the second circuit insulating member, and each can overlap at least one of the plurality of hinge portions.

[0018] The third circuit insulating member may be disposed on the second metal pattern and the plurality of second wirings.

[0019] The third metal pattern is disposed on the third circuit insulating member and can overlap the island portion.

[0020] The plurality of third wires are disposed on the third circuit insulating member, and each can overlap at least one of the plurality of hinge portions.

[0021] In one embodiment of the present invention, when an external force is applied, the distance between the hinge portion of the first unit portion and the hinge portion of the second unit portion among the plurality of unit portions may change.

[0022] In one embodiment of the present invention, a plurality of second contact holes are defined in the second circuit insulating member, and the second metal pattern is electrically connected to the first metal pattern through any one of the plurality of second contact holes, and at least one of the plurality of second wirings can be electrically connected to the first metal pattern through another of the plurality of second contact holes.

[0023] In one embodiment of the present invention, a third contact hole is defined in the third circuit insulating member, and the third metal pattern can be electrically connected to the second metal pattern through the third contact hole.

[0024] A display module according to one embodiment of the present invention may further include a fourth circuit insulating member disposed on the third metal pattern and the plurality of third wirings, an anode electrode disposed on the fourth circuit insulating member, a light-emitting layer disposed on the anode electrode, and a cathode electrode disposed on the light-emitting layer.

[0025] In one embodiment of the present invention, a fourth contact hole is defined in the fourth circuit insulating member, and the anode electrode can be electrically connected to the third metal pattern through the fourth contact hole.

[0026] In one embodiment of the present invention, the fourth circuit insulating member may be black.

[0027] In one embodiment of the present invention, the gate metal pattern comprises a first metal material, and each of the first metal pattern, the second metal pattern, the third metal pattern, the plurality of first wirings, the plurality of second wirings, and the plurality of third wirings may comprise a second metal material different from the first metal material.

[0028] In one embodiment of the present invention, the first metal material comprises molybdenum, and the second metal material may comprise at least one of titanium and aluminum.

[0029] In one embodiment of the present invention, the first metal material has a first elongation, and the second metal material may have a second elongation greater than the first elongation.

[0030] In one embodiment of the present invention, at least one of the plurality of hinge portions, at least one of the plurality of first wires, at least one of the plurality of second wires, and at least one of the plurality of third wires may overlap each other.

[0031] In one embodiment of the present invention, on a plane, the width of each of the second wires may be greater than the width of each of the plurality of first wires and the width of each of the plurality of third wires.

[0032] In one embodiment of the present invention, at least one of the plurality of second wires may overlap with at least two of the plurality of first wires.

[0033] In one embodiment of the present invention, a plurality of transistors and a capacitor are defined by the activation pattern, the gate metal pattern, and the first metal pattern, and the plurality of first wirings, the plurality of second wirings, and the plurality of third wirings can be electrically connected to the plurality of transistors or the capacitor.

[0034] A display module according to one embodiment of the present invention may further include a scanning driving unit and a data driving unit. The plurality of first wires may include at least a portion of a data line that receives a data signal from the data driving unit, at least a portion of a scan line that receives a scan signal from the scanning driving unit, and at least a portion of a light emission control line that receives a light emission control signal from the scanning driving unit.

[0035] In one embodiment of the present invention, the plurality of second wires may include at least a portion of a first power line providing a first potential to any one of the plurality of transistors and at least a portion of a second power line providing the first potential to the capacitor.

[0036] A display module according to one embodiment of the present invention may further include a fourth circuit insulating member disposed on the third metal pattern and the plurality of third wirings, an anode electrode disposed on the fourth circuit insulating member, a light-emitting layer disposed on the anode electrode, and a cathode electrode disposed on the light-emitting layer. The plurality of third wirings may include at least a portion of a third power line that provides a second potential different from the first potential to the cathode electrode, and at least a portion of an initialization power line that provides an initialization potential to any one of the plurality of transistors.

[0037] In one embodiment of the present invention, the first potential may be 4.5V or higher and 5.5V or lower, the second potential may be -5.5V or higher and -4.5V or lower, and the initialization potential may be -4.5 or higher and -3.5 or lower.

[0038] In one embodiment of the present invention, the plurality of hinge portions may include a first hinge portion extending in a first direction, a second hinge portion extending in a second direction intersecting the first direction, a third hinge portion extending in a third direction opposite to the first direction, and a fourth hinge portion extending in a fourth direction opposite to the second direction. The first power line may be disposed on the first hinge portion or the third hinge portion, and the second power line may be disposed on the second hinge portion or the fourth hinge portion.

[0039] A display module according to one embodiment of the present invention may further include a fourth circuit insulating member, a first anode electrode, a second anode electrode, and a third anode electrode. The fourth circuit insulating member may be disposed on the third metal pattern and the plurality of third wires. The first anode electrode is disposed on the fourth circuit insulating member and may have a first length in one direction. The second anode electrode is disposed on the fourth circuit insulating member and is disposed adjacent to the first anode electrode and may have a second length in one direction. The third anode electrode is disposed on the fourth circuit insulating member and is disposed adjacent to the second anode electrode and may have a third length in one direction. The second length may be longer than the first length and the third length.

[0040] In one embodiment of the present invention, the second anode electrode may be disposed between the first anode electrode and the third anode electrode.

[0041] A display module according to one embodiment of the present invention may include a base member, a plurality of transistors, a capacitor, a plurality of first wirings, a plurality of second wirings, and a plurality of third wirings.

[0042] The base member comprises a plurality of unit portions, and each of the plurality of unit portions may include an island portion and a plurality of hinge portions extending from the island portion. The plurality of transistors may be disposed on the island portion. The capacitor may be disposed on the island portion. The plurality of first wires may be disposed on the plurality of hinge portions and may be electrically connected to at least some of the plurality of transistors. The plurality of second wires may be electrically connected to at least some of the plurality of transistors and the capacitor, and may overlap with corresponding first wires among the plurality of first wires. The plurality of third wires may include a plurality of third wires that are electrically connected to at least some of the plurality of transistors and overlap with corresponding first wires among the plurality of first wires and corresponding second wires among the plurality of second wires.

[0043] In one embodiment of the present invention, each of the plurality of second wires may overlap with two or three of the plurality of first wires.

[0044] In one embodiment of the present invention, the plurality of second wires may be disposed on the plurality of first wires, and the plurality of third wires may be disposed on the plurality of second wires. Effects of the invention

[0045] According to one embodiment of the present invention, by arranging the wirings that provide a signal to the pixel in an overlapping manner vertically, the stress applied to the wirings during the process of expanding the display module can be reduced.

[0046] In addition, according to one embodiment of the present invention, the wirings providing signals to the pixels are composed of a highly flexible material, thereby preventing damage to the wirings during the process of expanding the display module.

[0047] Accordingly, a stretchable display module with high reliability can be provided. Brief explanation of the drawing

[0048] FIGS. 1 and FIGS. 2 are each display modules according to an embodiment of the present invention. FIGS. 3 and FIGS. 4 are each cross-sectional views of a display module according to an embodiment of the present invention. FIG. 5 illustrates a display panel according to one embodiment of the present invention. Figure 6 illustrates an exemplary equivalent circuit diagram corresponding to the pixels of Figure 5. FIG. 7 illustrates exemplary light emission control signals and scan signals applied to the pixels of FIG. 6. FIGS. 8 and FIGS. 9 each illustrate an exemplary part of a base member on which the pixels shown in FIGS. 6 are arranged. FIGS. 10a, FIGS. 10b, and FIGS. 10c each illustrate, exemplarily, wiring placed on any one of the unit parts shown in FIG. 8. FIGS. 11, FIGS. 12, and FIGS. 13 each illustrate an exemplary cross-section of a portion of a display panel according to an embodiment of the present invention. FIGS. 11, FIGS. 12, FIGS. 13a, and FIGS. 13b each illustrate an exemplary cross-section of a portion of a display panel according to an embodiment of the present invention. FIG. 14 illustrates an exemplary cross-section of a portion of a display panel according to one embodiment of the present invention. FIG. 15 illustrates an exemplary unit part according to one embodiment of the present invention. FIG. 16 illustrates, exemplarily, display modules according to one embodiment of the present invention being mounted inside an automobile. Specific details for implementing the invention

[0049] Hereinafter, embodiments of the present invention will be described with reference to the drawings.

[0050] In the drawings, the proportions and dimensions of the components are exaggerated for the effective illustration of the technical content. "And / or" includes all one or more combinations that the associated components may define.

[0051] Terms such as "include" are intended to indicate the existence of the features, numbers, steps, actions, components, parts, or combinations thereof described in the specification, and should be understood as not precluding the existence or addition of one or more other features, numbers, steps, actions, components, parts, or combinations thereof.

[0052] FIGS. 1 and FIGS. 2 are each a display module (DM) according to an embodiment of the present invention. The display module (DM) shown in FIGS. 1 is in a state before stretching (hereinafter, the first state). The display module (DM) shown in FIGS. 2 is in a state stretched in a predetermined direction by an externally applied force (hereinafter, the second state).

[0053] The display module (DM) may be intended to be mounted on large electronic devices such as televisions and monitors, as well as on small and medium-sized electronic devices such as mobile phones, tablets, car navigation systems, game consoles, or smartwatches.

[0054] A display module (DM) may define a display area (DA) and a non-display area (NDA).

[0055] The display area (DA) where the image (IM) is displayed is parallel to the plane defined by the first direction axis (DR1) and the second direction axis (DR2). The third direction axis (DR3) indicates a direction opposite to the first direction axis (DR1), and the fourth direction axis (DR4) indicates a direction opposite to the second direction axis (DR2).

[0056] The normal direction of the display area (DA), that is, the thickness direction of the display device (DD), is indicated by the fifth direction axis (DR5). The front (or top) and back (or bottom) surfaces of each member are distinguished by the fifth direction axis (DR5). However, the directions indicated by the first to fifth direction axes (DR1, DR2, DR3, DR4, DR5) are relative concepts and can be converted to other directions. Hereinafter, the first to fifth directions refer to the same reference numerals as the directions indicated by the first to fifth direction axes (DR1, DR2, DR3, DR4, DR5), respectively.

[0057] The shape of the display area (DA) shown in FIG. 1 is exemplary, and the shape of the display area (DA) can be changed without limitation as needed.

[0058] The non-display area (NDA) is an area adjacent to the display area (DA) where the image (IM) is not displayed. The bezel area of ​​the display device (DD) can be defined by the non-display area (NDA).

[0059] The non-display area (NDA) may surround the display area (DA). However, not limited thereto, the shape of the display area (DA) and the shape of the non-display area (NDA) may be designed relative to each other.

[0060] FIGS. 3 and FIGS. 4 are each cross-sectional views of a display module (DM, DM-1) according to an embodiment of the present invention.

[0061] Referring to FIG. 3, the display module (DM) may include a display panel (DP) and an input detection circuit (ISC). The input detection circuit (ISC) may detect touch and / or pressure applied from the outside.

[0062] The input sensing circuit (ISC) can be placed directly on a thin film encapsulation layer (not shown) of a display panel (DP). Here, "direct placement" means that the input sensing circuit (ISC) is placed on the display panel (DP) without a separate adhesive member.

[0063] Referring to FIG. 4, the display module (DM-1) may include a display panel (DP), an input detection circuit (ISC), and an adhesive member (AD). The display panel (DP) and the input detection circuit (ISC) may be bonded by the adhesive member (AD).

[0064] FIG. 5 illustrates a display panel (DP) according to one embodiment of the present invention.

[0065] The display panel (DP) includes a display area (DP-DA) and a non-display area (DP-NDA) on a plane. In this embodiment, the non-display area (DP-NDA) may be defined along the border of the display area (DP-DA). The display area (DP-DA) and the non-display area (DP-NDA) of the display panel (DP) may correspond, respectively, to the display area (DA) and the non-display area (NDA) of the display module (DM) shown in FIG. 1.

[0066] A display panel (DP) may include a scanning driver (100), a data driver (200), a plurality of scan lines (SL), a plurality of light emission control lines (ECL), a plurality of data lines (DL), a plurality of power lines (PL), and a plurality of pixels (PX, hereinafter pixels). The pixels (PX) are placed in a display area (DP-DA). Each of the pixels (PX) includes a light-emitting element (LD, see FIG. 6) and a pixel circuit (CC, see FIG. 6) connected thereto.

[0067] The injection drive unit (100) may include a scan drive unit and a light emission control drive unit.

[0068] The scan driver generates scan signals and sequentially outputs the generated scan signals to the scan lines (SL). The light emission control driver generates light emission control signals and outputs the generated light emission control signals to the light emission control lines (ECL).

[0069] In another embodiment of the present invention, the scan driving unit and the light emission control driving unit are not separated within the injection driving unit (100) and may be configured as a single circuit.

[0070] The scanning driving unit (100) may include a plurality of thin-film transistors formed through the same process as the driving circuit of the pixels (PX), such as the LTPS (Low Temperature Polycrystalline Silicon) process or the LTPO (Low Temperature Polycrystalline Oxide) process.

[0071] The data driving unit (200) outputs data signals to data lines (DL). The data signals are analog voltages corresponding to the grayscale values ​​of the image data.

[0072] In one embodiment of the present invention, the data driving unit (200) is mounted on a printed circuit board (FPCB), and the printed circuit board (FPCB) may be connected to pads disposed at one end of the data lines (DL). However, it is not limited thereto, and the data driving unit (200) may be directly mounted on a display panel (DP).

[0073] Scan lines (SL) can be extended in a first direction (DR1) and arranged in a second direction (DR2). Scan lines (SL) can provide scan signals to pixels (PX).

[0074] The light emission control lines (ECL) can be extended in a first direction (DR1) and arranged in a second direction (DR2). That is, each light emission control line (ECL) can be arranged parallel to a corresponding scan line among the scan lines (SL). The light emission control lines (ECL) can provide light emission control signals to the pixels (PX).

[0075] The data lines (DL) extend to the second direction (DR2) and are arranged in the first direction (DR1). The data lines (DL) can provide data signals to the corresponding pixels (PX).

[0076] The power lines (PL) extend in a second direction (DR2) and are arranged in a first direction (DR1). The power lines (PL) can provide a first power supply (ELVDD) to the corresponding pixels (PX).

[0077] Each of the multiple pixels (PX) is connected to a corresponding scan line among the scan lines (SL), a corresponding light emission control line among the light emission control lines (ECL), a corresponding data line among the data lines (DL), and a corresponding power line among the power lines (PL).

[0078] A second power supply (ELVSS) may be provided to the pixels (PX) of the display panel (DP).

[0079] FIG. 6 illustrates an equivalent circuit diagram of a pixel (PX) according to an embodiment of the present invention. FIG. 7 illustrates, exemplarily, a light emission control signal (Ei) and scan signals (Si-1, Si) applied to the pixel (PX) of FIG. 6. FIG. 6 exemplarily illustrates a pixel (PX) connected to the i-th scan line (SLi) and the i-th light emission control line (ECLi).

[0080] A pixel (PX) may include a light-emitting element (LD) and a pixel circuit (CC). The pixel circuit (CC) may include a plurality of transistors (T1 to T7) and a capacitor (CP). The pixel circuit (CC) controls the amount of current flowing to the light-emitting element (LD) in response to a data signal.

[0081] The light-emitting element (LD) can emit light with a predetermined brightness in response to the amount of current provided from the pixel circuit (CC). To this end, the potential of the first power source (ELVDD) can be set higher than the potential of the second power source (ELVSS).

[0082] A plurality of transistors (T1 to T7) may each include an input electrode (or source electrode), an output electrode (or drain electrode), and a control electrode (or gate electrode). For convenience within this specification, either the input electrode or the output electrode may be referred to as the first electrode, and the other as the second electrode.

[0083] The first electrode of the first transistor (T1) is connected to the first power supply (ELVDD) via the fifth transistor (T5), and the second electrode is connected to the anode electrode of the light-emitting element (LD) via the sixth transistor (T6). The first transistor (T1) may be referred to as a driving transistor within this specification.

[0084] The first transistor (T1) controls the amount of current flowing through the light-emitting element (LD) in response to the voltage applied to the control electrode.

[0085] The second transistor (T2) is connected between the data line (DL) and the first electrode of the first transistor (T1). The control electrode of the second transistor (T2) is connected to the i-th scan line (SLi). The second transistor (T2) is turned on when the i-th scan signal (Si) is provided to the i-th scan line (SLi), thereby electrically connecting the data line (DL) and the first electrode of the first transistor (T1).

[0086] The third transistor (T3) is connected between the second electrode and the control electrode of the first transistor (T1). The control electrode of the third transistor (T3) is connected to the i-th scan line (SLi). The third transistor (T3) is turned on when the i-th scan signal (Si) is provided to the i-th scan line (SLi), thereby electrically connecting the second electrode and the control electrode of the first transistor (T1). Thus, when the third transistor (T3) is turned on, the first transistor (T1) is connected in the form of a diode.

[0087] The fourth transistor (T4) is connected between the node (ND) and the initialization power generation unit (not shown). The control electrode of the fourth transistor (T4) is connected to the i-1th scan line (SLi-1). The fourth transistor (T4) is turned on when the i-1th scan signal (Si-1) is provided to the i-1th scan line (SLi-1) to provide an initialization voltage (Vint) to the node (ND).

[0088] The fifth transistor (T5) is connected between the power line (PL) and the first electrode of the first transistor (T1). The control electrode of the fifth transistor (T5) is connected to the i-th light emission control line (ECLi).

[0089] The sixth transistor (T6) is connected between the second electrode of the first transistor (T1) and the anode electrode of the light-emitting element (LD). Also, the control electrode of the sixth transistor (T6) is connected to the i-th light-emitting control line (ECLi).

[0090] The seventh transistor (T7) is connected between an initialization power generation unit (not shown) and the anode electrode of a light-emitting element (LD). The control electrode of the seventh transistor (T7) is connected to the i-th scan line (SLi). The seventh transistor (T7) is turned on when the i-th scan signal (Si) is provided to the i-th scan line (SLi), thereby providing an initialization voltage (Vint) to the anode electrode of the light-emitting element (LD).

[0091] The seventh transistor (T7) can improve the black expression capability of the pixel (PX). Specifically, when the seventh transistor (T7) is turned on, the parasitic capacitor (not shown) of the light-emitting element (LD) is discharged. Then, when black luminance is implemented, the light-emitting element (LD) does not emit light due to leakage current from the first transistor (T1), and accordingly, the black expression capability can be improved.

[0092] Additionally, although FIG. 6 is illustrated as the control electrode of the seventh transistor (T7) being connected to the i-th scan line (SLi), the present invention is not limited thereto. In another embodiment of the present invention, the control electrode of the seventh transistor (T7) may be connected to the i-1-th scan line (SLi-1) or the i+1-th scan line (SLi+1).

[0093] Figure 6 illustrates a PMOS, but is not limited thereto. In another embodiment of the present invention, the pixel (PX) may be composed of an NMOS. In yet another embodiment of the present invention, the pixel (PX) may be composed of a combination of an NMOS and a PMOS.

[0094] A capacitor (CP) is placed between the power line (PL) and the node (ND). The capacitor (CP) stores a voltage corresponding to the data signal. Depending on the voltage stored in the capacitor (CP), the amount of current flowing through the first transistor (T1) when the fifth transistor (T5) and the sixth transistor (T6) are turned on can be determined.

[0095] In the present invention, the structure of the pixel (PX) is not limited to the structure shown in FIG. 6. In other embodiments of the present invention, the pixel (PX) can be implemented in various forms to emit light from a light-emitting element (LD).

[0096] In one embodiment of the present invention, the light-emitting element (LD) may be an organic light-emitting element, a micro LED, or a light-emitting element using quantum dots.

[0097] Referring to FIG. 7, the light emission control signal (Ei) may have a high level (E-HIGH) or a low level (E-LOW). The scan signals (SLi-1, SLi) may each have a high level (S-HIGH) or a low level (S-LOW).

[0098] When the light emission control signal (Ei) has a high level (E-HIGH), the fifth transistor (T5) and the sixth transistor (T6) are turned off. When the fifth transistor (T5) is turned off, the power line (PL) and the first electrode of the first transistor (T1) are electrically cut off. When the sixth transistor (T6) is turned off, the second electrode of the first transistor (T1) and the anode electrode of the light-emitting element (LD) are electrically cut off. Therefore, the light-emitting element (LD) does not emit light during the period when the light emission control signal (Ei) having a high level (E-HIGH) is provided to the i-th light emission control line (ECLi).

[0099] Subsequently, when the i-1th scan signal (Si-1) provided to the i-1th scan line (SLi-1) has a low level (S-LOW), the fourth transistor (T4) is turned on. When the fourth transistor (T4) is turned on, an initialization voltage (Vint) is provided to the node (ND).

[0100] When the i-th scan signal (Si) provided to the i-th scan line (SLi) has a low level (S-LOW), the second transistor (T2), the third transistor (T3), and the seventh transistor (T7) are turned on.

[0101] When the second transistor (T2) is turned on, a data signal is provided to the first electrode of the first transistor (T1). At this time, the first transistor (T1) is turned on because the node (ND) is initialized to the initialization voltage (Vint). When the first transistor (T1) is turned on, a voltage corresponding to the data signal is provided to the node (ND). At this time, the capacitor (CP) stores the voltage corresponding to the data signal.

[0102] When the seventh transistor (T7) is turned on, an initialization voltage (Vint) is provided to the anode electrode of the light-emitting element (LD), and the parasitic capacitor of the light-emitting element (LD) is discharged.

[0103] When the light emission control signal (Ei) provided to the light emission control line (ECLi) has a low level (E-LOW), the fifth transistor (T5) and the sixth transistor (T6) are turned on. When the fifth transistor (T5) is turned on, the first power supply (ELVDD) is supplied to the first electrode of the first transistor (T1). When the sixth transistor (T6) is turned on, the second electrode of the first transistor (T1) and the anode electrode of the light-emitting element (LD) are electrically connected. Then, the light-emitting element (LD) generates light of a predetermined brightness corresponding to the amount of current supplied.

[0104] FIGS. 8 and FIGS. 9 each illustrate an exemplary portion of a base member (BL) on which pixels (PX) shown in FIGS. 6 are arranged. Specifically, FIGS. 8 illustrates an exemplary shape of the base member (BL) when the display module (DM) is in a first state as shown in FIGS. 1. FIGS. 9 illustrates an exemplary shape of the base member (BL) when the display module (DM) is in a second state as shown in FIGS. 2.

[0105] The base member (BL) may include a synthetic resin. For example, the base member (BL) may include polyimide (PI).

[0106] The base member (BL) may include a plurality of unit parts (UNP1, UNP2, UNP3, UNP4). Although four unit parts are illustrated as examples in FIG. 8, this only illustrates a part of the base member (BL), and the base member (BL) may include a larger number of unit parts. In this specification, the reference numeral for designating any one of the unit parts (UNP1, UNP2, UNP3, UNP4) may be designated as UNP.

[0107] Each of the unit parts (UNP1, UNP2, UNP3, UNP4) may include an island part (IA) and a plurality of hinge parts (HA). Although FIG. 8 exemplarily illustrates one unit part (UNP) including one island part (IA) and four hinge parts (HA), the number of island parts (IA) and hinge parts (HA) may be changed as needed.

[0108] The island portion (IA) may be positioned in the center of the unit portion (UNP). Each of the hinge portions (HA) may extend from the island portion (IA). The hinge portions (HA) may be spaced apart from each other and may extend in different directions. FIG. 8 illustrates, by way of example, that each of the hinge portions (HA) extends in any one of the first to fourth directions (DR1 to DR4), but is not limited thereto. The extension of each of the hinge portions (HA) may be changed as needed.

[0109] The unit parts (UNP1, UNP2, UNP3, UNP4) can be connected to each other by hinge parts (HA).

[0110] Referring to FIGS. 8 and 9, when the display module (DM) changes from a first state to a second state, the distance (LL) between the hinge portion (HA) of one unit part (UNP) and the hinge portion (HA) of another unit part (UNP) adjacent to the one unit part (UNP) can be increased.

[0111] In one embodiment of the present invention, when the display module (DM) changes from a first state to a second state, the angle formed by the corner of the island portion (IA) with the first direction (DR1) may change.

[0112] In one embodiment of the present invention, when the display module (DM) changes from a first state to a second state, the angle formed by at least one of the island portion (IA) and the hinge portions (HA) may be changed.

[0113] In this way, a stretchable display module (DM) that can be easily changed from a first state to a second state can be implemented as at least one of the spacing (LL) between the hinge parts (HA), the angle formed by the corner of the island part (IA) with the first direction (DR1), and the angle formed by the island part (IA) and the hinge part (HA) changes.

[0114] FIGS. 10a, FIGS. 10b, and FIGS. 10c each illustrate, exemplarily, wiring (LN1, LN2, LN3) placed on the second unit part (UNP2) among the unit parts (UNP1, UNP2, UNP3, UNP4) shown in FIGS. 8.

[0115] Specifically, FIG. 10a illustrates first wiring (LN1) placed in a first layer, FIG. 10b illustrates second wiring (LN2) placed in a second layer, and FIG. 10c illustrates third wiring (LN3) placed in a third layer. That is, the first to third wirings (LN11, LN2, LN3) can be placed in different layers.

[0116] A pixel region (PXA) may be defined in the island portion (IA). The pixel region (PXA) is an area where transistors, capacitors, and light-emitting elements are arranged to implement a plurality of pixels (PX, see FIG. 6).

[0117] A pixel area (PXA) may include a first pixel area (PXA1), a second pixel area (PXA2), and a third pixel area (PXA3). The second pixel area (PXA2) may be positioned adjacent to the first pixel area (PXA1), and the third pixel area (PXA3) may be positioned adjacent to the second pixel area (PXA2). The second pixel area (PXA2) may be positioned between the first pixel area (PXA1) and the third pixel area (PXA3).

[0118] In the first pixel area (PXA1), transistors, a capacitor, and a light-emitting element for emitting light having a first color may be disposed. In one embodiment of the present invention, the first color may be red, but is not limited thereto.

[0119] In the second pixel area (PXA2), transistors, capacitors, and light-emitting elements for emitting light having a second color may be disposed. In one embodiment of the present invention, the second color may be blue, but is not limited thereto.

[0120] In the third pixel area (PXA3), transistors, capacitors, and light-emitting elements for emitting light having a third color may be disposed. In one embodiment of the present invention, the third color may be green, but is not limited thereto.

[0121] The length of the first pixel region (PXA1) measured in one direction (LP1, hereinafter the first length), the length of the second pixel region (PXA2) measured in the same direction (LP2, hereinafter the second length), and the length of the third pixel region (PXA3) measured in the same direction (LP3, hereinafter the third length) can each be determined according to the anode electrode (AE, see FIG. 11) of the corresponding light-emitting element (LD). That is, if the length of the anode electrode (AE, see FIG. 11) of the light-emitting element (LD) is long, the length of the corresponding pixel region among the first to third pixel regions (PXA1, PXA2, PXA3) is long, and if the length of the anode electrode (AE, see FIG. 11) is short, the length of the corresponding pixel region among the first to third pixel regions (PXA1, PXA2, PXA3) is short.

[0122] Referring to FIGS. 10a to 10c, the second length (LP2) may be longer than the first length (LP1) and the third length (LP3). That is, the length of the anode electrode (AE, see FIG. 11) of the light-emitting element (LD) placed in the second pixel area (PXA2) may be longer than the length of the anode electrode (AE, see FIG. 11) of the light-emitting element (LD) placed in the first pixel area (PXA1) or the third pixel area (PXA3). This is to balance the visibility between colors by increasing the area where the blue color is emitted, because the blue color emitted from the second pixel area (PXA2) has lower visibility than the red color emitted from the first pixel area (PXA1) and the green color emitted from the third pixel area (PXA3).

[0123] The hinge portions (HA) may include a first hinge portion (HA1) extending in a first direction (DR1) from the island portion (IA), a second hinge portion (HA2) extending in a second direction (DR2) from the island portion (IA), a third hinge portion (HA3) extending in a third direction (DR3) from the island portion (IA), and a fourth hinge portion (HA4) extending in a fourth direction (DR4) from the island portion (IA).

[0124] Referring to FIG. 10a, first wiring (LN1) electrically connected to transistors of a pixel area (PXA) may be disposed on the upper portion of each of the hinge portions (HA1~HA2).

[0125] Referring to FIGS. 5 and 6, the first wiring (LN1) may include data lines (DL), scan lines (SLi-1, SLi), and light emission control lines (ECLi).

[0126] Data lines (DL) may be placed on at least one of the first hinge portion (HA1) and the third hinge portion (HA3). The data lines (DL) may provide data signals to transistors placed on the first to third pixel regions (PXA1 to PXA3), respectively.

[0127] Scan lines (SLi-1, SLi) and light emission control line (ECLi) can be placed on at least one of the second hinge portion (HA2) and the fourth hinge portion (HA4).

[0128] Referring to FIG. 10b, second wiring (LN2) electrically connected to transistors or capacitors of a pixel area (PXA) may be disposed on the upper portion of each of the hinge portions (HA1~HA4).

[0129] Referring to FIGS. 5 and 6, the second wiring (LN2) may include a first power line (PL1) and a second power line (PL2).

[0130] The first power line (PL1) is positioned on at least one of the first hinge portion (HA1) and the third hinge portion (HA3) and can be electrically connected to the fifth transistor (T5) of the pixel (PX). The second power line (PL2) is positioned on at least one of the second hinge portion (HA2) and the fourth hinge portion (HA4) and can be electrically connected to the capacitor (CP) of the pixel (PX).

[0131] In one embodiment of the present invention, the first power line (PL1) may be divided into a branch line (BR), a first supply line (PL11), a second supply line (PL12), and a third supply line (PL13) in the pixel area (PXA). The first supply line (PL11) may provide a first power supply (ELVDD) to the first pixel area (PXA1), the second supply line (PL12) may provide a first power supply (ELVDD) to the second pixel area (PXA2), and the third supply line (PL13) may provide a first power supply (ELVDD) to the third pixel area (PXA3). According to an embodiment, the second power line (PL2) may supply a first power supply (ELVDD) to the pixel areas (PXA1, PXA2, PXA3) in a direction different from the first to third supply lines (PL11, PL12, PL13). In this case, each pixel area (PXA1, PXA2, PXA3) can receive a first power supply (ELVDD) in the form of a mesh.

[0132] In FIG. 10b, the branch line (BR) is exemplarily shown being placed on the same layer as the supply lines (PL11, PL12, PL13), but is not limited thereto. In another embodiment of the present invention, the branch line (BR) may be placed on a different layer from the supply lines (PL11, PL12, PL13).

[0133] In one embodiment of the present invention, the first power supply (ELVDD) provided to the pixel (PX) by the first power line (PL1) and the second power line (PL2) may have a potential of about 4.5V or higher and 5.5V or lower, but is not limited thereto.

[0134] Referring to FIG. 10c, third wiring (LN3) electrically connected to transistors of a pixel area (PXA) may be disposed on the upper portion of each of the hinge portions (HA).

[0135] Referring to FIGS. 5 and 6, the third wiring (LN3) may include a third power line (PL3) and an initialization power line (VL). The third power line (PL3) is positioned on at least one of the first hinge portion (HA1) and the third hinge portion (HA3) and may be electrically connected to the cathode electrode (CE, see FIG. 11) of the light-emitting element (LD). The initialization power line (VL) is positioned on at least one of the second hinge portion (HA2) and the fourth hinge portion (HA4) and may be electrically connected to the fourth transistor (T4) and the seventh transistor (T7) of the pixel (PX).

[0136] In one embodiment of the present invention, the second power supply (ELVSS) provided by the third power line (PL3) to the pixel (PX) may have a potential of approximately -5.5V or higher and -4.5V or lower, but is not limited thereto.

[0137] In one embodiment of the present invention, the initialization power line (VL) may provide an electrical signal to the pixel (PX) having a potential of approximately -4.5V or higher and -3.5V or lower, but is not limited thereto.

[0138] The initial power line (VL) provides an electrical signal to the pixel (PX) having a potential similar to that of the third power line (PL3) compared to other wires. Therefore, electrical stability can be improved by placing the initial power line (VL) and the third power line (PL3), which provide electrical signals with similar potentials, on the same layer.

[0139] The second wiring (LN2) includes the first power line (PL1) and the second power line (PL2), thereby providing the first power (ELVDD) required for the light-emitting element (LD) to emit light to the pixel (PX). Accordingly, it is desirable that the electrical signal transmission power of the second wiring (LN2) be greater than the electrical signal transmission power of the first wiring (LN1) or the third wiring (LN3). Accordingly, on a plane defined by the first direction (DR1) and the second direction (DR2), the second wiring (LN2) placed at the hinge portions (HA) may have a greater width than the first wiring (LN1) and the third wiring (LN3).

[0140] FIGS. 11, FIGS. 12, FIGS. 13a, and FIGS. 13b each illustrate an exemplary cross-section of a portion of a display panel (DP) according to an embodiment of the present invention.

[0141] FIG. 11 illustrates an exemplary cross-section corresponding to a part of the island portion (IA) and a part of the hinge portion (HA) of the display panel (DP).

[0142] The display panel (DP) may include a base member (BL), a circuit layer (CL), a light-emitting element layer (ELL), and an encapsulation layer (ECP).

[0143] The circuit layer (CL) can be placed on the base member (BL).

[0144] The circuit layer (CL) may include an activation pattern (ACL), metal patterns (GMP, MP1, MP2, MP3), wiring (LN1, LN2, LN3), a buffer layer (BFL), a gate insulating layer (GI, or a gate insulating member), interlayer insulating layers (ILD1, ILD2, or interlayer insulating members), passivation layers (PVX1, PVX2, or passivation members), and circuit insulating layers (VIA1, VIA2, VIA3, VIA4, or circuit insulating members). Each of the circuit insulating layers (VIA1, VIA2, VIA3, VIA4) may include an organic or inorganic material.

[0145] The buffer layer (BFL) may be placed on the base member (BL). The buffer layer (BFL) may be placed overlappingly on the island portion (IA).

[0146] The buffer layer (BFL) prevents impurities present in the base material (BL) from entering the pixel (PX) during the manufacturing process. In particular, it prevents impurities from spreading to the activation patterns (ACL) of the transistors (T1~T7) constituting the pixel (PX).

[0147] Impurities may be introduced from the outside or generated by the thermal decomposition of the base member (BL). The impurities may be gases or sodium emitted from the base member (BL). Additionally, the buffer layer (BFL) can block moisture from entering the pixel (PX) from the outside.

[0148] An activation pattern (ACL) can be placed on a buffer layer (BFL). The activation pattern (ACL) can constitute each of the transistors (T1 to T7). The activation pattern (ACL) may include polysilicon, amorphous silicon, or a metal oxide semiconductor.

[0149] The activation pattern (ACL) may include a channel region that serves as a passage for electrons or holes to move, a first ion-doping region and a second ion-doping region positioned between the channel region.

[0150] A gate insulating layer (GI) is disposed on a buffer layer (BFL) and covers an activation pattern (ACL). The gate insulating layer (GI) comprises an organic film and / or an inorganic film. In one embodiment of the present invention, the gate insulating layer (GI) may comprise a plurality of inorganic thin films. The plurality of inorganic thin films may comprise a silicon nitride layer and a silicon oxide layer.

[0151] A gate metal pattern (GMP) may be disposed on a gate insulating layer (GI). The gate metal pattern (GMP) may constitute control electrodes of transistors (T1 to T7). In one embodiment of the present invention, the gate metal pattern (GMP) may be either of two electrodes constituting a capacitor (CP) of a pixel (PX).

[0152] In one embodiment of the present invention, the gate metal pattern (GMP) may include molybdenum (Mo), but is not limited thereto.

[0153] The first interlayer insulating layer (ILD1) can be placed on the gate metal pattern (GMP). The first interlayer insulating layer (ILD1) can be superimposed on the island portion (IA).

[0154] The second interlayer insulating layer (ILD2) may be disposed on the first interlayer insulating layer (ILD1). The second interlayer insulating layer (ILD2) may be superimposed on the gate metal pattern (GMP).

[0155] The first interlayer insulating layer (ILD1) and the second interlayer insulating layer (ILD2) may include an organic film and / or an inorganic film. The first interlayer insulating layer (ILD1) and the second interlayer insulating layer (ILD2) may include a plurality of inorganic thin films. The plurality of inorganic thin films may include a silicon nitride layer and a silicon oxide layer.

[0156] The first circuit insulating layer (VIA1) may be disposed on at least a portion of the first interlayer insulating layer (ILD1) and at least a portion of the second interlayer insulating layer (ILD2). The first circuit insulating layer (VIA1) may expose a portion of the second interlayer insulating layer (ILD2). The first circuit insulating layer (VIA1) may overlap at least a portion of the island portion (IA) and at least a portion of the hinge portion (HA).

[0157] First contact holes (CH1) can be defined in the first circuit insulation layer (VIA1).

[0158] A first metal pattern (MP1) may be disposed on the second interlayer insulation layer (ILD2) or the first circuit insulation layer (VIA1). The first metal pattern (MP1) may be superimposed on the island portion (IA).

[0159] The first metal pattern (MP1) can form the input electrodes and output electrodes of the transistors (T1 to T7).

[0160] The first metal pattern (MP1) can form the other electrode among the two electrodes constituting the capacitor (CP, see FIG. 6). That is, a part of the gate metal pattern (GMP) and a part of the first metal pattern (MP1) can overlap to form the capacitor (CP) shown in FIG. 6. However, the structure in which the electrodes constituting the capacitor (CP) are arranged is not limited to this.

[0161] The first wiring (LN1) can be placed on the first circuit insulating layer (VIA1). The first wiring (LN1) can be electrically connected to the gate metal pattern (GMP) through the first contact hole (CH1) of the first circuit insulating layer (VIA1).

[0162] The first metal pattern (MP1) and the first wiring (LN1) may include at least one of aluminum (Al) and titanium (Ti), but are not limited thereto. In one embodiment of the present invention, the first metal pattern (MP1) or the first wiring (LN1) may have a structure in which titanium, aluminum, and titanium are stacked in order.

[0163] Generally, the elongation of aluminum and titanium is greater than that of molybdenum. In other words, the flexibility of aluminum and titanium is greater than that of molybdenum.

[0164] The first metal material included in the gate metal pattern (GMP) or the second metal material included in each of the first metal pattern (MP1) and the first wiring (LN1) is not particularly limited, and it is sufficient if the elongation of the second metal material is greater than the elongation of the first metal material.

[0165] In one embodiment of the present invention, a first wiring (LN1) comprising a metal material having a greater elongation than the gate metal pattern (GMP) is used to provide an electrical signal to the gate metal pattern (GMP). Accordingly, even if stress is applied to the hinge portion (HA) during the process of changing the display module (DM) from a first state to a second state, an electrical signal can be stably provided to the gate metal pattern (GMP).

[0166] The first passivation layer (PVX1) is disposed on the second interlayer insulation layer (ILD2) and can cover the first metal pattern (MP1). The first passivation layer (PVX1) may include organic and / or inorganic materials.

[0167] The second circuit insulating layer (VIA2) is disposed on the first circuit insulating layer (VIA1) and can cover the first metal pattern (MP1), the first wiring (LN1), and the first passivation layer (PVX1).

[0168] Second contact holes (CH2) can be defined in the second circuit insulation layer (VIA2).

[0169] The second metal pattern (MP2) can be placed on the second circuit insulating layer (VIA2). The second metal pattern (MP2) can be superimposed on the island portion (IA).

[0170] The second wiring (LN2) can be placed on the second circuit insulation layer (VIA2). The second wiring (LN2) can be superimposed on the hinge portion (HA).

[0171] The second metal pattern (MP2) is electrically connected to the first metal pattern (MP1) through one of the second contact holes (CH2) of the second circuit insulating layer (VIA2), and the second wiring (LN2) can be electrically connected to the first metal pattern (MP1) through the other of the second contact holes (CH2) of the second circuit insulating layer (VIA2).

[0172] The second metal pattern (MP2) and the second wiring (LN2) may include at least one of aluminum (Al) and titanium (Ti), but are not limited thereto. In one embodiment of the present invention, the second metal pattern (MP2) or the second wiring (LN2) may have a structure in which titanium, aluminum, and titanium are stacked in sequence.

[0173] The third circuit insulating layer (VIA3) is placed on the second circuit insulating layer (VIA2) and can cover the second metal pattern (MP2) and the second wiring (LN2).

[0174] A third contact hole (CH3) can be defined in the third circuit insulation layer (VIA3).

[0175] The third metal pattern (MP3) can be placed on the third circuit insulating layer (VIA3). The third metal pattern (MP3) can be superimposed on the island portion (IA).

[0176] The third wiring (LN3) can be placed on the third circuit insulation layer (VIA3). The third wiring (LN3) can be superimposed on the hinge portion (HA).

[0177] The third metal pattern (MP3) can be electrically connected to the second metal pattern (MP2) through the third contact hole (CH3) of the third circuit insulating layer (VIA3).

[0178] The third metal pattern (MP3) and the third wiring (LN3) may include at least one of aluminum (Al) and titanium (Ti), but are not limited thereto. In one embodiment of the present invention, the third metal pattern (MP3) or the third wiring (LN3) may have a structure in which titanium, aluminum, and titanium are stacked in sequence.

[0179] The fourth circuit insulating layer (VIA4) is placed on the third circuit insulating layer (VIA3) and can cover the third metal pattern (MP3) and the third wiring (LN3).

[0180] Fourth contact holes (CH4) can be defined in the fourth circuit insulation layer (VIA4).

[0181] In one embodiment of the present invention, the fourth circuit insulating layer (VIA4) may be black. As the fourth circuit insulating layer (VIA4), which constitutes the uppermost layer of the circuit layer (CL), is black, the components below the fourth circuit insulating layer (VIA4) may not be visible to the user of the display module (DM). Accordingly, the aesthetic appeal and premium feel of the display module (DM) may be enhanced.

[0182] The second passivation layer (PVX2) can be placed on the fourth circuit insulation layer (VIA4).

[0183] The light-emitting element layer (ELL) may include a light-emitting element (LD) and a pixel defining layer (PDL). The light-emitting element (LD) may include an anode electrode (AE), a light-emitting layer (EML), and a cathode electrode (CE).

[0184] The anode electrode (AE) can be placed on the second passivation layer (PVX2). The anode electrode (AE) can be electrically connected to the third metal pattern (MP3) through the fourth contact hole (CH4) of the fourth circuit insulation layer (VIA4). The anode electrode (AE) can receive the first power supply (ELVDD) provided from the second wiring (LN2) through the first to third metal patterns (MP1, MP2, MP3).

[0185] The pixel defining layer (PDL) is disposed on the second passivation layer (PVX2) and can expose at least a portion of the anode electrode (AE).

[0186] The light-emitting layer (EML) can be placed on the anode electrode (AE).

[0187] When the light-emitting element (LD) is an organic light-emitting diode (OLED), the light-emitting layer (EML) may include an organic material. In another embodiment of the present invention, when the light-emitting element (LD) is a micro LED, the light-emitting layer (EML) may include an inorganic material.

[0188] The cathode electrode (CE) can be placed on the light-emitting layer (EML). The cathode electrode (CE) can be electrically connected to the third metal pattern (MP3) through the fourth contact hole (CH4) of the fourth circuit insulating layer (VIA4). The cathode electrode (CE) can receive the second power supply (ELVSS) provided from the third wiring (LN3) through the third metal pattern (MP3).

[0189] The encapsulation layer (ECP) can seal the light-emitting element layer (ELL) to protect the light-emitting element layer (ELL) from external oxygen or moisture. The encapsulation layer (ECP) may be a layer in which organic and inorganic films are mixed.

[0190] FIG. 12 illustrates, by way of example, a portion of the cross-section of a display panel (DP) corresponding to the first hinge portion (HA1) or the third hinge portion (HA3) in FIG. 10a to 10c.

[0191] Data lines (DL) may be placed on the first circuit insulation layer (VIA1), the first power line (PL1) may be placed on the second circuit insulation layer (VIA2), and the third power line (PL3) may be placed on the third circuit insulation layer (VIA3).

[0192] The first power line (PL1) may overlap with a plurality of data lines (DL). FIG. 12 illustrates, by way of example, that the first power line (PL1) overlaps with three data lines (DL). In another embodiment of the present invention, the first power line (PL1) may overlap with two data lines (DL).

[0193] The third power line (PL3) overlaps with the second power line (PL2) and can also overlap with at least one of the data lines (DL).

[0194] FIGS. 13a and FIGS. 13b each illustrate, exemplarily, a portion of the cross-section of a display panel (DP) corresponding to the second hinge portion (HA2) or the fourth hinge portion (HA4) in FIGS. 10a to 10c.

[0195] Referring to FIG. 13a, scan lines (SLi, SLi-1) and light emission control lines (ECL) may be placed on a first circuit insulating layer (VIA1), a second power line (PL2) may be placed on a second circuit insulating layer (VIA2), and an initialization power line (VL) may be placed on a third circuit insulating layer (VIA3).

[0196] The second power line (PL2) may overlap with the scan lines (SLi, SLi-1) and the light emission control line (ECL). FIG. 13a illustrates, by way of example, that the second power line (PL2) overlaps with both the scan lines (SLi, SLi-1) and the light emission control line (ECL). In another embodiment of the present invention, the second power line (PL2) may overlap only with the scan lines (SLi, SLi-1), or only with one of the scan lines (SLi, SLi-1) and the light emission control line (ECL).

[0197] The initialization power line (VL) overlaps with the second power line (PL2) and can overlap with at least one of the scan lines (SLi, SLi-1) and the light emission control line (ECL).

[0198] Referring to FIG. 13b, two initialization power lines (VL-1) may be placed on the third circuit insulation layer (VIA3). One of the initialization power lines (VL-1) may be connected to the fourth transistor (T4, see FIG. 6), and the other may be connected to the seventh transistor (T7, see FIG. 6). Otherwise, the description of FIG. 13b is substantially the same as the description of FIG. 13a and is therefore omitted.

[0199] FIG. 14 illustrates an exemplary cross-section of a portion of a display panel (DP) according to one embodiment of the present invention.

[0200] Referring to FIG. 14, the display panel (DP) may further include a protection member (CPL) disposed between the buffer layer (BFL) and the base member (BL). The protection member (CPL) may overlap with an activation pattern (ACL).

[0201] The protective member (CPL) may be electrically connected to the gate metal pattern (GMP) through a contact hole (CH0) defined in the gate insulating layer (GI) and the buffer layer (BFL). However, the protective member (CPL) may be electrically connected to any one of the first to third metal patterns (MP1, MP2, MP3) or may be in a floating state, provided that it is not limited to these.

[0202] FIG. 15 illustrates, by way of example, one unit part (UNP2-1) according to one embodiment of the present invention. Specifically, FIG. 15 is a second unit part (UNP2-1) that is a modified version of the second unit part (UNP2) illustrated in FIG. 8. In FIG. 15, the wiring (LN1, LN2, LN3) is not illustrated for convenience.

[0203] A pixel area (PXA-1) is placed in an island portion (IA) and may include a first pixel area (PXA1-1), a second pixel area (PXA2-1), and a third pixel area (PXA3-1).

[0204] The second pixel area (PXA2-1) may be arranged adjacent to the first pixel area (PXA1-1) and the third pixel area (PXA3-1).

[0205] Since the second pixel area (PXA2-1) is an area that emits light with a blue color with low visibility, it may have a larger area than the first pixel area (PXA1-1) that emits light with a red color and the third pixel area (PXA3-1) that emits light with a green color. Accordingly, the second length (LP2) measured in one direction of the second pixel area (PXA2-1) may be longer than the first length (LP1) measured in one direction of the first pixel area (PXA1-1) and the third length (LP3) measured in one direction of the third pixel area (PXA3-1).

[0206] FIG. 16 illustrates, by way of example, display modules (DM) according to one embodiment of the present invention being mounted inside an automobile. The display modules (DM) may be mounted on a center fascia, steering wheel, or instrument panel inside the automobile.

[0207] A display module (DM) according to one embodiment of the present invention can be easily mounted on curved parts, such as the interior of a car, because it can be stretched well by an applied force.

[0208] Although the invention has been described with reference to exemplary embodiments, those skilled in the art will understand that various modifications and changes can be made to the invention without departing from the spirit and scope of the invention as set forth in the following claims. Furthermore, the exemplary embodiments disclosed in the invention are not intended to limit the technical spirit of the invention, and all technical spirits within the scope of the following claims and their equivalents should be interpreted as being included within the scope of the rights of the invention. Explanation of the symbols

[0209] DM: Display module DP: Display panel ISC: Input sensing element PX: Pixel BL: Absence of base IA: Island part HA: Hinge part GMP: Gate metal pattern MP1~MP3: Metal patterns LN1~LN3: Wiring

Claims

Claim 1 A base member comprising a plurality of unit portions, each of which comprises a first portion and a plurality of second portions extending from the first portion and connecting adjacent first portions; a pixel disposed on the first portion; a gate metal pattern superimposed on the first portion and not extending over the plurality of second portions; a first circuit insulating member disposed on the base member and covering the gate metal pattern, superimposed on the first portion and the plurality of second portions, and having a first contact hole defined therein; a plurality of first wires disposed on the first circuit insulating member, each superimposed on at least one of the plurality of second portions, and at least one of which is electrically connected to the gate metal pattern through the first contact hole; a second circuit insulating member disposed on the plurality of first wires; a plurality of second wires disposed on the second circuit insulating member, each superimposed on at least one of the plurality of second portions; and a third circuit insulating member disposed on the plurality of second wires. A display module comprising a plurality of third wires disposed on the third circuit insulating member, each of which overlaps at least one of the plurality of second parts, wherein the plurality of first wires include data lines and scan lines electrically connected to the pixel, and the plurality of second wires include power lines supplying power to the pixel, and wherein, on a plane, the width of each of the plurality of second wires is greater than the width of each of the plurality of first wires. Claim 2 In claim 1, a display module in which at least one of the plurality of second parts, at least one of the plurality of first wires, at least one of the plurality of second wires, and any one of the plurality of third wires overlap each other. Claim 3 A display module according to claim 2, wherein, on a plane, the width of each of the plurality of second wires is greater than the width of each of the plurality of third wires, and on a plane, the width of each of the plurality of third wires is greater than the width of each of the plurality of first wires. Claim 4 In claim 1, a display module in which at least one of the plurality of second wires overlaps with at least two of the plurality of first wires. Claim 5 A display module according to claim 1, wherein the gate metal pattern comprises a first metal material, and each of the plurality of first wires, the plurality of second wires, and the plurality of third wires comprises a second metal material different from the first metal material. Claim 6 In claim 5, the first metal material has a first elongation, and the second metal material has a second elongation greater than the first elongation, in a display module. Claim 7 A display module according to claim 1, further comprising: a first metal pattern disposed on the first circuit insulating member and overlapping the first portion; a second metal pattern disposed on the second circuit insulating member and overlapping the first portion; and a third metal pattern disposed on the third circuit insulating member and overlapping the first portion. Claim 8 A display module according to claim 7, wherein a plurality of second contact holes are defined in the second circuit insulating member, the second metal pattern is electrically connected to the first metal pattern through any one of the plurality of second contact holes, and at least one of the plurality of second wirings is electrically connected to the first metal pattern through another of the plurality of second contact holes. Claim 9 In claim 8, a third contact hole is defined in the third circuit insulating member, and the third metal pattern is electrically connected to the second metal pattern through the third contact hole in the display module. Claim 10 A display module according to claim 7, further comprising: a fourth circuit insulating member disposed on the third metal pattern and the plurality of third wirings; an anode electrode disposed on the fourth circuit insulating member; a light-emitting layer disposed on the anode electrode; and a cathode electrode disposed on the light-emitting layer. Claim 11 In claim 10, a fourth contact hole is defined in the fourth circuit insulating member, and the anode electrode is electrically connected to the third metal pattern through the fourth contact hole in the display module. Claim 12 In claim 10, the fourth circuit insulating member is a black display module. Claim 13 A display module according to claim 1, further comprising a scanning driving unit; and a data driving unit, wherein the plurality of first wires include at least a portion of a data line receiving a data signal from the data driving unit, at least a portion of a scan line receiving a scan signal from the scanning driving unit, and at least a portion of a light emission control line receiving a light emission control signal from the scanning driving unit. Claim 14 In claim 13, the pixel comprises a plurality of transistors and a capacitor disposed on the first portion, and the plurality of second wires comprise at least a portion of a first power line providing a first potential to any one of the plurality of transistors and at least a portion of a second power line providing the first potential to the capacitor. Claim 15 A display module according to claim 14, further comprising a fourth circuit insulating member disposed on the plurality of third wires, wherein the pixel further comprises an anode electrode disposed on the fourth circuit insulating member; a light-emitting layer disposed on the anode electrode; and a cathode electrode disposed on the light-emitting layer, wherein the plurality of third wires comprises at least a portion of a third power line providing a second potential different from the first potential to the cathode electrode and at least a portion of an initialization power line providing an initialization potential to any one of the plurality of transistors. Claim 16 In claim 14, the plurality of second parts include a first hinge part extending in a first direction, a second hinge part extending in a second direction intersecting the first direction, a third hinge part extending in a third direction opposite to the first direction, and a fourth hinge part extending in a fourth direction opposite to the second direction, wherein the first power line is disposed on the first hinge part or the third hinge part, and the second power line is disposed on the second hinge part or the fourth hinge part, a display module. Claim 17 A display module comprising a plurality of unit parts, wherein each of the plurality of unit parts comprises a base member including a first part and a plurality of second parts extending from the first part; a pixel including a plurality of transistors and a capacitor disposed on the first part; a plurality of first wires disposed on the plurality of second parts; a plurality of second wires overlapping a corresponding first wire among the plurality of first wires; and a plurality of third wires overlapping a corresponding first wire among the plurality of first wires and a corresponding second wire among the plurality of second wires, wherein the plurality of first wires include a data line and a scan line electrically connected to the pixel, and the plurality of second wires include a power line supplying power to the pixel, and wherein, on a plane, the width of each of the plurality of second wires is greater than the width of each of the plurality of first wires. Claim 18 In claim 17, each of the plurality of second wires overlaps with at least two adjacent first wires among the plurality of first wires, and in a plane, the width of each of the second wires is greater than the width of each of the plurality of third wires. Claim 19 In claim 17, each of the plurality of transistors comprises an input electrode, an output electrode, and a control electrode, wherein the control electrode comprises a first metal material, and each of the output electrode, the input electrode, the plurality of first wires, the plurality of second wires, and the plurality of third wires comprises a second metal material different from the first metal material. Claim 20 A display module comprising: a plurality of first parts spaced apart from each other; a plurality of second parts, each extending from one of the plurality of first parts and connecting two adjacent first parts among the plurality of first parts; and a plurality of pixels disposed on the plurality of first parts, wherein each of the plurality of second parts comprises: a first layer having at least two lines among a plurality of data lines, a plurality of scan lines, and a light emission control line; a second layer having a first power line having a first power line having a first potential to at least one of the plurality of pixels; and a third layer having at least one line among a second power line having a second potential to at least one of the plurality of pixels and an initialization power line having a third potential to at least one of the plurality of pixels.

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