Mutilayer electronic component

Abstract

A stacked electronic component according to one embodiment of the present invention comprises a dielectric layer and first and second internal electrodes alternately arranged with the dielectric layer in between, a body including first and second surfaces facing in a first direction, third and fourth surfaces connected to the first and second surfaces and facing in a second direction, and fifth and sixth surfaces connected to the first to fourth surfaces and facing in a third direction; a first external electrode including a first connection portion disposed on the third surface and a first band portion extending from the first connection portion to a part of the first surface; and a second external electrode including a second connection portion disposed on the fourth surface and a second band portion extending from the second connection portion to a part of the first surface. The apparatus comprises: an insulating layer disposed on the second surface and extending to a portion of the first and second connection portions; and a plating layer disposed on the first and second band portions; wherein the plating layer extends to a portion of the first and second connection portions and contacts the insulating layer, and in the region where the plating layer and the insulating layer contact, the insulating layer gradually decreases in thickness toward the end, and the end of the plating layer may include a first region extending between the insulating layer and the first and second connection portions and a second region extending to cover the insulating layer.

Description

Technology Field

[0001] The present invention relates to a stacked electronic component. Background Technology

[0003] A Multi-Layered Ceramic Capacitor (MLCC), one of the multilayer electronic components, is a chip-type capacitor mounted on the printed circuit boards of various electronic products—such as video devices like Liquid Crystal Displays (LCDs) and Plasma Display Panels (PDPs), computers, smartphones, and mobile phones—that serves to charge or discharge electricity.

[0005] These multilayer ceramic capacitors can be used as components in various electronic devices due to their advantages of being compact, guaranteeing high capacitance, and being easy to mount.

[0006] Recently, with the miniaturization and multifunctionality of electronic products, the demand for higher integration and capacitance of multilayer ceramic capacitors has increased, leading to the minimization of the space between multilayer ceramic capacitors.

[0007] In addition, as multilayer ceramic capacitors are used in automobiles or infotainment systems, there is an increasing demand for high reliability, high strength characteristics, and miniaturization.

[0009] Accordingly, in Patent Document 1, in order to suppress cracks in the body caused by tensile stress due to thermal shrinkage of the solder fillet, a glass layer is disposed directly on the sintered body layer on each cross-sectional side so as to extend in a direction orthogonal to one main surface and side of the body and constitute a part of the external electrode surface, and a plating layer is disposed on the external electrode surface not covered by the glass layer.

[0011] Meanwhile, to achieve miniaturization and high capacitance of multilayer ceramic capacitors, it is necessary to increase the number of layers by forming the internal electrodes and dielectric layers thinly, and to increase the effective volume fraction required for capacitance realization by minimizing the volume of parts that do not affect capacitance formation.

[0012] In addition, in order to mount the maximum number of components within a limited substrate area, it is necessary to minimize the mounting space.

[0013] In addition, as multilayer ceramic capacitors become smaller and have higher capacitance, the margin thickness becomes thinner, which can make it easier for external moisture or plating solution to penetrate, and this can compromise reliability. Therefore, a method is required to protect multilayer ceramic capacitors from external moisture or plating solution penetration. Prior art literature

[0015] (Patent Document 0001) JP 2016-178219 A The problem to be solved

[0016] One of the various objectives of the present invention is to protect stacked electronic components from stress caused by thermal shrinkage of solder fillets.

[0017] One of the various objectives of the present invention is to miniaturize and increase the capacity of stacked electronic components.

[0018] One of the various objectives of the present invention is to reduce the mounting volume.

[0019] One of the various objectives of the present invention is to protect laminated electronic components from the penetration of external moisture and plating solutions.

[0021] However, the purpose of the present invention is not limited to the above description and may be more easily understood in the process of explaining specific embodiments of the present invention. means of solving the problem

[0023] A stacked electronic component according to one embodiment of the present invention comprises a dielectric layer and first and second internal electrodes alternately arranged with the dielectric layer in between, a body including first and second surfaces facing in a first direction, third and fourth surfaces connected to the first and second surfaces and facing in a second direction, and fifth and sixth surfaces connected to the first to fourth surfaces and facing in a third direction; a first external electrode including a first connection portion disposed on the third surface and a first band portion extending from the first connection portion to a part of the first surface; and a second external electrode including a second connection portion disposed on the fourth surface and a second band portion extending from the second connection portion to a part of the first surface. The apparatus comprises: an insulating layer disposed on the second surface and extending to a portion of the first and second connection portions; and a plating layer disposed on the first and second band portions; wherein the plating layer extends to a portion of the first and second connection portions and contacts the insulating layer, and in the region where the plating layer and the insulating layer contact, the insulating layer gradually decreases in thickness toward the end, and the end of the plating layer may include a first region extending between the insulating layer and the first and second connection portions and a second region extending to cover the insulating layer.

[0026] A stacked electronic component according to one embodiment of the present invention comprises a dielectric layer and first and second internal electrodes alternately arranged with the dielectric layer in between, a body including first and second surfaces facing in a first direction, third and fourth surfaces connected to the first and second surfaces and facing in a second direction, and fifth and sixth surfaces connected to the first to fourth surfaces and facing in a third direction; a first external electrode including a first connection portion disposed on the third surface and a first band portion extending from the first connection portion to a part of the first surface; a second external electrode including a second connection portion disposed on the fourth surface and a second band portion extending from the second connection portion to a part of the first surface; and an insulating layer disposed on the second surface and the first and second connection portions and extending to a part of the first and second band portions. and a plating layer disposed on the first and second band portions and in contact with the insulating layer; wherein in the region where the insulating layer and the plating layer are in contact, the insulating layer gradually decreases in thickness toward the end, and the end of the plating layer may include a third region disposed extending between the insulating layer and the first and second band portions and a fourth region disposed extending to cover the insulating layer.

[0028] A stacked electronic component according to one embodiment of the present invention comprises: a body including a dielectric layer and first and second internal electrodes alternately arranged with the dielectric layer in between, and including first and second surfaces facing in a first direction, third and fourth surfaces connected to the first and second surfaces and facing in a second direction, and fifth and sixth surfaces connected to the first to fourth surfaces and facing in a third direction; a first external electrode including a first connection portion disposed on the third surface, a first band portion extending from the first connection portion to a part of the first surface, and a third band portion extending from the first connection portion to a part of the second surface; a second external electrode including a second connection portion disposed on the fourth surface, a second band portion extending from the second connection portion to a part of the first surface, and a fourth band portion extending from the second connection portion to a part of the second surface; and an insulating layer disposed on the first and second connection portions and disposed to cover the second surface and the third and fourth band portions. The apparatus includes a plating layer disposed on the first and second band portions, wherein the plating layer extends to a portion of the first and second connection portions and contacts the insulating layer, and in the region where the plating layer and the insulating layer contact, the insulating layer gradually decreases in thickness toward the end, and the end of the plating layer may include a first region disposed extending between the insulating layer and the first and second connection portions and a second region disposed extending to cover the insulating layer.

[0030] A stacked electronic component according to one embodiment of the present invention comprises: a body including a dielectric layer and first and second internal electrodes alternately arranged with the dielectric layer in between, and including first and second surfaces facing in a first direction, third and fourth surfaces connected to the first and second surfaces and facing in a second direction, and fifth and sixth surfaces connected to the first to fourth surfaces and facing in a third direction; a first external electrode including a first connection portion disposed on the third surface, a first band portion extending from the first connection portion to a part of the first surface, and a first corner portion disposed extending from the first connection portion to a corner connecting the second surface and the third surface; and a second external electrode including a second connection portion disposed on the fourth surface, a second band portion extending from the second connection portion to a part of the first surface, and a second corner portion disposed extending from the second connection portion to a corner connecting the second surface and the fourth surface. An insulating layer disposed on the first and second connection portions and disposed to cover the second surface, the first and second corner portions; and a plating layer disposed on the first and second band portions; wherein B3 is the second direction average size from the extension line of the third surface to the end of the first corner portion, B4 is the second direction average size from the extension line of the fourth surface to the end of the second corner portion, G1 is the second direction average size of the area separated from the third surface and the second internal electrode, and G2 is the second direction average size of the area separated from the fourth surface and the first internal electrode, satisfying B3≤G1 and B4≤G2, and the plating layer extends to a part of the first and second connection portions and contacts the insulating layer, and in the area where the plating layer and the insulating layer contact, the thickness of the insulating layer gradually decreases towards the end, and the end of the plating layer may include a first area disposed by extending between the insulating layer and the first and second connection portions and a second area disposed by extending to cover the insulating layer.

[0032] A stacked electronic component according to one embodiment of the present invention comprises: a body including a dielectric layer and first and second internal electrodes alternately disposed with the dielectric layer in between, and including first and second surfaces facing in a first direction, third and fourth surfaces connected to the first and second surfaces and facing in a second direction, and fifth and sixth surfaces connected to the first to fourth surfaces and facing in a third direction; a first external electrode including a first connecting electrode disposed on the third surface and a first band electrode disposed on the first surface and connected to the first connecting electrode; a second external electrode including a second connecting electrode disposed on the fourth surface and a second band electrode disposed on the first surface and connected to the second connecting electrode; a first insulating layer disposed on the first connecting electrode; a second insulating layer disposed on the second connecting electrode; a first plating layer disposed on the first band electrode; and a second plating layer disposed on the second band electrode. The first plating layer may include a first-1 region extending between the first insulating layer and the first connecting electrode and a first-2 region extending to cover the first insulating layer, and the second plating layer may include a second-1 region extending between the second insulating layer and the second connecting electrode and a second-2 region extending to cover the second insulating layer. Effects of the invention

[0034] One of the various effects of the present invention is to suppress the occurrence of cracks caused by stress due to thermal shrinkage of the solder fillet.

[0035] One of the various effects of the present invention is to increase the effective volume fraction required for a volume sphere.

[0036] One of the various objectives of the present invention is to minimize the mounting space of stacked electronic components.

[0037] One of the various objectives of the present invention is to prevent the penetration of external moisture and plating solution into stacked electronic components.

[0039] The various and beneficial advantages and effects of the present invention are not limited to those described above and will be more easily understood in the process of explaining specific embodiments of the present invention. Brief explanation of the drawing

[0041] FIG. 1 is a schematic perspective view of a stacked electronic component according to one embodiment of the present invention. Figure 2 is a schematic perspective view of the body of the stacked electronic component of Figure 1. Figure 3 is a cross-sectional view according to II' of Figure 1. Figure 4 is an enlarged view of the P1 region of Figure 3. FIG. 5 is an exploded perspective view schematically illustrating the body of FIG. 2 disassembled. FIG. 6 is a schematic perspective view of a substrate on which the stacked electronic components of FIG. 1 are mounted. FIG. 7 schematically illustrates a perspective view of a stacked electronic component according to one embodiment of the present invention. FIG. 8 is a cross-sectional view taken along II-II' of FIG. 7. Figure 9 is an enlarged view of the P2 region of Figure 8. FIG. 10 is a schematic perspective view of a stacked electronic component according to one embodiment of the present invention. FIG. 11 is a cross-sectional view taken along III-III' of FIG. 10. FIG. 12 schematically illustrates a perspective view of a stacked electronic component according to one embodiment of the present invention. FIG. 13 is a cross-sectional view taken along IV-IV' of FIG. 12. FIG. 14 schematically illustrates a perspective view of a stacked electronic component according to one embodiment of the present invention. FIG. 15 is a cross-sectional view according to VV' of FIG. 14. FIG. 16 schematically illustrates a perspective view of a stacked electronic component according to one embodiment of the present invention. FIG. 17 is a cross-sectional view taken along VI-VI' of FIG. 16. FIG. 18 schematically illustrates a perspective view of a stacked electronic component according to one embodiment of the present invention. FIG. 19 is a cross-sectional view along VII-VII' of FIG. 18. Figure 20 is an enlarged view of the P3 area of ​​Figure 19. FIG. 21 schematically illustrates a perspective view of a stacked electronic component according to one embodiment of the present invention. FIG. 22 is a cross-sectional view along VIII-VIII' of FIG. 21. FIG. 23 illustrates a modified example of FIG. 21. FIG. 24 schematically illustrates a perspective view of a stacked electronic component according to one embodiment of the present invention. FIG. 25 is a cross-sectional view according to IX-IX' of FIG. 24. FIG. 26 illustrates a modified example of FIG. 24. FIG. 27 schematically illustrates a perspective view of a stacked electronic component according to one embodiment of the present invention. FIG. 28 is a cross-sectional view according to XX' of FIG. 27. FIG. 29 illustrates a modified example of FIG. 27. FIG. 30 schematically illustrates a perspective view of a stacked electronic component according to an embodiment of the present invention. FIG. 31 is a cross-sectional view taken along XI-XI' of FIG. 30. FIG. 32 illustrates a modified example of FIG. 30. FIG. 33 schematically illustrates a perspective view of a stacked electronic component according to one embodiment of the present invention. FIG. 34 is a cross-sectional view taken along XII-XII' of FIG. 33. FIG. 35 schematically illustrates a perspective view of a stacked electronic component according to one embodiment of the present invention. FIG. 36 is a cross-sectional view taken along XIII-XIII' of FIG. 35. FIG. 37 illustrates a modified example of FIG. 35. Fig. 38 illustrates a modified example of Fig. 17. FIG. 39 schematically illustrates a perspective view of a stacked electronic component according to an embodiment of the present invention. FIG. 40 is a cross-sectional view taken along XIV-XIV' of FIG. 39. FIG. 41 is an enlarged view of the K1 region of FIG. 40. Specific details for implementing the invention

[0042] Embodiments of the present invention will be described below with reference to specific embodiments and the attached drawings. However, embodiments of the present invention may be modified in various different forms, and the scope of the present invention is not limited to the embodiments described below. Furthermore, embodiments of the present invention are provided to more completely explain the present invention to those skilled in the art. Accordingly, the shapes and sizes of elements in the drawings may be exaggerated for clearer explanation, and elements indicated by the same reference numerals in the drawings are the same elements.

[0044] Furthermore, in order to clearly explain the invention in the drawings, parts unrelated to the explanation are omitted, and the size and thickness of each component shown in the drawings are depicted arbitrarily for convenience of explanation; thus, the invention is not necessarily limited to what is illustrated. Additionally, components with the same function within the scope of the same concept are described using the same reference numerals. Moreover, throughout the specification, when a part is described as "comprising" a certain component, this means that, unless specifically stated otherwise, it does not exclude other components but may include additional components.

[0045] In the drawing, the first direction may be defined as the stacking direction or the thickness (T) direction, the second direction as the length (L) direction, and the third direction as the width (W) direction.

[0047] FIG. 1 is a schematic perspective view of a stacked electronic component according to one embodiment of the present invention.

[0048] Figure 2 is a schematic perspective view of the body of the stacked electronic component of Figure 1.

[0049] Figure 3 is a cross-sectional view according to II' of Figure 1.

[0050] Figure 4 is an enlarged view of the P1 region of Figure 3.

[0051] FIG. 5 is an exploded perspective view schematically illustrating the body of FIG. 2 disassembled.

[0052] FIG. 6 is a schematic perspective view of a substrate on which the stacked electronic components of FIG. 1 are mounted.

[0054] Hereinafter, with reference to FIGS. 1 to 6, a stacked electronic component (1000) according to one embodiment of the present invention will be described.

[0056] *

[0057] A stacked electronic component (1000) according to one embodiment of the present invention may include a dielectric layer (111) and first and second internal electrodes (121, 122) alternately arranged with the dielectric layer (111) in between, and may include a body (110) comprising first and second surfaces (1, 2) facing in a first direction, third and fourth surfaces (3, 4) connected to the first and second surfaces and facing in a second direction, and fifth and sixth surfaces (5, 6) connected to the first to fourth surfaces and facing in a third direction.

[0058] Referring to FIGS. 2 and 3, the body (110) has dielectric layers (111) and internal electrodes (121, 122) alternately stacked.

[0059] There are no specific restrictions on the specific shape of the body (110), but as illustrated, the body (110) may be formed in a cuboid shape or a similar shape. Due to the shrinkage of the ceramic powder contained in the body (110) during the firing process, the body (110) may not have a cuboid shape with perfect straight lines, but may have a substantially cuboid shape.

[0060] The body (110) may have first and second surfaces (1, 2) facing each other in a first direction, third and fourth surfaces (3, 4) connected to the first and second surfaces (1, 2) and facing each other in a second direction, and fifth and sixth surfaces (5, 6) connected to the first and second surfaces (1, 2) and facing each other in a third direction.

[0061] In one embodiment, the body (110) includes a first-3 corner connecting a first surface and a third surface, a first-4 corner connecting the first surface and a fourth surface, a second-3 corner connecting the second surface and a third surface, and a second-4 corner connecting the second surface and a fourth surface, wherein the first-3 corner and the second-3 corner have a shape that contracts toward the center of the first direction of the body as they get closer to the third surface, and the first-4 corner and the second-4 corner may have a shape that contracts toward the center of the first direction of the body as they get closer to the fourth surface.

[0062] As the margin area where the internal electrodes (121, 122) are not placed on the dielectric layer (111) overlaps, a step difference occurs due to the thickness of the internal electrodes (121, 122), so that the corner connecting the first surface and the third to sixth surfaces and / or the corner connecting the second surface and the third to sixth surfaces may have a shape that is contracted toward the center of the first direction of the body (110) when viewed with respect to the first surface or the second surface. Alternatively, due to shrinkage behavior during the sintering process of the body, the corner connecting the first surface (1) and the third to sixth surfaces (3, 4, 5, 6) and / or the corner connecting the second surface (2) and the third to sixth surfaces (3, 4, 5, 6) may have a shape that is contracted toward the center of the first direction of the body (110) when viewed with respect to the first surface or the second surface. Alternatively, in order to prevent chipping defects, the corners connecting each face of the body (110) may be rounded by performing a separate process, so that the corner connecting the first face and the third to sixth faces and / or the corner connecting the second face and the third to sixth faces may have a round shape.

[0063] The above corners may include a 1-3 corner connecting the first surface and the third surface, a 1-4 corner connecting the first surface and the fourth surface, a 2-3 corner connecting the second surface and the third surface, and a 2-4 corner connecting the second surface and the fourth surface. Additionally, the corners may include a 1-5 corner connecting the first surface and the fifth surface, a 1-6 corner connecting the first surface and the sixth surface, a 2-5 corner connecting the second surface and the fifth surface, and a 2-6 corner connecting the second surface and the sixth surface. The first to sixth surfaces of the body (110) may generally be flat surfaces, and uneven areas may be viewed as corners. Hereinafter, the extension line of each surface may mean a line extended based on the flat part of each surface.

[0064] At this time, among the external electrodes (131, 132), the area placed on the corner of the body (110) may be called the corner portion, the area placed on the third and fourth surfaces of the body (110) may be called the connection portion, and the area placed on the first and second surfaces of the body may be called the band portion.

[0065] Meanwhile, in order to suppress the step difference caused by the internal electrodes (121, 122), after lamination, the internal electrodes are cut so that they are exposed to the fifth and sixth surfaces (5, 6) of the body, and then a single dielectric layer or two or more dielectric layers are laminated in the third direction (width direction) on both sides of the capacitance forming part (Ac) to form a margin part (114, 115), the part connecting the first surface and the fifth and sixth surfaces and the part connecting the second surface and the fifth and sixth surfaces may not have a shrunken shape.

[0067] A plurality of dielectric layers (111) forming the body (110) are in a sintered state, and the boundary between adjacent dielectric layers (111) can be integrated to such an extent that it is difficult to verify without using a scanning electron microscope (SEM).

[0068] According to one embodiment of the present invention, the raw material forming the dielectric layer (111) is not particularly limited as long as sufficient capacitance can be obtained. For example, a barium titanate-based material, a lead composite perovskite-based material, or a strontium titanate-based material may be used. The barium titanate-based material may include BaTiO3-based ceramic powder, and examples of the ceramic powder include BaTiO3, or BaTiO3 in which Ca (calcium), Zr (zirconium), etc. are partially dissolved (Ba 1-x Ca x )TiO3(0 <x<1), Ba(Ti 1-y Ca y )O3(0 <y<1), (Ba 1-x Ca x )(Ti 1-y Zr y )O3(0 <x<1, 0<y<1)또는 Ba(Ti1-y Zr y )O3(0 <y<1) 등을 들 수 있다.

[0069] In addition, the raw material forming the dielectric layer (111) may have various ceramic additives, organic solvents, binders, dispersants, etc. added to a powder such as barium titanate (BaTiO3) according to the purpose of the present invention.

[0071] Meanwhile, the average thickness (td) of the dielectric layer (111) does not need to be specifically limited.

[0072] However, generally, when the dielectric layer is formed thinly with a thickness of less than 0.6 μm, especially when the thickness of the dielectric layer is 0.35 μm or less, there was a concern that reliability would be reduced.

[0073] According to one embodiment of the present invention, by placing an insulating layer on the connection portion of an external electrode and placing a plating layer on the band portion of an external electrode, the penetration of external moisture and plating solution can be prevented, thereby improving reliability, so excellent reliability can be secured even when the average thickness of the dielectric layer (111) is 0.35 μm or less.

[0074] Therefore, when the average thickness of the dielectric layer (111) is 0.35 μm or less, the reliability improvement effect according to the present invention can be more pronounced.

[0075] The average thickness (td) of the dielectric layer (111) may refer to the average thickness of the dielectric layer (111) disposed between the first and second internal electrodes (121, 122).

[0076] The average thickness of the dielectric layer (111) can be measured by scanning an image of the cross-section of the body (110) in the length and thickness direction (LT) using a scanning electron microscope (SEM) at a magnification of 10,000. More specifically, the average value can be measured by measuring the thickness of a dielectric layer at 30 equally spaced points in the length direction from the scanned image. The 30 equally spaced points can be designated in the capacitance forming unit (Ac). In addition, if this average value measurement is extended to 10 dielectric layers and the average value is measured, the average thickness of the dielectric layer can be further generalized.

[0078] The body (110) may include a capacitance forming part (Ac) in which a capacitance is formed by including a first internal electrode (121) and a second internal electrode (122) that are positioned facing each other with a dielectric layer (111) in between, and cover parts (112, 113) formed on the upper and lower sides of the first direction of the capacitance forming part (Ac).

[0079] In addition, the capacitance forming part (Ac) is a part that contributes to the capacitance formation of the capacitor, and can be formed by repeatedly stacking a plurality of first and second internal electrodes (121, 122) with a dielectric layer (111) in between.

[0081] The cover portion (112, 113) may include an upper cover portion (112) positioned above the first direction of the capacity forming portion (Ac) and a lower cover portion (113) positioned below the first direction of the capacity forming portion (Ac).

[0083] The upper cover portion (112) and lower cover portion (113) can be formed by stacking a single dielectric layer or two or more dielectric layers in the thickness direction on the upper and lower surfaces of the capacitance forming portion (Ac), respectively, and can basically perform the role of preventing damage to the internal electrode due to physical or chemical stress.

[0084] The upper cover portion (112) and lower cover portion (113) do not include an internal electrode and may include the same material as the dielectric layer (111).

[0085] That is, the upper cover portion (112) and the lower cover portion (113) may include a ceramic material, for example, a barium titanate (BaTiO3)-based ceramic material.

[0086] Meanwhile, the average thickness of the cover portions (112, 113) does not need to be specifically limited. However, in order to more easily achieve miniaturization and high capacity of the stacked electronic component, the average thickness (tc) of the cover portions (112, 113) may be 15 μm or less. In addition, according to one embodiment of the present invention, by placing an insulating layer on the connection portion of the external electrode and placing a plating layer on the band portion of the external electrode, the penetration of external moisture and plating solution can be prevented, thereby improving reliability. Therefore, excellent reliability can be secured even when the average thickness (tc) of the cover portions (112, 113) is 15 μm or less.

[0087] The average thickness (tc) of the cover portion (112, 113) may mean the first direction size and may be the average value of the first direction sizes of the cover portion (112, 113) measured at five equally spaced points on the upper or lower part of the capacitance forming portion (Ac).

[0089] In addition, a margin portion (114, 115) may be disposed on the side of the above-mentioned capacity forming portion (Ac).

[0090] The margin portions (114, 115) may include a first margin portion (114) disposed on the fifth surface (5) of the body (110) and a second margin portion (115) disposed on the sixth surface (6). That is, the margin portions (114, 115) may be disposed on both end surfaces in the width direction of the ceramic body (110).

[0091] The margin portion (114, 115) may refer to the area between the two ends of the first and second internal electrodes (121, 122) and the boundary surface of the body (110) in a cross-section cut in the width-thickness (WT) direction of the body (110), as shown in FIG. 3.

[0092] The margin portion (114, 115) can basically perform the role of preventing damage to the internal electrode due to physical or chemical stress.

[0093] The margin portion (114, 115) may be formed by applying a conductive paste to the ceramic green sheet, excluding the area where the margin portion is to be formed, to form an internal electrode.

[0094] In addition, to suppress the step difference caused by the internal electrodes (121, 122), after lamination, the internal electrodes may be cut so that they are exposed to the fifth and sixth sides (5, 6) of the body, and then a single dielectric layer or two or more dielectric layers may be laminated in the third direction (width direction) on both sides of the capacitance forming part (Ac) to form a margin part (114, 115).

[0095] Meanwhile, the width of the margin portion (114, 115) does not need to be specifically limited. However, in order to more easily achieve miniaturization and high capacity of the stacked electronic component, the average width of the margin portion (114, 115) may be 15 μm or less. In addition, according to one embodiment of the present invention, by placing an insulating layer on the connection portion of the external electrode and placing a plating layer on the band portion of the external electrode, the penetration of external moisture and plating solution can be prevented, thereby improving reliability. Therefore, excellent reliability can be secured even when the average width of the margin portion (114, 115) is 15 μm or less.

[0096] The average width of the margin portion (114, 115) may mean the average size of the third direction of the margin portion (114, 115), and may be the average value of the third direction sizes of the margin portion (114, 115) measured at five equally spaced points on the side of the capacitance forming portion (Ac).

[0098] The internal electrodes (121, 122) are alternately stacked with the dielectric layer (111).

[0099] The internal electrodes (121, 122) may include first and second internal electrodes (121, 122). The first and second internal electrodes (121, 122) are alternately arranged to face each other with the dielectric layer (111) constituting the body (110) in between, and may be exposed to the third and fourth surfaces (3, 4) of the body (110), respectively.

[0100] Referring to FIG. 3, the first internal electrode (121) may be spaced apart from the fourth surface (4) and exposed through the third surface (3), and the second internal electrode (122) may be spaced apart from the third surface (3) and exposed through the fourth surface (4). A first external electrode (131) may be disposed on the third surface (3) of the body and connected to the first internal electrode (121), and a second external electrode (132) may be disposed on the fourth surface (4) of the body and connected to the second internal electrode (122).

[0101] That is, the first internal electrode (121) is connected to the first external electrode (131) but is not connected to the second external electrode (132), and the second internal electrode (122) is connected to the second external electrode (132) but is not connected to the first external electrode (131). Accordingly, the first internal electrode (121) can be formed at a certain distance from the fourth surface (4), and the second internal electrode (122) can be formed at a certain distance from the third surface (3).

[0102] At this time, the first and second internal electrodes (121, 122) can be electrically separated from each other by a dielectric layer (111) placed in the middle.

[0103] The body (110) can be formed by alternately stacking a ceramic green sheet with a first internal electrode (121) printed thereon and a ceramic green sheet with a second internal electrode (122) printed thereon, and then firing them.

[0104] The material forming the internal electrode (121, 122) is not particularly limited and a material with excellent electrical conductivity may be used. For example, the internal electrode (121, 122) may include one or more of nickel (Ni), copper (Cu), palladium (Pd), silver (Ag), gold (Au), platinum (Pt), tin (Sn), tungsten (W), titanium (Ti), and alloys thereof.

[0105] Additionally, the internal electrodes (121, 122) can be formed by printing a conductive paste for internal electrodes, comprising one or more of nickel (Ni), copper (Cu), palladium (Pd), silver (Ag), gold (Au), platinum (Pt), tin (Sn), tungsten (W), titanium (Ti), and alloys thereof, onto a ceramic green sheet. The printing method of the conductive paste for internal electrodes may include screen printing or gravure printing, but the present invention is not limited thereto.

[0107] Meanwhile, the average thickness (te) of the internal electrodes (121, 122) does not need to be specifically limited.

[0108] However, generally, when the internal electrode is formed thinly with a thickness of less than 0.6 μm, especially when the thickness of the internal electrode is 0.35 μm or less, there was a concern that reliability would be reduced.

[0109] According to one embodiment of the present invention, by placing an insulating layer on the connection portion of an external electrode and placing a plating layer on the band portion of an external electrode, the penetration of external moisture and plating solution can be prevented, thereby improving reliability, so excellent reliability can be secured even when the average thickness of the internal electrode (121, 122) is 0.35 μm or less.

[0110] Accordingly, when the thickness of the internal electrodes (121, 122) is 0.35 μm or less on average, the effect according to the present invention can be more pronounced, and the miniaturization and high capacity of the ceramic electronic component can be achieved more easily.

[0111] The average thickness (te) of the internal electrodes (121, 122) above may mean the average thickness of the internal electrodes (121, 122).

[0112] The average thickness of the internal electrodes (121, 122) can be measured by scanning an image of the cross-section of the body (110) in the length and thickness direction (LT) using a scanning electron microscope (SEM) at a magnification of 10,000. More specifically, the average value can be measured by measuring the thickness of one internal electrode at 30 equally spaced points in the length direction from the scanned image. The 30 equally spaced points can be designated in the capacitance forming unit (Ac). Additionally, if this average value measurement is extended to 10 internal electrodes and the average value is measured, the average thickness of the internal electrodes can be further generalized.

[0114] The external electrodes (131, 132) may be disposed on the third surface (3) and the fourth surface (4) of the body (110). The external electrodes (131, 132) may include first and second external electrodes (131, 132) respectively disposed on the third and fourth surfaces (3, 4) of the body (110) and connected to the first and second internal electrodes (121, 122) respectively.

[0115] The external electrodes (131, 132) may include a first external electrode (131) comprising a first connection portion (131a) disposed on a third surface and a first band portion (131b) extending from the first connection portion to a part of the first surface, and a second external electrode (132) comprising a second connection portion (132a) disposed on a fourth surface and a second band portion (132b) extending from the second connection portion to a part of the first surface. The first connection portion (131a) may be connected to the first internal electrode (121) on the third surface, and the second connection portion (132a) may be connected to the second internal electrode (122) on the fourth surface.

[0116] Additionally, the first external electrode (131) may include a third band portion (131c) extending from the first connection portion (131a) to a part of the second surface, and the second external electrode (132) may include a fourth band portion (132c) extending from the second connection portion (132a) to a part of the second surface. Furthermore, the first external electrode (131) may include a first side band portion extending from the first connection portion (131a) to a part of the fifth and sixth surfaces, and the second external electrode (132) may include a second side band portion extending from the second connection portion (132a) to a part of the fifth and sixth surfaces.

[0117] However, the third band portion, the fourth band portion, the first side band portion, and the second side band portion may not be essential components of the present invention. The first and second external electrodes (131, 132) may not be disposed on the second surface, nor may they be disposed on the fifth and sixth surfaces. Since the first and second external electrodes (131, 132) are not disposed on the second surface, the first and second external electrodes (131, 132) may be disposed below the extension line of the second surface of the body. Additionally, the first and second connection portions (131a, 132a) may be disposed spaced apart from the fifth and sixth surfaces, and the first and second connection portions (131a, 132a) may be disposed spaced apart from the second surface. Additionally, the first and second band portions (131b, 132b) may also be disposed spaced apart from the fifth and sixth surfaces.

[0118] Meanwhile, when the first and second external electrodes (131, 132) include third and fourth band portions (131c, 132c), an insulating layer is shown disposed on the third and fourth band portions (131c, 132c), but is not limited thereto, and a plating layer may be disposed on the third and fourth band portions (131c, 132c) to improve ease of mounting. Additionally, the first and second external electrodes (131, 132) may be in a form that includes the third and fourth band portions (131c, 132c) but does not include the side band portions, in which case the first and second connection portions (131a, 132a) and the first to fourth band portions (131a, 132b, 131c, 132c) may have a form that is spaced apart from the fifth and sixth surfaces.

[0120] In this embodiment, a ceramic electronic component (100) is described having a structure having two external electrodes (131, 132), but the number or shape of the external electrodes (131, 132) may change depending on the shape of the internal electrodes (121, 122) or other purposes.

[0122] Meanwhile, the external electrodes (131, 132) can be formed using any material that has electrical conductivity, such as metal, and the specific material can be determined by considering electrical properties, structural stability, etc., and furthermore, they can have a multilayer structure.

[0123] The external electrode (131, 132) may be a fired electrode including a conductive metal and glass, or a resin-based electrode including a conductive metal and resin.

[0124] Additionally, the external electrodes (131, 132) may be formed such that a sintered electrode and a resin-based electrode are sequentially formed on the body. Additionally, the external electrodes (131, 132) may be formed by transferring a sheet containing a conductive metal onto the body, or by transferring a sheet containing a conductive metal onto the sintered electrode.

[0125] The conductive metal included in the external electrodes (131, 132) may be a material with excellent electrical conductivity and is not specifically limited. For example, the conductive metal may be one or more of Cu, Ni, Pd, Ag, Sn, Cr, and their alloys. Preferably, the external electrodes (131, 132) may include one or more of Ni and Ni alloys, thereby further improving connectivity with the internal electrodes (121, 122) containing Ni.

[0127] The insulating layer (151) can be placed on the first and second connection parts (131a, 132a).

[0128] Since the first and second connection portions (131a, 132a) are parts connected to the internal electrodes (121, 122), they can become a path for the penetration of plating solution during the plating process or for moisture penetration during actual use. In the present invention, since an insulating layer (151) is disposed on the connection portions (131a, 132a), the penetration of external moisture or plating solution can be prevented.

[0129] The insulating layer (151) may be positioned to be in contact with the first and second plating layers (141, 142). At this time, the insulating layer (151) may be in contact with the first and second plating layers (141, 142) in a manner that partially covers the ends of the insulating layer (151), or the first and second plating layers (141, 142) may be in contact with the insulating layer (151) in a manner that partially covers the ends of the insulating layer (151).

[0130] An insulating layer (151) is disposed on the first and second connection portions (131a, 132a) and may be disposed to cover the second surface and the third and fourth band portions (131c, 132c). At this time, the insulating layer (151) may be disposed to cover the area of ​​the second surface where the third and fourth band portions (131c, 132c) are not disposed, and the third and fourth band portions (131c, 132c). Accordingly, the insulating layer (151) can further improve moisture resistance reliability by covering the area where the ends of the third and fourth band portions (131c, 132c) and the body (110) come into contact, thereby blocking the moisture penetration path.

[0131] The insulating layer (151) may be disposed on the second surface and extended to the first and second connection parts (131a, 132a). Additionally, if the external electrodes (131, 132) are not disposed on the second surface, the insulating layer may be disposed to cover the entire second surface. Meanwhile, the insulating layer (151) does not necessarily have to be disposed on the second surface; the insulating layer may not be disposed on part or all of the second surface, and the insulating layer may be separated into two parts and disposed on the first and second connection parts (131a, 132a), respectively. If the insulating layer is not disposed on the entire second surface, it may be disposed below the extension line of the second surface. Additionally, the insulating layer may not be disposed on the second surface but may extend to the fifth and sixth surfaces on the first and second connection parts (131a, 132a) to form a single insulating layer.

[0132] Furthermore, the insulating layer (151) may be positioned to cover parts of the first and second side band portions, the fifth surface, and the sixth surface. At this time, parts of the fifth surface and the sixth surface that are not covered by the insulating layer (151) may be exposed to the outside.

[0133] Additionally, the insulating layer (151) may be arranged to cover all of the first and second side band portions, the fifth surface, and the sixth surface. In this case, the fifth surface and the sixth surface are not exposed to the outside, thereby improving moisture resistance reliability, and the connection portions (131a, 132a) are also not directly exposed to the outside, thereby improving the reliability of the stacked electronic component (1000). More specifically, the insulating layer may cover all of the first and second side band portions and cover all of the fifth and sixth surfaces except for the area where the first and second side band portions are formed.

[0135] The insulating layer (151) can prevent the formation of a plating layer (141, 142) on the external electrode (131, 132) on which the insulating layer (151) is placed, and can improve sealing characteristics to minimize the penetration of moisture or plating solution from the outside.

[0137] A stacked electronic component (1000) according to one embodiment of the present invention may include an insulating layer (151) disposed on the second surface (2) and extending to a portion of the first and second connection portions (131a, 132a).

[0139] The insulating layer (151) is preferably disposed on the second surface (2) and extends to the first connection part (131a), the second connection part (132a), a part of the fifth surface (5), and a part of the sixth surface (6) so as to come into contact with the plating layer (141, 142). Thus, the insulating layer (151) simultaneously covers a part of the first and second external electrodes (131, 132) and a part of the body (110), thereby protecting the stacked electronic component (1000) from plating solution, moisture, and external shock.

[0140] In addition, since the first and second external electrodes (131, 132) and the body (110) do not cover the entire surface but only a part of it, a plating layer (141, 142) can be formed on the first and second external electrodes (131, 132), so the structure can be mounted on a substrate (180).

[0141] That is, a stacked electronic component (1000) according to one embodiment of the present invention may include a plating layer (141, 142) disposed on the first and second band portions (131b, 132b).

[0143] The insulating layer (151) may include a glass material with excellent resistance to plating solution, such as a glass material containing Si, but is not limited thereto, and may be composed of a material having sufficient strength to protect the stacked electronic component (1000) from tensile stress caused by thermal shrinkage. In addition, the insulating layer (151) may include a single component or a plurality of components, and more preferably, to improve the bonding strength with the body (100) or external electrodes (131, 132), it may include one or more additives selected from TiO2, BaTiO3, Al2O3, SiO2, BaO, etc.

[0144] The method of forming the insulating layer (151) can vary depending on the composition and purpose. For example, it can be formed by forming a film of insulating paste using a squeegee, then placing external electrodes (131, 132) on the body (110) to sequentially immerse each cross-section, and then drying at a temperature of 150°C. In addition, it can be formed by sol-gel processing, chemical vapor deposition (CVD), atomic layer deposition (ALD), etc., but is not limited thereto, and can also be formed by other methods capable of forming a thin and uniform insulating layer.

[0146] In one embodiment, the insulating layer (151) is positioned to be in direct contact with the first and second external electrodes (131, 132), and the first and second external electrodes (131, 132) may include a conductive metal and glass. Accordingly, since the plating layer (141, 142) may not be positioned in the area where the insulating layer (151) is positioned on the outer surface of the first and second external electrodes (131, 132), the prevention of external electrode erosion by the plating solution can be effectively suppressed.

[0147] At this time, the first plating layer (141) is positioned to cover the end of the first external electrode (131) of the insulating layer (151), and the second plating layer (142) can be positioned to cover the end of the second external electrode (132) of the insulating layer (151). By forming the insulating layer (151) first before forming the plating layer (141, 142) on the external electrodes (131, 132), the penetration of the plating solution during the plating layer formation process can be more reliably suppressed. By forming the insulating layer before the plating layer, the plating layer (141, 142) can have a shape that covers the end of the insulating layer (151).

[0149] In one embodiment, the insulating layer (151) is positioned to be in direct contact with the first and second external electrodes (131, 132), and the first and second external electrodes (131, 132) may include a conductive metal and a resin. Accordingly, since the plating layer (141, 142) may not be positioned in the area where the insulating layer (151) is positioned on the outer surface of the first and second external electrodes (131, 132), the prevention of external electrode erosion by the plating solution can be effectively suppressed.

[0150] At this time, the first plating layer (141) is positioned to cover the end positioned on the first external electrode (131) of the insulating layer (151), and the second plating layer (142) can be positioned to cover the end positioned on the second external electrode (132) of the insulating layer (151). By forming the insulating layer (151) first before forming the plating layer (141, 142) on the external electrodes (131, 132), the penetration of the plating solution during the plating layer formation process can be more reliably suppressed.

[0152] The first and second plating layers (141, 142) can be placed on the first and second band portions (131b, 132b), respectively. The plating layers (141, 142) can perform a role in improving mounting characteristics, and as the plating layers (141, 142) are placed on the band portions (131b, 132b), the mounting space can be minimized and reliability can be improved by minimizing the penetration of the plating solution into the internal electrode. One end of the first and second plating layers (141, 142) can be in contact with the first surface, and the other end can be in contact with the insulating layer (151).

[0153] The type of plating layer (141, 142) is not specifically limited and may be a plating layer comprising one or more of Cu, Ni, Sn, Ag, Au, Pd and alloys thereof, and may be formed into multiple layers.

[0154] As a more specific example regarding the plating layer (141, 142), the plating layer (141, 142) may be a Ni plating layer or a Sn plating layer, and may be in the form where the Ni plating layer and the Sn plating layer are sequentially formed on the first and second band portions (131b, 132b).

[0156] The method of forming the plating layer (141, 142) is not particularly limited. However, the plating layer (141, 142) may be formed after the insulating layer (151) is formed to improve adhesion. The plating layer (141, 142) may be formed by any one of the wet plating method, electroplating method, or electroless plating method, but is not limited thereto, and may be formed by any other method that can form a plating layer of high purity and uniformity.

[0158] In one embodiment, the plating layer (141, 142) may be arranged to extend to a portion of the first and second connection portions (131a, 132a). That is, the plating layer (141, 142) is arranged on the first and second band portions (131b, 132b) and may extend to a portion of the first and second connection portions (131a, 132a) to come into contact with the insulating layer (151).

[0160] In Patent Document 1, to suppress cracks in a stacked electronic component caused by thermal shrinkage of a solder fillet, a glass layer is directly provided on one main surface of the body and is directly provided on the sintered body layer on each cross-sectional side so as to extend in a direction orthogonal to the side, constituting a part of the external electrode surface, and a metal layer is provided to cover the sintered body layer other than the part covered by the glass layer for mounting by a solder fillet, constituting another part of the external electrode surface.

[0161] The glass layer of Patent Document 1 is a glass material with excellent resistance to plating solutions and is composed of a glass material having a Si content of 20 mol% or more and 65 mol% or less. Meanwhile, Patent Document 1 discloses that when the molar fraction of Si is less than 20 mol%, the resistance to plating solutions is insufficient, and when it exceeds 65 mol%, the glass softening point increases and the wettability to the sintered body layer decreases, making it easy for the glass layer to peel off.

[0162] Generally, glass layers formed from glass materials containing Si are composed of insulating materials regardless of Si content, which presents a problem of weak adhesion to plating layers or external electrodes made of metal components. Consequently, delamination may occur in multilayer electronic components due to residual stress generated during the manufacturing process or external shocks, and the overall resistance of the multilayer electronic component to external shocks may be reduced.

[0163] In particular, the structure disclosed in Patent Document 1 has a structure in which the glass layer and the metal layer are simply connected with the same thickness or substantially the same thickness, so the aforementioned problems may occur further, which may cause a decrease in adhesion strength when mounting a stacked electronic component on a substrate through solder.

[0164] In the following, the correlation between the plating layer (141, 142), the insulating layer (151), and the first and second connection parts (131a, 132a) according to a stacked electronic component (1000) according to one embodiment of the present invention is explained based on the first connection part (131a), and the case based on the second connection part (132a) is omitted as it overlaps with the case based on the first connection part (131a).

[0165] Referring to FIG. 4, an insulating layer (151) according to one embodiment of the present invention may be arranged such that its thickness gradually decreases toward the end. Preferably, the insulating layer (151) may be arranged such that the distance between both ends in the longitudinal direction gradually decreases toward the end. Accordingly, a gap may be arranged between the insulating layer (151) and the first connecting part (131a).

[0166] The plating layer (141) may include an end portion in contact with the insulating layer (151) and may be divided into two regions.

[0167] The end portion of the plating layer (141) may include a first region (S1) that extends and is disposed between the insulating layer (151) and the first connection portion (131a), and may include a second region (S2) that extends and is disposed to cover the insulating layer (151). The first region (S1) may be the region of the end portion of the plating layer that extends and is disposed between the insulating layer (151) and the first connection portion (131a). Accordingly, the first region (S1) and the second region (S2) may be disposed connected to each other.

[0168] The first region (S1) is a region where the plating layer (151) is in direct contact with the first connection part (131a), so it can have a significant effect on improving adhesion.

[0169] The second region (S2) may be an end region of the plating layer that is extended and arranged to cover the insulating layer (151). That is, the second region (S2) may serve to physically connect the insulating layer (151) and the plating layer (141).

[0170] By making the end of the plating layer (151) include the first region (S1), the contact area between the plating layer (151) and the first connection part (131a) can be improved, thereby improving the adhesion between the plating layer (151) and the first connection part (131a).

[0172] In addition, the physical bonding strength can be improved by creating an anchoring effect between the insulating layer (151) and the insulating layer (141) by having the end of the plating layer include a second region (S2). More preferably, the anchoring effect can be further improved by placing the insulating layer (151) between the first region (S1) and the second region (S2).

[0173] According to a stacked electronic component (1000) according to one embodiment of the present invention, in the region where the plating layer (141, 142) and the insulating layer (151) are in contact, the insulating layer (151) gradually decreases in thickness toward the end, and the end of the plating layer (141, 142) includes a first region that extends and is arranged between the insulating layer (151) and the first and second connecting portions (131a, 132a), and a second region that extends and is arranged to cover the insulating layer (151). By doing so, even if the insulating layer is composed of a material having an insulating component, the physical bonding strength of the plating layer (141), the insulating layer (151), and the first connecting portion (131a) can be improved, thereby improving the overall strength of the stacked electronic component (1000). Accordingly, the resistance to external shock of the stacked electronic component (1000) and the decrease in adhesion strength can be prevented even when mounted on a substrate via solder.

[0175] In one embodiment, when the maximum length in the first direction of the first region (S1) is denoted as a1 and the maximum length in the first direction of the second region (S2) is denoted as a2, the condition a1 > a2 can be satisfied. If a2 is greater than a1, the area where the plating layer (141) contacts the insulating layer (151) is larger than the area where the plating layer (141) contacts the first connecting part (131a), so the adhesion between the plating layer (141), the insulating layer (151), and the first connecting part (131a) may not be sufficient. In one embodiment, by satisfying a1 > a2, the length or area where the plating layer (141) contacts the first connecting part (131a) is increased, and the area where the plating layer (141) and the insulating layer (151) come into contact is minimized, thereby further improving the physical bonding strength. Accordingly, the overall strength of the stacked electronic component (1000) can be further improved.

[0176] Meanwhile, a1 is the maximum length in the first direction of the first region (S1), which may mean the distance from the end portion of the insulating layer (151) to the point where the gap between the insulating layer (151) and the connection portion (131a, 132a) begins. Also, a2 is the maximum length in the first direction of the second region (S2), which may mean the distance from the end portion of the insulating layer to the end portion of the second region covering the end portion of the insulating layer (151).

[0177] The above a1 and a2 may be the average value of values ​​measured at 10 cross-sections in the first direction-second direction that are cut at equal intervals in the third direction.

[0179] There may be various ways to ensure that the end of the plating layer includes a first region (S1) and a second region (S2). For example, when forming an insulating layer (151) by a dipping method, the first region (S1) and the second region (S2) can be formed by controlling the shape of a plastic carrier plate or a rubber zig that fixes the upper part of a stacked electronic component.

[0180] Specifically, the ends of the plastic carrier or rubber zig are manufactured to have shapes corresponding to the first region (S1) and the second region (S2), and then the laminated electronic components are fixed and immersed in insulating paste. In this case, since the insulating layer is formed in the portion not occupied by the plastic carrier or rubber zig, the insulating layer may not be formed in the area corresponding to the first region (S1) and the second region (S2).

[0181] After immersing a stacked electronic component in insulating paste and drying it at a temperature of about 150°C, the stacked electronic component is separated from a plastic carrier or rubber zig, and then a plating layer is formed on the part where the insulating layer is not formed as described below.

[0182] At this time, since the plating solution penetrates the area where the end of the plastic carrier or rubber zig was located, the end of the plating layer can form a first region (S1) and a second region (S2).

[0183] At this time, the thickness of the plating layer can be controlled by changing the amount of plating solution or plating conditions, and at the same time, the maximum length (a1) in the first direction of the first region and the maximum length (a2) in the second region can be controlled by controlling the shape of the end of the plastic carrier or rubber zig.

[0185] Meanwhile, the order in which the insulating layer (151) and the plating layer (141) are formed does not need to be specifically limited, but after forming the insulating layer (151), the plating layer (151) is formed on the connection portion (131a, 132a) or band portion (131b, 132b) of the external electrode (131, 132) where the insulating layer (151) is not placed, thereby minimizing the gap between the plating layer (141, 142) and the insulating layer (151).

[0187] The size of the stacked electronic component (1000) does not need to be specifically limited.

[0188] However, in order to achieve both miniaturization and high capacity simultaneously, the thickness of the dielectric layer and internal electrode must be reduced to increase the number of layers, so the reliability and capacity improvement effects per unit volume according to the present invention can be more pronounced in a stacked electronic component (1000) having a size of 1005 (length × width, 1.0 mm × 0.5 mm) or less.

[0189] Accordingly, considering manufacturing error, external electrode size, etc., if the length of the ceramic electronic component (100) is 1.1 mm or less and the width is 0.55 mm or less, the reliability improvement effect according to the present invention may be more pronounced. Here, the length of the stacked electronic component (1000) refers to the second direction size of the stacked electronic component (1000), and the width of the stacked electronic component (1000) may refer to the third direction size of the stacked electronic component (1000).

[0191] Hereinafter, a stacked electronic component (1001) according to another embodiment of the present invention will be described, but descriptions that overlap with the electronic component (1000) according to one embodiment of the present invention will be omitted.

[0193] FIG. 7 is a schematic perspective view of a stacked electronic component (1001) according to one embodiment of the present invention, and FIG. 8 is a cross-sectional view according to II-II' of FIG. 7.

[0194] Figure 9 is an enlarged view of the P2 region of Figure 8.

[0195] Referring to FIGS. 7 through 9, a stacked electronic component (1001) according to another embodiment of the present invention may include an insulating layer (151-1) disposed on the second surface (2) and the first and second connection portions (131a, 132a) and extending to a portion of the first and second band portions (131b, 132b), and a plating layer (141-1, 142-1) disposed on the first and second band portions (131b, 132b) and in contact with the insulating layer (151-1). Additionally, in the area where the insulating layer and the plating layer are in contact, the insulating layer gradually decreases in thickness toward the end, and the end of the plating layer may include a third area extending between the insulating layer and the first and second band portions and a fourth area extending to cover the insulating layer. Accordingly, the height of the solder can be minimized during mounting and the mounting space can be minimized.

[0197] Referring to FIG. 9, an insulating layer (151-1) of a stacked electronic component (1001) according to another embodiment of the present invention may be arranged such that its thickness gradually decreases toward the ends on the first and second band portions (131b, 132b). Preferably, the insulating layer (151-1) may be arranged such that the distance between both ends in the longitudinal direction gradually decreases toward the ends. Accordingly, a gap may be arranged between the insulating layer (151-1) and the first and second band portions (131a).

[0199] The following description is based on the first band section (131b), and the case where the second band section (132b) is based is similar to the case where the first band section (131b) is based, so it will be omitted.

[0200] The plating layer (141-1) may include an end portion in contact with the insulating layer (151-1) and may be divided into two regions.

[0201] The end of the plating layer (141-1) may include a third region (S3) that extends between the insulating layer (151-1) and the first band portion (131b), and may include a fourth region (S4) that extends to cover the insulating layer (151-1). The third region (S3) may be the region of the end of the plating layer that extends between the insulating layer (151-1) and the first band portion (131b). Accordingly, the third region (S3) and the fourth region (S4) may be connected to each other.

[0202] The third region (S3) is the region where the plating layer (151-1) is in direct contact with the first band portion (131b), so it can have a significant effect on improving adhesion.

[0203] The fourth region (S4) may be an end region of the plating layer that is extended and arranged to cover the insulating layer (151-1). That is, the fourth region (S4) may serve to physically connect the insulating layer (151-1) and the plating layer (141-1).

[0204] By making the end of the plating layer (151-1) include a third region (S3), the contact area between the plating layer (151-1) and the first band portion (131b) can be improved, thereby improving the adhesion between the plating layer (151-1) and the first band portion (131b).

[0205] In addition, the physical bonding strength can be improved by creating an anchoring effect between the insulating layer (151-1) and the insulating layer (141-1) by having the end of the plating layer include the fourth region (S2). More preferably, the anchoring effect can be further improved by having the insulating layer (151-1) positioned between the third region (S3) and the fourth region (S4).

[0206] According to a stacked electronic component (1001) according to another embodiment of the present invention, in the region where the plating layer (141-1, 142-1) and the insulating layer (151-1) are in contact, the insulating layer (151-1) gradually decreases in thickness toward the end, and the end of the plating layer (141, 142) includes a first region that extends between the insulating layer (151) and the first and second band portions (131b, 132b) and a second region that extends to cover the insulating layer (151), thereby improving the physical bonding strength of the plating layer (141), the insulating layer (151), and the connecting portions (131b, 132b) and improving the overall strength of the stacked electronic component (1001).

[0208] In one embodiment, when the maximum length in the second direction of the third region (S3) is denoted as a3 and the maximum length in the second direction of the fourth region (S4) is denoted as a4, the condition a3 > a4 can be satisfied. If a4 is greater than a3, the area where the plating layer (141-1) contacts the insulating layer (15-1) is larger than the area where the plating layer (141-1) contacts the first band portion (131b), so the adhesion between the plating layer (141-1), the insulating layer (151-1), and the first connection portion (131b) may not be sufficient. In one embodiment, by satisfying a3 > a4, the length or area where the plating layer (141-1) contacts the first connection portion (131b) is increased, and the area where the plating layer (141-1) and the insulating layer (151-1) come into contact is minimized, thereby further improving the physical bonding strength. Accordingly, the overall strength of the stacked electronic component (1001) can be further improved.

[0209] Meanwhile, a3 is the maximum length in the second direction of the third region (S3), which may mean the distance from the end portion of the insulating layer (151-1) to the point where the gap between the insulating layer (151-1) and the band portions (131b, 132b) begins. Additionally, a4 is the maximum length in the second direction of the fourth region (S4), which may mean the distance from the end portion of the insulating layer (151-1) to the end portion of the fourth region covering the end portion of the insulating layer (151-1).

[0211] The above a3 and a4 may be the average value of values ​​measured at 10 cross-sections in the first direction-second direction that are cut at equal intervals in the third direction.

[0213] In one embodiment, when the second direction size of the body (110) is L, the second direction size from the extension line of the third surface to the end of the first band portion is B1, and the second direction size from the extension line of the fourth surface to the end of the second band portion is B2, then 0.2≤B1 / L≤0.4 and 0.2≤B2 / L≤0.4 can be satisfied.

[0214] If B1 / L and B2 / L are less than 0.2, it may be difficult to secure sufficient adhesion strength. On the other hand, if B2 / L is greater than 0.4, there is a risk that leakage current may occur between the first band portion (131b) and the second band portion (132b) under high voltage current, and there is a risk that the first band portion (131b) and the second band portion (132b) may become electrically connected due to plating bleeding during the plating process.

[0216] Meanwhile, when the internal electrodes (121, 122) are stacked in a first direction, the stacked electronic component (1000) can be horizontally mounted on the substrate (180) so that the internal electrodes (121, 122) are parallel to the mounting surface. However, the present invention is not limited to horizontal mounting, and when the internal electrodes (121, 122) are stacked in a third direction, the stacked electronic component can be vertically mounted on the substrate so that the internal electrodes (121, 122) are perpendicular to the mounting surface.

[0218] Hereinafter, a stacked electronic component according to another embodiment of the present invention will be described, but descriptions that overlap with the stacked electronic component according to one embodiment (1000) or another embodiment (10001) of the present invention will be omitted.

[0220] FIG. 10 is a schematic perspective view of a stacked electronic component (1002) according to one embodiment of the present invention, and FIG. 11 is a cross-sectional view taken along III-III' of FIG. 10.

[0221] Referring to FIGS. 10 and 11, a stacked electronic component (1002) according to one embodiment of the present invention may further include an additional insulating layer (161) disposed on a first surface (1) and disposed between a first band portion (131b) and a second band portion (132b). Accordingly, leakage current, etc., that may occur between the first band portion (131b) and the second band portion (132b) under high voltage current can be prevented.

[0222] The type of the additional insulating layer 161 is not particularly limited. For example, it may include the same components as the insulating layer 151. Meanwhile, the additional insulating layer 161 and the insulating layer 151 do not need to be formed of the same material, and may be formed of different materials. For example, the additional insulating layer 161 may include one or more thermosetting resins selected from epoxy resins, acrylic resins, and the like. In addition, the additional insulating layer 161 may include, as an additive, one or more selected from TiO2, BaTiO3, Al2O3, SiO2, BaO, and the like in addition to the polymer resin. Accordingly, the bonding force with the body or the external electrode can be improved.

[0224] FIG. 12 schematically shows a perspective view of a multilayer electronic component 1003 according to an embodiment of the present invention, and FIG. 13 is a cross-sectional view taken along line IV-IV' of FIG. 12.

[0225] Referring to FIGS. 12 and 13, in the multilayer electronic component 1003 according to an embodiment, when H1 is the average size in the first direction from the first surface 1 to the inner electrode, which is the closest to the first surface 1 among the first and second inner electrodes 121 and 122, and H2 is the average size in the first direction from the extension line of the first surface 1 to the ends of the plating layers 141-3 and 142-3 disposed on the first and second connection portions 131a and 132a, H1<H2 may be satisfied. Accordingly, the area in contact with solder during mounting can be increased to improve the fixing strength.

[0226] More preferably, when T is the average size of the body 110 in the first direction, H2<T / 2 may be satisfied. That is, H1<H2<T / 2 may be satisfied. This is because if H2 is T / 2 or more, the effect of improving moisture resistance reliability by the insulating layer may be reduced.

[0227] H1, H2, and T may be the average of values ​​measured at cross-sections (LT cross-sections) cut in the first and second directions at five equally spaced points in the third direction of the body (110). H1 may be the average of values ​​measured at the point where the internal electrode closest to the first surface (1) in each cross-section is connected to the external electrode, and H2 may be the average of values ​​measured based on the end of the plating layer in contact with the external electrode in each cross-section, and the extension line of the first surface used as a reference when measuring H1 and H2 may be the same. Additionally, T may be the average of the maximum size in the first direction of the body (110) measured in each cross-section.

[0229] FIG. 14 schematically illustrates a perspective view of a stacked electronic component (1004) according to an embodiment of the present invention, and FIG. 15 is a cross-sectional view according to VV' of FIG. 14. Referring to FIG. 14 and FIG. 15, in a stacked electronic component (1004) according to an embodiment of the present invention, the average length (B1) of the first band portion (131b-4) may be longer than the average length (B3) of the third band portion (131c-4), and the average length of the second band portion (132b-4) may be longer than the average length (B4) of the fourth band portion (132c-4). Accordingly, the surface area in contact with the solder during mounting can be increased to improve adhesion strength.

[0230] More specifically, when the second direction average size from the extension line of the third surface (3) to the end of the first band portion (131b-4) is denoted as B1, the second direction average size from the extension line of the fourth surface (4) to the end of the second band portion (132b-4) is denoted as B2, the second direction average size from the extension line of the third surface (3) to the end of the third band portion (131c-4) is denoted as B3, and the second direction average size from the extension line of the fourth surface (4) to the end of the fourth band portion (132c-4) is denoted as B4, B3 <B1 및 B4<B2를 만족할 수 있다.

[0231] At this time, when the average size of the second direction of the body (110) is L, 0.2≤B1 / L≤0.4 and 0.2≤B2 / L≤0.4 can be satisfied.

[0232] B1, B2, B3, B4 and L may be the average of values ​​measured at cross-sections (LT cross-sections) cut in the first and second directions at five points with equal intervals in the third direction of the body (110).

[0233] Additionally, the first external electrode (131-4) may include a first side band portion extending from the first connection portion (131a-4) to a part of the fifth and sixth surfaces, and the second external electrode (132-4) may include a second side band portion extending from the second connection portion (132a-4) to a part of the fifth and sixth surfaces. In this case, the size of the second direction of the first and second side band portions may gradually increase as it approaches the first surface. That is, the first and second side band portions may be arranged in a tapered shape or a trapezoidal shape.

[0235] Furthermore, when B3 is the average size in the second direction from the extension line of the third surface to the end of the third band portion (131c-4), B4 is the average size in the second direction from the extension line of the fourth surface to the end of the fourth band portion (132c-4), G1 is the average size in the second direction of the area separated from the third surface and the second internal electrode (122), and G2 is the average size in the second direction of the area separated from the fourth surface and the first internal electrode (121), then B3≤G1 and B4≤G2 can be satisfied. Accordingly, the volume occupied by the external electrode can be minimized, thereby increasing the capacity per unit volume of the stacked electronic component (1004).

[0236] The above G1 and G2 may be such that, in a cross-section where the body is cut in the first and second directions from the center of the third direction, the average value of the second direction size spaced apart to the third surface measured for any five second internal electrodes located in the center of the first direction is G1, and the average value of the second direction size spaced apart to the fourth surface measured for any five first internal electrodes located in the center of the first direction is G2.

[0237] Furthermore, G1 and G2 can be obtained from cross-sections (LT cross-sections) in which the body (110) is cut in the first and second directions at five points with equal intervals in the third direction, and the average values ​​of them can be further generalized as G1 and G2.

[0238] However, the present invention is not intended to be limited to B3≤G1 and B4≤G2, and cases satisfying B3≥G1 and B4≥G2 may also be included as embodiments of the present invention. Accordingly, in one embodiment, when B3 is the second direction average size from the extension line of the third surface to the end of the third band portion, B4 is the second direction average size from the extension line of the fourth surface to the end of the fourth band portion, G1 is the second direction average size of the area separated from the third surface and the second internal electrode, and G2 is the second direction average size of the area separated from the fourth surface and the first internal electrode, B3≥G1 and B4≥G2 may be satisfied.

[0240] In one embodiment, when the average size in the second direction from the extension line of the third surface (E3) to the end of the first band portion is denoted as B1 and the average size in the second direction from the extension line of the fourth surface to the end of the second band portion is denoted as B2, B1 ≥ G1 and B2 ≥ G2 can be satisfied. Accordingly, the adhesion strength with the substrate (180) of the stacked electronic component (1004) can be improved.

[0242] FIG. 16 schematically illustrates a perspective view of a stacked electronic component (1005) according to an embodiment of the present invention, and FIG. 17 is a cross-sectional view taken along VI-VI' of FIG. 16. Referring to FIG. 16 and FIG. 17, the first and second external electrodes (131-5, 132-5) of the stacked electronic component (1005) according to an embodiment of the present invention may not be placed on the second plane, but may be placed on the third, fourth, and first planes to form an L-shape. That is, the first and second external electrodes (131-5, 132-5) may be placed below the extension line of the second plane.

[0243] The first external electrode (131-5) may include a first connection portion (131a-5) disposed on the third surface (3) and a first band portion (131b-5) extending from the first connection portion (131a-5) to a part of the first surface (1), and the second external electrode (132-5) may include a second connection portion (132a-5) disposed on the fourth surface (4) and a second band portion (132b-5) extending from the second connection portion (132a-5) to a part of the first surface (1). The external electrodes (131-5, 132-5) may not be disposed on the second surface (2), so that the insulating layer (151-5) may be disposed to cover the entire second surface (2). Accordingly, since the volume occupied by the external electrodes (131-5, 132-5) can be minimized, the capacity per unit volume of the stacked electronic component (1005) can be further improved. However, it is not necessary to limit the insulating layer (151-5) to a form that covers the entire second surface (2), and the insulating layer may not cover part or all of the second surface (2), but may be separated and cover the first and second connection parts (131a-5, 132a-5) respectively.

[0244] Additionally, the insulating layer (151-5) may be positioned to cover a portion of the fifth and sixth surfaces to further improve reliability. At this time, a portion of the fifth and sixth surfaces not covered by the insulating layer (151-5) may be exposed to the outside.

[0245] Furthermore, the insulating layer 151-5 may be disposed to cover the entirety of the fifth surface and the sixth surface. In this case, the fifth surface and the sixth surface are not exposed to the outside, so that moisture resistance reliability can be further improved.

[0247] A first plating layer 141-5 is disposed on the first band portion 131b-5, and a second plating layer 142-5 is disposed on the second band portion 132b-5. The first and second plating layers 141-5 and 142-5 may be disposed to extend to portions on the first and second connection portions 132a-5 and 132b-5.

[0248] At this time, the external electrodes 131-5 and 132-5 may not be disposed on the fifth and sixth surfaces 5 and 6 either. That is, the external electrodes 131-5 and 132-5 may be arranged to be disposed only on the third, fourth and first surfaces.

[0249] When the average size in the first direction from the first surface 1 to the inner electrode, which is the closest to the first surface 1 among the first and second inner electrodes 121 and 122, is defined as H1, and the average size in the first direction from the extension line of the first surface 1 to the ends of the plating layers 141-5 and 142-5 disposed on the first and second connection portions 131a-5 and 132a-5 is defined as H2, H1<H2 may be satisfied. Accordingly, the area in contact with solder during mounting can be increased to improve bonding strength, and the contact area between the external electrodes 131-5, 132-5 and the plating layers 141-5, 142-5 can be increased to suppress an increase in ESR (Equivalent Series Resistance).

[0250] More preferably, when the average size of the body 110 in the first direction is defined as T, H2<T / 2 may be satisfied. That is, H1<H2<T / 2 may be satisfied. This is because when H2 is equal to or greater than T / 2, the effect of improving moisture resistance reliability by the insulating layer may be reduced.

[0251] Additionally, the first and second plating layers (141-5, 142-5) may be arranged to cover a portion of the insulating layer (151-1) on the third and fourth sides. That is, the plating layers (141-5, 142-5) may be arranged to cover the ends of the insulating layer (151-5) on the third and fourth sides. Accordingly, the bonding strength between the insulating layer (151-5) and the plating layers (141-5, 142-5) can be strengthened, thereby improving the reliability of the stacked electronic component (1005).

[0252] Additionally, the insulating layer (151-5) may be positioned to cover a portion of the first and second plating layers (141-5, 142-5) on the third and fourth sides. That is, the insulating layer (151-5) may be positioned to cover the ends of the plating layers (141-5, 142-5) on the third and fourth sides. Accordingly, the reliability of the stacked electronic component (1005) can be improved by strengthening the bonding strength between the insulating layer (151-5) and the plating layers (141-5, 142-5).

[0254] FIG. 18 is a schematic perspective view of a stacked electronic component (1006) according to one embodiment of the present invention, and FIG. 19 is a cross-sectional view according to VII-VII' of FIG. 18.

[0255] Referring to FIGS. 18 and 19, the average thickness (t1) of the first and second plating layers (141-6, 142-6) of a stacked electronic component (1006) according to one embodiment of the present invention may be thinner than the average thickness (t2) of the insulating layer (151-6).

[0256] By making the thickness (t1) of the first and second plating layers (141-6, 142-6) thinner than the thickness (t2) of the insulating layer (151-6), the contact area between the first and second plating layers (141-6, 142-6) and the insulating layer (151-6) can be minimized, thereby ensuring an excellent total bonding strength of the stacked electronic component (1006).

[0257] The thickness (t1) of the first and second plating layers (141-6, 142-6) may be the average of the thicknesses measured at 10 points at equal intervals along the first direction of the first and second connecting portions (131a-5, 132a-5) or the first and second band portions (131b-5, 132b-5), and the thickness (t2) of the insulating layer (151-6) may be the average of the thicknesses measured at 10 points at equal intervals along the first direction of the first and second connecting portions (131a-5, 132a-5).

[0259] Figure 20 is an enlarged view of the P3 area of ​​Figure 19.

[0260] Referring to FIG. 20, the plating layer (141-6, 142-6) of the stacked electronic component (1006) extends to a portion of the first and second connection portions (131a-5, 132a-5) and contacts the plating layer (141-6, 152-6). In the region where the plating layer (141-6, 142-6) and the insulating layer (151-6) are in contact, the insulating layer (151-6) gradually decreases in thickness toward the end. The end of the plating layer (141-6, 142-6) may include a first region (S1') that extends between the insulating layer (151-6) and the first and second connection portions (131a-5, 132a-5) and a second region (S2') that extends to cover the insulating layer (151-6).

[0261] Therefore, not only is the area where the plating layer (141-6, 142-6) and the insulating layer (151-6) come into direct contact minimized, but the area where the plating layer (141-6, 142-6) and the connecting part (131a-5, 132a-5) come into contact is maximized, thereby further improving the total bonding strength of the stacked electronic component (1006).

[0262] In one embodiment, when the maximum length in the first direction of the first region (S1') is a1' and the maximum length in the first direction of the second region (S'2) is a2', a1'>a2' can be satisfied. If a2' is greater than a1', the area where the plating layer (141-6) contacts the insulating layer (151-6) is larger than the area where the plating layer (141-6) contacts the connecting portion (131a-5, 132a-5), so the adhesion between the plating layer (141-6), the insulating layer (151-6), and the connecting portion (131a-5, 132a-5) may not be sufficient. In one embodiment, by satisfying a1'>a2', the length or area where the plating layer (141-6) contacts the connection portion (131a-5, 132-5) is increased, and the area where the plating layer (141-6) and the insulating layer (151-6) come into contact is minimized, thereby further improving the physical bonding strength. Accordingly, the overall strength of the stacked electronic component (1006) can be further improved.

[0264] FIG. 21 is a schematic perspective view of a stacked electronic component according to one embodiment of the present invention, and FIG. 22 is a cross-sectional view according to VIII-VIII' of FIG. 21.

[0265] Referring to FIGS. 21 and 22, a stacked electronic component (2000) according to one embodiment of the present invention comprises: a dielectric layer (111); first and second internal electrodes (121, 122) alternately arranged with the dielectric layer in between; a body (110) comprising first and second surfaces (1, 2) facing in a first direction; third and fourth surfaces (3, 4) connected to the first and second surfaces and facing in a second direction; and fifth and sixth surfaces (5, 6) connected to the first to fourth surfaces and facing in a third direction; and a first external electrode (231) comprising a first connecting electrode (231a) disposed on the third surface and a first band electrode (231b) disposed on the first surface and connected to the first connecting electrode. A second external electrode (232) comprising a second connecting electrode (232a) disposed on the fourth surface and a second band electrode (232b) disposed on the first surface and connected to the second connecting electrode; a first insulating layer (251) disposed on the first connecting electrode; a second insulating layer (252) disposed on the second connecting electrode; a first plating layer (241) disposed on the first band electrode; and a second plating layer (242) disposed on the second band electrode; The first plating layer (241) extends to a portion of the first connecting electrode (231a) and contacts the first insulating layer (251), and the second plating layer (142) extends to a portion of the second connecting electrode (232a) and contacts the second insulating layer (152), and in the region where the first and second plating layers (241, 242) contact the first and second insulating layers (251, 252), the insulating layer (251, 252) gradually decreases in thickness toward the end, and the end of the plating layer (241, 242) may include a first region extending between the insulating layer (251, 252) and the first and second connecting electrodes (231a, 232a) and a second region extending to cover the insulating layer (251, 252).

[0267] The first connecting electrode (231a) may be placed on the third surface (3) and connected to the first internal electrode (121), and the second connecting electrode (231b) may be placed on the fourth surface (4) and connected to the second internal electrode (122). Additionally, a first insulating layer (251) may be placed on the first connecting electrode (231a'), and a second insulating layer (252) may be placed on the second connecting electrode (232a).

[0268] Conventionally, when forming external electrodes, a paste containing a conductive metal was used, and a method of dipping the exposed surface of the internal electrode of the body into the paste was mainly used. However, the thickness of the external electrode formed by the dipping method could be too thick at the center in the thickness direction. Furthermore, even without the problem of thickness imbalance of the external electrode due to this dipping method, since the internal electrode is exposed on the third and fourth surfaces of the body, the thickness of the external electrode placed on the third and fourth surfaces was formed to be greater than a certain level in order to suppress the penetration of moisture and plating solution through the external electrode.

[0269] On the other hand, in the present invention, since an insulating layer (251, 252) is placed on the connecting electrode (231a, 232a), sufficient reliability can be ensured even if the thickness of the connecting electrode (231a, 232a) on the third and fourth surfaces where the internal electrode is exposed is thin.

[0271] The first and second connecting electrodes (231a, 232a) may each have a shape corresponding to the third and fourth surfaces, and the surfaces of the first and second connecting electrodes (231a, 232a) facing the body (110) may each have the same area as the third and fourth surfaces of the body (110). The first and second connecting electrodes (231a, 232a) may be positioned within a range that does not extend beyond the third and fourth surfaces (3, 4). The connecting electrodes (231a, 232a) may be positioned so as not to extend to the first, second, fifth, and sixth surfaces (1, 2, 5, 6) of the body (110). Specifically, in one embodiment, the first and second connecting electrodes (231a, 232a) may be spaced apart from the fifth and sixth surfaces. Accordingly, sufficient connectivity between the internal electrodes (121, 122) and the external electrodes (231, 232) can be secured while minimizing the volume occupied by the external electrodes, thereby increasing the capacity per unit volume of the stacked electronic component (2000).

[0272] In this regard, the first and second connecting electrodes (231a, 232a) may be spaced apart from the second surface (2). That is, since the external electrodes (231, 232) are not placed on the second surface, the volume occupied by the external electrodes (231, 232) can be further minimized, thereby further increasing the capacity per unit volume of the stacked electronic component (2000).

[0274] However, the connecting electrodes (231a, 232a) may include a corner portion that extends to the corner of the body (110) and is disposed on the corner. That is, in one embodiment, the first connecting electrode includes a corner portion (not shown) that extends to and is disposed on the first-3 corner and the second-3 corner, and the second connecting electrode may include a corner portion (not shown) that extends to and is disposed on the first-4 corner and the second-4 corner.

[0276] The thickness of the connecting electrode (231a, 232a) is not specifically limited, but may be, for example, 2 to 7 μm. Here, the thickness of the connecting electrode (231a, 232a) may mean the maximum thickness and may mean the second direction size of the connecting electrode (231a, 232a).

[0277] In one embodiment, the first and second connecting electrodes (231a, 232a) may include a metal and glass identical to the metal included in the internal electrodes (121, 122). As the first and second connecting electrodes (231a, 232a) include a metal identical to the metal included in the internal electrodes (121, 122), electrical connectivity with the internal electrodes (121, 122) can be improved, and as the first and second connecting electrodes (231a, 232a) include glass, bonding strength with the body (110) and / or insulating layer (251, 252) can be improved. In this case, the metal identical to the metal included in the internal electrodes (121, 122) may be Ni.

[0279] The first and second insulating layers (251, 252) are each placed on the first and second connecting electrodes (231a, 232a) and can perform the function of preventing a plating layer from being formed on the first and second connecting electrodes (231a, 232a). In addition, the first and second insulating layers (251, 252) can perform the function of improving sealing characteristics to minimize the penetration of moisture or plating solution from the outside.

[0280] The first and second insulating layers (251, 252) may include a silicone-based resin. Accordingly, moisture resistance reliability can be further improved, and cracks caused by thermal shrinkage and radiation cracks caused by metal diffusion can be suppressed.

[0282] The first and second insulating layers (251, 252) are each placed on the first and second connecting electrodes (231a, 232a) and can perform the function of preventing a plating layer from being formed on the first and second connecting electrodes (231a, 232a). In addition, the first and second insulating layers (251, 252) can perform the function of improving sealing characteristics to minimize the penetration of moisture or plating solution from the outside.

[0283] The insulating layer (251, 252) may include a glass material with excellent resistance to plating solution, such as a glass material containing Si, but is not limited thereto, and may be composed of a material having sufficient strength to protect the stacked electronic component (2000) from tensile stress caused by thermal shrinkage. Additionally, the insulating layer (251, 252) may include a single component or a plurality of components, and more preferably, to improve the bonding strength with the body (100) or external electrode (131, 132), it may include one or more additives selected from TiO2, BaTiO3, Al2O3, SiO2, BaO, etc.

[0284] The method of forming the insulating layer (251, 252) does not need to be specifically limited, but it can be formed by, for example, sol-gel processing, chemical vapor deposition (CVD), atomic layer deposition (ALD), etc., but is not limited thereto, and can also be formed by other methods capable of forming a thin and uniform insulating layer.

[0285] The thickness of the insulating layer (251, 252) is not specifically limited, but may be, for example, 3 to 15 μm. Here, the thickness of the insulating layer (251, 252) may mean the maximum thickness and may mean the second direction size of the insulating layer (251, 252).

[0287] The first and second band electrodes (231b, 232b) may be placed on the first surface (1) of the body (110). The first and second band electrodes (231b, 232b) may be electrically connected to the first and second internal electrodes (121, 122), respectively, by contacting the first and second connecting electrodes (231a, 232a), respectively.

[0288] The external electrode formed by the conventional dipping method was formed thickly on the third and fourth surfaces and partially extended on the first, second, fifth, and sixth surfaces, which made it difficult to secure a high effective volume ratio.

[0289] On the other hand, according to one embodiment of the present invention, the first and second connecting electrodes (231a, 232a) are placed on the surface where the internal electrode is exposed, and the first and second band electrodes (231b, 232b) are placed on the surface mounted on the substrate, thereby securing a high effective volume ratio.

[0290] Meanwhile, when the internal electrodes (121, 122) are stacked in a first direction, the stacked electronic component (2000) can be horizontally mounted on a substrate such that the internal electrodes (121, 122) are parallel to the mounting surface. However, the present invention is not limited to horizontal mounting, and when the internal electrodes (121, 122) are stacked in a third direction, the stacked electronic component can be vertically mounted on a substrate such that the internal electrodes (121, 122) are perpendicular to the mounting surface.

[0292] The first and second band electrodes (231b, 232b) can be formed using any material that has electrical conductivity, such as metal, and the specific material can be determined by considering electrical properties, structural stability, etc. For example, the first and second band electrodes (231, 232b) may be fired electrodes including a conductive metal and glass, and may be formed by applying a paste including a conductive metal and glass to the first surface of the body, but is not limited thereto, and may be a plating layer in which a conductive metal is plated on the first surface of the body.

[0293] The conductive metal included in the first and second band electrodes (231b, 232b) may be a material with excellent electrical conductivity and is not specifically limited. For example, the conductive metal may be one or more of nickel (Ni), copper (Cu), and their alloys, and may include the same metal as the metal included in the internal electrodes (121, 122).

[0295] Meanwhile, in order to secure sealing characteristics and high strength, in one embodiment, the first external electrode (231) further includes a third band electrode (not shown) disposed on the second surface (2) and connected to the first connecting electrode (231a), and the second external electrode (232) may further include a fourth band electrode (not shown) disposed on the second surface (2) and connected to the second connecting electrode (232a).

[0297] In one embodiment, when the distance from the extension line (E3) of the third surface to the end of the first band electrode (231b) is B1, the distance from the extension line (E4) of the fourth surface to the end of the second band electrode (232b) is B2, the distance from the extension line of the third surface to the end of the third band electrode (not shown) is B3, the distance from the extension line of the fourth surface to the end of the fourth band electrode (not shown) is B4, the average size in the second direction of the area separated from the third surface and the second internal electrode (122) is G1, and the average size in the second direction of the area separated from the fourth surface and the first internal electrode (121) is G2, then B1 ≥ G1, B3 ≤ G1, B2 ≥ G2, and B4 ≤ G2 can be satisfied. Accordingly, the volume occupied by the external electrode is minimized to increase the capacity per unit volume of the stacked electronic component (2000), and at the same time, the contact area with the solder during mounting is increased to improve the adhesion strength.

[0298] However, the present invention is not intended to be limited to B1≥G1, B3≤G1, B2≥G2, and B4≤G2, and cases satisfying B1≥G1, B3≥G1, B2≥G2, and B4≥G2 may also be included as embodiments of the present invention. Accordingly, in one embodiment, when the distance from the extension line (E3) of the third surface to the end of the first band electrode (231b) is B1, the distance from the extension line (E4) of the fourth surface to the end of the second band electrode (232b) is B2, the distance from the extension line of the third surface to the end of the third band electrode (not shown) is B3, the distance from the extension line of the fourth surface to the end of the fourth band electrode (not shown) is B4, the average size in the second direction of the area separated from the third surface and the second internal electrode (122) is G1, and the average size in the second direction of the area separated from the fourth surface and the first internal electrode (121) is G2, then B1≥G1, B3≥G1, B2≥G2, and B4≥G2 can be satisfied.

[0300] The first and second plating layers (241, 242) may be disposed on the first and second band electrodes (231b, 232b). The first and second plating layers (241, 242) serve to improve mounting characteristics. The types of the first and second plating layers (241, 242) are not specifically limited and may be plating layers comprising one or more of Ni, Sn, Pd, and alloys thereof, and may be formed in multiple layers.

[0301] As a more specific example regarding the first and second plating layers (241, 242), the first and second plating layers (241, 242) may be a Ni plating layer or a Sn plating layer, and may be in the form where the Ni plating layer and the Sn plating layer are sequentially formed on the first and second band electrodes (231b, 232b).

[0303] In one embodiment, the end of the first plating layer (241) may include a first-1 region extending between the first insulating layer (251) and the first connecting electrode (231a) and a first-2 region extending to cover the first insulating layer (251), and the end of the second plating layer (242) may include a second-1 region extending between the second insulating layer (252) and the second connecting electrode (232a) and a second-2 region extending to cover the second insulating layer (252). Accordingly, even if the first and second insulating layers (251, 252) are composed of a material having insulating components, the physical bonding strength of the plating layer (241, 242), insulating layer (251, 252), and connecting electrode (231a, 232a) can be improved to enhance the overall strength and resistance to external shock of the stacked electronic component (2000), and when mounted on a substrate, a decrease in adhesion strength can be prevented.

[0305] In one embodiment, when the maximum length in the first direction of the first-1 region and the second-1 region is denoted as a1 and the maximum length in the first direction of the second-1 region and the second-2 region is denoted as a2, the condition a1 > a2 can be satisfied. If a2 is greater than a1, the area where the plating layer (241, 242) contacts the insulating layer (251, 252) is larger than the area where the plating layer contacts the connecting electrode, so the adhesive strength may not be sufficient. In one embodiment, by satisfying a1 > a2, the length or area where the plating layer contacts the connecting electrode is increased, and the area where the plating layer and the insulating layer come into contact is minimized, thereby further improving the physical bonding strength. Accordingly, the overall strength of the stacked electronic component (2000) can be further improved.

[0307] In one embodiment, the first and second plating layers (241, 242) may be extended and arranged to partially cover the first and second connecting electrodes (231a, 232a), respectively.

[0308] When the average size in the first direction from the first surface (1) to the internal electrode closest to the first surface (1) among the first and second internal electrodes (121, 122) is denoted as H1, and the average size in the first direction from the extension line of the first surface (1) to the end of the first and second plating layers (241, 242) placed on the first and second connecting electrodes (231a, 232a) is denoted as H2, H1 > H2 can be satisfied. Accordingly, the penetration of the plating solution into the internal electrode during the plating process can be suppressed, thereby improving reliability.

[0310] In one embodiment, the first plating layer (241) is positioned to cover the end of the first external electrode (231) of the first insulating layer (251), and the second plating layer (242) may be positioned to cover the end of the second external electrode (232) of the second insulating layer (252). Accordingly, the reliability of the stacked electronic component (2000) can be improved by strengthening the bonding strength between the insulating layer (251, 252) and the plating layer (241, 242). In addition, by forming the first and second insulating layers (251, 252) first before forming the plating layer (241, 242) on the external electrode (231, 232), the penetration of the plating solution during the plating layer formation process can be more reliably suppressed. By forming the insulating layer before the plating layer, the plating layer (241, 242) may have a shape that covers the ends of the insulating layer (251, 252).

[0312] In one embodiment, the first insulating layer (251) is positioned to cover the end positioned on the first external electrode (231) of the first plating layer (241), and the second insulating layer (252) may be positioned to cover the end positioned on the second external electrode (332) of the second plating layer (342). Accordingly, the bonding strength between the insulating layer (351) and the plating layers (341, 342) can be strengthened to improve the reliability of the stacked electronic component (2000).

[0314] FIG. 23 illustrates a modified example (2001) of FIG. 21. Referring to FIG. 23, a modified example (2001) of a stacked electronic component (2000) according to one embodiment of the present invention may be connected to a single insulating layer (253-1) by extending the first and second insulating layers (251-1, 252-1) to the fifth and sixth surfaces (5, 6) and connecting them to each other. At this time, the connected first and second insulating layers (253-1) may be arranged to cover a portion of the fifth and sixth surfaces.

[0316] FIG. 24 schematically illustrates a perspective view of a stacked electronic component (2002) according to an embodiment of the present invention, and FIG. 25 is a cross-sectional view according to IX-IX' of FIG. 24. Referring to FIG. 24 and FIG. 25, in a stacked electronic component (2002) according to an embodiment of the present invention, the first and second plating layers (241-2, 242-2) may be arranged below the extension line of the first surface. Accordingly, the height of the solder can be minimized during mounting, and the mounting space can be minimized.

[0317] Additionally, the first and second insulating layers (251-2, 252-2) may be arranged to extend below the extension line of the first surface and to be in contact with the first and second plating layers (241-2, 242-2).

[0318] Here, the meaning that the first and second insulating layers (251-2, 252-2) are arranged to extend below the extension line of the first surface and come into contact with the first and second plating layers (241-2, 242-2) may mean that the first and second insulating layers are arranged to come into contact with the first and second plating layers and the band electrode (231b, 132b), but is not limited thereto, and the detailed position can be adjusted so as to minimize solder height and minimize mounting space during mounting. At this time, the connected first and second insulating layers (253-3) may be arranged to cover the entirety of the fifth and sixth surfaces.

[0321] FIG. 26 illustrates a variation of FIG. 24. Referring to FIG. 26, a variation (2003) of a stacked electronic component (2002) according to one embodiment of the present invention may be connected to a single insulating layer (253-3) by extending the first and second insulating layers (251-3, 252-3) to the fifth and sixth surfaces (5, 6) and connecting them to each other.

[0323] FIG. 27 schematically illustrates a perspective view of a stacked electronic component (2004) according to an embodiment of the present invention, and FIG. 28 is a cross-sectional view according to XX' of FIG. 27. Referring to FIG. 27 and FIG. 28, the stacked electronic component (2004) according to an embodiment of the present invention may further include an additional insulating layer (261) disposed on a first surface (1) and disposed between a first band electrode (231b) and a second band electrode (232b). Accordingly, leakage current, etc., that may occur between the first band electrode (231b) and the second band electrode (232b) under high voltage current can be prevented.

[0324] The type of additional insulating layer (261) does not need to be specifically limited. For example, it may contain components similar to those of the insulating layer (251-2, 252-2). Meanwhile, the additional insulating layer (261) and the insulating layer (251-2, 252-2) do not need to be formed from the same material and may be formed from different materials. For example, the additional insulating layer (261) may include one or more thermosetting resins selected from epoxy resin, acrylic resin, etc. In addition, the additional insulating layer (261) may include one or more additives selected from TiO2, BaTiO3, Al2O3, SiO2, BaO, etc., in addition to the polymer resin. Accordingly, the bonding strength with the body or external electrode can be improved.

[0326] FIG. 29 illustrates a variation of FIG. 27. Referring to FIG. 29, a variation (2005) of a stacked electronic component (2004) according to one embodiment of the present invention can be connected to a single insulating layer (253-5) by extending the first and second insulating layers (251-5, 252-5) to the fifth and sixth surfaces (5, 6) and connecting them to each other.

[0328] FIG. 30 schematically shows a perspective view of a multilayer electronic component 2006 according to an embodiment of the present invention, and FIG. 31 is a cross-sectional view taken along line XI-XI' of FIG. 30. Referring to FIGS. 30 and 31, the multilayer electronic component 2006 according to an embodiment includes a first insulating layer 251-6 disposed on the first connection electrode 231a, and a second insulating layer 252-6 disposed on the second connection electrode 232a, wherein when a first-direction average size from the first surface 1 to the inner electrode, which is disposed closest to the first surface 1 among the first and second inner electrodes 121 and 122, is defined as H1, and a first-direction average size from an extension line of the first surface 1 to the ends of the first and second plating layers 241-6 and 242-6 disposed on the first and second connection electrodes 231a and 232a is defined as H2, H1<H2 may be satisfied. Accordingly, it is possible to improve the bonding strength by increasing the area in contact with the solder during mounting.

[0329] More preferably, when the average size of the body 110 in the first direction is defined as T, H2<T / 2 may be satisfied. That is, H1<H2<T / 2 may be satisfied. This is because when H2 is T / 2 or more, the effect of improving moisture resistance reliability by the insulating layer may be reduced.

[0331] FIG. 32 shows a modified example of FIG. 30. Referring to FIG. 32, in a modified example 2007 of the multilayer electronic component 2006 according to an embodiment of the present invention, the first and second insulating layers 251-7 and 252-7 extend to the fifth and sixth surfaces 5 and 6 and are connected to each other, so as to be connected as a single insulating layer 253-7.

[0333] FIG. 33 schematically illustrates a perspective view of a stacked electronic component (2008) according to an embodiment of the present invention, and FIG. 34 is a cross-sectional view taken along XII-XII' of FIG. 33. Referring to FIG. 33 and FIG. 34, the stacked electronic component (2008) according to an embodiment of the present invention may be connected to a single insulating layer (253-8) by extending the first and second insulating layers (251-8, 252-8) to the second, fifth, and sixth surfaces (2, 5, 6) and connecting them to each other. As shown in FIG. 30, the insulating layer (253-8) may be in a form that covers the entire second surface, and may be in a form that covers only a portion of the fifth and sixth surfaces.

[0335] FIG. 35 is a schematic perspective view of a stacked electronic component (2009) according to one embodiment of the present invention, and FIG. 36 is a cross-sectional view according to XIII-XIII' of FIG. 35.

[0336] Referring to FIGS. 35 and 36, the average thickness (t1) of the first and second plating layers (241-9, 242-9) of a stacked electronic component (2009) according to one embodiment of the present invention may be thinner than the average thickness (t2) of the first and second insulating layers (251-9, 252-9).

[0337] According to one embodiment of the present invention, the average thickness (t1) of the first and second plating layers (241-9, 242-9) can be made thinner than the average thickness (t2) of the first and second insulating layers (251-9, 252-9) to reduce the contact area between the plating layer and the insulating layer, thereby suppressing the occurrence of delamination and improving the adhesion strength with the substrate (180) of the stacked electronic component (2009).

[0338] The average thickness (t1) of the first and second plating layers (241-9, 242-9) may be the average of the thicknesses measured at five equally spaced points on the first and second connecting electrodes (231a, 232a) or the first and second band electrodes (231b, 232b), and the average thickness (t2) of the insulating layer (251-9, 252-9) may be the average of the thicknesses measured at five equally spaced points on the first and second connecting electrodes (231a, 232a).

[0340] FIG. 37 illustrates a variation of FIG. 35. Referring to FIG. 34, a variation (2010) of a stacked electronic component (2009) according to one embodiment of the present invention can be connected to a single insulating layer (253-10) by extending the first and second insulating layers (251-10, 252-10) to the fifth and sixth surfaces (5, 6) and connecting them to each other.

[0342] FIG. 38 illustrates a variation of FIG. 17. Referring to FIG. 38, a variation (1007) of a stacked electronic component (1005) according to one embodiment of the present invention may have an L-shape in which the first and second external electrodes (131-7, 132-7) are not disposed on the second surface.

[0343] The first external electrode (131-7) may include a first connection portion (131a-7) disposed on the third surface (3) and a first band portion (131b-7) extending from the first connection portion (131a-7) to a part of the first surface (1), and the second external electrode (132-7) may include a second connection portion (132a-7) disposed on the fourth surface (4) and a second band portion (132b-7) extending from the second connection portion (132a-7) to a part of the first surface (1). The external electrodes (131-7, 132-7) are not disposed on the second surface (2), so that the insulating layer (151-7) can cover the entire second surface (2). At this time, the external electrodes (131-7, 132-7) may not be disposed on the fifth and sixth surfaces (5, 6) either. That is, the external electrodes (131-7, 132-7) may have a form in which they are disposed only on the third, fourth, and first surfaces.

[0344] A first additional electrode layer (134) may be disposed between the first connection part (131a-7) and the third surface, and a second additional electrode layer (135) may be disposed between the second connection part (132a-7) and the fourth surface. The first connection part (131a-7) may be disposed within a range that does not extend beyond the third surface, and the second connection part (132a-7) may be disposed within a range that does not extend beyond the fourth surface.

[0346] FIG. 39 schematically illustrates a perspective view of a stacked electronic component (3000) according to one embodiment of the present invention. FIG. 40 is a cross-sectional view taken along XIV-XIV' of FIG. 39. FIG. 41 is an enlarged view of the K1 region of FIG. 40.

[0347] Referring to FIGS. 39 to 41, a stacked electronic component (3000) according to one embodiment of the present invention comprises a dielectric layer (111) and first and second internal electrodes (121, 122) alternately arranged with the dielectric layer in between, a body (110) comprising first and second surfaces facing in a first direction, third and fourth surfaces connected to the first and second surfaces and facing in a second direction, and fifth and sixth surfaces connected to the first to fourth surfaces and facing in a third direction; and a first external electrode (331) comprising a first connection portion (331a) disposed on the third surface of the body, a first band portion (331b) extending from the first connection portion to a part of the first surface, and a first corner portion (331c) extending from the first connection portion to a corner connecting the second surface and the third surface of the body. A second external electrode (332) comprising a second connection portion (332a) disposed on the fourth surface of the body, a second band portion (332b) extending from the second connection portion to a part of the first surface, and a second corner portion (332c) extending from the second connection portion to a corner connecting the second surface and the fourth surface of the body; an insulating layer (351) disposed on the first and second connection portions (331a, 332a) and disposed to cover the second surface, the first and second corner portions; a first plating layer (341) disposed on the first band portion; and a second plating layer (342) disposed on the second band portion; wherein the first and second insulating layers may comprise a silicone-based resin.

[0349] In one embodiment, when the average size in the second direction from the extension line of the third surface to the end of the first corner portion (331c) is B3, the average size in the second direction from the extension line of the fourth surface to the end of the second corner portion (332c) is B4, the average size in the second direction of the area separated from the third surface and the second internal electrode is G1, and the average size in the second direction of the area separated from the fourth surface and the first internal electrode is G2, then B3 ≤ G1 and B4 ≤ G2 can be satisfied. Accordingly, the volume occupied by the external electrodes (331, 332) can be minimized, thereby increasing the capacity per unit volume of the stacked electronic component (3000).

[0350] At this time, when the average size in the second direction from the extension line of the third surface to the end of the first band portion (331b) is denoted as B1 and the average size in the second direction from the extension line of the fourth surface to the end of the second band portion (332b) is denoted as B2, B1 ≥ G1 and B3 ≥ G2 can be satisfied. Accordingly, the bonding strength can be improved by increasing the surface area in contact with the solder during mounting.

[0352] A stacked electronic component (3000) according to one embodiment may include a dielectric layer (111) and first and second internal electrodes (121, 122) alternately arranged with the dielectric layer in between, and may include a body (110) comprising first and second surfaces facing in a first direction, third and fourth surfaces connected to the first and second surfaces and facing in a second direction, and fifth and sixth surfaces connected to the first to fourth surfaces and facing in a third direction. The body (110) of the stacked electronic component (3000) may have the same configuration as the body (110) of the stacked electronic component (1000), except that the end of the first or second surface of the body has a contracted shape as described below.

[0354] The external electrodes (331, 332) may be disposed on the third surface (3) and the fourth surface (4) of the body (110). The external electrodes (331, 332) may include first and second external electrodes (331, 332) respectively disposed on the third and fourth surfaces (3, 4) of the body (110) and connected to the first and second internal electrodes (121, 122) respectively.

[0355] The external electrodes (331, 332) may include a first external electrode (331) comprising a first connection portion (331a) disposed on a third surface, a first band portion (331b) extending from the first connection portion to a part of the first surface, and a first corner portion (331c) disposed extending from the first connection portion to a corner connecting the second surface and the third surface, and a second external electrode (132) comprising a second connection portion (332a) disposed on a fourth surface, a second band portion (332b) extending from the second connection portion to a part of the first surface, and a second corner portion (332c) disposed extending from the second connection portion to a corner connecting the second surface and the fourth surface. The first connection portion (331a) may be connected to the first internal electrode (121) on the third surface, and the second connection portion (332a) may be connected to the second internal electrode (122) on the fourth surface.

[0356] In one embodiment, the first and second connection portions (331a, 332a) may be spaced apart from the fifth and sixth surfaces. Accordingly, the proportion occupied by the external electrodes (331, 332) can be minimized, thereby making the stacked electronic component (3000) even smaller.

[0358] As the margin area where the internal electrodes (121, 122) are not placed on the dielectric layer (111) overlaps, a step difference occurs due to the thickness of the internal electrodes (121, 122), so that the corner connecting the first surface and the third to sixth surfaces and / or the corner connecting the second surface and the third to sixth surfaces may have a shape that is contracted toward the center of the first direction of the body (110) when viewed with respect to the first surface or the second surface. Alternatively, due to shrinkage behavior during the sintering process of the body, the corner connecting the first surface (1) and the third to sixth surfaces (3, 4, 5, 6) and / or the corner connecting the second surface (2) and the third to sixth surfaces (3, 4, 5, 6) may have a shape that is contracted toward the center of the first direction of the body (110) when viewed with respect to the first surface or the second surface. Alternatively, in order to prevent chipping defects, the corners connecting each face of the body (110) may be rounded by performing a separate process, so that the corner connecting the first face and the third to sixth faces and / or the corner connecting the second face and the third to sixth faces may have a round shape.

[0359] The above corner may include a 1-3 corner (c1-3) connecting the first surface and the third surface, a 1-4 corner (c1-4) connecting the first surface and the fourth surface, a 2-3 corner (c2-3) connecting the second surface and the third surface, and a 2-4 corner (c2-4) connecting the second surface and the fourth surface. Additionally, the corner may include a 1-5 corner connecting the first surface and the fifth surface, a 1-6 corner connecting the first surface and the sixth surface, a 2-5 corner connecting the second surface and the fifth surface, and a 2-6 corner connecting the second surface and the sixth surface. However, in order to suppress the step difference caused by the internal electrodes (121, 122), after lamination, the internal electrodes are cut so that they are exposed to the fifth and sixth surfaces (5, 6) of the body, and then a single dielectric layer or two or more dielectric layers are laminated in the third direction (width direction) on both sides of the capacitance forming part (Ac) to form a margin part (114, 115), the part connecting the first surface and the fifth and sixth surfaces and the part connecting the second surface and the fifth and sixth surfaces may not have a shrunken shape.

[0360] Meanwhile, the first to sixth surfaces of the body (110) may generally be flat surfaces, and the non-flat areas may be viewed as corners. Additionally, the area of ​​the external electrodes (131, 132) placed on the corner may be viewed as a corner section.

[0362] In this regard, the first and second corner portions (331c, 332c) may be positioned below the extension line (E2) of the second surface, and the first and second corner portions (331c, 332c) may be positioned spaced apart from the second surface. That is, as the external electrodes (331, 332) are not positioned on the second surface, the volume occupied by the external electrodes (331, 332) can be further minimized, thereby further increasing the capacity per unit volume of the stacked electronic component (3000). Additionally, the first corner portion (331c) may be positioned on a part of the second-third corner (C2-3) connecting the third surface and the second surface, and the second corner portion (332c) may be positioned on a part of the second-fourth corner (C2-4) connecting the fourth surface and the second surface.

[0364] The extension line (E2) of the second plane can be defined as follows.

[0365] In a length-thickness cross-section (LT cross-section) obtained by cutting a stacked electronic component (3000) at the center in the width direction, seven straight lines (P0, P1, P2, P3, P4, P5, P6, P7) in the thickness direction are drawn with equal spacing in the length direction from the third surface to the fourth surface, and the straight line passing through the point where P2 meets the second surface and the point where P4 meets the second surface can be defined as the extension line (E2) of the second surface.

[0367] Meanwhile, the external electrodes (331, 332) can be formed using any material that has electrical conductivity, such as metal, and the specific material can be determined by considering electrical properties, structural stability, etc., and furthermore, they can have a multilayer structure.

[0368] The external electrode (331, 332) may be a fired electrode including a conductive metal and glass, or a resin-based electrode including a conductive metal and resin.

[0369] Additionally, the external electrodes (331, 332) may be formed such that a sintered electrode and a resin-based electrode are sequentially formed on the body. Additionally, the external electrodes (331, 332) may be formed by transferring a sheet containing a conductive metal onto the body, or by transferring a sheet containing a conductive metal onto the sintered electrode.

[0370] The conductive metal included in the external electrodes (331, 332) may be a material with excellent electrical conductivity and is not specifically limited. For example, the conductive metal may be one or more of Cu, Ni, Pd, Ag, Sn, Cr, and their alloys. Preferably, the external electrodes (331, 332) may include one or more of Ni and Ni alloys, thereby further improving connectivity with the internal electrodes (121, 122) containing Ni.

[0372] The insulating layer (351) can be placed on the first and second connection parts (331a, 332a).

[0373] Since the first and second connection portions (331a, 332a) are parts connected to the internal electrodes (121, 122), they can become a path for the penetration of plating solution during the plating process or for moisture penetration during actual use. In the present invention, since an insulating layer (351) is disposed on the connection portions (331a, 332a), the penetration of external moisture or plating solution can be prevented.

[0374] The insulating layer (351) may be positioned to be in contact with the first and second plating layers (341, 342). At this time, the insulating layer (351) may be in contact with the first and second plating layers (341, 342) in a manner that partially covers the ends of the insulating layer (351), or the first and second plating layers (341, 342) may be in contact with the insulating layer (351) in a manner that partially covers the ends of the insulating layer (351).

[0375] The insulating layer (353) is disposed on the first and second connection portions (331a, 332a) and may be disposed to cover the second surface and the first and second corner portions (331c, 332c). Additionally, the insulating layer (351) can further improve moisture resistance reliability by covering the area where the ends of the first and second corner portions (331c, 332c) and the body (110) come into contact, thereby blocking the moisture penetration path.

[0376] The insulating layer (351) may be disposed on the second surface and extended to the first and second connection portions (331a, 332a). Additionally, if the external electrodes (331, 332) are not disposed on the second surface, the insulating layer may be disposed to cover the entire second surface. Meanwhile, the insulating layer (351) is not necessarily disposed on the second surface, and the insulating layer may not be disposed on part or all of the second surface, or the insulating layer may be separated into two parts and disposed on the first and second connection portions (331a, 332a), respectively. However, even in this case, the insulating layer may be disposed to cover the entire first and second corner portions (331c, 332c). If the insulating layer is not disposed on the entire second surface, it may be disposed below the extension line of the second surface. Additionally, although the insulating layer is not placed on the second surface, it may extend to the fifth and sixth surfaces on the first and second connecting portions (331a, 332a) to form a single insulating layer.

[0377] In one embodiment, the insulating layer (351) may be positioned to cover a portion of the fifth and sixth surfaces to improve reliability. At this time, the portion of the fifth and sixth surfaces not covered by the insulating layer may be exposed to the outside.

[0378] Furthermore, the insulating layer (351) may be arranged to cover the entirety of the fifth and sixth surfaces, in which case the fifth and sixth surfaces are not exposed to the outside, thereby further improving moisture resistance.

[0380] The insulating layer (351) can perform the role of preventing the formation of a plating layer (341, 342) on the external electrode (331, 332) on which the insulating layer (351) is disposed, and can perform the role of improving sealing characteristics to minimize the penetration of moisture or plating solution from the outside. Since the components, composition, average thickness, and resulting effects of the insulating layer (351) are the same as those of the insulating layer (151, 251, 252, 253) included in the stacked electronic component (1000, 2000) or various embodiments thereof, a description thereof will be omitted.

[0382] The first and second plating layers (341, 342) can be placed on the first and second band portions (331b, 332b), respectively. The plating layers (341, 342) can perform a role in improving mounting characteristics, and as the plating layers (341, 342) are placed on the band portions (331b, 332b), the mounting space can be minimized and reliability can be improved by minimizing the penetration of the plating solution into the internal electrode. One end of the first and second plating layers (341, 342) can be in contact with the first surface, and the other end can be in contact with the insulating layer (351).

[0383] The type of plating layer (341, 342) is not specifically limited and may be a plating layer comprising one or more of Cu, Ni, Sn, Ag, Au, Pd and alloys thereof, and may be formed in multiple layers.

[0384] As a more specific example regarding the plating layer (341, 342), the plating layer (341, 342) may be a Ni plating layer or a Sn plating layer, and may be in the form where the Ni plating layer and the Sn plating layer are sequentially formed on the first and second band portions (331b, 332b).

[0385] In one embodiment, the first plating layer (341) is positioned to cover the end of the first external electrode (331) of the insulating layer (351), and the second plating layer (342) may be positioned to cover the end of the second external electrode (332) of the insulating layer (351). Accordingly, the reliability of the stacked electronic component (3000) can be improved by strengthening the bonding strength between the insulating layer (351) and the plating layers (341, 342). Additionally, by forming the insulating layer (351) first before forming the plating layers (341, 342) on the external electrodes (331, 332), the penetration of the plating solution during the plating layer formation process can be more reliably suppressed. By forming the insulating layer before the plating layer, the plating layer (341, 342) may have a shape that covers the end of the insulating layer (351).

[0386] In one embodiment, the insulating layer (351) is positioned to cover the end positioned on the first external electrode (331) of the first plating layer (341), and the insulating layer (351) may be positioned to cover the end positioned on the second external electrode (332) of the second plating layer (342). Accordingly, the bonding strength between the insulating layer (351) and the plating layers (341, 342) can be strengthened to improve the reliability of the stacked electronic component (3000).

[0388] In one embodiment, the first and second plating layers (341, 342) may be extended and arranged to partially cover the first and second connection portions (331a, 332a), respectively. When the average size in the first direction to the internal electrode closest to the first surface (1) among the first and second internal electrodes (121, 122) is denoted as H1, and the average size in the first direction to the end of the first and second plating layers (141, 142) arranged on the first and second connection portions (131a, 132a) from the extension line of the first surface (1) is denoted as H2, H1 > H2 can be satisfied. Accordingly, the penetration of the plating solution into the internal electrode during the plating process can be suppressed, thereby improving reliability.

[0390] In an embodiment, when the average size in the first direction from the first surface to the inner electrode, which is disposed closest to the first surface among the first and second inner electrodes (121, 122), is defined as H1, and the average size in the first direction from the extension line of the first surface to the ends of the plating layers (341, 342) disposed on the first and second connection portions (331a, 332a) is defined as H2, H1<H2 may be satisfied. Accordingly, the area in contact with solder during mounting can be increased to improve the bonding strength. More preferably, when the average size of the body (110) in the first direction is defined as T, H2<T / 2 may be satisfied. That is, H1<H2<T / 2 may be satisfied. This is because when H2 is T / 2 or more, there is a concern that the effect of improving moisture resistance reliability by the insulating layer may be reduced.

[0392] In an embodiment, the first and second plating layers (341, 342) may be disposed below the extension line of the first surface. Accordingly, the height of solder during mounting can be minimized, and the mounting space can be minimized. In addition, the insulating layer (351) may extend below the extension line of the first surface and be disposed to contact the first and second plating layers (341, 342).

[0394] In an embodiment, when the average size of the body in the second direction is defined as L, the average size in the second direction from the extension line of the third surface to the end of the first band portion is defined as B1, and the average size in the second direction from the extension line of the fourth surface to the end of the second band portion is defined as B2, 0.2≤B1 / L≤0.4 and 0.2≤B2 / L≤0.4 may be satisfied.

[0395] If B1 / L and B2 / L are less than 0.2, it may be difficult to secure sufficient adhesion strength. On the other hand, if B2 / L is greater than 0.4, there is a risk that leakage current may occur between the first band portion (331b) and the second band portion (332b) under high voltage current, and there is a risk that the first band portion (331b) and the second band portion (332b) may become electrically connected due to plating bleeding during the plating process.

[0397] In one embodiment, an additional insulating layer may be further included that is disposed on the first surface and disposed between the first band portion (331b) and the second band portion (332b). Accordingly, leakage current, etc., that may occur between the first band electrode (331b) and the second band electrode (332b) under high voltage current can be prevented.

[0398] There is no need to specifically limit the type of additional insulating layer. For example, it may include components similar to those of the insulating layer (351). Meanwhile, the additional insulating layer and the insulating layer (351) do not need to be formed from the same material and may be formed from different materials. For example, the additional insulating layer may include one or more thermosetting resins selected from epoxy resin, acrylic resin, etc. In addition, the additional insulating layer may include one or more additives selected from TiO2, BaTiO3, Al2O3, SiO2, BaO, etc., in addition to the polymer resin. Accordingly, the bonding strength with the body or external electrode can be improved.

[0400] In one embodiment, when the second direction average size from the extension line of the third surface to the end of the first band portion is denoted as B1 and the second direction average size from the extension line of the fourth surface to the end of the second band portion is denoted as B2, B3 <B1 및 B4<B2를 만족할 수 있다. 제1 밴드부(331b)의 평균 길이(B1)가 제1 코너부 (331c)의 평균 길이(B3)보다 길 수 있으며, 제2 밴드부(332b)의 평균 길이가 제2 코너부(332)의 평균 길이(B4)보다 길 수 있다. 이에 따라, 실장시 솔더와 접하는 면적을 증가시켜 고착 강도를 향상시킬 수 있다.

[0401] More specifically, when the second direction average size from the extension line of the third surface (3) to the end of the first band portion (331b) is denoted as B1, the second direction average size from the extension line of the fourth surface (4) to the end of the second band portion (332b) is denoted as B2, the second direction average size from the extension line of the third surface (3) to the end of the first corner portion (331c) is denoted as B3, and the second direction average size from the extension line of the fourth surface (4) to the end of the second corner portion (332c) is denoted as B4, B3 <B1 및 B4<B2를 만족할 수 있다.

[0403] In one embodiment, the average thickness of the first and second plating layers (341, 342) may be thinner than the average thickness of the insulating layer (351).

[0404] The insulating layer (351) serves to prevent external moisture penetration or the penetration of plating solution, but its weak connectivity with the plating layer (341, 342) can cause delamination of the plating layer. When the plating layer is delaminated, the adhesion strength with the substrate may decrease. Here, delamination of the plating layer may mean that the plating layer is partially detached or physically separated from the external electrode (331, 332). Because the connectivity between the plating layer and the insulating layer is weak, there is a higher possibility that a gap will open at the interface between the insulating layer and the plating layer or that foreign substances will penetrate, and it may become vulnerable to external impacts, thereby increasing the likelihood of delamination.

[0405] According to one embodiment of the present invention, the average thickness of the plating layer can be made thinner than the average thickness of the insulating layer to reduce the contact area between the plating layer and the insulating layer, thereby suppressing the occurrence of delamination and improving the adhesion strength of the stacked electronic component (3000).

[0407] The size of the stacked electronic component (3000) does not need to be specifically limited.

[0408] However, in order to achieve both miniaturization and high capacity simultaneously, the thickness of the dielectric layer and internal electrode must be reduced to increase the number of layers, so the reliability and capacity improvement effects per unit volume according to the present invention can be more pronounced in a stacked electronic component (3000) having a size of 1005 (length × width, 1.0 mm × 0.5 mm) or less.

[0409] Accordingly, considering manufacturing error, external electrode size, etc., if the length of the stacked electronic component (3000) is 1.1 mm or less and the width is 0.55 mm or less, the reliability improvement effect according to the present invention may be more pronounced. Here, the length of the stacked electronic component (3000) refers to the maximum size in the second direction of the stacked electronic component (3000), and the width of the stacked electronic component (3000) may refer to the maximum size in the third direction of the stacked electronic component (3000).

[0411] Although embodiments of the present invention have been described in detail above, the present invention is not limited by the above-described embodiments and the attached drawings, but is intended to be limited by the appended claims. Accordingly, various substitutions, modifications, and changes may be made by those skilled in the art within the scope of the technical spirit of the present invention as described in the claims, and such are also to be considered to fall within the scope of the present invention.

[0413] Furthermore, the expression "one embodiment" as used in this disclosure does not imply identical embodiments, but is provided to emphasize distinct features of each. However, the presented one embodiment does not exclude implementation in combination with features of other one embodiments. For example, even if a matter described in a specific one embodiment is not described in another one embodiment, it may be understood as a description related to another one embodiment, provided that there is no description in another one embodiment that contradicts or conflicts with such matter.

[0414] The terms used in this disclosure are used merely to describe one embodiment and are not intended to limit this disclosure. Whereby, singular expressions include plural expressions unless the context clearly indicates otherwise. Explanation of the symbols

[0416] 1000, 2000, 3000: Stacked electronic components 1100: Mounting board for stacked electronic components 110: Body 111: Genome layer 112, 113: Cover section 114, 115: Margin 121, 122: Internal electrodes 131, 231, 331: First external electrode 132, 232, 332: Second external electrode 134, 135: Additional electrode layer 141, 142, 241, 242, 341, 342: Plating layer 151, 251, 252, 253, 351: Insulating layer 161, 261: Additional insulation layer 180: Substrate 181, 182: Electrode pads 191, 192: Solder

Claims

Claim 1 A body comprising a dielectric layer and first and second internal electrodes alternately arranged with the dielectric layer in between, and comprising first and second surfaces facing in a first direction, third and fourth surfaces connected to the first and second surfaces and facing in a second direction, and fifth and sixth surfaces connected to the first to fourth surfaces and facing in a third direction; a first external electrode comprising a first connection portion disposed on the third surface and a first band portion extending from the first connection portion to a part of the first surface; a second external electrode comprising a second connection portion disposed on the fourth surface and a second band portion extending from the second connection portion to a part of the first surface; an insulating layer disposed on the second surface and extending to a part of the first and second connection portions; and a plating layer disposed on the first and second band portions. A laminated electronic component comprising, wherein the plating layer is in contact with the insulating layer on the first and second external electrodes, and the end of the plating layer comprises a first region disposed between the insulating layer and the first and second external electrodes and a second region disposed to cover at least a portion of the insulating layer, and the end of the insulating layer extends between the first region and the second region from a portion of the inner surface of the insulating layer in contact with the first or second external electrode, and the end of the insulating layer is located further from the body than the portion of the inner surface of the insulating layer in contact with the first or second external electrode. Claim 2 A laminated electronic component according to claim 1, wherein the thickness decreases toward the end in the region of the insulating layer in contact with the insulating layer. Claim 3 In claim 1, the plating layer is a laminated electronic component in contact with the insulating layer and the first and second connection portions. Claim 4 In paragraph 3, the first region is an end region of the plating layer disposed between the insulating layer and the first and second connection portions, and the second region is an end region of the plating layer disposed to cover at least a portion of the insulating layer, and a stacked electronic component satisfying a1 > a2 when the first direction maximum length of the first region is a1 and the first direction maximum length of the second region is a2. Claim 5 In claim 1, the plating layer is a laminated electronic component in contact with the insulating layer and the first and second band portions. Claim 6 In claim 5, the first region is an end region of the plating layer disposed between the insulating layer and the first and second band portions, and the second region is an end region of the plating layer disposed to cover a part of the insulating layer, and when the second maximum length of the first region in the second direction is a3 and the second maximum length of the second region in the second direction is a4, a stacked electronic component satisfying a3 > a4. Claim 7 A stacked electronic component according to claim 1, wherein H1 is the average size in the first direction from the first surface to the internal electrode closest to the first surface among the first and second internal electrodes, and H2 is the average size in the first direction from the extension line of the first surface to the end of the plating layer disposed on the first and second connection portions, satisfying H1 ≥ H2. Claim 8 In claim 7, when the average size of the first direction of the above body is denoted as T, H2 <T / 2를 만족하는적층형 전자 부품. Claim 9 In claim 1, the first and second connecting portions are arranged spaced apart from the second surface and are stacked electronic components. Claim 10 A stacked electronic component according to claim 1, wherein L is the average size in the second direction of the body, B1 is the average size in the second direction from the extension line of the third surface to the end of the first band portion, and B2 is the average size in the second direction from the extension line of the fourth surface to the end of the second band portion, satisfying 0.2≤B1 / L≤0.4 and 0.2≤B2 / L≤0.

4. Claim 11 A stacked electronic component according to claim 1, wherein the maximum size in the second direction of the stacked electronic component is 1.1 mm or less, and the maximum size in the third direction of the stacked electronic component is 0.55 mm or less. Claim 12 A laminated electronic component according to claim 1, wherein the average thickness of the dielectric layer is 0.35 μm or less. Claim 13 A laminated electronic component according to claim 1, wherein the average thickness of the first and second internal electrodes is 0.35 μm or less. Claim 14 A stacked electronic component according to claim 1, wherein the body comprises a capacitance forming portion including first and second internal electrodes alternately arranged with the dielectric layer in between, and a cover portion disposed on both ends of the capacitance forming portion in a first direction, and the average size of the cover portion in the first direction is 15 μm or less. Claim 15 A stacked electronic component according to claim 1, wherein the first external electrode includes a third band portion extending from the first connection portion to a part of the second surface, and the second external electrode includes a fourth band portion extending from the second connection portion to a part of the second surface. Claim 16 A stacked electronic component according to claim 1, wherein the first external electrode includes a first side band portion extending from the first connection portion to a part of the fifth and sixth surfaces, and the second external electrode includes a second side band portion extending from the second connection portion to a part of the fifth and sixth surfaces. Claim 17 A laminated electronic component according to claim 1, further comprising an additional insulating layer disposed on the first surface and disposed between the first band portion and the second band portion. Claim 18 In claim 16, a stacked electronic component in which the second direction size of the first and second side band portions increases as it approaches the first surface. Claim 19 A laminated electronic component according to claim 1, wherein the insulating layer is arranged to cover the first and second side band portions, the fifth surface, and a portion of the sixth surface. Claim 20 A stacked electronic component according to claim 1, wherein the body includes a 1-3 corner connecting the first surface and the third surface, a 1-4 corner connecting the first surface and the fourth surface, a 2-3 corner connecting the second surface and the third surface, and a 2-4 corner connecting the second surface and the fourth surface, wherein the 1-3 corner and the 2-3 corner have a shape that contracts toward the center of the first direction of the body as they approach the third surface, and the 1-4 corner and the 2-4 corner have a shape that contracts toward the center of the first direction of the body as they approach the fourth surface, and the first external electrode includes a first corner portion that extends from the first connection portion onto the 1-3 corner and the 2-3 corner, and the second external electrode includes a second corner portion that extends from the second connection portion onto the 1-4 corner and the 2-4 corner. Claim 21 A stacked electronic component according to claim 20, wherein B3 is the second direction average size from the extension line of the third surface to the end of the first corner portion, B4 is the second direction average size from the extension line of the fourth surface to the end of the second corner portion, G1 is the second direction average size of the area separated from the third surface and the second internal electrode, and G2 is the second direction average size of the area separated from the fourth surface and the first internal electrode, satisfying B3≤G1 and B4≤G2. Claim 22 A stacked electronic component according to claim 1, wherein B1 is the second direction average size from the extension line of the third surface to the end of the first band portion, B2 is the second direction average size from the extension line of the fourth surface to the end of the second band portion, G1 is the second direction average size of the area separated from the third surface and the second internal electrode, and G2 is the second direction average size of the area separated from the fourth surface and the first internal electrode, satisfying B1≥G1 and B2≥G2. Claim 23 In claim 1, the average thickness of the plating layer is thinner than the thickness of the insulating layer in a laminated electronic component. Claim 24 In claim 1, the first and second connecting portions are arranged spaced apart from the fifth surface and the sixth surface, forming a stacked electronic component. Claim 25 A laminated electronic component according to claim 1, wherein the insulating layer is positioned to cover a portion of the fifth and sixth sides. Claim 26 A laminated electronic component according to claim 1, wherein the insulating layer is arranged to cover all of the fifth and sixth sides. Claim 27 A stacked electronic component according to claim 1, wherein the first external electrode comprises a first connecting electrode disposed on the third surface and a first band electrode disposed on the first surface and connected to the first connecting electrode, and the second external electrode comprises a second connecting electrode disposed on the fourth surface and a second band electrode disposed on the first surface and connected to the second connecting electrode. Claim 28 In claim 27, the first and second connecting electrodes are arranged spaced apart from the fifth surface and the sixth surface, forming a stacked electronic component. Claim 29 In claim 27, the above-mentioned first and second connecting electrodes are arranged spaced apart from the second surface, forming a stacked electronic component.

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