Controller and memory system having the controller

Abstract

The present invention includes a light queue configured to queue commands including zone IDs and light pointers in the order in which they are input; and a queue controller configured to allocate temporary buffers to the zone IDs of the commands and to store the commands output from the light queue in the temporary buffers separated according to the zone IDs, wherein the queue controller includes a controller configured to output the commands stored in the temporary buffers among the temporary buffers when a set storage size is filled.

Description

Technology Field

[0001] The present invention relates to a controller and a memory system including the same, and more specifically, to a controller that manages a storage device included in a memory system in zone units and a memory system including the same. Background Technology

[0003] The electronic system may include hosts and memory systems.

[0004] Hosts may be devices such as mobile phones or computers, and the memory system may be a system that stores data or outputs read data under the control of the hosts. The memory system may include a memory device in which data is stored and a controller that controls the memory device. Memory devices are classified into volatile memory devices and non-volatile memory devices.

[0005] Volatile memory devices are memory devices that store data only when power is supplied, and the stored data is lost when the power supply is cut off. Volatile memory devices include Static Random Access Memory (SRAM) and Dynamic Random Access Memory (DRAM).

[0006] Non-volatile memory devices are memory devices in which data is not lost even when the power is cut off, and include ROM (Read Only Memory; ROM), PROM (Programmable ROM), EPROM (Electrically Programmable ROM), EEPROM (Electrically Erasable and Programmable ROM), and Flash Memory. The problem to be solved

[0008] An embodiment of the present invention provides a controller capable of preventing the accumulation of commands by increasing the priority of commands that can be processed by each zone in a memory system that manages a storage device in zone units, and a memory system including the same. means of solving the problem

[0010] A controller according to an embodiment of the present invention comprises: a light queue configured to queue commands including zone IDs and light pointers in the order in which they are input; and a queue controller configured to allocate temporary buffers to the zone IDs of the commands and to store the commands output from the light queue in the temporary buffers separated according to the zone IDs, wherein the queue controller is configured to output the commands stored in the temporary buffer among the temporary buffers that has a set storage size filled.

[0011] A memory system according to an embodiment of the present invention comprises: a storage device including dies for storing data; and a controller configured to generate commands in response to requests output from a host and to queue the commands according to the state of the dies, wherein the controller manages the storage device by classifying the dies into zone IDs, and, during program operation, gives priority to a zone ID among the zone IDs in which all light pointers are filled regardless of the order of the queued commands, and outputs the commands assigned to the zone ID having priority.

[0012] A controller according to an embodiment of the present invention comprises: a command management unit configured to generate commands corresponding to requests received from a host, assign light pointers to the commands according to the order in which the commands are generated, and queue the commands according to the state of a storage device in which data is stored; a light queue configured to temporarily store the queued commands; temporary buffers separated by zone ID; and a zone management unit configured to store the commands output from the light queue in the temporary buffers according to the order of the zone IDs and the light pointers, and to output the commands of the temporary buffers filled with a set size. Effects of the invention

[0014] This technology can prevent the backlog of commands by increasing the priority of commands that can be processed by zone. Brief explanation of the drawing

[0016] FIG. 1 is a drawing for explaining a memory system according to an embodiment of the present invention. Figure 2 is a drawing for explaining the die shown in Figure 1. Figure 3 is a diagram for explaining the memory block illustrated in Figure 2. FIGS. 4a to 4c are drawings for explaining zones according to embodiments of the present invention. FIG. 5 is a drawing for explaining a controller according to an embodiment of the present invention. FIG. 6 is a diagram illustrating the operation of a controller according to an embodiment of the present invention. FIG. 7 is a drawing for explaining a zone management unit according to an embodiment of the present invention. FIG. 8 is a diagram illustrating the operation of a zone management unit according to an embodiment of the present invention. FIG. 9 is a drawing for explaining a memory interface according to an embodiment of the present invention. FIG. 10 is a diagram illustrating the operation of a controller accessing dies. FIGS. 11 to 18b are drawings for sequentially explaining the operation of a memory system according to a first embodiment of the present invention. FIGS. 19a and FIGS. 19b are drawings for explaining the operation of a memory system according to a second embodiment of the present invention. FIGS. 20a and FIGS. 20b are drawings for explaining the operation of a memory system according to a third embodiment of the present invention. FIG. 21 is a drawing showing a memory card system to which the controller of the present invention is applied. FIG. 22 is a drawing showing a Solid State Drive (SSD) system to which the controller of the present invention is applied. Specific details for implementing the invention

[0017] FIG. 1 is a drawing for explaining a memory system according to an embodiment of the present invention.

[0018] Referring to FIG. 1, the memory system (1000) may include a storage device (1100) capable of storing data and a controller (1200) capable of controlling the storage device (1100).

[0019] The storage device (1100) may include a plurality of dies (D01 to Dnm). The dies (D01 to Dnm) may be configured identically to each other. The dies (D01 to Dnm) may perform program, read, or erase operations in response to a command output from the controller (1200). The dies (D01 to Dnm) may be configured as non-volatile memory devices. For example, the non-volatile memory devices may include EEPROM (Electrically Erasable and Programmable ROM), NAND flash memory, NOR flash memory, PRAM (Phase-change RAM), ReRAM (Resistive RAM), FRAM (Ferroelectric RAM), STT-MRAM (Spin Transfer Torque - Magnetic RAM), etc.

[0020] The controller (1200) can communicate between the host (2000) and the storage device (1100). For example, the controller (1200) can generate a program, read, or erase command according to a request output from the host (2000) and transmit the generated command to the storage device (1100).

[0021] The host (2000) can output a program request, a write pointer, and data to the controller (1200) during program operation. The write pointer may indicate the order in which the program request is output. For example, the write pointer may have a value that increases stepwise each time a program request is output.

[0022] The controller (1200) according to the present embodiment can manage the dies (D01~Dnm) included in the storage device (1100) in zone units. For example, the controller (1200) can divide the memory blocks included in each of the dies (D01~Dnm) into logical block address units according to a certain storage capacity, and divide multiple logical block addresses into zone-unit groups. That is, multiple logical block addresses can be mapped to a single zone. The controller (1200) according to the present embodiment can be configured to output commands in zone units. Accordingly, the controller (1200) can be configured to queue and output commands by zone using a light pointer. For example, the controller (1200) can queue commands according to the state of the storage device (1100) regardless of the order of requests received from the host (2000), and can prevent the accumulation of commands by using a light pointer to re-queue the commands by zone.

[0024] FIG. 2 is a drawing for explaining the die shown in FIG. 1. Since the 01st to 01st nm dies (D01~Dnm) shown in FIG. 1 can be configured identically to each other, the 01st nm die (Dnm) among them will be explained as an example.

[0025] Referring to FIG. 2, the die (Dnm) may include at least one plane, and FIG. 2 illustrates a die (Dnm) including a plurality of planes (PL1 to PLj). The first to j-th planes (PL1 to PLj) may be configured identically to each other and may each include first to i-th memory blocks (BLK1 to BLKi). Each of the first to i-th memory blocks (BLK1 to BLKi) includes a plurality of memory cells in which data can be stored. During a program, read, or erase operation, at least one memory block among the first to i-th memory blocks (BLK1 to BLKi) included in each of the first to j-th planes (PL1 to PLj) may be selected. That is, when a program, read, or erase operation is performed on the die (Dnm), a plurality of memory blocks may be selected simultaneously. The die (Dnm) further includes peripheral circuits configured to program, read, or erase selected memory blocks included in the first to j planes (PL1 to PLj), and since the peripheral circuits can be configured in various ways depending on the die (Dnm), a specific description is omitted in this embodiment.

[0027] Figure 3 is a diagram for explaining the memory block illustrated in Figure 2.

[0028] Referring to FIG. 3, one of the multiple memory blocks (BLK1~BLKi) shown in FIG. 2, specifically memory block (BLKi), is illustrated as an example.

[0029] A memory block (BLKi) may include a plurality of strings (ST) connected between the first to m bit lines (BL1 to BLm; m is a positive integer) and a source line (SL). Each of the strings (ST) may include a source select transistor (SST), first to n memory cells (C1 to Cn), and a drain select transistor (DST) connected in series between the source line (SL) and the first to m bit lines (BL1 to BLm).

[0030] Since the memory block (BLKi) illustrated in FIG. 3 is a diagram for explaining the configuration of the memory block, the number of source select transistors (SST), first to nth memory cells (C1~Cn), and drain select transistors (DST) is not limited to the number illustrated in FIG. 3.

[0031] The gates of source select transistors (SST) connected to different strings (ST) are connected to the source select line (SSL), the gates of each of the first to nth memory cells (C1 to Cn) are connected to the first to nth word lines (WL1 to WLn), and the gates of drain select transistors (DST) can be connected to the drain select line (DSL).

[0032] A group of memory cells connected to the same word line and contained in different strings (ST) can constitute a page (PG). Program operations and read operations can be performed on a page (PG) basis.

[0034] FIGS. 4a to 4c are drawings for explaining zones according to embodiments of the present invention.

[0035] Referring to FIG. 4a, the storage device (1100) includes physically separated dies (D01~Dnm) as shown in FIG. 1 and FIG. 2, and physically separated memory blocks (BLK1~BLKi) in each of the dies (D01~Dnm), but in this embodiment, all memory blocks included in the storage device (1100) can be logically separated. All memory blocks included in the dies (D01~Dnm) can be separated by logical block address (LBA). For example, a logical block address (LBA) can be assigned to all memory blocks included in the storage device (1100). That is, first to i-th logical block addresses (LBA01~LBAi) can be mapped to the memory blocks, and memory blocks mapped to consecutive logical block addresses can be physically discontinuously arranged within the storage device (1100).

[0036] Referring to FIG. 4b, logical block addresses (LBA01~LBAi) can be grouped into multiple zones, and a zone ID (Zid) can be assigned to each zone group. That is, the zone ID (Zid) may be an index of groups formed by grouping memory blocks according to a certain storage capacity. For example, logical block addresses (LBA01~LBAi) can be divided into multiple zones classified into first to x-zone IDs (Zid01~Zidx). The storage capacity of each of the first to x-zone IDs (Zid01~Zidx) may be set to be the same or different. If the storage capacity is set to be the same, the number of logical block addresses assigned to each of the first to x-zone IDs (Zid01~Zidx) may be the same. If the storage capacity is set to be different, the number of logical block addresses assigned to the first to x-zone IDs (Zid01~Zidx) may be different. Alternatively, among the 1st to xth zone IDs (Zid01~Zidx), the storage capacity of some zone IDs may be set to be the same, and the storage capacity of the remaining zone IDs may be set differently.

[0037] Referring to FIG. 4c, the x-th zone ID (Zidx) among the first to x-th zone IDs (Zid01 to Zidx) illustrated in FIG. 4b is illustrated as an example. It is assumed that the nth to i-th logical block addresses (LBAn to LBAi) are assigned to the x-th zone ID (Zidx). A write pointer (WP) received from a host may represent a logical block address selected when storing continuous data, and a start pointer (SP) may be the first logical block address of the x-th zone ID (Zidx). For example, the write pointer may represent the order of requests transmitted by the host to the controller. Referring to FIG. 4c, LBAn, LBAn+1, LBAn+2, …, LBAi each become a write pointer (WP), and among these, the first write pointer, LBAn, becomes the start pointer (SP). Thus, the start pointers of different zone IDs may be designated as different logical block addresses.

[0039] FIG. 5 is a drawing for explaining a controller according to an embodiment of the present invention.

[0040] Referring to FIG. 5, the controller (1200) may include a zone manager (500), a system buffer (510), a command manager (520), a host interface (530), and a memory interface (540). The zone manager (500), the system buffer (510), the command manager (520), the host interface (530), and the memory interface (540) may communicate with each other via a bus.

[0041] The zone management unit (500) can adjust the queuing order of commands so that light pointers corresponding to commands are continuous in the same zone ID when light pointers corresponding to commands are discontinuous during program operation. Additionally, the zone management unit (500) can increase the output priority of the command corresponding to the zone ID when a zone ID in which all light pointers are filled occurs. For example, the zone management unit (500) can output the command corresponding to the zone ID in which all light pointers are filled with priority over the command corresponding to the zone ID in which light pointers are not filled.

[0042] The system buffer (510) may be configured to store various information necessary for the operation of the controller (1200). For example, the system buffer (510) may store mapping information for logical block addresses and physical block addresses. For example, the system buffer (510) may store a map table containing logical block addresses corresponding to write pointers and physical block addresses mapped to the logical block addresses. The physical block address is an address assigned to each of the die and memory blocks that can be managed by the storage device, and the logical block address may be an address that can be managed by the host. Thus, non-sequential physical block addresses may be mapped to sequential logical block addresses.

[0043] When a request output from the host (2000) is input to the command management unit (520), it generates a command corresponding to the request and can change the order of the commands according to the state of the storage device (1100). At this time, the commands can be queued regardless of the order of the light pointer. The queued commands can be transmitted to the zone management unit (500).

[0044] The host interface (530) can be configured to exchange requests, addresses, or data between the host (2000) and the controller (1200).

[0045] The memory interface (540) may be configured to exchange commands, addresses, or data between the controller (1200) and the storage device (1100). The memory interface (540) may include buffers capable of temporarily storing commands before outputting commands from the zone management unit (500) to the storage device (1100). The memory interface (540) may receive physical block addresses corresponding to each light pointer output from the zone management unit (500) from the system buffer (510) and output commands and physical block addresses to the storage device (1100).

[0047] FIG. 6 is a diagram illustrating the operation of a controller according to an embodiment of the present invention.

[0048] Referring to FIG. 6, when the command management unit (520) receives requests (RQ#) and light pointers (WP#) output from the host, it generates commands (CMD#) to execute the requests (RQ#) and can adjust the execution order of the commands (CMD#) according to the operating status of the dies on which the commands (CMD#) are to be executed. That is, the command management unit (520) can queue commands (CMD#) according to the operating status of the dies included in the storage device regardless of the order of the light pointers (WP#). For example, the command management unit (520) can identify idle dies and dies in operation and change the execution order of the commands so that the priority of commands that can be executed on idle dies is increased. In addition to this, the command management unit (520) can change the execution order of the commands in various ways.

[0049] The zone management unit (500) can temporarily store commands (CMD#) output from the command management unit (520) and reorder the commands (CMD#) according to the zone ID (Zid) and light pointers (WP#). When a zone ID (Zid) occurs in which all commands (CMD#) corresponding to the set write size are filled, the zone management unit (500) can transmit the commands (CMD#) of the zone ID (Zid) to the memory interface (540). Here, the commands (CMD#) may be program commands.

[0050] The memory interface (540) may include a plurality of output buffers (B1 to Bp) for storing commands (CMD) output from the zone management unit (500) by zone ID (Zid#). For example, the output buffers (B1 to Bp) may correspond 1:1 to the zone IDs (Zid#). The memory interface (540) may output physical block addresses (PBA#) corresponding to the write pointers (WP#) and commands (CMD#) to the die corresponding to the zone ID (Zid#).

[0052] FIG. 7 is a drawing for explaining a zone management unit according to an embodiment of the present invention.

[0053] Referring to FIG. 7, the zone management unit (500) may include a write queue (710) and a queue controller (720).

[0054] The light queue (710) may include a queue buffer (711) for temporarily storing commands (CMD#) output from the command management unit (520 in FIG. 6) and zone IDs and light pointers corresponding to each command (CMD#). The order of zone IDs and light pointers of the commands (CMD#) input into the queue buffer (711) may be discontinuous.

[0055] The queue controller (720) may include temporary buffers (721) for storing commands (CMD#) output from the light queue (710) according to zone ID and light pointer. The queue controller (720) may sequentially store commands (CMD#) in the temporary buffers (721) according to zone ID and light pointer. When a temporary buffer is filled to the set size, the queue controller (720) may output the commands (CMD#) stored in the temporary buffer.

[0057] FIG. 8 is a diagram illustrating the operation of a zone management unit according to an embodiment of the present invention.

[0058] Referring to FIG. 8, when commands (CMD#) are input, the zone management unit (500) can store the commands (CMD#), zone IDs (Zid#) and light pointers (WP#) corresponding to the commands (CMD#) in the queue buffer (711) in the order in which they are input. For example, it is assumed that memory blocks included in a storage device are logically divided into five zones, five zone IDs are set, and at least one light pointer is assigned to each zone ID. That is, the zone ID (Zid#) may include first to fifth zone IDs (Zid1~Zid5), and different light pointers (WP#) may be assigned to each of the first to fifth zone IDs (Zid1~Zid5).

[0059] In FIG. 8, the numbers of the commands in the queue buffer (711) indicate the order in which they were entered into the queue buffer (711). For example, the first command (CMD01) represents the first command entered into the queue buffer (711). The first command (CMD01) may be assigned a first zone ID (Zid1) and a first light pointer (WP01). In this way, the first to 23 commands (CMD01 to CMD23) may be entered sequentially into the queue buffer (711). However, the light pointers assigned to the first to 23 commands (CMD01 to CMD23) are discontinuous, unlike the order in which the commands were entered. This means that the order of the commands requested by the host has been changed. For example, since the first to fourth light pointers (WP01 to WP04) are assigned to the first to fourth commands (CMD01 to CMD04), the order of the first to fourth commands (CMD01 to CMD04) is the same as the order requested by the host. Since the eighth light pointer (WP08) is assigned to the fifth command (CMD05) entered after the fourth command (CMD04), the fifth command (CMD05) is discontinuous with the fourth command (CMD04), which indicates that the fifth command (CMD05) is different from the order requested by the host.

[0060] The queue controller (720) can store commands (CMD#) output from the light queue (710) in temporary buffers (TB1 to TB5) separated by zone ID (Zid#). For example, each of the first to fifth temporary buffers (TB1 to TB5) may include sub-buffers for storing a set number of commands (CMD#). For example, if the first temporary buffer (TB1) is allocated a larger storage capacity than the second to fifth temporary buffers (TB2 to TB5), the first temporary buffer (TB1) may include a first_1 temporary buffer (TB1_1) and a first_2 temporary buffer (TB1_2). The first temporary buffer (TB1_1) and the first temporary buffer (TB1_2) can be assigned to the first zone ID (Zid1), and the second to fifth temporary buffers (TB2~TB5) can be assigned to the second to fifth zone IDs (Zid2~Zid5), respectively. The queue controller (720) can select a temporary buffer according to the zone ID (Zid#) of the command (CMD#) stored in the queue buffer (711), select one sub-buffer among the sub-buffers included in the selected temporary buffer according to the light pointer (WP#) of the command (CMD#), and then store the command (CMD#) in the selected sub-buffer.

[0061] For example, if the start pointer (SP) of the first_1 temporary buffer (TB1_1) is set to 01 and the start pointer (SP) of the first_2 temporary buffer (TB_1_2) is set to 06, the first_1 temporary buffer (TB1_1) may store the first, second, third, fourth, and seventh commands (CMD01, CMD02, CMD03, CMD04, CMD07) to which the first to fifth light pointers (WP01~WP05) are assigned, and the first_2 temporary buffer (TB1_2) may store the eighth, ninth, fifth, sixth, and twelfth commands (CMD08, CMD09, CMD05, CMD06, CMD12) to which the sixth to tenth light pointers (WP06~WP10) are assigned. Here, the first subbuffer of the first_1 temporary buffer (TB1_1) is assigned a first light pointer (WP01) designated as a start pointer (SP) 01, so the first subbuffer stores the first command (CMD01) assigned to the first light pointer (WP01), and the first subbuffer of the first_2 temporary buffer (TB1_2) stores the eighth command (CMD08) assigned to the sixth light pointer (WP06) designated as a start pointer (SP) 06.

[0062] For example, when the 10th command (CMD10) stored in the queue buffer (711) is output from the write queue (710), the 10th command (CMD10) is assigned a 3rd zone ID (Zid3) and a 16th write pointer (WP16), so the 3rd temporary buffer (TB3) to which the 3rd zone ID (Zid3) is assigned can be selected among the 1st to 5th temporary buffers (TB1 to TB5). Since the start pointer (SP) of the 3rd temporary buffer (TB3) is 16, the 10th command (CMD10) to which the 16th write pointer (WP16) is assigned can be stored in the sub-buffer corresponding to the start pointer (SP) 16.

[0063] The first to 23 commands (CMD01~CMD23) temporarily stored in the queue buffer (711) in the manner described above can be stored in temporary buffers (721) according to the zone ID and light pointer.

[0064] The queue controller (720) can output commands stored in a temporary buffer when a temporary buffer is created in which all sub-buffers among the first to fifth temporary buffers (TB1 to TB5) are filled with commands. For example, when the first, second, third, fourth, and seventh commands (CMD01, CMD02, CMD03, CMD04, CMD07), for which the first to fifth light pointers (WP01 to WP05) are assigned, are all stored in the sub-buffers included in the first_1 temporary buffer (TB1_1), the queue controller (720) can output the first, second, third, fourth, and seventh commands (CMD01, CMD02, CMD03, CMD04, CMD07) stored in the first_1 temporary buffer (TB1_1). That is, the first, second, third, fourth, and seventh commands (CMD01, CMD02, CMD03, CMD04, CMD07) can be rearranged according to the first to fifth light pointers (WP01~WP05) in the order requested by the host. When all eighth, ninth, fifth, sixth, and twelfth commands (CMD08, CMD09, CMD05, CMD06, CMD12), to which the sixth to tenth light pointers (WP06~WP10) are assigned, are stored in the sub-buffers contained in the first_2 temporary buffer (TB1_2), the queue controller (720) can output the eighth, ninth, fifth, sixth, and twelfth commands (CMD08, CMD09, CMD05, CMD06, CMD12) stored in the first_2 temporary buffer (TB1_2). When all commands (CMD#) are stored in the second and third temporary buffers (TB2, TB3) in this way, the queue controller (720) can output the commands in the temporary buffer that were filled first.

[0065] If the commands (CMD#) in the fourth and fifth temporary buffers (TB4, TB5) are not all filled, the queue controller (720) can hold the output of the commands (CMD#) stored in the fourth and fifth temporary buffers (TB4, TB5) until the commands (CMD#) are all filled. For example, if the 21st to 25th light pointers (WL21~WP25) are allocated to the fourth temporary buffer (TB4), and among them only the 23rd and 18th commands (CMD23, ​​CMD18) corresponding to the 21st and 22nd light pointers (WP21, WP22) are stored, then since the commands (CMD#) allocated to the remaining 23rd to 25th light pointers (WP23~WP25) are not stored, continuous data cannot be programmed into the memory areas mapped to the fourth zone ID (Zid4). Therefore, the queue controller (720) can delay the output of commands until all commands are filled in the fourth temporary buffer (TB4).

[0066] The queue controller (720) can output the commands stored in the fifth temporary buffer (TB5) if the fifth temporary buffer (TB5) is filled with commands before the fourth temporary buffer (TB4).

[0068] FIG. 9 is a drawing for explaining a memory interface according to an embodiment of the present invention.

[0069] Referring to FIGS. 9 and FIGS. 8, the memory interface (540) may include first to fifth output buffers (B1 to B5) distinguished by first to fifth zone IDs (Zid1 to Zid5). The first output buffer (B1) may store first to fifth physical block addresses (PBA01 to PBA05) each mapped to first to fifth light pointers (WP01 to WP05). The first to fifth physical block addresses (PBA01 to PBA05) may be information searched from the system buffer (510 in FIG. 5) by the command management unit (520 in FIG. 5).

[0070] When a first zone ID (Zid1) is assigned to a first output buffer (B1) in the memory interface (540), the physical block addresses (PBA#) of the light pointers (WP01~WP05 or WP06~WP10) assigned to the commands (CMD) output from the first_1 temporary buffer (TB1_1) or the first_2 temporary buffer (TB1_2) may be temporarily stored in the first output buffer (B1) and then output. The memory interface (540) may store the first to fifth physical block addresses (PBA01~PBA05) mapped to the first to fifth light pointers (WP01~WP05) respectively, and then transmit the command (CMD) to the dies included in the storage device according to the first zone ID (Zid1) and the first to fifth physical block addresses (PBA01~PBA05).

[0071] Since some commands are not stored in temporary buffers such as the fourth and fifth temporary buffers (TB4, TB5), the stored commands are not output, so even if commands assigned to the 21st, 22nd, or 26th write pointers (WP21, WP22, or WP26) are stored in the fourth and fifth temporary buffers (TB4, TB5), physical block addresses (PBA#) are not stored in the fourth output buffer (B4) corresponding to the fourth temporary buffer (TB4) and the fifth output buffer (B5) corresponding to the fifth temporary buffer (TB5).

[0073] FIG. 10 is a diagram illustrating the operation of a controller accessing dies.

[0074] Referring to FIG. 10, the controller (1200) can transmit physical block addresses (PBA#) and a command (CMD) to selected dies according to the physical block addresses (PBA#) stored in the memory interface (540) and the zone ID (Zid#) corresponding to the physical block addresses (PBA#).

[0075] Based on the above explanation, the method by which the Zone Management Department rearranges the output order of commands is specifically described as follows.

[0077] FIGS. 11 to 18b are drawings for sequentially explaining the operation of a memory system according to a first embodiment of the present invention.

[0078] Referring to FIG. 11, when commands (CMD#) are input into the light queue (710), the light queue (710) can store the commands (CMD#), the zone IDs (Zid1~Zid5) assigned to the commands (CMD#), and the light pointers (WP01~WP25) in the order in which they were input into the queue buffer (711). In the first embodiment, the case where the first to 22nd commands (CMD01~CMD22) are input is described as an example, but if there is an empty area in the queue buffer (711), the commands (CMD#) may continue to be input. The first to 22nd commands (CMD01~CMD22) may all be program commands, and the numbers '01~22' of the commands (CMD#) indicate the order in which the commands (CMD#) were input.

[0079] Since the first zone ID (Zid1) and the first to fourth light pointers (WP01 to WP04) are assigned to the first to fourth commands (CMD01 to CMD04), the first temporary buffer (TB1) corresponding to the first zone ID (Zid1) can be selected among the temporary buffers (721). The first temporary buffer (TB1) may include the first_1 and first_2 temporary buffers (TB1_1, TB1_2). Since the start pointer (SP) of the first temporary buffer (TB1_1) is 01, the first command (CMD01) assigned to the first light pointer (WP01) is input into the first sub-buffer of the first temporary buffer (TB1_1), and the second, third, and fourth commands (CMD02, CMD03, CMD04) assigned to the second to fourth light pointers (WP02~WP04) respectively can be input sequentially into the remaining sub-buffers.

[0080] Referring to FIG. 12, the 5th command (CMD05), which is entered after the 4th command (CMD04), is assigned the 1st zone ID (Zid1), but the order of the light pointers is discontinuous because it is the 8th light pointer (WP08) rather than the 5th light pointer (WP05). Therefore, the queue controller (720) can input the 5th command (CMD05), in which the 8th light pointer (WP08) is assigned, into the third sub-buffer of the 1st_2 temporary buffer (TB1_2), where the start pointer (SP) is 06. Since the 6th command (CMD06), in which the 9th light pointer (WP09) of the 1st zone ID (Zid1) is assigned, is entered after the 8th light pointer (WP08), the 6th command (CMD06), in which the 9th light pointer (WP09) is assigned, can be input into the fourth sub-buffer of the 1st_2 temporary buffer (TB1_2).

[0081] Referring to FIG. 13a, the order of light pointers is discontinuous because the 5th light pointer (WP05) of the 1st zone ID (Zid1) is assigned to the 7th command (CMD07) that is entered after the 6th command (CMD06). Accordingly, the queue controller (720) can input the 7th command (CMD07) in which the 5th light pointer (WP05) is assigned to the 5th sub-buffer in the 1_1 temporary buffer (TB1_1). Accordingly, all sub-buffers of the 1_1 temporary buffer (TB1_1) can be filled with the 1st, 2nd, 3rd, 4th, and 7th commands (CMD01, CMD02, CMD03, CMD04, CMD07) in which the 1st to 5th light pointers (WP01~WP05) are respectively assigned. Since all five sub-buffers, which are storage sizes capable of programming continuous data, are filled, the queue controller (720) can output the first, second, third, fourth, and seventh commands (CMD01, CMD02, CMD03, CMD04, CMD07) to which the first zone ID (Zid1) and the first to fifth light pointers (WP01~WP05) are assigned. In this embodiment, the storage sizes capable of programming continuous data are described as five, but since this is an example to explain this embodiment, the storage sizes may be changed depending on the memory system. Since the sub-buffers of the first_2 temporary buffer (TB1_2) are not completely filled with commands, when the first, second, third, fourth, and seventh commands (CMD01, CMD02, CMD03, CMD04, CMD07) assigned to the first to fifth light pointers (WP01~WP05) in the first_1 temporary buffer (TB1_1) are output, the fifth and sixth commands (CMD05, CMD06) assigned to the eighth and ninth light pointers (WP08, WP09) in the first_2 temporary buffer (TB1_2) are not output.

[0082] Referring to FIG. 13b, commands (CMD) for a first zone ID (Zid1) output from a zone management unit (500) can be transmitted to a memory interface (540). The memory interface (540) can store first to fifth physical block addresses (PBA01~PBA05) mapped to first to fifth light pointers (WP01~WP05) in a first output buffer (B1) corresponding to the first zone ID (Zid1), and transmit the first to fifth physical block addresses (PBA01~PBA05) and commands (CMD) to a storage device (1100). The storage device (1100) can perform program operations according to the physical block addresses (PBA#) and commands (CMD) on dies corresponding to the zone ID.

[0083] Referring to FIG. 14, the first, second, third, fourth, and seventh commands (CMD01, CMD02, CMD03, CMD04, CMD07) stored in the first_1 temporary buffer (TB1_1) have been output (see FIG. 13a), so the first_1 temporary buffer (TB1_1) can be emptied. Since the first zone ID (Zid1) and the sixth light pointer (WP06) are assigned to the eighth command (CMD08) that is input after the seventh command (CMD07), the queue controller (720) can input the eighth command (CMD08), in which the sixth light pointer (WP06) is assigned to the first sub-buffer in the first_2 temporary buffer (TB1_2) where the start pointer (SP) is 06. Since the 9th command (CMD09) entered after the 8th command (CMD08) is assigned the 1st zone ID (Zid1) and the 7th light pointer (WP07), the 9th command (CMD09) assigned the 7th light pointer (WP07) can be entered into the second sub-buffer of the 1_2 temporary buffer (TB1_2).

[0084] Referring to FIG. 15, the 10th command (CMD10), which is entered after the 9th command (CMD09), is assigned the 3rd zone ID (Zid3) and the 16th light pointer (WP16), so the queue controller (720) can input the 10th command (CMD10), in which the 16th light pointer (WP16) is assigned, into the first sub-buffer of the 3rd temporary buffer (TB3), in which the start pointer (SP) is 16. Since the 17th light pointer (WP17) of the 3rd zone ID (Zid3) is queued after the 16th light pointer (WP16), the 11th command (CMD11), in which the 17th light pointer (WP17) is assigned, can be input into the second sub-buffer of the 3rd temporary buffer (TB3).

[0085] Referring to FIG. 16a, the 12th command (CMD12) entered after the 11th command (CMD11) is assigned the 10th light pointer (WP10) of the 1st zone ID (Zid1), so the queue controller (720) can input the 12th command (CMD12) with the 10th light pointer (WP10) assigned to it into the fifth sub-buffer of the 1_2 temporary buffer (TB1_2). Accordingly, the 8th, 9th, 5th, 6th, and 12th commands (CMD08, CMD09, CMD05, CMD06, CMD12) with the 6th to 10th light pointers (WP06~WP10) assigned to them can be filled into all sub-buffers of the 1_2 temporary buffer (TB1_2). Since all five sub-buffers, which are storage sizes capable of programming continuous data, are filled, the queue controller (720) can output the 8th, 9th, 5th, 6th, and 12th commands (CMD08, CMD09, CMD05, CMD06, CMD12) to which the 6th to 10th light pointers (WP06~WP10) are assigned in the 1st zone ID (Zid1).

[0086] Referring to FIG. 16b, the 8th, 9th, 5th, 6th, and 12th commands (CMD08, CMD09, CMD05, CMD06, CMD12) for the 1st zone ID (Zid1) output from the zone management unit (500) can be transmitted to the memory interface (540). The memory interface (540) stores the 6th to 10th physical block addresses (PBA06~PBA10) mapped to the 6th to 10th light pointers (WP06~WP10) assigned to the 8th, 9th, 5th, 6th, and 12th commands (CMD08, CMD09, CMD05, CMD06, CMD12) in the 1st output buffer (B1) corresponding to the 1st zone ID (Zid1), and can transmit the 8th, 9th, 5th, 6th, and 12th commands (CMD08, CMD09, CMD05, CMD06, CMD12) to the storage device (1100) according to the 6th to 10th physical block addresses (PBA06~PBA10). The storage device (1100) can perform a program operation according to the physical block addresses (PBA#) and the 8th, 9th, 5th, 6th, and 12th commands (CMD08, CMD09, CMD05, CMD06, CMD12) on the dies corresponding to the zone ID.

[0087] Referring to FIG. 16c, when the 8th, 9th, 5th, 6th, and 12th commands (CMD08, CMD09, CMD05, CMD06, CMD12) are filled with 6th to 10th light pointers (WP06~WP10) assigned to all sub-buffers of the 1st_2 temporary buffer (TB1_2) but the 1st output buffer (B1) of the memory interface (540) is not emptied, the zone management unit (500) can delay the output of the 8th, 9th, 5th, 6th, and 12th commands (CMD08, CMD09, CMD05, CMD06, CMD12). For example, if the first to fifth physical block addresses (PBA01~PBA05) corresponding to previous commands are stored in the first output buffer (B1) of the memory interface (540), the zone management unit (500) can delay the output of the eighth, ninth, fifth, sixth, and twelfth commands (CMD08, CMD09, CMD05, CMD06, CMD12) to which the sixth to tenth write pointers (WP06~WP10) are assigned until the first output buffer (B1) is reset. When the first output buffer (B1) is reset, the zone management unit (500) can output the 8th, 9th, 5th, 6th, and 12th commands (CMD08, CMD09, CMD05, CMD06, CMD12) to which the 6th to 10th light pointers (WP06~WP10) are assigned.

[0088] Referring to FIG. 17a, the 8th, 9th, 5th, 6th, and 12th commands (CMD08, CMD09, CMD05, CMD06, CMD12) stored in the 1st_2nd temporary buffer (TB1_2) have been output (see FIG. 16a), so the 1st_2nd temporary buffer (TB1_2) can be emptied. Since the 13th to 17th commands (CMD13~CMD17) entered after the 12th command (CMD12) have the 2nd zone ID (Zid2) and the 11th to 15th light pointers (WP11~WP15) assigned to them, the queue controller (720) can sequentially input the 13th, 14th, 15th, 16th, and 17th commands (CMD13, CMD14, CMD15, CMD16, CMD17) in which the 11th to 15th light pointers (WP11~WP15) are assigned to the sub-buffers of the 2nd temporary buffer (TB2) in which the start pointer (SP) is 11. Accordingly, the 13th, 14th, 15th, 16th, and 17th commands (CMD13, CMD14, CMD15, CMD16, CMD17), to which the 11th to 15th light pointers (WP11~WP15) are assigned, can be filled into all sub-buffers of the second temporary buffer (TB2). Since all five sub-buffers, which are storage sizes capable of programming continuous data, are filled, the queue controller (720) can output the 13th, 14th, 15th, 16th, and 17th commands (CMD13, CMD14, CMD15, CMD16, CMD17), to which the 11th to 15th light pointers (WP11~WP15) are assigned, from the second zone ID (Zid2).

[0089] Referring to FIG. 17b, the 13th, 14th, 15th, 16th, and 17th commands (CMD13, CMD14, CMD15, CMD16, CMD17) to which the 2nd zone ID (Zid2) output from the zone management unit (500) and the 11th to 15th light pointers (WP11~WP15) are assigned can be transmitted to the memory interface (540). The memory interface (540) can store the 11th to 15th physical block addresses (PBA11~PBA15) mapped to the 11th to 15th light pointers (WP11~WP15) in the second output buffer (B2) corresponding to the second zone ID (Zid2), and transmit the 13th, 14th, 15th, 16th, and 17th commands (CMD13, CMD14, CMD15, CMD16, CMD17) to the storage device (1100) according to the 11th to 15th physical block addresses (PBA11~PBA15). The storage device (1100) can perform a program operation according to the physical block addresses (PBA#) and the 13th, 14th, 15th, 16th, and 17th commands (CMD13, CMD14, CMD15, CMD16, CMD17) on the dies corresponding to the zone ID.

[0090] Referring to FIG. 18a, the 18th to 22nd commands (CMD18~CMD22) entered after the 17th command (CMD17) are assigned the 4th zone ID (Zid4) and the 21st to 25th light pointers (WP21~WP25), so the queue controller (720) can sequentially input the 18th, 19th, 20th, 21st, and 22nd commands (CMD18, CMD19, CMD20, CMD21, CMD22) in which the 21st to 25th light pointers (WP21~WP25) are assigned to the sub-buffers of the 4th temporary buffer (TB4) where the start pointer (SP) is 21. Accordingly, the 18th, 19th, 20th, 21st, and 22nd commands (CMD18, CMD19, CMD20, CMD21, CMD22), to which the 21st to 25th light pointers (WP21~WP25) are assigned, can be filled into all sub-buffers of the 4th temporary buffer (TB4). Since all five sub-buffers, which are storage sizes capable of programming continuous data, are filled, the queue controller (720) gives priority to the 4th zone ID (Zid4) over the 3rd zone ID (Zid3) and can output the 18th, 19th, 20th, 21st, and 22nd commands (CMD18, CMD19, CMD20, CMD21, CMD22), to which the 4th zone ID (Zid4), having higher priority, is assigned.

[0091] Referring to FIG. 18b, the 18th, 19th, 20th, 21st, and 22nd commands (CMD18, CMD19, CMD20, CMD21, CMD22) to which the 4th zone ID (Zid4) output from the zone management unit (500) and the 21st to 25th light pointers (WP21~WP25) are assigned can be transmitted to the memory interface (540). The memory interface (540) can store the 21st to 25th physical block addresses (PBA21~PBA25) mapped to the 21st to 25th light pointers (WP21~WP25) in the 4th output buffer (B4) corresponding to the 4th zone ID (Zid4), and can transmit the 18th, 19th, 20th, 21st, and 22nd commands (CMD18, CMD19, CMD20, CMD21, CMD22) according to the 21st to 25th physical block addresses (PBA21~PBA25) to the storage device (1100). The storage device (1100) can perform a program operation according to the physical block addresses (PBA#) and commands (CMD) on the die corresponding to the zone ID.

[0093] FIGS. 19a and FIGS. 19b are drawings for explaining the operation of a memory system according to a second embodiment of the present invention.

[0094] Referring to FIG. 19a, the zone management unit (500) may wait without outputting the light pointers (WP#) until an output request is received from the host (2000), even if a temporary buffer is filled with all commands. For example, when the first_1, first_2, second, and fourth temporary buffers (TB1_1, TB1_2, TB2, TB4) are all filled with commands, the zone management unit (500) may check whether an output request has been received from the host (2000). If no output request has been received, the zone management unit (500) may hold the output of the commands.

[0095] Referring to FIG. 19b, when the host (2000) outputs an output request (RQ_out), the zone management unit (500) can output commands (CMD) stored in the first_1, first_2, second and fourth temporary buffers (TB1_1, TB1_2, TB2, TB4) in response to the output request (RQ_out).

[0097] FIGS. 20a and FIGS. 20b are drawings for explaining the operation of a memory system according to a third embodiment of the present invention.

[0098] Referring to FIG. 20a, some light pointers may include a control key (CON_KEY). The control key (CON_KEY) may be an index that designates a light pointer that can be output only upon an output request from the host (2000). The control key (CON_KEY) may be designated by the host (2000) or by the command management unit (520 in FIG. 5) included in the controller. Thus, normal light pointers may consist only of a logical block address (LBA), and light pointers selected by the host (2000) or the command management unit (520) may consist of a control key (CON_KEY) and a logical block address (LBA).

[0099] When a temporary buffer is filled with all commands, the zone management unit (500) can immediately output the commands contained in the temporary buffer, but can hold the output of commands until an output request is received from the host (2000) in a temporary buffer containing light pointers with a control key (CON_KEY) set. For example, when commands are filled in the first_1, first_2, second, and fourth temporary buffers (TB1_1, TB1_2, TB2, TB4), the zone management unit (500) can check whether there is a command assigned to a light pointer with a control key (CON_KEY) set among the commands stored in the first_1, first_2, second, and fourth temporary buffers (TB1_1, TB1_2, TB2, TB4). If the zone management unit (500) determines that only commands assigned to normal light pointers are stored in the second and fourth temporary buffers (TB2, TB4), it can immediately output the commands (CMD) stored in the second and fourth temporary buffers (TB2, TB4). If the zone management unit (500) determines that among the commands assigned to light pointers (WP01~WP10) stored in the first_1 and first_2 temporary buffers (TB1_1, TB1_2), commands assigned to light pointers (WP03~WP06) with a control key (CON_KEY) set are stored, it can check whether an output request has been received from the host (2000). If there is no received output request, the zone management unit (500) can hold the output of commands (CMD) to which the first_1 and first_2 temporary buffers (TB1_1, TB1_2) are stored and light pointers (WP01~WP10) are assigned.

[0100] Referring to FIG. 20b, when the host (2000) outputs an output request (RQ_out), the zone management unit (500) can output commands (CMD) stored in the first_1 and first_2 temporary buffers (TB1_1, TB1_2) in response to the output request (RQ_out).

[0102] FIG. 21 is a drawing showing a memory card system to which the controller of the present invention is applied.

[0103] Referring to FIG. 21, the memory card system (3000) includes a controller (3100), a memory device (3200), and a connector (3300).

[0104] The controller (3100) is connected to the memory device (3200). The controller (3100) is configured to access the memory device (3200). For example, the controller (3100) may be configured to control program, read, or erase operations of the memory device (3200), or to control background operations. The controller (3100) may be configured in the same way as the controller (1200) shown in FIG. 5. The controller (3100) is configured to provide an interface between the memory device (3200) and the host. The controller (3100) is configured to run firmware for controlling the memory device (3200).

[0105] For example, the controller (3100) may include components such as RAM (Random Access Memory), a processing unit, a host interface, a memory interface, and an error correction unit.

[0106] The controller (3100) can communicate with an external device through a connector (3300). The controller (3100) can communicate with an external device (e.g., a host) according to a specific communication standard. For example, the controller (3100) is configured to communicate with an external device through at least one of various communication standards such as USB (Universal Serial Bus), MMC (multimedia card), eMMC (embedded MMC), PCI (peripheral component interconnection), PCI-E (PCI-express), ATA (Advanced Technology Attachment), Serial-ATA, Parallel-ATA, SCSI (small computer system interface), ESDI (enhanced small disk interface), IDE (Integrated Drive Electronics), Firewire, UFS (Universal Flash Storage), WIFI, Bluetooth, NVMe, etc. For example, the connector (3300) may be defined by at least one of the various communication standards described above.

[0107] For example, the memory device (3200) may be composed of various non-volatile memory devices such as EEPROM (Electrically Erasable and Programmable ROM), NAND flash memory, NOR flash memory, PRAM (Phase-change RAM), ReRAM (Resistive RAM), FRAM (Ferroelectric RAM), STT-MRAM (Spin Transfer Torque - Magnetic RAM), etc.

[0108] The controller (3100) and the memory device (3200) can be integrated into a single semiconductor device to form a memory card. For example, the controller (3100) and the memory device (3200) can be integrated into a single semiconductor device to form a memory card such as a PC card (PCMCIA, Personal Computer Memory Card International Association), Compact Flash Card (CF), Smart Media Card (SM, SMC), Memory Stick, Multimedia Card (MMC, RS-MMC, MMCmicro, eMMC), SD Card (SD, miniSD, microSD, SDHC), Universal Flash Storage (UFS), etc.

[0110] FIG. 22 is a drawing showing a Solid State Drive (SSD) system to which the controller of the present invention is applied.

[0111] Referring to FIG. 22, the SSD system (4000) includes a host (4100) and an SSD (4200). The SSD (4200) transmits and receives signals with the host (4100) through a signal connector (4001) and receives power through a power connector (4002). The SSD (4200) includes a controller (4210), a plurality of flash memories (4221 to 422n), an auxiliary power supply (4230), and a buffer memory (4240).

[0112] According to an embodiment of the present invention, the controller (4210) can perform the function of the controller (1200) described with reference to FIG. 5.

[0113] The controller (4210) can control a plurality of flash memories (4221 to 422n) in response to a signal received from the host (4100). For example, the signal may be a signal based on an interface between the host (4100) and the SSD (4200). For example, the signal may be a signal defined by at least one of interfaces such as USB (Universal Serial Bus), MMC (multimedia card), eMMC (embedded MMC), PCI (peripheral component interconnection), PCI-E (PCI-express), ATA (Advanced Technology Attachment), Serial-ATA, Parallel-ATA, SCSI (small computer system interface), ESDI (enhanced small disk interface), IDE (Integrated Drive Electronics), Firewire, UFS (Universal Flash Storage), WIFI, Bluetooth, NVMe, etc.

[0114] The auxiliary power supply unit (4230) is connected to the host (4100) via a power connector (4002). The auxiliary power supply unit (4230) receives power voltage from the host (4100) and can charge. The auxiliary power supply unit (4230) can provide power voltage to the SSD (4200) when power supply from the host (4100) is not smooth. For example, the auxiliary power supply unit (4230) may be located inside the SSD (4200) or outside the SSD (4200). For example, the auxiliary power supply unit (4230) may be located on the main board and provide auxiliary power to the SSD (4200).

[0115] The buffer memory (4240) operates as a buffer memory of the SSD (4200). For example, the buffer memory (4240) may temporarily store data received from the host (4100) or data received from a plurality of flash memories (4221 to 422n), or may temporarily store metadata (e.g., mapping tables) of the flash memories (4221 to 422n). The buffer memory (4240) may include volatile memory such as DRAM, SDRAM, DDR SDRAM, LPDDR SDRAM, etc., or non-volatile memory such as FRAM, ReRAM, STT-MRAM, PRAM, etc. Explanation of the symbols

[0117] 1000: Memory System 1100: Storage Device 1200: Controller 2000: Host 500: Zone Management Department 510: System Buffer 520: Command Management Section 530: Host Interface 540: Memory Interface 710: Light Queue 711: Queue buffer 720: Queue controller 721: Temporary buffers

Claims

Claim 1 A light queue configured to queue commands including zone IDs and light pointers in the order in which they are input; and a queue controller configured to allocate temporary buffers to the zone IDs of the commands and to store the commands output from the light queue in the temporary buffers separated according to the zone IDs, wherein the queue controller is configured to output the commands stored in the temporary buffers among the temporary buffers that have a set storage size filled. Claim 2 In claim 1, the zone IDs are indices assigned to memory regions separated by consecutive logical block addresses, and the light pointers are logical block addresses selected after the logical block address selected within the selected zone ID, in a controller. Claim 3 In claim 1, the light queue is a controller comprising a queue buffer configured to temporarily store the commands. Claim 4 In claim 1, the queue controller is configured to select the temporary buffer according to the zone ID of the commands output from the light queue, and to store the commands in the selected temporary buffer according to the order of the light pointers. Claim 5 In paragraph 4, each of the above temporary buffers is a controller comprising sub-buffers for storing the commands according to the light pointer. Claim 6 A controller in which, in paragraph 5, a command is stored in the first sub-buffer among the sub-buffers included in each of the temporary buffers, wherein a light pointer designated as a start pointer is assigned. Claim 7 In paragraph 6, the queue controller is a controller configured to store the commands in the sub-buffers according to the light pointers. Claim 8 In claim 5, the queue controller is configured to hold the output of the commands stored in a temporary buffer containing at least one empty sub-buffer among the temporary buffers, and to output the commands stored in the selected temporary buffer when the commands are stored in all the sub-buffers included in the selected temporary buffer among the temporary buffers. Claim 9 A controller further comprising: a command management unit configured to convert requests output from a host into commands, change the execution order of the commands according to the state of the storage device, and transmit the changed commands to the light queue; a system buffer configured to store physical block addresses and logical block addresses of dies included in the storage device, and mapping information between the logical block addresses and the zone ID; and a memory interface configured to store the physical block addresses mapped to the light pointers output from the queue controller, and to transmit the mapped physical block addresses and the commands to the dies corresponding to the zone ID. Claim 10 In claim 9, the memory interface is a controller comprising output buffers corresponding one-to-one with the zone IDs. Claim 11 In claim 9, the command management unit is configured to search for the physical block addresses mapped to each of the light pointers using the mapping information stored in the system buffer when the light pointers are output from the queue controller, and to store the searched physical block addresses in the output buffers of the memory interface. Claim 12 In claim 11, the queue controller is configured to delay the output of the light pointers stored in the sub-buffers until the output buffer is emptied, when the physical block addresses are stored in the output buffer corresponding to the selected zone ID among the output buffers, and all the light pointers are stored in the sub-buffers included in the temporary buffer corresponding to the selected zone ID. Claim 13 A memory system comprising: a storage device including dies for storing data; and a controller configured to generate commands in response to requests output from a host and to queue the commands according to the state of the dies, wherein the controller manages the storage device by classifying the dies into zone IDs, gives priority to a zone ID among the zone IDs in which all light pointers are filled regardless of the order of the queued commands during program operation, and outputs the commands assigned to the zone ID having priority. Claim 14 In paragraph 13, each of the above dies is a memory system comprising a plurality of memory blocks that store the data. Claim 15 In claim 13, the controller comprises: a command management unit configured to convert requests output from the host into commands and change the execution order of the commands according to the state of the storage device; a system buffer configured to store a mapping table of physical block addresses, logical block addresses, and zone IDs of the dies; a zone management unit configured to adjust the queuing of the commands so that when the order of light pointers corresponding to the commands is discontinuous during program operation, the order of light pointers assigned to the same zone ID is continuous, and when a zone ID occurs in which all commands are filled in a temporary buffer, priority is given to the zone ID; and a memory interface configured to store the commands output from the zone management unit and the physical block addresses corresponding to the commands, and to transmit the mapped physical block addresses and the commands to the dies. Claim 16 A memory system comprising: a light queue configured to queue the commands output from the command management unit in the order in which the zone IDs and the light pointers are assigned and input; and a queue controller configured to store the commands in the order stored in the light queue in temporary buffers corresponding to the zone IDs, and to output the commands stored in the temporary buffers among the temporary buffers that have a set storage size filled. Claim 17 In paragraph 16, the above temporary buffers include sub-buffers to which light pointers are allocated, and the above commands are stored in the sub-buffers corresponding to the light pointers in a memory system. Claim 18 A memory system according to claim 17, wherein the queue controller includes temporary buffers in which all the commands are filled and temporary buffers in which the light pointers are not filled, wherein the queue controller gives priority to the temporary buffers in which all the commands are filled and outputs the commands stored in the temporary buffers having priority to the memory interface. Claim 19 In paragraph 13, the controller is a memory system in which, when light pointers containing a control key are included among the light pointers, commands assigned to the light pointers containing the control key are output to the memory interface in response to an output request from the host, and commands assigned to light pointers not containing the control key are output to the memory interface regardless of the output request. Claim 20 A controller comprising: a command management unit configured to generate commands corresponding to requests received from a host, assign light pointers to the commands according to the order in which the commands are generated, and queue the commands according to the state of the storage device in which data is stored; a light queue configured to temporarily store the queued commands; temporary buffers separated by zone ID; and a zone management unit configured to store the commands output from the light queue in the temporary buffers according to the order of the zone IDs and the light pointers, and output the commands from the temporary buffers filled with a set size.

Images