Image sensing device

Abstract

An embodiment of the present invention provides an image sensing device comprising: an image sensor for correcting depth information based on a control signal and generating image data according to the depth information; and a controller for analyzing an error in the depth information and generating the control signal based on first and second periodic signals provided from the image sensor.

Description

Technology Field

[0001] The present invention relates to semiconductor design technology, and more specifically to an image sensing device. Background Technology

[0003] An image sensing device is a device that captures images by utilizing the light-responsive properties of semiconductors. Image sensing devices can be broadly classified into image sensing devices using CCDs (Charge Coupled Devices) and image sensing devices using CMOS (Complementary Metal Oxide Semiconductor). Recently, image sensing devices using CMOS are widely used due to the advantage of being able to directly implement analog and digital control circuits on a single integrated circuit (IC). The problem to be solved

[0005] An embodiment of the present invention provides an image sensing device for correcting an error in depth information. means of solving the problem

[0007] According to one aspect of the present invention, an image sensing device may include: an image sensor for correcting depth information based on a control signal and generating image data according to the depth information; and a controller for analyzing an error in the depth information and generating the control signal based on first and second periodic signals provided from the image sensor.

[0008] The first periodic signal may be a signal required when generating a light signal radiated to a subject, and the second periodic signal may be a signal required when measuring the depth information.

[0009] The image sensor may include: an optical driver for radiating an optical signal to a subject based on the first periodic signal; a pixel driver for generating a driving signal based on the second periodic signal; a pixel array including at least one pixel for sensing an optical signal reflected from the subject based on the driving signal; and a corrector for generating the first periodic signal and the second periodic signal, each having a duty cycle, based on the control signal and the clock signal.

[0010] According to another aspect of the present invention, an image sensing device may include: an image sensor for correcting depth information based on a control signal and generating image data according to the depth information; and a controller for analyzing an error in the depth information based on the image data and generating the control signal.

[0011] The image sensor may include: an optical driver for radiating an optical signal to a subject based on a first periodic signal; a pixel driver for generating a driving signal based on a second periodic signal; a pixel array including at least one pixel for sensing an optical signal reflected from the subject based on the driving signal; and a corrector for generating the first periodic signal and the second periodic signal, each having a duty cycle, based on the control signal and the clock signal.

[0012] According to another aspect of the present invention, an image sensing device may include: an image sensor for correcting depth information based on first and second control signals and generating image data according to said depth information; a first controller for analyzing an error in said depth information based on said image data and generating said first control signal in a test mode; and a second controller for analyzing an error in said depth information based on first and second periodic signals provided from said image sensor and generating said second control signal in a normal mode.

[0013] The first periodic signal may be a signal required when generating a light signal radiated to a subject, and the second periodic signal may be a signal required when measuring the depth information.

[0014] The image sensor may include: an optical driver for radiating an optical signal to a subject based on the first periodic signal; a pixel driver for generating a driving signal based on the second periodic signal; a pixel array including at least one pixel for sensing an optical signal reflected from the subject based on the driving signal; and a corrector for generating the first periodic signal and the second periodic signal, each having a duty cycle based on the first and second control signals, a clock signal, and a test mode signal. Effects of the invention

[0016] The embodiment of the present invention has the effect of improving the operational reliability of an image sensing device because depth information can be easily corrected. Brief explanation of the drawing

[0018] FIG. 1 is a block diagram of an image sensing device according to a first embodiment of the present invention. Figure 2 is a block diagram of the image sensor shown in Figure 1. Figure 3 is a block diagram showing an example of a corrector illustrated in Figure 2. Figure 4 is a block diagram of the duty cycle correction circuit illustrated in Figure 3. Figure 5 is a block diagram showing another example of the corrector illustrated in Figure 2. Figure 6 is a block diagram of the duty cycle correction circuit illustrated in Figure 5. Figure 7 is a block diagram showing another example of the corrector illustrated in Figure 2. FIG. 8 is a block diagram of the first duty cycle correction circuit shown in FIG. 7. FIG. 9 is a block diagram of the second duty cycle correction circuit shown in FIG. 7. Figure 10 is a block diagram of the controller illustrated in Figure 1. FIG. 11 is a timing diagram for explaining the operation of an image sensing device according to a first embodiment of the present invention according to an example. FIG. 12 is a timing diagram for explaining the operation of an image sensing device according to a first embodiment of the present invention according to another example. FIG. 13 is a block diagram of an image sensing device according to a second embodiment of the present invention. FIG. 14 is a block diagram of the image sensor illustrated in FIG. 13. FIG. 15 is a block diagram showing an example of a corrector illustrated in FIG. 14. FIG. 16 is a block diagram of the duty cycle correction circuit illustrated in FIG. 15. FIG. 17 is a block diagram showing another example of the corrector illustrated in FIG. 14. FIG. 18 is a block diagram of the duty cycle correction circuit illustrated in FIG. 17. FIG. 19 is a block diagram showing another example of the compensator illustrated in FIG. 14. FIG. 20 is a block diagram of the first duty cycle correction circuit shown in FIG. 19. FIG. 21 is a block diagram of the second duty cycle correction circuit shown in FIG. 19. FIG. 22 is a block diagram of the controller shown in FIG. 13. FIG. 23 is a timing diagram for explaining the operation of an image sensing device according to a second embodiment of the present invention according to an example. FIG. 24 is a timing diagram for explaining the operation of an image sensing device according to a second embodiment of the present invention according to another example. FIG. 25 is a block diagram of an image sensing device according to a third embodiment of the present invention. FIG. 26 is a block diagram of the image sensor illustrated in FIG. 25. FIG. 27 is a block diagram showing an example of a corrector illustrated in FIG. 26. FIG. 28 is a block diagram of the duty cycle correction circuit illustrated in FIG. 27. FIG. 29 is a block diagram showing another example of the corrector illustrated in FIG. 26. FIG. 30 is a block diagram of the duty cycle correction circuit illustrated in FIG. 29. FIG. 31 is a block diagram showing another example of the compensator illustrated in FIG. 26. FIG. 32 is a block diagram of the first duty cycle correction circuit shown in FIG. 31. FIG. 33 is a block diagram of the second duty cycle correction circuit shown in FIG. 31. FIG. 34 is a block diagram of the first controller shown in FIG. 25. FIG. 35 is a block diagram of the second controller shown in FIG. 25. FIG. 36 is a timing diagram for explaining the operation of an image sensing device according to a third embodiment of the present invention according to an example. FIG. 37 is a timing diagram for explaining the operation of an image sensing device according to a third embodiment of the present invention according to another example. Specific details for implementing the invention

[0019] Hereinafter, in order to explain in detail enough for a person skilled in the art to easily implement the technical concept of the present invention, embodiments of the present invention will be described with reference to the accompanying drawings.

[0020] Furthermore, throughout the specification, when a part is described as being "connected" to another part, this includes not only cases where they are "directly connected" but also cases where they are "electrically connected" with other components interposed between them. Additionally, when a part is described as "including" or "equipped" with a certain component, this means that, unless specifically stated otherwise, it does not exclude other components but may include or be equipped with additional components. Moreover, it will be understood that even if some components are described in the singular form throughout the specification, the present invention is not limited thereto, and such components may be composed of multiple units.

[0021] Figure 1 shows an image sensing device according to a first embodiment of the present invention in a block diagram.

[0022] Referring to FIG. 1, the image sensing device may include an image sensor (100) and a controller (200).

[0023] The image sensor (100) can correct depth information based on a control signal (CTRL) and generate image data (IDT) according to the depth information. The depth information may include distance information between the image sensor (100) and a subject (not shown in the drawing).

[0024] The image sensor (100) can provide the controller (200) with first and second periodic signals (CCL1, CCL2) required when generating image data (IDT). The first periodic signal (CCL1) may be a signal required when generating an optical signal (LS) radiated to a subject (not shown in the drawing). The second periodic signal (CCL2) may be a signal required when measuring the depth information.

[0025] The controller (200) can analyze errors in the depth information and generate a control signal (CTRL) based on the first and second periodic signals (CCL1, CCL2) provided by the image sensor (100). The controller (200) can perform the analysis of errors in the depth information in real time during normal mode and dynamically generate a control signal (CTRL).

[0026] The controller (200) can be integrated on the same chip as the image sensor (100) (i.e., on chip) or on a different chip from the image sensor (100) (i.e., off chip).

[0027] Figure 2 shows a block diagram of the image sensor (100) illustrated in Figure 1.

[0028] Referring to FIG. 2, the image sensor (100) may include a clock generator (110), a compensator (120), an optical driver (130), a pixel driver (140), a row decoder (150), a pixel array (160), a signal converter (170), and an image processor (180).

[0029] The clock generator (110) can generate a clock signal (CLK) in the normal mode. For example, the clock generator (110) may include a phase locked loop or an oscillator.

[0030] The compensator (120) can generate first and second period signals (CCL1, CCL2) having respective duty cycles based on a control signal (CTRL) and a clock signal (CLK). The first and second period signals (CCL1, CCL2) may be designed to have the same duty cycle. Alternatively, the first and second period signals (CCL1, CCL2) may be intentionally designed to have different duty cycles. In an embodiment of the present invention, an example is described in which the first and second period signals (CCL1, CCL2) are designed to have the same duty cycle.

[0031] The optical driver (130) can radiate an optical signal (LS) to the subject based on a first periodic signal (CCL1). For example, the optical driver (130) may include a light-emitting diode or a laser diode, etc.

[0032] The pixel driver (140) can generate a driving signal (PX_DRV) based on a second periodic signal (CCL2). The driving signal (PX_DRV) may be one of the signals required when measuring the depth information.

[0033] The row decoder (150) can generate a row control signal (RCTRL) for controlling the pixel array (160) in row units.

[0034] A pixel array (160) may include multiple pixels arranged at the intersections of multiple rows and multiple columns. The multiple pixels may include at least one depth-measuring pixel for measuring depth information. The depth-measuring pixel may sense a light signal (not shown in the drawing) reflected from the subject based on a driving signal (PX_DRV). In other words, the depth-measuring pixel may generate a pixel signal corresponding to the depth information based on the driving signal (PX_DRV) and the reflected light signal.

[0035] The signal converter (170) can convert the pixel signal into a digital signal (DOUT). For example, the signal converter (170) may include a correlated double sampling circuit and an analog-to-digital converter.

[0036] The image processor (180) can generate image data (IDT) based on a digital signal (DOUT). The image data (IDT) may include the depth information.

[0037] FIG. 3 shows a block diagram illustrating an example of the corrector (120) shown in FIG. 2.

[0038] Referring to FIG. 3, the compensator (120) may include a first load (L1), a duty cycle compensation circuit (DCC), and a second load (L2).

[0039] The first load (L1) can generate a correction target signal (CCL11) corresponding to a clock signal (CLK). The first load (L1) may include a first line load that occurs in a first path where the correction target signal (CCL11) is generated. The first line load may include all loads formed directly or indirectly in the first path. Additionally, the first load (L1) may further include a first circuit, etc., for tuning the clock signal (CLK) according to the design. The duty cycle of the correction target signal (CCL11) may vary differently from the duty cycle of the clock signal (CLK) when passing through the first load (L1). That is, the duty cycle of the correction target signal (CCL11) may be unintentionally adjusted.

[0040] The duty cycle correction circuit (DCC) can generate a first periodic signal (CCL1) based on a control signal (CTRL) and a signal to be corrected (CCL11). For example, the duty cycle correction circuit (DCC) can generate the first periodic signal (CCL1) by correcting the duty cycle of the signal to be corrected (CCL11) in correspondence with the duty cycle of the second periodic signal (CCL2).

[0041] The second load (L2) can generate a second periodic signal (CCL2) corresponding to the clock signal (CLK). The second load (L2) may include a second line load that occurs in the second path where the second periodic signal (CCL2) is generated. The second line load may include all loads formed directly or indirectly in the second path. Additionally, the second load (L2) may further include a second circuit, etc., for tuning the clock signal (CLK) according to the design. The duty cycle of the second periodic signal (CCL2) may vary differently from the duty cycle of the clock signal (CLK) when passing through the second load (L2). That is, the duty cycle of the second periodic signal (CCL2) may be unintentionally adjusted. At this time, the duty cycle of the second periodic signal (CCL2) and the duty cycle of the signal to be corrected (CCL11) may be different.

[0042] FIG. 4 shows a block diagram of the duty cycle correction circuit (DCC) illustrated in FIG. 3. It should be noted that the number of elements, the number of element groups, and the number of signals included in the duty cycle correction circuit (DCC) of FIG. 4 are described as examples for convenience of explanation and are not necessarily limited thereto.

[0043] Referring to FIG. 4, the duty cycle correction circuit (DCC) may include a delay circuit (121), a logic circuit (123), and a selection circuit (125).

[0044] The delay circuit (121) can sequentially delay the correction target signal (CCL11) by a unit delay time and generate first to fifth delay clock signals (D1 to D5). The delay circuit (121) may include first to fifth delay element groups (DLY1 to DLY5) connected in series. Each of the first to fifth delay element groups (DLY1 to DLY5) can delay either the correction target signal (CCL11) or the previous stage delay clock signals (D1 to D4) by the unit delay time and output each delay clock signal (D1 to D5). Each of the first to fifth delay element groups (DLY1 to DLY5) may include an even number of inverters connected in series. In the embodiment of the present invention, each delay element group is described as including inverters, but it is not necessarily limited thereto, and each delay element group may be designed to include resistors and capacitors, etc.

[0045] The logic circuit (123) can perform logical operations on the first to fifth delayed clock signals (D1 to D5) and generate the first to fourth operation clock signals (L1 to L4). The logic circuit (123) may include a first logic element group (123A) and a second logic element group (123B).

[0046] A first logic element group (123A) can generate first and second operation clock signals (L1, L2) having a negative-duty cycle compared to the clock signal (CLK) among first to fourth operation clock signals (L1 to L4), based on a third delay clock signal (D3) having an intermediate delay amount among first to fifth delay clock signals (D1 to D5) and first and second delay clock signals (D1, D2) having a delay amount smaller than the intermediate delay amount. For example, the first logic element group (123A) may include first and second AND gates (AG1, AG2). The first AND gate (AG1) can perform a logical AND operation on the third delay clock signal (D3) having the intermediate delay amount and the first delay clock signal (D1) to generate a first operation clock signal (L1). The second AND gate (AG2) can perform a logical AND operation on the third delay clock signal (D3) having the intermediate delay amount and the second delay clock signal (D2) to generate a second operation clock signal (L2). In addition, the first and second AND gates (AG1, AG2) can be enabled or disabled based on the first and second power gating signals (PG1, PG2). This is to save power that is unnecessarily consumed by the first and second AND gates (AG1, AG2).

[0047] The second logic element group (123B) can generate third and fourth operation clock signals (L3, L4) having a positive-duty cycle compared to the clock signal (CLK) among the first to fourth operation clock signals (L1 to L4), based on the third delay clock signal (D3) having an intermediate delay amount among the first to fifth delay clock signals (D1 to D5) and the fourth and fifth delay clock signals (D4, D5) having a delay amount greater than the intermediate delay amount. For example, the second logic element group (123B) may include first and second OR gates (OG1, OG2). The first OR gate (OG1) can generate the third operation clock signal (L3) by performing a logical OR operation on the third delay clock signal (D3) having an intermediate delay amount and the fourth delay clock signal (D4). The second OR gate (OG2) can perform a logical OR operation on the third delay clock signal (D3) and the fifth delay clock signal (D5) having the aforementioned intermediate delay amount, and generate a fourth operation clock signal (L4). In addition, the first and second OR gates (OG1, OG2) can be enabled or disabled based on the third and fourth power gating signals (PG3, PG4). This is to save power that is unnecessarily consumed by the first and second OR gates (OG1, OG2).

[0048] The selection circuit (125) may include a decoder (DEC) and a multiplexer (MUX).

[0049] The decoder (DEC) can generate a selection code signal (DO) by decoding the control signal (CTRL). For example, if the duty cycle of the signal to be corrected (CCL11) needs to be reduced, the decoder (DEC) can generate a selection code signal (DO) to select either of the first and second operation clock signals (L1, L2) as the first period signal (CCL1). On the other hand, if the duty cycle of the signal to be corrected (CCL11) needs to be increased, the decoder (DEC) can generate a selection code signal (DO) to select either of the third and fourth operation clock signals (L3, L4) as the first period signal (CCL1). In addition, the decoder (DEC) can generate first to fourth power gating signals (PG1 ~ PG4). For example, the decoder (DEC) can disable the first power gating signal (PG1) and enable the second to fourth power gating signals (PG2 to PG4) when the first operation clock signal (L1) among the first to fourth operation clock signals (L1 to L4) is selected.

[0050] A multiplexer (MUX) can output any one of the first to fourth operation clock signals (L1 to L4) as a first period signal (CCL1) based on a selection code signal (DO).

[0051] FIG. 5 shows a block diagram illustrating another example of the corrector (120) shown in FIG. 2.

[0052] Referring to FIG. 5, the corrector (120) may include a first load (L1), a second load (L2), and a duty cycle correction circuit (DCC).

[0053] The first load (L1) can generate a first periodic signal (CCL1) corresponding to a clock signal (CLK). The first load (L1) may include a first line load occurring in a first path where the first periodic signal (CCL1) is generated. The first line load may include all loads formed directly or indirectly in the first path. Additionally, the first load (L1) may further include a first circuit, etc., for tuning the clock signal (CLK) according to the design. The duty cycle of the first periodic signal (CCL1) may vary differently from the duty cycle of the clock signal (CLK) when passing through the first load (L1). That is, the duty cycle of the first periodic signal (CCL1) may be unintentionally adjusted.

[0054] The second load (L2) can generate a correction target signal (CCL22) corresponding to the clock signal (CLK). The second load (L2) may include a second line load that occurs in the second path where the correction target signal (CCL22) is generated. The second line load may include all loads formed directly or indirectly in the second path. In addition, the second load (L2) may further include a second circuit, etc., for tuning the clock signal (CLK) according to the design. The duty cycle of the correction target signal (CCL22) may vary differently from the duty cycle of the clock signal (CLK) when passing through the second load (L2). That is, the duty cycle of the correction target signal (CCL22) may be unintentionally adjusted. At this time, the duty cycle of the correction target signal (CCL22) and the duty cycle of the first periodic signal (CCL1) may be different.

[0055] The duty cycle correction circuit (DCC) can generate a second period signal (CCL2) based on a control signal (CTRL) and a signal to be corrected (CCL22). For example, the duty cycle correction circuit (DCC) can generate the second period signal (CCL2) by correcting the duty cycle of the signal to be corrected (CCL22) in correspondence with the duty cycle of the first period signal (CCL1).

[0056] FIG. 6 shows a block diagram of the duty cycle correction circuit (DCC) illustrated in FIG. 5. It should be noted that the number of elements, the number of element groups, and the number of signals included in the duty cycle correction circuit (DCC) of FIG. 6 are described as examples for convenience of explanation and are not necessarily limited thereto.

[0057] Referring to FIG. 6, the duty cycle correction circuit (DCC) may include a delay circuit (121), a logic circuit (123), and a selection circuit (125).

[0058] The delay circuit (121) can sequentially delay the correction target signal (CCL22) by a unit delay time and generate first to fifth delay clock signals (D1 to D5). The delay circuit (121) may include first to fifth delay element groups (DLY1 to DLY5) connected in series. Each of the first to fifth delay element groups (DLY1 to DLY5) can delay either the correction target signal (CCL22) or the previous stage delay clock signals (D1 to D4) by the unit delay time and output each delay clock signal (D1 to D5). Each of the first to fifth delay element groups (DLY1 to DLY5) may include an even number of inverters connected in series. In the embodiment of the present invention, each delay element group is described as including inverters, but it is not necessarily limited thereto, and each delay element group may be designed to include resistors and capacitors, etc.

[0059] The logic circuit (123) can perform logical operations on the first to fifth delayed clock signals (D1 to D5) and generate the first to fourth operation clock signals (L1 to L4). The logic circuit (123) may include a first logic element group (123A) and a second logic element group (123B).

[0060] A first logic element group (123A) can generate first and second operation clock signals (L1, L2) having a negative-duty cycle compared to the clock signal (CLK) among first to fourth operation clock signals (L1 to L4), based on a third delay clock signal (D3) having an intermediate delay amount among first to fifth delay clock signals (D1 to D5) and first and second delay clock signals (D1, D2) having a delay amount smaller than the intermediate delay amount. For example, the first logic element group (123A) may include first and second AND gates (AG1, AG2). The first AND gate (AG1) can perform a logical AND operation on the third delay clock signal (D3) having the intermediate delay amount and the first delay clock signal (D1) to generate a first operation clock signal (L1). The second AND gate (AG2) can perform a logical AND operation on the third delay clock signal (D3) having the intermediate delay amount and the second delay clock signal (D2) to generate a second operation clock signal (L2). In addition, the first and second AND gates (AG1, AG2) can be enabled or disabled based on the first and second power gating signals (PG1, PG2). This is to save power that is unnecessarily consumed by the first and second AND gates (AG1, AG2).

[0061] The second logic element group (123B) can generate third and fourth operation clock signals (L3, L4) having a positive-duty cycle compared to the clock signal (CLK) among the first to fourth operation clock signals (L1 to L4), based on the third delay clock signal (D3) having an intermediate delay amount among the first to fifth delay clock signals (D1 to D5) and the fourth and fifth delay clock signals (D4, D5) having a delay amount greater than the intermediate delay amount. For example, the second logic element group (123B) may include first and second OR gates (OG1, OG2). The first OR gate (OG1) can generate the third operation clock signal (L3) by performing a logical OR operation on the third delay clock signal (D3) having an intermediate delay amount and the fourth delay clock signal (D4). The second OR gate (OG2) can perform a logical OR operation on the third delay clock signal (D3) and the fifth delay clock signal (D5) having the aforementioned intermediate delay amount, and generate a fourth operation clock signal (L4). In addition, the first and second OR gates (OG1, OG2) can be enabled or disabled based on the third and fourth power gating signals (PG3, PG4). This is to save power that is unnecessarily consumed by the first and second OR gates (OG1, OG2).

[0062] The selection circuit (125) may include a decoder (DEC) and a multiplexer (MUX).

[0063] The decoder (DEC) can generate a selection code signal (DO) by decoding the control signal (CTRL). For example, if the duty cycle of the signal to be corrected (CCL22) needs to be reduced, the decoder (DEC) can generate a selection code signal (DO) to select either of the first and second operation clock signals (L1, L2) as the second period signal (CCL2). On the other hand, if the duty cycle of the signal to be corrected (CCL22) needs to be increased, the decoder (DEC) can generate a selection code signal (DO) to select either of the third and fourth operation clock signals (L3, L4) as the second period signal (CCL2). In addition, the decoder (DEC) can generate first to fourth power gating signals (PG1 to PG4). For example, the decoder (DEC) can disable the first power gating signal (PG1) and enable the second to fourth power gating signals (PG2 to PG4) when the first operation clock signal (L1) among the first to fourth operation clock signals (L1 to L4) is selected.

[0064] A multiplexer (MUX) can output any one of the first to fourth operation clock signals (L1 to L4) as a second period signal (CCL2) based on a selection code signal (DO).

[0065] FIG. 7 shows a block diagram illustrating another example of the corrector (120) shown in FIG. 2.

[0066] Referring to FIG. 7, the corrector (120) may include a first load (L1), a first duty cycle correction circuit (DCC1), a second load (L2), and a second duty cycle correction circuit (DCC2).

[0067] The first load (L1) can generate a first correction target signal (CCL11) corresponding to a clock signal (CLK). The first load (L1) may include a first line load occurring in a first path where the first correction target signal (CCL11) is generated. The first line load may include all loads formed directly or indirectly in the first path. Additionally, the first load (L1) may further include a first circuit, etc., for tuning the clock signal (CLK) according to the design. The duty cycle of the first correction target signal (CCL11) may vary differently from the duty cycle of the clock signal (CLK) when passing through the first load (L1). That is, the duty cycle of the first correction target signal (CCL11) may be unintentionally adjusted.

[0068] The first duty cycle correction circuit (DCC1) can generate a first periodic signal (CCL1) based on a control signal (CTRL) and a first correction target signal (CCL11). For example, the first duty cycle correction circuit (DCC1) can generate the first periodic signal (CCL1) by correcting the duty cycle of the first correction target signal (CCL11) in correspondence with the duty cycle of the second periodic signal (CCL2). The first duty cycle correction circuit (DCC1) can be enabled based on a first enable signal (EN). The first enable signal (EN) may be a signal generated internally within the image sensor (100) or a signal provided by the controller (200).

[0069] The second load (L2) can generate a second correction target signal (CCL22) corresponding to the clock signal (CLK). The second load (L2) may include a second line load that occurs in the second path where the second correction target signal (CCL22) is generated. The second line load may include all loads formed directly or indirectly in the second path. In addition, the second load (L2) may further include a second circuit, etc., for tuning the clock signal (CLK) according to the design. The duty cycle of the second correction target signal (CCL22) may vary differently from the duty cycle of the clock signal (CLK) when passing through the second load (L2). That is, the duty cycle of the second correction target signal (CCL22) may be unintentionally adjusted. At this time, the duty cycle of the second correction target signal (CCL2) and the duty cycle of the first correction target signal (CCL11) may be different.

[0070] The second duty cycle correction circuit (DCC2) can generate a second periodic signal (CCL2) based on a control signal (CTRL) and a second correction target signal (CCL22). For example, the second duty cycle correction circuit (DCC2) can generate the second periodic signal (CCL2) by correcting the duty cycle of the second correction target signal (CCL22) in correspondence with the duty cycle of the first periodic signal (CCL1). The second duty cycle correction circuit (DCC2) can be enabled based on a second enable signal (ENB). The second enable signal (ENB) may be an inverted signal of the first enable signal (EN).

[0071] FIG. 8 shows a block diagram of the first duty cycle correction circuit (DCC1) illustrated in FIG. 7. It should be noted that the number of elements, the number of element groups, and the number of signals included in the first duty cycle correction circuit (DCC1) of FIG. 8 are described as examples for convenience of explanation and are not necessarily limited thereto.

[0072] Referring to FIG. 8, the first duty cycle correction circuit (DCC1) may include a delay circuit (121), a logic circuit (122), and a selection circuit (123).

[0073] The delay circuit (121) can sequentially delay the first correction target signal (CCL11) by a unit delay time and generate first to fifth delay clock signals (D11 to D15). The delay circuit (121) may include first to fifth delay element groups (DLY11 to DLY15) connected in series. Each of the first to fifth delay element groups (DLY11 to DLY15) can delay either the first correction target signal (CCL11) or the previous stage delay clock signals (D11 to D14) by the unit delay time and output each delay clock signal (D11 to D15). Each of the first to fifth delay element groups (DLY11 to DLY15) may include an even number of inverters connected in series. In the embodiment of the present invention, each delay element group is described as including inverters, but it is not necessarily limited thereto, and each delay element group may be designed to include resistors and capacitors, etc.

[0074] The logic circuit (122) can perform a logic operation on the first to fifth delay clock signals (D11 to D15) and generate the first to fourth operation clock signals (L11 to L14). The logic circuit (123) may include a first logic element group (122A) and a second logic element group (122B).

[0075] A first logic element group (122A) can generate first and second operation clock signals (L11, L12) having a negative-duty cycle compared to the clock signal (CLK) among first to fourth operation clock signals (L11 to L14), based on a third delay clock signal (D13) having an intermediate delay amount among first to fifth delay clock signals (D11 to D15) and first and second delay clock signals (D11, D12) having a delay amount smaller than the intermediate delay amount. For example, the first logic element group (122A) may include first and second AND gates (AG11, AG12). The first AND gate (AG11) can perform a logical AND operation on the third delay clock signal (D13) having the intermediate delay amount and the first delay clock signal (D11) to generate a first operation clock signal (L11). The second AND gate (AG12) can perform a logical AND operation on the third delay clock signal (D13) having the intermediate delay amount and the second delay clock signal (D12) to generate a second operation clock signal (L12). In addition, the first and second AND gates (AG11, AG12) can be enabled or disabled based on the first and second power gating signals (PG11, PG12). This is to save power that is unnecessarily consumed by the first and second AND gates (AG11, AG12).

[0076] The second logic element group (122B) can generate third and fourth operation clock signals (L13, L14) having a positive-duty cycle compared to the clock signal (CLK) among the first to fourth operation clock signals (L11 to L14), based on the third delay clock signal (D13) having an intermediate delay amount among the first to fifth delay clock signals (D11 to D15) and the fourth and fifth delay clock signals (D14, D15) having a delay amount greater than the intermediate delay amount. For example, the second logic element group (122B) may include first and second OR gates (OG11, OG12). The first OR gate (OG11) can generate the third operation clock signal (L13) by performing a logical OR operation on the third delay clock signal (D13) having an intermediate delay amount and the fourth delay clock signal (D14). The second OR gate (OG12) can perform a logical OR operation on the third delay clock signal (D13) and the fifth delay clock signal (D15) having the aforementioned intermediate delay amount, and generate a fourth operation clock signal (L14). In addition, the first and second OR gates (OG11, OG12) can be enabled or disabled based on the third and fourth power gating signals (PG13, PG14). This is to save power that is unnecessarily consumed by the first and second OR gates (OG11, OG12).

[0077] The selection circuit (123) may include a buffer (BK1), a decoder (DEC1), and a multiplexer (MUX1).

[0078] Buffer (BK1) can generate a signal (CTRL1) based on a control signal (CTRL) and a first enable signal (EN). For example, when the first enable signal (EN) is activated, buffer (BK1) can generate a signal (CTRL1) corresponding to the control signal (CTRL). On the other hand, when the first enable signal (EN) is deactivated, buffer (BK1) can maintain a signal (CTRL1) that is set by default regardless of the control signal (CTRL).

[0079] The decoder (DEC1) can generate a selection code signal (DO1) by decoding the signal (CTRL1). For example, if the duty cycle of the first correction target signal (CCL11) needs to be reduced, the decoder (DEC1) can generate a selection code signal (DO1) to select either of the first and second operation clock signals (L11, L12) as the first period signal (CCL1). On the other hand, if the duty cycle of the first correction target signal (CCL11) needs to be increased, the decoder (DEC1) can generate a selection code signal (DO1) to select either of the third and fourth operation clock signals (L13, L14) as the first period signal (CCL1). In addition, the decoder (DEC1) can generate first to fourth power gating signals (PG11 ~ PG14). For example, the decoder (DEC1) can disable the first power gating signal (PG11) and enable the second to fourth power gating signals (PG12 to PG14) when the first operation clock signal (L11) among the first to fourth operation clock signals (L11 to L14) is selected.

[0080] The multiplexer (MUX1) can output any one of the first to fourth operation clock signals (L11 to L14) as the first period signal (CCL1) based on the selection code signal (DO1).

[0081] FIG. 9 shows a block diagram of the second duty cycle correction circuit (DCC2) illustrated in FIG. 7. It should be noted that the number of elements, the number of element groups, and the number of signals included in the second duty cycle correction circuit (DCC2) of FIG. 9 are described as examples for convenience of explanation and are not necessarily limited thereto.

[0082] Referring to FIG. 9, the second duty cycle correction circuit (DCC2) may include a delay circuit (125), a logic circuit (126), and a selection circuit (127).

[0083] The delay circuit (125) can sequentially delay the second correction target signal (CCL22) by a unit delay time and generate first to fifth delay clock signals (D21 to D25). The delay circuit (125) may include first to fifth delay element groups (DLY21 to DLY25) connected in series. Each of the first to fifth delay element groups (DLY21 to DLY25) can delay either the second correction target signal (CCL22) or the previous stage delay clock signals (D21 to D24) by the unit delay time and output each delay clock signal (D21 to D25). Each of the first to fifth delay element groups (DLY21 to DLY25) may include an even number of inverters connected in series. In the embodiment of the present invention, each delay element group is described as including inverters, but it is not necessarily limited thereto, and each delay element group may be designed to include resistors and capacitors, etc.

[0084] The logic circuit (126) can perform a logic operation on the first to fifth delay clock signals (D21 to D25) and generate the first to fourth operation clock signals (L21 to L24). The logic circuit (126) may include a first logic element group (126A) and a second logic element group (126B).

[0085] A first logic element group (126A) can generate first and second operation clock signals (L21, L22) having a negative-duty cycle compared to the clock signal (CLK) among first to fourth operation clock signals (L21 to L24), based on a third delay clock signal (D23) having an intermediate delay amount among first to fifth delay clock signals (D21 to D25) and first and second delay clock signals (D21, D22) having a delay amount smaller than the intermediate delay amount. For example, the first logic element group (126A) may include first and second AND gates (AG21, AG22). The first AND gate (AG21) can perform a logical AND operation on the third delay clock signal (D23) having the intermediate delay amount and the first delay clock signal (D21) to generate a first operation clock signal (L21). The second AND gate (AG22) can perform a logical AND operation on the third delay clock signal (D23) having the intermediate delay amount and the second delay clock signal (D22) to generate a second operation clock signal (L22). In addition, the first and second AND gates (AG21, AG22) can be enabled or disabled based on the first and second power gating signals (PG21, PG22). This is to save power that is unnecessarily consumed by the first and second AND gates (AG21, AG22).

[0086] The second logic element group (126B) can generate third and fourth operation clock signals (L23, L24) having a positive-duty cycle compared to the clock signal (CLK) among the first to fourth operation clock signals (L21 to L24), based on the third delay clock signal (D23) having an intermediate delay amount among the first to fifth delay clock signals (D21 to D25) and the fourth and fifth delay clock signals (D24, D25) having a delay amount greater than the intermediate delay amount. For example, the second logic element group (126B) may include first and second OR gates (OG21, OG22). The first OR gate (OG21) can generate the third operation clock signal (L23) by performing a logical OR operation on the third delay clock signal (D23) having an intermediate delay amount and the fourth delay clock signal (D24). The second OR gate (OG22) can perform a logical OR operation on the third delay clock signal (D23) and the fifth delay clock signal (D25) having the aforementioned intermediate delay amount, and generate a fourth operation clock signal (L24). In addition, the first and second OR gates (OG21, OG22) can be enabled or disabled based on the third and fourth power gating signals (PG23, PG24). This is to save power that is unnecessarily consumed by the first and second OR gates (OG21, OG22).

[0087] The selection circuit (127) may include a buffer (BK2), a decoder (DEC2), and a multiplexer (MUX2).

[0088] Buffer (BK2) can generate a signal (CTRL2) based on a control signal (CTRL) and a second enable signal (ENB). For example, when the second enable signal (ENB) is activated, buffer (BK2) can generate a signal (CTRL2) corresponding to the control signal (CTRL). On the other hand, when the second enable signal (ENB) is deactivated, buffer (BK2) can maintain a signal (CTRL2) that is set by default regardless of the control signal (CTRL).

[0089] The decoder (DEC2) can decode the signal to generate a selection code signal. For example, if the duty cycle of the second correction target signal (CCL22) needs to be reduced, the decoder (DEC2) can generate the selection code signal to select either of the first and second operation clock signals (L21, L22) as the second period signal (CCL2). On the other hand, if the duty cycle of the second correction target signal (CCL22) needs to be increased, the decoder (DEC2) can generate the selection code signal to select either of the third and fourth operation clock signals (L23, L24) as the second period signal (CCL1). In addition, the decoder (DEC2) can generate first to fourth power gating signals (PG21 ~ PG24). For example, the decoder (DEC2) can disable the first power gating signal (PG21) and enable the second to fourth power gating signals (PG22 to PG24) when the first operation clock signal (L21) among the first to fourth operation clock signals (L21 to L24) is selected.

[0090] The multiplexer (MUX2) can output any one of the first to fourth operation clock signals (L21 to L24) as the second period signal (CCL2) based on the selection code signal.

[0091] Figure 10 shows a block diagram of the controller (200) illustrated in Figure 1.

[0092] Referring to FIG. 10, the controller (200) may include a detection circuit (210) and a conversion circuit (220).

[0093] The detection circuit (210) can detect the duty cycle difference between the first period signal (CCL1) and the second period signal (CCL2). For example, the detection circuit (210) can detect the difference in the duty cycle by detecting the difference between the period during which the first period signal (CCL1) is at a logic high level (or logic low level) and the period during which the second period signal (CCL2) is at a logic high level (or logic low level) during one period. The detection circuit (210) can generate a detection signal (DET) corresponding to the result of detecting the duty cycle difference.

[0094] The conversion circuit (220) can generate a control signal (CTRL) corresponding to a detection signal (DET). For example, the conversion circuit (220) can convert the detection signal (DET) into a control signal (CTRL) which is a digital signal.

[0095] Hereinafter, the operation of an image sensing device according to the first embodiment of the present invention having the configuration as described above will be explained.

[0096] The first embodiment of the present invention represents the operation of an image sensing device including a corrector (120) shown in FIG. 3.

[0097] In normal mode, the controller (200) can dynamically generate a control signal (CTRL) based on first and second period signals (CCL1, CCL2) provided in real time from the image sensor (100). For example, the controller (200) can detect the difference in duty cycle between the first period signal (CCL1) and the second period signal (CCL2) and generate a control signal (CTRL) corresponding to the detection result in real time.

[0098] The image sensor (100) can correct the depth information based on a control signal (CTRL). For example, the image sensor (100) can correct the depth information by eliminating the difference in duty cycle between a first periodic signal (CCL1) and a second periodic signal (CCL2). In particular, a corrector (120) included in the image sensor (100) can eliminate the difference in duty cycle between a first periodic signal (CCL1) and a second periodic signal (CCL2) based on the control signal (CTRL).

[0099] FIG. 11 shows a timing diagram to explain the operation of the corrector (120) illustrated in FIG. 3 according to an example.

[0100] Referring to FIG. 11, the corrector (120) can correct the duty cycle of the signal to be corrected (CCL11) based on the control signal (CTRL) and generate a first periodic signal (CCL1). That is, the corrector (120) can generate a first periodic signal (CCL1) having a positive duty cycle by correcting the duty cycle of the signal to be corrected (CCL11) according to the duty cycle of the second periodic signal (CCL2).

[0101] FIG. 12 shows a timing diagram to explain the operation of the corrector (120) shown in FIG. 3 according to another example.

[0102] Referring to FIG. 12, the corrector (120) can correct the duty cycle of the signal to be corrected (CCL11) based on the control signal (CTRL) and generate a first periodic signal (CCL1). That is, the corrector (120) can generate a first periodic signal (CCL1) having a negative duty cycle by correcting the duty cycle of the signal to be corrected (CCL11) according to the duty cycle of the second periodic signal (CCL2).

[0103] According to the first embodiment of the present invention, there is an advantage in that depth information can be corrected by easily eliminating the difference in duty cycle between the first and second periodic signals in normal mode.

[0105] FIG. 13 shows an image sensing device according to a second embodiment of the present invention in a block diagram.

[0106] Referring to FIG. 13, the image sensing device may include an image sensor (300) and a controller (400).

[0107] The image sensor (300) can correct depth information based on a control signal (CTRL) and generate image data (IDT) according to the depth information. The depth information may include distance information between the image sensor (300) and a subject (not shown in the drawing).

[0108] The controller (400) can analyze the error in the depth information based on the image data (IDT) provided from the image sensor (300) and generate a control signal (CTRL). The controller (400) can perform the error analysis operation of the depth information at least once during test mode and generate a static control signal (CTRL). The controller (400) may be included in a test device (not shown in the drawing).

[0109] FIG. 14 shows a block diagram of the image sensor (300) illustrated in FIG. 13.

[0110] Referring to FIG. 14, the image sensor (300) may include a clock generator (310), a corrector (320), an optical driver (330), a pixel driver (340), a row decoder (350), a pixel array (360), a signal converter (370), and an image processor (380).

[0111] The clock generator (310) can generate a clock signal (CLK) during the test mode. For example, the clock generator (310) may include a phase locked loop or an oscillator.

[0112] The compensator (320) can generate first and second period signals (CCL1, CCL2) having respective duty cycles based on a control signal (CTRL) and a clock signal (CLK). The first and second period signals (CCL1, CCL2) may be designed to have the same duty cycle. Alternatively, the first and second period signals (CCL1, CCL2) may be intentionally designed to have different duty cycles. In an embodiment of the present invention, an example is described in which the first and second period signals (CCL1, CCL2) are designed to have the same duty cycle.

[0113] The optical driver (330) can radiate an optical signal (LS) to the subject based on a first periodic signal (CCL1). For example, the optical driver (330) may include a light-emitting diode or a laser diode, etc.

[0114] The pixel driver (340) can generate a driving signal (PX_DRV) based on a second periodic signal (CCL2). The driving signal (PX_DRV) may be one of the signals required when measuring the depth information.

[0115] The row decoder (350) can generate a row control signal (RCTRL) for controlling the pixel array (360) in row units.

[0116] The pixel array (360) may include multiple pixels arranged at the intersections of multiple rows and multiple columns. The multiple pixels may include at least one depth-measuring pixel for measuring depth information. The depth-measuring pixel may sense a light signal (not shown in the drawing) reflected from the subject based on a driving signal (PX_DRV). In other words, the depth-measuring pixel may generate a pixel signal corresponding to the depth information based on the driving signal (PX_DRV) and the reflected light signal.

[0117] The signal converter (370) can convert the pixel signal into a digital signal (DOUT). For example, the signal converter (370) may include a correlated double sampling circuit and an analog-to-digital converter.

[0118] The image processor (380) can generate image data (IDT) based on a digital signal (DOUT). The image data (IDT) may include the depth information.

[0119] FIG. 15 shows a block diagram illustrating an example of the corrector (320) shown in FIG. 14.

[0120] Referring to FIG. 15, the compensator (320) may include a first load (L1), a duty cycle compensation circuit (DCC), and a second load (L2). Since the first load (L1), the duty cycle compensation circuit (DCC), and the second load (L2) shown in FIG. 15 are identical to the first load (L1), the duty cycle compensation circuit (DCC), and the second load (L2) shown in FIG. 3, a detailed description is omitted.

[0121] FIG. 16 shows a block diagram of the duty cycle correction circuit (DCC) illustrated in FIG. 15. It should be noted that the number of elements, the number of element groups, and the number of signals included in the duty cycle correction circuit (DCC) of FIG. 16 are described as examples for convenience of explanation and are not necessarily limited thereto.

[0122] Referring to FIG. 16, the duty cycle correction circuit (DCC) may include a delay circuit (321), a logic circuit (323), and a selection circuit (325). Since the delay circuit (321), the logic circuit (323), and the selection circuit (325) shown in FIG. 16 are identical to the delay circuit (121), the logic circuit (123), and the selection circuit (125) shown in FIG. 4, a detailed description is omitted.

[0123] FIG. 17 shows a block diagram illustrating another example of the corrector (320) shown in FIG. 14.

[0124] Referring to FIG. 17, the compensator (320) may include a first load (L1), a second load (L2), and a duty cycle compensation circuit (DCC). Since the first load (L1), the second load (L2), and the duty cycle compensation circuit (DCC) shown in FIG. 17 are identical to the first load (L1), the second load (L2), and the duty cycle compensation circuit (DCC) shown in FIG. 5, a detailed description is omitted.

[0125] FIG. 18 shows a block diagram of the duty cycle correction circuit (DCC) illustrated in FIG. 17. It should be noted that the number of elements, the number of element groups, and the number of signals included in the duty cycle correction circuit (DCC) of FIG. 18 are described as examples for convenience of explanation and are not necessarily limited thereto.

[0126] Referring to FIG. 18, the duty cycle correction circuit (DCC) may include a delay circuit (321), a logic circuit (323), and a selection circuit (325). Since the delay circuit (321), the logic circuit (323), and the selection circuit (325) shown in FIG. 18 are identical to the delay circuit (121), the logic circuit (123), and the selection circuit (125) shown in FIG. 6, a detailed description is omitted.

[0127] FIG. 19 shows a block diagram illustrating another example of the corrector (320) shown in FIG. 14.

[0128] Referring to FIG. 19, the compensator (320) may include a first load (L1), a first duty cycle compensation circuit (DCC1), a second load (L2), and a second duty cycle compensation circuit (DCC2). Since the first load (L1), the first duty cycle compensation circuit (DCC1), the second load (L2), and the second duty cycle compensation circuit (DCC2) shown in FIG. 19 are identical to the first load (L1), the first duty cycle compensation circuit (DCC1), the second load (L2), and the second duty cycle compensation circuit (DCC2) shown in FIG. 7, a detailed description is omitted.

[0129] FIG. 20 shows a block diagram of the first duty cycle correction circuit (DCC1) illustrated in FIG. 19. It should be noted that the number of elements, the number of element groups, and the number of signals included in the first duty cycle correction circuit (DCC1) of FIG. 20 are described as examples for convenience of explanation and are not necessarily limited thereto.

[0130] Referring to FIG. 20, the first duty cycle correction circuit (DCC1) may include a delay circuit (321), a logic circuit (322), and a selection circuit (323). Since the delay circuit (321), the logic circuit (322), and the selection circuit (323) shown in FIG. 20 are identical to the delay circuit (121), the logic circuit (122), and the selection circuit (123) shown in FIG. 8, a detailed description is omitted.

[0131] FIG. 21 shows a block diagram of the second duty cycle correction circuit (DCC2) illustrated in FIG. 19. It should be noted that the number of elements, the number of element groups, and the number of signals included in the second duty cycle correction circuit (DCC2) of FIG. 20 are described as examples for convenience of explanation and are not necessarily limited thereto.

[0132] Referring to FIG. 21, the second duty cycle correction circuit (DCC2) may include a delay circuit (325), a logic circuit (326), and a selection circuit (327). Since the delay circuit (325), the logic circuit (326), and the selection circuit (327) shown in FIG. 21 are identical to the delay circuit (125), the logic circuit (126), and the selection circuit (127) shown in FIG. 9, a detailed description is omitted.

[0133] FIG. 22 shows a block diagram of the controller (400) illustrated in FIG. 13.

[0134] Referring to FIG. 22, the controller (400) may include a comparison circuit (410) and a discrimination circuit (420).

[0135] The comparison circuit (410) can compare image data (IDT) and reference data (RDT) and generate a comparison signal (CMP).

[0136] The discrimination circuit (420) can determine an error in the depth information based on a comparison signal (CMP) and generate a control signal (CTRL). For example, the discrimination circuit (420) can change the control signal (CTRL) if the result of determining the error in the depth information is a failure, and fix the control signal (CTRL) if the result of determining is a pass.

[0137] Hereinafter, the operation of an image sensing device according to a second embodiment of the present invention having the configuration as described above will be explained.

[0138] A second embodiment of the present invention describes the operation of an image sensing device including a corrector (320) shown in FIG. 15.

[0139] In test mode, the controller (400) can statically generate a control signal (CTRL) based on image data (IDT) provided from the image sensor (300). For example, the controller (400) can compare the image data (IDT) with reference data (RDT) and generate a control signal (CTRL) corresponding to the comparison result at least once.

[0140] The image sensor (300) can correct the depth information based on the control signal (CTRL). For example, the image sensor (300) can correct the depth information by eliminating the difference in duty cycle between the first periodic signal (CCL1) and the second periodic signal (CCL2). In particular, the corrector (320) included in the image sensor (300) can eliminate the difference in duty cycle between the first periodic signal (CCL1) and the second periodic signal (CCL2) based on the control signal (CTRL).

[0141] FIG. 23 shows a timing diagram to explain the operation of the corrector (320) illustrated in FIG. 15 according to an example.

[0142] Referring to FIG. 23, the corrector (320) can correct the duty cycle of the signal to be corrected (CCL11) based on the control signal (CTRL) and generate a first periodic signal (CCL1). That is, the corrector (320) can generate a first periodic signal (CCL1) having a positive duty cycle by correcting the duty cycle of the signal to be corrected (CCL11) according to the duty cycle of the second periodic signal (CCL2).

[0143] FIG. 24 shows a timing diagram to explain the operation of the corrector (320) shown in FIG. 15 according to another example.

[0144] Referring to FIG. 24, the corrector (320) can correct the duty cycle of the signal to be corrected (CCL11) based on the control signal (CTRL) and generate a first periodic signal (CCL1). That is, the corrector (320) can generate a first periodic signal (CCL1) having a negative duty cycle by correcting the duty cycle of the signal to be corrected (CCL11) according to the duty cycle of the second periodic signal (CCL2).

[0145] According to the second embodiment of the present invention, there is an advantage in that depth information can be corrected by easily eliminating the difference in duty cycle between the first and second periodic signals during test mode.

[0147] FIG. 25 shows an image sensing device according to a third embodiment of the present invention in a block diagram.

[0148] Referring to FIG. 25, the image sensing device may include an image sensor (500), a first controller (600), and a second controller (700).

[0149] The image sensor (500) can correct depth information based on the first and second control signals (CTRL1, CTRL2) and generate image data (IDT) according to the depth information. The depth information may include distance information between the image sensor (100) and a subject (not shown in the drawing).

[0150] The image sensor (500) can provide image data (IDT) to the first controller (600) in test mode and can provide first and second periodic signals (CCL1, CCL2) required when generating image data (IDT) in normal mode to the second controller (700). The first periodic signal (CCL1) may be a signal required when generating an optical signal (LS) radiated to a subject (not shown in the drawing). The second periodic signal (CCL2) may be a signal required when measuring the depth information.

[0151] The first controller (600) can analyze the error in the depth information based on the image data (IDT) provided from the image sensor (500) and generate a first control signal (CTRL1). The first controller (600) can perform the error analysis operation of the depth information at least once during the test mode and statically generate the first control signal (CTRL1). The first controller (600) may be included in a test device (not shown in the drawing).

[0152] The second controller (700) can analyze errors in the depth information and generate a second control signal (CTRL2) based on the first and second periodic signals (CCL1, CCL2) provided by the image sensor (500). The second controller (200) can perform the analysis of errors in the depth information in real time during the normal mode and dynamically generate the second control signal (CTRL2). The second controller (700) can be integrated on the same chip as the image sensor (500) (i.e., on chip) or on a different chip from the image sensor (500) (i.e., off chip).

[0153] FIG. 26 shows a block diagram of the image sensor (500) illustrated in FIG. 25.

[0154] Referring to FIG. 26, the image sensor (500) may include a clock generator (510), a compensator (520), an optical driver (530), a pixel driver (540), a row decoder (550), a pixel array (560), a signal converter (570), and an image processor (580).

[0155] The clock generator (510) can generate a clock signal (CLK) during the test mode and the normal mode. For example, the clock generator (510) may include a phase locked loop or an oscillator.

[0156] The compensator (520) can generate first and second period signals (CCL1, CCL2) having respective duty cycles based on first and second control signals (CTRL1, CTRL2), a clock signal (CLK), and a test mode signal (TM). The first and second period signals (CCL1, CCL2) may be designed to have the same duty cycle. Alternatively, the first and second period signals (CCL1, CCL2) may be intentionally designed to have different duty cycles. In an embodiment of the present invention, an example is described in which the first and second period signals (CCL1, CCL2) are designed to have the same duty cycle.

[0157] The optical driver (530) can radiate an optical signal (LS) to the subject based on a first periodic signal (CCL1). For example, the optical driver (530) may include a light-emitting diode or a laser diode, etc.

[0158] The pixel driver (540) can generate a driving signal (PX_DRV) based on a second periodic signal (CCL2). The driving signal (PX_DRV) may be one of the signals required when measuring the depth information.

[0159] The row decoder (550) can generate a row control signal (RCTRL) for controlling the pixel array (560) in row units.

[0160] A pixel array (560) may include multiple pixels arranged at the intersections of multiple rows and multiple columns. The multiple pixels may include at least one depth-measuring pixel for measuring depth information. The depth-measuring pixel may sense a light signal (not shown in the drawing) reflected from the subject based on a driving signal (PX_DRV). In other words, the depth-measuring pixel may generate a pixel signal corresponding to the depth information based on the driving signal (PX_DRV) and the reflected light signal.

[0161] The signal converter (570) can convert the pixel signal into a digital signal (DOUT). For example, the signal converter (570) may include a correlated double sampling circuit and an analog-to-digital converter.

[0162] The image processor (580) can generate image data (IDT) based on a digital signal (DOUT). The image data (IDT) may include the depth information.

[0163] FIG. 27 shows a block diagram illustrating an example of the corrector (520) shown in FIG. 26.

[0164] Referring to FIG. 27, the compensator (520) may include a first load (L1), a duty cycle compensation circuit (DCC), and a second load (L2).

[0165] The first load (L1) can generate a correction target signal (CCL11) corresponding to a clock signal (CLK). The first load (L1) may include a first line load that occurs in a first path where the correction target signal (CCL11) is generated. The first line load may include all loads formed directly or indirectly in the first path. Additionally, the first load (L1) may further include a first circuit, etc., for tuning the clock signal (CLK) according to the design. The duty cycle of the correction target signal (CCL11) may vary differently from the duty cycle of the clock signal (CLK) when passing through the first load (L1). That is, the duty cycle of the correction target signal (CCL11) may be unintentionally adjusted.

[0166] The duty cycle correction circuit (DCC) can generate a first periodic signal (CCL1) based on the first and second control signals (CTRL1, CTRL2), the test mode signal (TM), and the correction target signal (CCL11). For example, the duty cycle correction circuit (DCC) can statically generate the first periodic signal (CCL1) by correcting the duty cycle of the correction target signal (CCL11) in correspondence with the duty cycle of the second periodic signal (CCL2) during the test mode, and can dynamically generate the first periodic signal (CCL1) by correcting the duty cycle of the correction target signal (CCL11) in real time in correspondence with the duty cycle of the second periodic signal (CCL2) during the normal mode.

[0167] The second load (L2) can generate a second periodic signal (CCL2) corresponding to the clock signal (CLK). The second load (L2) may include a second line load that occurs in the second path where the second periodic signal (CCL2) is generated. The second line load may include all loads formed directly or indirectly in the second path. Additionally, the second load (L2) may further include a second circuit, etc., for tuning the clock signal (CLK) according to the design. The duty cycle of the second periodic signal (CCL2) may vary differently from the duty cycle of the clock signal (CLK) when passing through the second load (L2). That is, the duty cycle of the second periodic signal (CCL2) may be unintentionally adjusted. At this time, the duty cycle of the second periodic signal (CCL2) and the duty cycle of the signal to be corrected (CCL11) may be different.

[0168] FIG. 28 shows a block diagram of the duty cycle correction circuit (DCC) illustrated in FIG. 27. It should be noted that the number of elements, the number of element groups, and the number of signals included in the duty cycle correction circuit (DCC) of FIG. 28 are described as examples for convenience of explanation and are not necessarily limited thereto.

[0169] Referring to FIG. 28, the duty cycle correction circuit (DCC) may include a delay circuit (521), a logic circuit (523), and a selection circuit (525). Since the delay circuit (521) and the logic circuit (523) shown in FIG. 28 are identical to the delay circuit (121) and the logic circuit (123) shown in FIG. 4, a detailed description thereof is omitted.

[0170] The selection circuit (525) may include a first multiplexer (MUX1), a decoder (DEC), and a second multiplexer (MUX2).

[0171] The first multiplexer (MUX1) can output either one of the first and second control signals (CTRL1, CTRL2) as a control signal (CTRL) based on the test mode signal (TM). For example, the first multiplexer (MUX1) can output the first control signal (CTRL1) among the first and second control signals (CTRL1, CTRL2) as a control signal (CTRL) during the test mode, and can output the second control signal (CTRL2) among the first and second control signals (CTRL1, CTRL2) as a control signal (CTRL) during the normal mode.

[0172] The decoder (DEC) can generate a selection code signal (DO) by decoding the control signal (CTRL). For example, if the duty cycle of the signal to be corrected (CCL11) needs to be reduced, the decoder (DEC) can generate a selection code signal (DO) to select either of the first and second operation clock signals (L1, L2) as the first period signal (CCL1). On the other hand, if the duty cycle of the signal to be corrected (CCL11) needs to be increased, the decoder (DEC) can generate a selection code signal (DO) to select either of the third and fourth operation clock signals (L3, L4) as the first period signal (CCL1). In addition, the decoder (DEC) can generate first to fourth power gating signals (PG1 ~ PG4). For example, the decoder (DEC) can disable the first power gating signal (PG1) and enable the second to fourth power gating signals (PG2 to PG4) when the first operation clock signal (L1) among the first to fourth operation clock signals (L1 to L4) is selected.

[0173] The second multiplexer (MUX2) can output any one of the first to fourth operation clock signals (L1 to L4) as the first period signal (CCL1) based on the selection code signal (DO).

[0174] FIG. 29 shows a block diagram illustrating another example of the corrector (520) shown in FIG. 26.

[0175] Referring to FIG. 29, the corrector (520) may include a first load (L1), a second load (L2), and a duty cycle correction circuit (DCC).

[0176] The first load (L1) can generate a first periodic signal (CCL1) corresponding to a clock signal (CLK). The first load (L1) may include a first line load occurring in a first path where the first periodic signal (CCL1) is generated. The first line load may include all loads formed directly or indirectly in the first path. Additionally, the first load (L1) may further include a first circuit, etc., for tuning the clock signal (CLK) according to the design. The duty cycle of the first periodic signal (CCL1) may vary differently from the duty cycle of the clock signal (CLK) when passing through the first load (L1). That is, the duty cycle of the first periodic signal (CCL1) may be unintentionally adjusted.

[0177] The second load (L2) can generate a correction target signal (CCL22) corresponding to the clock signal (CLK). The second load (L2) may include a second line load that occurs in the second path where the correction target signal (CCL22) is generated. The second line load may include all loads formed directly or indirectly in the second path. In addition, the second load (L2) may further include a second circuit, etc., for tuning the clock signal (CLK) according to the design. The duty cycle of the correction target signal (CCL22) may vary differently from the duty cycle of the clock signal (CLK) when passing through the second load (L2). That is, the duty cycle of the correction target signal (CCL22) may be unintentionally adjusted. At this time, the duty cycle of the correction target signal (CCL22) and the duty cycle of the first periodic signal (CCL1) may be different.

[0178] The duty cycle correction circuit (DCC) can generate a second periodic signal (CCL2) based on the first and second control signals (CTRL1, CTRL2), the test mode signal (TM), and the correction target signal (CCL22). For example, the duty cycle correction circuit (DCC) can statically generate the second periodic signal (CCL2) by correcting the duty cycle of the correction target signal (CCL22) in correspondence with the duty cycle of the first periodic signal (CCL1) during the test mode, and can dynamically generate the second periodic signal (CCL2) by correcting the duty cycle of the correction target signal (CCL22) in real time in correspondence with the duty cycle of the first periodic signal (CCL1) during the normal mode.

[0179] FIG. 30 shows a block diagram of the duty cycle correction circuit (DCC) illustrated in FIG. 29. It should be noted that the number of elements, the number of element groups, and the number of signals included in the duty cycle correction circuit (DCC) of FIG. 30 are described as examples for convenience of explanation and are not necessarily limited thereto.

[0180] Referring to FIG. 30, the duty cycle correction circuit (DCC) may include a delay circuit (121), a logic circuit (123), and a selection circuit (125).

[0181] Referring to FIG. 30, the duty cycle correction circuit (DCC) may include a delay circuit (521), a logic circuit (523), and a selection circuit (525). Since the delay circuit (521) and the logic circuit (523) shown in FIG. 30 are identical to the delay circuit (121) and the logic circuit (123) shown in FIG. 6, a detailed description thereof is omitted.

[0182] The selection circuit (525) may include a first multiplexer (MUX1), a decoder (DEC), and a second multiplexer (MUX2).

[0183] The first multiplexer (MUX1) can output either one of the first and second control signals (CTRL1, CTRL2) as a control signal (CTRL) based on the test mode signal (TM). For example, the first multiplexer (MUX1) can output the first control signal (CTRL1) among the first and second control signals (CTRL1, CTRL2) as a control signal (CTRL) during the test mode, and can output the second control signal (CTRL2) among the first and second control signals (CTRL1, CTRL2) as a control signal (CTRL) during the normal mode.

[0184] The decoder (DEC) can generate a selection code signal (DO) by decoding the control signal (CTRL). For example, if the duty cycle of the signal to be corrected (CCL11) needs to be reduced, the decoder (DEC) can generate a selection code signal (DO) to select either of the first and second operation clock signals (L1, L2) as the first period signal (CCL1). On the other hand, if the duty cycle of the signal to be corrected (CCL11) needs to be increased, the decoder (DEC) can generate a selection code signal (DO) to select either of the third and fourth operation clock signals (L3, L4) as the first period signal (CCL1). In addition, the decoder (DEC) can generate first to fourth power gating signals (PG1 ~ PG4). For example, the decoder (DEC) can disable the first power gating signal (PG1) and enable the second to fourth power gating signals (PG2 to PG4) when the first operation clock signal (L1) among the first to fourth operation clock signals (L1 to L4) is selected.

[0185] The second multiplexer (MUX2) can output any one of the first to fourth operation clock signals (L1 to L4) as the first periodic signal (CCL1) based on the selection code signal.

[0186] FIG. 31 shows a block diagram illustrating another example of the corrector (520) shown in FIG. 26.

[0187] Referring to FIG. 31, the corrector (520) may include a first load (L1), a first duty cycle correction circuit (DCC1), a second load (L2), and a second duty cycle correction circuit (DCC2).

[0188] The first load (L1) can generate a first correction target signal (CCL11) corresponding to a clock signal (CLK). The first load (L1) may include a first line load occurring in a first path where the first correction target signal (CCL11) is generated. The first line load may include all loads formed directly or indirectly in the first path. Additionally, the first load (L1) may further include a first circuit, etc., for tuning the clock signal (CLK) according to the design. The duty cycle of the first correction target signal (CCL11) may vary differently from the duty cycle of the clock signal (CLK) when passing through the first load (L1). That is, the duty cycle of the first correction target signal (CCL11) may be unintentionally adjusted.

[0189] The first duty cycle correction circuit (DCC1) can generate a first periodic signal (CCL1) based on the first and second control signals (CTRL1, CTRL2), the test mode signal (TM), and the correction target signal (CCL11). For example, the first duty cycle correction circuit (DCC) can statically generate the first periodic signal (CCL1) by correcting the duty cycle of the correction target signal (CCL11) in correspondence with the duty cycle of the second periodic signal (CCL2) during the test mode, and can dynamically generate the first periodic signal (CCL1) by correcting the duty cycle of the correction target signal (CCL11) in real time in correspondence with the duty cycle of the second periodic signal (CCL2) during the normal mode. The first duty cycle correction circuit (DCC1) can be enabled based on the first enable signal (EN). The first enable signal (EN) may be a signal generated internally by the image sensor (500) or a signal provided by the first and second controllers (600, 700).

[0190] The second load (L2) can generate a second correction target signal (CCL22) corresponding to the clock signal (CLK). The second load (L2) may include a second line load that occurs in the second path where the second correction target signal (CCL22) is generated. The second line load may include all loads formed directly or indirectly in the second path. In addition, the second load (L2) may further include a second circuit, etc., for tuning the clock signal (CLK) according to the design. The duty cycle of the second correction target signal (CCL22) may vary differently from the duty cycle of the clock signal (CLK) when passing through the second load (L2). That is, the duty cycle of the second correction target signal (CCL22) may be unintentionally adjusted. At this time, the duty cycle of the second correction target signal (CCL2) and the duty cycle of the first correction target signal (CCL11) may be different.

[0191] The second duty cycle correction circuit (DCC2) can generate a second periodic signal (CCL2) based on the first and second control signals (CTRL1, CTRL2), the test mode signal (TM), and the correction target signal (CCL22). For example, the second duty cycle correction circuit (DCC2) can statically generate the second periodic signal (CCL2) by correcting the duty cycle of the correction target signal (CCL22) in correspondence with the duty cycle of the first periodic signal (CCL1) during the test mode, and can dynamically generate the second periodic signal (CCL2) by correcting the duty cycle of the correction target signal (CCL22) in real time in correspondence with the duty cycle of the first periodic signal (CCL1) during the normal mode. The second duty cycle correction circuit (DCC2) can be enabled based on the second enable signal (ENB). The second enable signal (ENB) may be the inverted signal of the first enable signal (EN).

[0192] FIG. 32 shows a block diagram of the first duty cycle correction circuit (DCC1) illustrated in FIG. 31. It should be noted that the number of elements, the number of element groups, and the number of signals included in the first duty cycle correction circuit (DCC1) of FIG. 32 are described as examples for convenience of explanation and are not necessarily limited thereto.

[0193] Referring to FIG. 32, the first duty cycle correction circuit (DCC1) may include a delay circuit (521), a logic circuit (522), and a selection circuit (523). Since the delay circuit (521) and the logic circuit (523) shown in FIG. 32 are identical to the delay circuit (121) and the logic circuit (122) shown in FIG. 8, a detailed description thereof is omitted.

[0194] The selection circuit (523) may include a first multiplexer (MUX11), a buffer (BK11), a decoder (DEC11), and a second multiplexer (MUX12).

[0195] The first multiplexer (MUX11) can output either one of the first and second control signals (CTRL1, CTRL2) as a control signal (11) based on the test mode signal (TM). For example, the first multiplexer (MUX11) can output the first control signal (CTRL1) among the first and second control signals (CTRL1, CTRL2) as a control signal (CTRL111) during the test mode, and can output the second control signal (CTRL2) among the first and second control signals (CTRL1, CTRL2) as a control signal (CTRL111) during the normal mode.

[0196] The buffer (BK11) can generate a signal based on the control signal (CTRL11) and the first enable signal (EN). For example, the buffer (BK11) can generate a signal (CTRL111) corresponding to the control signal (CTRL11) when the first enable signal (EN) is activated. On the other hand, the buffer (BK11) can maintain a default signal (CTRL111) regardless of the control signal (CTRL11) when the first enable signal (EN) is deactivated.

[0197] The decoder (DEC11) can generate a selection code signal (DO1) by decoding the signal (CTRL111). For example, if the duty cycle of the signal to be corrected (CCL11) needs to be reduced, the decoder (DEC11) can generate a selection code signal (DO1) to select either of the first and second operation clock signals (L11, L12) as the first period signal (CCL1). On the other hand, if the duty cycle of the signal to be corrected (CCL11) needs to be increased, the decoder (DEC11) can generate a selection code signal (DO1) to select either of the third and fourth operation clock signals (L13, L14) as the first period signal (CCL1). In addition, the decoder (DEC11) can generate first to fourth power gating signals (PG11 ~ PG14). For example, the decoder (DEC11) can disable the first power gating signal (PG11) and enable the second to fourth power gating signals (PG12 to PG14) when the first operation clock signal (L11) among the first to fourth operation clock signals (L11 to L14) is selected.

[0198] The second multiplexer (MUX12) can output any one of the first to fourth operation clock signals (L11 to L14) as the first period signal (CCL1) based on the selection code signal (DO1).

[0199] FIG. 33 shows a block diagram of the second duty cycle correction circuit (DCC2) illustrated in FIG. 31. It should be noted that the number of elements, the number of element groups, and the number of signals included in the second duty cycle correction circuit (DCC2) of FIG. 33 are described as examples for convenience of explanation and are not necessarily limited thereto.

[0200] Referring to FIG. 33, the second duty cycle correction circuit (DCC2) may include a delay circuit (525), a logic circuit (526), ​​and a selection circuit (527). Since the delay circuit (525) and the logic circuit (526) shown in FIG. 33 are identical to the delay circuit (125) and the logic circuit (126) shown in FIG. 9, a detailed description thereof is omitted.

[0201] The selection circuit (527) may include a first multiplexer (MUX21), a buffer (BK21), a decoder (DEC21), and a second multiplexer (MUX22).

[0202] The first multiplexer (MUX21) can output either one of the first and second control signals (CTRL1, CTRL2) as a control signal (CTRL22) based on the test mode signal (TM). For example, the first multiplexer (MUX21) can output the first control signal (CTRL1) among the first and second control signals (CTRL1, CTRL2) as a control signal (CTRL22) during the test mode, and can output the second control signal (CTRL2) among the first and second control signals (CTRL1, CTRL2) as a control signal (CTRL22) during the normal mode.

[0203] The buffer (BK21) can generate a signal (CTRL222) based on the control signal (CTRL22) and the second enable signal (ENB). For example, the buffer (BK21) can generate a signal (CTRL222) corresponding to the control signal (CTRL22) when the second enable signal (ENB) is activated. On the other hand, the buffer (BK21) can maintain a signal (CTRL222) that is set by default regardless of the control signal (CTRL22) when the second enable signal (ENB) is deactivated.

[0204] The decoder (DEC21) can generate a selection code signal (DO2) by decoding the signal (CTRL222). For example, if the duty cycle of the signal to be corrected (CCL22) needs to be reduced, the decoder (DEC21) can generate a selection code signal (DO2) to select either of the first and second operation clock signals (L21, L22) as the second period signal (CCL2). On the other hand, if the duty cycle of the signal to be corrected (CCL22) needs to be increased, the decoder (DEC21) can generate a selection code signal (DO2) to select either of the third and fourth operation clock signals (L23, L24) as the second period signal (CCL2). In addition, the decoder (DEC21) can generate first to fourth power gating signals (PG21 ~ PG24). For example, the decoder (DEC21) can disable the first power gating signal (PG21) and enable the second to fourth power gating signals (PG22 to PG24) when the first operation clock signal (L21) among the first to fourth operation clock signals (L21 to L24) is selected.

[0205] The second multiplexer (MUX22) can output any one of the first to fourth operation clock signals (L21 to L24) as the second period signal (CCL2) based on the selection code signal (DO2).

[0206] FIG. 34 shows a block diagram of the first controller (600) illustrated in FIG. 25.

[0207] Referring to FIG. 34, the controller (600) may include a comparison circuit (610) and a discrimination circuit (620).

[0208] The comparison circuit (610) can compare image data (IDT) and reference data (RDT) and generate a comparison signal (CMP). For example, the comparison circuit (610) can compare some or all of the digital values ​​included in the image data (IDT)—each corresponding to a digital signal (DOUT)—with the digital values ​​included in the reference data (RDT).

[0209] The determination circuit (620) can determine an error in the depth information based on a comparison signal (CMP) and generate a first control signal (CTRL1). For example, the determination circuit (620) can change the first control signal (CTRL1) if the result of determining the error in the depth information is a failure, and fix the first control signal (CTRL1) if the result of determining is a pass.

[0210] FIG. 35 shows a block diagram of the second controller (700) illustrated in FIG. 25.

[0211] Referring to FIG. 35, the second controller (700) may include a detection circuit (710) and a conversion circuit (720).

[0212] The detection circuit (710) can detect the duty cycle difference between the first period signal (CCL1) and the second period signal (CCL2). For example, the detection circuit (710) can detect the difference in the duty cycle by detecting the difference between the period during which the first period signal (CCL1) is at a logic high level (or logic low level) and the period during which the second period signal (CCL2) is at a logic high level (or logic low level) during one period. The detection circuit (710) can generate a detection signal (DET) corresponding to the result of detecting the duty cycle difference.

[0213] The conversion circuit (720) can generate a second control signal (CTRL2) corresponding to the detection signal (DET). For example, the conversion circuit (720) can convert the detection signal (DET) into a second control signal (CTRL2) which is a digital signal.

[0214] Hereinafter, the operation of an image sensing device according to a third embodiment of the present invention having the configuration as described above will be explained.

[0215] A third embodiment of the present invention represents the operation of an image sensing device including a corrector (520) shown in FIG. 27.

[0216] In the above test mode, the first controller (600) can statically generate a first control signal (CTRL1) based on image data (IDT) provided from the image sensor (500). For example, the first controller (600) can compare the image data (IDT) with reference data (RDT) and generate a first control signal (CTRL1) corresponding to the comparison result at least once.

[0217] In the above test mode, the image sensor (500) can correct the depth information based on the first control signal (CTRL). For example, the image sensor (500) can correct the depth information by eliminating the difference in duty cycle between the first periodic signal (CCL1) and the second periodic signal (CCL2). In particular, the corrector (520) included in the image sensor (500) can eliminate the difference in duty cycle between the first periodic signal (CCL1) and the second periodic signal (CCL2) based on the first control signal (CTRL) in the above test mode.

[0218] FIG. 36 shows a timing diagram to explain the operation of the corrector (520) illustrated in FIG. 27 according to an example.

[0219] Referring to FIG. 36, the corrector (520) can correct the duty cycle of the signal to be corrected (CCL11) based on the first control signal (CTRL1) and generate the first periodic signal (CCL1). That is, the corrector (520) can generate the first periodic signal (CCL1) having a positive duty cycle by correcting the duty cycle of the signal to be corrected (CCL11) according to the duty cycle of the second periodic signal (CCL2).

[0220] FIG. 37 shows a timing diagram to explain the operation of the corrector (520) illustrated in FIG. 27 according to another example.

[0221] Referring to FIG. 37, the corrector (520) can correct the duty cycle of the signal to be corrected (CCL11) based on the first control signal (CTRL1) and generate the first periodic signal (CCL1). That is, the corrector (520) can generate the first periodic signal (CCL1) having a negative duty cycle by correcting the duty cycle of the signal to be corrected (CCL11) according to the duty cycle of the second periodic signal (CCL2).

[0222] In the above normal mode, the second controller (700) can dynamically generate a second control signal (CTRL2) based on the first and second period signals (CCL1, CCL2) provided in real time from the image sensor (500). For example, the second controller (700) can detect the difference in duty cycle between the first period signal (CCL1) and the second period signal (CCL2) and generate a second control signal (CTRL2) corresponding to the detection result in real time.

[0223] In the above normal mode, the image sensor (500) can correct the depth information based on the second control signal (CTRL2). For example, the image sensor (500) can correct the depth information by eliminating the difference in duty cycle between the first periodic signal (CCL1) and the second periodic signal (CCL2). In particular, the corrector (520) included in the image sensor (500) can eliminate the difference in duty cycle between the first periodic signal (CCL1) and the second periodic signal (CCL2) based on the second control signal (CTRL) in the above normal mode. For example, the corrector (520) can generate a first periodic signal (CCL1) having a positive duty cycle by correcting the duty cycle of the signal to be corrected (CCL11) according to the duty cycle of the second periodic signal (CCL2) (see FIG. 36). Alternatively, the corrector (520) can generate a first periodic signal (CCL1) having a negative duty cycle by correcting the duty cycle of the signal to be corrected (CCL11) according to the duty cycle of the second periodic signal (CCL2) (see FIG. 37).

[0224] According to the third embodiment of the present invention, there is an advantage in that depth information can be corrected by easily eliminating the difference in duty cycle between the first and second periodic signals in test mode and normal mode.

[0225] Although the technical concept of the present invention has been specifically described according to the above embodiments, it should be noted that the embodiments described above are for illustrative purposes only and are not intended to be limiting. Furthermore, a person skilled in the art will understand that various embodiments are possible through various substitutions, modifications, and changes within the scope of the technical concept of the present invention. Explanation of the symbols

[0227] 100: Image sensor 200: Controller

Claims

Claim 1 An image sensing device comprising: an image sensor for generating first and second periodic signals based on a clock signal, correcting depth information by eliminating the difference in duty cycle between the first and second periodic signals based on a control signal, and generating image data according to the depth information; and a controller for analyzing errors in the depth information and generating the control signal based on the first and second periodic signals provided from the image sensor. Claim 2 In claim 1, the controller is an image sensing device that detects the difference in duty cycle between the first and second period signals based on the first and second period signals and generates the control signal corresponding to the detection result. Claim 3 An image sensing device according to claim 1, wherein the first periodic signal is a signal required to generate a light signal radiated to a subject, and the second periodic signal is a signal required to measure depth information. Claim 4 In claim 1, the image sensor comprises: an optical driver for radiating an optical signal to a subject based on the first periodic signal; a pixel driver for generating a driving signal based on the second periodic signal; a pixel array including at least one pixel for sensing an optical signal reflected from the subject based on the driving signal; and a compensator for generating the first periodic signal and the second periodic signal, each having a duty cycle based on the control signal and the clock signal. Claim 5 In paragraph 4, the corrector is an image sensing device that generates the first and second periodic signals in which the difference in duty cycle between the first and second periodic signals is removed. Claim 6 In claim 4, the image sensing device comprises: a first load that generates a signal to be corrected corresponding to the clock signal; a duty cycle correction circuit for correcting the duty cycle of the signal to be corrected according to the duty cycle of the second periodic signal based on the control signal and generating the first periodic signal; and a second load that generates the second periodic signal corresponding to the clock signal. Claim 7 In claim 4, the corrector comprises: a first load that generates a first periodic signal corresponding to the clock signal; a second load that generates a signal to be corrected corresponding to the clock signal; and a duty cycle correction circuit for correcting the duty cycle of the signal to be corrected according to the duty cycle of the first periodic signal based on the control signal and generating the second periodic signal; and an image sensing device. Claim 8 In claim 4, the image sensing device comprises: a first load that generates a first correction target signal corresponding to the clock signal; a first duty cycle correction circuit for correcting the duty cycle of the first correction target signal according to the duty cycle of the second period signal based on the control signal and the first enable signal and generating the first period signal; a second load that generates a second correction target signal corresponding to the clock signal; and a second duty cycle correction circuit for correcting the duty cycle of the second correction target signal according to the duty cycle of the first period signal based on the control signal and the second enable signal and generating the second period signal. Claim 9 In claim 1, the controller is an image sensing device that performs error analysis of the depth information in real time during normal mode and dynamically generates the control signal. Claim 10 An image sensing device according to claim 1, wherein the controller comprises: a detection circuit for detecting a duty cycle difference between the first periodic signal and the second periodic signal and generating a detection signal; and an output circuit for converting the detection signal into a digital signal and outputting the control signal. Claim 11 An image sensing device comprising: an image sensor for correcting depth information based on a control signal and generating image data according to the depth information; a comparison circuit for comparing the image data with reference data and generating a comparison signal; and a discrimination circuit for determining an error in the depth information based on the comparison signal and generating the control signal. Claim 12 An image sensing device according to claim 11, wherein the image sensor generates the first and second periodic signals based on a clock signal and corrects the depth information by eliminating the difference in duty cycle between the first and second periodic signals based on the control signal. Claim 13 In claim 11, the image sensor comprises: an optical driver for radiating an optical signal to a subject based on a first periodic signal; a pixel driver for generating a driving signal based on a second periodic signal; a pixel array including at least one pixel for sensing an optical signal reflected from the subject based on the driving signal; and a compensator for generating the first periodic signal and the second periodic signal, each having a duty cycle based on the control signal and the clock signal, an image sensing device. Claim 14 In paragraph 13, the corrector is an image sensing device that generates the first and second periodic signals in which the difference in duty cycle between the first and second periodic signals is removed. Claim 15 In claim 13, the image sensing device comprises: a first load that generates a signal to be corrected corresponding to the clock signal; a duty cycle correction circuit for correcting the duty cycle of the signal to be corrected according to the duty cycle of the second periodic signal based on the control signal and generating the first periodic signal; and a second load that generates the second periodic signal corresponding to the clock signal. Claim 16 In claim 13, the image sensing device comprises: a first load that generates a first periodic signal corresponding to the clock signal; a second load that generates a signal to be corrected corresponding to the clock signal; and a duty cycle correction circuit for correcting the duty cycle of the signal to be corrected according to the duty cycle of the first periodic signal based on the control signal and generating the second periodic signal. Claim 17 In claim 13, the image sensing device comprises: a first load that generates a first correction target signal corresponding to the clock signal; a first duty cycle correction circuit for correcting the duty cycle of the first correction target signal according to the duty cycle of the second period signal based on the control signal and the first enable signal and generating the first period signal; a second load that generates a second correction target signal corresponding to the clock signal; and a second duty cycle correction circuit for correcting the duty cycle of the second correction target signal according to the duty cycle of the first period signal based on the control signal and the second enable signal and generating the second period signal. Claim 18 An image sensing device according to claim 11, wherein the controller includes the comparison circuit and the discrimination circuit, and the controller performs the error analysis operation of the depth information a preset number of times during test mode and finally generates the control signal statically. Claim 19 delete Claim 20 An image sensing device comprising: an image sensor for correcting depth information based on first and second control signals and generating image data according to said depth information; a first controller for analyzing errors in said depth information based on said image data and generating said first control signal in a test mode; and a second controller for analyzing errors in said depth information based on first and second periodic signals provided from said image sensor and generating said second control signal in a normal mode. Claim 21 delete Claim 22 delete Claim 23 delete Claim 24 delete Claim 25 delete Claim 26 delete Claim 27 delete Claim 28 delete Claim 29 delete Claim 30 delete Claim 31 delete Claim 32 delete Claim 33 delete Claim 34 delete Claim 35 delete Claim 36 delete Claim 37 delete Claim 38 delete Claim 39 delete Claim 40 delete Claim 41 delete Claim 42 delete Claim 43 delete Claim 44 delete Claim 45 delete Claim 46 delete Claim 47 delete Claim 48 delete Claim 49 delete Claim 50 delete Claim 51 delete Claim 52 delete Claim 53 delete Claim 54 delete Claim 55 delete Claim 56 delete Claim 57 delete Claim 58 delete Claim 59 delete Claim 60 delete Claim 61 delete Claim 62 delete Claim 63 delete Claim 64 delete Claim 65 delete Claim 66 delete Claim 67 delete Claim 68 delete Claim 69 delete Claim 70 delete Claim 71 delete Claim 72 delete Claim 73 delete Claim 74 delete

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