Data transfer circuits of nonvolatile memory devices and nonvolatile memory devices including the same

Abstract

A data transfer circuit of a non-volatile memory device comprises a plurality of first repeaters, a plurality of second repeaters, and a plurality of signal lines. The plurality of first repeaters are connected to a first circuit element disposed in the data input / output path of the non-volatile memory device. The plurality of second repeaters are connected to a second circuit element disposed spaced apart from the first circuit element in the data input / output path of the non-volatile memory device. The plurality of signal lines connect the plurality of first repeaters and the plurality of second repeaters and comprise a first group of signal lines and a second group of signal lines that are alternately disposed. The plurality of first repeaters include a first group of repeaters activated in a first operating mode and a second group of repeaters activated in a second operating mode whose operating interval does not overlap with the first operating mode. The plurality of second repeaters includes a third group of repeaters that are activated in the first operating mode and connected to the first group of repeaters through the signal lines of the first group, and a fourth group of repeaters that are activated in the second operating mode and connected to the second group of repeaters through the signal lines of the second group. The signal lines of the second group are floating in the first operating mode, and the signal lines of the first group are floating in the second operating mode.

Description

Technology Field

[0001] The present invention relates to a semiconductor memory device, and more specifically, to a data transfer circuit of a non-volatile memory device and a non-volatile memory device including the same. Background Technology

[0002] Semiconductor memory devices for storing data can be broadly classified into volatile memory devices and non-volatile memory devices. Volatile memory devices, such as DRAM (Dynamic Random Access Memory), in which data is stored through the charging or discharging of cell capacitors, retain stored data as long as power is applied, but the stored data is lost when the power is cut off. On the other hand, non-volatile memory devices can store data even when the power is cut off. Volatile memory devices are mainly used as main memory in computers, while non-volatile memory devices are used as high-capacity memory for storing programs and data in a wide range of application devices, such as computers and portable communication devices.

[0003] Recently, non-volatile memory devices in which memory cells are stacked in three dimensions, such as vertical NAND flash memory devices, are being actively researched to improve the integration density of semiconductor memory devices.

[0004] The current consumption of signal lines transmitting data in non-volatile memory devices is significant. The problem to be solved

[0005] One objective of the present invention is to provide a data transfer circuit for a non-volatile memory device capable of reducing current consumption.

[0006] One objective of the present invention is to provide a non-volatile memory device capable of reducing current consumption. means of solving the problem

[0007] A data transfer circuit of a non-volatile memory device according to embodiments of the present invention comprises a plurality of first repeaters, a plurality of second repeaters, and a plurality of signal lines. The plurality of first repeaters are connected to a first circuit element disposed in a data input / output path of the non-volatile memory device. The plurality of second repeaters are connected to a second circuit element disposed spaced apart from the first circuit element in the data input / output path of the non-volatile memory device. The plurality of signal lines connect the plurality of first repeaters and the plurality of second repeaters and have a first group of signal lines and a second group of signal lines that are alternately disposed. The plurality of first repeaters include a first group of repeaters activated in a first operating mode and a second group of repeaters activated in a second operating mode whose operating interval does not overlap with the first operating mode. The plurality of second repeaters includes a third group of repeaters that are activated in the first operating mode and connected to the first group of repeaters through the signal lines of the first group, and a fourth group of repeaters that are activated in the second operating mode and connected to the second group of repeaters through the signal lines of the second group. The signal lines of the second group are floating in the first operating mode, and the signal lines of the first group are floating in the first operating mode.

[0008] A non-volatile memory device according to embodiments of the present invention comprises a memory cell array including a plurality of memory cells, a page buffer circuit, a data input / output circuit, a data transfer circuit, and a control circuit. The page buffer circuit is connected to the memory cell array through a plurality of bit lines. The data input / output circuit exchanges data with an external memory controller. The data transfer circuit is connected between the data input / output circuit and the page buffer circuit, and in a first operation mode, provides the data provided by the data input / output circuit to the page buffer circuit, and in a second operation mode, in which the operation interval does not overlap with the first operation mode, provides the data provided by the page buffer circuit to the data input / output circuit. The control circuit controls the page buffer circuit and the data transfer circuit. In response to a first power gating control signal and a second power gating signal from the control circuit, the data transfer circuit floats some of the signal lines that do not transmit data among a plurality of signal lines included internally in each of the first operation mode and the second operation mode.

[0009] A data transfer circuit of a non-volatile memory device according to embodiments of the present invention comprises a plurality of first repeaters, a plurality of second repeaters, and a plurality of signal lines. The plurality of first repeaters are connected to a first circuit element disposed in a data input / output path of the non-volatile memory device. The plurality of second repeaters are connected to a second circuit element disposed spaced apart from the first circuit element in the data input / output path of the non-volatile memory device. The plurality of signal lines connect the plurality of first repeaters and the plurality of second repeaters and have a first group of signal lines and a second group of signal lines that are alternately disposed. The plurality of first repeaters include a first group of repeaters activated in a first operating mode and a second group of repeaters activated in a second operating mode whose operating interval does not overlap with the first operating mode. The plurality of second repeaters includes a third group of repeaters that are activated in the first operating mode and connected to the first group of repeaters through the first group of signal lines, and a fourth group of repeaters that are activated in the second operating mode and connected to the second group of repeaters through the second group of signal lines. In the second operating mode, the first group of repeaters floats an output node connected to the first group of signal lines in response to a first power gating signal. In the first operating mode, the fourth group of repeaters floats an output node connected to the second group of signal lines in response to a second power gating signal. Effects of the invention

[0010] According to embodiments of the present invention, in a first operation mode, data is transmitted to a page buffer circuit through a first group of signal lines, and a second group of signal lines alternately arranged with the first group of signal lines are floated using repeaters of a second group and repeaters of a fourth group, and in a second operation mode, read data is transmitted to a data input / output circuit through the second group of signal lines, and a first group of signal lines are floated using repeaters of a first group and repeaters of a third group, thereby reducing the capacitance of the signal lines transmitting data and reducing current consumption. Brief explanation of the drawing

[0011] FIG. 1 is a block diagram showing a non-volatile memory device according to embodiments of the present invention. FIG. 2 is a block diagram showing a memory system including the non-volatile memory device of FIG. 1 according to embodiments of the present invention. FIG. 3 schematically shows the structure of the non-volatile memory device of FIG. 1 according to embodiments of the present invention. FIG. 4 is a block diagram showing an example of a memory cell array in a non-volatile memory device of FIG. 1. Figure 5 is a circuit diagram showing one of the memory blocks of Figure 4. Figure 6 shows an example of the structure of one cell string of the memory block of Figure 5. FIG. 7 illustrates an exemplary connection between the memory cell array and the page buffer circuit of FIG. 1 according to embodiments of the present invention. FIG. 8 illustrates a page buffer according to embodiments of the present invention in detail. FIG. 9 is a circuit diagram showing a cache unit according to embodiments of the present invention. FIG. 10 shows a data transfer circuit in a non-volatile memory device of FIG. 1 according to embodiments of the present invention. FIG. 11a is a circuit diagram showing the configuration of one of the first group of repeaters in the data transmission circuit of FIG. 10 according to embodiments of the present invention. FIG. 11b is a circuit diagram showing the configuration of one of the repeaters of the fourth group in the data transmission circuit of FIG. 10 according to embodiments of the present invention. FIG. 12 shows the operation of the repeater of FIG. 11a in a second operation mode according to embodiments of the present invention. FIG. 13 shows the operation of the data transfer circuit of FIG. 10 in a first operation mode according to embodiments of the present invention. Figure 14 shows data transferred to the page buffer circuit when the data transfer circuit operates as in Figure 13. FIG. 15 shows a first power gating signal and a second power gating signal when the data transmission circuit asynchronously transmits even data bits and odd data bits as in FIG. 14. FIG. 16 shows the operation of the data transfer circuit of FIG. 10 in a second operation mode according to embodiments of the present invention. Figure 17 shows data transferred to the page buffer circuit when the data transfer circuit operates as in Figure 16. FIG. 18 shows a first power gating signal and a second power gating signal when the data transmission circuit asynchronously transmits even data bits and odd data bits as in FIG. 17. FIG. 19 is a block diagram showing a non-volatile memory device according to embodiments of the present invention. FIG. 20 is a block diagram showing a non-volatile memory device according to embodiments of the present invention. FIG. 21 shows in detail the interface area of ​​FIG. 20 according to embodiments of the present invention. FIG. 22 is a flowchart illustrating a method of operation of a non-volatile memory device according to embodiments of the present invention. FIG. 23 is a cross-sectional view showing a non-volatile memory device according to embodiments of the present invention. FIG. 24 is a block diagram showing an electronic system including a semiconductor device according to embodiments of the present invention. Specific details for implementing the invention

[0012] Hereinafter, preferred embodiments of the present invention will be described in more detail with reference to the attached drawings. Identical components in the drawings are given the same reference numerals, and redundant descriptions of identical components are omitted.

[0013] FIG. 1 is a block diagram showing a non-volatile memory device in embodiments of the present invention.

[0014] Referring to FIG. 1, a non-volatile memory device (50) may include a memory cell array (100) and peripheral circuits (200). Peripheral circuits (200) may include a page buffer circuit (210), a control circuit (220), a voltage generator (230), an address decoder (240), a data transfer circuit (300), and a data input / output circuit (250). Although not shown in FIG. 1, peripheral circuits (200) may further include an input / output interface, column logic, a pre-decoder, a temperature sensor, etc.

[0015] The memory cell array (100) can be connected to an address decoder (240) via a string select line (SSL), a plurality of word lines (WLs), and a ground select line (GSL). Additionally, the memory cell array (100) can be connected to a page buffer circuit (210) via a plurality of bit lines (BLs). The memory cell array (100) may include a plurality of non-volatile memory cells connected to the plurality of word lines (WLs) and the plurality of bit lines (BLs).

[0016] In an embodiment, the memory cell array (100) may be a three-dimensional memory cell array formed in a three-dimensional structure (or vertical structure) on a substrate. In this case, the memory cell array (200) may include vertical memory cell strings comprising a plurality of memory cells formed by stacking each other.

[0017] The control circuit (220) receives a control signal (CTRL), a command signal (CMD), and an address signal (ADDR) from a memory controller (20 in FIG. 2), and can control the erase loop, program loop, and read operation of the non-volatile memory device (50) based on the control signal (CTRL), the command signal (CMD), and the address signal (ADDR).

[0018] For example, the control circuit (220) may generate control signals (CTLs) for controlling the voltage generator (230) based on the command signal (CMD), a page buffer control signal (PBCTL) for controlling the page buffer circuit (210), and a first power gating signal (PGS1) and a second power gating signal (PGS2) for controlling the data transfer circuit (300), and may generate a row address (R_ADDR) and a column address (C_ADDR) based on the low address signal (ADDR). The control circuit (220) may provide the row address (R_ADDR) to the address decoder (240) and provide the column address (C_ADDR) to the data input / output circuit (250). The control circuit (220) may include a status signal generator (225) that generates a status signal (or ready / busy) signal (RnB) indicating the operating state of the non-volatile memory device (50).

[0019] The address decoder (240) can be connected to the memory cell array (100) through a string select line (SSL), a plurality of word lines (WLs), and a ground select line (GSL). During a program operation or a read operation, the address decoder (240) can determine one of the plurality of word lines (WLs) as the selected word line based on a row address (R_ADDR) provided by the control circuit (450), and determine the remaining word lines among the plurality of word lines (WLs), excluding the selected word line, as non-selected word lines.

[0020] The voltage generator (230) can generate wordline voltages (VWLs) required for the operation of the non-volatile memory device (50) using power (PWR) based on control signals (CTLs) provided from the control circuit (220). The wordline voltages (VWLs) generated from the voltage generator (230) can be applied to a plurality of wordlines (WLs) through an address decoder (240).

[0021] For example, during an erase operation, the voltage generator (230) may apply an erase voltage to the wells of the memory block and apply a ground voltage to all word lines of the memory block. During an erase verification operation, the voltage generator (230) may apply an erase verification voltage to all word lines of a single memory block or apply an erase verification voltage on a word-line basis.

[0022] For example, during a program operation, the voltage generator (230) may apply a program voltage to selected word lines and a program pass voltage to non-selected word lines. Additionally, during a program verification operation, the voltage generator (230) may apply a program verification voltage to selected word lines and a verification pass voltage to non-selected word lines. Additionally, during a read operation, the voltage generator (230) may apply a read voltage to selected word lines and a read pass voltage to non-selected word lines.

[0023] The page buffer circuit (210) can be connected to the memory cell array (100) through a plurality of bit lines (BLs). The page buffer circuit (210) may include a plurality of page buffers (PB) and a page buffer driver (PBD, 215). The page buffer circuit (210) can temporarily store data to be programmed in a selected page during a program operation and can temporarily store data read from a selected page during a read operation. The page buffer driver (215) can transfer program data provided by the data transfer circuit (300) to a number of page buffers (PB) during a program operation and provide data provided by the plurality of page buffers (PB) to the data transfer circuit (300) during a read operation.

[0024] In the embodiment, the page buffer units (e.g., PBU0 to PBUn in FIG. 7) included in each of the plurality of page buffers (PB) and the cache latches (e.g., CL0 to CLn in FIG. 7) included in each of the plurality of page buffers (PB) may be spaced apart from each other and have a separated structure. Accordingly, the degree of freedom for the wiring placed above the page buffer units may be improved and the complexity of the layout may be reduced. In addition, by placing the cache latches adjacent to the data input / output lines, the distance between the carry latches and the data input / output lines may be reduced, thereby improving the data input / output speed.

[0025] The data transmission circuit (300) may include first repeaters (310), second repeaters (350), and signal lines (380).

[0026] The first repeaters (310) are connected to the data input / output circuit (250), the second repeaters (350) are connected to the page buffer driver (215) of the page buffer circuit (210), and the signal lines (380) can connect the first repeaters (310) and the second repeaters (350) to each other.

[0027] The first repeaters (310) may include a first group of repeaters activated in a first operation mode and a second group of repeaters activated in a second operation mode. The second repeaters (350) may include a third group of repeaters activated in a first operation mode and connected to the first group of repeaters through the signal lines (380) of the first group of repeaters, and a fourth group of repeaters activated in a second operation mode and connected to the second group of repeaters through the signal lines (380) of the second group of repeaters.

[0028] The signal lines of the first group and the signal lines of the second group can be arranged alternately.

[0029] The signal lines of the second group are floated in the first operating mode to reduce the capacitance of each of the signal lines of the first group, and the signal lines of the first group are floated in the second operating mode to reduce the capacitance of each of the signal lines of the second group, thereby reducing the current consumed in the signal lines (380) during data transmission in the first operating mode and the second operating mode.

[0030] In the second operation mode, the repeaters of the first group may float the output nodes connected to the signal lines of the first group in response to the first power gating signal (PGS1), and the repeaters of the third group may float the input nodes connected to the signal lines of the first group in response to the first power gating signal (PGS1).

[0031] In the first operating mode, the repeaters of the second group may float the output nodes connected to the signal lines of the second group in response to the second power gating signal (PGS2), and the repeaters of the fourth group may float the input nodes connected to the signal lines of the fourth group in response to the second power gating signal (PGS2).

[0032] In the embodiment, the first operation mode may correspond to a write operation, and the second operation mode may correspond to a read operation. In addition, the first operation mode and the second operation mode may not overlap with each other. That is, the operation interval of the first operation mode and the operation interval of the second operation mode may not overlap with each other (they may not overlap).

[0033] Although the data transfer circuit (300) in FIG. 1 is described as being connected between the data input / output circuit (250) and the page buffer circuit (210), the data transfer circuit (300) is positioned between the first circuit element and the second circuit element in the data input / output path within the non-volatile memory device (50), so as to be able to transfer data between the first circuit element and the second circuit element.

[0034] When the data transfer circuit (300) is positioned between a first circuit element and a second circuit element in a data input / output path within a non-volatile memory device (50), the first operation mode may correspond to an operation of transferring data from the first circuit element to the second circuit element, and the second operation mode may correspond to an operation of transferring data from the second circuit element to the first circuit element.

[0035] The data input / output circuit (250) can be connected to the page buffer circuit (210) through the data transfer circuit (300). During a program operation, the data input / output circuit (250) receives program data (DATA) from the memory controller (20 in FIG. 2) and can provide the program data (DATA) to the page buffer circuit (210) through the data transfer circuit (300) based on the column address (C_ADDR) provided by the control circuit (220). During a read operation, the data input / output circuit (250) receives the read data (DATA) stored in the page buffer circuit (210) through the data transfer circuit (300) based on the column address (C_ADDR) provided by the control circuit (220) and can provide the read data (DATA) to the memory controller (20).

[0036] The data input / output circuit (250) may include a serializer (SERDES, 255). The serializer (255) may parallelize program data (DATA) during a write operation and provide it to the data transfer circuit (300), and serialize read data (DATA) provided from the data transfer circuit (300) during a read operation and provide it to the memory controller (20).

[0037] FIG. 2 is a block diagram showing a memory system including the non-volatile memory device of FIG. 1 according to embodiments of the present invention.

[0038] Referring to FIG. 2, the memory system (10) may include a memory controller (20) and a non-volatile memory device (NVM, 50).

[0039] The memory controller (20) controls the operation of the non-volatile memory device (50) by applying a control signal (CTRL), a command (CMD), and an address (ADDR) to the non-volatile memory device (50), and can exchange data (DATA) with the non-volatile memory device (50). The non-volatile memory device (50) can indicate the operating state of the non-volatile memory device (50) by applying a status signal (RnB) to the memory controller (20). For example, if the status signal (RnB) is at a high level, it indicates that the non-volatile memory device (50) is in a state where it can receive a command from the memory controller (20).

[0040] FIG. 3 schematically shows the structure of the non-volatile memory device of FIG. 1 according to embodiments of the present invention.

[0041] Referring to FIG. 2, a non-volatile memory device (50) may include a first semiconductor layer (L1) and a second semiconductor layer (L2), and the first semiconductor layer (L1) may be stacked in a vertical direction (VD) with respect to the second semiconductor layer (L2). Specifically, the second semiconductor layer (L2) may be positioned below the first semiconductor layer (L1) in a vertical direction (VD), and accordingly, the second semiconductor layer (L2) may be positioned close to the substrate.

[0042] In one embodiment, the memory cell array (100) of FIG. 1 may be formed on a first semiconductor layer (L1), and the peripheral circuit (200) of FIG. 1 may be formed on a second semiconductor layer (L2). Accordingly, the non-volatile memory device (50) may have a structure in which the memory cell array (100) is placed on top of the peripheral circuit (200), i.e., a Cell Over Periphery (COP) structure. The COP structure can effectively reduce the horizontal area and improve the integration density of the non-volatile memory device (50).

[0043] In one embodiment, the second semiconductor layer (L2) may include a substrate, and a peripheral circuit (200) may be formed on the second semiconductor layer (L2) by forming transistors and metal patterns for wiring the transistors on the substrate. After the peripheral circuit (200) is formed on the second semiconductor layer (L2), a first semiconductor layer (L1) including a memory cell array (100) may be formed, and metal patterns may be formed to electrically connect the word lines (WL) and bit lines (BL) of the memory cell array (100) with the peripheral circuit (200) formed on the second semiconductor layer (L2). For example, the bit lines (BL) may extend in a first horizontal direction (HD1), and the word lines (WL) may extend in a second horizontal direction (HD2).

[0044] As the semiconductor process develops, as the number of memory cells placed in the memory cell array (100) increases, that is, as the number of stacked word lines (WL) increases, the area of ​​the memory cell array (100) decreases, and accordingly, the area of ​​the peripheral circuit (200) also decreases. According to the present embodiment, in order to reduce the area of ​​the region occupied by the page buffer circuit (210), the page buffer circuit (210) has a structure in which the page buffer unit and the cache latch are separated, and the sensing nodes included in each page buffer unit can be commonly connected to a combined sensing node.

[0045] FIG. 4 is a block diagram showing an example of a memory cell array in a non-volatile memory device of FIG. 1.

[0046] Referring to FIG. 4, the memory cell array (100) includes a plurality of memory blocks (BLK1 to BLKz, where z is a natural number greater than or equal to 3) arranged along a plurality of directions (HD1, HD2, VD). In an embodiment, the memory blocks are selected by an address decoder (240) shown in FIG. 1. For example, the address decoder (240) can select a memory block (BLK) corresponding to a block address among the memory blocks (BLK1 to BLKz).

[0047] Figure 5 is a circuit diagram showing one (BLKi) of the memory blocks (BLK1~BLKz) of Figure 4.

[0048] The memory block (BLKi) illustrated in FIG. 5 represents a three-dimensional memory block formed in a three-dimensional structure on a substrate (SUB). For example, a plurality of memory cell strings included in the memory block (BLKi) can be stacked in a direction perpendicular to the substrate (SUB) (PD).

[0049] Referring to FIG. 5, a memory block (BLKi) may include a plurality of memory cell strings (or NAND strings, NS11 to NS33) connected between bit lines (BL1, BL2, BL3) and a common source line (CSL). Each of the plurality of memory cell strings (NS11 to NS33) may include a string select transistor (SST), a plurality of memory cells (MC1, MC2, ..., MC8), and a ground select transistor (GST).

[0050] A string select transistor (SST) can be connected to corresponding string select lines (SSL1, SSL2, SSL3). Multiple memory cells (MC1, MC2, ..., MC8) can each be connected to corresponding word lines (WL1, WL2, ..., WL8). A ground select transistor (GST) can be connected to corresponding ground select lines (GSL1, GSL2, GSL3). A string select transistor (SST) is connected to corresponding bit lines (BL1, BL2, BL3), and a ground select transistor (GST) can be connected to a common source line (CSL).

[0051] Word lines of the same height (e.g., WL1) are connected in common, and ground selection lines (GSL1, GSL2, GSL3) and string selection lines (SSL1, SSL2, SSL3) can be separated respectively.

[0052] Figure 6 shows an example of the structure of one cell string of the memory block of Figure 5.

[0053] Referring to FIGS. 5 and 6, the cell string (NS11) may be provided with a pillar (PL) that extends perpendicular to the substrate (SUB) and contacts the substrate (SUB). The ground selection line (GSL1), word lines (WL1–WL8), and string selection line (SSL1) shown in FIG. 6 may each be formed of conductive materials parallel to the substrate (SUB), such as metallic materials. The pillar (PL) may contact the substrate (SUB) by penetrating the conductive materials forming the ground selection line (GSL1), word lines (WL1–WL8), and string selection line (SSL1).

[0054] In FIG. 6, a cross-sectional view along the cutting line (A-A') is also shown. For example, a cross-sectional view of a first memory cell (MC1) corresponding to a first word line (WL1) is shown. The pillar (PL) may include a cylindrical body (BD). An air gap (AG) may be provided inside the body (BD).

[0055] The body (BD) comprises P-type silicon and may be a region where a channel is formed. The pillar (PL) may further include a cylindrical tunnel insulating film (TI) surrounding the body (BD) and a cylindrical charge trapping film (CT) surrounding the tunnel insulating film (TI). A blocking insulating film (BI) may be provided between the first word line (WL1) and the pillar (PL). The body (BD), the tunnel insulating film (TI), the charge trapping film (CT), the blocking insulating film (BI), and the first word line (WL1) may be charge trapping transistors formed in a direction perpendicular to the substrate (SUB) or the upper surface of the substrate (SUB). The string select transistor (SST), the ground select transistor (GST), and other memory cells may have the same structure as the first memory cell (MC1).

[0056] FIG. 7 illustrates an exemplary connection between the memory cell array and the page buffer circuit of FIG. 1 according to embodiments of the present invention.

[0057] Referring to FIG. 7, the memory cell array (100) may include first to n+1 NAND strings (NS0 to NSn), and each of the first to n+1 NAND strings (NS0 to NSn) may include a ground select transistor (GST) connected to a ground select line (GSL), a plurality of memory cells (MC) each connected to a plurality of word lines (WL0 to WLm), and a string select transistor (SST) connected to a string select line (SSL), and the ground select transistor (GST), the plurality of memory cells (MC), and the string select transistor (SST) may be connected in series with each other. Here, m is a positive integer.

[0058] The page buffer circuit (210) may include first to n+1 page buffer units (PBU0 to PBUn). The first page buffer unit (PB0) may be connected to the first NAND string (NS0) through the first bit line (BL0), and the n+1 page buffer unit (PBUn) may be connected to the n+1 NAND string (NSn) through the n+1 bit line (BLn). Here, n is a positive integer. For example, n may be 7, and the page buffer circuit (210) may have a structure in which eight page buffer units (PBU0 to PBUn) are arranged in a row. For example, the first to n+1 page buffer units (PBU0 to PBUn) may be arranged in a row along the extension direction of the first to n+1 bit lines (BL0 to BLn).

[0059] The page buffer circuit (210) may further include first to n+1 cache latches (CL0 to CLn) corresponding to each of the first to n+1 page buffer units (PBU0 to PBUn). The page buffer circuit (210) may have a structure in which eight cache latches (CL0 to CLn) are arranged in a row. For example, the first to n+1 cache latches (CL0 to CLn) may be arranged in a row along the extension direction of the first to n+1 bit lines (BL0 to BLn).

[0060] Each of the sensing nodes of the first to n+1 page buffer units (PBU0 to PBUn) can be commonly connected to a combined sensing node (SOC). Additionally, the first to n+1 cache latches (CL0 to CLn) can be commonly connected to a combined sensing node (SOC). Accordingly, the first to n+1 page buffer units (PBU0 to PBUn) can be connected to the first to n+1 cache latches (CL0 to CLn) through the combined sensing node (SOC).

[0061] FIG. 8 illustrates a page buffer according to embodiments of the present invention in detail.

[0062] Referring to FIG. 8, the page buffer (PB) may correspond to an example of the page buffer (PB) of FIG. 1. The page buffer (PB) may include a page buffer unit (PBU) and a cache unit (CU). The cache unit (CU) includes a cache latch (C-LATCH, CL), and since the cache latch (CL) is connected to a data input / output line, the cache unit (CU) may be placed adjacent to the data input / output line. Accordingly, the page buffer unit (PBU) and the cache unit (CU) may be placed spaced apart from each other, and the page buffer (PB) may have a separated structure of the page buffer unit (PBU) and the cache unit (CU).

[0063] The Page Buffer Unit (PBU) may include a Main Unit (MU). The Main Unit (MU) may include the main transistors within the Page Buffer (PB). The Page Buffer Unit (PBU) may further include a Bitline Select Transistor (TR_hv) connected to a Bitline (BL) and driven by a Bitline Select Signal (BLSLT). The Bitline Select Transistor (TR_hv) may be implemented as a High Voltage Transistor, and accordingly, the Bitline Select Transistor (TR_hv) may be placed in a well region different from the Main Unit (MU), namely, a High Voltage Unit (HVU).

[0064] The main unit (MU) may include a sensing latch (S-LATCH) (SL), a force latch (F-LATCH) (FL), an upper bit latch (M-LATCH) (ML), and a lower bit latch (L-LATCH) (LL). According to an embodiment, the sensing latch (SL), the force latch (FL), the upper bit latch (ML), or the lower bit latch (LL) may be referred to as "main latch". The main unit (MU) may further include a precharge circuit (PC) capable of controlling a precharge operation for a bitline (BL) or a sensing node (SO) based on a bitline clamping control signal (BLCLAMP), and may further include a transistor (PM') driven by a bitline setup signal (BLSETUP).

[0065] The sensing latch (SL) can store the data stored in the memory cell or the sensing result of the threshold voltage of the memory cell during a read or program verification operation. Additionally, the sensing latch (SL) can be used to apply a program bitline voltage or a program prohibition voltage to the bitline (BL) during a program operation. The force latch (FL) can be used to improve the threshold voltage dispersion during a program operation. Specifically, the force latch (FL) stores force data. The force data is initially set to '1' and can be inverted to '0' when the threshold voltage of the memory cell enters a forcing region that falls short of the target region. By utilizing the force data, the bitline voltage can be controlled during the program execution operation, and the program threshold voltage dispersion can be formed more narrowly.

[0066] The upper bit latch (ML), lower bit latch (LL), and cache latch (CL) can be utilized to store data input from the outside during a program operation and may be referred to as "data latches." When 3 bits of data are programmed into a single memory cell, the 3 bits of data can be stored in the upper bit latch (ML), lower bit latch (LL), and cache latch (CL), respectively. Until the programming of the memory cell is completed, the upper bit latch (ML), lower bit latch (LL), and cache latch (CL) can retain the stored data. Additionally, during a read operation, the cache latch (CL) can receive data read from the memory cell from the sensing latch (SL) and output it externally through the data input / output line.

[0067] Additionally, the main unit (MU) may further include first to fourth transistors (NM1 to NM4). The first transistor (NM1) may be connected between the sensing node (SO) and the sensing latch (SL) and may be driven by a ground control signal (SOGND). The second transistor (NM2) may be connected between the sensing node (SO) and the force latch (FL) and may be driven by a force monitoring signal (MON_F). The third transistor (NM3) may be connected between the sensing node (SO) and the upper bit latch (ML) and may be driven by an upper bit monitoring signal (MON_M). The fourth transistor (NM4) may be connected between the sensing node (SO) and the lower bit latch (LL) and may be driven by a lower bit monitoring signal (MON_L).

[0068] Additionally, the main unit (MU) may further include fifth and sixth transistors (NM5, ​​NM6) connected in series between the bitline select transistor (TV_hv) and the sensing node (SO). The fifth transistor (NM5) may be driven by a bitline shut-off signal (BLSHF), and the sixth transistor (NM6) may be driven by a bitline connection control signal (CLBLK). Additionally, the main unit (MU) may further include a precharge transistor (PM). The precharge transistor (PM) is connected to the sensing node (SO), is driven by a load signal (LOAD), and precharges the sensing node (SO) to a precharge level during the precharge period.

[0069] In this embodiment, the main unit (MU) may further include a pair of pass transistors connected to a sensing node (SO), namely, first and second pass transistors (TR, TR'). According to the embodiment, the first and second pass transistors (TR, TR') may be referred to as "first and second sensing node connection transistors." The first and second pass transistors (TR, TR') may be driven according to a pass control signal (SO_PASS). According to the embodiment, the pass control signal (SO_PASS) may be referred to as a "sensing node connection control signal." Specifically, the first pass transistor (TR) may be connected between the first terminal (SOC_U) and the sensing node (SO), and the second pass transistor (TR') may be connected between the sensing node (SO) and the second terminal (SOC_D).

[0070] For example, if the page buffer unit (PBU) is the second page buffer unit (PBU1) of FIG. 7, the first terminal (SOC_U) can be connected to one end of a pass transistor included in the first page buffer unit (PBU0), and the second terminal (SOC_D) can be connected to one end of a pass transistor included in the third page buffer unit (PBU3). Thus, the sensing node (SO) can be electrically connected to the combined sensing node (SOC) through the pass transistors included in each of the third to n+1 page buffer units (PBU2 to PBUn).

[0071] The page buffer (PB) verifies whether a selected memory cell among the memory cells included in the NAND string connected to the bitline (BL) is programmed during a program operation. Specifically, the page buffer (PB) stores data detected through the bitline (BL) in the sensing latch (SL) during the program verification operation. Depending on the detected data stored in the sensing latch (SL), the upper bit latch (ML) and lower bit latch (LL), where the target data is stored, are configured. For example, if the detected data indicates that the program is complete, the upper bit latch (ML) and lower bit latch (LL) are switched to an inhibit setting for the selected memory cell in the subsequent program loop. The cache latch (CL) can temporarily store input data provided from the outside. During a program operation, the target data stored in the cache latch (CL) can be stored in the upper bit latch (ML) and lower bit latch (LL).

[0072] FIG. 9 is a circuit diagram showing a cache unit (CU) according to embodiments of the present invention.

[0073] Referring to FIGS. 8 and FIGS. 9 together, the cache unit (CU) may include a monitor transistor (NM7) and a cache latch (CL), and the cache latch (CL) may include first and second inverters (INV1, INV2), a dump transistor (132), and transistors (131, 133 to 135). The monitor transistor (NM7) is driven according to a cache monitoring signal (MON_C) and can control the connection between the coupled sensing node (SOC) and the cache latch (CL).

[0074] The first inverter (INV1) is connected between the first node (ND1) and the second node (ND2), and the second inverter (INV2) is connected between the second node (ND2) and the first node (ND1), and the first and second inverters (INV1, INV2) can form a latch. A transistor (131) has a gate connected to a combined sensing node (SOC). A dump transistor (132) can be driven by a dump signal (Dump_C) and can transfer data stored in a cache latch (CL) to a main latch in a page buffer unit (PBU), e.g., a sensing latch (SL). A transistor (133) can be driven by a data signal (DI), a transistor (134) can be driven by a data inversion signal (nDI), and a transistor (135) can be driven by a write control signal (DIO_W). When the write control signal (DIO_W) is activated, the voltage levels of the first and second nodes (ND1, ND2) can be determined according to the data signal (DI) and the data inversion signal (nDI).

[0075] The cache unit (CU) can be connected to the data input / output line (RDi) through transistors (136, 137). The transistor (136) has a gate connected to the second node (ND2) and can be turned on or turned off depending on the voltage level of the second node (ND2). The transistor (137) can be driven by a read control signal (DIO_R). When the read control signal (DIO_R) is activated and the transistor (137) is turned on, the voltage level of the data input / output line (RDi) can be determined to be '1' or '0' depending on the state of the cache latch (CL).

[0076] FIG. 10 shows a data transfer circuit in a non-volatile memory device of FIG. 1 according to embodiments of the present invention.

[0077] Referring to FIG. 10, the data transfer circuit (300) may include first repeaters (310) connected to a serial / parallelizer (255) of the data input / output circuit (250), second repeaters (350) connected to a page buffer driver (215) of the page buffer circuit (210), and a plurality of signal lines (380).

[0078] The signal lines (380) can connect the first repeaters (310) and the second repeaters (350) to each other.

[0079] The first repeaters (310) may include a first group of repeaters (311, 312, 313, 314) activated in a first operation mode and a second group of repeaters (321, 322, 323, 324) activated in a second operation mode. The second repeaters (350) may include a third group of repeaters (351, 352, 353, 354) activated in a first operation mode and a fourth group of repeaters (361, 362, 363, 364) activated in a second operation mode.

[0080] The repeaters of the first group (311, 312, 313, 314) and the repeaters of the third group (351, 352, 353, 354) are connected to the power supply voltage (VDD) and the ground voltage (VSS) and can operate in response to the first power gating signal (PGS1). The repeaters of the second group (321, 322, 323, 324) and the repeaters of the fourth group (361, 362, 363, 364) are connected to the power supply voltage (VDD) and the ground voltage (VSS) and can operate in response to the second power gating signal (PGS2).

[0081] The signal lines (380) may include signal lines (SL1, SL3, SL5, SL7) of a first group connecting repeaters (311, 312, 313, 314) of a first group and repeaters (351, 352, 353, 354) of a third group, and signal lines (SL2, SL4, SL6, SL8) of a second group connecting repeaters (321, 322, 323, 324) of a second group and repeaters (361, 362, 363, 364) of a fourth group. The signal lines of the first group (SL1, SL3, SL5, SL7) and the signal lines of the second group (SL2, SL4, SL6, SL8) may be arranged alternately.

[0082] Since the signal lines of the first group (SL1, SL3, SL5, SL7) and the signal lines of the second group (SL2, SL4, SL6, SL8) are formed using metal, capacitance (C1) is generated between the signal lines (SL1, SL2), capacitance (C2) is generated between the signal lines (SL2, SL3), capacitance (C3) is generated between the signal lines (SL3, SL4), capacitance (C4) is generated between the signal lines (SL4, SL5), capacitance (C5) is generated between the signal lines (SL5, SL6), capacitance (C6) is generated between the signal lines (SL6, SL7), and capacitance (C7) can be generated between the signal lines (SL7, SL8).

[0083] Each of the signal lines of the first group (SL1, SL3, SL5, SL7) is floated in the second operating mode, and each of the signal lines of the second group (SL2, SL4, SL6, SL8) is floated in the first operating mode, so that the capacitances that may occur between adjacent signal lines transmitting data are connected in series. Since the total capacitance is reduced when the capacitances are connected in series, the current consumption in the signal lines transmitting data can be reduced.

[0084] In FIG. 10, for convenience of explanation, eight signal lines (380) are shown (SL1, SL2, SL3, SL4, SL5, SL6, SL7, SL8), but the number of signal lines (380) is not limited thereto. In the embodiment, the number of signal lines (380) may include thousands.

[0085] FIG. 11a is a circuit diagram showing the configuration of one of the first group of repeaters in the data transmission circuit of FIG. 10 according to embodiments of the present invention.

[0086] FIG. 11a shows the configuration of repeater (311) among the repeaters (311, 312, 313, 314) of the first group, but each of the repeaters (312, 313, 314) and each of the repeaters (351, 352, 353, 354) of the third group may have the same configuration as repeater (311).

[0087] Referring to FIG. 11a, the repeater (311) may include a first inverter (410), a second inverter (420), a first discharge transistor (431), a second discharge transistor (433), and a precharge transistor (435).

[0088] The first inverter (410) may include a PMOS transistor (411) connected between the power supply voltage (VDD) and the first node (N11), and a second node (N12) corresponding to the output of the first inverter (410), and an NMOS transistor (413) connected between the second node (N12) and the first node (N11). The gates of the PMOS transistor (411) and the NMOS transistor (413) are commonly connected to an input node (NI1) so that an input data bit (IN_DB1) can be applied.

[0089] The first discharge transistor (431) may be implemented as an NMOS transistor having a drain connected to the first node (N11), a source connected to the ground voltage (VSS), and a gate receiving the first power gating signal (PGS1). The first discharge transistor (431) may discharge (pull-down) the first node (N11) to the ground voltage (VSS) level in response to the first power gating signal (PGS1) having a logic high level.

[0090] The precharge transistor (435) may be implemented as a PMOS transistor having a source connected to the power supply voltage (VDD), a drain connected to the second node (N12), and a gate receiving the first power gating signal (PGS1). The precharge transistor (435) may precharge (pull-up) the second node (N12) to the power supply voltage (VDD) level in response to the first power gating signal (PGS1) having a logic low level.

[0091] The second inverter (420) may include a PMOS transistor (421) connected between the power supply voltage (VDD) and the third node (N13), and connected between the power supply voltage (VDD) and the output node (NO1) connected to the signal line (SL1), and an NMOS transistor (423) connected between the output node (NO1) and the third node (N13). The gates of the PMOS transistor (421) and the NMOS transistor (423) may be commonly connected to the second node (N12), and the second inverter (420) may invert the voltage level of the second node (N12) to provide an input data bit (IN_DB1) at the output node (NO1).

[0092] The second discharge transistor (433) may be implemented as an NMOS transistor having a drain connected to the third node (N13), a source connected to the ground voltage (VSS), and a gate receiving the first power gating signal (PGS1). The second discharge transistor (433) may pull down the third node (N13) to the ground voltage (VSS) level in response to the first power gating signal (PGS1) having a logic high level.

[0093] The first power gating signal (PSG1) may have a logic high level in the first operating mode and a logic low level in the second operating mode. When the first power gating signal (PSG1) has a logic high level, the first discharge transistor (431) pulls down the first node (N11) to the ground voltage (VSS) level, and the second discharge transistor (433) pulls down the third node (N13) to the ground voltage (VSS) level. Accordingly, the first inverter (410) can invert the input data bit (IN_DB1), and the second inverter (420) can invert the voltage level of the second node (N12) to provide the input data bit (IN_DB1) at the output node (NO1).

[0094] FIG. 11b is a circuit diagram showing the configuration of one of the repeaters of the fourth group in the data transmission circuit of FIG. 10 according to embodiments of the present invention.

[0095] FIG. 11b shows the configuration of repeater (361) among the repeaters (361, 362, 363, 364) of the fourth group, but each of the repeaters (362, 363, 364) and each of the repeaters (321, 322, 323, 324) of the second group may have the same configuration as repeater (361).

[0096] Referring to FIG. 11b, the repeater (361) may include a first inverter (440), a second inverter (450), a first discharge transistor (461), a second discharge transistor (463), and a precharge transistor (465).

[0097] The first inverter (440) may include a PMOS transistor (441) connected between the power supply voltage (VDD) and the first node (N21), and a second node (N22) corresponding to the output of the first inverter (440), and an NMOS transistor (443) connected between the second node (N22) and the first node (N21). The gates of the PMOS transistor (441) and the NMOS transistor (443) are commonly connected to an input node (NI2) so that an output data bit (OUT_DB1) can be applied.

[0098] The first discharge transistor (461) may be implemented as an NMOS transistor having a drain connected to the first node (N11), a source connected to the ground voltage (VSS), and a gate receiving the second power gating signal (PGS2). The first discharge transistor (461) may pull down the first node (N21) to the ground voltage (VSS) level in response to the second power gating signal (PGS2) having a logic high level.

[0099] The precharge transistor (465) may be implemented as a PMOS transistor having a source connected to the power supply voltage (VDD), a drain connected to the second node (N22), and a gate receiving the second power gating signal (PGS2). The precharge transistor (465) may pull up the second node (N22) to the power supply voltage (VDD) level in response to the second power gating signal (PGS1) having a logic low level.

[0100] The second inverter (450) may include a PMOS transistor (451) connected between the power supply voltage (VDD) and the third node (N23), connected between the power supply voltage (VDD) and the output node (NO1), and an NMOS transistor (453) connected between the output node (NO2) and the third node (N23), connected to the signal line (SL2). The gates of the PMOS transistor (451) and the NMOS transistor (453) may be commonly connected to the second node (N22), and the second inverter (450) may invert the voltage level of the second node (N22) to provide an output data bit (OUT_DB1) at the output node (NO2).

[0101] The second discharge transistor (463) may be implemented as an NMOS transistor having a drain connected to the third node (N23), a source connected to the ground voltage (VSS), and a gate receiving the second power gating signal (PGS2). The second discharge transistor (463) may pull down the third node (N13) to the ground voltage (VSS) level in response to the second power gating signal (PGS2) having a logic high level.

[0102] The second power gating signal (PSG2) may have a logic high level in the second operation mode and a logic low level in the first operation mode. When the second power gating signal (PSG2) has a logic high level, the first discharge transistor (461) pulls down the first node (N21) to the ground voltage (VSS) level, and the second discharge transistor (463) pulls down the third node (N23) to the ground voltage (VSS) level. Accordingly, the first inverter (440) can invert the output data bit (OUT_DB1), and the second inverter (450) can invert the voltage level of the second node (N22) to provide the output data bit (OUT_DB1) at the output node (NO2).

[0103] FIG. 12 shows the operation of the repeater of FIG. 11a in a second operation mode according to embodiments of the present invention.

[0104] Referring to FIG. 12, in the second operating mode, the first power gating signal (PGS1) has a logic low level, so the first discharge transistor (431) and the second discharge transistor (433) are turned off, and the precharge transistor (435) pulls up the second node (N12) to the power supply voltage (VDD) level. The PMOS transistor (421) of the second inverter (420) is turned off in response to the logic high level of the second node (N12). Therefore, the signal line (SL1) connected to the output node (NO1) becomes floating. That is, in the second operating mode, the repeater (311) can make the signal line (SL1) connected to the output node (NO1) float in response to the first power gating signal (PGS1).

[0105] Likewise, the repeater (361) of FIG. 11b can float a signal line (SL2) connected to an output node in response to a second power gating signal (PGS2) in a first operating mode.

[0106] FIG. 13 shows the operation of the data transfer circuit of FIG. 10 in a first operation mode according to embodiments of the present invention.

[0107] Referring to FIG. 13, in the first operation mode, the first power gating signal (PGS1) has a logic high level and the second power gating signal (PGS2) has a logic low level. Accordingly, the first group of signal lines (SL1, SL3, SL5, SL7) connecting the first group of repeaters (311, 312, 313, 314) and the third group of repeaters (351, 352, 353, 354) can transmit (DT: data transmission) each of the data bits (EDB11, ODB11, EDB12, ODB12) from each of the first group of repeaters (311, 312, 313, 314) to each of the third group of repeaters (351, 352, 353, 354).

[0108] Additionally, the repeaters of the second group (321, 322, 323, 324) and the repeaters of the fourth group (361, 362, 363, 364) can float each of the signal lines of the second group (SL2, SL4, SL6, SL8) connected to the output node of each of the repeaters of the fourth group (361, 362, 363, 364) and the input node of each of the repeaters of the second group (321, 322, 323, 324) in response to the second power gating signal (PGS2) with a logic low level. Accordingly, the capacitance of each of the signal lines of the first group (SL1, SL3, SL5, SL7) carrying each of the data bits (EDB11, ODB11, EDB12, ODB12) can be reduced.

[0109] That is, the capacitance of the signal line (SL13) can have a value (first value) corresponding to the series connection of C1 and C2, the capacitance of the signal line (SL35) can have a value corresponding to the parallel connection of the first value and the value corresponding to the parallel connection of C3 and C4 (second value), the capacitance of the signal line (SL5) can have a value corresponding to the parallel connection of the second value and the value corresponding to the parallel connection of C5 and C6 (third value), and the capacitance of the signal line (SL7) can have a value corresponding to the parallel connection of the third value and C7.

[0110] Figure 14 shows data transferred to the page buffer circuit when the data transfer circuit operates as in Figure 13.

[0111] Referring to FIGS. 13 and 14, even data bits (EDB1) transmitted to the page buffer circuit (210) through signal lines (SL1, SL5) and odd data bits (ODB1) transmitted to the page buffer circuit (210) through signal lines (SL3, SL7) can be asynchronous with each other.

[0112] FIG. 15 shows a first power gating signal and a second power gating signal when the data transmission circuit asynchronously transmits even data bits and odd data bits as in FIG. 14.

[0113] Referring to FIG. 15, during the interval (T1) of the first operation mode, the second power gating signal (PGS2) may have a logic low level, and during the first sub-interval (T11) and the second sub-interval (T12), the first power gating signal (PGS1) may have a logic high level. Accordingly, each of the second group signal lines (SL2, SL4, SL6, SL8) connected to the output node of each of the fourth group repeaters (361, 362, 363, 364) and the input node of each of the second group repeaters (321, 322, 323, 324) can be floated. Additionally, the signal lines of the first group (SL1, SL3, SL5, SL7) can asynchronously provide each of the data bits (EDB11, ODB11, EDB12, ODB12) from each of the repeaters of the first group (311, 312, 313, 314) to each of the repeaters of the third group (351, 352, 353, 354).

[0114] FIG. 16 shows the operation of the data transfer circuit of FIG. 10 in a second operation mode according to embodiments of the present invention.

[0115] Referring to FIG. 16, in the second operation mode, the first power gating signal (PGS1) has a logic low level, and the second power gating signal (PGS2) has a logic high level. Accordingly, the second group signal lines (SL2, SL4, SL6, SL8) connecting the fourth group of repeaters (361, 362, 363, 364) and the second group of repeaters (321, 322, 323, 324) can transmit (DT: data transmission) each of the data bits (EDB21, ODB21, EDB22, ODB22) from each of the fourth group of repeaters (361, 362, 363, 364) to each of the second group of repeaters (321, 322, 323, 324).

[0116] Additionally, the repeaters of the first group (311, 312, 313, 314) and the repeaters of the third group (351, 352, 353, 354) can float each of the first group signal lines (SL1, SL3, SL5, SL7) connected to each of the output nodes of the first group repeaters (311, 312, 313, 314) and each of the input nodes of the third group repeaters (351, 352, 353, 354) in response to the first power gating signal (PGS1) with a logic low level. Accordingly, the capacitance of each of the second group signal lines (SL2, SL4, SL6, SL8) carrying each of the data bits (EDB21, ODB21, EDB22, ODB22) can be reduced.

[0117] Figure 17 shows data transferred to the page buffer circuit when the data transfer circuit operates as in Figure 16.

[0118] Referring to FIGS. 16 and 17, even data bits (EDB2) transmitted to the data input / output circuit (250) through signal lines (SL2, SL6) and odd data bits (ODB2) transmitted to the data input / output circuit (250) through signal lines (SL4, SL8) can be asynchronous with each other.

[0119] FIG. 18 shows a first power gating signal and a second power gating signal when the data transmission circuit asynchronously transmits even data bits and odd data bits as in FIG. 17.

[0120] Referring to FIG. 18, during the interval (T2) of the second operation mode, the first power gating signal (PGS1) may have a logic low level, and during the first sub-interval (T21) and the second sub-interval (T22), the second power gating signal (PGS2) may have a logic high level. Accordingly, each of the first group signal lines (SL1, SL3, SL5, SL7) connected to the output node of each of the first group repeaters (311, 312, 313, 314) and the input node of each of the third group repeaters (351, 352, 353, 354) can be floated. Additionally, the signal lines of the second group (SL2, SL4, SL6, SL8) can asynchronously provide each of the data bits (EDB21, ODB21, EDB22, ODB22) from each of the repeaters of the fourth group (361, 362, 363, 364) to each of the repeaters of the second group (321, 322, 323, 324).

[0121] FIG. 19 is a block diagram showing a non-volatile memory device according to embodiments of the present invention.

[0122] FIG. 19 shows the internal layout of a non-volatile memory device (500).

[0123] Referring to FIG. 19, a semiconductor memory device (500) may include a memory cell array (510) comprising a plurality of memory planes (511, 512, 513, 514). A peripheral region may be formed adjacent to one side of the memory cell array (510). The peripheral region may include a data path logic (530), a repeater region (540), a first region (550), a second region (560), etc. An interface region (520) may be formed adjacent to one side of the peripheral region.

[0124] A parallelizer (531) and a serializer (537) may be placed in the data path logic (530). The parallelizer (531) and the serializer (537) together may be referred to as SERDES, and are components for receiving data from input / output pads (525, 527) included within the interface area (520) or outputting data to the input / output pads (525, 527).

[0125] In an embodiment, the memory cell array (500) may be provided in the first semiconductor layer (L1) of FIG. 3, and the peripheral region may be provided in the second semiconductor layer (L2) of FIG. 3.

[0126] Referring to FIG. 19, data transfer from the repeater area (540) is illustrated by an arrow. First, when data is input through the data input / output pad in the interface area (220), the data is transferred to the data path logic (530). The data is processed by the servo and transferred to the repeater area (540). The repeater area (540) transfers the data to the repeater (553) in the first area (550) or the repeater (563) in the second area (560). The repeaters (553, 563) transfer the received data to the memory planes (510, 511, 512, 513). Data from the memory planes (510, 511, 512, 513) can be transferred to the data input / output pad of the interface area (520) in the reverse direction of the process described above.

[0127] FIG. 20 is a block diagram showing a non-volatile memory device according to embodiments of the present invention.

[0128] Referring to FIG. 20, a non-volatile memory device (600) includes a memory cell array (610) comprising a plurality of memory planes (611, 612, 613, 614), a peripheral area, and an interface area (620). The peripheral area is located between the memory cell array (600) and the interface area (620) and may include a data path logic area (630), a first area (650), a second area (660), etc.

[0129] The first region (650) may include a control circuit (651) and a repeater (653), and the second region (660) may include a voltage generator (661) and a repeater (663).

[0130] The interface area (620) may include serdes areas (621, 623). Serializers and parallelizers may be provided within the serdes areas (621, 623). In FIG. 20, arrows indicate the path of data movement. That is, data received through the input / output pads (625, 627) within the interface area is processed by the serializers and parallelizers within the serdes areas (621, 623) and transmitted to the repeaters (653, 663) through each of the signal lines (SLs1, SLs2). The repeaters (653, 663) may transmit the transmitted data to the memory planes (611, 612, 613, 614).

[0131] The repeaters, signal lines (SLs1, SLs2), and repeaters (653, 663) provided in the serdes regions (621, 623) may have the structure of FIG. 10. Accordingly, repeaters connected to signal lines that do not transmit data can reduce current consumption by floating the signal lines in response to a power gating signal.

[0132] FIG. 21 shows in detail the interface area of ​​FIG. 20 according to embodiments of the present invention.

[0133] Referring to FIG. 21, the interface area (620) may include sessions areas (621, 623). The input / output pads (625, 627) may include data input / output pads (670, 671, 672, 673, 674, 675, 676, 677). Additionally, the sessions areas (621, 623) may include a plurality of sessions (680, 681, 682, 683, 684, 685, 686, 687).

[0134] Each of the sedates (680, 681, 682, 683, 684, 685, 686, 687) is provided in an area adjacent to the data input / output pads (670, 671, 672, 673, 674, 675, 676, 677) and can be connected to the corresponding data input / output pad.

[0135] The serdes regions (621, 623) may each include a repeater (691, 692). Additionally, the interface region (20) may further include a repeater (693).

[0136] Data that is to be transferred to the memory plane (613, 614) among the data input / output pads (670, 671, 672, 673) can be processed by adjacent sub-pads (680, 681, 682, 683) and transferred to the repeater (692) through the repeater (693). The data is then transferred to the memory plane (613, 614) again through the repeater (663).

[0137] Data that is to be transferred to the memory plane (611, 612) among the data input / output pads (670, 671, 672, 673) can be processed by adjacent sub-pads (680, 681, 682, 683) and transferred to the repeater (691). The data can then be transferred back to the memory plane (611, 612) through the repeater (653).

[0138] FIG. 22 is a flowchart illustrating a method of operation of a non-volatile memory device according to embodiments of the present invention.

[0139] Referring to FIGS. 1 to 18 and FIG. 22, a non-volatile memory device (50) receives a write command and write data from a memory controller (20) (S110).

[0140] The control circuit (220) is positioned between the data input / output circuit (250) and the page buffer (210) and provides the write data to the memory cell array (100) through the page buffer using repeaters (311, 312, 313, 314) of the first group and repeaters (351, 352, 353, 354) of the third group, which are connected to each other through signal lines (SL1, SL3, SL5, SL7), while positioning the data input / output circuit (250) and the page buffer (210) and providing repeaters (321, 322, 323, 324) of the second group and repeaters (361, 362, 363, 364) of the fourth group, which are connected to each other through signal lines (SL2, SL4, SL6, SL8), to the outputs in a high impedance state. Set and plot the signal lines of the second group (SL2, SL4, SL6, SL8) (S120).

[0141] The non-volatile memory device (50) receives a read command from the memory controller (20) (S130).

[0142] The control circuit (220) provides data read from the memory cell array (100) to the data input / output circuit (250) using the repeaters (321, 322, 323, 324) of the second group and the repeaters (361, 362, 363, 364) of the fourth group, and sets the outputs of the repeaters (311, 312, 313, 314) of the first group and the repeaters (351, 352, 353, 354) of the third group to a high impedance state to float the signal lines (SL1, SL3, SL5, SL7) of the first group (S140).

[0143] Accordingly, the data transfer circuit of a non-volatile memory device according to embodiments of the present invention and the non-volatile memory device including the same can reduce current consumption by reducing the capacitance of the signal lines that transfer data, by using repeaters of a second group and repeaters of a fourth group to float signal lines of a second group that are alternately arranged with signal lines of a first group, while transferring data to a data input / output circuit through signal lines of a second group, and using repeaters of a first group and repeaters of a third group to float signal lines of a first group, while transferring read data to a data input / output circuit, in a second operation mode.

[0144] FIG. 23 is a cross-sectional view showing a non-volatile memory device according to embodiments of the present invention.

[0145] Referring to FIG. 23, the non-volatile memory device (2000) may have a C2C (chip-to-chip) structure. A C2C structure may mean fabricating an upper chip (first chip) containing a cell region (CELL) on a first wafer, fabricating a lower chip (second chip) containing a peripheral circuit region (PERI) on a second wafer different from the first wafer, and then connecting the upper chip and the lower chip to each other by a bonding method. For example, the bonding method may mean a method of electrically connecting a bonding metal formed on the uppermost metal layer of the upper chip and a bonding metal formed on the uppermost metal layer of the lower chip. For instance, if the bonding metal is formed of copper (Cu), the bonding method may be a Cu-to-Cu bonding method, and the bonding metal may also be formed of aluminum (Al) or tungsten (W).

[0146] Each of the peripheral circuit region (PERI) and cell region (CELL) of the non-volatile memory device (2000) may include an external pad bonding region (PA), a wordline bonding region (WLBA), and a bitline bonding region (BLBA).

[0147] The peripheral circuit region (PERI) may include a first substrate (2210), an interlayer insulating layer (2215), a plurality of circuit elements (2220a, 2220b, 2220c) formed on the first substrate (2210), a first metal layer (2230a, 2230b, 2230c) connected to each of the plurality of circuit elements (2220a, 2220b, 2220c), and a second metal layer (2240a, 2240b, 2240c) formed on the first metal layer (2230a, 2230b, 2230c). In one embodiment, the first metal layer (2230a, 2230b, 2230c) may be formed of tungsten, which has relatively high electrical resistivity, and the second metal layer (2240a, 2240b, 2240c) may be formed of copper, which has relatively low electrical resistivity.

[0148] In this specification, only the first metal layer (2230a, 2230b, 2230c) and the second metal layer (2240a, 2240b, 2240c) are illustrated and described, but are not limited thereto, and at least one additional metal layer may be formed on the second metal layer (2240a, 2240b, 2240c). At least some of the one or more metal layers formed on the upper part of the second metal layer (2240a, 2240b, 2240c) may be formed of aluminum or the like, having an electrical resistivity lower than that of copper forming the second metal layer (2240a, 2240b, 2240c).

[0149] The interlayer insulating layer (2215) is disposed on a first substrate (2210) to cover a plurality of circuit elements (2220a, 2220b, 2220c), a first metal layer (2230a, 2230b, 2230c), and a second metal layer (2240a, 2240b, 2240c), and may include an insulating material such as silicon oxide, silicon nitride, etc.

[0150] A lower bonding metal (2271b, 2272b) may be formed on the second metal layer (2240b) of the wordline bonding region (WLBA). In the wordline bonding region (WLBA), the lower bonding metal (2271b, 2272b) of the peripheral circuit region (PERI) may be electrically connected to the upper bonding metal (2371b, 2372b) of the cell region (CELL) by a bonding method, and the lower bonding metal (2271b, 2272b) and the upper bonding metal (2371b, 2372b) may be formed of aluminum, copper, or tungsten, etc.

[0151] A cell region (CELL) may provide at least one memory block. The cell region (CELL) may include a second substrate (2310) and a common source line (2320). On the second substrate (2310), a plurality of word lines (2331, 2332, 2333, 2334, 2335, 2336, 2337, 2338; 2330) may be stacked along a third direction (D3) perpendicular to the upper surface of the second substrate (2310). String selection lines and ground selection lines may be disposed on the upper and lower portions of the word lines (2330), respectively, and a plurality of word lines (2330) may be disposed between the string selection lines and the ground selection lines.

[0152] In the bitline bonding region (BLBA), the channel structure (CH) may extend in a direction (VD) perpendicular to the upper surface of the second substrate (2310) and penetrate wordlines (2330), string select lines, and ground select lines. The channel structure (CH) may include a data storage layer, a channel layer, and a buried insulating layer, and the channel layer may be electrically connected to a first metal layer (2350c) and a second metal layer (2360c). For example, the first metal layer (2350c) may be a bitline contact, and the second metal layer (2360c) may be a bitline. In one embodiment, the bitline (2360c) may extend along a second direction (D2) parallel to the upper surface of the second substrate (2310).

[0153] In the example of FIG. 23, the area where the channel structure (CH) and bit line (2360c), etc. are placed may be defined as a bit line bonding area (BLBA). The bit line (2360c) may be electrically connected to circuit elements (2220c) that provide a page buffer (2393) in the peripheral circuit area (PERI) in the bit line bonding area (BLBA). For example, the bit line (2360c) may be connected to an upper bonding metal (2371c, 2372c) in the peripheral circuit area (PERI), and the upper bonding metal (2371c, 2372c) may be connected to a lower bonding metal (2271c, 2272c) that is connected to the circuit elements (2220c) of the page buffer (2393).

[0154] In the wordline bonding area (WLBA), wordlines (2330) may be extended along a second horizontal direction (HD2) that is perpendicular to the first horizontal direction (HD1) and parallel to the upper surface of the second substrate (310), and may be connected to a plurality of cell contact plugs (2341, 2342, 2343, 2344, 2345, 2346, 2347; 2340). The wordlines (2330) and the cell contact plugs (2340) may be connected to each other at pads provided by extending at least some of the wordlines (2330) along the first horizontal direction (HD1) at different lengths. A first metal layer (2350b) and a second metal layer (2360b) may be connected in sequence to the upper portion of the cell contact plugs (2340) connected to the wordlines (2330). The cell contact plugs (2340) can be connected to the peripheral circuit area (PERI) through the upper bonding metal (2371b, 2372b) of the cell area (CELL) and the lower bonding metal (2271b, 2272b) of the peripheral circuit area (PERI) in the wordline bonding area (WLBA).

[0155] Cell contact plugs (2340) may be electrically connected to circuit elements (2220b) forming an address decoder or a row decoder (2394) in a peripheral circuit region (PERI). In one embodiment, the operating voltage of the circuit elements (2220b) forming the row decoder (2394) may be different from the operating voltage of the circuit elements (2220c) forming the page buffer (2393). For example, the operating voltage of the circuit elements (2220c) forming the page buffer (2393) may be greater than the operating voltage of the circuit elements (2220b) forming the row decoder (2394).

[0156] A common source line contact plug (2380) may be disposed in the external pad bonding area (PA). The common source line contact plug (2380) is formed of a conductive material such as a metal, a metal compound, or polysilicon and may be electrically connected to a common source line (2320). A first metal layer (2350a) and a second metal layer (2360a) may be sequentially laminated on top of the common source line contact plug (2380). For example, the area where the common source line contact plug (2380), the first metal layer (2350a), and the second metal layer (2360a) are disposed may be defined as the external pad bonding area (PA).

[0157] Meanwhile, input / output pads (2205, 2305) may be disposed in the external pad bonding area (PA). A lower insulating film (2201) covering the lower surface of the first substrate (2210) may be formed on the lower surface of the first substrate (2210), and a first input / output pad (2205) may be formed on the lower insulating film (2201). The first input / output pad (2205) is connected to at least one of a plurality of circuit elements (2220a, 2220b, 2220c) disposed in the peripheral circuit area (PERI) through the first input / output contact plug (2203), and may be separated from the first substrate (2210) by the lower insulating film (2201). Additionally, a side insulating film is disposed between the first input / output contact plug (2203) and the first substrate (2210) to electrically separate the first input / output contact plug (2203) and the first substrate (2210).

[0158] An upper insulating film (2301) covering the upper surface of the second substrate (2310) may be formed on the upper surface of the second substrate (2310), and a second input / output pad (2305) may be disposed on the upper insulating film (2301). The second input / output pad (2305) may be connected to at least one of a plurality of circuit elements (2220a, 2220b, 2220c) disposed in the peripheral circuit region (PERI) through a second input / output contact plug (2303). In one embodiment, the second input / output pad (2305) may be electrically connected to the circuit element (2220a).

[0159] According to the embodiment, the second substrate (2310) and common source line (2320), etc., may not be placed in the area where the second input / output contact plug (2303) is placed. Additionally, the second input / output pad (2305) may not overlap with the word lines (2380) in the third direction (D3). The second input / output contact plug (2303) is separated from the second substrate (2310) in a direction parallel to the upper surface of the second substrate (2310) and may be connected to the second input / output pad (2305) by penetrating the interlayer insulating layer (2315) of the cell area (CELL).

[0160] According to the embodiment, the first input / output pad (2205) and the second input / output pad (2305) may be formed optionally. For example, the non-volatile memory device (2000) may include only the first input / output pad (2205) disposed on the upper part of the first substrate (2201), or only the second input / output pad (2305) disposed on the upper part of the second substrate (2301). Alternatively, the memory device (2000) may include both the first input / output pad (2205) and the second input / output pad (2305).

[0161] In each of the external pad bonding region (PA) and bitline bonding region (BLBA) included in the cell region (CELL) and peripheral circuit region (PERI), the metal pattern of the top metal layer may exist as a dummy pattern, or the top metal layer may be empty.

[0162] A non-volatile memory device (2000) may form a lower metal pattern (2273a) of the same shape as the upper metal pattern (2372a) of the cell region (CELL) on the upper metal layer of the peripheral circuit region (PERI) in the external pad bonding region (PA), corresponding to the upper metal pattern (2372a) formed on the upper metal layer of the cell region (CELL). The lower metal pattern (2273a) formed on the upper metal layer of the peripheral circuit region (PERI) may not be connected to a separate contact in the peripheral circuit region (PERI). Similarly, an upper metal pattern (2372a) of the same shape as the lower metal pattern (2273a) of the peripheral circuit region (PERI) may be formed on the upper metal layer of the cell region (CELL) in the external pad bonding region (PA), corresponding to the lower metal pattern (2273a) formed on the upper metal layer of the peripheral circuit region (PERI).

[0163] A lower bonding metal (2271b, 2272b) may be formed on the second metal layer (2240b) of the wordline bonding region (WLBA). In the wordline bonding region (WLBA), the lower bonding metal (2271b, 2272b) of the peripheral circuit region (PERI) may be electrically connected to the upper bonding metal (2371b, 2372b) of the cell region (CELL) by a bonding method.

[0164] Additionally, in the bitline bonding area (BLBA), an upper metal pattern (2392) of the same shape as the lower metal pattern (2252) of the peripheral circuit area (PERI) can be formed on the upper metal layer of the cell area (CELL) in correspondence with the lower metal pattern (2252) formed on the upper metal layer of the peripheral circuit area (PERI). A contact may not be formed on the upper metal pattern (2392) formed on the upper metal layer of the cell area (CELL).

[0165] The aforementioned wordline voltages can be provided to at least one memory block of the cell region (CELL) through the lower bonding metal (2271b, 2272b) of the peripheral circuit region (PERI) and the upper bonding metal (2371b, 2372b) of the cell region (CELL).

[0166] A page buffer circuit including the page buffer (PB) of FIG. 8 can be provided in the peripheral circuit region (PERI) by using at least some of the plurality of circuit elements (2220a, 2220b, 2220c).

[0167] FIG. 24 is a block diagram showing an electronic system including a semiconductor device according to embodiments of the present invention.

[0168] Referring to FIG. 24, the electronic system (3000) may include a semiconductor device (3100) and a controller (3200) electrically connected to the semiconductor device (3100). The electronic system (3000) may be a storage device or an electronic device including a storage device, comprising one or more semiconductor devices (3100). For example, the electronic system (3000) may be a Solid State Drive (SSD) device, a Universal Serial Bus (USB), a computing system, a medical device, or a communication device, comprising one or more semiconductor devices (3100).

[0169] The semiconductor device (3100) may be a non-volatile memory device, for example, a non-volatile memory device described above with reference to FIGS. 1 to 21. The semiconductor device (3100) may include a first structure (3100F) and a second structure (3100S) on the first structure (3100F). The first structure (3100F) may be a peripheral circuit structure including a decoder circuit (3110), a page buffer circuit (3120), and a logic circuit (3130). The second structure (3100S) may be a memory cell structure including a bit line (BL), a common source line (CSL), word lines (WL), first and second gate upper lines (UL1, UL2), first and second gate lower lines (LL1, LL2), and memory cell strings (CSTR) between the bit line (BL) and the common source line (CSL).

[0170] In the second structure (3100S), each memory cell string (CSTR) may include lower transistors (LT1, LT2) adjacent to a common source line (CSL), upper transistors (UT1, UT2) adjacent to a bit line (BL), and a plurality of memory cell transistors (MCT) disposed between the lower transistors (LT1, LT2) and the upper transistors (UT1, UT2). The number of lower transistors (LT1, LT2) and the number of upper transistors (UT1, UT2) may vary depending on the embodiments.

[0171] In exemplary embodiments, the upper transistors (UT1, UT2) may include string select transistors, and the lower transistors (LT1, LT2) may include ground select transistors. The lower gate lines (LL1, LL2) may each be the gate electrodes of the lower transistors (LT1, LT2). The word lines (WL) may be the gate electrodes of the memory cell transistors (MCT), and the upper gate lines (UL1, UL2) may each be the gate electrodes of the upper transistors (UT1, UT2).

[0172] In exemplary embodiments, the lower transistors (LT1, LT2) may include a lower erase control transistor (LT1) and a ground select transistor (LT2) connected in series. The upper transistors (UT1, UT2) may include a string select transistor (UT1) and an upper erase control transistor (UT2) connected in series. At least one of the lower erase control transistor (LT1) and the upper erase control transistor (UT1) may be used for an erase operation to delete data stored in memory cell transistors (MCTs) using the Gate Induced Drain Leakage (GIDL) phenomenon.

[0173] The common source line (CSL), the first and second lower gate lines (LL1, LL2), the word lines (WL), and the first and second upper gate lines (UL1, UL2) can be electrically connected to the decoder circuit (3110) through first connecting wires (3115) extending from the first structure (3100F) to the second structure (1100S). The bit lines (BL) can be electrically connected to the page buffer circuit (3120) through second connecting wires (3125) extending from the first structure (3100F) to the second structure (3100S).

[0174] In the first structure (3100F), the decoder circuit (1110) and the page buffer circuit (3120) can perform control operations on at least one selected memory cell transistor among a plurality of memory cell transistors (MCTs). The decoder circuit (3110) and the page buffer circuit (3120) can be controlled by the logic circuit (3130). The semiconductor device (3000) can communicate with the controller (3200) through an input / output pad (3101) that is electrically connected to the logic circuit (3130). The input / output pad (3101) can be electrically connected to the logic circuit (3130) through an input / output connection wire (3135) that extends from the first structure (3100F) to the second structure (3100S).

[0175] The controller (3200) may include a processor (3210), a NAND controller (3220), and a host interface (1230). According to embodiments, the electronic system (3000) may include a plurality of semiconductor devices (3100), and in this case, the controller (3200) may control the plurality of semiconductor devices (3000).

[0176] The processor (3210) can control the operation of the entire electronic system (3000) including the controller (3200). The processor (3210) can operate according to a predetermined firmware and can access the semiconductor device (3100) by controlling the NAND controller (3220).

[0177] The NAND controller (3220) may include a NAND interface (3221) that handles communication with the semiconductor device (3100). Through the NAND interface (3221), control commands for controlling the semiconductor device (3100), data to be written to the memory cell transistors (MCT) of the semiconductor device (1100), data to be read from the memory cell transistors (MCT) of the semiconductor device (3100), etc., may be transmitted. The host interface (3230) may provide a communication function between the electronic system (1000) and an external host. When a control command is received from an external host through the host interface (3230), the processor (1210) may control the semiconductor device (1100) in response to the control command.

[0178] A non-volatile memory device or storage device according to an embodiment of the present invention can be implemented using various types of packages.

[0179] As described above, although the present invention has been explained with reference to preferred embodiments, those skilled in the art will understand that various modifications and changes can be made to the present invention without departing from the spirit and scope of the invention as set forth in the following claims.

Claims

Claim 1 A data transfer circuit of a non-volatile memory device comprising: a plurality of first repeaters connected to a first circuit element disposed in a data input / output path of the non-volatile memory device; and a plurality of second repeaters connected to a second circuit element disposed spaced apart from the first circuit element in the data input / output path of the non-volatile memory device. A data transmission circuit comprising a plurality of signal lines that connect the plurality of first repeaters and the plurality of second repeaters, and have a first group of signal lines and a second group of signal lines that are alternately arranged, wherein the plurality of first repeaters include a first group of repeaters activated in a first operating mode and a second group of repeaters activated in a second operating mode in which the operating interval does not overlap with the first operating mode, and the plurality of second repeaters include a third group of repeaters that is activated in the first operating mode and connected to the first group of repeaters through the first group of signal lines and a fourth group of repeaters that is activated in the second operating mode and connected to the second group of repeaters through the second group of signal lines, wherein the second group of signal lines are floating in the first operating mode and the first group of signal lines are floating in the second operating mode. Claim 2 A data transmission circuit according to claim 1, wherein in the second operation mode, the repeaters of the first group float an output node connected to the signal lines of the first group in response to the first power gating signal, and the repeaters of the third group float an input node connected to the signal lines of the first group in response to the first power gating signal, and in the first operation mode, the repeaters of the second group float an output node connected to the signal lines of the second group in response to the second power gating signal, and the repeaters of the fourth group float an input node connected to the signal lines of the fourth group in response to the second power gating signal. Claim 3 A data transfer circuit according to claim 1, wherein each of the repeaters of the first group and each of the repeaters of the third group comprises: a first inverter connected between a power supply voltage and a first node; a first discharge transistor connected between the first node and a ground voltage and having a gate that receives a first power gating signal; a precharge transistor connected between the power supply voltage and a second node corresponding to the output of the first inverter and having a gate that receives the first power gating signal; a second inverter connected between the second node and an output node and connected between the power supply voltage and a third node; and a second discharge transistor connected between the third node and the ground voltage and having a gate that receives the first power gating signal, wherein in the first operating mode, the first power gating signal has a logic high level, and in response to the first power gating signal, the first discharge transistor connects the first node to the ground voltage and the second discharge transistor connects the third node to the ground voltage. Claim 4 A data transmission circuit according to claim 3, wherein the first inverter comprises a first PMOS transistor connected between the power supply voltage and the second node; and a first NMOS transistor connected between the second node and the first node, and the second inverter comprises a second PMOS transistor connected between the power supply voltage and the output node; and a second NMOS transistor connected between the output node and the third node, wherein in the second operating mode, the first power gating signal has a logic low level, and in response to the first power gating signal having the logic low level in the second operating mode, the precharge transistor precharges the second node to the power supply voltage level, the first discharge transistor and the second discharge transistor are turned off, and the second PMOS transistor is turned off in response to the voltage level of the second node to float the output node connected to the corresponding signal line among the first group of signal lines. Claim 5 A data transfer circuit according to claim 1, wherein each of the repeaters of the second group and each of the repeaters of the fourth group comprises: a first inverter connected between a power supply voltage and a first node; a first discharge transistor connected between the first node and a ground voltage and having a gate that receives a second power gating signal; a precharge transistor connected between the power supply voltage and a second node corresponding to the output of the first inverter and having a gate that receives the second power gating signal; a second inverter connected between the second node and an output node and connected between the power supply voltage and a third node; and a second discharge transistor connected between the third node and the ground voltage and having a gate that receives the second power gating signal, wherein in the second operating mode, the second power gating signal has a logic high level, and in response to the second power gating signal, the first discharge transistor connects the first node to the ground voltage and the second discharge transistor connects the third node to the ground voltage. Claim 6 A data transmission circuit according to claim 5, wherein the first inverter comprises a first PMOS transistor connected between the power supply voltage and the second node; and a first NMOS transistor connected between the second node and the first node, and the second inverter comprises a second PMOS transistor connected between the power supply voltage and the output node; and a second NMOS transistor connected between the output node and the third node, wherein in the first operating mode, the second power gating signal has a logic low level, and in response to the second power gating signal having a logic low level in the first operating mode, the precharge transistor precharges the second node to the power supply voltage level, the first discharge transistor and the second discharge transistor are turned off, and the second PMOS transistor is turned off in response to the voltage level of the second node to float the output node connected to the corresponding signal line among the signal lines of the second group. Claim 7 A non-volatile memory device comprising: a memory cell array including a plurality of memory cells; a page buffer circuit connected to the memory cell array through a plurality of bit lines; a data input / output circuit that exchanges data with an external memory controller; a data transfer circuit connected between the data input / output circuit and the page buffer circuit, which provides the data provided from the data input / output circuit to the page buffer circuit in a first operation mode and provides the data provided from the page buffer circuit to the data input / output circuit in a second operation mode; and a control circuit that controls the page buffer circuit and the data transfer circuit, wherein the data transfer circuit floats some of the signal lines that do not transmit data among a plurality of signal lines included internally in each of the first operation mode and the second operation mode in response to a first power gating control signal and a second power gating signal from the control circuit, and the data transfer circuit includes a plurality of first repeaters connected to the data input / output circuit, wherein the plurality of first repeaters include a first group of repeaters activated in the first operation mode and a second group of repeaters activated in the second operation mode. Claim 8 A non-volatile memory device according to claim 7, wherein the data transfer circuit comprises a plurality of second repeaters connected to the page buffer circuit; and the plurality of signal lines that connect the plurality of first repeaters and the plurality of second repeaters and have a first group of signal lines and a second group of signal lines arranged alternately, wherein the plurality of second repeaters are activated in the first operation mode and include a third group of repeaters connected through the first group of repeaters and the first group of signal lines, and a fourth group of repeaters activated in the second operation mode and connected through the second group of repeaters and the second group of signal lines, wherein the second group of signal lines are floating in the first operation mode and the first group of signal lines are floating in the second operation mode. Claim 9 A non-volatile memory device according to claim 8, wherein in the second operation mode, the repeaters of the first group float an output node connected to the signal lines of the first group in response to the first power gating signal, and the repeaters of the third group float an input node connected to the signal lines of the first group in response to the first power gating signal, and in the first operation mode, the repeaters of the second group float an output node connected to the signal lines of the second group in response to the second power gating signal, and the repeaters of the fourth group float an input node connected to the signal lines of the fourth group in response to the second power gating signal. Claim 10 In claim 7, the page buffer circuit comprises: a plurality of page buffer units arranged along a first horizontal direction; and a plurality of cache latches arranged spaced apart from the page buffer units along the first horizontal direction, each corresponding to the plurality of page buffer units and commonly connected to a combined sensing node, wherein each of the plurality of page buffer units comprises a pass transistor connected to each sensing node and driven according to a pass control signal, the memory cell array is arranged in a first semiconductor layer, the page buffer circuit, the data input / output circuit, the data transfer circuit and the control circuit are arranged in a second semiconductor layer, and the first semiconductor layer and the second semiconductor layer are arranged in a vertical direction, a non-volatile memory device.

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