An Energy-Efficient Continuous-Time Discrete-Time Hybrid Delta-Sigma Capacitance-to-Digital Converter

Abstract

A power-efficient continuous-discrete-time hybrid delta-sigma capacitance-to-digital converter for capacitance measurement and a method of operation thereof are presented. The power-efficient continuous-discrete-time hybrid delta-sigma capacitance-to-digital converter for capacitance measurement proposed in the present invention includes a continuous-time capacitance-to-voltage converter that reduces the total noise bandwidth using anti-aliasing characteristics and converts the input capacitor value into voltage, a discrete-time switched capacitor integrator that receives the voltage and performs integration operations using a Floating Inverter Amplifier (FIA) to increase power efficiency, a second-order noise-shaping SAR ADC that quantizes the output of the discrete-time switched capacitor integrator, and a DSM C-DAC that has third-order noise-shaping characteristics, increases resolution, and forms a DSM loop.

Description

Technology Field

[0001] The present invention relates to a power-efficient continuous-discrete-time hybrid delta-sigma capacitance-to-digital converter for capacitance measurement. Background Technology

[0002] With the rise of the Internet of Things (IoT) and the proliferation of wearable smart devices, the demand for various sensor interface systems has surged significantly. Many environmental and biomedical sensor interface systems rely on sensors that convert physical quantities into outputs such as capacitance, resistance, voltage, or current. In particular, capacitive sensing transducers are widely used in IoT applications due to their advantageous properties of low noise and reduced temperature sensitivity.

[0003] Various capacitive sensor interface applications have demonstrated effectiveness in capturing environmental and biomedical information. This technology finds a wide range of applications for detecting various factors such as pressure, humidity, acceleration, gas molecules, and proximity. However, challenges arise particularly from minute variations in capacitance values ​​induced by physical quantities relative to nominal capacitance. Consequently, subsequent capacitive sensor interface integrated circuits (ICs) require exceptionally fine capacitance resolution. Furthermore, given the widespread use of batteries in IoT applications, interface ICs must exhibit high power efficiency.

[0004] The air particle sensor interface IC can detect fine particles by detecting attached air particles on a monolithic CMOS IDE (Inter Digitated Electrode) capacitive sensor. In addition, high-resolution capacitive sensors find utility in biomolecular detection, where the dielectric properties of Al / Al2O3IDE function as a MIE (Metal-Insulator Electrolyte) interface to enable the detection of bacteria.

[0005] Figure 1 is a diagram showing the type of CDC according to the prior art.

[0006] Capacitance-to-Digital Converter (CDC) ICs convert the capacitance difference value of a capacitance sensor into a digital code. There are various types of CDC topologies. Topologies can be broadly classified into three types: Successive Approximation Register (SAR) based CDCs, Period Modulation (PM) based CDCs, and DSM based CDCs.

[0007] Figure 1(a) shows the general structure of a SAR-based CDC. The SAR-based CDC has a sensor capacitance value (C S ) capacitive digital-to-analog converter (C DAC Compare with ) and use the SAR method C DAC Value and C S It balances the. Conventional SAR CDCs are Cs without analog blocks. DAC It consists of a comparator and a digital SAR logic block. Therefore, the topology demonstrates excellent power efficiency with relatively fast measurement times. On the other hand, without a front-end amplification stage, the noise and offset of the comparator and C DACThe achievable capacitance resolution is limited due to the mismatch. Recently, noise shaping techniques based on Finite-Impulse Response (FIR) / Infinite-Impulse Response (IIR) filters have been proposed to improve the resolution of SAR-based CDCs. Additionally, pipelined SAR and kT / C rejection techniques have been utilized to further increase power efficiency. Despite these advancements, SAR-based CDCs are still limited to 10aF rms It is difficult to achieve a capacitance resolution level below a certain level.

[0008] Figure 1(b) shows a simplified structure of a PM-based CDC. The PM-based CDC converts capacitance information into time-domain information. The sensor oscillator uses C, which is the capacitance value of the sensor. S The frequency is changed accordingly. The oscillator output signal is divided by the reference clock and counted using a multibit counter block. Since the input capacitance is read in the time domain without being limited by the supply voltage, a wide capacitance detection range of up to tens of nanofarads can be achieved. However, the time-based CDC topology requires significant time for capacitance measurement, which limits its application to narrow bandwidth sensor applications. Furthermore, to achieve high capacitance resolution, low-jitter oscillators must be utilized, which has the disadvantage of degrading overall power efficiency. A two-stage conversion method has been proposed to improve power efficiency. However, despite these efforts, time-based CDC cannot provide sufficient power efficiency and capacitance resolution, even though it offers a wide capacitance input range.

[0009] Finally, Fig. 1(c) shows a representative structure of a DSM-based CDC. The DSM CDC switches the applied voltage, converts capacitance to voltage using a Capacitance-to-Voltage Converter (CVC), and performs quantization through a high Signal-to-Noise Ratio (SNR) DSM using noise shaping techniques. This approach can achieve significantly high resolution thanks to the front-end amplification stage and sharp noise shaping characteristics. However, topologies using CVCs have limitations, particularly in the reduced input capacitance range. Additionally, including a loop filter in the DSM CDC structure results in insufficient power efficiency. Higher-order DSM CDCs have been presented with improved capacitance resolution. Various techniques, including zoom DSM topologies and time-based DSMs, have been proposed. Recently, adaptive range shift techniques using Floating Inverter Amplifiers (FIAs) have been introduced to improve the power efficiency of the topology. Despite the various evolutions of the DSM and CDC, 10aF rms For high-resolution CDCs with capacitance resolutions below this level, power efficiency is insufficient for capacitance sensor interface applications, and improvements in resolution related to power efficiency are required. Prior art literature

[0010] [1] S. Park et al., A 3.68 aFrms resolution 183 dB FoMs 4th-order continuous-time bandpass ΔΣ capacitance-to-digital converter in 0.18 μm CMOS, VLSI, June 2021, pp. 1-2. The problem to be solved

[0011] The technical problem that the present invention aims to solve is to provide a power-efficient continuous-discrete-time hybrid delta-sigma capacitance-to-digital converter for capacitance measurement that serves as an interface with environmental sensors, and a method of operation thereof, as the demand for various environmental, motion, and proximity sensors is rapidly increasing due to the emergence of the Internet of Things (IoT) and wearable devices. Through the proposed low-power design technique, we intend to propose an integrated circuit with excellent power consumption-to-resolution ratio characteristics compared to previously proposed capacitance-to-digital converters. means of solving the problem

[0012] In one aspect, the power-efficient continuous-discrete-time hybrid delta-sigma capacitance-to-digital converter for capacitance measurement proposed in the present invention includes a continuous-time capacitance-to-voltage converter that reduces the overall noise bandwidth using anti-aliasing characteristics and converts the input capacitor value into a voltage, a discrete-time switched capacitor integrator that receives the voltage and performs integration operations using a Floating Inverter Amplifier (FIA) to increase power efficiency, a second-order noise-shaping SAR ADC that quantizes the output of the discrete-time switched capacitor integrator, and a DSM C-DAC that has third-order noise-shaping characteristics, increases resolution, and forms a DSM loop.

[0013] The above continuous-time capacitance-voltage converter converts the delta-capacitance, which is the capacitance difference between the sensor capacitor and the reference capacitor of a capacitance excitation driver excited in opposite phases, into voltage.

[0014] The above continuous-time capacitance-voltage converter amplifies the delta-capacitance, which is the capacitance difference between the sensor capacitor and the reference capacitor, through a folded cascode amplifier at the ratio of the feedback capacitance to the reference voltage.

[0015] The discrete-time switched capacitor integrator converts the output of the continuous-time capacitance-voltage converter into a DC voltage using a chopper, and then samples it through a sampling capacitor.

[0016] The discrete-time switched capacitor integrator above performs integration after sampling through the sampling capacitor, and uses a chopper in the FIA ​​to avoid low-frequency 1 / f noise in the FIA.

[0017] The above FIA ​​includes a first storage capacitor and a second storage capacitor, stores charge in the first storage capacitor and the second storage capacitor in a sampling mode, and reduces power consumption through dynamic operation using the stored energy when the FIA ​​operates.

[0018] The above second-order noise-shaping SAR ADC stores the residual voltage of the above second-order noise-shaping SAR ADC in the integrator capacitor of the above discrete-time switched capacitor integrator for error feedback.

[0019] The above second-order noise-shaping SAR ADC stores the residual voltage in a capacitor having a capacitance greater than that of the DSM C-DAC and uses charge redistribution for error feedback.

[0020] The above DSM C-DAC performs DSM operation by controlling the DSM C-DAC (Delta-Sigma Modulator Capacitance Digital-to-Analog Converter) through a digital block including a truncator and a DWA (Data-Weighted Averaging) after SAR conversion is completed through the above 2nd Noise Shaping SAR ADC.

[0021] The above DSM C-DAC reduces the size of the DSM C-DAC and increases linearity through the truncator, and performs a second digital DSM to eliminate errors caused by the truncator, thereby having third-order noise shaping characteristics in the entire loop.

[0022] In another aspect, the method of operation of a power-efficient continuous-discrete-time hybrid delta-sigma capacitance-to-digital converter for capacitance measurement proposed in the present invention comprises the steps of: reducing the total noise bandwidth and converting the input capacitor value into a voltage by utilizing anti-aliasing characteristics through a continuous-time capacitance-to-voltage converter; receiving the voltage and increasing power efficiency and performing an integration operation through a discrete-time switched capacitor integrator using a Floating Inverter Amplifier (FIA); quantizing the output of the discrete-time switched capacitor integrator through a second-order noise-shaping SAR ADC; and increasing the resolution by having third-order noise-shaping characteristics through a DSM C-DAC constituting a DSM loop.

[0023] In another aspect, the power-efficient continuous-discrete-time hybrid delta-sigma capacitance-to-digital converter for capacitance measurement proposed in the present invention includes a discrete-time switched capacitor integrator that receives a voltage converted through a continuous-time capacitance-to-voltage converter and performs an integral operation using a Floating Inverter Amplifier (FIA) to increase power efficiency. The discrete-time switched capacitor integrator converts the output of the continuous-time capacitance-to-voltage converter into a DC voltage using a chopper, samples it through a sampling capacitor, performs an integral operation after sampling through the sampling capacitor, and uses a chopper in the FIA ​​to avoid low-frequency 1 / f noise in the FIA. The FIA ​​includes a first storage capacitor and a second storage capacitor, stores charge in the first storage capacitor and the second storage capacitor in a sampling mode, and reduces power consumption through dynamic operation using the stored energy when the FIA ​​is operating. Effects of the invention

[0024] According to embodiments of the present invention, the advantages of continuous-time and discrete-time based topologies can be efficiently combined to provide low noise and high charge resolution characteristics at an interface with an environmental sensor. While the continuous-time capacitance-voltage converter maintains low-noise performance, the Floating Inverter Amplifier (FIA) integrator improves power efficiency, and the second-order NS SAR ADC improves quantization performance and exhibits a third-order quantization-noise shaping effect. Brief explanation of the drawing

[0025] Figure 1 is a diagram showing the type of CDC according to the prior art. FIG. 2 is a diagram illustrating noise analysis for the CVC of a DSM CDC according to one embodiment of the present invention. FIG. 3 is a diagram showing the configuration of a power-efficient continuous-discrete-time hybrid delta-sigma capacitance-to-digital converter for capacitance measurement according to one embodiment of the present invention. FIG. 4 is a block diagram of a power-efficient continuous-discrete-time hybrid delta-sigma capacitance-to-digital converter for capacitance measurement according to one embodiment of the present invention. FIG. 5 is a circuit diagram of a power-efficient continuous-discrete-time hybrid delta-sigma capacitance-to-digital converter for capacitance measurement according to one embodiment of the present invention. FIG. 6 is a drawing for explaining a CT-CVC according to an embodiment of the present invention. FIG. 7 is a diagram illustrating a discrete-time switched capacitor integrator according to an embodiment of the present invention. FIG. 8 is a drawing for explaining an FIA according to an embodiment of the present invention. FIG. 9 is a diagram illustrating a second-order noise shaping SAR ADC according to one embodiment of the present invention. FIG. 10 is a drawing for explaining a truncator according to one embodiment of the present invention. FIG. 11 is a drawing for explaining a DSM C-DAC according to one embodiment of the present invention. FIG. 12 is a flowchart illustrating the operation method of a power-efficient continuous-discrete-time hybrid delta-sigma capacitance-to-digital converter for capacitance measurement according to one embodiment of the present invention. FIG. 13 is a graph showing the power spectral density of a digital output according to one embodiment of the present invention. FIG. 14 is a drawing showing the results of measuring capacitance resolution according to one embodiment of the present invention. Specific details for implementing the invention

[0026] Hereinafter, embodiments of the present invention will be described in detail with reference to the attached drawings.

[0028] FIG. 2 is a diagram illustrating noise analysis for the CVC of a DSM CDC according to one embodiment of the present invention.

[0029] According to an embodiment of the present invention, a Delta-Sigma Modulator Capacitance-to-Digital Converter (DSM CDC) is applied. The DSM CDC according to an embodiment of the present invention aims to further improve the resolution of the capacitor and enhance energy efficiency, which was lacking in DSM-based methods.

[0030] To analyze the noise of the Capacitance-to-Voltage Converter (CVC) of the DSM CDC according to an embodiment of the present invention, the Discrete-Time Capacitance-to-Voltage Converter (DT CVC) and the Continuous-Time Capacitance-to-Voltage Converter (CT CVC) are described.

[0031] Figure 2(a) shows a DT CVC, and Figure 2(b) shows a CT CVC.

[0032] Referring to Fig. 2(a), the DT-CVC uses a switched capacitor amplifier to perform sampling and amplification operations, which causes noise folding during the sampling process. The kT / C noise is multiplied by the square of CIN, resulting in capacitance equivalent noise that is proportional to kT and CIN.

[0033] On the other hand, referring to Fig. 2(b), since the CT-CVC does not perform sampling during the amplification process, noise folding does not occur. Only the Input Referred Noise (IRN) of the amplifier and noise generated by the Capacitance Excitation Driver occur within the signal bandwidth. In addition, the CT-CVC exhibits anti-aliasing characteristics, which can significantly reduce the noise bandwidth.

[0034] When comparing the two structures, DT-CVC utilizes dynamic amplifiers such as floating inverter amplifiers, which is advantageous for power consumption, whereas CT-CVC exhibits superior noise performance. In terms of the gain-bandwidth product, CT-CVC, which primarily uses static amplifiers, tends to have a slightly larger GBW (Gain-BandWidth) value.

[0036] FIG. 3 is a diagram showing the configuration of a power-efficient continuous-discrete-time hybrid delta-sigma capacitance-to-digital converter for capacitance measurement according to one embodiment of the present invention.

[0037] A power-efficient continuous-discrete-time hybrid delta-sigma capacitance-to-digital converter for capacitance measurement according to an embodiment of the present invention includes a continuous-time capacitance-to-voltage converter (CT CVC) (310), a discrete-time switched-capacitor integrator (320), a second-order noise-shaping SAR ADC (Successive Approximation Register Analog-to-Digital Converter) (330), and a DSM C-DAC (Delta-Sigma Modulator Capacitance Digital-to-Analog Converter) (340).

[0038] The CT CVC (310) according to an embodiment of the present invention reduces the overall noise bandwidth using anti-aliasing characteristics and converts the input capacitor value into voltage.

[0039] A CT CVC (310) according to an embodiment of the present invention converts the delta-capacitance, which is the capacitance difference between the sensor capacitor and the reference capacitor of a capacitance excitation driver excited in opposite phases, into a voltage.

[0040] The CT CVC (310) according to an embodiment of the present invention amplifies the delta-capacitance, which is the capacitance difference between the sensor capacitor and the reference capacitor, through a folded cascode amplifier at the ratio of the feedback capacitance to the reference voltage.

[0041] A discrete-time switched capacitor integrator (320) according to an embodiment of the present invention receives the voltage as input and uses a Floating Inverter Amplifier (FIA) to increase power efficiency and perform integration operations.

[0042] A discrete-time switched capacitor integrator (320) according to an embodiment of the present invention converts the output of the CT CVC (310) into a DC voltage using a chopper and then samples it through a sampling capacitor.

[0043] The discrete-time switched capacitor integrator (320) according to an embodiment of the present invention performs an integration operation after sampling through the sampling capacitor, and uses a chopper in the FIA ​​to avoid low-frequency 1 / f noise in the FIA.

[0044] An FIA according to an embodiment of the present invention includes a first storage capacitor and a second storage capacitor, stores charge in the first storage capacitor and the second storage capacitor in a sampling mode, and reduces power consumption through dynamic operation using the stored energy when the FIA ​​is operating.

[0045] A second-order noise-shaping SAR ADC (330) according to an embodiment of the present invention quantizes the output of the discrete-time switched capacitor integrator.

[0046] According to an embodiment of the present invention, the second noise shaping SAR ADC (330) stores the residual voltage of the second noise shaping SAR ADC (330) in the integrator capacitor of the discrete-time switched capacitor integrator (320) for error feedback.

[0047] A second noise shaping SAR ADC (330) according to an embodiment of the present invention stores the residual voltage in a capacitor having a capacitance greater than that of the DSM C-DAC (340) and uses charge redistribution for error feedback.

[0048] The DSM C-DAC (340) according to an embodiment of the present invention has third-order noise shaping characteristics, increases resolution, and forms a DSM loop.

[0049] The DSM C-DAC (340) according to an embodiment of the present invention performs DSM operation by controlling the DSM C-DAC (340) through a digital block including a truncator (341) and a DWA (Data-Weighted Averaging) (342) after SAR conversion is completed through the second noise shaping SAR ADC (330).

[0050] The DSM C-DAC (340) according to an embodiment of the present invention reduces the size of the DSM C-DAC (340) and increases linearity through the truncator (341), and performs a second digital DSM to eliminate errors caused by the truncator (341), thereby having third-order noise shaping characteristics in the entire loop.

[0052] FIG. 4 is a block diagram of a power-efficient continuous-discrete-time hybrid delta-sigma capacitance-to-digital converter for capacitance measurement according to one embodiment of the present invention.

[0053] FIG. 4(a) shows a block diagram of a continuous-discrete-time hybrid delta-sigma capacitance-to-digital converter according to one embodiment of the present invention, FIG. 4(b) shows a Noise Transfer Function (NTF) Pole / Zero map, and FIG. 4(c) shows an NTF conversion function.

[0054] A block diagram of a continuous-discrete-time hybrid delta-sigma capacitance-to-digital converter according to an embodiment of the present invention converts a capacitor value into a voltage through a front-end CT CVC, and a discrete-time switched capacitor integrator with an FIA performs an integration operation. Subsequently, the integrator output is quantized by a second-order fully passive noise-shaping SAR ADC. According to an embodiment of the present invention, a 5- to 4-bit digital DSM truncator is utilized to improve the linearity characteristics of the DAC.

[0056] FIG. 5 is a circuit diagram of a power-efficient continuous-discrete-time hybrid delta-sigma capacitance-to-digital converter for capacitance measurement according to one embodiment of the present invention.

[0057] Referring to FIG. 5(a), a specific circuit implementation of a continuous-discrete-time hybrid delta-sigma capacitance-digital converter according to an embodiment of the present invention includes a capacitance excitation driver (510), a CT-CVC (520), a DT-switched capacitor integrator (530), a second-order NS-SAR ADC (540), a truncator (550), a DWA (560), and a DSM C-DAC (570) which is an input cap-DAC calibration block.

[0058] Referring to FIG. 5(b), the sensor capacitor (C) of the capacitance excitation driver (510) according to an embodiment of the present invention S ) and reference capacitor (C REF ) is excited in opposite phase and CT-CVC (520) is the sensor capacitor (C S ) and reference capacitor (C REF Converts the delta-capacitance, which is the difference in capacitance between ), into voltage.

[0059] The output of CT-CVC (520) is converted into a DC voltage using a chopper, and then sampled through the sampling capacitor of a DT-switched capacitor integrator (530).

[0060] Referring to FIG. 5(c), an integration operation is performed in a DT-switched capacitor integrator (530) according to an embodiment of the present invention, and the resulting output voltage is sampled by a secondary NS-SAR ADC (540). A chopper is also used in the integrator's FIA to avoid low-frequency 1 / f in the FIA.

[0061] An FIA according to an embodiment of the present invention includes a first storage capacitor and a second storage capacitor, stores charge in the first storage capacitor and the second storage capacitor in a sampling mode, and can reduce power consumption through dynamic operation using the stored energy when the FIA ​​is operating.

[0062] Referring to FIG. 5(d), after SAR conversion is completed in the secondary NS-SAR ADC (540) according to an embodiment of the present invention, a digital block including a truncator (550) and a DWA (560) operates with a SAR conversion termination signal. The output of the digital block controls the DSM C-DAC (570) to perform the entire DSM operation.

[0063] Referring to FIG. 5(e), for error feedback, the residual voltage of the secondary NS-SAR ADC (540) according to an embodiment of the present invention is the integrator capacitor (C) of the DT-switched capacitor integrator (530).INT Save to ).

[0065] FIG. 6 is a drawing for explaining a CT-CVC according to an embodiment of the present invention.

[0066] Referring to FIG. 6(a), the CT-CVC according to an embodiment of the present invention amplifies the delta-capacitance between the sensor capacitor and the reference capacitor in the ratio of the feedback capacitance to the reference voltage. Due to the wide input range and large DC gain characteristics, a folded cascode amplifier structure is used as the amplifier of the CT-CVC.

[0067] According to an embodiment of the present invention, it consumes 4.2 uW of power and has an amplifier input referenced noise (IRN) of 2.5 uVrms, and the 1 / f corner (see FIG. 6(b)) is much lower than the excitation frequency of 15 kHz (under a load cap condition of 450 fF).

[0069] FIG. 7 is a diagram illustrating a discrete-time switched capacitor integrator according to an embodiment of the present invention.

[0070] Referring to FIG. 7, the structure of an FIA used in a discrete-time switched capacitor integrator according to an embodiment of the present invention is illustrated.

[0071] The FIA ​​according to an embodiment of the present invention uses a cascade structure to increase gain and uses dynamic operation to store charge in a storage capacitor, and can significantly reduce power consumption by using the stored energy when the FIA ​​operates. In sampling mode, the outputs of the first and second stages are connected to a VCM to adjust the output common mode.

[0073] FIG. 8 is a drawing for explaining an FIA according to an embodiment of the present invention.

[0074] Referring to FIG. 8, the FIA ​​according to an embodiment of the present invention consumes only 0.84 uW of power and uses a first storage capacitor of 7.2 pF and a second storage capacitor of 1.8 pF, which generates a dominant pole (p2) at the output of the second stage (indicated in the upper right corner of the diagram). When charge is discharged during amplification, the dominant pole moves forward four times faster than the second pole because the second storage capacitor is smaller, and the loop can always be stabilized. Therefore, the design according to an embodiment of the present invention is suitable for closed-loop integrator applications.

[0076] FIG. 9 is a diagram illustrating a second-order noise shaping SAR ADC according to one embodiment of the present invention.

[0077] According to an embodiment of the present invention, the residual voltage of the second-order noise-shaping SAR ADC is stored in a capacitor having a capacitance three times greater than that of the DSM C-DAC, and charge redistribution is utilized for error feedback. The multiple-input comparator (1-0.75z -1 It is used to generate the squared NTF.

[0079] FIG. 10 is a drawing for explaining a truncator according to one embodiment of the present invention.

[0080] Referring to FIG. 10(a), the truncator according to an embodiment of the present invention may be a 5-4 bit digital DSM truncator. The truncator according to an embodiment of the present invention can be used to reduce the size of a DSM C-DAC and improve linearity. However, truncator errors may occur during this operation. To reduce these errors, a second-order digital DSM can be used to have third-order noise shaping characteristics in the entire loop.

[0081] Referring to FIG. 10(b), as can be seen from the simulation results according to an embodiment of the present invention, the blue line shows a 26dB improvement in SNDR compared to the green line without using a digital DSM. In addition, the blue line exhibits SNDR characteristics similar to a 5-bit DAC without a truncator.

[0083] FIG. 11 is a drawing for explaining a DSM C-DAC according to one embodiment of the present invention.

[0084] The DSM C-DAC according to an embodiment of the present invention is performed through a coarse capacitor DAC calibration loop process. The unit capacitance is 20fF, and the CVC output is connected to a comparator to form a synchronous SAR loop, which can increase the range of the input capacitance.

[0086] FIG. 12 is a flowchart illustrating the operation method of a power-efficient continuous-discrete-time hybrid delta-sigma capacitance-to-digital converter for capacitance measurement according to one embodiment of the present invention.

[0087] A method of operation of a power-efficient continuous-discrete-time hybrid delta-sigma capacitance-to-digital converter for capacitance measurement according to an embodiment of the present invention comprises: a step (1210) of reducing the total noise bandwidth and converting the input capacitor value into a voltage using anti-aliasing characteristics through a continuous-time capacitance-to-voltage converter; a step (1220) of receiving the voltage and increasing power efficiency and performing an integration operation through a discrete-time switched capacitor integrator using a Floating Inverter Amplifier (FIA); a step (1230) of quantizing the output of the discrete-time switched capacitor integrator through a second-order noise-shaping SAR ADC; and a step (1240) of having third-order noise-shaping characteristics and increasing the resolution through a DSM C-DAC constituting a DSM loop.

[0088] In step (1210), the total noise bandwidth is reduced and the input capacitor value is converted into a voltage using anti-aliasing characteristics through a continuous-time capacitance-voltage converter.

[0089] According to an embodiment of the present invention, the delta-capacitance, which is the capacitance difference between the sensor capacitor and the reference capacitor of a capacitance excitation driver excited in opposite phases, is converted into a voltage.

[0090] According to an embodiment of the present invention, the delta-capacitance, which is the capacitance difference between the sensor capacitor and the reference capacitor, is amplified through a folded cascode amplifier at the ratio of the feedback capacitance to the reference voltage.

[0091] In step (1220), the voltage is input, and power efficiency is increased and integration is performed through a discrete-time switched capacitor integrator using FIA.

[0092] According to an embodiment of the present invention, the output of the continuous-time capacitance-voltage converter is converted into a DC voltage using a chopper, and then sampled through a sampling capacitor.

[0093] According to an embodiment of the present invention, an integral operation is performed after sampling through the sampling capacitor, and a chopper is used in the FIA ​​to avoid low-frequency 1 / f noise in the FIA, and the FIA ​​includes a first storage capacitor and a second storage capacitor, and charges are stored in the first storage capacitor and the second storage capacitor in the sampling mode, and power consumption can be reduced through dynamic operation using the stored energy when the FIA ​​is operating.

[0094] In step (1230), the output of the discrete-time switched capacitor integrator is quantized through the second-order noise-shaping SAR ADC.

[0095] According to an embodiment of the present invention, for error feedback, the residual voltage of the second-order noise-shaping SAR ADC is stored in the integrator capacitor of the discrete-time switched capacitor integrator.

[0096] According to an embodiment of the present invention, the residual voltage is stored in a capacitor having a capacitance greater than that of the DSM C-DAC, and charge redistribution is used for error feedback.

[0097] In step (1240), the DSM C-DAC constituting the DSM loop is used to have third-order noise shaping characteristics and increase the resolution.

[0098] According to an embodiment of the present invention, after SAR conversion is completed through the second noise shaping SAR ADC, a DSM C-DAC (Delta-Sigma Modulator Capacitance Digital-to-Analog Converter) is controlled through a digital block including a truncator and a DWA (Data-Weighted Averaging) to perform DSM operation.

[0099] According to an embodiment of the present invention, the size of the DSM C-DAC is reduced and linearity is increased through the truncator, and a second digital DSM is performed to eliminate errors caused by the truncator, thereby having third-order noise shaping characteristics in the entire loop.

[0101] FIG. 13 is a graph showing the power spectral density of a digital output according to one embodiment of the present invention.

[0102] According to an embodiment of the present invention, it was implemented using a 65nm CMOS process, and the following performance was confirmed through measurements based on experimental results. Referring to Fig. 13, it can be seen that a very low noise level is observed, and the third-order positivity-noise shaping effect can also be confirmed.

[0104] FIG. 14 is a drawing showing the results of measuring capacitance resolution according to one embodiment of the present invention.

[0105] Referring to Fig. 14, the capacitive resolution of the proposed capacitive-to-digital converter can be verified, demonstrating very high performance of 25.2 aFrms (@CS = 0.14 pF) (see Fig. 14(a)) and 30.9 aFrms (@CS = 2.38 pF) (see Fig. 14(b)). Furthermore, despite achieving such high resolution, it consumes only 9.8 μW of power, exhibiting very high power efficiency. Finally, it achieves a performance index (FoM) of 177.7 dB. S Achieved the highest FoM among existing capacitive-to-digital converters focused on power efficiency. S Achieved.

[0107] The device described above may be implemented as a hardware component, a software component, and / or a combination of a hardware component and a software component. For example, the device and components described in the embodiments may be implemented using one or more general-purpose or special-purpose computers, such as, for example, a processor, a controller, an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field programmable gate array (FPGA), a programmable logic unit (PLU), a microprocessor, or any other device capable of executing and responding to instructions. The processing unit may execute an operating system (OS) and one or more software applications executed on said operating system. Additionally, the processing unit may access, store, manipulate, process, and generate data in response to the execution of the software. For ease of understanding, the processing unit may be described as being used as a single unit, but those skilled in the art will understand that the processing unit may include a plurality of processing elements and / or a plurality of types of processing elements. For example, the processing unit may include multiple processors or one processor and one controller. Additionally, other processing configurations, such as parallel processors, are also possible.

[0108] Software may include computer programs, code, instructions, or a combination of one or more of these, and may configure a processing unit to operate as desired or instruct the processing unit independently or collectively. Software and / or data may be embodied in any type of machine, component, physical device, virtual equipment, computer storage medium, or device so as to be interpreted by the processing unit or to provide instructions or data to the processing unit. Software may be distributed over networked computer systems and may be stored or executed in a distributed manner. Software and data may be stored on one or more computer-readable recording media.

[0109] The method according to the embodiment may be implemented in the form of program instructions that can be executed through various computer means and recorded on a computer-readable medium. The computer-readable medium may include program instructions, data files, data structures, etc., either alone or in combination. The program instructions recorded on the medium may be those specifically designed and configured for the embodiment, or they may be those known and available to those skilled in the art of computer software. Examples of computer-readable recording media include magnetic media such as hard disks, floppy disks, and magnetic tapes; optical recording media such as CD-ROMs and DVDs; magneto-optical media such as floptical disks; and hardware devices specifically configured to store and execute program instructions, such as ROM, RAM, and flash memory. Examples of program instructions include machine code, such as that generated by a compiler, as well as high-level language code that can be executed by a computer using an interpreter, etc.

[0110] Although the embodiments have been described above with reference to limited examples and drawings, those skilled in the art can make various modifications and variations from the description above. For example, suitable results can be achieved even if the described techniques are performed in a different order than described, and / or the components of the described system, structure, device, circuit, etc. are combined or assembled in a form different from described, or replaced or substituted by other components or equivalents.

[0111] Therefore, other implementations, other embodiments, and equivalents to the claims also fall within the scope of the claims set forth below.

Claims

Claim 1 A delta-sigma capacitance-to-digital converter comprising: a continuous-time capacitance-to-voltage converter that reduces the total noise bandwidth using anti-aliasing characteristics and converts the input capacitor value into a voltage; a discrete-time switched capacitor integrator that receives the voltage, increases power efficiency using a Floating Inverter Amplifier (FIA), and performs an integration operation; a second-order noise-shaping SAR ADC that quantizes the output of the discrete-time switched capacitor integrator; and a DSM C-DAC that uses the output residual voltage of the second-order noise-shaping SAR ADC to form a delta-sigma modulation loop under the control of a truncator and a Data-Weighted Averaging (DWA) block and performs third-order noise shaping. Claim 2 In claim 1, the continuous-time capacitance-voltage converter is a delta-sigma capacitance-digital converter that converts the delta-capacitance, which is the capacitance difference between a sensor capacitor and a reference capacitor included in a capacitance excitation driver excited in opposite phases, into a voltage. Claim 3 In paragraph 2, the continuous-time capacitance-voltage converter comprises a feedback capacitance connected to a feedback path of a folded cascode amplifier, wherein the feedback capacitance amplifies the delta-capacitance by accumulating a charge corresponding to the capacitance difference between the sensor capacitor and the reference capacitor with respect to a reference potential set by a reference voltage. Claim 4 In claim 1, the discrete-time switched capacitor integrator is a delta-sigma capacitance-to-digital converter that converts the output of the continuous-time capacitance-to-voltage converter into a DC voltage using a chopper and then samples it through a sampling capacitor. Claim 5 In claim 4, the discrete-time switched capacitor integrator performs an integration operation after sampling through the sampling capacitor, and is a delta-sigma capacitance-to-digital converter that uses a chopper in the FIA ​​to avoid low-frequency 1 / f noise in the FIA. Claim 6 In claim 5, the above FIA ​​comprises a first storage capacitor and a second storage capacitor, stores charge in the first storage capacitor and the second storage capacitor in a sampling mode, and reduces power consumption through dynamic operation using the stored energy when the FIA ​​is operated. Claim 7 In claim 1, the second-order noise-shaping SAR ADC is a delta-sigma capacitance-to-digital converter that stores the residual voltage of the second-order noise-shaping SAR ADC in the integrator capacitor of the discrete-time switched capacitor integrator for error feedback. Claim 8 In claim 7, the second-order noise-shaping SAR ADC stores the residual voltage in a capacitor having a capacitance greater than the combined capacitance of a plurality of capacitors constituting the DSM C-DAC to store the residual voltage, and forms an error feedback loop by redistributing the stored charge to the input node of the DSM C-DAC. Claim 9 In claim 1, the above DSM C-DAC is a delta-sigma capacitance-to-analog converter that performs DSM operation by controlling the DSM C-DAC (Delta-Sigma Modulator Capacitance Digital-to-Analog Converter) through a digital block including a truncator and a DWA (Data-Weighted Averaging) after SAR conversion is completed through the above second-order noise shaping SAR ADC. Claim 10 In claim 9, the DSM C-DAC performs a second-order digital DSM to reduce the size of the DSM C-DAC and increase linearity through the truncator and eliminate errors caused by the truncator, and has a third-order noise shaping characteristic in the entire loop where the loop of the second-order digital DSM and the delta-sigma modulation loop of the DSM C-DAC are combined. Claim 11 A method of operation of a delta-sigma capacitance-to-digital converter comprising: a step of reducing the total noise bandwidth and converting the input capacitor value into a voltage by utilizing anti-aliasing characteristics through a continuous-time capacitance-to-voltage converter; a step of receiving the voltage and increasing power efficiency and performing an integration operation through a discrete-time switched capacitor integrator using a Floating Inverter Amplifier (FIA); a step of quantizing the output of the discrete-time switched capacitor integrator through a second-order noise-shaping SAR ADC; and a step of having third-order noise-shaping characteristics and increasing the resolution through a DSM C-DAC constituting a DSM loop. Claim 12 In claim 11, the step of reducing the total noise bandwidth and converting the input capacitor value into a voltage using anti-aliasing characteristics through a continuous-time capacitance-voltage converter is a method of operation of a delta-sigma capacitance-digital converter that converts the delta-capacitance, which is the capacitance difference between a sensor capacitor and a reference capacitor included in a capacitance excitation driver excited in opposite phases, into a voltage. Claim 13 In claim 12, the step of reducing the total noise bandwidth and converting the input capacitor value into a voltage using anti-aliasing characteristics through a continuous-time capacitance-voltage converter comprises a feedback capacitance connected to a feedback path of a folded cascode amplifier, wherein the feedback capacitance amplifies the delta-capacitance by accumulating a charge corresponding to the capacitance difference between the sensor capacitor and the reference capacitor with respect to a reference potential set by a reference voltage. Claim 14 In claim 11, the step of receiving the above voltage input and increasing power efficiency and performing an integration operation through a discrete-time switched capacitor integrator using FIA is a method of operation of a delta-sigma capacitance-to-digital converter in which the output of the continuous-time capacitance-to-voltage converter is converted into a DC voltage using a chopper and then sampled through a sampling capacitor. Claim 15 In claim 14, the step of receiving the above voltage and increasing power efficiency and performing an integral operation through a discrete-time switched capacitor integrator using an FIA comprises sampling through the above sampling capacitor and then performing an integral operation, using a chopper in the FIA ​​to avoid low-frequency 1 / f noise in the FIA, wherein the FIA ​​includes a first storage capacitor and a second storage capacitor, storing charge in the first storage capacitor and the second storage capacitor in a sampling mode, and reducing power consumption through dynamic operation using the stored energy when the FIA ​​operates. Claim 16 In claim 11, the step of quantizing the output of the discrete-time switched capacitor integrator through the second-order noise-shaping SAR ADC comprises storing the residual voltage of the second-order noise-shaping SAR ADC in the integrator capacitor of the discrete-time switched capacitor integrator for error feedback, in a method of operation of a delta-sigma capacitance-to-digital converter. Claim 17 In claim 16, the step of quantizing the output of the discrete-time switched capacitor integrator through the second-order noise-shaping SAR ADC comprises storing the residual voltage in a capacitor having a capacitance greater than the combined capacitance of a plurality of capacitors constituting the DSM C-DAC to store the residual voltage, and forming an error feedback loop by redistributing the stored charge to the input node of the DSM C-DAC. Claim 18 In claim 11, the step of having a third-order noise shaping characteristic and increasing the resolution through a DSM C-DAC constituting the DSM loop is a method of operation of a delta-sigma capacitance-to-analog converter that performs DSM operation by controlling a DSM C-DAC (Delta-Sigma Modulator Capacitance Digital-to-Analog Converter) through a digital block including a truncator and a DWA (Data-Weighted Averaging) after SAR conversion is completed through the second-order noise shaping SAR ADC. Claim 19 In claim 18, the step of having a third-order noise shaping characteristic and increasing the resolution through a DSM C-DAC constituting the DSM loop comprises: performing a second-order digital DSM to reduce the size of the DSM C-DAC and increase linearity through the truncator and to eliminate errors caused by the truncator, and having a third-order noise shaping characteristic in the entire loop where the loop of the second-order digital DSM and the delta-sigma modulation loop of the DSM C-DAC are combined. Claim 20 A delta-sigma capacitance-to-digital converter that includes a discrete-time switched capacitor integrator that receives a voltage converted through a continuous-time capacitance-to-voltage converter and performs an integral operation using a Floating Inverter Amplifier (FIA) to increase power efficiency, wherein the discrete-time switched capacitor integrator converts the output of the continuous-time capacitance-to-voltage converter into a DC voltage using a chopper, samples it through a sampling capacitor, performs an integral operation after sampling through the sampling capacitor, and uses a chopper in the FIA ​​to avoid low-frequency 1 / f noise in the FIA, wherein the FIA ​​includes a first storage capacitor and a second storage capacitor, stores charge in the first storage capacitor and the second storage capacitor in a sampling mode, and reduces power consumption through dynamic operation using the stored energy when the FIA ​​operates.

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