Semiconductor interface device and semiconductor system including the same

Abstract

The present disclosure provides a semiconductor interface device comprising a plurality of first delay circuits, a clock delay circuit, a plurality of flip-flop groups, a PLL, a first FIFO register, third flip-flops, a first multiplexer, and a second delay circuit, and a semiconductor system comprising the same.

Description

Technology Field

[0001] The embodiments of the present disclosure relate to an electronic device and a method of operating the same, and more specifically, to a semiconductor interface device and a semiconductor system including the same. Background Technology

[0002] In order to ensure the quality and reliability of chips manufactured in the semiconductor industry, semiconductor test equipment (also referred to as ATE (Automatic Test Equipment)) is an essential facility. Semiconductor test equipment applies various electrical signals and patterns to a chip to be tested (e.g., referred to as DUT (Device Under Test)), and measures and analyzes the response to inspect for functional and electrical defects of the chip.

[0003] Semiconductor test devices are equipped with high-speed digital signal generation and response analysis capabilities. Recently, Field Programmable Gate Arrays (FPGAs) have been utilized to flexibly and rapidly implement functions such as test pattern generation, DUT control, and data processing. FPGAs provide the flexibility to quickly change hardware configurations in response to changes in test requirements and improve test speed by processing test algorithms in parallel. Semiconductor test devices capture information such as the time, location (address), and data of a DUT failure and store it in an internal fail memory. The fail data stored in the fail memory is used to analyze the type of chip defect and its cause.

[0004] In conventional semiconductor test devices for testing high-bandwidth memory such as HBM (High Bandwidth Memory), there are problems such as a shortage of pins for transmitting signals due to the limited width of test sites and an increase in bus turnaround sections when simultaneously pipelined read and write traffic. Accordingly, there is a need to develop an interface for semiconductor test devices that can provide a variety of pins even in a limited space. Prior art literature

[0005] Published Patent Application, No. 10-2021-0065263 (June 4, 2021) The problem to be solved

[0006] These conventional methods have problems such as a shortage of pins for transmitting signals due to the limited width of the test site, and an increase in the bus turnaround section when pipelined lead and write traffic simultaneously.

[0007] The embodiments of the present disclosure aim to provide a semiconductor interface device and a semiconductor system including the same for solving various problems, including the problems mentioned above.

[0008] However, these tasks are exemplary and do not limit the scope of the present disclosure. means of solving the problem

[0009] According to one aspect of the present disclosure, a plurality of first delay circuits that delay a plurality of data signals and output a plurality of delay signals; a clock delay circuit that delays an external input clock signal and outputs a delayed input clock signal; a plurality of flip-flop groups that receive the plurality of delay signals and output slice-specific first signals and second signals in response to the delayed input clock signal; a phase-locked loop (PLL) that changes the frequency of the delayed input clock signal based on the delayed input clock signal and outputs a clock signal having the changed frequency; a first FIFO (First-In First-Out) register that outputs a first partial signal corresponding to a portion of the slice-specific first signals and a second partial signal corresponding to a portion of the slice-specific second signals in response to the delayed input clock signal and the clock signal; third flip-flops that output the first partial signals and the second partial signals respectively input in response to the clock signal; and the first partial signal output from the third flip-flops using the clock signal as a selection signal. A semiconductor interface device is provided, comprising a first multiplexer for selecting signals or the second set of signals, and a second delay circuit for delaying a signal output from the first multiplexer and outputting a plurality of DQ signals.

[0010] According to the present embodiment, the plurality of data signals include first data signals corresponding to a first slice, second data signals corresponding to a second slice, third data signals corresponding to a third slice, and fourth data signals corresponding to a fourth slice, and the plurality of first delay circuits may include four delay circuits that receive data signals for each slice.

[0011] According to the present embodiment, the plurality of flip-flop groups may include first flip-flops that receive delay signals for data signals for each slice and second flip-flops connected to the outputs of the first flip-flops.

[0012] According to the present embodiment, the first data signals, the second data signals, the third data signals, and the fourth data signals are each 32-bit data signals, the number of the first flip-flops and the number of the second flip-flops are each 8, the first signals and the second signals per slice are each 8-bit signals, and the first partial signals and the second partial signals may each be 8-bit signals.

[0013] According to the present embodiment, the plurality of flip-flop groups may include a first flip-flop group that receives the plurality of delay signals, and a second flip-flop group that receives the output signals of the first flip-flop group.

[0014] According to one aspect of the present disclosure, a first delay circuit that delays a read data strobe signal provided from a semiconductor device and outputs a delayed strobe signal; a second delay circuit that delays a plurality of DQ signals provided from the semiconductor device and outputs a plurality of delay signals; first flip-flops that receive the plurality of delay signals and output a plurality of first signals and a plurality of second signals in response to the delayed strobe signal; a clock delay circuit that delays an external input clock signal and outputs a delayed input clock signal; a phase-locked loop (PLL) that changes the frequency of the delayed input clock signal based on the delayed input clock signal and outputs a clock signal having the changed frequency; a first FIFO register that outputs the plurality of first signals and the plurality of second signals of the first flip-flops in response to the clock signal and the delayed data strobe signal; a second FIFO register that outputs a plurality of signals of the first FIFO register in response to the delayed input clock signal and the clock signal; and the plurality of signals received and A semiconductor interface device is provided, comprising a plurality of second flip-flops that output the plurality of signals in response to a delayed input clock signal, and a plurality of first multiplexers that select the signals output from the plurality of second flip-flops using the delayed input clock signal as a selection signal.

[0015] According to the present embodiment, the number of first flip-flops is two, and the delayed strobe signal is input to the club input of one of the first flip-flops, and the inverted signal of the delayed strobe signal can be input to the club input of the other of the first flip-flops.

[0016] According to the present embodiment, the clock delay circuit can correct the phase of the input clock signal to 90 degrees.

[0017] According to the present embodiment, the plurality of signals output from the second FIFO register include first to eight signals, the number of the plurality of second flip-flops is eight, and the plurality of second flip-flops can receive the first to eight signals.

[0018] According to the present embodiment, the number of the plurality of first multiplexers is four, and each first multiplexer can receive the output of two second flip-flops.

[0019] Other aspects, features, and advantages other than those described above will become clear from the following specific details, claims, and drawings for implementing the invention.

[0020] In addition, these general and specific aspects may be implemented using a system, method, computer program, or any combination of a system, method, or computer program. Effects of the invention

[0021] According to an exemplary embodiment of the present disclosure, the bus turnaround interval ('tRTW') is shortened (e.g., shortened to 2 clocks), cross-toggle collisions are eliminated, and read / write commands are made easier to issue in parallel.

[0022] Of course, the scope of the present disclosure is not limited by these effects. Brief explanation of the drawing

[0023] FIG. 1 is a block diagram of a semiconductor system according to an exemplary embodiment of the present disclosure. FIG. 2 is a block diagram of a semiconductor interface device according to an exemplary embodiment of the present disclosure. FIG. 3 is a timing diagram of signals for performing read and write operations of a semiconductor system according to an exemplary embodiment of the present disclosure. FIG. 4 is a timing diagram of signals provided to a semiconductor device from a semiconductor interface device according to the light operation of the present disclosure. FIG. 5 is a timing diagram of signals provided to a semiconductor device from a semiconductor interface device according to the read operation of the present disclosure. FIG. 6 is a drawing for illustrating the arrangement of a semiconductor system according to an exemplary embodiment of the present disclosure. FIG. 7 is a drawing for illustrating the arrangement of two core boards according to an exemplary embodiment of the present disclosure. FIG. 8 is a drawing for illustrating the arrangement of a control board according to an exemplary embodiment of the present disclosure. FIG. 9 is a drawing illustrating the arrangement of two Device Power Supply (DPS) boards according to an exemplary embodiment of the present disclosure. FIG. 10 is a drawing for explaining the arrangement of a plurality of DUT boards according to an exemplary embodiment of the present disclosure. FIG. 11 is a drawing for explaining the arrangement of a plurality of core boards according to an exemplary embodiment of the present disclosure. FIGS. 12 and FIGS. 13 are drawings for explaining the upper and lower parts of a semiconductor system according to an exemplary embodiment of the present disclosure. FIGS. 14 and FIGS. 15 are side views of a semiconductor system according to an exemplary embodiment of the present disclosure. Specific details for implementing the invention

[0024] Specific structural or functional descriptions of the embodiments are disclosed for illustrative purposes only and may be modified and implemented in various forms. Accordingly, actual implementations are not limited to the specific embodiments disclosed, and the scope of this specification includes modifications, equivalents, or substitutions included in the technical concept described by the embodiments.

[0025] Terms such as "first" or "second" may be used to describe various components, but these terms should be interpreted solely for the purpose of distinguishing one component from another. For example, the first component may be named the second component, and similarly, the second component may be named the first component.

[0026] In the following examples, singular expressions include plural expressions unless the context clearly indicates otherwise.

[0027] In the following embodiments, terms such as "comprising" or "having" mean that the features or components described in the specification are present, and do not preclude the possibility that one or more other features or components may be added.

[0028] In the following embodiments, when a part such as a layer, region, or component is described as being on or above another part, it includes not only cases where it is directly on top of another part, but also cases where another region, component, etc. is interposed in between.

[0029] In the drawings, the size of components may be exaggerated or reduced for convenience of explanation. For example, the size and thickness of each component shown in the drawings are depicted arbitrarily for convenience of explanation, and therefore the present disclosure is not necessarily limited to what is depicted.

[0030] Where an embodiment can be implemented differently, a specific sequence of operations may be performed differently from the order described. For example, two steps described consecutively may be performed substantially simultaneously or proceed in the reverse order of the description.

[0031] In this specification, “A and / or B” indicates the case where it is A, B, or both A and B. Additionally, phrases such as “at least one of A and B,” “at least one of A or B,” “at least one of A, B and C,” and “at least one of A, B, or C” may each include any one of the items listed together in the corresponding phrase, or all possible combinations thereof. For example, “at least one of A and B” indicates the case where it is A, B, or both A and B.

[0032] In the following embodiments, when layers, regions, components, etc. are described as being connected, this includes cases where the layers, regions, components are directly connected, or / or cases where other layers, regions, components are interposed between the layers, regions, components to form an indirect connection. For example, when layers, regions, components, etc. are described as being electrically connected in this specification, it indicates cases where the layers, regions, components, etc. are directly electrically connected, and / or cases where other layers, regions, components, etc. are interposed between them to form an indirect electrical connection.

[0033] The x-axis, y-axis, and z-axis are not limited to the three axes of an orthogonal coordinate system but can be interpreted in a broader sense that includes them. For example, the x-axis, y-axis, and z-axis may be orthogonal to each other, but they may also refer to different directions that are not orthogonal to each other.

[0034] The advantages and features of the present disclosure and the methods for achieving them will become clear by referring to the embodiments described below in detail together with the accompanying drawings. However, the present disclosure is not limited to the embodiments disclosed below but may be implemented in various different forms. These embodiments are provided merely to ensure that the disclosure is complete and to fully inform those skilled in the art of the scope of the present disclosure, and the present disclosure is defined only by the scope of the claims.

[0035] The terms used in this disclosure are for describing the embodiments and are not intended to limit this disclosure. In this disclosure, the singular form may include the plural form unless specifically stated otherwise in the text. The terms “comprises” and / or “comprising” used in this disclosure do not exclude the presence or addition of one or more other components in addition to the components mentioned. Throughout the disclosure, the same reference numerals refer to the same components, and “and / or” may include each of the mentioned components and all combinations of one or more. Although terms such as “first,” “second,” etc., are used to describe various components, these components are not limited by these terms. These terms are used merely to distinguish one component from another. Accordingly, the first component mentioned below may be the second component within the technical scope of this disclosure.

[0036] The word "exemplary" is used in this disclosure to mean "used as an example or illustration." Any embodiment described as "exemplary" in this disclosure should not be interpreted as being preferred or having an advantage over other embodiments.

[0037] Embodiments of the present disclosure may be described in terms of a function or a block performing a function.

[0038] The term “module” in this disclosure may include a unit implemented in hardware, software, or firmware, and may be used interchangeably with terms such as logic, logic block, component, or circuit, for example. A “module” may be a component formed integrally or a minimum unit of a component or part thereof that performs one or more functions. For example, according to one embodiment, a “module” may be implemented in the form of an application-specific integrated circuit (ASIC).

[0039] The term “part” in this disclosure refers to a software or hardware component, such as an FPGA or ASIC, and the “part” performs certain roles. However, the “part” is not limited to software or hardware. The “part” may be configured to reside in an addressable storage medium or configured to operate one or more processors. For example, the “part” may include components such as software components, object-oriented software components, class components, and task components, as well as processes, functions, attributes, procedures, subroutines, segments of program code, drivers, firmware, microcode, circuits, data, databases, data structures, tables, arrays, and variables. The functions provided within the components and “parts” may be combined into a smaller number of components and “parts” or further separated into additional components and “parts.” Furthermore, the components and “parts” may be implemented to operate one or more CPUs within a device or secure multimedia card. Additionally, "~part" may include one or more processors.

[0040] Embodiments of the present disclosure may be implemented using at least one software program running on at least one hardware device and may perform network management functions to control elements.

[0041] Spatially relative terms such as "below," "beneath," "lower," "above," and "upper" may be used to facilitate the description of the relationship between one component and other components as illustrated in the drawings. Spatially relative terms should be understood as encompassing different orientations of components during use or operation, in addition to the orientations depicted in the drawings. For example, if a component depicted in a drawing is inverted, a component described as "below" or "beneath" of another component may be placed "above" of that component. Therefore, the exemplary term "below" may encompass both the lower and upper directions. Components may also be oriented in other directions, and accordingly, spatially relative terms may be interpreted according to the orientation.

[0042] Unless otherwise defined, all terms used in this disclosure (including technical and scientific terms) may be used in a meaning commonly understood by those skilled in the art to which this disclosure pertains. Additionally, terms defined in commonly used dictionaries are not to be interpreted ideally or excessively unless explicitly and specifically defined otherwise.

[0043] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the attached drawings. When describing with reference to the drawings, identical or corresponding components are given the same reference numerals, and redundant descriptions thereof will be omitted.

[0044] FIG. 1 is a block diagram of a semiconductor system (100) according to an exemplary embodiment of the present disclosure.

[0045] Referring to FIG. 1, the semiconductor system (100) may include a controller (110), a semiconductor interface device (120), and a semiconductor device (130).

[0046] The controller (110) may be configured to control the operation of the semiconductor device (130). To this end, the controller (110) may provide various data and / or signals to the semiconductor interface device (120). In an exemplary embodiment, the controller (110) may provide a plurality of data signals (DATA0_A~DATA31_A, DATA0_B~DATA31_B, DATA0_C~DATA31_C, DATA0_D~DATA31_D), a plurality of data driving signals (DATA0~31_OE), a plurality of data strobe enable signals (DQS_ENB0~3), a read enable signal (Read_ENB), an input clock signal (CLK_IN), I 2 C serial clock signal (I 2 C_SCL), I 2 C serial data signal (I 2C_SDA) can be provided to the semiconductor interface device (120). In an exemplary embodiment, the controller (110) can receive a plurality of data (DATA0_A~DATA31_A, DATA0_B~DATA31_B, DATA0_C~DATA31_C, DATA0_D~DATA31_D), and a strobe signal (STRB) from the semiconductor interface device (120). In an exemplary embodiment, a plurality of data signals (DATA0_A~DATA31_A, DATA0_B~DATA31_B, DATA0_C~DATA31_C, DATA0_D~DATA31_D) may be distinguished according to the unit of the slice, and for example, with reference to FIG. 1, when there are 4 slices, the first slice corresponds to the data signals (DATA0_A~DATA31_A), the second slice corresponds to the data signals (DATA0_B~DATA31_B), the third slice corresponds to the data signals (DATA0_C~DATA31_C), and the fourth slice corresponds to the data signals (DATA0_D~DATA31_D). The number (or size) of the plurality of data driving signals (DATA0~31_OE) may correspond to the number (or size) of the data signals of each slice, for example, if the number of data signals of each slice is 32 (or the size of the data of each slice is 32 bits), the number of the plurality of data driving signals (DATA0~31_OE) may be 32. However, the present disclosure is not limited to the embodiments described above. The number of the plurality of data strobe enable signals (DQS_ENB0~3) may correspond to the number of slices.

[0047] In an exemplary embodiment, the controller (110) may have 168 wires, pins, and pads. For example, between the controller (110) and the semiconductor interface device (120), there are 32 wires for transmitting and receiving data signals (DATA0_A~DATA31_A), 32 wires for transmitting and receiving data signals (DATA0_B~DATA31_B), 32 wires for transmitting and receiving data signals (DATA0_C~DATA31_C), 32 wires for transmitting and receiving data signals (DATA0_D~DATA31_D), 32 wires for transmitting a plurality of data driving signals (DATA0~31_OE) to the semiconductor interface device (120), 4 wires for transmitting a plurality of data strobe enable signals (DQS_ENB0~3) to the semiconductor interface device (120), 1 wire for transmitting an input clock signal (CLK_IN) to the semiconductor interface device (120), and a strobe signal (STRB) to the controller (110). 1 wiring for, I 2 C serial clock signal (I 2 C_SCL) and I 2 C serial data signal (I 2 Two wires may be provided to transmit C_SDA to the semiconductor interface device (120).

[0048] The controller (110) may include a pattern generator configured to shuffle data with a byte-slice interleave-4 rule and load it into an ODDR, a tri-state FSM (Finite-State Machine) that accurately covers the transition edge between multiple data driving signals (DATA0~31_OE) and high-impedance, DQ bus skew and reflection time, an OE gate that outputs multiple data driving signals (DATA0~31_OE), and a DQS gate that outputs multiple data strobe enable signals (DQS_ENB0~3).

[0049] A semiconductor interface device (120) can interface signals between a controller (110) and a semiconductor device (130). The semiconductor interface device (120) may be referred to as a Bias Temperature Instability (BTI) slice PHY. The semiconductor interface device (120) may be implemented as an Application-Specific Integrated Circuit (ASIC) including a SERializer and DESerializer (SERDES), a strobe generator, a light data strobe generator, flip-flops, etc. In an exemplary embodiment, the semiconductor interface device (120) may be interleaved into four slices and may include 16 Field Programmable Gate Arrays (FPGAs).

[0050] The semiconductor interface device (120) can provide various data and / or signals received from the controller (110) to the semiconductor device (130). Additionally, the semiconductor interface device (120) can provide various data and / or signals received from the semiconductor device (130) to the controller (110). In an exemplary embodiment, the semiconductor interface device (120) receives a plurality of data signals (DATA0_A~DATA31_A, DATA0_B~DATA31_B, DATA0_C~DATA31_C, DATA0_D~DATA31_D) from the controller (110) and outputs a plurality of data input / output signals (DATA0_INOUT~DATA31_INOUT) to the semiconductor device (130). The size of the plurality of data input / output signals (DATA0_INOUT~DATA31_INOUT) may be 32 bits, but is not limited thereto. The semiconductor interface device (120) can receive a plurality of read data strobe signals (RD_DQS0_P~RD_DQS3_P, RD_DQS0_N~RD_DQS3_N) from the semiconductor device (130). The semiconductor interface device (120) can receive a plurality of light data strobe signals (WR_DQS0_P~WR_DQS3_P, WR_DQS0_N~WR_DQS3_N). Multiple read data strobe signals (RD_DQS0_P~RD_DQS3_P, RD_DQS0_N~RD_DQS3_N) can be configured as pairs of differential signals, and multiple light data strobe signals (WR_DQS0_P~WR_DQS3_P, WR_DQS0_N~WR_DQS3_N) can also be configured as pairs of differential signals.For example, first differential read data strobe signals (RD_DQS0_P, RD_DQS0_N), second differential read data strobe signals (RD_DQS1_P, RD_DQS1_N), third differential read data strobe signals (RD_DQS2_P, RD_DQS2_N), and fourth differential read data strobe signals (RD_DQS3_P, RD_DQS3_N) can be generated as differential signals. In addition, the first differential light data strobe signals (WR_DQS0_P, WR_DQS0_N), the second differential light data strobe signals (WR_DQS1_P, WR_DQS1_N), the third differential light data strobe signals (WR_DQS2_P, WR_DQS2_N), and the fourth differential light data strobe signals (WR_DQS3_P, WR_DQS3_N) can be generated as differential signals.

[0051] In an exemplary embodiment, the semiconductor interface device (120) may have a plurality of pins (or a plurality of pads) to which a plurality of data signals (DATA0_A~DATA31_A, DATA0_B~DATA31_B, DATA0_C~DATA31_C, DATA0_D~DATA31_D) are transmitted and received. The semiconductor interface device (120) may have a plurality of pins to receive a plurality of data driving signals (DATA0~31_OE). Additionally, the semiconductor interface device (120) may have a plurality of pins to receive a plurality of data strobe enable signals (DQS_ENB0~3). Additionally, the semiconductor interface device (120) may have a read enable signal (Read_ENB), an input clock signal (CLK_IN), I 2 C serial clock signal (I 2 C_SCL), I 2 C serial data signal (I 2 It may be equipped with multiple pins that transmit or receive C_SDA).

[0052] In an exemplary embodiment, the semiconductor interface device (120) may have 48 wires, pins, and pads. For example, between the semiconductor interface device (120) and the semiconductor device (130), 32 wires for transmitting and receiving a plurality of data input / output signals (DATA0_INOUT~DATA31_INOUT), i.e., DQ signals, 8 wires for transmitting a plurality of light data strobe signals (WR_DQS0_P~WR_DQS3_P, WR_DQS0_N~WR_DQS3_N) to the semiconductor device (130), and 8 wires for transmitting a plurality of read data strobe signals (RD_DQS0_P~RD_DQS3_P, RD_DQS0_N~RD_DQS3_N) to the semiconductor interface device (120) may be provided.

[0053] In an exemplary embodiment, the semiconductor interface device (120) can maintain a plurality of light data strobe signals (WR_DQS0_P~WR_DQS3_P, WR_DQS0_N~WR_DQS3_N) matching with the length of the PCB within ±5ps of the DQ signal.

[0054] In an exemplary embodiment, the semiconductor interface device (120) may include a plurality of first pads to which a plurality of first data signals are transmitted between the controller (110) and the semiconductor interface device (120), a plurality of second pads to which a plurality of data driving signals for driving the plurality of first data signals are transmitted, a third pad to which a data strobe enable signal for the plurality of first data signals is transmitted, a plurality of fourth pads to which a plurality of DQ signals are transmitted between the semiconductor interface device (120) and the semiconductor device (130), a plurality of fifth pads to which a pair of first write data enable signals for the plurality of DQ signals is provided to the semiconductor device (130), and a plurality of sixth pads to which a pair of first read data enable signals for the plurality of DQ signals is provided from the semiconductor device (130) to the semiconductor interface device (120).

[0055] In one embodiment, the semiconductor interface device (120) may further include a plurality of seventh pads through which a plurality of second data signals are transmitted between the controller (110) and the semiconductor interface device (120), a plurality of eighth pads through which a pair of second write data enable signals different from the pair of first write data enable signals is provided to the semiconductor device (130), and a plurality of ninth pads through which a pair of second read data enable signals different from the pair of first read data enable signals is provided to the semiconductor interface device (120).

[0056] In one embodiment, the period during which the data strobe enable signal is activated during light operation may be longer than the period during which the plurality of data driving signals are activated.

[0057] In one embodiment, when a light operation occurs, after the logic level of the data strobe enable signal is changed from a first logic level to a second logic level, the logic level of the plurality of data driving signals may be changed from the first logic level to the second logic level. After the logic level of the plurality of data driving signals is changed from the second logic level to the first logic level, the logic level of the data strobe enable signal may be changed from the second logic level to the first logic level.

[0058] In one embodiment, the semiconductor interface device (120) may further include a 10th pad, to which a read enable signal is provided from the controller (110) during a read operation. During the read operation, the plurality of data driving signals may be deactivated.

[0059] The semiconductor device (130) can receive various electrical signals and pattern data, etc., through the semiconductor interface device (100) as a DUT (Device Under Test) to be tested, and can output read data, etc., or store write data in response to the control of the controller (110) through the semiconductor interface device (100).

[0060] FIG. 2 is a block diagram of a semiconductor interface device (200) according to an exemplary embodiment of the present disclosure.

[0061] Referring to FIG. 2, the semiconductor interface device (200) is I 2It may include a C register (210), a plurality of first delay circuits (221–224), a clock delay circuit (225), first to fifth flip-flop groups (F11–F18, F21–F28, F31–F32, F41–F42, F51–F58), a Phase-Locked Loop (PLL) (230), first to third First-In First-Out (FIFO) registers (241–243), a first multiplexer (M11), a plurality of second delay circuits (251–253), a Power Management Unit (PMU) (260), first and second switches (SW1, SW2), and a second multiplexer group (M21–M24).

[0062] I 2 The C register (210) is I 2 C serial clock signal (I 2 It can receive C_SCL and provide an internal clock signal to a plurality of first delay circuits (221~224), a plurality of second delay circuits (251~253), and a PMU (260). 2 The C register (210) is I 2 C serial data signal (I 2 Can transmit and receive C_SDA.

[0063] The first delay circuits (221–224) receive an internal clock signal and a plurality of data signals (DATA0_A–DATA31_A, DATA0_B–DATA31_B, DATA0_C–DATA31_C, DATA0_D–DATA31_D) and can provide a plurality of delayed data signals to the data input (e.g., D input) of the first flip-flop group (F11–F18). In an exemplary embodiment, the first delay circuit (221) can provide the delayed data signal to the first flip-flops (F11, F12). The first delay circuit (222) can provide the delayed data signal to the first flip-flops (F13, F14). The first delay circuit (223) can provide the delayed data signal to the first flip-flops (F15, F16). The first delay circuit (224) can provide a delayed data signal to the first flip-flops (F17, F18).

[0064] A clock delay circuit (225) receives an internal clock signal and an input clock signal (CLK_IN) and can provide a delayed input clock signal to first, second, and fifth flip-flop groups (F11–F18, F21–F28, F51–F58), a PLL (230), first and second FIFO registers (241, 242), and a second multiplexer group (M21–M24). In an exemplary embodiment, the clock delay circuit (225) can provide the delayed input clock signal to the first clock input of the first, second, and fifth flip-flop groups (F11–F18, F21–F28, F51–F58) and the first and second FIFO registers (241, 242). The clock delay circuit (225) can provide a delayed input clock signal to the PLL (230) as an input and can provide the delayed input clock signal to the second multiplexer group (M21~M24) as a select signal. In an exemplary embodiment, the frequency of the input clock signal (CLK_IN) may be 1600 MHz, but is not limited thereto. The clock delay circuit (225) may be implemented as a DLL or Vernier with a variable width of ±10 ps.

[0065] In terms of the signal path of the light data strobe signals (WDQS_c, WDQS_t) (and / or WR_DQS_P, WR_DQS_N of FIG. 3), the clock delay circuit (225) can correct the phase of the input clock signal (CLK_IN) by 90 degrees in response to the internal clock signal for a tDQSS precision delay relative to CK. The DQS pattern generator can output the light data strobe signals (WDQS_c, WDQS_t) corresponding to the signal in which the phase of the input clock signal (CLK_IN) is corrected by 90 degrees to the corresponding pads and microbumps. The data strobe signals (WDQS_c, WDQS_t) are toggled between the preamble and postamble, including a logic low level (or '0' level) for one clock (CK) each for the preamble and postamble.

[0066] The PLL (230) receives a delayed input clock signal from the clock delay circuit (225) and changes the phase and / or frequency of the delayed input clock signal to provide the changed clock signal to the second clock input of the first and second FIFO registers (241, 242), the first clock input of the third FIFO register (243), and the first multiplexer (M11). The clock signal of the PLL (230) input to the first multiplexer (M11) can operate as a select signal.

[0067] The number of flip-flops included in each of the first, second, and fifth flip-flop groups (F11–F18, F21–F28, F51–F58) may be eight. The number of flip-flops included in each of the third and fourth flip-flop groups (F31–F32, F41–F42) may be two. However, the present disclosure is not limited to the examples described above.

[0068] The first flip-flop group (F11–F18) can output data signals of the input first delay circuits (221–224) in response to the clock signal of the clock delay circuit (225). In an exemplary embodiment, the first flip-flops (F11, F12) can output a data signal of the first delay circuit (221) in response to the clock signal of the clock delay circuit (225). The first flip-flops (F13, F14) can output a data signal of the first delay circuit (222) in response to the clock signal of the clock delay circuit (225). The first flip-flops (F15, F16) can output a data signal of the first delay circuit (223) in response to the clock signal of the clock delay circuit (225). The first flip-flops (F17, F18) can output a data signal of the first delay circuit (224) in response to a clock signal of the clock delay circuit (225).

[0069] The second flip-flop group (F21~F28) can output signals from the first flip-flop group (F11~F18) that are input in response to the clock signal of the clock delay circuit (225). In an exemplary embodiment, the second flip-flop (F21) can output signals (DATA0~7_A_H) in response to the clock signal of the clock delay circuit (225). The second flip-flop (F22) can output signals (DATA0~7_A_L) in response to the clock signal of the clock delay circuit (225). The second flip-flop (F23) can output signals (DATA0~7_B_H) in response to the clock signal of the clock delay circuit (225). The second flip-flop (F24) can output signals (DATA0~7_B_L) in response to the clock signal of the clock delay circuit (225). The second flip-flop (F25) can output a signal (DATA0~7_C_H) in response to the clock signal of the clock delay circuit (225). The second flip-flop (F26) can output a signal (DATA0~7_C_L) in response to the clock signal of the clock delay circuit (225). The second flip-flop (F27) can output a signal (DATA0~7_D_H) in response to the clock signal of the clock delay circuit (225). The second flip-flop (F28) can output a signal (DATA0~7_D_L) in response to the clock signal of the clock delay circuit (225).

[0070] The first FIFO register (241) receives signals (DATA0~7_A_H, DATA0~7_A_L, DATA0~7_B_H, DATA0~7_B_L, DATA0~7_C_H, DATA0~7_C_L, DATA0~7_D_H, DATA0~7_D_L) of the second flip-flop group (F21~F28) in response to the clock signal of the clock delay circuit (225), and can output some signals (DATA0~7_H_OUT, DATA0~7_L_OUT) to the third flip-flop group (F31~F32) in response to the clock signal of the PLL (230). In an exemplary embodiment, signals (DATA0~7_H_OUT) are input to the third flip-flop (F31), and signals (DATA0~7_L_OUT) can be input to the third flip-flop (F32).

[0071] The third flip-flop group (F31~F32) can output signals (DATA0~7_H_OUT, DATA0~7_L_OUT) in response to the clock signal of the PLL (230).

[0072] The first multiplexer (M11) can select the signal output from the third flip-flop (F31) or the signal output from the third flip-flop (F32) using the clock signal of the PLL (230) as a select signal.

[0073] The second delay circuit (251) is I 2 In response to the internal clock signal of the C register (210), the signal of the first multiplexer (M11) can be delayed and the delayed signal can be output. The delayed signal can be provided to the semiconductor device (130) as DQ signals (DQ0~31_A) when the first switch (SW1) is turned on.

[0074] The second delay circuit (252) is I 2In response to the internal clock signal of the C register (210), the read data strobe signals (RD_DQS0~3) of the semiconductor device (130) can be delayed, and the delayed data strobe signals can be output to the clock input of the fourth flip-flop group (F41~F42) and the second clock input of the third FIFO register (243).

[0075] The second delay circuit (253) is I 2 In response to the internal clock signal of the C register (210), the DQ signals (DQ0~31_A) provided from the semiconductor device (130) can be delayed, and the delayed DQ signals can be output to the data input of the fourth flip-flop group (F41~F42).

[0076] The fourth flip-flop group (F41~F42) can output DQ signals of the second delay circuit (253) in response to data strobe signals of the second delay circuit (252).

[0077] The third FIFO register (243) can receive signals from the fourth flip-flop group (F41~F42) in response to the data strobe signals of the second delay circuit (252) and output signals in response to the clock signal of the PLL (230).

[0078] The second FIFO register (242) can receive signals from the third FIFO register (243) in response to the clock signal of the PLL (230) and output signals in response to the clock signal of the clock delay circuit (225).

[0079] In an exemplary embodiment, the first FIFO register (241) may be an 8:2 FIFO structure that receives 8 signals and outputs 2 signals, the second FIFO register (242) may be a 2:8 FIFO structure that receives 2 signals and outputs 8 signals, and the third FIFO register (243) may be a 2:2 FIFO structure that receives 2 signals and outputs 2 signals.

[0080] The fifth flip-flop group (F51–F58) can provide eight signals of the second FIFO register (242) to the second multiplexer group (M21–M24) in response to the clock signal of the clock delay circuit (225). In an exemplary embodiment, the fifth flip-flops (F51, F52) can provide two signals of the second FIFO register (242) to the second multiplexer (M21) in response to the clock signal of the clock delay circuit (225). The fifth flip-flops (F53, F54) can provide the other two signals of the second FIFO register (242) to the second multiplexer (M22) in response to the clock signal of the clock delay circuit (225). The fifth flip-flops (F55, F56) can provide two other signals of the second FIFO register (242) to the second multiplexer (M23) in response to the clock signal of the clock delay circuit (225). The fifth flip-flops (F57, F58) can provide two other signals of the second FIFO register (242) to the second multiplexer (M24) in response to the clock signal of the clock delay circuit (225).

[0081] The second multiplexer group (M21~M24) can select signals of the fifth flip-flop group (F51~F58) using the clock signal of the clock delay circuit (225) as a selection signal. The second multiplexer group (M21~M24) can sequentially select 32-bit data signals over 4 clocks in the order of the slices. The signals selected by the second multiplexer group (M21~M24) can be provided to the controller (110) as multiple data signals (DATA0_A~DATA31_A, DATA0_B~DATA31_B, DATA0_C~DATA31_C, DATA0_D~DATA31_D). A MUX shuffle LUT of 1 GHz or higher can be stored in the semiconductor interface device (200).

[0082] The PMU (260) can manage power within the semiconductor interface device (200). The PMU (260) can be electrically connected to a pin where DQ signals (DQ0~31_A) are transmitted and received when the second switch (SW2) is turned on.

[0083] In an exemplary embodiment, the semiconductor interface device (200) comprises: a plurality of first delay circuits that delay a plurality of data signals and output a plurality of delay signals; a clock delay circuit that delays an external input clock signal and outputs a delayed input clock signal; a plurality of flip-flop groups that receive the plurality of delay signals and output slice-specific first signals and second signals in response to the delayed input clock signal; a PLL that changes the frequency of the delayed input clock signal based on the delayed input clock signal and outputs a clock signal having the changed frequency; a first FIFO register that outputs a first partial signal corresponding to a portion of the slice-specific first signals and a second partial signal corresponding to a portion of the slice-specific second signals in response to the delayed input clock signal and the clock signal; third flip-flops that output the first partial signals and the second partial signals respectively input in response to the clock signal; and a first circuit that selects the first partial signals or the second partial signals output from the third flip-flops using the clock signal as a selection signal. It may include a multiplexer and a second delay circuit that delays a signal output from the first multiplexer and outputs a plurality of DQ signals.

[0084] According to one embodiment, the plurality of data signals may include first data signals corresponding to a first slice, second data signals corresponding to a second slice, third data signals corresponding to a third slice, and fourth data signals corresponding to a fourth slice. The plurality of first delay circuits may include four delay circuits that receive data signals for each slice.

[0085] According to one embodiment, the plurality of flip-flop groups may include first flip-flops that receive delay signals for data signals for each slice and second flip-flops connected to the outputs of the first flip-flops.

[0086] According to one embodiment, the first data signals, the second data signals, the third data signals, and the fourth data signals may each be 32-bit data signals. The number of the first flip-flops and the number of the second flip-flops may each be 8. The first signals and the second signals per slice may each be 8-bit signals. The first partial signals and the second partial signals may each be 8-bit signals.

[0087] According to one embodiment, the plurality of flip-flop groups may include a first flip-flop group that receives the plurality of delay signals, and a second flip-flop group that receives the output signals of the first flip-flop group.

[0088] In an exemplary embodiment, the semiconductor interface device (200) comprises: a first delay circuit that delays a read data strobe signal provided from a semiconductor device and outputs a delayed strobe signal; a second delay circuit that delays a plurality of DQ signals provided from the semiconductor device and outputs a plurality of delay signals; first flip-flops that receive the plurality of delay signals and output a plurality of first signals and a plurality of second signals in response to the delayed strobe signal; a clock delay circuit that delays an external input clock signal and outputs a delayed input clock signal; a PLL that changes the frequency of the delayed input clock signal based on the delayed input clock signal and outputs a clock signal having the changed frequency; a first FIFO register that outputs the plurality of first signals and the plurality of second signals of the first flip-flops in response to the clock signal and the delayed data strobe signal; a second FIFO register that outputs a plurality of signals of the first FIFO register in response to the delayed input clock signal and the clock signal; and receiving the plurality of signals and the delayed input clock It may include a plurality of second flip-flops that output the plurality of signals in response to a signal, and a plurality of first multiplexers that select the signals output from the plurality of second flip-flops using the delayed input clock signal as a selection signal.

[0089] According to one embodiment, the number of the first flip-flops is two, and the delayed strobe signal is input to the club input of one of the first flip-flops, and the inverted signal of the delayed strobe signal can be input to the club input of the other of the first flip-flops.

[0090] According to one embodiment, the clock delay circuit can correct the phase of the input clock signal to 90 degrees.

[0091] According to one embodiment, the plurality of signals output from the second FIFO register may include first to eighth signals. The number of the plurality of second flip-flops may be eight. The plurality of second flip-flops may receive the first to eighth signals.

[0092] According to one embodiment, the number of the plurality of first multiplexers may be four. Each first multiplexer can receive the output of two second flip-flops.

[0093] Although not shown, the semiconductor interface device (200) utilizes chip-package re-mapping for PAR corresponding to command / address parity consisting of 4 wires, DERR corresponding to data CRC error flags consisting of 4 wires, RD[7:0], RR, and RC spare lines corresponding to data CRC error flags, thereby improving the yield by 0.5-1%.

[0094] The semiconductor interface device (200) of the present disclosure can be defined as a comprehensive PHY-TX architecture for implementing low-latency and high-reliability DDR5 and wide-I / O write paths in a high-density 3D package environment, and can configure separation of data strobe lines, hard gating of data driving lines and data strobe lines, microbump (μ-bump)-based redundancy, and low-latency pipelines. Microbumps refer to ultra-small solder bumps used in 3D-IC and HBM packages. The diameter of the microbumps may be about 20 to 40 μm, which is more than 10 times smaller than the size of a typical BGA ball (about 0.3 to 0.6 mm). Microbumps may be placed at the ends of Through-Silicon Via (TSVs) placed between a silicon die (e.g., DRAM) and a silicon interposer, and / or TSVs placed between dies. The pitch of the microbumps can be about 40 to 55 μm, and accordingly, hundreds to thousands of inputs and outputs (I / O) can be transmitted and received without thermal area loss, so they can be essentially provided in HBM and / or Wide-IO.

[0095] Specifically, for example, the semiconductor interface device (200) can accommodate 128 DQ wide channels of 30 GB / s or more within the area of ​​a microbump (μ-bump), achieve low latency with RL set to 6 (or 6 clocks), WL set to 4 (or 4 clocks), and tRTW of 2 (or 2 clocks), and can be robust against link errors and faults through lead data strobe lines and light data strobe lines implemented with independent wiring, and DERR lines and spare lines implemented with independent wiring, thereby improving bandwidth, latency performance, and reliability.

[0096] In addition, since the semiconductor interface device (200) is implemented with a structure of microbumps and silicon injectors, the board-level signal integrity design can be greatly simplified. Furthermore, by eliminating the effort of signal rewiring between the core and the PHY through FIFO interleave, the design burden of the package and board respectively is minimized.

[0097] In addition, by tracking PVT changes without the intervention of the controller (110) firmware through delay lines and logic gates included in the semiconductor interface device (200), the burden on system integration is reduced and the hardware-level is automatically calibrated.

[0098] FIG. 3 is a timing diagram of signals for performing read and write operations of a semiconductor system (100) according to an exemplary embodiment of the present disclosure. FIG. 3 is a timing diagram that exemplarily shows a scenario of a write operation immediately following a read operation according to standards such as JEDEC standards and HBM standards using signals.

[0099] Referring to FIGS. 1 and FIG. 3, clock signals (CK_c, CK_t) may be differential signals provided from the controller (110) to the semiconductor device (130) (e.g., DRAM implemented as DDR). In the column command bus (see 'Column Command' in FIG. 3), 'READ' indicates a read command and 'WRITE' indicates a write command. In the column address bus (see 'Column Address' in FIG. 3), 'BA' indicates a bank address and 'CA' indicates a column address. Write data strobe signals (WDQS_c, WDQS_t) may be differential signals provided from the controller (110) to the semiconductor device (130) during a write operation. Read data strobe signals (RDQS_c, RWDQS_t) may be differential signals provided from the semiconductor device (130) to the controller (110) during a read operation. In FIG. 3, 'Odd Byte DATA' and 'Even Byte DATA' are data signals, for example, data signals in an x8 interleave of DDR5 that output half 64-bit data and half 8-bit ECC signals. 'RL (Read Latency)', 'WL (Write Latency)', 'PL (Preamble Length)', and 'tRTW (Read-to-Write Delay)' are values ​​of programmable registers according to the DDR5 spec and can be initialized with the same setting values ​​in the registers of the controller (110), the semiconductor interface device (120), and the semiconductor device (130), respectively. 'PL' can be set before the read data strobe signals (RDQS_c, RWDQS_t). In an exemplary embodiment, the value of 'RL' may be greater than the value of 'WL'.For example, the value of 'RL' may be 6 (or 6 clocks) and the value of 'WL' may be 4 (or 4 clocks), and 'tRTW' may be at least 2 (or 2 clocks) as 'RL-WL+burst-connection allowance (specification defined value)'. However, the present disclosure is not limited to the examples described above. Here, 'x clocks' may represent the number of clock cycles of a clock signal (CK_c or CK_t), for example, 6 clocks may be 6 clock cycles. 'PAR' is a command / address parity line (or bus) for protecting a command signal.

[0100] In an exemplary embodiment, the data signal, i.e., the DQ signal, may be 128 bits (i.e., DQ[127:0]), and the number of microbumps for transmitting and receiving the 128-bit DQ signal may be 128. The column command / address may be 8 bits (i.e., C[7:0]) or 9 bits (i.e., C[8:0]), and the number of microbumps for transmitting the 8-bit column command / address may be 8, and the number of microbumps for transmitting the 9-bit column command / address may be 9. The low command / address can be 6 bits (i.e., R[5:0]) or 7 bits (i.e., R[6:0]), and the number of microbumps for transmitting a 6-bit low command / address can be 6, and the number of microbumps for transmitting a 7-bit low command / address can be 7. The Data Bus Inversion (DBI) signal for improving energy and signal integrity is set to 1 per 8-bit DQ signal, and the number of microbumps for the DBI signal can be 16. The Data Mask (DM) signal for protecting write operations is set to 1 per 8-bit DQ signal, and the number of microbumps for the DM signal can be 16. The PAR signal for detecting command / address errors is set to 1 per 32-bit DQ signal, and the number of microbumps for the PAR signal can be 4. The DERR signal of the data CRC error flag is set to one per 32-bit DQ signal, and the number of microbumps for the DERR signal can be four. The pairs of read and write data strobe signals are each set to one pair, i.e., four, per 32-bit DQ signal, and the number of microbumps for DQS can be a total of 16.The number of microbumps for a pair of clock signals may be 2, the number of microbumps for a clock enable signal (e.g., CKE) for controlling sleep and / or refresh may be 1, and the number of microbumps for an access error signal (e.g., AERR) may be 1. A redundant data signal (e.g., RD) may be 8 bits (i.e., RD[7:0]), and the number of microbumps for transmitting and receiving an 8-bit redundant data signal may be 8. The number of microbumps for a redundant row signal (e.g., RR) may be 1, and the number of microbumps for a redundant column signal (e.g., RC) may be 1. Therefore, in a low-capacity semiconductor system that supports 8-bit column command / address and 6-bit row command / address, the total number of microbumps may be 212, or in a high-capacity semiconductor system that supports 9-bit column command / address and 7-bit row command / address, the total number of microbumps may be 214.

[0101] At T0, the controller (110) can output a read command (READ) to the column command bus and output a bank address and a column address (BAx, CAa) to the column address bus. Afterwards, a delay (e.g., 6 edges of the clock signal) of 'RL' (e.g., 6) set to an initialized value occurs.

[0102] At T6, the semiconductor device (130) begins to return read data for the read command, bank address, and column address. For example, the semiconductor device (130) begins to toggle the read data strobe signals (RDQS_c, RWDQS_t), and the controller (110) may receive a data burst (see 'Da' for 'Odd Byte DATA' and 'Even Byte DATA' respectively in FIG. 3) in response to the edges of the read data strobe signals (RDQS_c, RWDQS_t). At this time, a preamble may be included in the preceding cycle of the first toggle of the read data strobe signals (RDQS_c, RWDQS_t) according to 'PL' set to an initialized value (e.g., 1).

[0103] Meanwhile, at T6, the controller (110) can output a write command (WRITE) to the column command bus and output a bank address and a column address (BAx, Cab) to the column address bus. At this time, 'tRTW' must satisfy internal specifications such as 'RL-WL'.

[0104] Subsequently, when a delay (e.g., 4 edges of the clock signal) of 'WL' (e.g., 4) set to an initialized value occurs at T10, the controller (110) begins to toggle the light data strobe signals (WDQS_c, WDQS_t) and can output a data burst (see 'Db' for each of 'Odd Byte DATA' and 'Even Byte DATA' in FIG. 3) in response to the edges of the light data strobe signals (WDQS_c, WDQS_t). At this time, when according to 'PL' (e.g., 1), actual data can be provided after the preamble.

[0105] Between the final data of the lead operation and the first (or leading) data of the write operation, there is a high impedance ('Hi-z') (e.g., the section from T9 to T10 before), and this means an inactive slot to prevent data transmission from colliding because the direction of data transmission changes during the lead operation and the write operation (i.e., bus turnaround).

[0106] In an exemplary embodiment, the controller (110) may be designed so that a write command (WRITE) is issued after obtaining 'tRTW' following the issuance of a read command (READ), and in this case, 'tRTW' may be automatically recalculated when 'RL' and 'WL' are changed. The circuit generating the write data strobe signals (WDQS_c, WDQS_t) and / or the read data strobe signals (RDQS_c, RWDQS_t) in the controller (110) may be designed so that the receiving and transmitting switching timing of the differential signals exactly matches, thereby preventing burst collisions.

[0107] In an exemplary embodiment, a semiconductor interface device (120) can be designed by modeling an ASIC such as an SoC by verifying the state machine (read pipeline 6 stage, write pipeline 4 stage) and I / O pad tri-state control of the DDR PHY RTL (Register-Transfer-Level) according to the timing diagram shown in FIG. 3. In the simulation, a verification pattern can be configured by applying the skew, preamble length, postamble length, and burst length of the write data strobe / read data strobe (WDQS / RDQS).

[0108] In an exemplary embodiment regarding PCB and signal integrity, since the light data strobe / lead data strobe (WDQS / RDQS) needs to be matched with the same length as the data, data alignment may fail if impedance and skew problems occur even in the preamble section.

[0109] As described above, in a WRITE (4 CK latency) scenario immediately following a READ (6 CK latency), round-trip delays and bus direction switching are possible on all lines and buses, such as differential clock, command / address, data, data strobe, and parity.

[0110] FIG. 4 is a timing diagram of signals provided from a semiconductor interface device (120) to a semiconductor device according to the write operation of the present disclosure. FIG. 4 shows, on the time axis, the process in which a 32-bit write burst is distributed to 4×8 DQ lines through a PHY internal serialization process, and the output-enable, DQS gate, and differential strobe toggle are sequentially engaged.

[0111] Referring to FIGS. 2 and FIGS. 4, the semiconductor interface device (200) can construct an entire PHY-TX pipeline in which 32-bit light data is transmitted to an internal bus, bit shuffle, SerDes, pads, and microbumps, and DQS and OE waveforms are generated and aligned to the same standard.

[0112] Referring to FIG. 4, a channel with a bandwidth of 128 bits can be divided into four slices of 32 bits each, and each slice may be equipped with two wires for read data strobe signal pairs and two wires for write data strobe signal pairs, and 16 data strobe wires may be provided according to the four slices and four data strobe wires per slice. The burst length can transmit 32 bits of data and be distributed in a pattern of 4 bytes and interleaved (i.e., Interleave = 4) across four slices. For example, the data in the first slice (e.g., 'A') (e.g., 'DATA0~31_A') may be '1→5→9→...→29', the data in the second slice (e.g., 'B') (e.g., 'DATA0~31_B') may be '2→6→10→...→30', the data in the third slice (e.g., 'C') (e.g., 'DATA0~31_C') may be '3→7→11→...→31', and the data in the fourth slice (e.g., 'D') (e.g., 'DATA0~31_D') may be '4→8→12→...→32'. That is, a structure can be implemented in which the first and fifth data are transmitted in DQ[7:0], the second and sixth data are transmitted in DQ[15:8], the third and seventh data are transmitted in DQ[23:16], and the fourth and eighth data are transmitted in DQ[31:24]. However, the present disclosure is not limited to the examples described above. 32-bit logic data can be loaded into FIFO registers one clock at a time in the order of slices A, B, C, and D, and the multiplexer (M11) can extract 8-bit logic data in a cycle of 4 clocks to serialize the 32-bit logic data into 8-bit logic data. According to this, even if the core-bus and PHY-bus widths and clocks are different, they can be connected without a clock-domain X-bar.

[0113] The data drive signals (DATA0~31_OE) are signals for driving the external DQ line, and the external DQ line can be driven during the period when the level is enabled or a specific logic level (e.g., logic high level). The period for a certain number of clock cycles (e.g., 2 clocks) from when the logic level of the data drive signals (DATA0~31_OE) changes from a logic low level to a logic high level may be a bus turnaround period. That is, the corresponding slice drives the bus and pad during the period when the data drive signals (DATA0~31_OE) are enabled (i.e., the burst period), and the period when the data drive signals (DATA0~31_OE) are disabled (0.5 clocks before and after the burst period (CK)) may be a high-impedance (Hi-Z) state.

[0114] The data strobe enable signal (DQS_ENB) is a signal for enabling the toggle of differential data strobe signals (e.g., WR_DQS_P, WR_DQS_N), and the toggle of the differential light data strobe signals (WR_DQS_P, WR_DQS_N) provided to the semiconductor device (130) can be started and enabled during the interval when the data strobe enable signal (DQS_ENB) is at a specific logic level (e.g., logic high level). The internal PHY adder preamble length may be included in the data strobe enable signal (DQS_ENB). Each edge of the differential light data strobe signals (WR_DQS_P, WR_DQS_N) may serve as a reference for a 2-bit sample of the DQ signal. The differential light data strobe signals (WR_DQS_P, WR_DQS_N) can correspond to the light data strobe signals (WDQS_c, WDQS_t) shown in FIG. 3.

[0115] In an exemplary embodiment, the data drive signals (DATA0~31_OE) may have a logic high level one clock after the data strobe enable signal (DQS_ENB) has a logic high level. According to this, there is an advantage of maintaining the preamble window (WPRE) one clock longer to ensure the postamble window (WPST).

[0116] In an exemplary embodiment, the data driving signals (DATA0~31_OE) may be changed from a logic high level to a logic low level, and after one clock, the data strobe enable signal (DQS_ENB) may be changed from a logic high level to a logic low level.

[0117] Due to the write preamble (e.g., 'WPRE') and write postamble (e.g., 'WPST'), the DQS driver of the semiconductor interface device (120) may be activated for only (N+2) clocks (CLK_IN), and the DQ driver of the semiconductor interface device (120) may be activated for only N clocks (CLK_IN). Here, N may be a natural number. Accordingly, in an exemplary embodiment, the interval during which the data strobe enable signal (DQS_ENB) is activated (e.g., the interval having a logic high level) may be longer than the interval during which the data driving signals (DATA0~31_OE) are activated (e.g., the interval having a logic high level). That is, the preamble interval before the first toggle may be secured for 1 clock (CLK_IN), and the postamble interval after the last toggle may be secured for 1 clock (CLK_IN).

[0118] In an exemplary embodiment, during a 1-clock preamble interval, the data strobe enable signal (DQS_ENB) may be at a logic high level, and the data drive signals (DATA0~31_OE) may be at a logic low level. The data strobe signal line is already driving a '0 level' preamble, and the DQ bus may still be in a Hi-Z state to prevent bus collisions.

[0119] In an exemplary embodiment, during the interval where actual data is output while N clocks are toggled, the data strobe enable signal (DQS_ENB) and the data driving signals (DATA0~31_OE) may both be at a logic high level. This allows the data strobe signal toggling and DQ transmission to be synchronized.

[0120] In an exemplary embodiment, during a 1-clock post-amble interval, the data strobe enable signal (DQS_ENB) may be at a logic high level, and the data drive signals (DATA0~31_OE) may be at a logic low level. After the last data strobe signal toggle, the DQ bus may immediately be in a Hi-Z state. The data strobe signal line drives a '0 level' post-amble, and the bus direction change may be completed.

[0121] In an exemplary embodiment, the delay value, burst, and fixed width value of the data strobe enable signal (DQS_ENB) and 2 clocks (CK) can be stored and set in a register.

[0122] The differential light data strobe signals (WR_DQS_P, WR_DQS_N) may correspond to a clock signal output from, for example, a PLL (230) with reference to FIG. 2 and may be toggled with a phase of 90 degrees (°) relative to the input clock signal (CLK_IN) according to the DDR specification. At the rising edge and falling edge of the differential light data strobe signals (WR_DQS_P, WR_DQS_N), respectively, the semiconductor device (130) may sample DQ 16 bits (e.g., A+B or C+D). Accordingly, a configuration delaying the clock CK by DQS 90 degrees can be implemented in a digital Vernier without a DLL (±10 ps tap) and can be reset in real time during PVT, i.e., process and temperature fluctuations. In response to the edges of the differential light data strobe signals (WR_DQS_P, WR_DQS_N), a first output data (DATA_OUT_QT) or a second output data (DATA_OUT) may be output. The first output data (DATA_OUT_QT) is data output via a 2-bit wide quick-toggle bus before serialization for controller pipeline debugging and may be referred to as quick-toggle output data, and the second output data (DATA_OUT) may be data corresponding to a 1-bit wide serial stream. The number annotations of the data shown in FIG. 4 may be the order in which the actual semiconductor interface device (120) is transmitted to the semiconductor device (130).

[0123] In terms of timing constraints, the DQ valid window can correspond to the 'tDS / tDH' before and after the edge of the data strobe. Meanwhile, the controller (110) satisfies the specifications of the preamble section (e.g., 'tWPRE / tWPST(=1CK)') relative to the postamble section, and the DQ output may be prohibited during each of the preamble and postamble sections.

[0124] FIG. 5 is a timing diagram of signals provided to a semiconductor device in a semiconductor interface device according to the read operation of the present disclosure. Descriptions in FIG. 5 that overlap with the descriptions given above with reference to FIG. 4 are omitted.

[0125] Referring to FIG. 5, the burst length can be distributed in a pattern of interleaving in 4 bytes / slices of 32 bits. The data driving signals (DATA0~31_OE) can maintain a specific logic level (e.g., logic low level).

[0126] The read enable signal (READ_ENB) is a signal for enabling the toggle of differential data strobe signals (e.g., RD_DQS_P, RD_DQS_N), and the toggle of the differential read data strobe signals (RD_DQS_P, RD_DQS_N) provided to the semiconductor interface device (120) can be enabled during the interval when the read enable signal (READ_ENB) is at a specific logic level (e.g., logic high level).

[0127] The differential read data strobe signals (RD_DQS_P, RD_DQS_N) may correspond to the read data strobe signals (RDQS_c, RWDQS_t) shown in FIG. 3. The differential read data strobe signals (RD_DQS_P, RD_DQS_N) are output from the semiconductor device (130), and in response to the edges of the differential read data strobe signals (RD_DQS_P, RD_DQS_N), a first output data (DATA_OUT_QT) or a second output data (DATA_OUT) may be output from the semiconductor device (130). The number annotation of the data shown in FIG. 5 may be the order in which it is transmitted from the actual semiconductor device (130) to the semiconductor interface device (120).

[0128] After the toggle of the differential read data strobe signals (RD_DQS_P, RD_DQS_N) is activated, the toggle of the strobe signal (STRB) can be activated. In response to the edges of the strobe signal (STRB), data of 4 slices (e.g., 'DATA0~31_A', 'DATA0~31_B', 'DATA0~31_C', 'DATA0~31_D') can be output to the controller (110) as shown in FIG. 5.

[0129] The semiconductor interface device (120) and semiconductor device (130) according to exemplary embodiments of the present disclosure have the following differences from general DDR4 and / or PHY.

[0130] In terms of input / output (I / O) topology, in typical DDR4 and / or PHY, a pair of differential data strobes (DQS_P, DQS_N) are shared in both read and write directions, and a pair is placed per 8 slice. On the other hand, the present disclosure has a bidirectional separated strobe structure, and four independent wires are assigned to each slice containing 32 DQs, for example, differential data strobe signals (WR_DQS_P, WR_DQS_N, RD_DQS_P, RD_DQS_N) can be arranged as four independent wires, for example, two wires through which light data strobe signals (WR_DQS_P, WR_DQS_N) are transmitted and two wires through which read data strobe signals (RD_DQS_P, RD_DQS_N) are transmitted for each 32 DQ slice, and when four slices are included in the semiconductor interface device (120), the wiring of the differential data strobe signals (WR_DQS_P, WR_DQS_N, RD_DQS_P, RD_DQS_N) can be made up of a total of 16 wires. According to this, when read and write traffic are pipelined simultaneously, the bus turnaround period (e.g., 'tRTW') is shortened (e.g., shortened to 2 clocks), cross-toggle collisions are eliminated, and read / write commands can be issued in parallel.

[0131] In terms of bus width mapping, in typical DDR4 and / or PHY, the difference between the core and the bus width is mostly the DQ width (e.g., 8-bit, 16-bit), whereas in the present disclosure, the 32-bit core bus corresponds to an 8-bit 4-slice and can be distributed across 4 CKs with a mini FIFO and interleaved-4 shuffle. According to this, direct connection between logic and PHY with different widths is easy, wiring is simplified, and power consumption is reduced.

[0132] In terms of DQS and DQ gating, in typical DDR4 and / or PHY, data drive signals (e.g., OE) are simple and rely on controller firmware for most of the preamble and postamble, but in the present disclosure, the data strobe enable signal (DQS_ENB) is enabled before the data drive signals (DATA0 to 31_OE) (e.g., logic high level) and disabled after the data drive signals (DATA0 to 31_OE), thereby automatically satisfying preamble / postamble specifications (e.g., WPRE / WPST specifications). According to this, there are effects such as reducing or eliminating firmware loading, eliminating preamble / postamble interval (e.g., tWPRE / tWPST) errors, and simplifying measurement and calibration.

[0133] In terms of delay alignment, in typical DDR4 and / or PHY, a fixed phase of the DLL or external PLL reference around the pad occurs, but in the present disclosure, the 90-degree (°) phase of the data strobe (DQS) is aligned with the clock signal (CK or CLK_IN) by an embedded variable delay line (Delay Line (±10 ps)). According to this, fine skew per slice is corrected, and length deviations of the board and package or process PVT variations can be automatically tracked, thereby improving yield.

[0134] From the perspective of package interface, while a 0.4 to 0.8 mm Ball Grid Array (BGA) is implemented in typical DDR4 and / or PHY and the number of pins is less than 200, the present disclosure may design a structure in which the microbumps (μ-bump) have a size (Ψ) of about 20-40 μm, 212 or 214 microbumps and pins are provided per channel, and the microbumps and silicon interposer are directly connected through TSVs of the silicon interposer. According to this, 128 DQ channels can be fan-out within 4.5 x 4.5 mm, bandwidth and area can be increased, and electrical losses can be reduced.

[0135] In terms of redundancy and error lines, while in typical DDR4 and / or PHY only ECC parity and parity are transmitted externally, in the present disclosure, in addition to DBI (Data Bus Inversion), DM (Data Mask), and PAR, four DERR (Data CRC Error: used when a semiconductor device (e.g., DRAM) returns an error to the controller after the last clock) lines and RD[7:0], RR, and RC spares may be provided. Accordingly, yield and reliability can be improved by reporting runtime link errors and mapping out manufacturing defects.

[0136] In terms of pipeline depth, in typical DDR4 and / or PHY, RL and CL are equal and WL is greater than RL, whereas in the present disclosure, RL can be set to be greater than WL by example (e.g., RL is 6 clocks, WL is 4 clocks, and RL-WL is 2 clocks). According to this, a deep-pipeline and low-latency structure can be secured simultaneously, and read-after-write latency can be minimized at the same frequency.

[0137] FIG. 6 is a drawing for explaining the arrangement of a semiconductor system (600) according to an exemplary embodiment of the present disclosure, FIG. 7 is a drawing for explaining the arrangement of two core boards (621, 622) according to an exemplary embodiment of the present disclosure, FIG. 8 is a drawing for explaining the arrangement of a control board (630) according to an exemplary embodiment of the present disclosure, and FIG. 9 is a drawing for explaining the arrangement of two DPS (Device Power Supply) boards (641, 642) according to an exemplary embodiment of the present disclosure.

[0138] Referring to FIGS. 6 through 9, in an exemplary embodiment, a semiconductor system (600) may include a silicon interposer, a plurality of microbumps disposed on the silicon interposer, a die connected to the silicon interposer through the plurality of microbumps, and a DUT board including a plurality of TSVs (Through Silicon Via) connecting the plurality of microbumps and the substrate through the silicon interposer, a plurality of core boards disposed below the DUT board and connected to the DUT board, a control board connected to the DUT board below the plurality of core boards, a plurality of DPS boards including a plurality of DPS (Device Power Supply) disposed below the control board, and a Switching Mode Power Supply (SMPS) connected to the plurality of DPS boards below the plurality of DPS boards.

[0139] Referring to FIG. 6, when testing the semiconductor system (600), the width of the test site may be limited to a specific value (e.g., 49 mm). The semiconductor system (600) may be implemented as an ultra-compact and highly integrated HBM memory tester structure that simultaneously secures 6.4 GHz high-speed signal quality and high-current power stability by directly connecting at least one HBM and a SerDes ASIC to an ultra-thin glass substrate and integrating the directly connected module with a modular board stack (or modular board) with a width of 49 mm. At least one HBM may be included in DUT boards (611, 612), and the modular board stack may include two core boards (621, 622), one control board (630), and two DPS boards (641, 642). Additionally, the semiconductor system (600) may further include a Switching Mode Power Supply (SMPS) (640) positioned and connected to the lower part of the DPS boards (641, 642) of the modular board stack. Core boards (621, 622) are positioned to the lower part of the DUT boards (611, 612), and the core boards (621, 622) and the DUT boards (611, 612) can be connected via wiring. A control board (630) may be positioned to the lower part of the core boards (621, 622), and DPS boards (641, 642) may be positioned on the side of the test site. The SMPS (640) is positioned at the bottom center and can be directly connected to the DPS boards (641, 642), thereby having the effect of shortening the power and noise loops, and ensuring heat dissipation while keeping the high-current supply path short.

[0140] Referring to FIG. 7, the size of each core board (621, 622) may be 33 x 21 mm. That is, the width of each core board (621, 622) may be 33 mm, and the length of each core board (621, 622) may be 21 mm. However, the present disclosure is not limited to the examples described above. Each core board (621, 622) may be arranged in a repeating pattern (PTN) of a total of 16 cell array structures of 4 x 4 tiles. According to this, there is an advantage of supporting testing for multiple channels simultaneously.

[0141] Referring to FIG. 8, the size of the control board (630) may be 49 x 33 mm. The width of the control board (630) may be 33 mm, and the length of the control board (630) may be 49 mm. However, the present disclosure is not limited to the examples described above.

[0142] Referring to FIG. 9, the size of each of the DPS boards (641, 642) may be 29 x 32 mm. The width of each of the DPS boards (641, 642) may be 29 mm, and the length of each of the DPS boards (641, 642) may be 32 mm. However, the present disclosure is not limited to the examples described above.

[0143] FIG. 10 is a drawing for explaining the arrangement of a plurality of DUT boards according to an exemplary embodiment of the present disclosure, and FIG. 11 is a drawing for explaining the arrangement of a plurality of core boards according to an exemplary embodiment of the present disclosure.

[0144] Referring to FIG. 10, the size of the DUT board may be 60 (width) x 50 (length) mm, for example, corresponding to HBM3 and / or HBM3E, and each DUT board may include multiple HBMs and multiple sockets. On each DUT board, 1,024 I / O lines and 1,024 DR lines may be arranged per socket, and 16 power DPS with 2A characteristics and 24 power DPS with 40A characteristics may be arranged, thereby enabling high-current testing. Referring to FIG. 11, the size of each core board may be 66 (width) x 49 (length) mm, for example, corresponding to HBM3 and / or HBM3E.

[0145] FIGS. 12 and FIGS. 13 are drawings for explaining the upper and lower parts of a semiconductor system according to an exemplary embodiment of the present disclosure. FIG. 12 is a front view (or top view) and a side view for explaining the upper surface of the semiconductor system, and FIG. 13 is a bottom view and a block diagram of a test SerDes ASIC and HBM for explaining the lower surface of the semiconductor system.

[0146] Referring to FIG. 12, in a semiconductor system, a socket may be disposed on an ultra-thin glass substrate, and an HBM may be disposed on the upper surface of the socket. The thickness of the ultra-thin glass substrate may be approximately 178 μm, but is not limited thereto. A plurality of bumps may be disposed on the lower surface of the ultra-thin glass substrate, and the distance between adjacent bumps may be approximately 500 μm, but is not limited thereto. In the HBM, one strobe may be assigned for every 32. A plurality of microbumps may be disposed between the socket and the HBM, and the distance between adjacent microbumps may be approximately 78 μm, but is not limited thereto. According to this, the signal path between the socket, the HBM, and the ASIC through the ultra-thin glass substrate is shortened to approximately 500 μm or less, and signal attenuation, jitter, and crosstalk are minimized at high frequencies (6.4 GHz).

[0147] Referring to FIG. 13, in a semiconductor system, a flip-chip of a test SerDes ASIC can be directly mounted on the underside of an ultra-thin glass substrate. The SerDes ASIC can rapidly convert a 1,600 MHz input / output DQ into a 6,400 MHz data signal via a 4:1 multilink. The SerDes ASIC may include a read data strobe signal generator, a light data strobe signal generator, and a strobe generator, and can be synchronized on a total of 16 lines, with one set for every 32 DQ lines.

[0148] As described above, by directly connecting the HBM package and the tester SerDes ASIC through an interposer and microbumps, the lead frame and PCB wiring are eliminated, thereby having the effect of reducing parasitic inductance and parasitic capacitance within the system.

[0149] FIGS. 14 and FIGS. 15 are side views of a semiconductor system according to an exemplary embodiment of the present disclosure.

[0150] Referring to FIGS. 14 and 15, the semiconductor system includes an HBM, which may include 3D stacked DRAMs, for example, 16 DDR5 dies. All signal lines and microbumps required by one channel of the 3D stacked DRAM in the semiconductor system may be exemplarily illustrated in FIGS. 14 and 15.

[0151] In an exemplary embodiment, the semiconductor system may include a substrate; a silicon interposer disposed on the substrate, a plurality of microbumps disposed on the silicon interposer, a die connected to the silicon interposer through the plurality of microbumps, and a plurality of Through Silicon Via (TSVs) connecting the plurality of microbumps and the substrate through the silicon interposer; and a SerDes ASIC disposed on the underside of the substrate and connected to the DUT.

[0152] In one embodiment, the silicon interposer includes a first region and a second region, and the plurality of TSVs can penetrate the first region of the silicon interposer.

[0153] In an exemplary embodiment, the number of pins and / or microbumps may be a total of 212 or 214 per channel. For example, the number of microbumps for 128-bit DQ is 128, the number of microbumps for column command / address is 8 (for 8-bit column command / address) or 9 (for 9-bit column command / address) depending on chip density, the number of microbumps for row command / address is 6 (for 6-bit row command / address) or 7 (for 7-bit row command / address configured when bank groups are included), the number of microbumps for DBI is 16, the number of microbumps for DM is 16, the number of microbumps for PAR is 4, the number of microbumps for DERR is 4, the total number of microbumps for DQS is 16, the number of microbumps for CK is 2, the number of microbumps for CKE is 1, and the number of microbumps for AERR is There may be 1 microbump, 8 microbumps for RD, 1 microbump for RR, and 1 microbump for RC.

[0154] In an exemplary embodiment, when the semiconductor system includes 8 channels of 3D stacked DRAMs, the number of pins and / or microbumps may be 1,696 or 1,712. In this case, the DBI line, DM line, and DERR line may be matched to the same length as the DQ bus. The semiconductor system has a structure of 128-bit bandwidth and 1 DQS pair per 32-bit DQ, includes a high-density 2.5D interposer for smooth fan-out in the package and board, and supports DBI, thereby reducing data toggle switching power by up to 50% and improving signal integrity. Additionally, from the perspective of manufacturing yield, the semiconductor system includes RD spares, RR spares, and RC spares, which has the effect of correcting defects in the semiconductor system through layout remapping at the packaging stage to compensate for some process defects.

[0155] In an exemplary embodiment, the PAD-cell can be integrated with DQ 32, DBI 4, DM 4, DQS 4, and other controls and fan-out to an interposer. Skew between DQ and DQS can be eliminated by making the matching of package, board, and microbump lengths less than 5 ps.

[0156] Although the present disclosure has been described with reference to the embodiments illustrated in the drawings, this is merely illustrative, and those skilled in the art will understand that various modifications and equivalent alternative embodiments are possible therefrom. Accordingly, the true technical scope of protection of the present disclosure should be determined by the technical spirit of the appended claims. Explanation of the symbols

[0157] 100: Semiconductor System 110: Controller 120: Semiconductor interface device 130: Semiconductor device

Claims

Claim 1 A plurality of first delay circuits that delay a plurality of data signals and output a plurality of delay signals; a clock delay circuit that delays an external input clock signal and outputs a delayed input clock signal; a plurality of flip-flop groups that receive the plurality of delay signals and output slice-specific first signals and second signals in response to the delayed input clock signal; a phase-locked loop (PLL) that changes the frequency of the delayed input clock signal based on the delayed input clock signal and outputs a clock signal having the changed frequency; a first FIFO (First-In First-Out) register that outputs a first partial signal corresponding to a portion of the slice-specific first signals and a second partial signal corresponding to a portion of the slice-specific second signals in response to the delayed input clock signal and the clock signal; third flip-flops that output the first partial signals and the second partial signals respectively input in response to the clock signal; and the first partial signals or the second partial signals output from the third flip-flops using the clock signal as a selection signal A semiconductor interface device comprising: a first multiplexer for selection; and a second delay circuit for delaying a signal output from the first multiplexer and outputting a plurality of DQ signals. Claim 2 A semiconductor interface device according to claim 1, wherein the plurality of data signals include first data signals corresponding to a first slice, second data signals corresponding to a second slice, third data signals corresponding to a third slice, and fourth data signals corresponding to a fourth slice, and the plurality of first delay circuits include four delay circuits that receive data signals for each slice. Claim 3 A semiconductor interface device according to claim 2, wherein the plurality of flip-flop groups include first flip-flops that receive delay signals for data signals for each slice and second flip-flops connected to the outputs of the first flip-flops. Claim 4 A semiconductor interface device according to claim 3, wherein the first data signals, the second data signals, the third data signals, and the fourth data signals are each transmitted through 32 parallel data lines, the number of the first flip-flops and the number of the second flip-flops are each 8 per slice, the first signals per slice and the second signals per slice are each output through 8 parallel lines, and the first partial signals and the second partial signals are each output through 8 parallel lines. Claim 5 A semiconductor interface device according to claim 1, wherein the plurality of flip-flop groups comprises: a first flip-flop group receiving the plurality of delay signals; and a second flip-flop group receiving the output signals of the first flip-flop group. Claim 6 A first delay circuit that delays a read data strobe signal provided from a semiconductor device and outputs a delayed strobe signal; a second delay circuit that delays a plurality of DQ signals provided from the semiconductor device and outputs a plurality of delay signals; first flip-flops that receive the plurality of delay signals and output a plurality of first signals and a plurality of second signals in response to the delayed strobe signal; a clock delay circuit that delays an external input clock signal and outputs a delayed input clock signal; a phase-locked loop (PLL) that changes the frequency of the delayed input clock signal based on the delayed input clock signal and outputs a clock signal having the changed frequency; a first FIFO register that outputs the plurality of first signals and the plurality of second signals of the first flip-flops in response to the clock signal and the delayed data strobe signal; a second FIFO register that outputs a plurality of signals of the first FIFO register in response to the delayed input clock signal and the clock signal; and receiving the plurality of signals and in response to the delayed input clock signal A semiconductor interface device comprising: a plurality of second flip-flops that output the plurality of signals; and a plurality of first multiplexers that select the signals output from the plurality of second flip-flops as the delayed input clock signal as a selection signal. Claim 7 A semiconductor interface device according to claim 6, wherein the number of first flip-flops is two, the delayed strobe signal is input to the club input of one of the first flip-flops, and the inverted signal of the delayed strobe signal is input to the club input of the other of the first flip-flops. Claim 8 A semiconductor interface device according to claim 6, wherein the clock delay circuit corrects the phase of the input clock signal by 90 degrees. Claim 9 A semiconductor interface device according to claim 6, wherein the plurality of signals output from the second FIFO register include first to eight signals output through eight parallel lines, the number of the plurality of second flip-flops is eight, and the eight second flip-flops each receive one of the first to eight signals. Claim 10 A semiconductor interface device according to claim 9, wherein the number of the plurality of first multiplexers is 4, and each first multiplexer receives the output of 2 second flip-flops.

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