Memory device and operating method of the memory device

Abstract

The present invention includes a memory device and a method of operation thereof, comprising the steps of: applying a first erase voltage to a source line during an erase operation of a memory block connected between a source line and bit lines; lowering the voltage of the source line to which the first erase voltage is applied to a second erase voltage; and raising the voltage of the source line to which the second erase voltage is applied to a third erase voltage.

Description

Technology Field

[0001] The present invention relates to a memory device and a method of operating the same, and more specifically, to a memory device configured to perform an erase operation and a method of operating the same. Background Technology

[0002] A memory device may include a memory cell array in which data is stored, a peripheral circuit configured to perform program, read, or erase operations, and a control circuit that controls the peripheral circuit.

[0003] A memory cell array may include a plurality of memory blocks, and each of the plurality of memory blocks may include a plurality of memory cells. A memory device having a three-dimensional structure may include memory cells stacked on a substrate. For example, a memory device having a three-dimensional structure may include plugs perpendicular to the substrate. The plugs may include selection transistors connected between bit lines and source lines, and memory cells connected between the selection transistors. The memory cells and selection transistors between the bit lines and source lines may form strings.

[0004] Memory cells can be classified into a programmed state or an erased state depending on the threshold voltage. For example, memory cells having a threshold voltage higher than the reference voltage can be classified as a programmed state, and memory cells having a threshold voltage lower than the reference voltage can be classified as an erased state.

[0005] The programming operation is the process of raising the threshold voltage of memory cells in the erased state to the threshold voltage corresponding to the programmed state. Since memory cells possess different electrical characteristics, the threshold voltage levels may differ even if the same programming voltage is applied to them during the programming operation. Consequently, memory cells may exhibit a threshold voltage distribution. The distribution of threshold voltages among memory cells implies that the threshold voltage varies from cell to cell. This is because the threshold voltages of memory cells rise or fall at different rates. In other words, when comparing two memory cells, if the rate at which the threshold voltage of a single cell changes is used as the criterion, the cell whose threshold voltage changes more slowly than the other is called a "slow cell," and the cell whose threshold voltage changes more quickly is called a "fast cell." Therefore, among programmed memory cells, slow cells have a relatively low threshold voltage within the distribution, while fast cells have a relatively high threshold voltage. Conversely, among the erased memory cells, slow cells have a relatively high threshold voltage in the threshold voltage distribution, while fast cells have a relatively low threshold voltage. Therefore, during the programming operation of an erased memory block, the greater the difference in threshold voltage between the slow cells and fast cells included in the erased memory block, the longer the programming operation time of the memory block may increase. The problem to be solved

[0007] An embodiment of the present invention provides a memory device capable of narrowing the threshold voltage distribution width of memory cells during an erase operation of memory cells, and a method of operating the same. means of solving the problem

[0008] A method of operation of a memory device according to an embodiment of the present invention comprises: a step of applying a first erase voltage to a source line during an erase operation of a memory block connected between a source line and bit lines; a step of lowering the voltage of the source line to which the first erase voltage is applied to a second erase voltage; and a step of raising the voltage of the source line to which the second erase voltage is applied to a third erase voltage.

[0009] A method of operating a memory device according to an embodiment of the present invention comprises: a first step of lowering the threshold voltage of slow cells and fast cells included in a selected memory block; a second step of reducing the difference in threshold voltage between the slow cells and the fast cells after the first step; and a third step of lowering the threshold voltage of the slow cells and the fast cells after the second step.

[0010] A memory device according to an embodiment of the present invention comprises: a section management unit configured to sequentially output time information for an erasure voltage rise section, an erasure section including a plurality of sub-sections, and a discharge section in response to an erasure command; a voltage level management unit configured to change and output an operation code in response to the time information; and a voltage generator configured to sequentially output erasure voltages having different levels in response to the operation code, wherein, when an erasure operation occurs, the voltage generator is configured to sequentially output a first erasure voltage, a second erasure voltage lower than the first erasure voltage, and a third erasure voltage higher than the second erasure voltage in response to the operation code. Effects of the invention

[0012] This technology can prevent the threshold voltage of memory cells from becoming excessively low during an erase operation, and can shorten the time of subsequent program execution by narrowing the threshold voltage distribution width of memory cells in the erased state. Brief explanation of the drawing

[0013] Figure 1 is a diagram illustrating a memory device. Figure 2 is a circuit diagram for explaining a memory block. Figure 3 is a diagram illustrating the threshold voltage distribution of memory cells. FIG. 4 is a diagram illustrating a control circuit according to an embodiment of the present invention. FIG. 5 is a diagram illustrating an erasure operation according to a first embodiment of the present invention. FIGS. 6a and FIGS. 6b are drawings for explaining the threshold voltage of memory cells according to a first embodiment of the present invention. FIG. 7 is a diagram illustrating an erasure operation according to a second embodiment of the present invention. FIG. 8 is a diagram illustrating an erasure operation according to a third embodiment of the present invention. FIG. 9 is a drawing for explaining an erasure operation according to a fourth embodiment of the present invention. FIG. 10 is a drawing for explaining an erasure operation according to a fifth embodiment of the present invention. FIG. 11 is a drawing for explaining an erasure operation according to a sixth embodiment of the present invention. FIG. 12 is a drawing for explaining a memory card system to which the memory device of the present invention is applied. FIG. 13 is a drawing for explaining a Solid State Drive (SSD) system to which the memory device of the present invention is applied. Specific details for implementing the invention

[0014] The specific structural or functional descriptions disclosed below are illustrative of embodiments according to the concept of the present invention. Embodiments according to the concept of the present invention are not to be interpreted as being limited to the embodiments described below, but can be modified in various ways and replaced with other equivalent embodiments.

[0015] In the following description, terms such as "first," "second," etc., may be used to describe various components, but said components are not limited by said terms. These terms are used for the purpose of distinguishing one component from another.

[0017] Figure 1 is a diagram illustrating a memory device.

[0018] Referring to FIG. 1, a memory device (100) may include a memory cell array (110), a peripheral circuit (170), and a control circuit (180).

[0019] The memory cell array (110) may include first to j-th memory blocks (BLK1 to BLKj). Each of the first to j-th memory blocks (BLK1 to BLKj) may include memory cells capable of storing data. Drain select lines (DSL), word lines (WL), source select lines (SSL), and source lines (SL) may be connected to each of the first to j-th memory blocks (BLK1 to BLKj). Bit lines (BL) may be connected in common to the first to j-th memory blocks (BLK1 to BLKj). The first to j-th memory blocks (BLK1 to BLKj) may be formed in a three-dimensional structure. Memory blocks having a three-dimensional structure may include memory cells stacked on a substrate.

[0020] Memory cells can store 1 bit or 2 or more bits of data depending on the programming method. For example, the method of storing 1 bit of data in a single memory cell is called the single-level cell method, and the method of storing 2 bits of data is called the multi-level cell method. The method of storing 3 bits of data in a single memory cell is called the triple-level cell method, and the method of storing 4 bits of data is called the quad-level cell method. In addition, 5 bits or more of data may be stored in a single memory cell.

[0021] The peripheral circuit (170) may be configured to perform a program operation for storing data in the memory cell array (110), a read operation for outputting data stored in the memory cell array (110), and an erase operation for erasing data stored in the memory cell array (110). For example, the peripheral circuit (170) may include a voltage generator (120), a row decoder (130), a page buffer group (140), a column decoder (150), and an input / output circuit (160).

[0022] The voltage generator (120) can generate various operating voltages (Vop) used for program operation, read operation, or erase operation in response to the operation code (OPCD). For example, the voltage generator (120) can be configured to generate program voltages, turn-on voltages, turn-off voltages, precharge voltage, negative voltages, verify voltages, read voltages, pass voltages, or erase voltages in response to the operation code (OPCD). The operating voltages (Vop) generated by the voltage generator (120) can be applied to the drain select lines (DSL), word lines (WL), source select lines (SSL), and source line (SL) of the selected memory block through the row decoder (130).

[0023] Program voltages are voltages applied to selected word lines (WL) during a program operation and can be used to raise the threshold voltage of memory cells connected to the selected word line. Turn-on voltages can be applied to drain select lines (DSL) or source select lines (SSL) and can be used to turn on drain select transistors or source select transistors. Turn-off voltages can be applied to drain select lines (DSL) or source select lines (SSL) and can be used to turn off drain select transistors or source select transistors. For example, the turn-off voltage can be set to 0V. Precharge voltages can be applied to source lines and can be used to raise the channel voltage of unselected strings during soft program or normal program operations. Negative voltages can be set to voltages lower than 0V. Verification voltages can be used during a verification operation to determine whether the threshold voltage of selected memory cells has been raised to or lowered to a target level. Verification voltages can be set to various levels depending on the target level and can be applied to selected word lines. Read voltages can be applied to selected word lines during a read operation of selected memory cells. Pass voltages are voltages applied to unselected word lines during a program or read operation and can be used to turn on memory cells connected to unselected word lines. Erase voltages can be used during an erase operation to erase memory cells included in a selected memory block and can be applied to source lines (SL).

[0024] The voltage generator (120) can control the levels of voltages applied to drain select lines (DSL), word lines (WL), source select lines (SSL) and source line (SL) in response to an operation code (OPCD), and the time at which the voltages are output. The voltage generator (120) can discharge the lines to which the operation voltages (Vop) are applied and can control the time at which they are discharged. The voltage generator (120) can also float the selected lines.

[0025] The row decoder (130) may be configured to transmit operating voltages (Vop) to drain select lines (DSL), word lines (WL), source select lines (SSL), and source line (SL) connected to a memory block selected according to a row address (RADD). For example, the row decoder (130) may be connected to a voltage generator (120) via global lines and to first to j memory blocks (BLK1 to BLKj) via drain select lines (DSL), word lines (WL), source select lines (SSL), and source line (SL).

[0026] The page buffer group (140) may include page buffers (not shown) connected to the first to j memory blocks (BLK1 to BLKj) via bit lines (BL). During a program operation, program data transmitted from the input / output circuit (160) may be stored in the page buffer group (140). The page buffer group (140) may apply a program allow voltage or a program prohibit voltage to the bit lines (BL) according to the program data in response to page buffer control signals (PBSIG). During a verification operation, the page buffer group (140) may sense the current or voltage of the bit lines (BL) which varies according to the threshold voltages of the selected memory cells, and store the sensed data.

[0027] A column decoder (150) may be configured to transmit data between a page buffer group (140) and an input / output circuit (160) in response to a column address (CADD). For example, the column decoder (150) may be connected to the page buffer group (140) via column lines (CL) and may transmit enable signals via column lines (CL). Page buffers (not shown) included in the page buffer group (140) may receive or output data via data lines (DL) in response to the enable signals.

[0028] The input / output circuit (160) may be configured to receive or output commands (CMD), addresses (ADD), or data through input / output lines (I / O). For example, the input / output circuit (160) may transmit commands (CMD) and addresses (ADD) received from an external controller through input / output lines (I / O) to the control circuit (180), and transmit data received from an external controller through input / output lines (I / O) to the page buffer group (140). Alternatively, the input / output circuit (160) may output data received from the page buffer group (140) to an external controller through input / output lines (I / O).

[0029] The control circuit (180) can output an operation code (OPCD), a row address (RADD), page buffer control signals (PBSIG), and a column address (CADD) in response to a command (CMD) and an address (ADD). For example, if the command (CMD) input to the control circuit (180) is a command corresponding to a program operation, the control circuit (180) can control the peripheral circuit (170) so that a program operation of the memory block selected by the address (ADD) is performed. If the command (CMD) input to the control circuit (180) is a command corresponding to a read operation, the control circuit (180) can control the peripheral circuit (170) to perform a read operation of the memory block selected by the address and output the read data. If the command (CMD) input to the control circuit (180) is a command corresponding to an erase operation, the control circuit (180) can control the peripheral circuit (170) so that the erase operation of the selected memory block is performed.

[0030] In the erasure operation according to the present embodiment, the control circuit (180) can divide the interval in which the erasure voltage is applied to the source line (SL) or bit lines (BL) into a plurality of intervals, and control the peripheral circuit (170) so that different erasure voltages are applied to the source line (SL) or bit lines (BL) in each of the plurality of intervals.

[0032] Figure 2 is a circuit diagram for explaining a memory block.

[0033] Referring to FIG. 2, the memory block (BLK) may be any one of the first to j-th memory blocks (BLK1 to BLKj) illustrated in FIG. 1. The memory block (BLK) may include strings (ST) connected between the first to n-th bit lines (BL1 to BLn) and the source line (SL). For example, the strings (ST) may be connected in common to the source line (SL) and connected to the first to n-th bit lines (BL1 to BLn) respectively. The structure of the string (ST) connected between the n-th bit line (BLn) and the source line (SL) is described as an example as follows.

[0034] A string (ST) may include a source select transistor (SST), memory cells (MC1–MCm), and a drain select transistor (DST) connected in series between a source line (SL) and the n-th bit line (BLn). Since the string (ST) illustrated in FIG. 2 is an example to explain the configuration of a memory block (BLK), the number of source select transistors (SST), memory cells (MC1–MCm), and drain select transistors (DST) included in the string (ST) may vary depending on the memory device. Additionally, dummy cells may be further included in some of the spaces between the source select transistor (SST), memory cells (MC1–MCm), and drain select transistor (DST). Dummy cells are cells used to prevent electrical degradation of the string (ST) or to improve electrical characteristics, and can store dummy data instead of normal data. Normal data may be stored in the memory cells (MC1–MCm).

[0035] A source select transistor (SST) can be configured to electrically connect or disconnect a source line (SL) and a memory cell (MC1). The gates of source select transistors (SST) included in different strings (ST) can be connected to a source select line (SSL). Memory cells (MC1–MCm) can be configured to store normal data. The gates of memory cells (MC1–MCm) included in different strings (ST) can be connected to word lines (WL1–WLm), respectively. A group of memory cells connected to the same word line can form a page (PG), and program or read operations can be performed on a page basis. A drain select transistor (DST) can be configured to electrically connect or disconnect bit lines (BL1–BLn) and 20th memory cells (MC20). The gates of drain select transistors (DST) included in different strings (ST) can be connected to a drain select line (DSL).

[0036] During an erase operation, a turn-on voltage (Von) may be applied to the source select line (SSL) and drain select line (DSL) to turn on the source select transistors (SST) and drain select transistors (DST). A pass voltage (Vpass) may be applied to the word lines (WL1–WLm) to turn on the memory cells (MC1–MCm). An erase voltage (Vers) may be applied to the source line (SL). During an erase operation, the bit lines (BL1–BLn) may be floating (FLT), but an erase voltage (Vers) may also be applied to the bit lines (BL1–BLn). The erase voltage (Vers) is higher than the pass voltage (Vpass) and the turn-on voltage (Von). The turn-on voltage (Von) is higher than 0V. The pass voltage (Vpass) may be equal to or higher than the turn-on voltage (Von) and lower than the erase voltage.

[0038] Figure 3 is a diagram illustrating the threshold voltage distribution of memory cells.

[0039] Referring to FIG. 3, memory cells can be classified into various states according to a threshold voltage, and the threshold voltage can have different levels depending on the data stored in the memory cells. For example, memory cells can store 1 bit or 2 bits or more of data depending on the programming method. A method in which 1 bit of data is stored in a single memory cell is called a single-level cell method, and a method in which 2 bits of data are stored is called a multi-level cell method. A method in which 3 bits of data are stored in a single memory cell is called a triple-level cell method, and a method in which 4 bits of data are stored is called a quad-level cell method. In addition, 5 bits or more of data may be stored in a single memory cell.

[0040] Figure 3 illustrates the threshold voltage distribution of memory cells in a quad-level cell method as an example, but the present embodiment is not limited to a quad-level cell method.

[0041] In a quad-level cell method, memory cells may be in an erase state (ER) or one of the first to fifteen program states (P1 to P15) depending on the threshold voltage. A program operation refers to an operation of raising the threshold voltage of memory cells in the erase state (ER) to a threshold voltage corresponding to any one of the first to fifteen program states (P1 to P15). An erase operation refers to an operation of lowering the threshold voltage of memory cells corresponding to the first to fifteen program states (P1 to P15) to a threshold voltage corresponding to the erase state (ER). Therefore, the wider the threshold voltage distribution width (WD) of memory cells in the erase state (ER), the longer the time required to raise the threshold voltage of the memory cells during a program operation may be.

[0042] In the following embodiments, an erasure operation is initiated to narrow the threshold voltage distribution width (WD) corresponding to the erasure state (ER).

[0044] FIG. 4 is a diagram illustrating a control circuit according to an embodiment of the present invention.

[0045] Referring to FIG. 4, the control circuit (180) may include a period manager (41) and a voltage level manager (42).

[0046] The section management unit (41) may be configured to sequentially output time information (TIF) in response to a command (CMD). For example, the section management unit (41) may include an algorithm corresponding to a program, read, or erase operation, respectively, and may output time information (TIF) for the sections of each operation according to the selected algorithm in response to the command (CMD). To explain the erase operation as an example, the erase operation may be performed in response to an erase command. The erase operation may be divided into an erase voltage rise section, an erase section, and a discharge section. In the erase voltage rise section, the level of the erase voltage may be raised to a target level, in the erase section, memory cells may be erased, and in the discharge section, the line to which the erase voltage is applied may be discharged. The erase section may be divided into a plurality of sub-sections. In the following description, an erase operation is initiated in which three sub-sections are included in the erase section, but the number of sub-sections may be changed depending on the memory device. Time information (TIF) may include information on the start time of each of the erase voltage rise interval, erase interval, multiple sub-intervals, or discharge interval.

[0047] The voltage level management unit (42) may be configured to change and output an operation code (OPCD) in response to time information (TIF). The voltage level management unit (42) may change the operation code (OPCD) so that a voltage corresponding to a corresponding section is generated and output according to the information on the start time of each section included in the time information (TIF). That is, the operation code (OPCD) may include a code corresponding to a section and a code corresponding to a voltage level. For example, the voltage level management unit (42) may include a code corresponding to a sub-section and a code corresponding to the level of the erase voltage to be used in the sub-section in the operation code (OPCD). Accordingly, the voltage level management unit (42) may output an operation code (OPCD) containing the changed code whenever a section or voltage level is changed.

[0048] The operation code (OPCD) output from the voltage level management unit (42) can be transmitted to the voltage generator (120). The voltage generator (120) can be configured to output a voltage at a time corresponding to each interval in response to the operation code (OPCD). For example, during an erase operation, the voltage generator (120) can selectively output operation voltages (Vop), including an erase voltage, a pass voltage, and a turn-on voltage, at a time corresponding to each interval in response to the operation code (OPCD). Since the voltage generator (120) is connected to the row decoder (130 in FIG. 1) through global lines, the operation voltages (Vop) output from the voltage generator (120) can be transmitted to the row decoder (130 in FIG. 1) through global lines.

[0050] FIG. 5 is a diagram illustrating an erasure operation according to a first embodiment of the present invention.

[0051] Referring to FIG. 5, the erase operation may include an erase voltage rise section (VU), an erase section (ERS), and a discharge section (DS). The erase voltage rise section (VU), the erase section (ERS), and the discharge section (DS) may be sequential in time. For example, when the erase voltage rise section (VU) ends (T1), the erase section (ERS) begins, and when the erase section (ERS) ends, the discharge section (DS) begins.

[0052] In the erase voltage rise interval (VU), an erase voltage may be applied to the source line. The source line may be the source line (SL) shown in FIG. 2. It is assumed that the potential of the source line is 0V prior to the erase voltage rise interval (VU). In this case, when the erase voltage rise interval (VU) begins, an erase voltage may be applied to the source line, causing the potential of the source line to rise. The erase voltage may also be applied to the bit lines. While the erase voltage is applied to the source line, a pass voltage may be applied to the word lines of the selected memory block. While the potential of the source line is raised by the erase voltage applied to it, the potential of the word lines may also be raised by the pass voltage. As the potential of the source line rises, the threshold voltage (Vth) of the memory cells may be lowered. Among the memory cells, the threshold voltage of the slow cells (MCs) may be lowered more slowly than the threshold voltage of the fast cells (MCf).

[0053] When the first time (T1) is reached in which the erase voltage applied to the source line rises to the first erase voltage (1Vers), the erase period (ERS) may begin. The first erase voltage (1Vers) may be set to a level higher than the reference voltage (Vref). The reference voltage (Vref) may be set to a positive voltage level at which memory cells can be erased. Since the first erase voltage (1Vers) is higher than the reference voltage (Vref), the time at which memory cells are erased by the first erase voltage (1Vers) may be faster than the time at which memory cells are erased by the reference voltage (Vers). That is, fast cells (MCf) may be erased faster than slow cells (MCs).

[0054] The erasure interval (ERS) can be divided into first to third sub-intervals (1SEC~3SEC).

[0055] The first sub-period (1SEC) can be set between the first and second times (T1~T2), the second sub-period (2SEC) can be set between the second and third times (T2~T3), and the third sub-period (3SEC) can be set between the third and fourth times (T3~T4).

[0056] In the first sub-section (1SEC), a first erase voltage (1Vers) higher than the reference voltage (Vref) may be used to allow the erase operation of memory cells to proceed quickly. In the second sub-section (2SEC), a second erase voltage (2Vers) lower than the reference voltage (Vref) may be used to reduce the threshold voltage difference between slow cells (MCs) and fast cells (MCf). In the third sub-section (3SEC), a third erase voltage (3Vers) equal to the reference voltage (Vref) may be used to allow the erase operation to proceed while maintaining the threshold voltage difference between slow cells (MCs) and fast cells (MCf). The erase operation performed in the first to third sub-sections (1SEC~3SEC) is described in detail as follows.

[0057] Since the first sub-period (1SEC) is a period for rapidly performing the erase operation of memory cells, a first erase voltage (1Vers) higher than the reference voltage (Vref) can be consistently applied to the source line. Accordingly, between the start of the erase operation and the end of the first sub-period (1SEC) in the second time (T2), the slopes (1Gs, 1Gf) of memory cells (MCs, MCf) lowered by the first erase voltage (1Vers) can be greater than the slopes (pGs, pGf) of the threshold voltage (Vth) of memory cells lowered by the reference voltage (Vref). Here, the slope refers to the value obtained by dividing the change in the threshold voltage (Vth) by the change in time. Therefore, a large slope means that the threshold voltage (Vth) has been lowered relatively quickly during the same period of time, and a small slope means that the threshold voltage (Vth) has been lowered relatively slowly during the same period of time. If the erase operation is performed quickly, the threshold voltage (Vth) of the fast cells (MCf) decreases faster than that of the slow cells (MCs), so the difference in threshold voltage between the slow cells (MCs) and the fast cells (MCf) may increase before the second time (T2).

[0058] Since the second sub-section (2SEC) is a section for reducing the threshold voltage difference between slow cells (MCs) and fast cells (MCf), a second erase voltage (2Vers) lower than the reference voltage (Vref) can be constantly applied to the source line. The second erase voltage (2Vers) can be set to a positive voltage lower than the reference voltage (Vref) and higher than 0V. When the first erase voltage (1Vers) applied to the source line is lowered to the second erase voltage (2Vers), the amount of change in the threshold voltage (Vth) of the slow cells (MCs) and fast cells (MCf) can be reduced. At this time, the amount of change in the threshold voltage (Vth) of the fast cells (MCf) can be reduced more than that of the slow cells (MCs). Because, prior to the second time (T2), the amount of change in the threshold voltage (Vth) of the slow cells (MCs) is lower than the amount of change in the threshold voltage (Vth) of the fast cells (MCf), the effect of the change in the erase voltage between the second and third times (T2~T3) may be less in the slow cells (MCs) than in the fast cells (MCf).

[0059] Since the threshold voltage (Vth) of the fast cells (MCf) decreased faster than the threshold voltage (Vth) of the slow cells (MCs) prior to the second time (T2), the effect of the erase voltage change between the second and third times (T2~T3) may be greater in the fast cells (MCf) than in the slow cells (MCs). Therefore, in the second sub-interval (2SEC), the slope (2Gf) ​​for the change in threshold voltage of the fast cells (MCf) may be lower than the slope (2Gs) for the change in threshold voltage of the slow cells (MCs).

[0060] That is, in the second sub-period (2SEC), the change in the threshold voltage (Vth) of the slow cells (MCs) is greater than the change in the threshold voltage (Vth) of the fast cells (MCf). As a result, assuming that the difference in threshold voltage between the fast cells (MCf) and the slow cells (MCs) is the first level (1LV) at the second time (T2) when the second sub-period (2SEC) begins, the difference in threshold voltage between the fast cells (MCf) and the slow cells (MCs) can have a second level (2LV) lower than the first level (1LV) at the third time (T3) when the second sub-period (2SEC) ends.

[0061] Since the third sub-section (3SEC) is a section where the erase operation proceeds while maintaining the threshold voltage difference between the slow cells (MCs) and the fast cells (MCf), a third erase voltage (3Vers) higher than the second erase voltage (2Vers) can be constantly applied to the source line. In order to erase the memory cells while suppressing the increase in the threshold voltage difference between the slow cells (MCs) and the fast cells (MCf) in the third sub-section (3SEC), the third erase voltage (3Vers) can be set to a voltage higher than the second erase voltage (2Vers) and lower than the first erase voltage (1Vers). For example, the third erase voltage (3Vers) can be set to have the same level as the reference voltage (Vref). As a result, the slope (3Gs) of the threshold voltage (Vth) of the slow cells (MCs) and the slope (3Gf) of the threshold voltage (Vth) of the fast cells (MCf) are larger than the second sub-period (2SEC) and can be maintained similarly to each other.

[0062] After the fourth time (T4) at which the third sub-period (3SEC) ends, a discharge operation may be performed to lower the potential of the source line for the next operation. In the discharge period (DS) where the discharge operation is performed, not only the source line but also word lines, select lines, and bit lines may be discharged.

[0064] FIGS. 6a and FIGS. 6b are drawings for explaining the threshold voltage of memory cells according to a first embodiment of the present invention.

[0065] Referring to FIG. 6a and FIG. 5, when only a reference voltage (Vref) is applied consistently to the source line during the erasure interval (ERS), the distribution width (pD) of the threshold voltage (61) of the memory cells may be widened due to deep erasing of the fast cells (MCf). However, as in the first embodiment, deep erasing of the fast cells (MCf) can be prevented by applying a first erasure voltage (1Vers) higher than the reference voltage (Vref), a second erasure voltage (2Vers) lower than the reference voltage (Vref), and a third erasure voltage (3Vers) equal to the reference voltage (Vref) to the source line in different sub-intervals. As a result, the threshold voltage of the fast cells (MCf) may be increased, and thus the distribution width (rD) of the threshold voltage (62) of the memory cells may be relatively narrowed.

[0066] Referring to FIG. 6b, if the distribution width of the threshold voltage (62) of the erased memory cells is narrowed, the time (tPGM) required for the threshold voltage of the fast cells to rise to the target voltage (VT) during program operation can be shortened, and thus the program operation time can be shortened.

[0068] FIG. 7 is a diagram illustrating an erasure operation according to a second embodiment of the present invention.

[0069] Referring to FIGS. 7 and FIGS. 5, the same erase voltage may be applied to the source line in the first and third sub-sections (1SEC, 3SEC), and a second erase voltage (2Vers) may be applied to the source line in the second sub-section (2SEC). In the second embodiment, some descriptions that overlap with the first embodiment are omitted. In the first and third sub-sections (1SEC, 3SEC), a first erase voltage (1Vers) or a third erase voltage (3Vers) may be applied to the source line. The first to third erase voltages (1Vers to 3Vers) used in the second embodiment may each be the same as the first to third erase voltages (1Vers to 3Vers) used in the first embodiment.

[0070] When the first erasure voltage (1Vers) is used in the first and third sub-sections (1SEC, 3SEC), the first erasure voltage (1Vers) is the highest among the first to third erasure voltages (1Vers to 3Vers), so the time taken for the third sub-section (3SEC) can be shortened compared to the first embodiment. For example, the third sub-section (3SEC) can be performed from the third time (T3) to the fourth time (T4), and the fourth time (T4) of the second embodiment may be shorter than the fourth time (T4) of the first embodiment.

[0071] When a third erase voltage (3Vers) is used in the first and third sub-sections (1SEC, 3SEC), the third erase voltage (3Vers) is lower than the first erase voltage (1Vers), so the time taken for the first sub-section (1SEC) may increase compared to the first embodiment. For example, the first sub-section (1SEC) may be performed from the first time (T1) to the second time (T2), and the second time (T2) of the second embodiment may be longer than the second time (T2 of FIG. 5) of the first embodiment. However, since a second erase voltage (2Vers) lower than the first and third erase voltages (1Vers, 3Vers) is applied to the source line in the second sub-section (2SEC), the threshold voltage distribution width of the erased memory cells may be narrowed.

[0073] FIG. 8 is a diagram illustrating an erasure operation according to a third embodiment of the present invention.

[0074] Referring to FIG. 8 and FIG. 5, in the third embodiment, the second time (T2) or the third time (T3) may be variable (81), and the first to third erase voltages (1Vers to 3Vers) applied to the source line in the first to third sub-sections (1SEC to 3SEC) may be the same as the first to third erase voltages (1Vers to 3Vers) described in the first embodiment. In the third embodiment, since the electrical characteristics of the memory cells may differ depending on the memory device, the time set in the first to third sub-sections (1SEC to 3SEC) may be changed according to the electrical characteristics of the memory cells included in the memory device. The second time (T2) or the third time (T3) may be set according to the number of fast cells (MCf). For example, in a memory device with a relatively small number of fast cells (MCf), the threshold voltage difference between the fast cells (MCf) and the slow cells (MCs) may be relatively small, so the second or third time (T2 or T3) may be adjusted so that the time taken for the second sub-period (2SEC) to reduce the threshold voltage difference is shortened. Conversely, in a memory device with a relatively large number of fast cells (MCf), the threshold voltage difference between the fast cells (MCf) and the slow cells (MCs) may be relatively large, so the second or third time (T2 or T3) may be adjusted so that the time taken for the second sub-period (2SEC) to reduce the threshold voltage difference is increased.

[0076] FIG. 9 is a drawing for explaining an erasure operation according to a fourth embodiment of the present invention.

[0077] Referring to FIG. 9, in the fourth embodiment, when the second sub-period (2SEC) begins, the first erasure voltage (1Vers) applied to the source line can be gradually lowered to the second erasure voltage (2Vers) (SP). Since the erasure operation can be performed in the same manner as in the first embodiment from the start of the erasure operation until the second time (T2), a description that overlaps with the first embodiment is omitted.

[0078] When the second time (T2) begins, the first erasure voltage (1Vers) applied to the source line can be lowered to a reference voltage (Vref), and after a certain period of time, the reference voltage (Vref) can be lowered to a second erasure voltage (2Vers). FIG. 9 illustrates a step of lowering the first erasure voltage (1Vers) to the reference voltage (Vref) by one step before it is lowered to the second erasure voltage (2Vers), but it may be lowered by two or more steps. From the third time (T3) onwards, the erasure operation can be performed in the same manner as in the first embodiment.

[0080] FIG. 10 is a drawing for explaining an erasure operation according to a fifth embodiment of the present invention.

[0081] Referring to FIG. 10, in the fifth embodiment, when the third sub-period (3SEC) begins, the second erase voltage (2Vers) applied to the source line can be gradually increased to the third erase voltage (3Vers) (SP). Since the erase operation can be performed in the same manner as in the first embodiment from the start of the erase operation until the third time (T3), a description that overlaps with the first embodiment is omitted.

[0082] When the third time (T3) begins, the second erase voltage (2Vers) applied to the source line can be raised to a step voltage between the second erase voltage (2Vers) and the reference voltage (Vref), and after a certain period of time, the step voltage can be lowered to the third erase voltage (3Vers). FIG. 10 shows a step of raising the step voltage by one step before the second erase voltage (2Vers) is raised to the third erase voltage (3Vers), but it may be raised by two or more steps.

[0084] FIG. 11 is a drawing for explaining an erasure operation according to a sixth embodiment of the present invention.

[0085] Referring to FIG. 11, in the sixth embodiment, the second erase voltage (2Vers) in the second sub-period (2SEC) may not be maintained for a certain period of time and may gradually increase to the third erase voltage (3Vers). Since the erase operation may be performed in the same manner as in the first embodiment up to the second time (T2) after the erase operation begins, a description that overlaps with the first embodiment is omitted.

[0086] When the second time (T2) begins, the first erasure voltage (1Vers) applied to the source line can be gradually lowered to the second erasure voltage (2Vers). When the potential of the source line is lowered to the second erasure voltage (2Vers), the potential of the source line can be gradually raised to the third erasure voltage (3Vers) without maintaining the second erasure voltage (2Vers). At this time, the voltage generator (120 in FIG. 1) can adjust the voltage so that the second erasure voltage (2Vers) is gradually raised to the third erasure voltage (3Vers) without rapidly raising it. For example, assuming the time taken to decrease from the first erasure voltage (1Vers) to the second erasure voltage (2Vers) is the first variable time (1DT), the second variable time (2DT) taken to increase from the second erasure voltage (2Vers) to the third erasure voltage (3Vers) may be longer than the first variable time (1DT). From the third time (T3) onwards, the erasure operation may be performed in the same manner as in the first embodiment.

[0088] FIG. 12 is a drawing for explaining a memory card system to which the memory device of the present invention is applied.

[0089] Referring to FIG. 12, the memory card system (3000) includes a controller (3100), a memory device (3200), and a connector (3300).

[0090] The controller (3100) is connected to the memory device (3200). The controller (3100) is configured to access the memory device (3200). For example, the controller (3100) may be configured to control program, read, or erase operations of the memory device (3200), or to control background operations. The controller (3100) is configured to provide an interface between the memory device (3200) and a host. The controller (3100) is configured to run firmware for controlling the memory device (3200). For example, the controller (3100) may include components such as RAM (Random Access Memory), a processing unit, a host interface, a memory interface, and an error correction unit.

[0091] The controller (3100) can communicate with an external device through a connector (3300). The controller (3100) can communicate with an external device (e.g., a host) according to a specific communication standard. For example, the controller (3100) is configured to communicate with an external device through at least one of various communication standards such as USB (Universal Serial Bus), MMC (multimedia card), eMMC (embedded MMC), PCI (peripheral component interconnection), PCI-E (PCI-express), ATA (Advanced Technology Attachment), Serial-ATA, Parallel-ATA, SCSI (small computer system interface), ESDI (enhanced small disk interface), IDE (Integrated Drive Electronics), Firewire, UFS (Universal Flash Storage), WIFI, Bluetooth, NVMe, etc. For example, the connector (3300) may be defined by at least one of the various communication standards described above.

[0092] The memory device (3200) may include a plurality of memory cells and may be configured in the same way as the memory device (100) shown in FIG. 1. Accordingly, the memory device (3200) can control a soft program operation to raise the threshold voltage of the dummy cells.

[0093] The controller (3100) and the memory device (3200) can be integrated into a single semiconductor device to form a memory card. For example, the controller (3100) and the memory device (3200) can be integrated into a single semiconductor device to form a memory card such as a PC card (PCMCIA, Personal Computer Memory Card International Association), Compact Flash Card (CF), Smart Media Card (SM, SMC), Memory Stick, Multimedia Card (MMC, RS-MMC, MMCmicro, eMMC), SD Card (SD, miniSD, microSD, SDHC), Universal Flash Storage (UFS), etc.

[0095] FIG. 13 is a drawing for explaining a Solid State Drive (SSD) system to which the memory device of the present invention is applied.

[0096] Referring to FIG. 13, the SSD system (4000) includes a host (4100) and an SSD (4200). The SSD (4200) transmits and receives signals with the host (4100) through a signal connector (4001) and receives power through a power connector (4002). The SSD (4200) includes a controller (4210), a plurality of memory devices (4221 to 422n), an auxiliary power supply (4230), and a buffer memory (4240).

[0097] The controller (4210) can control a plurality of memory devices (4221 to 422n) in response to a signal received from the host (4100). For example, the signal may be a signal based on an interface between the host (4100) and the SSD (4200). For example, the signal may be a signal defined by at least one of interfaces such as USB (Universal Serial Bus), MMC (multimedia card), eMMC (embedded MMC), PCI (peripheral component interconnection), PCI-E (PCI-express), ATA (Advanced Technology Attachment), Serial-ATA, Parallel-ATA, SCSI (small computer system interface), ESDI (enhanced small disk interface), IDE (Integrated Drive Electronics), Firewire, UFS (Universal Flash Storage), WIFI, Bluetooth, NVMe, etc.

[0098] A plurality of memory devices (4221 to 422n) may include a plurality of memory cells configured to store data. Each of the plurality of memory devices (4221 to 422n) may be configured identically to the memory device (100) shown in FIG. 1. Accordingly, each of the plurality of memory devices (4221 to 422n) can control a soft program operation to raise the threshold voltage of the dummy cells. The plurality of memory devices (4221 to 422n) can communicate with the controller (4210) through channels (CH1 to CHn).

[0099] The auxiliary power supply unit (4230) is connected to the host (4100) via a power connector (4002). The auxiliary power supply unit (4230) receives power voltage from the host (4100) and can charge. The auxiliary power supply unit (4230) can provide power voltage to the SSD (4200) when power supply from the host (4100) is not smooth. For example, the auxiliary power supply unit (4230) may be located inside the SSD (4200) or outside the SSD (4200). For example, the auxiliary power supply unit (4230) may be located on the main board and provide auxiliary power to the SSD (4200).

[0100] The buffer memory (4240) operates as a buffer memory for the SSD (4200). For example, the buffer memory (4240) may temporarily store data received from the host (4100) or data received from a plurality of memory devices (4221 to 422n), or may temporarily store metadata (e.g., mapping tables) of the memory devices (4221 to 422n). The buffer memory (4240) may include volatile memory such as DRAM, SDRAM, DDR SDRAM, LPDDR SDRAM, etc., or non-volatile memory such as FRAM, ReRAM, STT-MRAM, PRAM, etc. Explanation of the symbols

[0102] 100: Memory device 110: Memory cell array 120: Voltage generator 130: Low decoder 140: Page buffer group 150: Column decoder 160: Input / Output Circuit 170: Peripheral circuits 180: Control circuit 41: Section Management Department 42: Voltage Level Management Unit

Claims

Claim 1 A method of operating a memory device comprising: a step of applying a first erase voltage to a source line during an erase operation of a memory block connected between a source line and bit lines; a step of lowering the voltage of the source line to which the first erase voltage is applied to a second erase voltage; and a step of raising the voltage of the source line to which the second erase voltage is applied to a third erase voltage. Claim 2 A method of operation of a memory device according to claim 1, wherein the third erase voltage is higher than the second erase voltage and lower than the first erase voltage. Claim 3 In claim 1, the third erase voltage is the same as the first erase voltage, in the method of operation of the memory device. Claim 4 A method of operation of a memory device according to claim 1, wherein the first erase voltage is maintained for a certain period of time after the first erase voltage is applied to the source line. Claim 5 A method of operation of a memory device according to claim 1, wherein the second erase voltage is maintained for a certain period of time after the second erase voltage is applied to the source line. Claim 6 A method of operation of a memory device according to claim 1, wherein after the second erase voltage is applied to the source line, the second erase voltage is raised to the third erase voltage without maintaining the second erase voltage. Claim 7 A method of operation of a memory device according to claim 6, wherein the time taken to increase from the second erase voltage to the third erase voltage is longer than the time taken to decrease from the first erase voltage to the second erase voltage. Claim 8 A method of operation of a memory device according to claim 1, wherein when the first erase voltage, the second erase voltage, or the third erase voltage is applied to the source line, the bit lines are floated, the select transistors between the source line and the bit lines are turned on, and the memory cells between the select transistors are turned on. Claim 9 A method of operation of a memory device according to claim 8, wherein a turn-on voltage is applied to select lines connected to the gates of the select transistors, and a pass voltage is applied to word lines connected to the gates of the memory cells. Claim 10 A method of operation of a memory device according to claim 9, wherein the turn-on voltage is set to a positive voltage higher than 0V, and the pass voltage has the same level as the turn-on voltage. Claim 11 A method of operation of a memory device according to claim 9, wherein the turn-on voltage is set to a positive voltage higher than 0V, and the pass voltage has a level higher than the turn-on voltage and lower than the first to third erase voltages. Claim 12 A method of operating a memory device comprising: a first step of lowering the threshold voltage of slow cells and fast cells included in a selected memory block; a second step of reducing the difference in threshold voltage between the slow cells and the fast cells after the first step; and a third step of lowering the threshold voltage of the slow cells and the fast cells after the second step. Claim 13 A method of operation of a memory device according to claim 12, wherein, in the first step, a first erase voltage having a positive voltage level is applied to source lines or bit lines connected to the selected memory block. Claim 14 A method of operation of a memory device according to claim 13, wherein, in the second step, a second erase voltage having a positive voltage level lower than the positive voltage level of the first erase voltage is applied to the source lines or bit lines connected to the selected memory block. Claim 15 A method of operation of a memory device according to claim 14, wherein, in the third step, a third erase voltage higher than the second erase voltage is applied to the source lines or bit lines connected to the selected memory block. Claim 16 A method of operation of a memory device according to claim 15, wherein the third erase voltage is equal to the first erase voltage or has a lower level than the first erase voltage. Claim 17 A memory device comprising: a section management unit configured to sequentially output time information for an erasure voltage rise section, an erasure section including a plurality of sub-sections, and a discharge section in response to an erasure command; a voltage level management unit configured to change and output an operation code in response to the time information; and a voltage generator configured to sequentially output erasure voltages having different levels in response to the operation code, wherein, during an erasure operation, the voltage generator is configured to sequentially output a first erasure voltage, a second erasure voltage lower than the first erasure voltage, and a third erasure voltage higher than the second erasure voltage in response to the operation code. Claim 18 In claim 17, the above-mentioned interval management unit includes algorithms corresponding to program, read, or erase operations, respectively, and is configured to output time information according to an algorithm selected in response to a command among the algorithms. Claim 19 In claim 17, the voltage level management unit is a memory device configured to generate and output the operation code including the erase voltage rise section included in the time information, the erase section including the plurality of sub-sections or the discharge section, and the code corresponding to the voltage level. Claim 20 In claim 17, the above voltage generator is configured to sequentially output the erasure voltages having the different levels to a global line corresponding to the source line of a memory block.

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