Semiconductor package and method of manufacturing the semiconductor package

Abstract

A semiconductor package comprises a package substrate, a plurality of first semiconductor chips having a first top semiconductor chip having a first height from the package substrate and sequentially stacked in a stepped shape on the upper surface of the package substrate, conductive wires electrically connecting the chip pads of the first semiconductor chips to the substrate pads of the package substrate, and a plurality of first support structures each extending from the upper surface of the package substrate to have a height equal to the first height and inclined at a predetermined inclination from the vertical direction, and arranged along an overhang portion of the first top semiconductor chip protruding from the first semiconductor chips below the first top semiconductor chip to support the overhang portion.

Description

Technology Field

[0001] The present invention relates to a semiconductor package and a method for manufacturing a semiconductor package. More specifically, the present invention relates to a multi-chip package in which semiconductor chips of different heights are arranged on a package substrate and a method for manufacturing the same. Background Technology

[0002] In Multi-Chip Packages (MCPs), issues such as bouncing, wire bonding defects, and chip cracks may occur in the overhang portion of the top-level semiconductor chip. Regarding methods to resolve these problems, increasing the thickness of the top-level semiconductor chip increases the overall package thickness; forming spacer chips consumes space; and requiring a waiting time for bouncing to dissipate reduces productivity due to a decrease in overall production speed. Prior art literature

[65535] Patent Document 1: U.S. Patent Application Publication US2011 / 0089575 The problem to be solved

[0003] One objective of the present invention is to provide a semiconductor package comprising a plurality of support structures for supporting a top semiconductor chip.

[0004] Another objective of the present invention is to provide a method for manufacturing the semiconductor package. means of solving the problem

[0005] A semiconductor package according to exemplary embodiments for achieving one objective of the present invention comprises: a package substrate; a plurality of first semiconductor chips having a first top semiconductor chip having a first height from the package substrate and sequentially stacked in a stepped shape on the upper surface of the package substrate; conductive wires electrically connecting the chip pads of the first semiconductor chips to the substrate pads of the package substrate; and a plurality of first support structures each extending from the upper surface of the package substrate to have a height equal to the first height and inclined at a predetermined inclination from the vertical direction, and arranged along an overhang portion of the first top semiconductor chip protruding from the first semiconductor chips below the first top semiconductor chip to support the overhang portion.

[0006] A semiconductor package according to exemplary embodiments for achieving another objective of the present invention comprises: a package substrate; a plurality of first semiconductor chips having a first top semiconductor chip spaced apart from the package substrate at a first height, having bonding pads exposed on an upper surface and stacked on the package substrate in an inclined stepped shape; conductive wires that contact the bonding pads to electrically connect the first top semiconductor chip to the package substrate; and a plurality of first support structures each extending from the package substrate at the first height and inclined at a predetermined inclination from the vertical direction, arranged along an overhang portion of the first top semiconductor chip protruding from the first semiconductor chips, and supporting the lower portion of the overhang portion at a position spaced apart from the bonding pads in the vertical direction.

[0007] A method for manufacturing a semiconductor package according to exemplary embodiments for achieving another objective of the present invention comprises forming support structures having a predetermined height in a vertical direction from the upper surface of a package substrate. A plurality of semiconductor chips are stacked in a stepped shape up to a height equal to the predetermined height of the support structures. An uppermost semiconductor chip is stacked on the support structures and the semiconductor chips. A conductive wire is connected to the uppermost semiconductor chip. Forming the support structures includes extending a conductive material ejected from a capillary to have a predetermined length equal to the predetermined height from the package substrate to contact a contact pad, forming a scratch on the conductive material while the conductive material is not attached to the contact pad, and moving the capillary in the vertical direction to erect the conductive material and cut the scratch on the conductive material. Effects of the invention

[0008] According to exemplary embodiments, a semiconductor package may include a package substrate, a plurality of first semiconductor chips having a first top semiconductor chip having a first height from the package substrate and sequentially stacked in a stepped shape on the upper surface of the package substrate, conductive wires electrically connecting the chip pads of the first semiconductor chips to the substrate pads of the package substrate, and a plurality of first support structures each extending from the upper surface of the package substrate to have a height equal to the first height and inclined at a predetermined inclination from the vertical direction, and arranged along an overhang portion of the first top semiconductor chip protruding from the first semiconductor chips below the first top semiconductor chip to support the overhang portion.

[0009] Accordingly, the support structure can support the overhang portion of the first top semiconductor chip by compensating for the height difference between the package substrate and the first top semiconductor chip. Therefore, by utilizing the support structures formed during the wire bonding process, bouncing of the first top semiconductor chip can be prevented, costs can be reduced, and productivity can be improved.

[0010] However, the effects of the present invention are not limited to the effects mentioned above and may be extended in various ways without departing from the spirit and scope of the present invention. Brief explanation of the drawing

[0011] FIG. 1 is a cross-sectional view showing a semiconductor package according to exemplary embodiments. Figure 2 is an enlarged cross-sectional view showing part A of Figure 1. Figure 3 is an enlarged perspective view showing part A of Figure 1. FIG. 4 is a flowchart illustrating a method for manufacturing a semiconductor package according to exemplary embodiments. FIGS. 5 to 12 are cross-sectional views illustrating a method for manufacturing a semiconductor package according to exemplary embodiments. FIGS. 13 to 15 are enlarged cross-sectional views showing part B of FIG. 12 when including support structures having a preset inclination. FIGS. 16 to 18 are enlarged perspective views showing part B of FIG. 12 when including support structures having a preset inclination. FIG. 19 is an enlarged cross-sectional view showing part B of FIG. 12 when the supporting structures have different height deviations. FIG. 20 is a cross-sectional view showing a semiconductor package including support structures that support the lower surface of additional semiconductor chips according to exemplary embodiments. FIG. 21 is a cross-sectional view showing a semiconductor package including support structures that support the top semiconductor chip of additional semiconductor chips according to exemplary embodiments. Specific details for implementing the invention

[0012] Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the attached drawings.

[0013] FIG. 1 is a cross-sectional view showing a semiconductor package according to exemplary embodiments. FIG. 2 is an enlarged cross-sectional view showing portion A of FIG. 1. FIG. 3 is an enlarged perspective view showing portion A of FIG. 1.

[0014] Referring to FIGS. 1 to 3, a semiconductor package (10) may include a package substrate (20), a plurality of first semiconductor chips (100) disposed on the package substrate, conductive wires (200) for electrically connecting the first semiconductor chips (100) to the package substrate (20), and a plurality of first support structures (300). Additionally, the semiconductor package (10) may further include a sealing member (400). The semiconductor package (10) may further include an electronic device (40).

[0015] In exemplary embodiments, the package substrate (20) may be a substrate having an upper surface (20a) and a lower surface (20b) facing each other. For example, the package substrate (20) may include a printed circuit board (PCB), a flexible substrate, a tape substrate, etc. The printed circuit board may be a multilayer circuit board having vias and various circuits inside.

[0016] Substrate pads (22), each connected to a plurality of wires, may be disposed on the upper surface (20a) of the package substrate (20). The wires may extend from the upper surface (20a) or from within the package substrate (20). The substrate pads (22) may be connected to the ends of the wires. For example, at least a portion of the wires may be used as a landing pad and as a substrate pad.

[0017] The above wiring may include power wiring or ground wiring as a power net for supplying power to electronic components mounted on the package substrate (20). The substrate pads (22) may include power pads or ground pads connected to the power wiring or ground wiring. Additionally, the substrate pads (22) may further include a plurality of substrate signal wirings and substrate signal pads for transmitting data signals to the electronic components.

[0018] Although only a few substrate pads are illustrated in the drawings above, it will be understood that the number and arrangement of the substrate pads are provided as examples and that the present invention is not limited thereto. Since the substrate pads, the substrate signal pads, and the wiring are widely known in the art to which the present invention belongs, their illustration and description will be omitted.

[0019] A first insulating film (24) covering the wiring and exposing the substrate pads (22) may be formed on the upper surface (20a) of the package substrate (20). The first insulating film (24) may cover the entire upper surface (20a) of the package substrate (20) excluding the substrate pads (22). For example, the first insulating film (24) may include a solder resist.

[0020] External connection pads (28) for providing an electrical signal may be formed on the lower surface (20b) of the package substrate (20). The external connection pads (28) may be exposed by a second insulating film (26). The second insulating film may include a silicon oxide film, a silicon nitride film, or a silicon oxynitride film. An external connection member (30) may be disposed on the external connection pads (28) of the package substrate (20) for electrical connection with an external device. For example, the external connection member (30) may be a solder ball. The semiconductor package (10) may be mounted on a module substrate (not shown) via the solder balls to form a memory module.

[0021] In exemplary embodiments, a sealing member (400) is formed on a package substrate (20) to protect first semiconductor chips (100), conductive wires (200), electronic devices (40), and first support structures (300) from the outside. The sealing member may include an epoxy mold compound (EMC).

[0022] In exemplary embodiments, a plurality of first semiconductor chips (100) may be mounted on a package substrate (20). A plurality of first semiconductor chips (100) may be stacked in a stepped shape on the package substrate (20). The stepped shape may include a stepped shape inclined to one side. A plurality of first semiconductor chips (100) may include a first uppermost semiconductor chip (110) spaced apart from the package substrate (20) by a first height (H1).

[0023] In the present specification, the direction in which the first semiconductor chips (100) are stacked in the step shape is called the first horizontal direction, the horizontal direction opposite to the first horizontal direction is called the second horizontal direction, and the direction orthogonal to the first horizontal direction and the second horizontal direction is called the vertical direction.

[0024] For example, five first semiconductor chips (100a, 100b, 100c, 100d, 110) can be attached to the upper surface (20a) of a package substrate (20) using first adhesive members (120a, 120b, 120c, 120d, 120e). For example, the first adhesive members may include an adhesive film such as a direct adhesive film (DAF).

[0025] The first semiconductor chip (100) may have first chip pads (bonding pads) formed on an upper surface, that is, an active surface. The first chip pads (130) may include an input / output terminal that performs a power pin function, an input / output terminal that performs a ground pin function, or an input / output terminal that performs a data pin function.

[0026] The first chip pads (130) may be rewiring pads. The first semiconductor chip (100) may include a rewiring layer at the top. The rewiring layer may include the first chip pads (130). Although only a few chip pads are shown in the drawings, it will be understood that the structure and arrangement of the chip pads are provided as examples and that the present invention is not limited thereto. Furthermore, the chip signal pads, including the chip pads, are widely known in the art to which the present invention belongs, so they are omitted from illustration and description.

[0027] The first semiconductor chip (100) can be electrically connected to the package substrate (20) by conductive wires (200). For example, the first semiconductor chips can be mounted on the package substrate (20) by a wire bonding method. Specifically, the conductive wire (200) can electrically connect the first chip pad (130) of the first semiconductor chip (100) to the substrate pad (22) of the package substrate (20). For example, the conductive wire (200) may include a bonding wire. Accordingly, the first semiconductor chips (100) can be stacked on the package substrate (20) by the first adhesive member and electrically connected to the package substrate (20) by a plurality of conductive wires (200).

[0028] The first semiconductor chip (100) may include a memory chip comprising a memory circuit. For example, the first semiconductor chip (100) may include a volatile memory device such as a DRAM. It will be understood that the number, size, arrangement, etc. of the first semiconductor chips are provided as examples and that the present invention is not limited thereto.

[0029] In exemplary embodiments, the electronic device (40) may be mounted on the package substrate (20). The electronic device (40) may be spaced apart from the first semiconductor chips (100) on the package substrate (20). The electronic device (40) may be electrically connected to the first semiconductor chips (100) through the package substrate (20). The electronic device (40) may be attached to the upper surface (20a) of the package substrate (20) using an adhesive member. The electronic device (40) may include an integrated circuit. For example, the electronic device (40) may be a logic chip including a logic circuit. The logic chip may be a controller that controls memory chips.

[0030] In exemplary embodiments, the first top semiconductor chip (110) may be a semiconductor chip stacked on the uppermost layer among the first semiconductor chips (100). The first top semiconductor chip (110) may have a first upper surface (110a) and a first lower surface (110b) opposite each other. The first lower surface (110b) of the first top semiconductor chip (110) may be spaced apart from the package substrate (20) by a first height (H1). The first top semiconductor chip (110) may include an overhang portion (OH) protruding from the first semiconductor chips (100).

[0031] The first uppermost semiconductor chip (110) may have first bonding pads (112) formed on the upper surface, that is, the active surface. The first bonding pads (112) may include an input / output terminal that performs a power pin function, an input / output terminal that performs a ground pin function, or an input / output terminal that performs a data pin function.

[0032] The first bonding pads (112) may be the rewiring pads. The first uppermost semiconductor chip (110) may include the rewiring layer at the top. The rewiring layer may include the first bonding pads (112).

[0033] The first top semiconductor chip (110) can be electrically connected to the package substrate (20) by conductive wires (200). For example, the first top semiconductor chips can be mounted on the package substrate (20) by the wire bonding method. Specifically, the conductive wire (200) can electrically connect the first bonding pad (112) of the first top semiconductor chip (110) to the substrate pad (22) of the package substrate (20). Accordingly, the first semiconductor chips (100) can be stacked on the package substrate (20) by the adhesive members and electrically connected to the package substrate (20) by a plurality of conductive wires (200).

[0034] The overhang portion (OH) may be a structure protruding from the inclined step shape of the first semiconductor chips (100). First bonding pads (112) may be provided in the overhang portion (OH). For example, the length of the overhang portion (OH) may be within the range of 200 µm to 400 µm. In the process of connecting conductive wires (200) by contacting the first bonding pads (112) provided in the overhang portion (OH), the first uppermost semiconductor chip (110) may receive a force in the vertical direction.

[0035] In exemplary embodiments, the first support structure (300) may be disposed on the package substrate (20). The first support structure (300) may be disposed between the package substrate (20) and the first top semiconductor chip (110) of the first semiconductor chips (100) to support the first top semiconductor chip (110). The height of the first support structure (300) may have a first height (H1) equal to the distance from the package substrate (20) to the first bottom surface (110b) of the first top semiconductor chip (110).

[0036] Specifically, the first support structure (300) may include at least one first dummy pad (310) disposed on the package substrate (20) and a first dummy wire (320) having one end bonded to the first dummy pad (310) and supporting the first lower surface (110b) of the first top semiconductor chip (110). The one end of the first dummy wire (320) may be bonded to the upper surface of the package substrate (20). The other end of the first dummy wire (320) may extend upward from the one end and contact the lower part of the overhang portion (OH) of the first top semiconductor chip (110). For example, the first dummy wire (320) may have an I-shaped form and support the overhang portion.

[0037] The first support structures (300) may be arranged adjacent to the side of the overhang portion (OH) at the bottom of the overhang portion (OH). The first support structures (300) may be arranged in multiple rows to cover the bottom of the overhang portion (OH). For example, the multiple rows may be provided without limitation to support the bottom surface of the overhang portion (OH).

[0038] For example, a plurality of first dummy pads (310) may be arranged on the upper surface (20a) of the package substrate (20). A plurality of first dummy pads (310) may be arranged along one direction. A plurality of first dummy pads (310) may be spaced apart from each other by a predetermined interval. One end of the first dummy wire (320) may be joined to the first dummy pad (310). The first dummy wire (320) may have a first height (H1) that extends upward from the end end to support the overhang portion (OH) of the first top semiconductor chip (110).

[0039] A plurality of first dummy pads (310) may be provided on the package substrate (20) at a position corresponding to the first bonding pads (112) of the first top semiconductor chip (110). A plurality of first dummy pads (310) may be arranged at any desired position on the upper surface of the package substrate (20). Additionally, each of the first dummy wires (320) connected to the plurality of first dummy pads (310) may have a first height (H1) selected according to the height difference between the upper surface (20a) of the package substrate (20) and the overhang portion (OH) of the first top semiconductor chip (110).

[0040] A plurality of first dummy wires (320) may each extend in the vertical direction from the first dummy pads (310). A plurality of first dummy wires (320) may extend in the vertical direction from the first dummy pads (310) at a position corresponding to the first bonding pads (112) of the first top semiconductor chip (110). The first dummy wires (320) may extend in the vertical direction to support the overhang portion (OH) of the first top semiconductor chip (110) in the process of connecting the first bonding pads (112) of the first top semiconductor chip (110) and the conductive wires (200).

[0041] The spacing between the plurality of first dummy pads (310) and the diameter of the first dummy wire (320) can be selected by considering the length or thickness of the overhang portion (OH) of the first uppermost semiconductor chip (110). For example, the diameter of the first dummy wire (320) may be within the range of 1.0 mm to 3.5 mm.

[0042] The first dummy wire (320) may have a thickness equal to or greater than the thickness of the bonding wire. Additionally, the first dummy wire (320) may be formed using a material having excellent strength and high thermal conductivity. For example, the first dummy wire (320) may be formed using the same material as the bonding wire. Alternatively, the first dummy wire (320) may be formed using a non-conductive material.

[0043] For example, the first dummy wire (320) may include copper (Cu), aluminum (Al), tungsten, nickel (Ni), molybdenum (Mo), gold (Au), silver (Ag), chromium (Cr), tin (Sn), and titanium (Ti).

[0044] Additionally, the dummy pad may be formed using the same material as the chip pad. Alternatively, the dummy pad may be attached to the package substrate via a non-conductive adhesive film. An example of the non-conductive adhesive film may be a polyimide film.

[0045] Below, a method for manufacturing the semiconductor package of FIG. 1 will be described.

[0046] FIG. 4 is a flowchart illustrating a method for manufacturing a semiconductor package according to exemplary embodiments. FIGS. 5 to 12 are cross-sectional views illustrating a method for manufacturing a semiconductor package according to exemplary embodiments. FIGS. 13 to 15 are enlarged cross-sectional views showing part B of FIG. 12 when supporting structures having a preset inclination are included. FIGS. 16 to 18 are enlarged perspective views showing part B of FIG. 12 when supporting structures having a preset inclination are included. FIG. 19 is an enlarged cross-sectional view showing part B of FIG. 12 when supporting structures have different height deviations.

[0047] Referring to FIGS. 4 to 12, a first support structure (300) extending vertically on a package substrate (20) can first be formed (S110).

[0048] In exemplary embodiments, the first support structure (300) may be disposed on the package substrate (20). The first support structure (300) may be formed during the wire bonding process.

[0049] As shown in FIG. 6, a conductive material (322) can be extended from a package substrate (20) to have a predetermined length (L) and come into contact with a contact pad (23).

[0050] The conductive material (322) may be ejected from a capillary (CP). The conductive material (322) may extend from a substrate pad (22) formed on a package substrate (20). The extended conductive material (322) may come into contact with a contact pad (23). The contact pad (23) may be a conductive pad formed on a semiconductor package (10) to form a first support structure (300). Alternatively, the conductive material (322) may extend from the package substrate (20) and come into contact with any point on the package substrate (20).

[0051] The conductive material (322) may include the same material as the conductive wires (200) that electrically connect the semiconductor package (10) and the first semiconductor chips (100). The conductive material (322) may include copper (Cu), aluminum (Al), tungsten, nickel (Ni), molybdenum (Mo), gold (Au), silver (Ag), chromium (Cr), tin (Sn), and titanium (Ti).

[0052] As shown in FIG. 7, when a stitch operation is performed without the conductive material (322) being attached to the contact pad (23), a scratch (CR) may be formed on the conductive material (322).

[0053] A scratch (CR) may be formed on the conductive material (322) through the stitching operation during the process in which the conductive material (322) is ejected from the capillary (CP). The stitching operation may be performed when the conductive material (322) is ejected from the capillary (CP) for a predetermined length (L).

[0054] As shown in FIG. 8, a conductive material (322) can be erected in a vertical direction orthogonal to the package substrate (20), and a first support structure (300) can be formed by cutting the scratch portion (CR) of the conductive material (322).

[0055] The above capillary (CP) can be moved in the vertical direction from the substrate pad (22) to cut the conductive material (322). The conductive material (322) can be cut at the above scratch portion (CR). The first support structure (300) can be formed during the process of cutting the conductive material (322). The first support structure (300) can have a first height (H1) equal to the above preset length (L).

[0056] Next, a plurality of first semiconductor chips (100) can be stacked in a stepped shape up to a height equal to the first height (H1) of the first support structure (300) (S120).

[0057] In exemplary embodiments, as illustrated in FIG. 9, a plurality of first semiconductor chips (100) may be stacked in a stepped shape on a package substrate (20). The stepped shape may include a stepped shape inclined to one side.

[0058] For example, four first semiconductor chips (100a, 100b, 100c, 100d) can be laminated on the upper surface (20a) of a package substrate (20) using first adhesive members (120a, 120b, 120c, 120d). For example, the first adhesive members may include an adhesive film such as a direct adhesive film (DAF).

[0059] Next, a first uppermost semiconductor chip (110) can be stacked on a first support structure (300) and a plurality of first semiconductor chips (100) (S130).

[0060] In exemplary embodiments, the first top semiconductor chip (110) may be a semiconductor chip stacked on the uppermost layer among the first semiconductor chips (100). The first lower surface (110b) of the first top semiconductor chip (110) may be spaced apart from the package substrate (20) by a first height (H1). Because the first lower surface (110b) of the first top semiconductor chip (110) is spaced apart from the package substrate (20) by a first height (H1), the first top semiconductor chip (110) may be supported by a first support structure.

[0061] As illustrated in FIG. 10, the first top semiconductor chip (110) may include an overhang portion (OH) protruding from the first semiconductor chips (100). Conductive wires (200) may be connected to first bonding pads (112) formed on the active surface of the first top semiconductor chip (110). The first bonding pads (112) may be formed on the overhang portion (OH). The first bonding pads (112) may be formed at the same location as the first dummy pad (310) of the first support structure (300) in the vertical direction.

[0062] Next, a conductive wire (200) can be connected to the first uppermost semiconductor chip (110) and a sealing member (400) can be formed (S140).

[0063] In exemplary embodiments, the conductive wire (200) can electrically connect the first bonding pad (112) of the first top semiconductor chip (110) to the substrate pad (22) of the package substrate (20). A sealing member (400) can be formed on the package substrate (20) to protect the first semiconductor chips (100), the conductive wire (200), and the first support structures (300) from the outside. The sealing member may include an epoxy mold compound (EMC).

[0064] As illustrated in FIGS. 11 and 12, in the process of connecting conductive wires (200) by contacting them onto first bonding pads (112) provided in the overhang portion (OH), the first uppermost semiconductor chip (110) may receive a force in the vertical direction. The first support structures (300) may support the force acting in the vertical direction. Since the first support structures (300) are formed below the first bonding pads (112), they may effectively support the vertical force generated in the first uppermost semiconductor chip (110).

[0065] Referring to FIGS. 13 to 19, forming the first support structure (300) (S110) can be formed so that the first support structure (300) is inclined at a preset inclination. The first support structure (300) may have a preset inclination from the vertical direction.

[0066] In exemplary embodiments, forming the first support structure (300) (S110) may include extending a conductive material (322) ejected from a capillary (CP) from a package substrate (20) to have a preset length (L) and contacting it on a contact pad (23), performing the stitching operation while the conductive material (322) is not attached to the contact pad (23) to form a scratch (CR) on the conductive material (322), setting the conductive material (322) upright so as to be inclined at a preset inclination with the vertical direction orthogonal to the package substrate (20), and cutting the scratch (CR) of the conductive material (322) to form the first support structure (300).

[0067] As illustrated in FIGS. 13 and 16, each of the first dummy wires (320) of the semiconductor package (11) may extend in the vertical direction with a predetermined first inclination (D1). The first inclination (D1) may be an inclination that is inclined toward the stacking direction (first horizontal direction) of the step shape of the first semiconductor chips (100). The first dummy wires (320) may be inclined toward the direction in which the first top semiconductor chip (110) protrudes from the first semiconductor chips (100). For example, the first inclination (D1) may be within the range of 0 to 20 degrees.

[0068] As illustrated in FIGS. 14 and 17, each of the first dummy wires (320) of the semiconductor package (12) may extend in the vertical direction with a predetermined second inclination (D2). The second inclination (D2) may be an inclination that is inclined toward a direction opposite to the stacking direction of the step shape of the first semiconductor chips (100) (a second horizontal direction). The first dummy wires (320) may be inclined toward a direction opposite to the direction in which the first top semiconductor chip (110) protrudes from the first semiconductor chips (100). For example, the second inclination (D2) may be within the range of 0 to 20 degrees.

[0069] As illustrated in FIGS. 15 and 18, each of the first dummy wires (320) of the semiconductor package (13) may extend in the vertical direction with the preset inclinations. The first dummy wires (320) may be inclined toward a direction opposite to that of adjacent dummy wires. The first dummy wires (320) may be inclined to intersect with the adjacent dummy wires in a direction opposite to that of adjacent dummy wires. The first dummy wires (320) may be inclined with first and second inclinations (D1, D2). For example, the first and second inclinations (D1, D2) may be within the range of 0 to 20 degrees.

[0070] As illustrated in FIG. 19, when the first support structure (300a) extends vertically from the upper surface of the package substrate (20), the first support structure (300a) may have a first height tolerance (T1). When the first support structure (300b) extends in the vertical direction from the upper surface of the package substrate (20) with the aforementioned preset inclination (D1), the first support structure (300b) may have a second height tolerance (T2).

[0071] The first support structure (300) can be extended toward a target point (M) where the first top semiconductor chip (110) is placed. The closer the first and second height deviations (T1, T2) of the first support structures (300a, 300b) are to the target point (M), the more stably and efficiently the first support structure (300) can support the first top semiconductor chip (110).

[0072] In the process of the first support structure (300), the first support structure (300a) that is vertically extended may have a shorter predetermined length (L) from the target point (M) than the first support structure (300b) that has a predetermined slope. The first height deviation (T1) of the first support structure (300a) that is vertically extended may be greater than the second height deviation (T2) of the first support structure (300b) that has a predetermined slope (D1). The first support structure (300b) that has a predetermined slope (D1) can stably and efficiently support the first uppermost semiconductor chip (110) by utilizing a shorter height deviation than the first support structure (300a) that is vertically extended.

[0073] FIG. 20 is a cross-sectional view showing a semiconductor package including support structures supporting the lower surface of additional semiconductor chips according to exemplary embodiments. FIG. 21 is a cross-sectional view showing a semiconductor package including support structures supporting the upper semiconductor chip of additional semiconductor chips according to exemplary embodiments. The semiconductor package is substantially identical or similar to the semiconductor package described with reference to FIG. 1 through 3, except for the configuration of the additional semiconductor chips. Accordingly, identical components are denoted by the same reference numerals, and a repeated description of identical components is omitted.

[0074] Referring to FIGS. 20 and 21, each of the semiconductor packages (14, 15) may include a package substrate (20), a plurality of first semiconductor chips (100) disposed on the package substrate, a plurality of second semiconductor chips (500) disposed on the first semiconductor chips (100), conductive wires (200) for electrically connecting the first and second semiconductor chips (100, 500) to the package substrate (20), a plurality of first support structures (300), and a plurality of second support structures (600). Additionally, the semiconductor packages (14, 15) may further include a sealing member (400).

[0075] For example, five second semiconductor chips (500a, 500b, 500c, 500d, 510) may be attached to the first uppermost semiconductor chip (110) of the first semiconductor chips (100) using second adhesive members (520a, 520b, 520c, 520d, 520e). For example, the second adhesive members may include the adhesive film such as a direct adhesive film (DAF).

[0076] The second semiconductor chip (500) may have second chip pads (530) formed on an upper surface, that is, on the active surface. The second chip pads (530) may include an input / output terminal that performs a power pin function, an input / output terminal that performs a ground pin function, or an input / output terminal that performs a data pin function. The second chip pads (530) may be the rewiring pads. The second semiconductor chip (500) may include a rewiring layer on the top surface. The rewiring layer may include the second chip pads (530).

[0077] The second semiconductor chip (500) can be electrically connected to the package substrate (20) by conductive wires (200). For example, the second semiconductor chips can be mounted on the first semiconductor chips (100) by the wire bonding method. Specifically, the conductive wire (200) can electrically connect the second chip pad (530) of the second semiconductor chip (500) to the substrate pad (22) of the package substrate (20). For example, the conductive wire (200) may include a bonding wire. Accordingly, the second semiconductor chips (500) can be stacked on the first semiconductor chip (100) by the second adhesive members and electrically connected to the package substrate (20) by a plurality of conductive wires (200).

[0078] As illustrated in FIG. 20, at least one second semiconductor chip (500) may be positioned to protrude from one side of the first top semiconductor chip (110) on the first top semiconductor chip (110). The second semiconductor chip (500) may include a second overhang portion (OH2) protruding from the first semiconductor chips (100).

[0079] The second bonding pads (512) may be provided on the second overhang portion (OH2). For example, the length of the second overhang portion (OH2) may be within the range of 200 µm to 400 µm. In the process of connecting the second bonding pads (512) provided on the second overhang portion (OH2) by contacting the conductive wires (200), the second semiconductor chip (500) may receive a force in the vertical direction.

[0080] In exemplary embodiments, the second support structure (600) may be placed on the first semiconductor chip (100). The second support structure (600) may be placed between the first semiconductor chip (100) and the second semiconductor chip (500) to support the second semiconductor chip (500).

[0081] Specifically, the second support structure (600) may include at least one second dummy pad (610) disposed on the first semiconductor chip (100) and a second dummy wire (620) having one end joined to the second dummy pad (610) and supporting the second lower surface (500b) of the second semiconductor chip (500). The one end of the second dummy wire (620) may be joined to the upper surface of the first semiconductor chip (100). The other end of the second dummy wire (620) may extend upward from the one end and contact the lower part of the second overhang portion (OH2) of the second semiconductor chip (500). For example, the second dummy wire (620) may have an I-shaped form and support the second overhang portion.

[0082] For example, the diameter of the second dummy wire (620) may be within the range of 1.0 mm to 3.5 mm. The second dummy wire (620) may include copper (Cu), aluminum (Al), tungsten, nickel (Ni), molybdenum (Mo), gold (Au), silver (Ag), chromium (Cr), tin (Sn), and titanium (Ti).

[0083] As illustrated in FIG. 21, a plurality of second semiconductor chips (500) may be mounted on the first semiconductor chips (100). A plurality of second semiconductor chips (500) may be stacked in a stepped shape on the first semiconductor chips (100). The stepped shape may include a stepped shape inclined to one side. A plurality of second semiconductor chips (500) may be stacked in a second horizontal direction opposite to the first horizontal direction in which the first semiconductor chips (100) are stacked in the stepped shape.

[0084] A plurality of second semiconductor chips (500) may include a second upper semiconductor chip (510) spaced apart from any one of the first semiconductor chips (100) by a second height (H2). The second upper semiconductor chip (510) may have a second upper surface (500a) and a second lower surface (500b) opposite each other. The second lower surface (500b) of the second upper semiconductor chip (510) may be spaced apart from any one of the first semiconductor chips (100) by a second height (H2). The second upper semiconductor chip (510) may include a second overhang portion (OH2) protruding from the second semiconductor chips (500).

[0085] A plurality of second dummy pads (610) may be provided on the first semiconductor chip (100) at a position corresponding to the second bonding pads (512) of the second top semiconductor chip (510). A plurality of second dummy pads (610) may be arranged at any desired position on the upper surface of the first semiconductor chip (100). Additionally, each of the second dummy wires (620) connected to the plurality of second dummy pads (610) may have a second height (H2) selected according to the height difference between the upper surface of the first semiconductor chip (100) and the second overhang portion (OH2) of the second top semiconductor chip (510).

[0086] A plurality of second dummy wires (620) may each extend in the vertical direction from the second dummy pads (610). A plurality of second dummy wires (620) may extend in the vertical direction from the second dummy pads (610) at a position corresponding to the second bonding pads (512) of the second top semiconductor chip (510). The second dummy wires (620) may extend in the vertical direction during the process of connecting the second bonding pads (512) of the second top semiconductor chip (510) and the conductive wires (200) to support the second overhang portion (OH2) of the second top semiconductor chip (510).

[0087] As described above, the first support structure (300) can support the overhang portion (OH) of the first top semiconductor chip (110) by compensating for the height difference between the package substrate (20) and the first top semiconductor chip (110). Accordingly, by using the first support structures (300) formed during the wire bonding process, the bouncing phenomenon of the first top semiconductor chip (110) can be prevented, costs can be reduced, and productivity can be improved.

[0088] Although the present invention has been described above with reference to embodiments thereof, those skilled in the art will understand that various modifications and changes can be made to the invention without departing from the spirit and scope of the invention as described in the following claims. Explanation of the symbols

[0089] 10: Semiconductor package 20: Package substrate 22: Board pad 23: Contact pad 24: First insulating layer 26: Second insulating layer 28: External connection pad 30: External connection missing 40: Electronic device 100: First semiconductor chip 110: 1st topmost semiconductor chip 112: 1st bonding pad 120: First adhesive members 130: First chip pad 200: Conducting wire 300: First support structure 310: 1st Dummy Pad 320: 1st Dummy Wire 400: Sealing member 500: Second semiconductor chip 510: Second uppermost semiconductor chip 512: Second bonding pad 520: Second adhesive members 530: Second chip pad 600: Second support structure 610: Second dummy pad 620: 2nd Dummy Wire

Claims

Claim 1 A semiconductor package comprising: a package substrate; a plurality of first semiconductor chips having a first top semiconductor chip having a first height from the package substrate and sequentially stacked in a stepped shape on the upper surface of the package substrate; conductive wires electrically connecting the chip pads of the first semiconductor chips to the substrate pads of the package substrate; and a plurality of first support structures each extending from the upper surface of the package substrate to have a height equal to the first height and inclined at a predetermined inclination from a vertical direction, and arranged along an overhang portion of the first top semiconductor chip protruding from the first semiconductor chips below the first top semiconductor chip to support the overhang portion, wherein each of the first support structures has one end joined to the upper surface of the package substrate and the other end opposite to the one end contacts the lower part of the overhang portion of the first top semiconductor chip. Claim 2 A semiconductor package according to claim 1, wherein at least some of the chip pads of the first topmost semiconductor chip are provided on the upper surface of the overhang region, and each of the first support structures has its other end supporting the lower surface of the first topmost semiconductor chip in the overhang region. Claim 3 A semiconductor package according to claim 1, wherein each of the first support structures comprises: a wire joint disposed on the package substrate; and a dummy wire having one end joined to the wire joint and the other end opposite to the one end in contact with the lower part of the overhang portion. Claim 4 A semiconductor package according to claim 1, further comprising: at least one second semiconductor chip disposed to protrude from one side of the first top semiconductor chip on the first top semiconductor chip; and a plurality of second support structures each extending in the vertical direction from the upper surface of any one of the first semiconductor chips and arranged along a second overhang region of the at least one second semiconductor chip to support the second overhang region. Claim 5 A semiconductor package according to claim 1, further comprising: a plurality of second semiconductor chips having a second top semiconductor chip having a second height from the upper surface of any one selected of the first semiconductor chips, stacked in a reverse step shape opposite to the stacking direction of the step shape; and a plurality of third support structures each extending in the vertical direction to have a height equal to the second height from the upper surface of the selected first semiconductor chip, and arranged along a third overhang portion of the second top semiconductor chip protruding from the second semiconductor chips below the second top semiconductor chip to support the third overhang portion of the second top semiconductor chip. Claim 6 A semiconductor package according to claim 1, wherein the preset slope is within the range of 0 to 20 degrees. Claim 7 In claim 6, each of the first support structures is a semiconductor package inclined along the stepped stacking direction. Claim 8 In claim 6, each of the first support structures is a semiconductor package inclined along a direction opposite to the stacking direction of the stepped shape. Claim 9 Forming support structures such that they each have a predetermined height in a vertical direction from the upper surface of a package substrate and extend at a predetermined inclination from the vertical direction, with each end thereof bonded to the upper surface of the package substrate; stacking a plurality of semiconductor chips in a stepped shape up to a height equal to the predetermined height of the support structures; stacking an uppermost semiconductor chip on the support structures and the semiconductor chips; and connecting a conductive wire to the uppermost semiconductor chip, wherein forming the support structures includes extending a conductive material ejected from a capillary from the package substrate to have a predetermined length longer than the predetermined height and contacting a contact pad; and forming a scratch portion on the conductive material while the conductive material is not attached to the contact pad. A method for manufacturing a semiconductor package comprising moving the capillary to be inclined at a predetermined inclination from the above vertical direction to erect the conductive material and cutting the scratch portion of the conductive material, wherein when stacking the uppermost semiconductor chip on the support structures, each of the support structures has a other end opposite to the one end contacting the lower part of the overhang portion of the uppermost semiconductor chip protruding from the semiconductor chips below the uppermost semiconductor chip. Claim 10 A method for manufacturing a semiconductor package according to claim 9, wherein the cutting of the scratch portion is performed by cutting the scratch portion while the conductive material is tilted at a preset inclination from the vertical direction.

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