Memory device and method for manufacturing the same

Abstract

According to embodiments, a memory element is provided comprising: a substrate; and a structure provided on the substrate; wherein the structure comprises: a bit line formed by stacking on the substrate; and a word line formed perpendicular to the substrate and penetrating the bit line.

Description

Technology Field

[0001] The embodiments relate to a memory device and a method for manufacturing a memory device. For example, the embodiments apply to a three-dimensional memory device and a method for manufacturing a three-dimensional memory device. Background Technology

[0002] A semiconductor is a material that conducts electric current like a conductor only under specific conditions. With recent technological advancements leading to the miniaturization, high integration, and increased functionality of semiconductor devices, interest in semiconductors is growing across the entire electronics industry.

[0003] These semiconductors include memory semiconductors used for storing information and non-memory semiconductors intended for information processing. In the case of a memory semiconductor, a single memory element includes a single transistor and a single capacitor. Additionally, the memory element includes a Word Line (WL) connected to the gate of the transistor and connected to the transistor, and a Bit Line (BL) connected to the source and / or drain and accessing the capacitor. For example, the memory element includes one or more BLs, WLs, and transistors connected to the BLs and WLs that are perpendicular to each other.

[0004] Meanwhile, with recent technological advancements, research on the miniaturization of memory semiconductors is underway. Accordingly, 3D memory semiconductors are emerging alongside 2D memory semiconductors with structures such as the one described above. 3D memory semiconductors include methods of vertically aligning the BL or vertically aligning the WL. The problem to be solved

[0005] The embodiments provide a memory device implemented according to 3D VSCAT (Vertical Stacked Cell Array Transistor).

[0006] The embodiments provide a method for manufacturing a memory device having a 3D structure.

[0007] The problem to be solved through the embodiments is not limited to the above-described details and includes all matters that a person skilled in the art can consider through the details described in the embodiments. means of solving the problem

[0008] According to embodiments, a memory element is provided comprising: a substrate; and a structure provided on the substrate; wherein the structure comprises: a bit line formed by stacking on the substrate; and a word line formed perpendicular to the substrate and penetrating the bit line.

[0009] According to embodiments, the structure provides a memory device formed by alternately stacking one or more insulating layers and one or more active layers, and then etching at least a portion of them into a stepped shape.

[0010] According to embodiments, a memory element is provided comprising: one or more first holes formed perpendicularly on a substrate to support an insulating layer and formed through the structure; and one or more second holes formed perpendicularly on a substrate to form a word line and formed through the structure.

[0011] According to embodiments, the second hole is formed in a 'C' shape on the upper surface of the structure, such that one side of the insulating layer is closed and the other side of the insulating layer facing the one side is open, thereby providing a memory element.

[0012] According to the embodiments, the second hole is formed on the upper surface of the structure such that one side of the insulating layer has a thickness greater than or equal to a predetermined thickness, thereby providing a memory element.

[0013] According to embodiments, a method for manufacturing a memory device is provided, comprising the steps of: forming a bitline step from a mold located on a substrate; forming a support on the bitline step; and performing etching on the bitline step with the support formed to form a structure.

[0014] According to embodiments, a method for manufacturing a memory device is provided, comprising the step of forming a bitline step from a mold, the step of forming a mold by alternately stacking one or more insulating layers and one or more active layers; and the step of forming a bitline step by removing at least a portion of the mold in a step shape.

[0015] According to embodiments, a method for manufacturing a memory device is provided, comprising the step of forming a support on a bitline step, the step of forming one or more first holes in a direction perpendicular to the substrate; and the step of filling the holes with a first filling material.

[0016] According to the embodiments, a method for manufacturing a memory device is provided in which, in the case where there are one or more first holes, the spacing between the plurality of first holes is formed in proportion to the thickness of the insulating layer.

[0017] According to embodiments, the step of forming a structure by performing etching on a bitline step formed with a support comprises the step of forming a second hole on the bitline step in a direction perpendicular to the substrate; wherein the second hole is formed in a 'C' shape on the upper surface of the bitline step, with one side closed and the other side facing the one side open. A method for manufacturing a memory device is provided.

[0018] According to embodiments, a method for manufacturing a memory device is provided, wherein the second hole is formed such that the thickness of one side of the closed portion of the second hole is greater than or equal to a predetermined thickness.

[0019] According to embodiments, the step of forming a structure by performing etching on a bitline step in which a zone is formed further comprises the step of forming a word line by filling a second filler material into a second hole; thereby providing a method for manufacturing a memory device.

[0020] According to embodiments, a method for manufacturing a memory device comprises the steps of: performing channel filling on a structure; etching at least a portion of the portion where channel filling has been performed; and performing bitline filling and wordline filling on the structure where at least a portion has been etched.

[0021] According to the embodiments, a method for manufacturing a memory device is provided, wherein etching is performed on a portion where channel filling is performed until a word line formed in the structure is exposed. Effects of the invention

[0022] The embodiments can implement a 3D VSCAT (Vertical Stacked Cell Array Transistor).

[0023] The embodiments can propose a general-purpose structure applicable to various channels. For example, various channels include poly-Si, IGZO (Indium Gallium Zink Oxide), 2D, etc.

[0024] The effects obtainable through the embodiments are not limited to those described above and include various effects that a person skilled in the art can derive from the embodiments. Brief explanation of the drawing

[0025] In the following, technical features of various embodiments are described together with the drawings below to further aid in the explanation of the embodiments. FIG. 1 is a schematic diagram illustrating the schematic structure of a memory device according to embodiments. FIG. 2 is a flowchart illustrating a method for manufacturing a memory device according to embodiments. Figure 3 is a flowchart that explains s101 described in Figure 2 in more detail. Figure 4 is a plan view illustrating s201 described in Figure 3. Figure 5 is a plan view illustrating s201 described in Figure 3. Figure 6 is a plan view illustrating s202 described in Figure 3. Figure 7 is a plan view illustrating s203 described in Figure 3. FIG. 8 is a plan view and perspective view illustrating s203 described in FIG. 3. FIG. 9 is a plan view and a perspective view illustrating s102 described in FIG. 3. FIG. 10 is a plan view and a perspective view illustrating s102 described in FIG. 2. FIG. 11 is a perspective view illustrating s103 described in FIG. 2. FIG. 12 is a perspective view illustrating s104 described in FIG. 2. FIG. 13 is a perspective view illustrating s104 described in FIG. 2. FIG. 14 is a perspective view illustrating s104 described in FIG. 2. FIG. 15 is a plan view and perspective view illustrating s104 described in FIG. 2. FIG. 16 is a plan view and perspective view illustrating s104 described in FIG. 2. FIG. 17 is a plan view and perspective view illustrating s104 described in FIG. 2. Specific details for implementing the invention

[0026] Hereinafter, specific embodiments of the present invention will be described with reference to the drawings. The following detailed description is provided to facilitate a comprehensive understanding of the methods, apparatuses, and / or systems described herein. However, this is merely illustrative and the present invention is not limited thereto.

[0027] In describing the embodiments of the present invention, detailed descriptions of known technologies related to the present invention are omitted if it is determined that such detailed descriptions may unnecessarily obscure the essence of the present invention. Furthermore, the terms described below are defined in consideration of their functions within the present invention, and these may vary depending on the intentions or practices of the user or operator. Therefore, such definitions should be based on the content throughout this specification. Terms used in the detailed description are intended merely to describe the embodiments of the present invention and should not be limiting in any way. Unless explicitly stated otherwise, expressions in the singular form include the meaning of the plural form. In this description, expressions such as "include" or "comprise" are intended to refer to certain characteristics, numbers, steps, actions, elements, parts thereof, or combinations thereof, and should not be interpreted to exclude the existence or possibility of one or more other characteristics, numbers, steps, actions, elements, parts thereof, or combinations thereof other than those described.

[0028] Additionally, terms such as "first," "second," etc., may be used to describe various components, but said components should not be limited by said terms. These terms may be used for the purpose of distinguishing one component from another. For example, without departing from the scope of the present invention, the first component may be named the second component, and similarly, the second component may be named the first component.

[0029] In addition, the terms "part," "unit," or "module" in this specification may refer to a functional and structural combination of hardware for carrying out the technical concept of the present invention and software for driving said hardware. For example, the "part," "unit," or "module" may refer to a logical unit of a specific code and a hardware resource for executing said code, and does not necessarily refer to physically connected code or a single type of hardware. Furthermore, the terms "part," "unit," or "module" may be used interchangeably as appropriate.

[0031] FIG. 1 is a schematic diagram illustrating the schematic structure of a memory device according to embodiments.

[0032] In FIG. 1, 100 represents a step describing the process of manufacturing a memory element (100) or a memory element (100) according to the embodiments. Also, in FIG. 1, 23 represents a support of the memory element (100). In FIG. 1, BC represents a bitline cut. In FIG. 1, WC represents a wordline cut. Each symbol is described in the following drawings.

[0033] Such a memory element (100) (or, memory semiconductor element, hereinafter referred to as a memory element) includes a bit line and a word line. For example, the memory element (100) is formed by stacking bit lines. At this time, the stacked bit lines are required to be connected to wiring for electrical connection with other circuits. Accordingly, the memory element (100) is formed in a stepped shape as shown in FIG. 1 in order to connect wiring to at least some of the stacked bit lines.

[0034] By means of such a structure, the memory device (100) according to the embodiments proposes a structure of a three-dimensional memory device. For example, the embodiments can implement a 3D VSCAT (Vertical Stacked Cell Array Transistor). Through this, the embodiments can provide a general-purpose structure and / or process solution applicable to the channel. For example, the embodiments are applicable to channels such as poly-Si, IGZO, and 2D.

[0035] The manufacturing method of such a memory device (100) and the memory device (100) formed by such a manufacturing method of such a memory device will be described in detail through FIGS. 2 to 20 below.

[0037] FIG. 2 is a flowchart illustrating a method for manufacturing a memory device according to embodiments.

[0038] FIG. 2 describes the overall process of manufacturing a memory device (100) according to embodiments.

[0039] As illustrated in FIG. 2, the method for manufacturing a memory device (100) according to the embodiments includes the step (s101) of forming a structure. s101 is described in more detail through FIG. 3 to 6.

[0040] As illustrated in FIG. 2, the method for manufacturing a memory device (100) according to the embodiments includes the step (s102) of performing channel fill in a structure. s102 is described in more detail through FIG. 9 and FIG. 10.

[0041] As illustrated in FIG. 2, the method for manufacturing a memory device (100) according to the embodiments includes the step (s103) of etching at least a portion of the part where channel filling has been performed. s103 is described in more detail with reference to FIG. 11.

[0042] As illustrated in FIG. 2, a method for manufacturing a memory device (100) according to embodiments includes a step (s104) of performing bit line filling (BL fill) and / or word line filling (WL fill). s104 is described in more detail through FIG. 12 to 18.

[0043] Meanwhile, in FIG. 2, steps s101 to s104 are described for manufacturing a memory device (100) according to the embodiments. However, the embodiments include omitting all or part of steps s102 to s104 and / or adding new steps between s101 to s104 or before and after steps s101 to s104. That is, the method for manufacturing a memory device (100) according to the embodiments can be applied to any method for manufacturing a memory device (100) that includes the step according to s101.

[0045] Figure 3 is a flowchart that explains s101 described in Figure 2 in more detail.

[0046] As described in FIG. 2, the method for manufacturing a memory device (100) according to the embodiments includes the step (s101) of forming a structure.

[0047] As illustrated in FIG. 3, the method for manufacturing a memory device (100) according to the embodiments includes the step (s201) ​​of forming a bitline step from a mold. s201 is described in more detail through FIG. 4 and FIG. 5.

[0048] As illustrated in FIG. 3, the method for manufacturing a memory device (100) according to the embodiments includes the step (s202) of forming a support on a bitline step. s201 is explained in more detail through FIG. 6.

[0049] As illustrated in FIG. 3, the method for manufacturing a memory device (100) according to the embodiments includes the step (s203) of forming a structure through etching. s201 is described in more detail through FIG. 7 and FIG. 8.

[0051] Figure 4 is a plan view illustrating s201 described in Figure 3.

[0052] As described through s201 in FIG. 3, the method for manufacturing a memory element (100) according to the embodiments includes the step (s201) ​​of forming a bitline step from a mold. FIG. 4 describes a method for creating a mold (10) for creating a bitline step. Meanwhile, FIG. 4 and FIG. 5 to 7 below describe a method for creating a memory element (100) in a cross-sectional direction in which the memory element (100) is cut along A-A' shown in FIG. 1.

[0053] A mold (10) according to the embodiments comprises one or more insulating layers (11) and one or more active layers (12). The mold (10) is formed by alternately stacking the insulating layers (11) and the active layers (12). For example, the mold (10) includes a structure in which one active layer (12) is formed on one insulating layer (11), and another insulating layer (11) is formed on the active layer (12).

[0054] At this time, the insulating layer (11) electrically separates the layers in the mold (10). For example, the insulating layer (11) electrically separates the active layer (12a) located below the insulating layer (11) and the active layer (12b) located above the insulating layer (11). The insulating layer (11) includes, for example, an oxide. For example, the insulating layer (11) includes silicon oxide.

[0055] At this time, the active layer (12) acts as a channel material that performs transistor operation in the memory device (100). Alternatively, the active layer (12) may be etched in whole or in part to provide a space for a new material to enter. The active layer (12) includes any material that has a selectivity ratio with the insulating layer (11). Alternatively, if a different sacrificial film is used in the process of manufacturing the mold (10) or the memory device (100), the active layer (12) includes any material that has a selectivity ratio with such sacrificial film. The active layer (12) includes, for example, poly-Si, nitride, and silicon nitride.

[0056] Although not illustrated in FIG. 4, the memory device (100) according to the embodiments may further include a substrate. The substrate is, for example, a semiconductor substrate and includes, for example, silicon (Si), gallium arsenide (GaAs), etc. A mold (10) may be formed on the substrate. For example, the mold (10) is formed by alternately stacking an insulating layer (11) and an active layer (12) on the substrate. At this time, although not illustrated in FIG. 4, a circuit may be formed between the substrate and the mold (10) to electrically connect at least a portion of the substrate and the mold (10).

[0057] Through such a process, the embodiments provide a method for creating a mold (10) for forming a bitline step.

[0059] Figure 5 is a plan view illustrating s201 described in Figure 3.

[0060] As described through s201 in FIG. 3, the method for manufacturing a memory device (100) according to the embodiments includes the step (s201) ​​of forming a bitline step from a mold. A method for forming a bitline step (20) from the mold (10) described in FIG. 4 is explained through FIG. 5.

[0061] The embodiments remove at least a portion of the mold (10) so that the mold (10) is formed into a stepped shape. For example, the mold (10) is formed into a stepped shape through an etching or trimming process. At this time, the stepped shape may be formed in a V shape in the middle of the mold (10), for example, as shown in FIG. 5. The mold (10) includes a plurality of layers (e.g., 21). In FIG. 5, each layer (e.g., 21) is formed at an angle, but each layer (e.g., 21) may be formed at an angle of 90 degrees.

[0062] At this time, one layer (e.g., 21) includes one insulating layer (11) and one active layer (12). However, one layer may include one or more insulating layers and one or more active layers. At this time, each layer (e.g., 21) serves as one bit line. For example, each bit line is connected to the outside by wiring through a stepped shape. Through this, the memory element (100) according to the embodiments provides a method for individually driving each bit line (e.g., 21) formed in a stepped shape.

[0063] Meanwhile, the embodiments fill an insulating material (22) into at least a portion of the removed mold (10). For example, the insulating material (22) is filled into the portion of the mold (10) formed in a stepped shape that has been removed through an etching or trimming process. For example, the insulating material (22) is filled through a chemical vapor deposition (CVD). At this time, the insulating material (22) is, for example, an interlayer dielectric (ILD) and includes, for example, a TEOS (Tetra Ethyl Ortho Silicate) material.

[0064] In this way, the embodiments form a bitline step (20) by filling an insulating material (22) into a step-shaped mold (10). The bitline step (20) can be flattened through a chemical mechanical polishing (CMP) process. In this way, the embodiments form a stepline step (20) without steps. Through this, the embodiments allow subsequent processes, such as photolithography, to proceed smoothly.

[0065] Through such a method, the memory device (22) according to the embodiments is insulated between bit lines (22) through the insulating material (22). In addition, the embodiments provide a method to facilitate subsequent processes through the insulating material (22).

[0067] Figure 6 is a plan view illustrating s202 described in Figure 3.

[0068] As described through s201 in FIG. 3, the method for manufacturing a memory device (100) according to the embodiments includes the step (s202) of forming a support on a bitline step. A bitline step (20) was formed through FIG. 4 and FIG. 5. At this time, for example, all or part of the active layer (12) may be removed in a subsequent process. In this case, as the active layer (12) is removed, at least part of the bitline step (20) may collapse. FIG. 6 describes a method of forming a support (23) within the bitline step (20) to prevent the bitline step (20) from collapsing in this way.

[0069] The support member (23) passes through at least a portion (e.g., H1) of the bitline stairs (20). Accordingly, the width of the stairs formed within the bitline stairs (20) can be narrowed.

[0070] For example, at least a portion of the bitline stairs (20) (e.g., H1, for convenience, hereinafter referred to as the first hole (H1). However, the first hole (H1) actually refers not only to the concept of a hole or passage being formed within the bitline stairs (20), but also to the space formed as the support (23) passes through the bitline stairs (20) as described in FIG. 6) is formed between the bitline cut (BC) and the cut (CC) for the cell cap, as formed in FIG. 1.

[0071] At this time, one or more supports (23) are formed in a direction perpendicular to the bit line (21). The direction perpendicular to the bit line (21) is, for example, the direction perpendicular to the substrate described in FIG. 4. Or, for example, the direction perpendicular to the bit line (21) is the direction perpendicular to the insulating layer (11) and / or the active layer (12). FIG. 6 illustrates an example in which six first holes are formed for convenience of explanation, but the number of first holes (H1) is not limited thereto. The first holes (H1) are formed, for example, by performing dry etching on the bit line steps (20).

[0072] The support member (23) is formed by a first filler. The first filler includes, for example, an oxide filler, a nitride filler, etc. In the case where there are multiple first holes (H1), the spacing between the first holes (H1) is proportional to the thickness of the insulating layer (11). For example, if the insulating layer (11) is thick, the spacing between the first holes (H1) may be longer, and accordingly, the number of first holes (H1) formed in the bitline step (20) may be reduced.

[0073] The support member (23) may be formed with a round cross-section when viewed from the top surface of the memory element (100), for example, as shown in the perspective view of FIG. 1. However, the cross-sectional shape of the support member (23) is not limited to this and may be formed in any shape that helps with the convenience of the manufacturing process or the improvement of functionality.

[0074] Through such a method, the memory device (22) according to the embodiments provides a method to prevent the bitline step (20) from collapsing even when, for example, all or part of the active layer (12) is deleted in a subsequent process.

[0076] Figure 7 is a plan view illustrating s203 described in Figure 3.

[0077] FIG. 8 is a plan view and perspective view illustrating s203 described in FIG. 3.

[0078] As described through s203 in FIG. 3, the method for manufacturing a memory device (100) according to the embodiments includes the step (s203) of forming a structure through etching. FIG. 8(a) is a cross-sectional view of B-B' shown in FIG. 7. FIG. 8(b) is a perspective view of the structure (30) shown in FIG. 8(a). That is, FIG. 8(a) is a front or top view of FIG. 8(b) viewed from the direction of arrow G. FIG. 8(c) is a perspective view showing an example in which a second filler is filled with FIG. 8(b). Meanwhile, in FIG. 8, S represents a substrate (e.g., the substrate described in FIG. 4).

[0079] The memory element (100) has a three-dimensional structure. Accordingly, the memory element (100) requires electrical isolation between bit lines and / or between word lines. Therefore, to achieve electrical isolation, the memory element (100) performs a word line cut (see WL in FIG. 1). That is, a word line etching process is performed on the bit line step (20) in a direction perpendicular to the bit line. Word line etching includes, for example, dry etching. Through this etching process, a second hole (H2) is formed in the bit line step (20). Through this, a structure (30) is formed. FIG. 7 illustrates an example in which two second holes (H2) are formed, but the number of second holes (H2) formed in the memory element (100) is not limited thereto.

[0080] At this time, as illustrated in FIG. 8(b), the second hole (H2) included in the structure (30) has a shape in which one side is closed and the other side is open when viewed from the top surface. For example, the second hole (H2) is formed on one side of the structure (30) while leaving a predetermined thickness (d). Due to the closure of one side and the opening of the other side, the second hole (H2) has a "C" shaped circumference when viewed from the top surface, for example.

[0081] In this way, the memory device (100) according to the embodiments leaves a width for the bit line to pass through. By doing so, the embodiments provide a method for connecting bit lines in a subsequent process.

[0082] A second filler is filled into one or more second holes (H2) formed in the structure (30). The second filler includes, for example, an oxide filler, a nitride filler, etc. At this time, the second filler is filled into the second holes (H2) through, for example, a Shallow Trench Isolation (STI) process. The second filler filled into the second holes (H2) becomes a word line (31). The word line (31) is formed, for example, as shown in (c) of FIG. 8.

[0083] Through this, the memory device (100) according to the embodiments provides a method for electrically separating word lines through a subsequent process.

[0085] FIG. 9 is a plan view and a perspective view illustrating s102 described in FIG. 3.

[0086] As described in s102 of FIG. 2, the method for manufacturing a memory device (100) according to the embodiments includes the step (s102) of performing channel fill in a structure.

[0087] FIG. 9(a) is a plan view showing the step in which channel filling is performed for FIG. 8(a). FIG. 8(b) is a perspective view showing the step in which channel filling is performed for FIG. 8(b).

[0088] In order to perform channel fill, etching is first performed on the structure (30) described in FIGS. 7 and 8. For example, as shown in FIG. 9, etching is performed on the area where the word line (31) is not formed in the place where the second filler is filled.

[0089] First, the structure (30) places a mask on the structure (30) based on the area to be etched. In the structure (30), etching is selectively performed based on the mask position.

[0090] For example, etching is performed on the second filler located on both sides of the structure (30). This removes the second filler formed in the area not used as a word line (31). As the area where the second filler of the structure (30) has been removed, for example, a third filler (32) is deposited on both sides of the structure (30). At this time, the third filler (32) is, for example, SiN, as a nitride. However, the third filler (32) is not limited thereto, and the third filler (32) may be any material having a different etch selectivity than the second filler. The third filler (32) is deposited through a process such as CVD or ALD.

[0091] Meanwhile, etching is performed on a second filler located in the center of the structure (30), for example. The center area is an area that is not used as, for example, a word line (24), and is a closed area for connecting bit lines. Through this, an opening (33) is formed in the structure (30) in a direction perpendicular to the substrate (S). Additionally, the structure (30) removes at least a portion of the active layer (12) formed perpendicular to the opening (33) using a photo process or wet etching. Through this, a vertical opening (34) is formed in the structure (30).

[0092] Fig. 9 describes a method for providing a space where channel filling can be performed. Fig. 10 below describes the process of performing channel filling in such a space.

[0094] FIG. 10 is a perspective view illustrating s102 described in FIG. 2.

[0095] As described in s102 of FIG. 2, the method for manufacturing a memory device (100) according to the embodiments includes the step (s102) of performing channel fill in a structure.

[0096] An oxide film (35) is formed on the structure (30) through an oxidation process. At this time, the oxide film (35) is deposited, for example, via ALD or CVD. For example, the oxide film (35) is an oxide film formed as the active layer (12) is oxidized by heat. At this time, the oxide film (35) is formed at the boundary between the vertical opening (34) and the active layer (12). Through this, the embodiments are configured to function as a stopping layer in subsequent processes.

[0097] A channel (36) is further formed in the structure (30). The channel (36) is formed, for example, by filling a vertical opening (34). The channel (36) comprises, for example, Poly Si or IGZO. For example, if the channel (36) comprises Poly-Si, the channel (36) is formed within the vertical opening (34) via CVD or Atomic Layer Deposition (ALD). Or, for example, if the channel (36) comprises IGZO, the channel (36) is formed within the vertical opening (34) via ALD. Through such channel filling, the embodiments provide a method for forming a channel (36) that functions, for example, as a channel of a transistor of a memory device (100).

[0099] FIG. 11 is a perspective view illustrating s103 described in FIG. 2.

[0100] As described in s103 of FIG. 2, the method for manufacturing a memory device (100) according to the embodiments includes the step (s103) of etching at least a portion of the portion where channel filling has been performed. FIG. 11 (a) is a perspective view illustrating s103, and FIG. 11 (b) is a perspective view showing an enlarged portion of FIG. 11 (a).

[0101] FIGS. 9 and 10 describe a method for forming a channel (36) in a vertical opening (34) formed in a structure (30). However, in this case, there is a problem of electrical connection between the cells included in the memory element (100). Therefore, FIG. 11 describes a method for electrically insulating the cells from each other.

[0102] At least a portion of the channel (36) is etched. This forms a third hole (H3) in the structure (30). The third hole (H3) is formed, for example, by wet etching or trimming. At this time, the second filler formed by the word line (31) is exposed through the third hole (H3). That is, the third hole (H3) is etched until the second filler is exposed. At this time, the direction in which the third hole (H3) is etched is the same or similar to the direction in which the vertical opening (34) is formed.

[0103] Through such a method, the memory device (100) according to the embodiments achieves electrical insulation between cells. For example, according to a subsequent process, the memory device (100) includes a first cell (c1) and a second cell (c2). At this time, the first cell (c1) and the second cell (c2) are electrically separated from each other by a third hole (H3).

[0105] FIG. 12 is a perspective view illustrating s104 described in FIG. 2.

[0106] As described in s104 of FIG. 2, the method for manufacturing a memory device (100) according to the embodiments includes the step (s104) of performing bit line filling (BL fill) and / or word line filling (WL fill).

[0107] To perform bitline filling and / or wordline filling, a drain and / or source are first formed for the structure (30). At this time, the drain and / or source has a higher concentration of dopant than the channel (36). For example, if the channel (36) uses a low-doped material such as Poly-Si, the drain and / or source uses a high-doped material. Meanwhile, for example, if the channel (36) is IGZO, a separate structure (30) does not need to have a drain and / or source formed. A method for creating a drain is explained through FIG. 12.

[0108] In the structure (30), an oxide film (35) is formed on one side of the channel (36), and an insulating layer (11) is formed on the upper or lower surface of the channel (36). Additionally, a drain (37) is formed on the other side of the channel (36), which is the surface facing the oxide film (35). To this end, metal wiring is provided on the other side of the structure (30). The metal wiring performs inter-cell connections within the memory element (100). The metal wiring is provided on the other side of the structure (30) by a deposition method such as CVD or ALD. The metal wiring is formed so as not to protrude outward beyond the insulating layer (11) through a trimming process such as wet etching. Accordingly, for example, as shown in FIG. 12, the drain (37) is formed on the other side of the channel (36) and is provided in a shape that is concavely inserted between the insulating layers (11).

[0109] Meanwhile, for the convenience of subsequent processes, the embodiments fill the empty space where the drain (37) is not formed with a fourth filler (38). The fourth filler (38) is, for example, nitride, for example, SiN. The fourth filler (38) is produced by a deposition method, for example, CVD or ALD, to protect the drain (37) from the empty space of the structure (30).

[0110] Through this, the embodiments provide a method for forming a drain (37) and protecting the drain (37) during the process.

[0112] FIG. 13 is a perspective view illustrating s104 described in FIG. 2.

[0113] As described in s104 of FIG. 2, the method for manufacturing a memory element (100) according to the embodiments includes the step (s104) of performing bit line filling (BL fill) and / or word line filling (WL fill). FIG. 13 describes a method for creating a source (39) within the memory element (100).

[0114] First, in order to form a cell capacitor included in the memory element (100) according to the embodiments, a third filling material (32) formed on both sides of the structure (30) is removed. For example, the third filling material (32) is removed by wet etching. Accordingly, empty spaces (32') are formed on both sides of the structure (30).

[0115] In addition, to form a source included in the memory element (100) according to the embodiments, all or part of the active layer (12) formed in the structure (30) is removed. For example, the active layer (12) is removed through trimming, such as wet etching, in the direction toward the oxide film (35) from the empty space (32').

[0116] In addition, to form a source included in the memory element (100) according to the embodiments, the oxide film (35) formed on the structure (30) is removed. For example, the oxide film (35) is removed by an HF solution.

[0117] The embodiments provide metal wiring on one side of the structure (30) to form a source. The metal wiring is provided on one side of the structure (30) by a deposition method such as, for example, CVD or ALD. The metal wiring is formed so as not to protrude outward from the insulating layer (11) through a trimming process such as, for example, wet etching. Accordingly, for example, as shown in FIG. 12, the source (39) is formed on one side of the channel (36) and is provided in a shape that is concavely inserted between the insulating layers (11). Accordingly, the channel (36) is formed such that the source (39) is located on one side and the drain (37) is located on the other side.

[0118] Additionally, the embodiments deposit a fifth filler from the empty space (32') toward the source (39) to form a capacitor (41). The fifth filler is deposited on the structure (30) through a deposition process, such as ALD, for example. The fifth filler includes, for example, TiN or HZO. Accordingly, a channel (36) is formed on one side of the source (39), and a capacitor (41) is formed on the other side of the source (39). Additionally, the capacitor (41) is formed by being separated into layers by an insulating layer (11).

[0119] Through such a method, embodiments provide a method for forming a capacitor and / or source in a memory element (100).

[0121] FIG. 14 is a perspective view illustrating s104 described in FIG. 2.

[0122] As described in s104 of FIG. 2, the method for manufacturing a memory element (100) according to the embodiments includes the step (s104) of performing bitline filling (BL fill) and / or wordline filling (WL fill). FIG. 14 describes bitline filling that creates bitline wiring (43) electrically connecting the drain (37) and the bitline (21).

[0123] First, the embodiments form a sixth filler (42) in the empty space (32'). The sixth filler (42) is deposited through a deposition method, for example, CVD or ALD. The sixth filler (42) includes, for example, a metal such as W, Mo, Ru, or poly-Si. The sixth filler forms, for example, a cap contact. That is, the sixth filler (42) forms, for example, a cell cap line in the memory element (100). Through this, both sides of the memory element (100) are also electrically connected to the outside.

[0124] The embodiments perform bitline opening. For example, the embodiments remove the fourth filler (38) to create a space where bitline wiring (43) is created. The fourth filler (38) is removed, for example, by wet etching. Accordingly, the structure (30) includes an empty space (38') from which the filler (38) has been removed.

[0125] The embodiments form bitline wiring (43) on the structure (30). The bitline wiring (43) is formed on at least a portion of the empty space (38'). The bitline wiring (43) is formed to electrically connect the drain (37) and the bitline (21). For example, the bitline wiring (43) is deposited through a deposition process such as CVD or ALD.

[0126] Thus, the embodiments provide a method for forming cell cap lines and bit line wiring. Through this, the memory device (100) includes a structure in which the bit line and the drain are electrically connected.

[0128] FIG. 15 is a plan view and perspective view illustrating s104 described in FIG. 2.

[0129] As described in s104 of FIG. 2, the method for manufacturing a memory device (100) according to the embodiments includes the step (s104) of performing bit line filling (BL fill) and / or word line filling (WL fill). FIG. 15 describes a method for forming a gate electrode. FIG. 15 (a) is a plan view of a structure, and FIG. 15 (b) is a perspective view of a structure.

[0130] The embodiments provide a space to be filled with wordlines in order to perform wordline filling. To do this, at least a portion of the insulating layer (11) is removed from the structure (30). This creates a void space (11') in the structure (30). At this time, the void space (11') is formed, for example, in at least a portion between the channels (36). At least a portion of the insulating layer (11) is selectively removed by a mask.

[0131] Additionally, the embodiments perform an opening operation to connect a word line (31) from the structure (30) to the upper and lower parts of the structure (30). At this time, the opening operation and the removal of at least a portion of the insulating film (11) are performed simultaneously or sequentially. At this time, the area opened in the structure (30) according to the opening operation is narrower than the area where the above-described channel (36) is formed.

[0132] At this time, a space is provided for word line filling, and an upper film (40) is formed on the upper part of the structure (30) to perform the opening operation. The upper film (40) includes, for example, poly-Si. In the embodiments, after forming the upper film (40) on the structure (30), at least a portion of the insulating layer (11) is removed through trimming. Meanwhile, the process of forming the upper film (40) in this manner may be omitted. That is, the embodiments are not limited to using the upper film (40) and any method can be applied as long as at least a portion of the insulating layer (11) is appropriately removed from the structure (30).

[0134] FIG. 16 is a plan view and perspective view illustrating s104 described in FIG. 2.

[0135] As described in s104 of FIG. 2, the method for manufacturing a memory element (100) according to the embodiments includes the step (s104) of performing bit line filling (BL fill) and / or word line filling (WL fill). FIG. 16 describes a method for performing word line filling following the processes performed in FIG. 15. FIG. 16 (a) is a plan view of a structure, and FIG. 16 (b) is a perspective view of a structure. Meanwhile, FIG. 16 (b) illustrates an example in which the eighth filling is omitted to explain the eighth filling filled in the empty space (38').

[0136] The embodiments fill the structure (30) with a seventh filler (44). The seventh filler (44) is filled into the structure (30) through the upper film (40), for example, by removing at least a portion of the upper film (40). Alternatively, the seventh filler (44) is filled into the structure (30), for example, through a mask. The seventh filler (44) fills the structure (30) from the top to the bottom along the opening created in FIG. 15. The seventh filler (44) filled from the top to the bottom of the opening is etch-backed through a trim process. In this way, the seventh filler (44) covers all or part of the gate electrode. At this time, the seventh filler (44) is, for example, nitride, but the seventh filler (44) is not limited thereto and includes any material having an etching selectivity ratio with the insulating layer (11) or the eighth filler (45). The space in which the seventh filler (44) is filled provides a space in which wordline wiring is formed in a subsequent process.

[0137] Meanwhile, as described above, the eighth filler (45) is filled into the empty space (38') of the structure (30). At this time, the eighth filler (45) is, for example, SiO2 and includes, for example, a material identical or similar to the insulating layer (11).

[0139] FIG. 17 is a plan view and perspective view illustrating s104 described in FIG. 2.

[0140] As described in s104 of FIG. 2, the method for manufacturing a memory element (100) according to the embodiments includes the step (s104) of performing bit line filling (BL fill) and / or word line filling (WL fill). FIG. 17 describes a method for performing word line filling following the processes performed in FIG. 16. FIG. 17 (a) is a plan view of a structure, and FIG. 17 (b) is a perspective view of a structure.

[0141] A method for manufacturing a memory device (100) according to the embodiments includes a step of removing an upper film (40) to perform word line filling. Additionally, the manufacturing method includes a step of removing a seventh filler (44) after removing the upper film (40). For example, the seventh filler is removed through wet etching. For example, the seventh filler (44) is removed through phosphoric acid, etc.

[0142] Additionally, the manufacturing method of the memory device (100) according to the embodiments forms a word line wiring (46) in the space (44') from which the seventh filler has been removed. The word line wiring (46) is formed in the space (44') from which the seventh filler has been removed through a deposition process, for example, CVD, ALD, etc. The word line wiring (46) includes a metal, for example, W, Mo, Ru, etc. Through this, the embodiments provide a method for forming the word line wiring (46). Additionally, the word line wiring (46) may further include TiN. Through this, the embodiments provide a method for controlling the work function of the word line wiring (46).

[0144] Through FIGS. 1 to 17, a method for manufacturing a memory device (100) having a three-dimensional stacked structure and the structure thereof have been described. Through such a method, the embodiments implement a 3D DRAM architecture. In addition, the embodiments provide a general-purpose structure and / or process applicable to various channels.

[0146] Although representative embodiments of the present invention have been described in detail above, those skilled in the art will understand that various modifications can be made to the above-described embodiments without departing from the scope of the present invention. Therefore, the scope of the present invention should not be limited to the described embodiments, but should be defined by the claims set forth below as well as equivalents thereof. Explanation of the symbols

[0148] 10: Mold 20: Beatline Stairs 30: Structure 100: Memory element

Claims

Claim 1 delete Claim 2 delete Claim 3 delete Claim 4 delete Claim 5 delete Claim 6 A method for manufacturing a memory device comprising: a step of forming a bitline step from a mold located on a substrate; a step of forming one or more first holes in a direction perpendicular to the substrate; a step of forming a support member that supports the bitline step by filling the first hole with a first filler material; and a step of forming a structure by performing etching on at least a portion of the bitline step on which the support member is formed; wherein the step of forming a structure by performing etching on at least a portion of the bitline step on which the support member is formed comprises: a step of forming a second hole on the bitline step in a direction perpendicular to the substrate; and a step of forming a first word line by filling the second hole with a second filler material; wherein the second hole is formed in a 'C' shape on the upper surface of the bitline step, such that one side is closed and the other side facing the one side is open, and the thickness of the closed side is greater than or equal to a predetermined thickness. Claim 7 A method for manufacturing a memory device according to claim 6, wherein the step of forming a bitline step from the mold comprises: a step of forming a mold by stacking a plurality of bitlines; and a step of forming the bitline step by removing at least a portion of the mold in a step shape, wherein each of the plurality of bitlines comprises one or more insulating layers and one or more active layers. Claim 8 delete Claim 9 A method for manufacturing a memory device according to claim 7, wherein, in the case where there are multiple first holes, the spacing between the multiple first holes is formed in proportion to the thickness of the insulating layer. Claim 10 delete Claim 11 delete Claim 12 delete Claim 13 In claim 6, the method for manufacturing the memory device comprises: a step of performing channel filling on the structure; a step of etching at least a portion of the portion where the channel filling is performed until the first word line formed in the structure is exposed; and a step of filling a second word line in the structure where the at least portion is etched; wherein the second word line is formed by replacing a portion of the filled channel, and the filled channel is formed by replacing a portion of the bit line step formed as a frame structure of the memory device. Claim 14 delete

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